2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant_32bit
= 1 << 1,
65 /* label_{abs,neg,mul,omod2,omod4,omod5,clamp} are used for both 16 and
66 * 32-bit operations but this shouldn't cause any issues because we don't
67 * look through any conversions */
72 label_literal
= 1 << 6,
76 label_omod5
= 1 << 10,
77 label_omod_success
= 1 << 11,
78 label_clamp
= 1 << 12,
79 label_clamp_success
= 1 << 13,
80 label_undefined
= 1 << 14,
83 label_add_sub
= 1 << 17,
84 label_bitwise
= 1 << 18,
85 label_minmax
= 1 << 19,
87 label_uniform_bool
= 1 << 21,
88 label_constant_64bit
= 1 << 22,
89 label_uniform_bitwise
= 1 << 23,
90 label_scc_invert
= 1 << 24,
91 label_vcc_hint
= 1 << 25,
92 label_scc_needed
= 1 << 26,
94 label_constant_16bit
= 1 << 29,
97 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
|
98 label_add_sub
| label_bitwise
| label_uniform_bitwise
| label_minmax
| label_fcmp
;
99 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
|
100 label_omod2
| label_omod4
| label_omod5
| label_clamp
| label_scc_invert
| label_b2i
;
101 static constexpr uint32_t val_labels
= label_constant_32bit
| label_constant_64bit
| label_constant_16bit
| label_literal
| label_mad
;
111 ssa_info() : label(0) {}
113 void add_label(Label new_label
)
115 /* Since all labels which use "instr" use it for the same thing
116 * (indicating the defining instruction), there is no need to clear
117 * any other instr labels. */
118 if (new_label
& instr_labels
)
119 label
&= ~temp_labels
; /* instr and temp alias */
121 if (new_label
& temp_labels
) {
122 label
&= ~temp_labels
;
123 label
&= ~instr_labels
; /* instr and temp alias */
126 uint32_t const_labels
= label_literal
| label_constant_32bit
| label_constant_64bit
| label_constant_16bit
;
127 if (new_label
& const_labels
)
128 label
&= ~val_labels
| const_labels
;
129 else if (new_label
& val_labels
)
130 label
&= ~val_labels
;
135 void set_vec(Instruction
* vec
)
137 add_label(label_vec
);
143 return label
& label_vec
;
146 void set_constant(chip_class chip
, uint64_t constant
)
148 Operand
op16((uint16_t)constant
);
149 Operand
op32((uint32_t)constant
);
150 add_label(label_literal
);
153 if (chip
>= GFX8
&& !op16
.isLiteral())
154 add_label(label_constant_16bit
);
156 if (!op32
.isLiteral() || ((uint32_t)constant
== 0x3e22f983 && chip
>= GFX8
))
157 add_label(label_constant_32bit
);
159 if (constant
<= 64) {
160 add_label(label_constant_64bit
);
161 } else if (constant
>= 0xFFFFFFFFFFFFFFF0) { /* [-16 .. -1] */
162 add_label(label_constant_64bit
);
163 } else if (constant
== 0x3FE0000000000000) { /* 0.5 */
164 add_label(label_constant_64bit
);
165 } else if (constant
== 0xBFE0000000000000) { /* -0.5 */
166 add_label(label_constant_64bit
);
167 } else if (constant
== 0x3FF0000000000000) { /* 1.0 */
168 add_label(label_constant_64bit
);
169 } else if (constant
== 0xBFF0000000000000) { /* -1.0 */
170 add_label(label_constant_64bit
);
171 } else if (constant
== 0x4000000000000000) { /* 2.0 */
172 add_label(label_constant_64bit
);
173 } else if (constant
== 0xC000000000000000) { /* -2.0 */
174 add_label(label_constant_64bit
);
175 } else if (constant
== 0x4010000000000000) { /* 4.0 */
176 add_label(label_constant_64bit
);
177 } else if (constant
== 0xC010000000000000) { /* -4.0 */
178 add_label(label_constant_64bit
);
181 if (label
& label_constant_64bit
) {
182 val
= Operand(constant
).constantValue();
184 label
&= ~(label_literal
| label_constant_16bit
| label_constant_32bit
);
188 bool is_constant(unsigned bits
)
192 return label
& label_literal
;
194 return label
& label_constant_16bit
;
196 return label
& label_constant_32bit
;
198 return label
& label_constant_64bit
;
203 bool is_literal(unsigned bits
)
205 bool is_lit
= label
& label_literal
;
210 return is_lit
&& ~(label
& label_constant_16bit
);
212 return is_lit
&& ~(label
& label_constant_32bit
);
219 bool is_constant_or_literal(unsigned bits
)
222 return label
& label_constant_64bit
;
224 return label
& label_literal
;
227 void set_abs(Temp abs_temp
)
229 add_label(label_abs
);
235 return label
& label_abs
;
238 void set_neg(Temp neg_temp
)
240 add_label(label_neg
);
246 return label
& label_neg
;
249 void set_neg_abs(Temp neg_abs_temp
)
251 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
255 void set_mul(Instruction
* mul
)
257 add_label(label_mul
);
263 return label
& label_mul
;
266 void set_temp(Temp tmp
)
268 add_label(label_temp
);
274 return label
& label_temp
;
277 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
279 add_label(label_mad
);
286 return label
& label_mad
;
289 void set_omod2(Temp def
)
291 add_label(label_omod2
);
297 return label
& label_omod2
;
300 void set_omod4(Temp def
)
302 add_label(label_omod4
);
308 return label
& label_omod4
;
311 void set_omod5(Temp def
)
313 add_label(label_omod5
);
319 return label
& label_omod5
;
322 void set_omod_success(Instruction
* omod_instr
)
324 add_label(label_omod_success
);
328 bool is_omod_success()
330 return label
& label_omod_success
;
333 void set_clamp(Temp def
)
335 add_label(label_clamp
);
341 return label
& label_clamp
;
344 void set_clamp_success(Instruction
* clamp_instr
)
346 add_label(label_clamp_success
);
350 bool is_clamp_success()
352 return label
& label_clamp_success
;
357 add_label(label_undefined
);
362 return label
& label_undefined
;
365 void set_vcc(Temp vcc
)
367 add_label(label_vcc
);
373 return label
& label_vcc
;
376 void set_b2f(Temp val
)
378 add_label(label_b2f
);
384 return label
& label_b2f
;
387 void set_add_sub(Instruction
*add_sub_instr
)
389 add_label(label_add_sub
);
390 instr
= add_sub_instr
;
395 return label
& label_add_sub
;
398 void set_bitwise(Instruction
*bitwise_instr
)
400 add_label(label_bitwise
);
401 instr
= bitwise_instr
;
406 return label
& label_bitwise
;
409 void set_uniform_bitwise()
411 add_label(label_uniform_bitwise
);
414 bool is_uniform_bitwise()
416 return label
& label_uniform_bitwise
;
419 void set_minmax(Instruction
*minmax_instr
)
421 add_label(label_minmax
);
422 instr
= minmax_instr
;
427 return label
& label_minmax
;
430 void set_fcmp(Instruction
*fcmp_instr
)
432 add_label(label_fcmp
);
438 return label
& label_fcmp
;
441 void set_scc_needed()
443 add_label(label_scc_needed
);
448 return label
& label_scc_needed
;
451 void set_scc_invert(Temp scc_inv
)
453 add_label(label_scc_invert
);
459 return label
& label_scc_invert
;
462 void set_uniform_bool(Temp uniform_bool
)
464 add_label(label_uniform_bool
);
468 bool is_uniform_bool()
470 return label
& label_uniform_bool
;
475 add_label(label_vcc_hint
);
480 return label
& label_vcc_hint
;
483 void set_b2i(Temp val
)
485 add_label(label_b2i
);
491 return label
& label_b2i
;
498 std::vector
<aco_ptr
<Instruction
>> instructions
;
500 std::pair
<uint32_t,Temp
> last_literal
;
501 std::vector
<mad_info
> mad_infos
;
502 std::vector
<uint16_t> uses
;
505 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
507 if (instr
->operands
[0].isConstant() ||
508 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
511 switch (instr
->opcode
) {
512 case aco_opcode::v_add_f32
:
513 case aco_opcode::v_mul_f32
:
514 case aco_opcode::v_or_b32
:
515 case aco_opcode::v_and_b32
:
516 case aco_opcode::v_xor_b32
:
517 case aco_opcode::v_max_f32
:
518 case aco_opcode::v_min_f32
:
519 case aco_opcode::v_max_i32
:
520 case aco_opcode::v_min_i32
:
521 case aco_opcode::v_max_u32
:
522 case aco_opcode::v_min_u32
:
523 case aco_opcode::v_cmp_eq_f32
:
524 case aco_opcode::v_cmp_lg_f32
:
526 case aco_opcode::v_sub_f32
:
527 instr
->opcode
= aco_opcode::v_subrev_f32
;
529 case aco_opcode::v_cmp_lt_f32
:
530 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
532 case aco_opcode::v_cmp_ge_f32
:
533 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
535 case aco_opcode::v_cmp_lt_i32
:
536 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
543 bool can_use_VOP3(opt_ctx
& ctx
, const aco_ptr
<Instruction
>& instr
)
548 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
551 if (instr
->isDPP() || instr
->isSDWA())
554 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
555 instr
->opcode
!= aco_opcode::v_madak_f32
&&
556 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
557 instr
->opcode
!= aco_opcode::v_madak_f16
&&
558 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
559 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
560 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
561 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
562 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
563 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
564 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
567 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
569 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
570 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
571 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
572 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
573 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
576 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
581 aco_ptr
<Instruction
> tmp
= std::move(instr
);
582 Format format
= asVOP3(tmp
->format
);
583 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
584 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
585 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
586 instr
->definitions
[i
] = tmp
->definitions
[i
];
587 if (instr
->definitions
[i
].isTemp()) {
588 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
589 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
590 info
.instr
= instr
.get();
595 /* only covers special cases */
596 bool alu_can_accept_constant(aco_opcode opcode
, unsigned operand
)
599 case aco_opcode::v_interp_p2_f32
:
600 case aco_opcode::v_mac_f32
:
601 case aco_opcode::v_writelane_b32
:
602 case aco_opcode::v_writelane_b32_e64
:
603 case aco_opcode::v_cndmask_b32
:
605 case aco_opcode::s_addk_i32
:
606 case aco_opcode::s_mulk_i32
:
607 case aco_opcode::p_wqm
:
608 case aco_opcode::p_extract_vector
:
609 case aco_opcode::p_split_vector
:
610 case aco_opcode::v_readlane_b32
:
611 case aco_opcode::v_readlane_b32_e64
:
612 case aco_opcode::v_readfirstlane_b32
:
619 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
621 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
622 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
627 /* check constant bus and literal limitations */
628 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
630 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
631 Operand
literal32(s1
);
632 Operand
literal64(s2
);
633 unsigned num_sgprs
= 0;
634 unsigned sgpr
[] = {0, 0};
636 for (unsigned i
= 0; i
< num_operands
; i
++) {
637 Operand op
= operands
[i
];
639 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
640 /* two reads of the same SGPR count as 1 to the limit */
641 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
643 sgpr
[num_sgprs
++] = op
.tempId();
648 } else if (op
.isLiteral()) {
649 if (ctx
.program
->chip_class
< GFX10
)
652 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
654 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
657 /* Any number of 32-bit literals counts as only 1 to the limit. Same
658 * (but separately) for 64-bit literals. */
659 if (op
.size() == 1 && literal32
.isUndefined()) {
662 } else if (op
.size() == 2 && literal64
.isUndefined()) {
675 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
677 Operand op
= instr
->operands
[op_index
];
681 Temp tmp
= op
.getTemp();
682 if (!ctx
.info
[tmp
.id()].is_add_sub())
685 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
687 switch (add_instr
->opcode
) {
688 case aco_opcode::v_add_u32
:
689 case aco_opcode::v_add_co_u32
:
690 case aco_opcode::v_add_co_u32_e64
:
691 case aco_opcode::s_add_i32
:
692 case aco_opcode::s_add_u32
:
698 if (add_instr
->usesModifiers())
701 for (unsigned i
= 0; i
< 2; i
++) {
702 if (add_instr
->operands
[i
].isConstant()) {
703 *offset
= add_instr
->operands
[i
].constantValue();
704 } else if (add_instr
->operands
[i
].isTemp() &&
705 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal(32)) {
706 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
710 if (!add_instr
->operands
[!i
].isTemp())
713 uint32_t offset2
= 0;
714 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
717 *base
= add_instr
->operands
[!i
].getTemp();
725 unsigned get_operand_size(aco_ptr
<Instruction
>& instr
, unsigned index
)
727 if (instr
->format
== Format::PSEUDO
)
728 return instr
->operands
[index
].bytes() * 8u;
729 else if (instr
->opcode
== aco_opcode::v_mad_u64_u32
|| instr
->opcode
== aco_opcode::v_mad_i64_i32
)
730 return index
== 2 ? 64 : 32;
731 else if (instr
->isVALU() || instr
->isSALU())
732 return instr_info
.operand_size
[(int)instr
->opcode
];
737 Operand
get_constant_op(opt_ctx
&ctx
, ssa_info info
, uint32_t bits
)
740 return Operand((uint8_t)info
.val
);
742 return Operand((uint16_t)info
.val
);
743 // TODO: this functions shouldn't be needed if we store Operand instead of value.
744 Operand
op(info
.val
, bits
== 64);
745 if (info
.is_literal(32) && info
.val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
746 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
750 bool fixed_to_exec(Operand op
)
752 return op
.isFixed() && op
.physReg() == exec
;
755 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
757 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
758 ASSERTED
bool all_const
= false;
759 for (Operand
& op
: instr
->operands
)
760 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal(32));
761 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
764 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
766 if (!instr
->operands
[i
].isTemp())
769 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
770 /* propagate undef */
771 if (info
.is_undefined() && is_phi(instr
))
772 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
773 /* propagate reg->reg of same type */
774 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
775 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
776 info
= ctx
.info
[info
.temp
.id()];
779 /* SALU / PSEUDO: propagate inline constants */
780 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
781 bool is_subdword
= false;
782 // TODO: optimize SGPR propagation for subdword pseudo instructions on gfx9+
783 if (instr
->format
== Format::PSEUDO
) {
784 is_subdword
= std::any_of(instr
->definitions
.begin(), instr
->definitions
.end(),
785 [] (const Definition
& def
) { return def
.regClass().is_subdword();});
786 is_subdword
= is_subdword
|| std::any_of(instr
->operands
.begin(), instr
->operands
.end(),
787 [] (const Operand
& op
) { return op
.hasRegClass() && op
.regClass().is_subdword();});
788 if (is_subdword
&& ctx
.program
->chip_class
< GFX9
)
792 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
793 instr
->operands
[i
].setTemp(info
.temp
);
794 info
= ctx
.info
[info
.temp
.id()];
795 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
796 /* propagate vgpr if it can take it */
797 switch (instr
->opcode
) {
798 case aco_opcode::p_create_vector
:
799 case aco_opcode::p_split_vector
:
800 case aco_opcode::p_extract_vector
:
801 case aco_opcode::p_phi
: {
802 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
803 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
805 instr
->operands
[i
] = Operand(info
.temp
);
806 info
= ctx
.info
[info
.temp
.id()];
814 unsigned bits
= get_operand_size(instr
, i
);
815 if ((info
.is_constant(bits
) || (!is_subdword
&& info
.is_literal(bits
) && instr
->format
== Format::PSEUDO
)) &&
816 !instr
->operands
[i
].isFixed() && alu_can_accept_constant(instr
->opcode
, i
)) {
817 instr
->operands
[i
] = get_constant_op(ctx
, info
, bits
);
822 /* VALU: propagate neg, abs & inline constants */
823 else if (instr
->isVALU()) {
824 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
825 instr
->operands
[i
].setTemp(info
.temp
);
826 info
= ctx
.info
[info
.temp
.id()];
829 /* for instructions other than v_cndmask_b32, the size of the instruction should match the operand size */
830 unsigned can_use_mod
= instr
->opcode
!= aco_opcode::v_cndmask_b32
|| instr
->operands
[i
].getTemp().bytes() == 4;
831 can_use_mod
= can_use_mod
&& instr_info
.can_use_input_modifiers
[(int)instr
->opcode
];
833 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && can_use_mod
) {
836 instr
->operands
[i
] = Operand(info
.temp
);
838 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
840 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
842 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
843 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
844 instr
->operands
[i
].setTemp(info
.temp
);
846 } else if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f16
) {
847 instr
->opcode
= i
? aco_opcode::v_sub_f16
: aco_opcode::v_subrev_f16
;
848 instr
->operands
[i
].setTemp(info
.temp
);
850 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && can_use_mod
) {
853 instr
->operands
[i
].setTemp(info
.temp
);
855 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
857 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
860 unsigned bits
= get_operand_size(instr
, i
);
861 if (info
.is_constant(bits
) && alu_can_accept_constant(instr
->opcode
, i
)) {
862 Operand op
= get_constant_op(ctx
, info
, bits
);
863 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
864 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
865 instr
->operands
[i
] = op
;
867 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
868 instr
->operands
[i
] = instr
->operands
[0];
869 instr
->operands
[0] = op
;
871 } else if (can_use_VOP3(ctx
, instr
)) {
873 instr
->operands
[i
] = op
;
879 /* MUBUF: propagate constants and combine additions */
880 else if (instr
->format
== Format::MUBUF
) {
881 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
884 while (info
.is_temp())
885 info
= ctx
.info
[info
.temp
.id()];
887 if (mubuf
->offen
&& i
== 1 && info
.is_constant_or_literal(32) && mubuf
->offset
+ info
.val
< 4096) {
888 assert(!mubuf
->idxen
);
889 instr
->operands
[1] = Operand(v1
);
890 mubuf
->offset
+= info
.val
;
891 mubuf
->offen
= false;
893 } else if (i
== 2 && info
.is_constant_or_literal(32) && mubuf
->offset
+ info
.val
< 4096) {
894 instr
->operands
[2] = Operand((uint32_t) 0);
895 mubuf
->offset
+= info
.val
;
897 } else if (mubuf
->offen
&& i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
898 assert(!mubuf
->idxen
);
899 instr
->operands
[1].setTemp(base
);
900 mubuf
->offset
+= offset
;
902 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
903 instr
->operands
[i
].setTemp(base
);
904 mubuf
->offset
+= offset
;
909 /* DS: combine additions */
910 else if (instr
->format
== Format::DS
) {
912 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
915 bool has_usable_ds_offset
= ctx
.program
->chip_class
>= GFX7
;
916 if (has_usable_ds_offset
&&
917 i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) &&
918 base
.regClass() == instr
->operands
[i
].regClass() &&
919 instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
920 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
921 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
922 unsigned mask
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 0x7 : 0x3;
923 unsigned shifts
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 3 : 2;
925 if ((offset
& mask
) == 0 &&
926 ds
->offset0
+ (offset
>> shifts
) <= 255 &&
927 ds
->offset1
+ (offset
>> shifts
) <= 255) {
928 instr
->operands
[i
].setTemp(base
);
929 ds
->offset0
+= offset
>> shifts
;
930 ds
->offset1
+= offset
>> shifts
;
933 if (ds
->offset0
+ offset
<= 65535) {
934 instr
->operands
[i
].setTemp(base
);
935 ds
->offset0
+= offset
;
941 /* SMEM: propagate constants and combine additions */
942 else if (instr
->format
== Format::SMEM
) {
944 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
947 if (i
== 1 && info
.is_constant_or_literal(32) &&
948 ((ctx
.program
->chip_class
== GFX6
&& info
.val
<= 0x3FF) ||
949 (ctx
.program
->chip_class
== GFX7
&& info
.val
<= 0xFFFFFFFF) ||
950 (ctx
.program
->chip_class
>= GFX8
&& info
.val
<= 0xFFFFF))) {
951 instr
->operands
[i
] = Operand(info
.val
);
953 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
954 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
956 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal(32) ||
957 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
961 smem
->operands
[1] = Operand(offset
);
962 smem
->operands
.back() = Operand(base
);
964 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
965 new_instr
->operands
[0] = smem
->operands
[0];
966 new_instr
->operands
[1] = Operand(offset
);
967 if (smem
->definitions
.empty())
968 new_instr
->operands
[2] = smem
->operands
[2];
969 new_instr
->operands
.back() = Operand(base
);
970 if (!smem
->definitions
.empty())
971 new_instr
->definitions
[0] = smem
->definitions
[0];
972 new_instr
->can_reorder
= smem
->can_reorder
;
973 new_instr
->barrier
= smem
->barrier
;
974 new_instr
->glc
= smem
->glc
;
975 new_instr
->dlc
= smem
->dlc
;
976 new_instr
->nv
= smem
->nv
;
977 new_instr
->disable_wqm
= smem
->disable_wqm
;
978 instr
.reset(new_instr
);
979 smem
= static_cast<SMEM_instruction
*>(instr
.get());
985 else if (instr
->format
== Format::PSEUDO_BRANCH
) {
986 if (ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
987 /* Flip the branch instruction to get rid of the scc_invert instruction */
988 instr
->opcode
= instr
->opcode
== aco_opcode::p_cbranch_z
? aco_opcode::p_cbranch_nz
: aco_opcode::p_cbranch_z
;
989 instr
->operands
[0].setTemp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
994 /* if this instruction doesn't define anything, return */
995 if (instr
->definitions
.empty())
998 switch (instr
->opcode
) {
999 case aco_opcode::p_create_vector
: {
1000 bool copy_prop
= instr
->operands
.size() == 1 && instr
->operands
[0].isTemp() &&
1001 instr
->operands
[0].regClass() == instr
->definitions
[0].regClass();
1003 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1007 unsigned num_ops
= instr
->operands
.size();
1008 for (const Operand
& op
: instr
->operands
) {
1009 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
1010 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
1012 if (num_ops
!= instr
->operands
.size()) {
1013 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
1014 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
1015 instr
->definitions
[0] = old_vec
->definitions
[0];
1017 for (Operand
& old_op
: old_vec
->operands
) {
1018 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
1019 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
1020 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
1021 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
1022 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
1023 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
1024 instr
->operands
[k
++] = op
;
1027 instr
->operands
[k
++] = old_op
;
1030 assert(k
== num_ops
);
1033 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
1036 case aco_opcode::p_split_vector
: {
1037 ssa_info
& info
= ctx
.info
[instr
->operands
[0].tempId()];
1039 if (info
.is_constant_or_literal(32)) {
1040 uint32_t val
= info
.val
;
1041 for (Definition def
: instr
->definitions
) {
1042 uint32_t mask
= u_bit_consecutive(0, def
.bytes() * 8u);
1043 ctx
.info
[def
.tempId()].set_constant(ctx
.program
->chip_class
, val
& mask
);
1044 val
>>= def
.bytes() * 8u;
1047 } else if (!info
.is_vec()) {
1051 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
1052 unsigned split_offset
= 0;
1053 unsigned vec_offset
= 0;
1054 unsigned vec_index
= 0;
1055 for (unsigned i
= 0; i
< instr
->definitions
.size(); split_offset
+= instr
->definitions
[i
++].bytes()) {
1056 while (vec_offset
< split_offset
&& vec_index
< vec
->operands
.size())
1057 vec_offset
+= vec
->operands
[vec_index
++].bytes();
1059 if (vec_offset
!= split_offset
|| vec
->operands
[vec_index
].bytes() != instr
->definitions
[i
].bytes())
1062 Operand vec_op
= vec
->operands
[vec_index
];
1063 if (vec_op
.isConstant()) {
1064 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(ctx
.program
->chip_class
, vec_op
.constantValue64());
1065 } else if (vec_op
.isUndefined()) {
1066 ctx
.info
[instr
->definitions
[i
].tempId()].set_undefined();
1068 assert(vec_op
.isTemp());
1069 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
1074 case aco_opcode::p_extract_vector
: { /* mov */
1075 ssa_info
& info
= ctx
.info
[instr
->operands
[0].tempId()];
1076 const unsigned index
= instr
->operands
[1].constantValue();
1077 const unsigned dst_offset
= index
* instr
->definitions
[0].bytes();
1079 if (info
.is_constant_or_literal(32)) {
1080 uint32_t mask
= u_bit_consecutive(0, instr
->definitions
[0].bytes() * 8u);
1081 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, (info
.val
>> (dst_offset
* 8u)) & mask
);
1083 } else if (!info
.is_vec()) {
1087 /* check if we index directly into a vector element */
1088 Instruction
* vec
= info
.instr
;
1089 unsigned offset
= 0;
1091 for (const Operand
& op
: vec
->operands
) {
1092 if (offset
< dst_offset
) {
1093 offset
+= op
.bytes();
1095 } else if (offset
!= dst_offset
|| op
.bytes() != instr
->definitions
[0].bytes()) {
1099 /* convert this extract into a copy instruction */
1100 instr
->opcode
= aco_opcode::p_parallelcopy
;
1101 instr
->operands
.pop_back();
1102 instr
->operands
[0] = op
;
1104 if (op
.isConstant()) {
1105 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, op
.constantValue64());
1106 } else if (op
.isUndefined()) {
1107 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1109 assert(op
.isTemp());
1110 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(op
.getTemp());
1116 case aco_opcode::s_mov_b32
: /* propagate */
1117 case aco_opcode::s_mov_b64
:
1118 case aco_opcode::v_mov_b32
:
1119 case aco_opcode::p_as_uniform
:
1120 if (instr
->definitions
[0].isFixed()) {
1121 /* don't copy-propagate copies into fixed registers */
1122 } else if (instr
->usesModifiers()) {
1124 } else if (instr
->operands
[0].isConstant()) {
1125 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, instr
->operands
[0].constantValue64());
1126 } else if (instr
->operands
[0].isTemp()) {
1127 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1129 assert(instr
->operands
[0].isFixed());
1132 case aco_opcode::p_is_helper
:
1133 if (!ctx
.program
->needs_wqm
)
1134 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, 0u);
1136 case aco_opcode::s_movk_i32
: {
1137 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
1138 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
1139 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1142 case aco_opcode::v_bfrev_b32
:
1143 case aco_opcode::s_brev_b32
: {
1144 if (instr
->operands
[0].isConstant()) {
1145 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
1146 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1150 case aco_opcode::s_bfm_b32
: {
1151 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
1152 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
1153 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
1154 uint32_t v
= ((1u << size
) - 1u) << start
;
1155 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1159 case aco_opcode::v_mul_f16
:
1160 case aco_opcode::v_mul_f32
: { /* omod */
1161 /* TODO: try to move the negate/abs modifier to the consumer instead */
1162 if (instr
->usesModifiers())
1165 bool fp16
= instr
->opcode
== aco_opcode::v_mul_f16
;
1167 for (unsigned i
= 0; i
< 2; i
++) {
1168 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
1169 if (instr
->operands
[!i
].constantValue() == (fp16
? 0x4000 : 0x40000000)) { /* 2.0 */
1170 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
1171 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0x4400 : 0x40800000)) { /* 4.0 */
1172 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
1173 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0xb800 : 0x3f000000)) { /* 0.5 */
1174 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
1175 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0x3c00 : 0x3f800000) &&
1176 !(fp16
? block
.fp_mode
.must_flush_denorms16_64
: block
.fp_mode
.must_flush_denorms32
)) { /* 1.0 */
1177 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
1186 case aco_opcode::v_and_b32
: { /* abs */
1187 if (!instr
->usesModifiers() && instr
->operands
[1].isTemp() &&
1188 instr
->operands
[1].getTemp().type() == RegType::vgpr
&&
1189 ((instr
->definitions
[0].bytes() == 4 && instr
->operands
[0].constantEquals(0x7FFFFFFFu
)) ||
1190 (instr
->definitions
[0].bytes() == 2 && instr
->operands
[0].constantEquals(0x7FFFu
))))
1191 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
1193 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1196 case aco_opcode::v_xor_b32
: { /* neg */
1197 if (!instr
->usesModifiers() && instr
->operands
[1].isTemp() &&
1198 ((instr
->definitions
[0].bytes() == 4 && instr
->operands
[0].constantEquals(0x80000000u
)) ||
1199 (instr
->definitions
[0].bytes() == 2 && instr
->operands
[0].constantEquals(0x8000u
)))) {
1200 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
1201 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1202 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
1203 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
1204 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1205 instr
->opcode
= aco_opcode::v_or_b32
;
1206 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
1208 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
1212 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1216 case aco_opcode::v_med3_f16
:
1217 case aco_opcode::v_med3_f32
: { /* clamp */
1218 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1219 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1220 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1221 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1225 bool found_zero
= false, found_one
= false;
1226 bool is_fp16
= instr
->opcode
== aco_opcode::v_med3_f16
;
1227 for (unsigned i
= 0; i
< 3; i
++)
1229 if (instr
->operands
[i
].constantEquals(0))
1231 else if (instr
->operands
[i
].constantEquals(is_fp16
? 0x3c00 : 0x3f800000)) /* 1.0 */
1236 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1237 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1241 case aco_opcode::v_cndmask_b32
:
1242 if (instr
->operands
[0].constantEquals(0) &&
1243 instr
->operands
[1].constantEquals(0xFFFFFFFF))
1244 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1245 else if (instr
->operands
[0].constantEquals(0) &&
1246 instr
->operands
[1].constantEquals(0x3f800000u
))
1247 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1248 else if (instr
->operands
[0].constantEquals(0) &&
1249 instr
->operands
[1].constantEquals(1))
1250 ctx
.info
[instr
->definitions
[0].tempId()].set_b2i(instr
->operands
[2].getTemp());
1252 ctx
.info
[instr
->operands
[2].tempId()].set_vcc_hint();
1254 case aco_opcode::v_cmp_lg_u32
:
1255 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1256 instr
->operands
[0].constantEquals(0) &&
1257 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1258 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1260 case aco_opcode::p_phi
:
1261 case aco_opcode::p_linear_phi
: {
1262 /* lower_bool_phis() can create phis like this */
1263 bool all_same_temp
= instr
->operands
[0].isTemp();
1264 /* this check is needed when moving uniform loop counters out of a divergent loop */
1266 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1267 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1268 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1269 all_same_temp
= false;
1271 if (all_same_temp
) {
1272 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1274 bool all_undef
= instr
->operands
[0].isUndefined();
1275 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1276 if (!instr
->operands
[i
].isUndefined())
1280 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1284 case aco_opcode::v_add_u32
:
1285 case aco_opcode::v_add_co_u32
:
1286 case aco_opcode::v_add_co_u32_e64
:
1287 case aco_opcode::s_add_i32
:
1288 case aco_opcode::s_add_u32
:
1289 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1291 case aco_opcode::s_not_b32
:
1292 case aco_opcode::s_not_b64
:
1293 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1294 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1295 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1296 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1297 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1298 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1300 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1302 case aco_opcode::s_and_b32
:
1303 case aco_opcode::s_and_b64
:
1304 if (fixed_to_exec(instr
->operands
[1]) && instr
->operands
[0].isTemp()) {
1305 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1306 /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
1307 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1308 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1310 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1311 /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
1312 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1313 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1318 case aco_opcode::s_or_b32
:
1319 case aco_opcode::s_or_b64
:
1320 case aco_opcode::s_xor_b32
:
1321 case aco_opcode::s_xor_b64
:
1322 if (std::all_of(instr
->operands
.begin(), instr
->operands
.end(), [&ctx
](const Operand
& op
) {
1323 return op
.isTemp() && (ctx
.info
[op
.tempId()].is_uniform_bool() || ctx
.info
[op
.tempId()].is_uniform_bitwise());
1325 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1328 case aco_opcode::s_lshl_b32
:
1329 case aco_opcode::v_or_b32
:
1330 case aco_opcode::v_lshlrev_b32
:
1331 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1333 case aco_opcode::v_min_f32
:
1334 case aco_opcode::v_min_f16
:
1335 case aco_opcode::v_min_u32
:
1336 case aco_opcode::v_min_i32
:
1337 case aco_opcode::v_min_u16
:
1338 case aco_opcode::v_min_i16
:
1339 case aco_opcode::v_max_f32
:
1340 case aco_opcode::v_max_f16
:
1341 case aco_opcode::v_max_u32
:
1342 case aco_opcode::v_max_i32
:
1343 case aco_opcode::v_max_u16
:
1344 case aco_opcode::v_max_i16
:
1345 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1347 case aco_opcode::v_cmp_lt_f32
:
1348 case aco_opcode::v_cmp_eq_f32
:
1349 case aco_opcode::v_cmp_le_f32
:
1350 case aco_opcode::v_cmp_gt_f32
:
1351 case aco_opcode::v_cmp_lg_f32
:
1352 case aco_opcode::v_cmp_ge_f32
:
1353 case aco_opcode::v_cmp_o_f32
:
1354 case aco_opcode::v_cmp_u_f32
:
1355 case aco_opcode::v_cmp_nge_f32
:
1356 case aco_opcode::v_cmp_nlg_f32
:
1357 case aco_opcode::v_cmp_ngt_f32
:
1358 case aco_opcode::v_cmp_nle_f32
:
1359 case aco_opcode::v_cmp_neq_f32
:
1360 case aco_opcode::v_cmp_nlt_f32
:
1361 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1363 case aco_opcode::s_cselect_b64
:
1364 case aco_opcode::s_cselect_b32
:
1365 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1366 instr
->operands
[1].constantEquals(0)) {
1367 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1368 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1370 if (instr
->operands
[2].isTemp() && ctx
.info
[instr
->operands
[2].tempId()].is_scc_invert()) {
1371 /* Flip the operands to get rid of the scc_invert instruction */
1372 std::swap(instr
->operands
[0], instr
->operands
[1]);
1373 instr
->operands
[2].setTemp(ctx
.info
[instr
->operands
[2].tempId()].temp
);
1376 case aco_opcode::p_wqm
:
1377 if (instr
->operands
[0].isTemp() &&
1378 ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1379 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1387 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1389 *ordered
= *unordered
= op
;
1391 #define CMP(ord, unord) \
1392 case aco_opcode::v_cmp_##ord##_f32:\
1393 case aco_opcode::v_cmp_n##unord##_f32:\
1394 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1395 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1396 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1410 aco_opcode
get_ordered(aco_opcode op
)
1412 aco_opcode ordered
, unordered
, inverse
;
1413 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::num_opcodes
;
1416 aco_opcode
get_unordered(aco_opcode op
)
1418 aco_opcode ordered
, unordered
, inverse
;
1419 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::num_opcodes
;
1422 aco_opcode
get_inverse(aco_opcode op
)
1424 aco_opcode ordered
, unordered
, inverse
;
1425 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::num_opcodes
;
1428 bool is_cmp(aco_opcode op
)
1430 aco_opcode ordered
, unordered
, inverse
;
1431 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1434 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1436 if (ctx
.info
[tmp
.id()].is_temp())
1437 return ctx
.info
[tmp
.id()].temp
.id();
1442 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1444 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1445 for (const Operand
& op
: instr
->operands
) {
1447 ctx
.uses
[op
.tempId()]--;
1452 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1454 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1456 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1459 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1461 if (instr
->definitions
.size() == 2) {
1462 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1463 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1470 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1471 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1472 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1474 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1476 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1479 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1481 bool neg
[2] = {false, false};
1482 bool abs
[2] = {false, false};
1484 Instruction
*op_instr
[2];
1487 for (unsigned i
= 0; i
< 2; i
++) {
1488 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1492 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1494 if (op_instr
[i
]->opcode
!= expected_cmp
)
1496 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1499 if (op_instr
[i
]->isVOP3()) {
1500 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1501 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1503 neg
[i
] = vop3
->neg
[0];
1504 abs
[i
] = vop3
->abs
[0];
1505 opsel
|= (vop3
->opsel
& 1) << i
;
1508 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1509 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1510 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1516 if (op
[1].type() == RegType::sgpr
)
1517 std::swap(op
[0], op
[1]);
1518 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1519 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1522 ctx
.uses
[op
[0].id()]++;
1523 ctx
.uses
[op
[1].id()]++;
1524 decrease_uses(ctx
, op_instr
[0]);
1525 decrease_uses(ctx
, op_instr
[1]);
1527 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1528 Instruction
*new_instr
;
1529 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1530 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1531 for (unsigned i
= 0; i
< 2; i
++) {
1532 vop3
->neg
[i
] = neg
[i
];
1533 vop3
->abs
[i
] = abs
[i
];
1535 vop3
->opsel
= opsel
;
1536 new_instr
= static_cast<Instruction
*>(vop3
);
1538 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1540 new_instr
->operands
[0] = Operand(op
[0]);
1541 new_instr
->operands
[1] = Operand(op
[1]);
1542 new_instr
->definitions
[0] = instr
->definitions
[0];
1544 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1545 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1547 instr
.reset(new_instr
);
1552 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1553 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1554 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1556 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1558 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1561 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1562 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1564 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1565 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1566 if (!nan_test
|| !cmp
)
1569 if (cmp
->opcode
== expected_nan_test
)
1570 std::swap(nan_test
, cmp
);
1571 else if (nan_test
->opcode
!= expected_nan_test
)
1574 if (!is_cmp(cmp
->opcode
))
1577 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1579 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1582 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1583 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1584 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1585 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1586 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1588 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1591 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1592 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1593 decrease_uses(ctx
, nan_test
);
1594 decrease_uses(ctx
, cmp
);
1596 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1597 Instruction
*new_instr
;
1598 if (cmp
->isVOP3()) {
1599 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1600 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1601 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1602 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1603 new_vop3
->clamp
= cmp_vop3
->clamp
;
1604 new_vop3
->omod
= cmp_vop3
->omod
;
1605 new_vop3
->opsel
= cmp_vop3
->opsel
;
1606 new_instr
= new_vop3
;
1608 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1610 new_instr
->operands
[0] = cmp
->operands
[0];
1611 new_instr
->operands
[1] = cmp
->operands
[1];
1612 new_instr
->definitions
[0] = instr
->definitions
[0];
1614 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1615 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1617 instr
.reset(new_instr
);
1622 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1623 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1624 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1626 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1628 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1631 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1633 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1634 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1636 if (!nan_test
|| !cmp
)
1639 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1640 if (cmp
->opcode
== expected_nan_test
)
1641 std::swap(nan_test
, cmp
);
1642 else if (nan_test
->opcode
!= expected_nan_test
)
1645 if (!is_cmp(cmp
->opcode
))
1648 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1650 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1653 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1654 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1655 if (prop_nan0
!= prop_nan1
)
1658 if (nan_test
->isVOP3()) {
1659 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1660 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1664 int constant_operand
= -1;
1665 for (unsigned i
= 0; i
< 2; i
++) {
1666 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1667 constant_operand
= !i
;
1671 if (constant_operand
== -1)
1675 if (cmp
->operands
[constant_operand
].isConstant()) {
1676 constant
= cmp
->operands
[constant_operand
].constantValue();
1677 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1678 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1679 unsigned id
= original_temp_id(ctx
, tmp
);
1680 if (!ctx
.info
[id
].is_constant_or_literal(32))
1682 constant
= ctx
.info
[id
].val
;
1688 memcpy(&constantf
, &constant
, 4);
1689 if (isnan(constantf
))
1692 if (cmp
->operands
[0].isTemp())
1693 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1694 if (cmp
->operands
[1].isTemp())
1695 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1696 decrease_uses(ctx
, nan_test
);
1697 decrease_uses(ctx
, cmp
);
1699 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1700 Instruction
*new_instr
;
1701 if (cmp
->isVOP3()) {
1702 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1703 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1704 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1705 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1706 new_vop3
->clamp
= cmp_vop3
->clamp
;
1707 new_vop3
->omod
= cmp_vop3
->omod
;
1708 new_vop3
->opsel
= cmp_vop3
->opsel
;
1709 new_instr
= new_vop3
;
1711 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1713 new_instr
->operands
[0] = cmp
->operands
[0];
1714 new_instr
->operands
[1] = cmp
->operands
[1];
1715 new_instr
->definitions
[0] = instr
->definitions
[0];
1717 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1718 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1720 instr
.reset(new_instr
);
1725 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1726 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1728 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1730 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1732 if (!instr
->operands
[0].isTemp())
1735 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1739 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1740 if (new_opcode
== aco_opcode::num_opcodes
)
1743 if (cmp
->operands
[0].isTemp())
1744 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1745 if (cmp
->operands
[1].isTemp())
1746 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1747 decrease_uses(ctx
, cmp
);
1749 Instruction
*new_instr
;
1750 if (cmp
->isVOP3()) {
1751 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1752 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1753 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1754 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1755 new_vop3
->clamp
= cmp_vop3
->clamp
;
1756 new_vop3
->omod
= cmp_vop3
->omod
;
1757 new_vop3
->opsel
= cmp_vop3
->opsel
;
1758 new_instr
= new_vop3
;
1760 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1762 new_instr
->operands
[0] = cmp
->operands
[0];
1763 new_instr
->operands
[1] = cmp
->operands
[1];
1764 new_instr
->definitions
[0] = instr
->definitions
[0];
1766 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1767 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1769 instr
.reset(new_instr
);
1774 /* op1(op2(1, 2), 0) if swap = false
1775 * op1(0, op2(1, 2)) if swap = true */
1776 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1777 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1778 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1779 bool *op1_clamp
, uint8_t *op1_omod
,
1780 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1783 if (op1_instr
->opcode
!= op1
)
1786 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1787 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1789 if (fixed_to_exec(op2_instr
->operands
[0]) || fixed_to_exec(op2_instr
->operands
[1]))
1792 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1793 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1795 /* don't support inbetween clamp/omod */
1796 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1799 /* get operands and modifiers and check inbetween modifiers */
1800 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1801 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1804 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1805 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1809 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1810 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1813 if (inbetween_opsel
)
1814 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1815 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1819 shuffle
[shuffle_str
[0] - '0'] = 0;
1820 shuffle
[shuffle_str
[1] - '0'] = 1;
1821 shuffle
[shuffle_str
[2] - '0'] = 2;
1823 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1824 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1825 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1826 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1827 *opsel
|= 1 << shuffle
[0];
1829 for (unsigned i
= 0; i
< 2; i
++) {
1830 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1831 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1832 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1833 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1834 *opsel
|= 1 << shuffle
[i
+ 1];
1837 /* check operands */
1838 if (!check_vop3_operands(ctx
, 3, operands
))
1844 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1845 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1846 bool clamp
, unsigned omod
)
1848 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1849 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1850 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1851 new_instr
->clamp
= clamp
;
1852 new_instr
->omod
= omod
;
1853 new_instr
->opsel
= opsel
;
1854 new_instr
->operands
[0] = operands
[0];
1855 new_instr
->operands
[1] = operands
[1];
1856 new_instr
->operands
[2] = operands
[2];
1857 new_instr
->definitions
[0] = instr
->definitions
[0];
1858 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1860 instr
.reset(new_instr
);
1863 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1865 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1866 (label_omod_success
| label_clamp_success
);
1868 for (unsigned swap
= 0; swap
< 2; swap
++) {
1869 if (!((1 << swap
) & ops
))
1872 Operand operands
[3];
1873 bool neg
[3], abs
[3], clamp
;
1874 uint8_t opsel
= 0, omod
= 0;
1875 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1876 instr
.get(), swap
, shuffle
,
1877 operands
, neg
, abs
, &opsel
,
1878 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1879 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1880 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1881 if (omod_clamp
& label_omod_success
)
1882 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1883 if (omod_clamp
& label_clamp_success
)
1884 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1891 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
1893 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
1896 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1897 (label_omod_success
| label_clamp_success
);
1899 /* min(-max(a, b), c) -> min3(-a, -b, c) *
1900 * max(-min(a, b), c) -> max3(-a, -b, c) */
1901 for (unsigned swap
= 0; swap
< 2; swap
++) {
1902 Operand operands
[3];
1903 bool neg
[3], abs
[3], clamp
;
1904 uint8_t opsel
= 0, omod
= 0;
1906 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
1907 instr
.get(), swap
, "012",
1908 operands
, neg
, abs
, &opsel
,
1909 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
1911 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1914 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1915 if (omod_clamp
& label_omod_success
)
1916 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1917 if (omod_clamp
& label_clamp_success
)
1918 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1925 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1926 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1927 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1928 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1929 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1930 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1931 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1934 if (!instr
->operands
[0].isTemp())
1936 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1939 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1942 switch (op2_instr
->opcode
) {
1943 case aco_opcode::s_and_b32
:
1944 case aco_opcode::s_or_b32
:
1945 case aco_opcode::s_xor_b32
:
1946 case aco_opcode::s_and_b64
:
1947 case aco_opcode::s_or_b64
:
1948 case aco_opcode::s_xor_b64
:
1954 /* create instruction */
1955 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1956 std::swap(instr
->definitions
[1], op2_instr
->definitions
[1]);
1957 ctx
.uses
[instr
->operands
[0].tempId()]--;
1958 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1960 switch (op2_instr
->opcode
) {
1961 case aco_opcode::s_and_b32
:
1962 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1964 case aco_opcode::s_or_b32
:
1965 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1967 case aco_opcode::s_xor_b32
:
1968 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1970 case aco_opcode::s_and_b64
:
1971 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1973 case aco_opcode::s_or_b64
:
1974 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1976 case aco_opcode::s_xor_b64
:
1977 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1986 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1987 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1988 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1989 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1990 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1992 if (instr
->definitions
[0].isTemp() && ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bool())
1995 for (unsigned i
= 0; i
< 2; i
++) {
1996 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1997 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1999 if (ctx
.uses
[op2_instr
->definitions
[1].tempId()] || fixed_to_exec(op2_instr
->operands
[0]))
2002 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
2003 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
2006 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2007 instr
->operands
[0] = instr
->operands
[!i
];
2008 instr
->operands
[1] = op2_instr
->operands
[0];
2009 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2011 switch (instr
->opcode
) {
2012 case aco_opcode::s_and_b32
:
2013 instr
->opcode
= aco_opcode::s_andn2_b32
;
2015 case aco_opcode::s_or_b32
:
2016 instr
->opcode
= aco_opcode::s_orn2_b32
;
2018 case aco_opcode::s_and_b64
:
2019 instr
->opcode
= aco_opcode::s_andn2_b64
;
2021 case aco_opcode::s_or_b64
:
2022 instr
->opcode
= aco_opcode::s_orn2_b64
;
2033 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
2034 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
2036 if (instr
->opcode
== aco_opcode::s_add_i32
&& ctx
.uses
[instr
->definitions
[1].tempId()])
2039 for (unsigned i
= 0; i
< 2; i
++) {
2040 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
2041 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
||
2042 ctx
.uses
[op2_instr
->definitions
[1].tempId()])
2044 if (!op2_instr
->operands
[1].isConstant() || fixed_to_exec(op2_instr
->operands
[0]))
2047 uint32_t shift
= op2_instr
->operands
[1].constantValue();
2048 if (shift
< 1 || shift
> 4)
2051 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
2052 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
2055 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2056 instr
->operands
[1] = instr
->operands
[!i
];
2057 instr
->operands
[0] = op2_instr
->operands
[0];
2058 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2060 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
2061 aco_opcode::s_lshl2_add_u32
,
2062 aco_opcode::s_lshl3_add_u32
,
2063 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
2070 bool combine_add_sub_b2i(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode new_op
, uint8_t ops
)
2072 if (instr
->usesModifiers())
2075 for (unsigned i
= 0; i
< 2; i
++) {
2076 if (!((1 << i
) & ops
))
2078 if (instr
->operands
[i
].isTemp() &&
2079 ctx
.info
[instr
->operands
[i
].tempId()].is_b2i() &&
2080 ctx
.uses
[instr
->operands
[i
].tempId()] == 1) {
2082 aco_ptr
<Instruction
> new_instr
;
2083 if (instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2084 new_instr
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 2));
2085 } else if (ctx
.program
->chip_class
>= GFX10
||
2086 (instr
->operands
[!i
].isConstant() && !instr
->operands
[!i
].isLiteral())) {
2087 new_instr
.reset(create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOP2
), 3, 2));
2091 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2092 new_instr
->definitions
[0] = instr
->definitions
[0];
2093 new_instr
->definitions
[1] = instr
->definitions
.size() == 2 ? instr
->definitions
[1] :
2094 Definition(ctx
.program
->allocateId(), ctx
.program
->lane_mask
);
2095 new_instr
->definitions
[1].setHint(vcc
);
2096 new_instr
->operands
[0] = Operand(0u);
2097 new_instr
->operands
[1] = instr
->operands
[!i
];
2098 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2099 instr
= std::move(new_instr
);
2100 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2108 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
2111 #define MINMAX(type, gfx9) \
2112 case aco_opcode::v_min_##type:\
2113 case aco_opcode::v_max_##type:\
2114 case aco_opcode::v_med3_##type:\
2115 *min = aco_opcode::v_min_##type;\
2116 *max = aco_opcode::v_max_##type;\
2117 *med3 = aco_opcode::v_med3_##type;\
2118 *min3 = aco_opcode::v_min3_##type;\
2119 *max3 = aco_opcode::v_max3_##type;\
2120 *some_gfx9_only = gfx9;\
2134 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
2135 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
2136 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
2137 aco_opcode min
, aco_opcode max
, aco_opcode med
)
2139 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
2140 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
2141 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
2142 aco_opcode other_op
;
2143 if (instr
->opcode
== min
)
2145 else if (instr
->opcode
== max
)
2150 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
2151 (label_omod_success
| label_clamp_success
);
2153 for (unsigned swap
= 0; swap
< 2; swap
++) {
2154 Operand operands
[3];
2155 bool neg
[3], abs
[3], clamp
;
2156 uint8_t opsel
= 0, omod
= 0;
2157 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
2158 "012", operands
, neg
, abs
, &opsel
,
2159 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
2160 int const0_idx
= -1, const1_idx
= -1;
2161 uint32_t const0
= 0, const1
= 0;
2162 for (int i
= 0; i
< 3; i
++) {
2164 if (operands
[i
].isConstant()) {
2165 val
= operands
[i
].constantValue();
2166 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal(32)) {
2167 val
= ctx
.info
[operands
[i
].tempId()].val
;
2171 if (const0_idx
>= 0) {
2179 if (const0_idx
< 0 || const1_idx
< 0)
2182 if (opsel
& (1 << const0_idx
))
2184 if (opsel
& (1 << const1_idx
))
2187 int lower_idx
= const0_idx
;
2189 case aco_opcode::v_min_f32
:
2190 case aco_opcode::v_min_f16
: {
2191 float const0_f
, const1_f
;
2192 if (min
== aco_opcode::v_min_f32
) {
2193 memcpy(&const0_f
, &const0
, 4);
2194 memcpy(&const1_f
, &const1
, 4);
2196 const0_f
= _mesa_half_to_float(const0
);
2197 const1_f
= _mesa_half_to_float(const1
);
2199 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
2200 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
2201 if (neg
[const0_idx
]) const0_f
= -const0_f
;
2202 if (neg
[const1_idx
]) const1_f
= -const1_f
;
2203 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
2206 case aco_opcode::v_min_u32
: {
2207 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
2210 case aco_opcode::v_min_u16
: {
2211 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
2214 case aco_opcode::v_min_i32
: {
2215 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
2216 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
2217 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2220 case aco_opcode::v_min_i16
: {
2221 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
2222 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
2223 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2229 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
2231 if (instr
->opcode
== min
) {
2232 if (upper_idx
!= 0 || lower_idx
== 0)
2235 if (upper_idx
== 0 || lower_idx
!= 0)
2239 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2240 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2241 if (omod_clamp
& label_omod_success
)
2242 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2243 if (omod_clamp
& label_clamp_success
)
2244 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2254 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2256 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2257 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2258 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2260 /* find candidates and create the set of sgprs already read */
2261 unsigned sgpr_ids
[2] = {0, 0};
2262 uint32_t operand_mask
= 0;
2263 bool has_literal
= false;
2264 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2265 if (instr
->operands
[i
].isLiteral())
2267 if (!instr
->operands
[i
].isTemp())
2269 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2270 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
2271 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
2273 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
2274 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
2275 operand_mask
|= 1u << i
;
2277 unsigned max_sgprs
= 1;
2278 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2283 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2285 /* keep on applying sgprs until there is nothing left to be done */
2286 while (operand_mask
) {
2287 uint32_t sgpr_idx
= 0;
2288 uint32_t sgpr_info_id
= 0;
2289 uint32_t mask
= operand_mask
;
2292 unsigned i
= u_bit_scan(&mask
);
2293 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2294 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
2296 sgpr_info_id
= instr
->operands
[i
].tempId();
2299 operand_mask
&= ~(1u << sgpr_idx
);
2301 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2302 * definitively beneficial.
2303 * TODO: this is too conservative because later the use count could be reduced to 1 */
2304 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2307 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2308 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2309 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2312 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2313 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2314 } else if (can_swap_operands(instr
)) {
2315 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2316 instr
->operands
[0] = Operand(sgpr
);
2317 /* swap bits using a 4-entry LUT */
2318 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2319 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2320 } else if (can_use_VOP3(ctx
, instr
)) {
2321 to_VOP3(ctx
, instr
);
2322 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2328 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2329 ctx
.uses
[sgpr_info_id
]--;
2330 ctx
.uses
[sgpr
.id()]++;
2334 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2336 /* check if we could apply omod on predecessor */
2337 if (instr
->opcode
== aco_opcode::v_mul_f32
|| instr
->opcode
== aco_opcode::v_mul_f16
) {
2338 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2339 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2341 unsigned idx
= op0
? 0 : 1;
2342 /* omod was successfully applied */
2343 /* if the omod instruction is v_mad, we also have to change the original add */
2344 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2345 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2346 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2347 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2348 add_instr
->definitions
[0] = instr
->definitions
[0];
2351 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2352 /* check if we have an additional clamp modifier */
2353 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2354 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2355 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2356 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2358 /* change definition ssa-id of modified instruction */
2359 omod_instr
->definitions
[0] = instr
->definitions
[0];
2361 /* change the definition of instr to something unused, e.g. the original omod def */
2362 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2363 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2366 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2367 /* in all other cases, label this instruction as option for multiply-add */
2368 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2372 /* check if we could apply clamp on predecessor */
2373 if (instr
->opcode
== aco_opcode::v_med3_f32
|| instr
->opcode
== aco_opcode::v_med3_f16
) {
2374 bool is_fp16
= instr
->opcode
== aco_opcode::v_med3_f16
;
2376 bool found_zero
= false, found_one
= false;
2377 for (unsigned i
= 0; i
< 3; i
++)
2379 if (instr
->operands
[i
].constantEquals(0))
2381 else if (instr
->operands
[i
].constantEquals(is_fp16
? 0x3c00 : 0x3f800000)) /* 1.0 */
2386 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2387 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2388 /* clamp was successfully applied */
2389 /* if the clamp instruction is v_mad, we also have to change the original add */
2390 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2391 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2392 add_instr
->definitions
[0] = instr
->definitions
[0];
2394 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2395 /* change definition ssa-id of modified instruction */
2396 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2398 /* change the definition of instr to something unused, e.g. the original omod def */
2399 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2400 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2405 /* omod has no effect if denormals are enabled */
2406 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2407 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2408 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2409 bool can_use_omod
= (instr
->definitions
[0].bytes() == 4 ? block
.fp_mode
.denorm32
: block
.fp_mode
.denorm16_64
) == 0;
2410 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2411 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2412 to_VOP3(ctx
, instr
);
2413 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2414 def_info
.set_omod_success(instr
.get());
2415 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2416 to_VOP3(ctx
, instr
);
2417 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2418 def_info
.set_omod_success(instr
.get());
2419 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2420 to_VOP3(ctx
, instr
);
2421 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2422 def_info
.set_omod_success(instr
.get());
2423 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2424 to_VOP3(ctx
, instr
);
2425 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2426 def_info
.set_clamp_success(instr
.get());
2433 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2434 // this would mean that we'd have to fix the instruction uses while value propagation
2436 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2438 if (instr
->definitions
.empty() || is_dead(ctx
.uses
, instr
.get()))
2441 if (instr
->isVALU()) {
2442 if (can_apply_sgprs(instr
))
2443 apply_sgprs(ctx
, instr
);
2444 if (apply_omod_clamp(ctx
, block
, instr
))
2448 if (ctx
.info
[instr
->definitions
[0].tempId()].is_vcc_hint()) {
2449 instr
->definitions
[0].setHint(vcc
);
2452 /* TODO: There are still some peephole optimizations that could be done:
2453 * - abs(a - b) -> s_absdiff_i32
2454 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2455 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2456 * These aren't probably too interesting though.
2457 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2458 * probably more useful than the previously mentioned optimizations.
2459 * The various comparison optimizations also currently only work with 32-bit
2462 /* neg(mul(a, b)) -> mul(neg(a), b) */
2463 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2464 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2466 if (!ctx
.info
[val
.id()].is_mul())
2469 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2471 if (mul_instr
->operands
[0].isLiteral())
2473 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2476 /* convert to mul(neg(a), b) */
2477 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2478 Definition def
= instr
->definitions
[0];
2479 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2480 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2481 instr
.reset(create_instruction
<VOP3A_instruction
>(mul_instr
->opcode
, asVOP3(Format::VOP2
), 2, 1));
2482 instr
->operands
[0] = mul_instr
->operands
[0];
2483 instr
->operands
[1] = mul_instr
->operands
[1];
2484 instr
->definitions
[0] = def
;
2485 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2486 if (mul_instr
->isVOP3()) {
2487 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2488 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2489 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2490 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2491 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2492 new_mul
->omod
= mul
->omod
;
2494 new_mul
->neg
[0] ^= true;
2495 new_mul
->clamp
= false;
2497 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2501 /* combine mul+add -> mad */
2502 bool mad32
= instr
->opcode
== aco_opcode::v_add_f32
||
2503 instr
->opcode
== aco_opcode::v_sub_f32
||
2504 instr
->opcode
== aco_opcode::v_subrev_f32
;
2505 bool mad16
= instr
->opcode
== aco_opcode::v_add_f16
||
2506 instr
->opcode
== aco_opcode::v_sub_f16
||
2507 instr
->opcode
== aco_opcode::v_subrev_f16
;
2508 if (mad16
|| mad32
) {
2509 bool need_fma
= mad32
? block
.fp_mode
.denorm32
!= 0 :
2510 (block
.fp_mode
.denorm16_64
!= 0 || ctx
.program
->chip_class
>= GFX10
);
2511 if (need_fma
&& instr
->definitions
[0].isPrecise())
2513 if (need_fma
&& mad32
&& !ctx
.program
->has_fast_fma32
)
2516 uint32_t uses_src0
= UINT32_MAX
;
2517 uint32_t uses_src1
= UINT32_MAX
;
2518 Instruction
* mul_instr
= nullptr;
2519 unsigned add_op_idx
;
2520 /* check if any of the operands is a multiplication */
2521 ssa_info
*op0_info
= instr
->operands
[0].isTemp() ? &ctx
.info
[instr
->operands
[0].tempId()] : NULL
;
2522 ssa_info
*op1_info
= instr
->operands
[1].isTemp() ? &ctx
.info
[instr
->operands
[1].tempId()] : NULL
;
2523 if (op0_info
&& op0_info
->is_mul() && (!need_fma
|| !op0_info
->instr
->definitions
[0].isPrecise()))
2524 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2525 if (op1_info
&& op1_info
->is_mul() && (!need_fma
|| !op1_info
->instr
->definitions
[0].isPrecise()))
2526 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2528 /* find the 'best' mul instruction to combine with the add */
2529 if (uses_src0
< uses_src1
) {
2530 mul_instr
= op0_info
->instr
;
2532 } else if (uses_src1
< uses_src0
) {
2533 mul_instr
= op1_info
->instr
;
2535 } else if (uses_src0
!= UINT32_MAX
) {
2536 /* tiebreaker: quite random what to pick */
2537 if (op0_info
->instr
->operands
[0].isLiteral()) {
2538 mul_instr
= op1_info
->instr
;
2541 mul_instr
= op0_info
->instr
;
2546 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2547 bool neg
[3] = {false, false, false};
2548 bool abs
[3] = {false, false, false};
2551 op
[0] = mul_instr
->operands
[0];
2552 op
[1] = mul_instr
->operands
[1];
2553 op
[2] = instr
->operands
[add_op_idx
];
2554 // TODO: would be better to check this before selecting a mul instr?
2555 if (!check_vop3_operands(ctx
, 3, op
))
2558 if (mul_instr
->isVOP3()) {
2559 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2560 neg
[0] = vop3
->neg
[0];
2561 neg
[1] = vop3
->neg
[1];
2562 abs
[0] = vop3
->abs
[0];
2563 abs
[1] = vop3
->abs
[1];
2564 /* we cannot use these modifiers between mul and add */
2565 if (vop3
->clamp
|| vop3
->omod
)
2569 /* convert to mad */
2570 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2571 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2573 ctx
.uses
[op
[0].tempId()]++;
2575 ctx
.uses
[op
[1].tempId()]++;
2578 if (instr
->isVOP3()) {
2579 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2580 neg
[2] = vop3
->neg
[add_op_idx
];
2581 abs
[2] = vop3
->abs
[add_op_idx
];
2583 clamp
= vop3
->clamp
;
2584 /* abs of the multiplication result */
2585 if (vop3
->abs
[1 - add_op_idx
]) {
2591 /* neg of the multiplication result */
2592 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2594 if (instr
->opcode
== aco_opcode::v_sub_f32
|| instr
->opcode
== aco_opcode::v_sub_f16
)
2595 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2596 else if (instr
->opcode
== aco_opcode::v_subrev_f32
|| instr
->opcode
== aco_opcode::v_subrev_f16
)
2597 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2599 aco_opcode mad_op
= need_fma
? aco_opcode::v_fma_f32
: aco_opcode::v_mad_f32
;
2601 mad_op
= need_fma
? (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_fma_legacy_f16
: aco_opcode::v_fma_f16
) :
2602 (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_mad_legacy_f16
: aco_opcode::v_mad_f16
);
2604 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(mad_op
, Format::VOP3A
, 3, 1)};
2605 for (unsigned i
= 0; i
< 3; i
++)
2607 mad
->operands
[i
] = op
[i
];
2608 mad
->neg
[i
] = neg
[i
];
2609 mad
->abs
[i
] = abs
[i
];
2613 mad
->definitions
[0] = instr
->definitions
[0];
2615 /* mark this ssa_def to be re-checked for profitability and literals */
2616 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2617 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2618 instr
.reset(mad
.release());
2622 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2623 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2624 for (unsigned i
= 0; i
< 2; i
++) {
2625 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2626 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2627 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2628 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2629 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2631 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2632 new_instr
->operands
[0] = Operand(0u);
2633 new_instr
->operands
[1] = instr
->operands
[!i
];
2634 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2635 new_instr
->definitions
[0] = instr
->definitions
[0];
2636 instr
.reset(new_instr
.release());
2637 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2641 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2642 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2643 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2644 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2645 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2646 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_or_b32
, "120", 1 | 2)) ;
2647 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2648 } else if (instr
->opcode
== aco_opcode::v_xor_b32
&& ctx
.program
->chip_class
>= GFX10
) {
2649 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2)) ;
2650 else combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2);
2651 } else if (instr
->opcode
== aco_opcode::v_add_u32
) {
2652 if (combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2)) ;
2653 else if (ctx
.program
->chip_class
>= GFX9
) {
2654 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2655 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2656 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_i32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2657 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2658 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2659 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_add_u32
, "120", 1 | 2)) ;
2660 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2662 } else if (instr
->opcode
== aco_opcode::v_add_co_u32
||
2663 instr
->opcode
== aco_opcode::v_add_co_u32_e64
) {
2664 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2);
2665 } else if (instr
->opcode
== aco_opcode::v_sub_u32
||
2666 instr
->opcode
== aco_opcode::v_sub_co_u32
||
2667 instr
->opcode
== aco_opcode::v_sub_co_u32_e64
) {
2668 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 2);
2669 } else if (instr
->opcode
== aco_opcode::v_subrev_u32
||
2670 instr
->opcode
== aco_opcode::v_subrev_co_u32
||
2671 instr
->opcode
== aco_opcode::v_subrev_co_u32_e64
) {
2672 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 1);
2673 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2674 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2675 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2676 combine_salu_lshl_add(ctx
, instr
);
2677 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2678 combine_salu_not_bitwise(ctx
, instr
);
2679 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2680 if (combine_inverse_comparison(ctx
, instr
)) ;
2681 else combine_salu_not_bitwise(ctx
, instr
);
2682 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2683 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2684 if (combine_ordering_test(ctx
, instr
)) ;
2685 else if (combine_comparison_ordering(ctx
, instr
)) ;
2686 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2687 else combine_salu_n2(ctx
, instr
);
2689 aco_opcode min
, max
, min3
, max3
, med3
;
2690 bool some_gfx9_only
;
2691 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2692 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2693 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2694 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2699 bool to_uniform_bool_instr(opt_ctx
&ctx
, aco_ptr
<Instruction
> &instr
)
2701 switch (instr
->opcode
) {
2702 case aco_opcode::s_and_b32
:
2703 case aco_opcode::s_and_b64
:
2704 instr
->opcode
= aco_opcode::s_and_b32
;
2706 case aco_opcode::s_or_b32
:
2707 case aco_opcode::s_or_b64
:
2708 instr
->opcode
= aco_opcode::s_or_b32
;
2710 case aco_opcode::s_xor_b32
:
2711 case aco_opcode::s_xor_b64
:
2712 instr
->opcode
= aco_opcode::s_absdiff_i32
;
2715 /* Don't transform other instructions. They are very unlikely to appear here. */
2719 for (Operand
&op
: instr
->operands
) {
2720 ctx
.uses
[op
.tempId()]--;
2722 if (ctx
.info
[op
.tempId()].is_uniform_bool()) {
2723 /* Just use the uniform boolean temp. */
2724 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
2725 } else if (ctx
.info
[op
.tempId()].is_uniform_bitwise()) {
2726 /* Use the SCC definition of the predecessor instruction.
2727 * This allows the predecessor to get picked up by the same optimization (if it has no divergent users),
2728 * and it also makes sure that the current instruction will keep working even if the predecessor won't be transformed.
2730 Instruction
*pred_instr
= ctx
.info
[op
.tempId()].instr
;
2731 assert(pred_instr
->definitions
.size() >= 2);
2732 assert(pred_instr
->definitions
[1].isFixed() && pred_instr
->definitions
[1].physReg() == scc
);
2733 op
.setTemp(pred_instr
->definitions
[1].getTemp());
2735 unreachable("Invalid operand on uniform bitwise instruction.");
2738 ctx
.uses
[op
.tempId()]++;
2741 instr
->definitions
[0].setTemp(Temp(instr
->definitions
[0].tempId(), s1
));
2742 assert(instr
->operands
[0].regClass() == s1
);
2743 assert(instr
->operands
[1].regClass() == s1
);
2747 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2749 const uint32_t threshold
= 4;
2751 if (is_dead(ctx
.uses
, instr
.get())) {
2756 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2757 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2758 unsigned num_used
= 0;
2760 unsigned split_offset
= 0;
2761 for (unsigned i
= 0, offset
= 0; i
< instr
->definitions
.size(); offset
+= instr
->definitions
[i
++].bytes()) {
2762 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2765 split_offset
= offset
;
2769 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2770 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2771 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2775 for (Operand
& vec_op
: vec
->operands
) {
2776 if (off
== split_offset
) {
2780 off
+= vec_op
.bytes();
2782 if (off
!= instr
->operands
[0].bytes() && op
.bytes() == instr
->definitions
[idx
].bytes()) {
2783 ctx
.uses
[instr
->operands
[0].tempId()]--;
2784 for (Operand
& vec_op
: vec
->operands
) {
2785 if (vec_op
.isTemp())
2786 ctx
.uses
[vec_op
.tempId()]--;
2789 ctx
.uses
[op
.tempId()]++;
2791 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2792 extract
->operands
[0] = op
;
2793 extract
->definitions
[0] = instr
->definitions
[idx
];
2794 instr
.reset(extract
.release());
2800 if (!done
&& num_used
== 1 &&
2801 instr
->operands
[0].bytes() % instr
->definitions
[idx
].bytes() == 0 &&
2802 split_offset
% instr
->definitions
[idx
].bytes() == 0) {
2803 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2804 extract
->operands
[0] = instr
->operands
[0];
2805 extract
->operands
[1] = Operand((uint32_t) split_offset
/ instr
->definitions
[idx
].bytes());
2806 extract
->definitions
[0] = instr
->definitions
[idx
];
2807 instr
.reset(extract
.release());
2811 mad_info
* mad_info
= NULL
;
2812 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2813 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2814 /* re-check mad instructions */
2815 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2816 ctx
.uses
[mad_info
->mul_temp_id
]++;
2817 if (instr
->operands
[0].isTemp())
2818 ctx
.uses
[instr
->operands
[0].tempId()]--;
2819 if (instr
->operands
[1].isTemp())
2820 ctx
.uses
[instr
->operands
[1].tempId()]--;
2821 instr
.swap(mad_info
->add_instr
);
2824 /* check literals */
2825 else if (!instr
->usesModifiers()) {
2826 /* FMA can only take literals on GFX10+ */
2827 if ((instr
->opcode
== aco_opcode::v_fma_f32
|| instr
->opcode
== aco_opcode::v_fma_f16
) &&
2828 ctx
.program
->chip_class
< GFX10
)
2831 bool sgpr_used
= false;
2832 uint32_t literal_idx
= 0;
2833 uint32_t literal_uses
= UINT32_MAX
;
2834 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2836 if (instr
->operands
[i
].isConstant() && i
> 0) {
2837 literal_uses
= UINT32_MAX
;
2840 if (!instr
->operands
[i
].isTemp())
2842 unsigned bits
= get_operand_size(instr
, i
);
2843 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2844 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2845 if (!sgpr_used
&& ctx
.info
[instr
->operands
[i
].tempId()].is_literal(bits
)) {
2846 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2849 literal_uses
= UINT32_MAX
;
2852 /* don't break because we still need to check constants */
2853 } else if (!sgpr_used
&&
2854 ctx
.info
[instr
->operands
[i
].tempId()].is_literal(bits
) &&
2855 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2856 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2861 /* Limit the number of literals to apply to not increase the code
2862 * size too much, but always apply literals for v_mad->v_madak
2863 * because both instructions are 64-bit and this doesn't increase
2865 * TODO: try to apply the literals earlier to lower the number of
2866 * uses below threshold
2868 if (literal_uses
< threshold
|| literal_idx
== 2) {
2869 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2870 mad_info
->check_literal
= true;
2871 mad_info
->literal_idx
= literal_idx
;
2877 /* Mark SCC needed, so the uniform boolean transformation won't swap the definitions when it isn't beneficial */
2878 if (instr
->format
== Format::PSEUDO_BRANCH
&&
2879 instr
->operands
.size() &&
2880 instr
->operands
[0].isTemp()) {
2881 ctx
.info
[instr
->operands
[0].tempId()].set_scc_needed();
2883 } else if ((instr
->opcode
== aco_opcode::s_cselect_b64
||
2884 instr
->opcode
== aco_opcode::s_cselect_b32
) &&
2885 instr
->operands
[2].isTemp()) {
2886 ctx
.info
[instr
->operands
[2].tempId()].set_scc_needed();
2889 /* check for literals */
2890 if (!instr
->isSALU() && !instr
->isVALU())
2893 /* Transform uniform bitwise boolean operations to 32-bit when there are no divergent uses. */
2894 if (instr
->definitions
.size() &&
2895 ctx
.uses
[instr
->definitions
[0].tempId()] == 0 &&
2896 ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bitwise()) {
2897 bool transform_done
= to_uniform_bool_instr(ctx
, instr
);
2899 if (transform_done
&& !ctx
.info
[instr
->definitions
[1].tempId()].is_scc_needed()) {
2900 /* Swap the two definition IDs in order to avoid overusing the SCC. This reduces extra moves generated by RA. */
2901 uint32_t def0_id
= instr
->definitions
[0].getTemp().id();
2902 uint32_t def1_id
= instr
->definitions
[1].getTemp().id();
2903 instr
->definitions
[0].setTemp(Temp(def1_id
, s1
));
2904 instr
->definitions
[1].setTemp(Temp(def0_id
, s1
));
2910 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
2911 return; /* some encodings can't ever take literals */
2913 /* we do not apply the literals yet as we don't know if it is profitable */
2914 Operand
current_literal(s1
);
2916 unsigned literal_id
= 0;
2917 unsigned literal_uses
= UINT32_MAX
;
2918 Operand
literal(s1
);
2919 unsigned num_operands
= 1;
2920 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
2921 num_operands
= instr
->operands
.size();
2922 /* catch VOP2 with a 3rd SGPR operand (e.g. v_cndmask_b32, v_addc_co_u32) */
2923 else if (instr
->isVALU() && instr
->operands
.size() >= 3)
2926 unsigned sgpr_ids
[2] = {0, 0};
2927 bool is_literal_sgpr
= false;
2930 /* choose a literal to apply */
2931 for (unsigned i
= 0; i
< num_operands
; i
++) {
2932 Operand op
= instr
->operands
[i
];
2933 unsigned bits
= get_operand_size(instr
, i
);
2935 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
2936 op
.tempId() != sgpr_ids
[0])
2937 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
2939 if (op
.isLiteral()) {
2940 current_literal
= op
;
2942 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal(bits
)) {
2946 if (!alu_can_accept_constant(instr
->opcode
, i
))
2949 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
2950 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
2952 literal
= Operand(ctx
.info
[op
.tempId()].val
);
2953 literal_uses
= ctx
.uses
[op
.tempId()];
2954 literal_id
= op
.tempId();
2957 mask
|= (op
.tempId() == literal_id
) << i
;
2961 /* don't go over the constant bus limit */
2962 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2963 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2964 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2965 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
2966 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2967 const_bus_limit
= 2;
2969 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2970 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
2973 if (literal_id
&& literal_uses
< threshold
&&
2974 (current_literal
.isUndefined() ||
2975 (current_literal
.size() == literal
.size() &&
2976 current_literal
.constantValue() == literal
.constantValue()))) {
2977 /* mark the literal to be applied */
2979 unsigned i
= u_bit_scan(&mask
);
2980 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
2981 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2987 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2989 /* Cleanup Dead Instructions */
2993 /* apply literals on MAD */
2994 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2995 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2996 if (info
->check_literal
&&
2997 (ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0 || info
->literal_idx
== 2)) {
2998 aco_ptr
<Instruction
> new_mad
;
3000 aco_opcode new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f32
: aco_opcode::v_madmk_f32
;
3001 if (instr
->opcode
== aco_opcode::v_fma_f32
)
3002 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f32
: aco_opcode::v_fmamk_f32
;
3003 else if (instr
->opcode
== aco_opcode::v_mad_f16
|| instr
->opcode
== aco_opcode::v_mad_legacy_f16
)
3004 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f16
: aco_opcode::v_madmk_f16
;
3005 else if (instr
->opcode
== aco_opcode::v_fma_f16
)
3006 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f16
: aco_opcode::v_fmamk_f16
;
3008 new_mad
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 1));
3009 if (info
->literal_idx
== 2) { /* add literal -> madak */
3010 new_mad
->operands
[0] = instr
->operands
[0];
3011 new_mad
->operands
[1] = instr
->operands
[1];
3012 } else { /* mul literal -> madmk */
3013 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
3014 new_mad
->operands
[1] = instr
->operands
[2];
3016 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
3017 new_mad
->definitions
[0] = instr
->definitions
[0];
3018 ctx
.instructions
.emplace_back(std::move(new_mad
));
3023 /* apply literals on other SALU/VALU */
3024 if (instr
->isSALU() || instr
->isVALU()) {
3025 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
3026 Operand op
= instr
->operands
[i
];
3027 unsigned bits
= get_operand_size(instr
, i
);
3028 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal(bits
) && ctx
.uses
[op
.tempId()] == 0) {
3029 Operand
literal(ctx
.info
[op
.tempId()].val
);
3030 if (instr
->isVALU() && i
> 0)
3031 to_VOP3(ctx
, instr
);
3032 instr
->operands
[i
] = literal
;
3037 ctx
.instructions
.emplace_back(std::move(instr
));
3041 void optimize(Program
* program
)
3044 ctx
.program
= program
;
3045 std::vector
<ssa_info
> info(program
->peekAllocationId());
3046 ctx
.info
= info
.data();
3048 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
3049 for (Block
& block
: program
->blocks
) {
3050 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3051 label_instruction(ctx
, block
, instr
);
3054 ctx
.uses
= dead_code_analysis(program
);
3056 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
3057 for (Block
& block
: program
->blocks
) {
3058 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3059 combine_instruction(ctx
, block
, instr
);
3062 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
3063 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
3064 Block
* block
= &(*it
);
3065 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
3066 select_instruction(ctx
, *it
);
3069 /* 4. Add literals to instructions */
3070 for (Block
& block
: program
->blocks
) {
3071 ctx
.instructions
.clear();
3072 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3073 apply_literals(ctx
, instr
);
3074 block
.instructions
.swap(ctx
.instructions
);