2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant
= 1 << 1,
69 label_literal
= 1 << 6,
73 label_omod5
= 1 << 10,
74 label_omod_success
= 1 << 11,
75 label_clamp
= 1 << 12,
76 label_clamp_success
= 1 << 13,
77 label_undefined
= 1 << 14,
80 label_add_sub
= 1 << 17,
81 label_bitwise
= 1 << 18,
82 label_minmax
= 1 << 19,
84 label_uniform_bool
= 1 << 21,
85 label_constant_64bit
= 1 << 22,
86 label_uniform_bitwise
= 1 << 23,
87 label_scc_invert
= 1 << 24,
88 label_vcc_hint
= 1 << 25,
89 label_scc_needed
= 1 << 26,
92 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
|
93 label_add_sub
| label_bitwise
| label_uniform_bitwise
| label_minmax
| label_fcmp
;
94 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
|
95 label_omod2
| label_omod4
| label_omod5
| label_clamp
| label_scc_invert
;
96 static constexpr uint32_t val_labels
= label_constant
| label_constant_64bit
| label_literal
| label_mad
;
106 ssa_info() : label(0) {}
108 void add_label(Label new_label
)
110 /* Since all labels which use "instr" use it for the same thing
111 * (indicating the defining instruction), there is no need to clear
112 * any other instr labels. */
113 if (new_label
& instr_labels
)
114 label
&= ~temp_labels
; /* instr and temp alias */
116 if (new_label
& temp_labels
) {
117 label
&= ~temp_labels
;
118 label
&= ~instr_labels
; /* instr and temp alias */
121 if (new_label
& val_labels
)
122 label
&= ~val_labels
;
127 void set_vec(Instruction
* vec
)
129 add_label(label_vec
);
135 return label
& label_vec
;
138 void set_constant(uint32_t constant
)
140 add_label(label_constant
);
146 return label
& label_constant
;
149 void set_constant_64bit(uint32_t constant
)
151 add_label(label_constant_64bit
);
155 bool is_constant_64bit()
157 return label
& label_constant_64bit
;
160 void set_abs(Temp abs_temp
)
162 add_label(label_abs
);
168 return label
& label_abs
;
171 void set_neg(Temp neg_temp
)
173 add_label(label_neg
);
179 return label
& label_neg
;
182 void set_neg_abs(Temp neg_abs_temp
)
184 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
188 void set_mul(Instruction
* mul
)
190 add_label(label_mul
);
196 return label
& label_mul
;
199 void set_temp(Temp tmp
)
201 add_label(label_temp
);
207 return label
& label_temp
;
210 void set_literal(uint32_t lit
)
212 add_label(label_literal
);
218 return label
& label_literal
;
221 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
223 add_label(label_mad
);
230 return label
& label_mad
;
233 void set_omod2(Temp def
)
235 add_label(label_omod2
);
241 return label
& label_omod2
;
244 void set_omod4(Temp def
)
246 add_label(label_omod4
);
252 return label
& label_omod4
;
255 void set_omod5(Temp def
)
257 add_label(label_omod5
);
263 return label
& label_omod5
;
266 void set_omod_success(Instruction
* omod_instr
)
268 add_label(label_omod_success
);
272 bool is_omod_success()
274 return label
& label_omod_success
;
277 void set_clamp(Temp def
)
279 add_label(label_clamp
);
285 return label
& label_clamp
;
288 void set_clamp_success(Instruction
* clamp_instr
)
290 add_label(label_clamp_success
);
294 bool is_clamp_success()
296 return label
& label_clamp_success
;
301 add_label(label_undefined
);
306 return label
& label_undefined
;
309 void set_vcc(Temp vcc
)
311 add_label(label_vcc
);
317 return label
& label_vcc
;
320 bool is_constant_or_literal()
322 return is_constant() || is_literal();
325 void set_b2f(Temp val
)
327 add_label(label_b2f
);
333 return label
& label_b2f
;
336 void set_add_sub(Instruction
*add_sub_instr
)
338 add_label(label_add_sub
);
339 instr
= add_sub_instr
;
344 return label
& label_add_sub
;
347 void set_bitwise(Instruction
*bitwise_instr
)
349 add_label(label_bitwise
);
350 instr
= bitwise_instr
;
355 return label
& label_bitwise
;
358 void set_uniform_bitwise()
360 add_label(label_uniform_bitwise
);
363 bool is_uniform_bitwise()
365 return label
& label_uniform_bitwise
;
368 void set_minmax(Instruction
*minmax_instr
)
370 add_label(label_minmax
);
371 instr
= minmax_instr
;
376 return label
& label_minmax
;
379 void set_fcmp(Instruction
*fcmp_instr
)
381 add_label(label_fcmp
);
387 return label
& label_fcmp
;
390 void set_scc_needed()
392 add_label(label_scc_needed
);
397 return label
& label_scc_needed
;
400 void set_scc_invert(Temp scc_inv
)
402 add_label(label_scc_invert
);
408 return label
& label_scc_invert
;
411 void set_uniform_bool(Temp uniform_bool
)
413 add_label(label_uniform_bool
);
417 bool is_uniform_bool()
419 return label
& label_uniform_bool
;
424 add_label(label_vcc_hint
);
429 return label
& label_vcc_hint
;
435 std::vector
<aco_ptr
<Instruction
>> instructions
;
437 std::pair
<uint32_t,Temp
> last_literal
;
438 std::vector
<mad_info
> mad_infos
;
439 std::vector
<uint16_t> uses
;
442 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
444 if (instr
->operands
[0].isConstant() ||
445 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
448 switch (instr
->opcode
) {
449 case aco_opcode::v_add_f32
:
450 case aco_opcode::v_mul_f32
:
451 case aco_opcode::v_or_b32
:
452 case aco_opcode::v_and_b32
:
453 case aco_opcode::v_xor_b32
:
454 case aco_opcode::v_max_f32
:
455 case aco_opcode::v_min_f32
:
456 case aco_opcode::v_max_i32
:
457 case aco_opcode::v_min_i32
:
458 case aco_opcode::v_max_u32
:
459 case aco_opcode::v_min_u32
:
460 case aco_opcode::v_cmp_eq_f32
:
461 case aco_opcode::v_cmp_lg_f32
:
463 case aco_opcode::v_sub_f32
:
464 instr
->opcode
= aco_opcode::v_subrev_f32
;
466 case aco_opcode::v_cmp_lt_f32
:
467 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
469 case aco_opcode::v_cmp_ge_f32
:
470 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
472 case aco_opcode::v_cmp_lt_i32
:
473 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
480 bool can_use_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
485 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
488 if (instr
->isDPP() || instr
->isSDWA())
491 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
492 instr
->opcode
!= aco_opcode::v_madak_f32
&&
493 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
494 instr
->opcode
!= aco_opcode::v_madak_f16
&&
495 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
496 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
497 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
498 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
499 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
500 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
501 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
504 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
506 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
507 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
508 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
509 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
510 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
513 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
518 aco_ptr
<Instruction
> tmp
= std::move(instr
);
519 Format format
= asVOP3(tmp
->format
);
520 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
521 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
522 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
523 instr
->definitions
[i
] = tmp
->definitions
[i
];
524 if (instr
->definitions
[i
].isTemp()) {
525 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
526 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
527 info
.instr
= instr
.get();
532 /* only covers special cases */
533 bool alu_can_accept_constant(aco_opcode opcode
, unsigned operand
)
536 case aco_opcode::v_interp_p2_f32
:
537 case aco_opcode::v_mac_f32
:
538 case aco_opcode::v_writelane_b32
:
539 case aco_opcode::v_writelane_b32_e64
:
540 case aco_opcode::v_cndmask_b32
:
542 case aco_opcode::s_addk_i32
:
543 case aco_opcode::s_mulk_i32
:
544 case aco_opcode::p_wqm
:
545 case aco_opcode::p_extract_vector
:
546 case aco_opcode::p_split_vector
:
547 case aco_opcode::v_readlane_b32
:
548 case aco_opcode::v_readlane_b32_e64
:
549 case aco_opcode::v_readfirstlane_b32
:
556 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
558 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
559 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
564 /* check constant bus and literal limitations */
565 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
567 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
568 Operand
literal32(s1
);
569 Operand
literal64(s2
);
570 unsigned num_sgprs
= 0;
571 unsigned sgpr
[] = {0, 0};
573 for (unsigned i
= 0; i
< num_operands
; i
++) {
574 Operand op
= operands
[i
];
576 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
577 /* two reads of the same SGPR count as 1 to the limit */
578 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
580 sgpr
[num_sgprs
++] = op
.tempId();
585 } else if (op
.isLiteral()) {
586 if (ctx
.program
->chip_class
< GFX10
)
589 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
591 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
594 /* Any number of 32-bit literals counts as only 1 to the limit. Same
595 * (but separately) for 64-bit literals. */
596 if (op
.size() == 1 && literal32
.isUndefined()) {
599 } else if (op
.size() == 2 && literal64
.isUndefined()) {
612 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
614 Operand op
= instr
->operands
[op_index
];
618 Temp tmp
= op
.getTemp();
619 if (!ctx
.info
[tmp
.id()].is_add_sub())
622 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
624 switch (add_instr
->opcode
) {
625 case aco_opcode::v_add_u32
:
626 case aco_opcode::v_add_co_u32
:
627 case aco_opcode::v_add_co_u32_e64
:
628 case aco_opcode::s_add_i32
:
629 case aco_opcode::s_add_u32
:
635 if (add_instr
->usesModifiers())
638 for (unsigned i
= 0; i
< 2; i
++) {
639 if (add_instr
->operands
[i
].isConstant()) {
640 *offset
= add_instr
->operands
[i
].constantValue();
641 } else if (add_instr
->operands
[i
].isTemp() &&
642 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
643 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
647 if (!add_instr
->operands
[!i
].isTemp())
650 uint32_t offset2
= 0;
651 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
654 *base
= add_instr
->operands
[!i
].getTemp();
662 Operand
get_constant_op(opt_ctx
&ctx
, uint32_t val
, bool is64bit
= false)
664 // TODO: this functions shouldn't be needed if we store Operand instead of value.
665 Operand
op(val
, is64bit
);
666 if (val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
667 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
671 bool fixed_to_exec(Operand op
)
673 return op
.isFixed() && op
.physReg() == exec
;
676 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
678 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
679 ASSERTED
bool all_const
= false;
680 for (Operand
& op
: instr
->operands
)
681 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
682 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
685 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
687 if (!instr
->operands
[i
].isTemp())
690 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
691 /* propagate undef */
692 if (info
.is_undefined() && is_phi(instr
))
693 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
694 /* propagate reg->reg of same type */
695 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
696 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
697 info
= ctx
.info
[info
.temp
.id()];
700 /* SALU / PSEUDO: propagate inline constants */
701 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
702 const bool is_subdword
= std::any_of(instr
->definitions
.begin(), instr
->definitions
.end(),
703 [] (const Definition
& def
) { return def
.regClass().is_subdword();});
704 // TODO: optimize SGPR and constant propagation for subdword pseudo instructions on gfx9+
708 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
709 instr
->operands
[i
].setTemp(info
.temp
);
710 info
= ctx
.info
[info
.temp
.id()];
711 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
712 /* propagate vgpr if it can take it */
713 switch (instr
->opcode
) {
714 case aco_opcode::p_create_vector
:
715 case aco_opcode::p_split_vector
:
716 case aco_opcode::p_extract_vector
:
717 case aco_opcode::p_phi
: {
718 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
719 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
721 instr
->operands
[i
] = Operand(info
.temp
);
722 info
= ctx
.info
[info
.temp
.id()];
730 if ((info
.is_constant() || info
.is_constant_64bit() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) &&
731 !instr
->operands
[i
].isFixed() && alu_can_accept_constant(instr
->opcode
, i
)) {
732 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
737 /* VALU: propagate neg, abs & inline constants */
738 else if (instr
->isVALU()) {
739 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
740 instr
->operands
[i
].setTemp(info
.temp
);
741 info
= ctx
.info
[info
.temp
.id()];
743 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
746 instr
->operands
[i
] = Operand(info
.temp
);
748 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
750 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
752 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
753 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
754 instr
->operands
[i
].setTemp(info
.temp
);
756 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
759 instr
->operands
[i
].setTemp(info
.temp
);
761 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
763 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
766 if ((info
.is_constant() || info
.is_constant_64bit()) && alu_can_accept_constant(instr
->opcode
, i
)) {
767 Operand op
= get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
768 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
769 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
770 instr
->operands
[i
] = op
;
772 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
773 instr
->operands
[i
] = instr
->operands
[0];
774 instr
->operands
[0] = op
;
776 } else if (can_use_VOP3(ctx
, instr
)) {
778 instr
->operands
[i
] = op
;
784 /* MUBUF: propagate constants and combine additions */
785 else if (instr
->format
== Format::MUBUF
) {
786 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
789 while (info
.is_temp())
790 info
= ctx
.info
[info
.temp
.id()];
792 if (mubuf
->offen
&& i
== 1 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
793 assert(!mubuf
->idxen
);
794 instr
->operands
[1] = Operand(v1
);
795 mubuf
->offset
+= info
.val
;
796 mubuf
->offen
= false;
798 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
799 instr
->operands
[2] = Operand((uint32_t) 0);
800 mubuf
->offset
+= info
.val
;
802 } else if (mubuf
->offen
&& i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
803 assert(!mubuf
->idxen
);
804 instr
->operands
[1].setTemp(base
);
805 mubuf
->offset
+= offset
;
807 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
808 instr
->operands
[i
].setTemp(base
);
809 mubuf
->offset
+= offset
;
814 /* DS: combine additions */
815 else if (instr
->format
== Format::DS
) {
817 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
820 bool has_usable_ds_offset
= ctx
.program
->chip_class
>= GFX7
;
821 if (has_usable_ds_offset
&&
822 i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) &&
823 base
.regClass() == instr
->operands
[i
].regClass() &&
824 instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
825 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
826 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
827 unsigned mask
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 0x7 : 0x3;
828 unsigned shifts
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 3 : 2;
830 if ((offset
& mask
) == 0 &&
831 ds
->offset0
+ (offset
>> shifts
) <= 255 &&
832 ds
->offset1
+ (offset
>> shifts
) <= 255) {
833 instr
->operands
[i
].setTemp(base
);
834 ds
->offset0
+= offset
>> shifts
;
835 ds
->offset1
+= offset
>> shifts
;
838 if (ds
->offset0
+ offset
<= 65535) {
839 instr
->operands
[i
].setTemp(base
);
840 ds
->offset0
+= offset
;
846 /* SMEM: propagate constants and combine additions */
847 else if (instr
->format
== Format::SMEM
) {
849 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
852 if (i
== 1 && info
.is_constant_or_literal() &&
853 ((ctx
.program
->chip_class
== GFX6
&& info
.val
<= 0x3FF) ||
854 (ctx
.program
->chip_class
== GFX7
&& info
.val
<= 0xFFFFFFFF) ||
855 (ctx
.program
->chip_class
>= GFX8
&& info
.val
<= 0xFFFFF))) {
856 instr
->operands
[i
] = Operand(info
.val
);
858 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
859 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
861 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
862 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
866 smem
->operands
[1] = Operand(offset
);
867 smem
->operands
.back() = Operand(base
);
869 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
870 new_instr
->operands
[0] = smem
->operands
[0];
871 new_instr
->operands
[1] = Operand(offset
);
872 if (smem
->definitions
.empty())
873 new_instr
->operands
[2] = smem
->operands
[2];
874 new_instr
->operands
.back() = Operand(base
);
875 if (!smem
->definitions
.empty())
876 new_instr
->definitions
[0] = smem
->definitions
[0];
877 new_instr
->can_reorder
= smem
->can_reorder
;
878 new_instr
->barrier
= smem
->barrier
;
879 instr
.reset(new_instr
);
880 smem
= static_cast<SMEM_instruction
*>(instr
.get());
886 else if (instr
->format
== Format::PSEUDO_BRANCH
) {
887 if (ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
888 /* Flip the branch instruction to get rid of the scc_invert instruction */
889 instr
->opcode
= instr
->opcode
== aco_opcode::p_cbranch_z
? aco_opcode::p_cbranch_nz
: aco_opcode::p_cbranch_z
;
890 instr
->operands
[0].setTemp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
895 /* if this instruction doesn't define anything, return */
896 if (instr
->definitions
.empty())
899 switch (instr
->opcode
) {
900 case aco_opcode::p_create_vector
: {
901 unsigned num_ops
= instr
->operands
.size();
902 for (const Operand
& op
: instr
->operands
) {
903 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
904 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
906 if (num_ops
!= instr
->operands
.size()) {
907 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
908 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
909 instr
->definitions
[0] = old_vec
->definitions
[0];
911 for (Operand
& old_op
: old_vec
->operands
) {
912 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
913 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
914 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
915 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
916 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
917 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
918 instr
->operands
[k
++] = op
;
921 instr
->operands
[k
++] = old_op
;
924 assert(k
== num_ops
);
926 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
927 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
928 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
929 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
932 case aco_opcode::p_split_vector
: {
933 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
935 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
936 if (instr
->definitions
.size() != vec
->operands
.size())
938 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
939 Operand vec_op
= vec
->operands
[i
];
940 if (vec_op
.isConstant()) {
941 if (vec_op
.isLiteral())
942 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
943 else if (vec_op
.size() == 1)
944 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
945 else if (vec_op
.size() == 2)
946 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant_64bit(vec_op
.constantValue());
948 assert(vec_op
.isTemp());
949 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
954 case aco_opcode::p_extract_vector
: { /* mov */
955 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
958 /* check if we index directly into a vector element */
959 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
960 const unsigned index
= instr
->operands
[1].constantValue();
961 const unsigned dst_offset
= index
* instr
->definitions
[0].bytes();
964 for (const Operand
& op
: vec
->operands
) {
965 if (offset
< dst_offset
) {
966 offset
+= op
.bytes();
968 } else if (offset
!= dst_offset
|| op
.bytes() != instr
->definitions
[0].bytes()) {
972 /* convert this extract into a copy instruction */
973 instr
->opcode
= aco_opcode::p_parallelcopy
;
974 instr
->operands
.pop_back();
975 instr
->operands
[0] = op
;
977 if (op
.isConstant()) {
979 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(op
.constantValue());
980 else if (op
.size() == 1)
981 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(op
.constantValue());
982 else if (op
.size() == 2)
983 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(op
.constantValue());
986 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(op
.getTemp());
992 case aco_opcode::s_mov_b32
: /* propagate */
993 case aco_opcode::s_mov_b64
:
994 case aco_opcode::v_mov_b32
:
995 case aco_opcode::p_as_uniform
:
996 if (instr
->definitions
[0].isFixed()) {
997 /* don't copy-propagate copies into fixed registers */
998 } else if (instr
->usesModifiers()) {
1000 } else if (instr
->operands
[0].isConstant()) {
1001 if (instr
->operands
[0].isLiteral())
1002 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
1003 else if (instr
->operands
[0].size() == 1)
1004 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
1005 else if (instr
->operands
[0].size() == 2)
1006 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(instr
->operands
[0].constantValue());
1007 } else if (instr
->operands
[0].isTemp()) {
1008 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1010 assert(instr
->operands
[0].isFixed());
1013 case aco_opcode::p_is_helper
:
1014 if (!ctx
.program
->needs_wqm
)
1015 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
1017 case aco_opcode::s_movk_i32
: {
1018 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
1019 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
1020 if (v
<= 64 || v
>= 0xfffffff0)
1021 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1023 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1026 case aco_opcode::v_bfrev_b32
:
1027 case aco_opcode::s_brev_b32
: {
1028 if (instr
->operands
[0].isConstant()) {
1029 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
1030 if (v
<= 64 || v
>= 0xfffffff0)
1031 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1033 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1037 case aco_opcode::s_bfm_b32
: {
1038 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
1039 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
1040 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
1041 uint32_t v
= ((1u << size
) - 1u) << start
;
1042 if (v
<= 64 || v
>= 0xfffffff0)
1043 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1045 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1048 case aco_opcode::v_mul_f32
: { /* omod */
1049 /* TODO: try to move the negate/abs modifier to the consumer instead */
1050 if (instr
->usesModifiers())
1053 for (unsigned i
= 0; i
< 2; i
++) {
1054 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
1055 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
1056 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
1057 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
1058 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
1059 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
1060 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
1061 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000 &&
1062 !block
.fp_mode
.must_flush_denorms32
) { /* 1.0 */
1063 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
1072 case aco_opcode::v_and_b32
: /* abs */
1073 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x7FFFFFFF) &&
1074 instr
->operands
[1].isTemp() && instr
->operands
[1].getTemp().type() == RegType::vgpr
)
1075 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
1077 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1079 case aco_opcode::v_xor_b32
: { /* neg */
1080 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
1081 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
1082 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1083 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
1084 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
1085 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1086 instr
->opcode
= aco_opcode::v_or_b32
;
1087 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
1089 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
1093 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1097 case aco_opcode::v_med3_f32
: { /* clamp */
1098 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1099 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1100 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1101 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1105 bool found_zero
= false, found_one
= false;
1106 for (unsigned i
= 0; i
< 3; i
++)
1108 if (instr
->operands
[i
].constantEquals(0))
1110 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1115 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1116 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1120 case aco_opcode::v_cndmask_b32
:
1121 if (instr
->operands
[0].constantEquals(0) &&
1122 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
1123 instr
->operands
[2].isTemp())
1124 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1125 else if (instr
->operands
[0].constantEquals(0) &&
1126 instr
->operands
[1].constantEquals(0x3f800000u
) &&
1127 instr
->operands
[2].isTemp())
1128 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1130 ctx
.info
[instr
->operands
[2].tempId()].set_vcc_hint();
1132 case aco_opcode::v_cmp_lg_u32
:
1133 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1134 instr
->operands
[0].constantEquals(0) &&
1135 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1136 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1138 case aco_opcode::p_phi
:
1139 case aco_opcode::p_linear_phi
: {
1140 /* lower_bool_phis() can create phis like this */
1141 bool all_same_temp
= instr
->operands
[0].isTemp();
1142 /* this check is needed when moving uniform loop counters out of a divergent loop */
1144 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1145 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1146 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1147 all_same_temp
= false;
1149 if (all_same_temp
) {
1150 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1152 bool all_undef
= instr
->operands
[0].isUndefined();
1153 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1154 if (!instr
->operands
[i
].isUndefined())
1158 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1162 case aco_opcode::v_add_u32
:
1163 case aco_opcode::v_add_co_u32
:
1164 case aco_opcode::v_add_co_u32_e64
:
1165 case aco_opcode::s_add_i32
:
1166 case aco_opcode::s_add_u32
:
1167 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1169 case aco_opcode::s_not_b32
:
1170 case aco_opcode::s_not_b64
:
1171 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1172 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1173 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1174 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1175 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1176 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1178 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1180 case aco_opcode::s_and_b32
:
1181 case aco_opcode::s_and_b64
:
1182 if (fixed_to_exec(instr
->operands
[1]) && instr
->operands
[0].isTemp()) {
1183 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1184 /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
1185 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1186 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1188 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1189 /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
1190 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1191 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1196 case aco_opcode::s_or_b32
:
1197 case aco_opcode::s_or_b64
:
1198 case aco_opcode::s_xor_b32
:
1199 case aco_opcode::s_xor_b64
:
1200 if (std::all_of(instr
->operands
.begin(), instr
->operands
.end(), [&ctx
](const Operand
& op
) {
1201 return op
.isTemp() && (ctx
.info
[op
.tempId()].is_uniform_bool() || ctx
.info
[op
.tempId()].is_uniform_bitwise());
1203 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1206 case aco_opcode::s_lshl_b32
:
1207 case aco_opcode::v_or_b32
:
1208 case aco_opcode::v_lshlrev_b32
:
1209 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1211 case aco_opcode::v_min_f32
:
1212 case aco_opcode::v_min_f16
:
1213 case aco_opcode::v_min_u32
:
1214 case aco_opcode::v_min_i32
:
1215 case aco_opcode::v_min_u16
:
1216 case aco_opcode::v_min_i16
:
1217 case aco_opcode::v_max_f32
:
1218 case aco_opcode::v_max_f16
:
1219 case aco_opcode::v_max_u32
:
1220 case aco_opcode::v_max_i32
:
1221 case aco_opcode::v_max_u16
:
1222 case aco_opcode::v_max_i16
:
1223 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1225 case aco_opcode::v_cmp_lt_f32
:
1226 case aco_opcode::v_cmp_eq_f32
:
1227 case aco_opcode::v_cmp_le_f32
:
1228 case aco_opcode::v_cmp_gt_f32
:
1229 case aco_opcode::v_cmp_lg_f32
:
1230 case aco_opcode::v_cmp_ge_f32
:
1231 case aco_opcode::v_cmp_o_f32
:
1232 case aco_opcode::v_cmp_u_f32
:
1233 case aco_opcode::v_cmp_nge_f32
:
1234 case aco_opcode::v_cmp_nlg_f32
:
1235 case aco_opcode::v_cmp_ngt_f32
:
1236 case aco_opcode::v_cmp_nle_f32
:
1237 case aco_opcode::v_cmp_neq_f32
:
1238 case aco_opcode::v_cmp_nlt_f32
:
1239 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1241 case aco_opcode::s_cselect_b64
:
1242 case aco_opcode::s_cselect_b32
:
1243 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1244 instr
->operands
[1].constantEquals(0)) {
1245 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1246 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1248 if (instr
->operands
[2].isTemp() && ctx
.info
[instr
->operands
[2].tempId()].is_scc_invert()) {
1249 /* Flip the operands to get rid of the scc_invert instruction */
1250 std::swap(instr
->operands
[0], instr
->operands
[1]);
1251 instr
->operands
[2].setTemp(ctx
.info
[instr
->operands
[2].tempId()].temp
);
1254 case aco_opcode::p_wqm
:
1255 if (instr
->operands
[0].isTemp() &&
1256 ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1257 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1265 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1267 *ordered
= *unordered
= op
;
1269 #define CMP(ord, unord) \
1270 case aco_opcode::v_cmp_##ord##_f32:\
1271 case aco_opcode::v_cmp_n##unord##_f32:\
1272 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1273 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1274 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1288 aco_opcode
get_ordered(aco_opcode op
)
1290 aco_opcode ordered
, unordered
, inverse
;
1291 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1294 aco_opcode
get_unordered(aco_opcode op
)
1296 aco_opcode ordered
, unordered
, inverse
;
1297 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1300 aco_opcode
get_inverse(aco_opcode op
)
1302 aco_opcode ordered
, unordered
, inverse
;
1303 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1306 bool is_cmp(aco_opcode op
)
1308 aco_opcode ordered
, unordered
, inverse
;
1309 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1312 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1314 if (ctx
.info
[tmp
.id()].is_temp())
1315 return ctx
.info
[tmp
.id()].temp
.id();
1320 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1322 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1323 for (const Operand
& op
: instr
->operands
) {
1325 ctx
.uses
[op
.tempId()]--;
1330 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1332 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1334 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1337 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1339 if (instr
->definitions
.size() == 2) {
1340 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1341 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1348 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1349 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1350 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1352 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1354 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1357 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1359 bool neg
[2] = {false, false};
1360 bool abs
[2] = {false, false};
1362 Instruction
*op_instr
[2];
1365 for (unsigned i
= 0; i
< 2; i
++) {
1366 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1370 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1372 if (op_instr
[i
]->opcode
!= expected_cmp
)
1374 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1377 if (op_instr
[i
]->isVOP3()) {
1378 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1379 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1381 neg
[i
] = vop3
->neg
[0];
1382 abs
[i
] = vop3
->abs
[0];
1383 opsel
|= (vop3
->opsel
& 1) << i
;
1386 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1387 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1388 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1394 if (op
[1].type() == RegType::sgpr
)
1395 std::swap(op
[0], op
[1]);
1396 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1397 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1400 ctx
.uses
[op
[0].id()]++;
1401 ctx
.uses
[op
[1].id()]++;
1402 decrease_uses(ctx
, op_instr
[0]);
1403 decrease_uses(ctx
, op_instr
[1]);
1405 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1406 Instruction
*new_instr
;
1407 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1408 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1409 for (unsigned i
= 0; i
< 2; i
++) {
1410 vop3
->neg
[i
] = neg
[i
];
1411 vop3
->abs
[i
] = abs
[i
];
1413 vop3
->opsel
= opsel
;
1414 new_instr
= static_cast<Instruction
*>(vop3
);
1416 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1418 new_instr
->operands
[0] = Operand(op
[0]);
1419 new_instr
->operands
[1] = Operand(op
[1]);
1420 new_instr
->definitions
[0] = instr
->definitions
[0];
1422 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1423 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1425 instr
.reset(new_instr
);
1430 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1431 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1432 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1434 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1436 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1439 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1440 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1442 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1443 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1444 if (!nan_test
|| !cmp
)
1447 if (cmp
->opcode
== expected_nan_test
)
1448 std::swap(nan_test
, cmp
);
1449 else if (nan_test
->opcode
!= expected_nan_test
)
1452 if (!is_cmp(cmp
->opcode
))
1455 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1457 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1460 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1461 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1462 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1463 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1464 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1466 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1469 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1470 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1471 decrease_uses(ctx
, nan_test
);
1472 decrease_uses(ctx
, cmp
);
1474 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1475 Instruction
*new_instr
;
1476 if (cmp
->isVOP3()) {
1477 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1478 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1479 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1480 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1481 new_vop3
->clamp
= cmp_vop3
->clamp
;
1482 new_vop3
->omod
= cmp_vop3
->omod
;
1483 new_vop3
->opsel
= cmp_vop3
->opsel
;
1484 new_instr
= new_vop3
;
1486 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1488 new_instr
->operands
[0] = cmp
->operands
[0];
1489 new_instr
->operands
[1] = cmp
->operands
[1];
1490 new_instr
->definitions
[0] = instr
->definitions
[0];
1492 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1493 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1495 instr
.reset(new_instr
);
1500 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1501 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1502 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1504 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1506 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1509 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1511 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1512 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1514 if (!nan_test
|| !cmp
)
1517 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1518 if (cmp
->opcode
== expected_nan_test
)
1519 std::swap(nan_test
, cmp
);
1520 else if (nan_test
->opcode
!= expected_nan_test
)
1523 if (!is_cmp(cmp
->opcode
))
1526 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1528 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1531 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1532 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1533 if (prop_nan0
!= prop_nan1
)
1536 if (nan_test
->isVOP3()) {
1537 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1538 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1542 int constant_operand
= -1;
1543 for (unsigned i
= 0; i
< 2; i
++) {
1544 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1545 constant_operand
= !i
;
1549 if (constant_operand
== -1)
1553 if (cmp
->operands
[constant_operand
].isConstant()) {
1554 constant
= cmp
->operands
[constant_operand
].constantValue();
1555 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1556 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1557 unsigned id
= original_temp_id(ctx
, tmp
);
1558 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1560 constant
= ctx
.info
[id
].val
;
1566 memcpy(&constantf
, &constant
, 4);
1567 if (isnan(constantf
))
1570 if (cmp
->operands
[0].isTemp())
1571 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1572 if (cmp
->operands
[1].isTemp())
1573 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1574 decrease_uses(ctx
, nan_test
);
1575 decrease_uses(ctx
, cmp
);
1577 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1578 Instruction
*new_instr
;
1579 if (cmp
->isVOP3()) {
1580 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1581 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1582 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1583 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1584 new_vop3
->clamp
= cmp_vop3
->clamp
;
1585 new_vop3
->omod
= cmp_vop3
->omod
;
1586 new_vop3
->opsel
= cmp_vop3
->opsel
;
1587 new_instr
= new_vop3
;
1589 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1591 new_instr
->operands
[0] = cmp
->operands
[0];
1592 new_instr
->operands
[1] = cmp
->operands
[1];
1593 new_instr
->definitions
[0] = instr
->definitions
[0];
1595 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1596 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1598 instr
.reset(new_instr
);
1603 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1604 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1606 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1608 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1610 if (!instr
->operands
[0].isTemp())
1613 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1617 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1618 if (new_opcode
== aco_opcode::last_opcode
)
1621 if (cmp
->operands
[0].isTemp())
1622 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1623 if (cmp
->operands
[1].isTemp())
1624 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1625 decrease_uses(ctx
, cmp
);
1627 Instruction
*new_instr
;
1628 if (cmp
->isVOP3()) {
1629 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1630 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1631 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1632 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1633 new_vop3
->clamp
= cmp_vop3
->clamp
;
1634 new_vop3
->omod
= cmp_vop3
->omod
;
1635 new_vop3
->opsel
= cmp_vop3
->opsel
;
1636 new_instr
= new_vop3
;
1638 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1640 new_instr
->operands
[0] = cmp
->operands
[0];
1641 new_instr
->operands
[1] = cmp
->operands
[1];
1642 new_instr
->definitions
[0] = instr
->definitions
[0];
1644 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1645 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1647 instr
.reset(new_instr
);
1652 /* op1(op2(1, 2), 0) if swap = false
1653 * op1(0, op2(1, 2)) if swap = true */
1654 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1655 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1656 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1657 bool *op1_clamp
, uint8_t *op1_omod
,
1658 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1661 if (op1_instr
->opcode
!= op1
)
1664 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1665 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1667 if (fixed_to_exec(op2_instr
->operands
[0]) || fixed_to_exec(op2_instr
->operands
[1]))
1670 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1671 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1673 /* don't support inbetween clamp/omod */
1674 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1677 /* get operands and modifiers and check inbetween modifiers */
1678 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1679 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1682 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1683 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1687 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1688 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1691 if (inbetween_opsel
)
1692 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1693 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1697 shuffle
[shuffle_str
[0] - '0'] = 0;
1698 shuffle
[shuffle_str
[1] - '0'] = 1;
1699 shuffle
[shuffle_str
[2] - '0'] = 2;
1701 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1702 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1703 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1704 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1705 *opsel
|= 1 << shuffle
[0];
1707 for (unsigned i
= 0; i
< 2; i
++) {
1708 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1709 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1710 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1711 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1712 *opsel
|= 1 << shuffle
[i
+ 1];
1715 /* check operands */
1716 if (!check_vop3_operands(ctx
, 3, operands
))
1722 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1723 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1724 bool clamp
, unsigned omod
)
1726 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1727 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1728 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1729 new_instr
->clamp
= clamp
;
1730 new_instr
->omod
= omod
;
1731 new_instr
->opsel
= opsel
;
1732 new_instr
->operands
[0] = operands
[0];
1733 new_instr
->operands
[1] = operands
[1];
1734 new_instr
->operands
[2] = operands
[2];
1735 new_instr
->definitions
[0] = instr
->definitions
[0];
1736 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1738 instr
.reset(new_instr
);
1741 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1743 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1744 (label_omod_success
| label_clamp_success
);
1746 for (unsigned swap
= 0; swap
< 2; swap
++) {
1747 if (!((1 << swap
) & ops
))
1750 Operand operands
[3];
1751 bool neg
[3], abs
[3], clamp
;
1752 uint8_t opsel
= 0, omod
= 0;
1753 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1754 instr
.get(), swap
, shuffle
,
1755 operands
, neg
, abs
, &opsel
,
1756 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1757 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1758 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1759 if (omod_clamp
& label_omod_success
)
1760 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1761 if (omod_clamp
& label_clamp_success
)
1762 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1769 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
1771 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
1774 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1775 (label_omod_success
| label_clamp_success
);
1777 /* min(-max(a, b), c) -> min3(-a, -b, c) *
1778 * max(-min(a, b), c) -> max3(-a, -b, c) */
1779 for (unsigned swap
= 0; swap
< 2; swap
++) {
1780 Operand operands
[3];
1781 bool neg
[3], abs
[3], clamp
;
1782 uint8_t opsel
= 0, omod
= 0;
1784 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
1785 instr
.get(), swap
, "012",
1786 operands
, neg
, abs
, &opsel
,
1787 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
1789 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1792 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1793 if (omod_clamp
& label_omod_success
)
1794 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1795 if (omod_clamp
& label_clamp_success
)
1796 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1803 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1804 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1805 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1806 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1807 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1808 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1809 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1812 if (!instr
->operands
[0].isTemp())
1814 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1817 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1820 switch (op2_instr
->opcode
) {
1821 case aco_opcode::s_and_b32
:
1822 case aco_opcode::s_or_b32
:
1823 case aco_opcode::s_xor_b32
:
1824 case aco_opcode::s_and_b64
:
1825 case aco_opcode::s_or_b64
:
1826 case aco_opcode::s_xor_b64
:
1832 /* create instruction */
1833 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1834 std::swap(instr
->definitions
[1], op2_instr
->definitions
[1]);
1835 ctx
.uses
[instr
->operands
[0].tempId()]--;
1836 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1838 switch (op2_instr
->opcode
) {
1839 case aco_opcode::s_and_b32
:
1840 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1842 case aco_opcode::s_or_b32
:
1843 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1845 case aco_opcode::s_xor_b32
:
1846 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1848 case aco_opcode::s_and_b64
:
1849 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1851 case aco_opcode::s_or_b64
:
1852 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1854 case aco_opcode::s_xor_b64
:
1855 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1864 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1865 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1866 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1867 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1868 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1870 if (instr
->definitions
[0].isTemp() && ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bool())
1873 for (unsigned i
= 0; i
< 2; i
++) {
1874 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1875 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1877 if (ctx
.uses
[op2_instr
->definitions
[1].tempId()] || fixed_to_exec(op2_instr
->operands
[0]))
1880 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1881 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1884 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1885 instr
->operands
[0] = instr
->operands
[!i
];
1886 instr
->operands
[1] = op2_instr
->operands
[0];
1887 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1889 switch (instr
->opcode
) {
1890 case aco_opcode::s_and_b32
:
1891 instr
->opcode
= aco_opcode::s_andn2_b32
;
1893 case aco_opcode::s_or_b32
:
1894 instr
->opcode
= aco_opcode::s_orn2_b32
;
1896 case aco_opcode::s_and_b64
:
1897 instr
->opcode
= aco_opcode::s_andn2_b64
;
1899 case aco_opcode::s_or_b64
:
1900 instr
->opcode
= aco_opcode::s_orn2_b64
;
1911 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1912 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1914 if (instr
->opcode
== aco_opcode::s_add_i32
&& ctx
.uses
[instr
->definitions
[1].tempId()])
1917 for (unsigned i
= 0; i
< 2; i
++) {
1918 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1919 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
||
1920 ctx
.uses
[op2_instr
->definitions
[1].tempId()])
1922 if (!op2_instr
->operands
[1].isConstant() || fixed_to_exec(op2_instr
->operands
[0]))
1925 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1926 if (shift
< 1 || shift
> 4)
1929 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1930 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1933 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1934 instr
->operands
[1] = instr
->operands
[!i
];
1935 instr
->operands
[0] = op2_instr
->operands
[0];
1936 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1938 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1939 aco_opcode::s_lshl2_add_u32
,
1940 aco_opcode::s_lshl3_add_u32
,
1941 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1948 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1951 #define MINMAX(type, gfx9) \
1952 case aco_opcode::v_min_##type:\
1953 case aco_opcode::v_max_##type:\
1954 case aco_opcode::v_med3_##type:\
1955 *min = aco_opcode::v_min_##type;\
1956 *max = aco_opcode::v_max_##type;\
1957 *med3 = aco_opcode::v_med3_##type;\
1958 *min3 = aco_opcode::v_min3_##type;\
1959 *max3 = aco_opcode::v_max3_##type;\
1960 *some_gfx9_only = gfx9;\
1974 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1975 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1976 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1977 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1979 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
1980 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
1981 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
1982 aco_opcode other_op
;
1983 if (instr
->opcode
== min
)
1985 else if (instr
->opcode
== max
)
1990 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1991 (label_omod_success
| label_clamp_success
);
1993 for (unsigned swap
= 0; swap
< 2; swap
++) {
1994 Operand operands
[3];
1995 bool neg
[3], abs
[3], clamp
;
1996 uint8_t opsel
= 0, omod
= 0;
1997 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1998 "012", operands
, neg
, abs
, &opsel
,
1999 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
2000 int const0_idx
= -1, const1_idx
= -1;
2001 uint32_t const0
= 0, const1
= 0;
2002 for (int i
= 0; i
< 3; i
++) {
2004 if (operands
[i
].isConstant()) {
2005 val
= operands
[i
].constantValue();
2006 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
2007 val
= ctx
.info
[operands
[i
].tempId()].val
;
2011 if (const0_idx
>= 0) {
2019 if (const0_idx
< 0 || const1_idx
< 0)
2022 if (opsel
& (1 << const0_idx
))
2024 if (opsel
& (1 << const1_idx
))
2027 int lower_idx
= const0_idx
;
2029 case aco_opcode::v_min_f32
:
2030 case aco_opcode::v_min_f16
: {
2031 float const0_f
, const1_f
;
2032 if (min
== aco_opcode::v_min_f32
) {
2033 memcpy(&const0_f
, &const0
, 4);
2034 memcpy(&const1_f
, &const1
, 4);
2036 const0_f
= _mesa_half_to_float(const0
);
2037 const1_f
= _mesa_half_to_float(const1
);
2039 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
2040 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
2041 if (neg
[const0_idx
]) const0_f
= -const0_f
;
2042 if (neg
[const1_idx
]) const1_f
= -const1_f
;
2043 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
2046 case aco_opcode::v_min_u32
: {
2047 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
2050 case aco_opcode::v_min_u16
: {
2051 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
2054 case aco_opcode::v_min_i32
: {
2055 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
2056 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
2057 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2060 case aco_opcode::v_min_i16
: {
2061 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
2062 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
2063 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2069 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
2071 if (instr
->opcode
== min
) {
2072 if (upper_idx
!= 0 || lower_idx
== 0)
2075 if (upper_idx
== 0 || lower_idx
!= 0)
2079 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2080 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2081 if (omod_clamp
& label_omod_success
)
2082 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2083 if (omod_clamp
& label_clamp_success
)
2084 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2094 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2096 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2097 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2098 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2100 /* find candidates and create the set of sgprs already read */
2101 unsigned sgpr_ids
[2] = {0, 0};
2102 uint32_t operand_mask
= 0;
2103 bool has_literal
= false;
2104 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2105 if (instr
->operands
[i
].isLiteral())
2107 if (!instr
->operands
[i
].isTemp())
2109 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2110 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
2111 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
2113 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
2114 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
2115 operand_mask
|= 1u << i
;
2117 unsigned max_sgprs
= 1;
2118 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2123 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2125 /* keep on applying sgprs until there is nothing left to be done */
2126 while (operand_mask
) {
2127 uint32_t sgpr_idx
= 0;
2128 uint32_t sgpr_info_id
= 0;
2129 uint32_t mask
= operand_mask
;
2132 unsigned i
= u_bit_scan(&mask
);
2133 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2134 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
2136 sgpr_info_id
= instr
->operands
[i
].tempId();
2139 operand_mask
&= ~(1u << sgpr_idx
);
2141 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2142 * definitively beneficial.
2143 * TODO: this is too conservative because later the use count could be reduced to 1 */
2144 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2147 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2148 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2149 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2152 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2153 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2154 } else if (can_swap_operands(instr
)) {
2155 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2156 instr
->operands
[0] = Operand(sgpr
);
2157 /* swap bits using a 4-entry LUT */
2158 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2159 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2160 } else if (can_use_VOP3(ctx
, instr
)) {
2161 to_VOP3(ctx
, instr
);
2162 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2168 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2169 ctx
.uses
[sgpr_info_id
]--;
2170 ctx
.uses
[sgpr
.id()]++;
2174 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2176 /* check if we could apply omod on predecessor */
2177 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
2178 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2179 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2181 unsigned idx
= op0
? 0 : 1;
2182 /* omod was successfully applied */
2183 /* if the omod instruction is v_mad, we also have to change the original add */
2184 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2185 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2186 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2187 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2188 add_instr
->definitions
[0] = instr
->definitions
[0];
2191 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2192 /* check if we have an additional clamp modifier */
2193 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2194 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2195 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2196 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2198 /* change definition ssa-id of modified instruction */
2199 omod_instr
->definitions
[0] = instr
->definitions
[0];
2201 /* change the definition of instr to something unused, e.g. the original omod def */
2202 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2203 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2206 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2207 /* in all other cases, label this instruction as option for multiply-add */
2208 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2212 /* check if we could apply clamp on predecessor */
2213 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
2215 bool found_zero
= false, found_one
= false;
2216 for (unsigned i
= 0; i
< 3; i
++)
2218 if (instr
->operands
[i
].constantEquals(0))
2220 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
2225 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2226 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2227 /* clamp was successfully applied */
2228 /* if the clamp instruction is v_mad, we also have to change the original add */
2229 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2230 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2231 add_instr
->definitions
[0] = instr
->definitions
[0];
2233 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2234 /* change definition ssa-id of modified instruction */
2235 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2237 /* change the definition of instr to something unused, e.g. the original omod def */
2238 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2239 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2244 /* omod has no effect if denormals are enabled */
2245 bool can_use_omod
= block
.fp_mode
.denorm32
== 0;
2247 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2248 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2249 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2250 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2251 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2252 to_VOP3(ctx
, instr
);
2253 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2254 def_info
.set_omod_success(instr
.get());
2255 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2256 to_VOP3(ctx
, instr
);
2257 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2258 def_info
.set_omod_success(instr
.get());
2259 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2260 to_VOP3(ctx
, instr
);
2261 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2262 def_info
.set_omod_success(instr
.get());
2263 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2264 to_VOP3(ctx
, instr
);
2265 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2266 def_info
.set_clamp_success(instr
.get());
2273 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2274 // this would mean that we'd have to fix the instruction uses while value propagation
2276 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2278 if (instr
->definitions
.empty() || is_dead(ctx
.uses
, instr
.get()))
2281 if (instr
->isVALU()) {
2282 if (can_apply_sgprs(instr
))
2283 apply_sgprs(ctx
, instr
);
2284 if (apply_omod_clamp(ctx
, block
, instr
))
2288 if (ctx
.info
[instr
->definitions
[0].tempId()].is_vcc_hint()) {
2289 instr
->definitions
[0].setHint(vcc
);
2292 /* TODO: There are still some peephole optimizations that could be done:
2293 * - abs(a - b) -> s_absdiff_i32
2294 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2295 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2296 * These aren't probably too interesting though.
2297 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2298 * probably more useful than the previously mentioned optimizations.
2299 * The various comparison optimizations also currently only work with 32-bit
2302 /* neg(mul(a, b)) -> mul(neg(a), b) */
2303 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2304 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2306 if (!ctx
.info
[val
.id()].is_mul())
2309 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2311 if (mul_instr
->operands
[0].isLiteral())
2313 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2316 /* convert to mul(neg(a), b) */
2317 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2318 Definition def
= instr
->definitions
[0];
2319 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2320 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2321 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2322 instr
->operands
[0] = mul_instr
->operands
[0];
2323 instr
->operands
[1] = mul_instr
->operands
[1];
2324 instr
->definitions
[0] = def
;
2325 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2326 if (mul_instr
->isVOP3()) {
2327 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2328 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2329 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2330 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2331 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2332 new_mul
->omod
= mul
->omod
;
2334 new_mul
->neg
[0] ^= true;
2335 new_mul
->clamp
= false;
2337 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2340 /* combine mul+add -> mad */
2341 else if ((instr
->opcode
== aco_opcode::v_add_f32
||
2342 instr
->opcode
== aco_opcode::v_sub_f32
||
2343 instr
->opcode
== aco_opcode::v_subrev_f32
) &&
2344 block
.fp_mode
.denorm32
== 0 && !block
.fp_mode
.preserve_signed_zero_inf_nan32
) {
2345 //TODO: we could use fma instead when denormals are enabled if the NIR isn't marked as precise
2347 uint32_t uses_src0
= UINT32_MAX
;
2348 uint32_t uses_src1
= UINT32_MAX
;
2349 Instruction
* mul_instr
= nullptr;
2350 unsigned add_op_idx
;
2351 /* check if any of the operands is a multiplication */
2352 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2353 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2354 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2355 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2357 /* find the 'best' mul instruction to combine with the add */
2358 if (uses_src0
< uses_src1
) {
2359 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2361 } else if (uses_src1
< uses_src0
) {
2362 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2364 } else if (uses_src0
!= UINT32_MAX
) {
2365 /* tiebreaker: quite random what to pick */
2366 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2367 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2370 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2375 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2376 bool neg
[3] = {false, false, false};
2377 bool abs
[3] = {false, false, false};
2380 op
[0] = mul_instr
->operands
[0];
2381 op
[1] = mul_instr
->operands
[1];
2382 op
[2] = instr
->operands
[add_op_idx
];
2383 // TODO: would be better to check this before selecting a mul instr?
2384 if (!check_vop3_operands(ctx
, 3, op
))
2387 if (mul_instr
->isVOP3()) {
2388 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2389 neg
[0] = vop3
->neg
[0];
2390 neg
[1] = vop3
->neg
[1];
2391 abs
[0] = vop3
->abs
[0];
2392 abs
[1] = vop3
->abs
[1];
2393 /* we cannot use these modifiers between mul and add */
2394 if (vop3
->clamp
|| vop3
->omod
)
2398 /* convert to mad */
2399 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2400 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2402 ctx
.uses
[op
[0].tempId()]++;
2404 ctx
.uses
[op
[1].tempId()]++;
2407 if (instr
->isVOP3()) {
2408 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2409 neg
[2] = vop3
->neg
[add_op_idx
];
2410 abs
[2] = vop3
->abs
[add_op_idx
];
2412 clamp
= vop3
->clamp
;
2413 /* abs of the multiplication result */
2414 if (vop3
->abs
[1 - add_op_idx
]) {
2420 /* neg of the multiplication result */
2421 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2423 if (instr
->opcode
== aco_opcode::v_sub_f32
)
2424 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2425 else if (instr
->opcode
== aco_opcode::v_subrev_f32
)
2426 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2428 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2429 for (unsigned i
= 0; i
< 3; i
++)
2431 mad
->operands
[i
] = op
[i
];
2432 mad
->neg
[i
] = neg
[i
];
2433 mad
->abs
[i
] = abs
[i
];
2437 mad
->definitions
[0] = instr
->definitions
[0];
2439 /* mark this ssa_def to be re-checked for profitability and literals */
2440 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2441 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2442 instr
.reset(mad
.release());
2446 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2447 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2448 for (unsigned i
= 0; i
< 2; i
++) {
2449 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2450 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2451 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2452 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2453 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2455 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2456 new_instr
->operands
[0] = Operand(0u);
2457 new_instr
->operands
[1] = instr
->operands
[!i
];
2458 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2459 new_instr
->definitions
[0] = instr
->definitions
[0];
2460 instr
.reset(new_instr
.release());
2461 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2465 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2466 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2467 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2468 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2469 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2470 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2471 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2472 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2473 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2474 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2475 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2476 combine_salu_lshl_add(ctx
, instr
);
2477 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2478 combine_salu_not_bitwise(ctx
, instr
);
2479 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2480 if (combine_inverse_comparison(ctx
, instr
)) ;
2481 else combine_salu_not_bitwise(ctx
, instr
);
2482 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2483 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2484 if (combine_ordering_test(ctx
, instr
)) ;
2485 else if (combine_comparison_ordering(ctx
, instr
)) ;
2486 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2487 else combine_salu_n2(ctx
, instr
);
2489 aco_opcode min
, max
, min3
, max3
, med3
;
2490 bool some_gfx9_only
;
2491 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2492 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2493 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2494 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2499 bool to_uniform_bool_instr(opt_ctx
&ctx
, aco_ptr
<Instruction
> &instr
)
2501 switch (instr
->opcode
) {
2502 case aco_opcode::s_and_b32
:
2503 case aco_opcode::s_and_b64
:
2504 instr
->opcode
= aco_opcode::s_and_b32
;
2506 case aco_opcode::s_or_b32
:
2507 case aco_opcode::s_or_b64
:
2508 instr
->opcode
= aco_opcode::s_or_b32
;
2510 case aco_opcode::s_xor_b32
:
2511 case aco_opcode::s_xor_b64
:
2512 instr
->opcode
= aco_opcode::s_absdiff_i32
;
2515 /* Don't transform other instructions. They are very unlikely to appear here. */
2519 for (Operand
&op
: instr
->operands
) {
2520 ctx
.uses
[op
.tempId()]--;
2522 if (ctx
.info
[op
.tempId()].is_uniform_bool()) {
2523 /* Just use the uniform boolean temp. */
2524 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
2525 } else if (ctx
.info
[op
.tempId()].is_uniform_bitwise()) {
2526 /* Use the SCC definition of the predecessor instruction.
2527 * This allows the predecessor to get picked up by the same optimization (if it has no divergent users),
2528 * and it also makes sure that the current instruction will keep working even if the predecessor won't be transformed.
2530 Instruction
*pred_instr
= ctx
.info
[op
.tempId()].instr
;
2531 assert(pred_instr
->definitions
.size() >= 2);
2532 assert(pred_instr
->definitions
[1].isFixed() && pred_instr
->definitions
[1].physReg() == scc
);
2533 op
.setTemp(pred_instr
->definitions
[1].getTemp());
2535 unreachable("Invalid operand on uniform bitwise instruction.");
2538 ctx
.uses
[op
.tempId()]++;
2541 instr
->definitions
[0].setTemp(Temp(instr
->definitions
[0].tempId(), s1
));
2542 assert(instr
->operands
[0].regClass() == s1
);
2543 assert(instr
->operands
[1].regClass() == s1
);
2547 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2549 const uint32_t threshold
= 4;
2551 if (is_dead(ctx
.uses
, instr
.get())) {
2556 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2557 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2558 unsigned num_used
= 0;
2560 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2561 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2567 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2568 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2569 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2573 for (Operand
& vec_op
: vec
->operands
) {
2574 if (off
== idx
* instr
->definitions
[0].size()) {
2578 off
+= vec_op
.size();
2580 if (off
!= instr
->operands
[0].size()) {
2581 ctx
.uses
[instr
->operands
[0].tempId()]--;
2582 for (Operand
& vec_op
: vec
->operands
) {
2583 if (vec_op
.isTemp())
2584 ctx
.uses
[vec_op
.tempId()]--;
2587 ctx
.uses
[op
.tempId()]++;
2589 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2590 extract
->operands
[0] = op
;
2591 extract
->definitions
[0] = instr
->definitions
[idx
];
2592 instr
.reset(extract
.release());
2598 if (!done
&& num_used
== 1) {
2599 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2600 extract
->operands
[0] = instr
->operands
[0];
2601 extract
->operands
[1] = Operand((uint32_t) idx
);
2602 extract
->definitions
[0] = instr
->definitions
[idx
];
2603 instr
.reset(extract
.release());
2607 mad_info
* mad_info
= NULL
;
2608 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2609 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2610 /* re-check mad instructions */
2611 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2612 ctx
.uses
[mad_info
->mul_temp_id
]++;
2613 if (instr
->operands
[0].isTemp())
2614 ctx
.uses
[instr
->operands
[0].tempId()]--;
2615 if (instr
->operands
[1].isTemp())
2616 ctx
.uses
[instr
->operands
[1].tempId()]--;
2617 instr
.swap(mad_info
->add_instr
);
2620 /* check literals */
2621 else if (!instr
->usesModifiers()) {
2622 bool sgpr_used
= false;
2623 uint32_t literal_idx
= 0;
2624 uint32_t literal_uses
= UINT32_MAX
;
2625 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2627 if (instr
->operands
[i
].isConstant() && i
> 0) {
2628 literal_uses
= UINT32_MAX
;
2631 if (!instr
->operands
[i
].isTemp())
2633 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2634 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2635 if (!sgpr_used
&& ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2636 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2639 literal_uses
= UINT32_MAX
;
2642 /* don't break because we still need to check constants */
2643 } else if (!sgpr_used
&&
2644 ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2645 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2646 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2651 /* Limit the number of literals to apply to not increase the code
2652 * size too much, but always apply literals for v_mad->v_madak
2653 * because both instructions are 64-bit and this doesn't increase
2655 * TODO: try to apply the literals earlier to lower the number of
2656 * uses below threshold
2658 if (literal_uses
< threshold
|| literal_idx
== 2) {
2659 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2660 mad_info
->check_literal
= true;
2661 mad_info
->literal_idx
= literal_idx
;
2667 /* Mark SCC needed, so the uniform boolean transformation won't swap the definitions when it isn't beneficial */
2668 if (instr
->format
== Format::PSEUDO_BRANCH
&&
2669 instr
->operands
.size() &&
2670 instr
->operands
[0].isTemp()) {
2671 ctx
.info
[instr
->operands
[0].tempId()].set_scc_needed();
2673 } else if ((instr
->opcode
== aco_opcode::s_cselect_b64
||
2674 instr
->opcode
== aco_opcode::s_cselect_b32
) &&
2675 instr
->operands
[2].isTemp()) {
2676 ctx
.info
[instr
->operands
[2].tempId()].set_scc_needed();
2679 /* check for literals */
2680 if (!instr
->isSALU() && !instr
->isVALU())
2683 /* Transform uniform bitwise boolean operations to 32-bit when there are no divergent uses. */
2684 if (instr
->definitions
.size() &&
2685 ctx
.uses
[instr
->definitions
[0].tempId()] == 0 &&
2686 ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bitwise()) {
2687 bool transform_done
= to_uniform_bool_instr(ctx
, instr
);
2689 if (transform_done
&& !ctx
.info
[instr
->definitions
[1].tempId()].is_scc_needed()) {
2690 /* Swap the two definition IDs in order to avoid overusing the SCC. This reduces extra moves generated by RA. */
2691 uint32_t def0_id
= instr
->definitions
[0].getTemp().id();
2692 uint32_t def1_id
= instr
->definitions
[1].getTemp().id();
2693 instr
->definitions
[0].setTemp(Temp(def1_id
, s1
));
2694 instr
->definitions
[1].setTemp(Temp(def0_id
, s1
));
2700 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
2701 return; /* some encodings can't ever take literals */
2703 /* we do not apply the literals yet as we don't know if it is profitable */
2704 Operand
current_literal(s1
);
2706 unsigned literal_id
= 0;
2707 unsigned literal_uses
= UINT32_MAX
;
2708 Operand
literal(s1
);
2709 unsigned num_operands
= 1;
2710 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
2711 num_operands
= instr
->operands
.size();
2712 /* catch VOP2 with a 3rd SGPR operand (e.g. v_cndmask_b32, v_addc_co_u32) */
2713 else if (instr
->isVALU() && instr
->operands
.size() >= 3)
2716 unsigned sgpr_ids
[2] = {0, 0};
2717 bool is_literal_sgpr
= false;
2720 /* choose a literal to apply */
2721 for (unsigned i
= 0; i
< num_operands
; i
++) {
2722 Operand op
= instr
->operands
[i
];
2724 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
2725 op
.tempId() != sgpr_ids
[0])
2726 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
2728 if (op
.isLiteral()) {
2729 current_literal
= op
;
2731 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal()) {
2735 if (!alu_can_accept_constant(instr
->opcode
, i
))
2738 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
2739 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
2741 literal
= Operand(ctx
.info
[op
.tempId()].val
);
2742 literal_uses
= ctx
.uses
[op
.tempId()];
2743 literal_id
= op
.tempId();
2746 mask
|= (op
.tempId() == literal_id
) << i
;
2750 /* don't go over the constant bus limit */
2751 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2752 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2753 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2754 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
2755 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2756 const_bus_limit
= 2;
2758 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2759 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
2762 if (literal_id
&& literal_uses
< threshold
&&
2763 (current_literal
.isUndefined() ||
2764 (current_literal
.size() == literal
.size() &&
2765 current_literal
.constantValue() == literal
.constantValue()))) {
2766 /* mark the literal to be applied */
2768 unsigned i
= u_bit_scan(&mask
);
2769 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
2770 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2776 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2778 /* Cleanup Dead Instructions */
2782 /* apply literals on MAD */
2783 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2784 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2785 if (info
->check_literal
&&
2786 (ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0 || info
->literal_idx
== 2)) {
2787 aco_ptr
<Instruction
> new_mad
;
2788 if (info
->literal_idx
== 2) { /* add literal -> madak */
2789 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2790 new_mad
->operands
[0] = instr
->operands
[0];
2791 new_mad
->operands
[1] = instr
->operands
[1];
2792 } else { /* mul literal -> madmk */
2793 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2794 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2795 new_mad
->operands
[1] = instr
->operands
[2];
2797 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2798 new_mad
->definitions
[0] = instr
->definitions
[0];
2799 ctx
.instructions
.emplace_back(std::move(new_mad
));
2804 /* apply literals on other SALU/VALU */
2805 if (instr
->isSALU() || instr
->isVALU()) {
2806 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2807 Operand op
= instr
->operands
[i
];
2808 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal() && ctx
.uses
[op
.tempId()] == 0) {
2809 Operand
literal(ctx
.info
[op
.tempId()].val
);
2810 if (instr
->isVALU() && i
> 0)
2811 to_VOP3(ctx
, instr
);
2812 instr
->operands
[i
] = literal
;
2817 ctx
.instructions
.emplace_back(std::move(instr
));
2821 void optimize(Program
* program
)
2824 ctx
.program
= program
;
2825 std::vector
<ssa_info
> info(program
->peekAllocationId());
2826 ctx
.info
= info
.data();
2828 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2829 for (Block
& block
: program
->blocks
) {
2830 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2831 label_instruction(ctx
, block
, instr
);
2834 ctx
.uses
= std::move(dead_code_analysis(program
));
2836 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2837 for (Block
& block
: program
->blocks
) {
2838 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2839 combine_instruction(ctx
, block
, instr
);
2842 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2843 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2844 Block
* block
= &(*it
);
2845 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2846 select_instruction(ctx
, *it
);
2849 /* 4. Add literals to instructions */
2850 for (Block
& block
: program
->blocks
) {
2851 ctx
.instructions
.clear();
2852 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2853 apply_literals(ctx
, instr
);
2854 block
.instructions
.swap(ctx
.instructions
);