2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
59 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
, bool vop3
)
60 : add_instr(std::move(instr
)), mul_temp_id(id
), needs_vop3(vop3
), check_literal(false) {}
65 label_constant
= 1 << 1,
70 label_literal
= 1 << 6,
74 label_omod5
= 1 << 10,
75 label_omod_success
= 1 << 11,
76 label_clamp
= 1 << 12,
77 label_clamp_success
= 1 << 13,
78 label_undefined
= 1 << 14,
81 label_add_sub
= 1 << 17,
82 label_bitwise
= 1 << 18,
83 label_minmax
= 1 << 19,
87 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
| label_add_sub
| label_bitwise
| label_minmax
| label_fcmp
;
88 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
;
89 static constexpr uint32_t val_labels
= label_constant
| label_literal
| label_mad
;
99 void add_label(Label new_label
)
101 /* Since all labels which use "instr" use it for the same thing
102 * (indicating the defining instruction), there is no need to clear
103 * any other instr labels. */
104 if (new_label
& instr_labels
)
105 label
&= ~temp_labels
; /* instr and temp alias */
107 if (new_label
& temp_labels
) {
108 label
&= ~temp_labels
;
109 label
&= ~instr_labels
; /* instr and temp alias */
112 if (new_label
& val_labels
)
113 label
&= ~val_labels
;
118 void set_vec(Instruction
* vec
)
120 add_label(label_vec
);
126 return label
& label_vec
;
129 void set_constant(uint32_t constant
)
131 add_label(label_constant
);
137 return label
& label_constant
;
140 void set_abs(Temp abs_temp
)
142 add_label(label_abs
);
148 return label
& label_abs
;
151 void set_neg(Temp neg_temp
)
153 add_label(label_neg
);
159 return label
& label_neg
;
162 void set_neg_abs(Temp neg_abs_temp
)
164 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
168 void set_mul(Instruction
* mul
)
170 add_label(label_mul
);
176 return label
& label_mul
;
179 void set_temp(Temp tmp
)
181 add_label(label_temp
);
187 return label
& label_temp
;
190 void set_literal(uint32_t lit
)
192 add_label(label_literal
);
198 return label
& label_literal
;
201 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
203 add_label(label_mad
);
210 return label
& label_mad
;
215 add_label(label_omod2
);
220 return label
& label_omod2
;
225 add_label(label_omod4
);
230 return label
& label_omod4
;
235 add_label(label_omod5
);
240 return label
& label_omod5
;
243 void set_omod_success(Instruction
* omod_instr
)
245 add_label(label_omod_success
);
249 bool is_omod_success()
251 return label
& label_omod_success
;
256 add_label(label_clamp
);
261 return label
& label_clamp
;
264 void set_clamp_success(Instruction
* clamp_instr
)
266 add_label(label_clamp_success
);
270 bool is_clamp_success()
272 return label
& label_clamp_success
;
277 add_label(label_undefined
);
282 return label
& label_undefined
;
285 void set_vcc(Temp vcc
)
287 add_label(label_vcc
);
293 return label
& label_vcc
;
296 bool is_constant_or_literal()
298 return is_constant() || is_literal();
301 void set_b2f(Temp val
)
303 add_label(label_b2f
);
309 return label
& label_b2f
;
312 void set_add_sub(Instruction
*add_sub_instr
)
314 add_label(label_add_sub
);
315 instr
= add_sub_instr
;
320 return label
& label_add_sub
;
323 void set_bitwise(Instruction
*bitwise_instr
)
325 add_label(label_bitwise
);
326 instr
= bitwise_instr
;
331 return label
& label_bitwise
;
334 void set_minmax(Instruction
*minmax_instr
)
336 add_label(label_minmax
);
337 instr
= minmax_instr
;
342 return label
& label_minmax
;
345 void set_fcmp(Instruction
*fcmp_instr
)
347 add_label(label_fcmp
);
353 return label
& label_fcmp
;
360 std::vector
<aco_ptr
<Instruction
>> instructions
;
362 std::pair
<uint32_t,Temp
> last_literal
;
363 std::vector
<mad_info
> mad_infos
;
364 std::vector
<uint16_t> uses
;
367 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
369 if (instr
->operands
[0].isConstant() ||
370 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
373 switch (instr
->opcode
) {
374 case aco_opcode::v_add_f32
:
375 case aco_opcode::v_mul_f32
:
376 case aco_opcode::v_or_b32
:
377 case aco_opcode::v_and_b32
:
378 case aco_opcode::v_xor_b32
:
379 case aco_opcode::v_max_f32
:
380 case aco_opcode::v_min_f32
:
381 case aco_opcode::v_cmp_eq_f32
:
382 case aco_opcode::v_cmp_lg_f32
:
384 case aco_opcode::v_sub_f32
:
385 instr
->opcode
= aco_opcode::v_subrev_f32
;
387 case aco_opcode::v_cmp_lt_f32
:
388 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
390 case aco_opcode::v_cmp_ge_f32
:
391 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
393 case aco_opcode::v_cmp_lt_i32
:
394 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
401 bool can_use_VOP3(aco_ptr
<Instruction
>& instr
)
403 if (instr
->operands
.size() && instr
->operands
[0].isLiteral())
406 if (instr
->isDPP() || instr
->isSDWA())
409 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
410 instr
->opcode
!= aco_opcode::v_madak_f32
&&
411 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
412 instr
->opcode
!= aco_opcode::v_madak_f16
;
415 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
417 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
418 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
419 instr
->opcode
!= aco_opcode::v_writelane_b32
;
422 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
427 assert(!instr
->operands
[0].isLiteral());
428 aco_ptr
<Instruction
> tmp
= std::move(instr
);
429 Format format
= asVOP3(tmp
->format
);
430 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
431 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
432 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
433 instr
->definitions
[i
] = tmp
->definitions
[i
];
434 if (instr
->definitions
[i
].isTemp()) {
435 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
436 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
437 info
.instr
= instr
.get();
442 /* only covers special cases */
443 bool can_accept_constant(aco_ptr
<Instruction
>& instr
, unsigned operand
)
445 switch (instr
->opcode
) {
446 case aco_opcode::v_interp_p2_f32
:
447 case aco_opcode::v_mac_f32
:
448 case aco_opcode::v_writelane_b32
:
449 case aco_opcode::v_cndmask_b32
:
451 case aco_opcode::s_addk_i32
:
452 case aco_opcode::s_mulk_i32
:
453 case aco_opcode::p_wqm
:
454 case aco_opcode::p_extract_vector
:
455 case aco_opcode::p_split_vector
:
456 case aco_opcode::v_readlane_b32
:
457 case aco_opcode::v_readfirstlane_b32
:
460 if ((instr
->format
== Format::MUBUF
||
461 instr
->format
== Format::MIMG
) &&
462 instr
->definitions
.size() == 1 &&
463 instr
->operands
.size() == 4) {
470 bool valu_can_accept_literal(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, unsigned operand
)
472 // TODO: VOP3 can take a literal on GFX10
473 return !instr
->isSDWA() && !instr
->isDPP() && !instr
->isVOP3() &&
474 operand
== 0 && can_accept_constant(instr
, operand
);
477 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
479 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
)
484 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
486 Operand op
= instr
->operands
[op_index
];
490 Temp tmp
= op
.getTemp();
491 if (!ctx
.info
[tmp
.id()].is_add_sub())
494 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
496 switch (add_instr
->opcode
) {
497 case aco_opcode::v_add_u32
:
498 case aco_opcode::v_add_co_u32
:
499 case aco_opcode::s_add_i32
:
500 case aco_opcode::s_add_u32
:
506 if (add_instr
->usesModifiers())
509 for (unsigned i
= 0; i
< 2; i
++) {
510 if (add_instr
->operands
[i
].isConstant()) {
511 *offset
= add_instr
->operands
[i
].constantValue();
512 } else if (add_instr
->operands
[i
].isTemp() &&
513 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
514 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
518 if (!add_instr
->operands
[!i
].isTemp())
521 uint32_t offset2
= 0;
522 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
525 *base
= add_instr
->operands
[!i
].getTemp();
533 void label_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
535 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
536 ASSERTED
bool all_const
= false;
537 for (Operand
& op
: instr
->operands
)
538 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
539 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
542 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
544 if (!instr
->operands
[i
].isTemp())
547 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
548 /* propagate undef */
549 if (info
.is_undefined() && is_phi(instr
))
550 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
551 /* propagate reg->reg of same type */
552 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
553 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
554 info
= ctx
.info
[info
.temp
.id()];
557 /* SALU / PSEUDO: propagate inline constants */
558 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
559 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
560 instr
->operands
[i
].setTemp(info
.temp
);
561 info
= ctx
.info
[info
.temp
.id()];
562 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
563 /* propagate vgpr if it can take it */
564 switch (instr
->opcode
) {
565 case aco_opcode::p_create_vector
:
566 case aco_opcode::p_split_vector
:
567 case aco_opcode::p_extract_vector
:
568 case aco_opcode::p_phi
: {
569 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
570 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
572 instr
->operands
[i
] = Operand(info
.temp
);
573 info
= ctx
.info
[info
.temp
.id()];
581 if ((info
.is_constant() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) && !instr
->operands
[i
].isFixed() && can_accept_constant(instr
, i
)) {
582 instr
->operands
[i
] = Operand(info
.val
);
587 /* VALU: propagate neg, abs & inline constants */
588 else if (instr
->isVALU()) {
589 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
590 instr
->operands
[i
].setTemp(info
.temp
);
591 info
= ctx
.info
[info
.temp
.id()];
593 if (info
.is_abs() && (can_use_VOP3(instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
596 instr
->operands
[i
] = Operand(info
.temp
);
598 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
600 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
602 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
603 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
604 instr
->operands
[i
].setTemp(info
.temp
);
606 } else if (info
.is_neg() && (can_use_VOP3(instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
609 instr
->operands
[i
].setTemp(info
.temp
);
611 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
613 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
616 if (info
.is_constant() && can_accept_constant(instr
, i
)) {
617 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
619 instr
->operands
[i
] = Operand(info
.val
);
621 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
622 instr
->operands
[i
] = instr
->operands
[0];
623 instr
->operands
[0] = Operand(info
.val
);
625 } else if (can_use_VOP3(instr
)) {
627 instr
->operands
[i
] = Operand(info
.val
);
633 /* MUBUF: propagate constants and combine additions */
634 else if (instr
->format
== Format::MUBUF
) {
635 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
638 while (info
.is_temp())
639 info
= ctx
.info
[info
.temp
.id()];
641 if (mubuf
->offen
&& i
== 0 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
642 assert(!mubuf
->idxen
);
643 instr
->operands
[i
] = Operand(v1
);
644 mubuf
->offset
+= info
.val
;
645 mubuf
->offen
= false;
647 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
648 instr
->operands
[2] = Operand((uint32_t) 0);
649 mubuf
->offset
+= info
.val
;
651 } else if (mubuf
->offen
&& i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
652 assert(!mubuf
->idxen
);
653 instr
->operands
[i
].setTemp(base
);
654 mubuf
->offset
+= offset
;
656 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
657 instr
->operands
[i
].setTemp(base
);
658 mubuf
->offset
+= offset
;
663 /* DS: combine additions */
664 else if (instr
->format
== Format::DS
) {
666 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
669 if (i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == instr
->operands
[i
].regClass()) {
670 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
671 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
672 if (offset
% 4 == 0 &&
673 ds
->offset0
+ (offset
>> 2) <= 255 &&
674 ds
->offset1
+ (offset
>> 2) <= 255) {
675 instr
->operands
[i
].setTemp(base
);
676 ds
->offset0
+= offset
>> 2;
677 ds
->offset1
+= offset
>> 2;
680 if (ds
->offset0
+ offset
<= 65535) {
681 instr
->operands
[i
].setTemp(base
);
682 ds
->offset0
+= offset
;
688 /* SMEM: propagate constants and combine additions */
689 else if (instr
->format
== Format::SMEM
) {
691 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
694 if (i
== 1 && info
.is_constant_or_literal() && info
.val
<= 0xFFFFF) {
695 instr
->operands
[i
] = Operand(info
.val
);
697 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
698 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
700 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
701 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
705 smem
->operands
[1] = Operand(offset
);
706 smem
->operands
.back() = Operand(base
);
708 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
709 new_instr
->operands
[0] = smem
->operands
[0];
710 new_instr
->operands
[1] = Operand(offset
);
711 if (smem
->definitions
.empty())
712 new_instr
->operands
[2] = smem
->operands
[2];
713 new_instr
->operands
.back() = Operand(base
);
714 if (!smem
->definitions
.empty())
715 new_instr
->definitions
[0] = smem
->definitions
[0];
716 new_instr
->can_reorder
= smem
->can_reorder
;
717 new_instr
->barrier
= smem
->barrier
;
718 instr
.reset(new_instr
);
719 smem
= static_cast<SMEM_instruction
*>(instr
.get());
726 /* if this instruction doesn't define anything, return */
727 if (instr
->definitions
.empty())
730 switch (instr
->opcode
) {
731 case aco_opcode::p_create_vector
: {
732 unsigned num_ops
= instr
->operands
.size();
733 for (const Operand
& op
: instr
->operands
) {
734 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
735 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
737 if (num_ops
!= instr
->operands
.size()) {
738 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
739 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
740 instr
->definitions
[0] = old_vec
->definitions
[0];
742 for (Operand
& old_op
: old_vec
->operands
) {
743 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
744 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++)
745 instr
->operands
[k
++] = ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
747 instr
->operands
[k
++] = old_op
;
750 assert(k
== num_ops
);
752 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
753 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
754 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
755 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
758 case aco_opcode::p_split_vector
: {
759 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
761 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
762 assert(instr
->definitions
.size() == vec
->operands
.size());
763 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
764 Operand vec_op
= vec
->operands
[i
];
765 if (vec_op
.isConstant()) {
766 if (vec_op
.isLiteral())
767 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
769 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
771 assert(vec_op
.isTemp());
772 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
777 case aco_opcode::p_extract_vector
: { /* mov */
778 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
780 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
781 if (vec
->definitions
[0].getTemp().size() == vec
->operands
.size() && /* TODO: what about 64bit or other combinations? */
782 vec
->operands
[0].size() == instr
->definitions
[0].size()) {
784 /* convert this extract into a mov instruction */
785 Operand vec_op
= vec
->operands
[instr
->operands
[1].constantValue()];
786 bool is_vgpr
= instr
->definitions
[0].getTemp().type() == RegType::vgpr
;
787 aco_opcode opcode
= is_vgpr
? aco_opcode::v_mov_b32
: aco_opcode::s_mov_b32
;
788 Format format
= is_vgpr
? Format::VOP1
: Format::SOP1
;
789 instr
->opcode
= opcode
;
790 instr
->format
= format
;
791 instr
->operands
= {instr
->operands
.begin(), 1 };
792 instr
->operands
[0] = vec_op
;
794 if (vec_op
.isConstant()) {
795 if (vec_op
.isLiteral())
796 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(vec_op
.constantValue());
798 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(vec_op
.constantValue());
800 assert(vec_op
.isTemp());
801 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vec_op
.getTemp());
806 case aco_opcode::s_mov_b32
: /* propagate */
807 case aco_opcode::s_mov_b64
:
808 case aco_opcode::v_mov_b32
:
809 case aco_opcode::p_as_uniform
:
810 if (instr
->definitions
[0].isFixed()) {
811 /* don't copy-propagate copies into fixed registers */
812 } else if (instr
->usesModifiers()) {
814 } else if (instr
->operands
[0].isConstant()) {
815 if (instr
->operands
[0].isLiteral())
816 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
818 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
819 } else if (instr
->operands
[0].isTemp()) {
820 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
822 assert(instr
->operands
[0].isFixed());
825 case aco_opcode::p_is_helper
:
826 if (!ctx
.program
->needs_wqm
)
827 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
829 case aco_opcode::s_movk_i32
: {
830 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
831 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
832 if (v
<= 64 || v
>= 0xfffffff0)
833 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
835 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
838 case aco_opcode::v_bfrev_b32
:
839 case aco_opcode::s_brev_b32
: {
840 if (instr
->operands
[0].isConstant()) {
841 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
842 if (v
<= 64 || v
>= 0xfffffff0)
843 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
845 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
849 case aco_opcode::s_bfm_b32
: {
850 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
851 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
852 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
853 uint32_t v
= ((1u << size
) - 1u) << start
;
854 if (v
<= 64 || v
>= 0xfffffff0)
855 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
857 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
860 case aco_opcode::v_mul_f32
: { /* omod */
861 /* TODO: try to move the negate/abs modifier to the consumer instead */
862 if (instr
->usesModifiers())
865 for (unsigned i
= 0; i
< 2; i
++) {
866 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
867 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
868 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2();
869 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
870 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4();
871 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
872 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5();
873 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000) { /* 1.0 */
874 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
883 case aco_opcode::v_and_b32
: /* abs */
884 if (instr
->operands
[0].constantEquals(0x7FFFFFFF) && instr
->operands
[1].isTemp())
885 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
887 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
889 case aco_opcode::v_xor_b32
: { /* neg */
890 if (instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
891 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
892 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
894 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
895 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
896 instr
->opcode
= aco_opcode::v_or_b32
;
897 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
899 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
903 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
907 case aco_opcode::v_med3_f32
: { /* clamp */
908 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
909 if (vop3
->abs
[0] || vop3
->neg
[0] || vop3
->opsel
[0] ||
910 vop3
->abs
[1] || vop3
->neg
[1] || vop3
->opsel
[1] ||
911 vop3
->abs
[2] || vop3
->neg
[2] || vop3
->opsel
[2] ||
916 bool found_zero
= false, found_one
= false;
917 for (unsigned i
= 0; i
< 3; i
++)
919 if (instr
->operands
[i
].constantEquals(0))
921 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
926 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
927 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp();
931 case aco_opcode::v_cndmask_b32
:
932 if (instr
->operands
[0].constantEquals(0) &&
933 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
934 instr
->operands
[2].isTemp())
935 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
936 else if (instr
->operands
[0].constantEquals(0) &&
937 instr
->operands
[1].constantEquals(0x3f800000u
) &&
938 instr
->operands
[2].isTemp())
939 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
941 case aco_opcode::v_cmp_lg_u32
:
942 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
943 instr
->operands
[0].constantEquals(0) &&
944 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
945 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
947 case aco_opcode::p_phi
:
948 case aco_opcode::p_linear_phi
: {
949 /* lower_bool_phis() can create phis like this */
950 bool all_same_temp
= instr
->operands
[0].isTemp();
951 /* this check is needed when moving uniform loop counters out of a divergent loop */
953 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
954 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
955 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
956 all_same_temp
= false;
959 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
961 bool all_undef
= instr
->operands
[0].isUndefined();
962 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
963 if (!instr
->operands
[i
].isUndefined())
967 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
971 case aco_opcode::v_add_u32
:
972 case aco_opcode::v_add_co_u32
:
973 case aco_opcode::s_add_i32
:
974 case aco_opcode::s_add_u32
:
975 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
977 case aco_opcode::s_not_b32
:
978 case aco_opcode::s_not_b64
:
979 case aco_opcode::s_and_b32
:
980 case aco_opcode::s_and_b64
:
981 case aco_opcode::s_or_b32
:
982 case aco_opcode::s_or_b64
:
983 case aco_opcode::s_xor_b32
:
984 case aco_opcode::s_xor_b64
:
985 case aco_opcode::s_lshl_b32
:
986 case aco_opcode::v_or_b32
:
987 case aco_opcode::v_lshlrev_b32
:
988 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
990 case aco_opcode::v_min_f32
:
991 case aco_opcode::v_min_f16
:
992 case aco_opcode::v_min_u32
:
993 case aco_opcode::v_min_i32
:
994 case aco_opcode::v_min_u16
:
995 case aco_opcode::v_min_i16
:
996 case aco_opcode::v_max_f32
:
997 case aco_opcode::v_max_f16
:
998 case aco_opcode::v_max_u32
:
999 case aco_opcode::v_max_i32
:
1000 case aco_opcode::v_max_u16
:
1001 case aco_opcode::v_max_i16
:
1002 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1004 case aco_opcode::v_cmp_lt_f32
:
1005 case aco_opcode::v_cmp_eq_f32
:
1006 case aco_opcode::v_cmp_le_f32
:
1007 case aco_opcode::v_cmp_gt_f32
:
1008 case aco_opcode::v_cmp_lg_f32
:
1009 case aco_opcode::v_cmp_ge_f32
:
1010 case aco_opcode::v_cmp_o_f32
:
1011 case aco_opcode::v_cmp_u_f32
:
1012 case aco_opcode::v_cmp_nge_f32
:
1013 case aco_opcode::v_cmp_nlg_f32
:
1014 case aco_opcode::v_cmp_ngt_f32
:
1015 case aco_opcode::v_cmp_nle_f32
:
1016 case aco_opcode::v_cmp_neq_f32
:
1017 case aco_opcode::v_cmp_nlt_f32
:
1018 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1025 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1027 *ordered
= *unordered
= op
;
1029 #define CMP(ord, unord) \
1030 case aco_opcode::v_cmp_##ord##_f32:\
1031 case aco_opcode::v_cmp_n##unord##_f32:\
1032 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1033 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1034 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1048 aco_opcode
get_ordered(aco_opcode op
)
1050 aco_opcode ordered
, unordered
, inverse
;
1051 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1054 aco_opcode
get_unordered(aco_opcode op
)
1056 aco_opcode ordered
, unordered
, inverse
;
1057 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1060 aco_opcode
get_inverse(aco_opcode op
)
1062 aco_opcode ordered
, unordered
, inverse
;
1063 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1066 bool is_cmp(aco_opcode op
)
1068 aco_opcode ordered
, unordered
, inverse
;
1069 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1072 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1074 if (ctx
.info
[tmp
.id()].is_temp())
1075 return ctx
.info
[tmp
.id()].temp
.id();
1080 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1082 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1083 for (const Operand
& op
: instr
->operands
) {
1085 ctx
.uses
[op
.tempId()]--;
1090 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1092 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1094 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1097 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1099 if (instr
->definitions
.size() == 2) {
1100 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1101 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1108 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1109 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1110 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1112 if (instr
->opcode
!= aco_opcode::s_or_b64
&& instr
->opcode
!= aco_opcode::s_and_b64
)
1114 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1117 bool neg
[2] = {false, false};
1118 bool abs
[2] = {false, false};
1119 bool opsel
[2] = {false, false};
1120 Instruction
*op_instr
[2];
1123 for (unsigned i
= 0; i
< 2; i
++) {
1124 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1128 aco_opcode expected_cmp
= instr
->opcode
== aco_opcode::s_or_b64
?
1129 aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1131 if (op_instr
[i
]->opcode
!= expected_cmp
)
1133 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1136 if (op_instr
[i
]->isVOP3()) {
1137 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1138 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
[0] != vop3
->opsel
[1])
1140 neg
[i
] = vop3
->neg
[0];
1141 abs
[i
] = vop3
->abs
[0];
1142 opsel
[i
] = vop3
->opsel
[0];
1145 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1146 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1147 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1149 /* shouldn't happen yet, but best to be safe */
1150 if (op1
.type() != RegType::vgpr
)
1156 ctx
.uses
[op
[0].id()]++;
1157 ctx
.uses
[op
[1].id()]++;
1158 decrease_uses(ctx
, op_instr
[0]);
1159 decrease_uses(ctx
, op_instr
[1]);
1161 aco_opcode new_op
= instr
->opcode
== aco_opcode::s_or_b64
?
1162 aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1163 Instruction
*new_instr
;
1164 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
[0] || opsel
[1]) {
1165 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1166 for (unsigned i
= 0; i
< 2; i
++) {
1167 vop3
->neg
[i
] = neg
[i
];
1168 vop3
->abs
[i
] = abs
[i
];
1169 vop3
->opsel
[i
] = opsel
[i
];
1171 new_instr
= static_cast<Instruction
*>(vop3
);
1173 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1175 new_instr
->operands
[0] = Operand(op
[0]);
1176 new_instr
->operands
[1] = Operand(op
[1]);
1177 new_instr
->definitions
[0] = instr
->definitions
[0];
1179 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1180 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1182 instr
.reset(new_instr
);
1187 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1188 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1189 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1191 if (instr
->opcode
!= aco_opcode::s_or_b64
&& instr
->opcode
!= aco_opcode::s_and_b64
)
1193 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1196 aco_opcode expected_nan_test
= instr
->opcode
== aco_opcode::s_or_b64
?
1197 aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1199 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1200 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1201 if (!nan_test
|| !cmp
)
1204 if (cmp
->opcode
== expected_nan_test
)
1205 std::swap(nan_test
, cmp
);
1206 else if (nan_test
->opcode
!= expected_nan_test
)
1209 if (!is_cmp(cmp
->opcode
))
1212 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1214 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1217 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1218 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1219 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1220 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1221 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1223 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1226 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1227 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1228 decrease_uses(ctx
, nan_test
);
1229 decrease_uses(ctx
, cmp
);
1231 aco_opcode new_op
= instr
->opcode
== aco_opcode::s_or_b64
?
1232 get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1233 Instruction
*new_instr
;
1234 if (cmp
->isVOP3()) {
1235 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1236 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1237 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1238 memcpy(new_vop3
->opsel
, cmp_vop3
->opsel
, sizeof(new_vop3
->opsel
));
1239 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1240 new_vop3
->clamp
= cmp_vop3
->clamp
;
1241 new_vop3
->omod
= cmp_vop3
->omod
;
1242 new_instr
= new_vop3
;
1244 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1246 new_instr
->operands
[0] = cmp
->operands
[0];
1247 new_instr
->operands
[1] = cmp
->operands
[1];
1248 new_instr
->definitions
[0] = instr
->definitions
[0];
1250 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1251 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1253 instr
.reset(new_instr
);
1258 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1259 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1260 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1262 if (instr
->opcode
!= aco_opcode::s_or_b64
&& instr
->opcode
!= aco_opcode::s_and_b64
)
1264 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1267 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1268 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1270 if (!nan_test
|| !cmp
)
1273 aco_opcode expected_nan_test
= instr
->opcode
== aco_opcode::s_or_b64
?
1274 aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1275 if (cmp
->opcode
== expected_nan_test
)
1276 std::swap(nan_test
, cmp
);
1277 else if (nan_test
->opcode
!= expected_nan_test
)
1280 if (!is_cmp(cmp
->opcode
))
1283 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1285 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1288 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1289 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1290 if (prop_nan0
!= prop_nan1
)
1293 int constant_operand
= -1;
1294 for (unsigned i
= 0; i
< 2; i
++) {
1295 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1296 constant_operand
= !i
;
1300 if (constant_operand
== -1)
1304 if (cmp
->operands
[constant_operand
].isConstant()) {
1305 constant
= cmp
->operands
[constant_operand
].constantValue();
1306 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1307 unsigned id
= cmp
->operands
[constant_operand
].tempId();
1308 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1310 constant
= ctx
.info
[id
].val
;
1316 memcpy(&constantf
, &constant
, 4);
1317 if (isnan(constantf
))
1320 if (cmp
->operands
[0].isTemp())
1321 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1322 if (cmp
->operands
[1].isTemp())
1323 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1324 decrease_uses(ctx
, nan_test
);
1325 decrease_uses(ctx
, cmp
);
1327 aco_opcode new_op
= instr
->opcode
== aco_opcode::s_or_b64
?
1328 get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1329 Instruction
*new_instr
;
1330 if (cmp
->isVOP3()) {
1331 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1332 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1333 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1334 memcpy(new_vop3
->opsel
, cmp_vop3
->opsel
, sizeof(new_vop3
->opsel
));
1335 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1336 new_vop3
->clamp
= cmp_vop3
->clamp
;
1337 new_vop3
->omod
= cmp_vop3
->omod
;
1338 new_instr
= new_vop3
;
1340 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1342 new_instr
->operands
[0] = cmp
->operands
[0];
1343 new_instr
->operands
[1] = cmp
->operands
[1];
1344 new_instr
->definitions
[0] = instr
->definitions
[0];
1346 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1347 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1349 instr
.reset(new_instr
);
1354 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1355 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1357 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1359 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1361 if (!instr
->operands
[0].isTemp())
1364 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1368 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1369 if (new_opcode
== aco_opcode::last_opcode
)
1372 if (cmp
->operands
[0].isTemp())
1373 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1374 if (cmp
->operands
[1].isTemp())
1375 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1376 decrease_uses(ctx
, cmp
);
1378 Instruction
*new_instr
;
1379 if (cmp
->isVOP3()) {
1380 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1381 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1382 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1383 memcpy(new_vop3
->opsel
, cmp_vop3
->opsel
, sizeof(new_vop3
->opsel
));
1384 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1385 new_vop3
->clamp
= cmp_vop3
->clamp
;
1386 new_vop3
->omod
= cmp_vop3
->omod
;
1387 new_instr
= new_vop3
;
1389 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1391 new_instr
->operands
[0] = cmp
->operands
[0];
1392 new_instr
->operands
[1] = cmp
->operands
[1];
1393 new_instr
->definitions
[0] = instr
->definitions
[0];
1395 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1396 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1398 instr
.reset(new_instr
);
1403 /* op1(op2(1, 2), 0) if swap = false
1404 * op1(0, op2(1, 2)) if swap = true */
1405 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1406 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1407 Operand operands
[3], bool neg
[3], bool abs
[3], bool opsel
[3],
1408 bool *op1_clamp
, unsigned *op1_omod
,
1409 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1412 if (op1_instr
->opcode
!= op1
)
1415 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1416 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1419 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1420 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1422 /* don't support inbetween clamp/omod */
1423 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1426 /* get operands and modifiers and check inbetween modifiers */
1427 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1428 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1431 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1432 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1436 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1437 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1440 if (inbetween_opsel
)
1441 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
[swap
] : false;
1442 else if (op1_vop3
&& op1_vop3
->opsel
[swap
])
1446 shuffle
[shuffle_str
[0] - '0'] = 0;
1447 shuffle
[shuffle_str
[1] - '0'] = 1;
1448 shuffle
[shuffle_str
[2] - '0'] = 2;
1450 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1451 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1452 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1453 opsel
[shuffle
[0]] = op1_vop3
? op1_vop3
->opsel
[!swap
] : false;
1455 for (unsigned i
= 0; i
< 2; i
++) {
1456 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1457 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1458 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1459 opsel
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->opsel
[i
] : false;
1462 /* check operands */
1463 unsigned sgpr_id
= 0;
1464 for (unsigned i
= 0; i
< 3; i
++) {
1465 Operand op
= operands
[i
];
1466 if (op
.isLiteral()) {
1468 } else if (op
.isTemp() && op
.getTemp().type() == RegType::sgpr
) {
1469 if (sgpr_id
&& sgpr_id
!= op
.tempId())
1471 sgpr_id
= op
.tempId();
1478 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1479 Operand operands
[3], bool neg
[3], bool abs
[3], bool opsel
[3],
1480 bool clamp
, unsigned omod
)
1482 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1483 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1484 memcpy(new_instr
->opsel
, opsel
, sizeof(bool[3]));
1485 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1486 new_instr
->clamp
= clamp
;
1487 new_instr
->omod
= omod
;
1488 new_instr
->operands
[0] = operands
[0];
1489 new_instr
->operands
[1] = operands
[1];
1490 new_instr
->operands
[2] = operands
[2];
1491 new_instr
->definitions
[0] = instr
->definitions
[0];
1492 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1494 instr
.reset(new_instr
);
1497 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1499 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1500 (label_omod_success
| label_clamp_success
);
1502 for (unsigned swap
= 0; swap
< 2; swap
++) {
1503 if (!((1 << swap
) & ops
))
1506 Operand operands
[3];
1507 bool neg
[3], abs
[3], opsel
[3], clamp
;
1509 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1510 instr
.get(), swap
, shuffle
,
1511 operands
, neg
, abs
, opsel
,
1512 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1513 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1514 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1515 if (omod_clamp
& label_omod_success
)
1516 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1517 if (omod_clamp
& label_clamp_success
)
1518 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1525 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1526 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1527 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1528 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1529 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1530 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1531 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1534 if (!instr
->operands
[0].isTemp())
1536 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1539 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1542 switch (op2_instr
->opcode
) {
1543 case aco_opcode::s_and_b32
:
1544 case aco_opcode::s_or_b32
:
1545 case aco_opcode::s_xor_b32
:
1546 case aco_opcode::s_and_b64
:
1547 case aco_opcode::s_or_b64
:
1548 case aco_opcode::s_xor_b64
:
1554 /* create instruction */
1555 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1556 ctx
.uses
[instr
->operands
[0].tempId()]--;
1557 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1559 switch (op2_instr
->opcode
) {
1560 case aco_opcode::s_and_b32
:
1561 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1563 case aco_opcode::s_or_b32
:
1564 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1566 case aco_opcode::s_xor_b32
:
1567 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1569 case aco_opcode::s_and_b64
:
1570 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1572 case aco_opcode::s_or_b64
:
1573 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1575 case aco_opcode::s_xor_b64
:
1576 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1585 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1586 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1587 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1588 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1589 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1591 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1594 for (unsigned i
= 0; i
< 2; i
++) {
1595 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1596 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1599 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1600 instr
->operands
[0] = instr
->operands
[!i
];
1601 instr
->operands
[1] = op2_instr
->operands
[0];
1602 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1604 switch (instr
->opcode
) {
1605 case aco_opcode::s_and_b32
:
1606 instr
->opcode
= aco_opcode::s_andn2_b32
;
1608 case aco_opcode::s_or_b32
:
1609 instr
->opcode
= aco_opcode::s_orn2_b32
;
1611 case aco_opcode::s_and_b64
:
1612 instr
->opcode
= aco_opcode::s_andn2_b64
;
1614 case aco_opcode::s_or_b64
:
1615 instr
->opcode
= aco_opcode::s_orn2_b64
;
1626 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1627 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1629 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1632 for (unsigned i
= 0; i
< 2; i
++) {
1633 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1634 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
|| !op2_instr
->operands
[1].isConstant())
1637 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1638 if (shift
< 1 || shift
> 4)
1641 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1642 instr
->operands
[1] = instr
->operands
[!i
];
1643 instr
->operands
[0] = op2_instr
->operands
[0];
1644 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1646 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1647 aco_opcode::s_lshl2_add_u32
,
1648 aco_opcode::s_lshl3_add_u32
,
1649 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1656 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1659 #define MINMAX(type, gfx9) \
1660 case aco_opcode::v_min_##type:\
1661 case aco_opcode::v_max_##type:\
1662 case aco_opcode::v_med3_##type:\
1663 *min = aco_opcode::v_min_##type;\
1664 *max = aco_opcode::v_max_##type;\
1665 *med3 = aco_opcode::v_med3_##type;\
1666 *min3 = aco_opcode::v_min3_##type;\
1667 *max3 = aco_opcode::v_max3_##type;\
1668 *some_gfx9_only = gfx9;\
1682 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1683 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1684 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1685 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1687 aco_opcode other_op
;
1688 if (instr
->opcode
== min
)
1690 else if (instr
->opcode
== max
)
1695 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1696 (label_omod_success
| label_clamp_success
);
1698 for (unsigned swap
= 0; swap
< 2; swap
++) {
1699 Operand operands
[3];
1700 bool neg
[3], abs
[3], opsel
[3], clamp
, inbetween_neg
, inbetween_abs
;
1702 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1703 "012", operands
, neg
, abs
, opsel
,
1704 &clamp
, &omod
, &inbetween_neg
, &inbetween_abs
, NULL
)) {
1705 int const0_idx
= -1, const1_idx
= -1;
1706 uint32_t const0
= 0, const1
= 0;
1707 for (int i
= 0; i
< 3; i
++) {
1709 if (operands
[i
].isConstant()) {
1710 val
= operands
[i
].constantValue();
1711 } else if (operands
[i
].isTemp() && ctx
.uses
[operands
[i
].tempId()] == 1 &&
1712 ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
1713 val
= ctx
.info
[operands
[i
].tempId()].val
;
1717 if (const0_idx
>= 0) {
1725 if (const0_idx
< 0 || const1_idx
< 0)
1728 if (opsel
[const0_idx
])
1730 if (opsel
[const1_idx
])
1733 int lower_idx
= const0_idx
;
1735 case aco_opcode::v_min_f32
:
1736 case aco_opcode::v_min_f16
: {
1737 float const0_f
, const1_f
;
1738 if (min
== aco_opcode::v_min_f32
) {
1739 memcpy(&const0_f
, &const0
, 4);
1740 memcpy(&const1_f
, &const1
, 4);
1742 const0_f
= _mesa_half_to_float(const0
);
1743 const1_f
= _mesa_half_to_float(const1
);
1745 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
1746 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
1747 if (neg
[const0_idx
]) const0_f
= -const0_f
;
1748 if (neg
[const1_idx
]) const1_f
= -const1_f
;
1749 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
1752 case aco_opcode::v_min_u32
: {
1753 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
1756 case aco_opcode::v_min_u16
: {
1757 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
1760 case aco_opcode::v_min_i32
: {
1761 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
1762 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
1763 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1766 case aco_opcode::v_min_i16
: {
1767 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
1768 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
1769 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1775 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
1777 if (instr
->opcode
== min
) {
1778 if (upper_idx
!= 0 || lower_idx
== 0)
1781 if (upper_idx
== 0 || lower_idx
!= 0)
1785 neg
[1] ^= inbetween_neg
;
1786 neg
[2] ^= inbetween_neg
;
1787 abs
[1] |= inbetween_abs
;
1788 abs
[2] |= inbetween_abs
;
1790 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1791 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1792 if (omod_clamp
& label_omod_success
)
1793 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1794 if (omod_clamp
& label_clamp_success
)
1795 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1805 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1808 uint32_t sgpr_idx
= 0;
1809 uint32_t sgpr_info_id
= 0;
1810 bool has_sgpr
= false;
1811 uint32_t sgpr_ssa_id
= 0;
1812 /* find 'best' possible sgpr */
1813 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
1815 if (instr
->operands
[i
].isLiteral()) {
1819 if (!instr
->operands
[i
].isTemp())
1821 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
1823 sgpr_ssa_id
= instr
->operands
[i
].tempId();
1826 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
1827 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
1828 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
1829 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
1831 sgpr_info_id
= instr
->operands
[i
].tempId();
1835 if (!has_sgpr
&& sgpr_info_id
!= 0) {
1836 ssa_info
& info
= ctx
.info
[sgpr_info_id
];
1837 if (sgpr_idx
== 0 || instr
->isVOP3()) {
1838 instr
->operands
[sgpr_idx
] = Operand(info
.temp
);
1839 ctx
.uses
[sgpr_info_id
]--;
1840 ctx
.uses
[info
.temp
.id()]++;
1841 } else if (can_swap_operands(instr
)) {
1842 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
1843 instr
->operands
[0] = Operand(info
.temp
);
1844 ctx
.uses
[sgpr_info_id
]--;
1845 ctx
.uses
[info
.temp
.id()]++;
1846 } else if (can_use_VOP3(instr
)) {
1847 to_VOP3(ctx
, instr
);
1848 instr
->operands
[sgpr_idx
] = Operand(info
.temp
);
1849 ctx
.uses
[sgpr_info_id
]--;
1850 ctx
.uses
[info
.temp
.id()]++;
1853 /* we can have two sgprs on one instruction if it is the same sgpr! */
1854 } else if (sgpr_info_id
!= 0 &&
1855 sgpr_ssa_id
== sgpr_info_id
&&
1856 ctx
.uses
[sgpr_info_id
] == 1 &&
1857 can_use_VOP3(instr
)) {
1858 to_VOP3(ctx
, instr
);
1859 instr
->operands
[sgpr_idx
] = Operand(ctx
.info
[sgpr_info_id
].temp
);
1860 ctx
.uses
[sgpr_info_id
]--;
1861 ctx
.uses
[ctx
.info
[sgpr_info_id
].temp
.id()]++;
1865 bool apply_omod_clamp(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1867 /* check if we could apply omod on predecessor */
1868 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
1869 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success()) {
1871 /* omod was successfully applied */
1872 /* if the omod instruction is v_mad, we also have to change the original add */
1873 if (ctx
.info
[instr
->operands
[1].tempId()].is_mad()) {
1874 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[1].tempId()].val
].add_instr
.get();
1875 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
1876 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
1877 add_instr
->definitions
[0] = instr
->definitions
[0];
1880 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
1881 /* check if we have an additional clamp modifier */
1882 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1) {
1883 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
1884 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
1886 /* change definition ssa-id of modified instruction */
1887 omod_instr
->definitions
[0] = instr
->definitions
[0];
1889 /* change the definition of instr to something unused, e.g. the original omod def */
1890 instr
->definitions
[0] = Definition(instr
->operands
[1].getTemp());
1891 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
1894 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
1895 /* in all other cases, label this instruction as option for multiply-add */
1896 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
1900 /* check if we could apply clamp on predecessor */
1901 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
1903 bool found_zero
= false, found_one
= false;
1904 for (unsigned i
= 0; i
< 3; i
++)
1906 if (instr
->operands
[i
].constantEquals(0))
1908 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1913 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
1914 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
1915 /* clamp was successfully applied */
1916 /* if the clamp instruction is v_mad, we also have to change the original add */
1917 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
1918 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
1919 add_instr
->definitions
[0] = instr
->definitions
[0];
1921 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
1922 /* change definition ssa-id of modified instruction */
1923 clamp_instr
->definitions
[0] = instr
->definitions
[0];
1925 /* change the definition of instr to something unused, e.g. the original omod def */
1926 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
1927 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
1932 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
1933 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
1934 can_use_VOP3(instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
1935 if(ctx
.info
[instr
->definitions
[0].tempId()].is_omod2()) {
1936 to_VOP3(ctx
, instr
);
1937 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
1938 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1939 } else if (ctx
.info
[instr
->definitions
[0].tempId()].is_omod4()) {
1940 to_VOP3(ctx
, instr
);
1941 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
1942 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1943 } else if (ctx
.info
[instr
->definitions
[0].tempId()].is_omod5()) {
1944 to_VOP3(ctx
, instr
);
1945 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
1946 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1947 } else if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp()) {
1948 to_VOP3(ctx
, instr
);
1949 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
1950 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1957 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
1958 // this would mean that we'd have to fix the instruction uses while value propagation
1960 void combine_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1962 if (instr
->definitions
.empty() || !ctx
.uses
[instr
->definitions
[0].tempId()])
1965 if (instr
->isVALU()) {
1966 if (can_apply_sgprs(instr
))
1967 apply_sgprs(ctx
, instr
);
1968 if (apply_omod_clamp(ctx
, instr
))
1972 /* TODO: There are still some peephole optimizations that could be done:
1973 * - abs(a - b) -> s_absdiff_i32
1974 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
1975 * - patterns for v_alignbit_b32 and v_alignbyte_b32
1976 * These aren't probably too interesting though.
1977 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
1978 * probably more useful than the previously mentioned optimizations.
1979 * The various comparison optimizations also currently only work with 32-bit
1982 /* neg(mul(a, b)) -> mul(neg(a), b) */
1983 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
1984 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
1986 if (!ctx
.info
[val
.id()].is_mul())
1989 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
1991 if (mul_instr
->operands
[0].isLiteral())
1993 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
1996 /* convert to mul(neg(a), b) */
1997 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
1998 Definition def
= instr
->definitions
[0];
1999 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2000 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2001 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2002 instr
->operands
[0] = mul_instr
->operands
[0];
2003 instr
->operands
[1] = mul_instr
->operands
[1];
2004 instr
->definitions
[0] = def
;
2005 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2006 if (mul_instr
->isVOP3()) {
2007 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2008 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2009 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2010 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2011 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2012 new_mul
->omod
= mul
->omod
;
2014 new_mul
->neg
[0] ^= true;
2015 new_mul
->clamp
= false;
2017 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2020 /* combine mul+add -> mad */
2021 else if (instr
->opcode
== aco_opcode::v_add_f32
||
2022 instr
->opcode
== aco_opcode::v_sub_f32
||
2023 instr
->opcode
== aco_opcode::v_subrev_f32
) {
2025 uint32_t uses_src0
= UINT32_MAX
;
2026 uint32_t uses_src1
= UINT32_MAX
;
2027 Instruction
* mul_instr
= nullptr;
2028 unsigned add_op_idx
;
2029 /* check if any of the operands is a multiplication */
2030 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2031 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2032 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2033 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2035 /* find the 'best' mul instruction to combine with the add */
2036 if (uses_src0
< uses_src1
) {
2037 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2039 } else if (uses_src1
< uses_src0
) {
2040 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2042 } else if (uses_src0
!= UINT32_MAX
) {
2043 /* tiebreaker: quite random what to pick */
2044 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2045 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2048 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2053 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2054 bool neg
[3] = {false, false, false};
2055 bool abs
[3] = {false, false, false};
2058 bool need_vop3
= false;
2060 op
[0] = mul_instr
->operands
[0];
2061 op
[1] = mul_instr
->operands
[1];
2062 op
[2] = instr
->operands
[add_op_idx
];
2063 for (unsigned i
= 0; i
< 3; i
++)
2065 if (op
[i
].isLiteral())
2067 if (op
[i
].isTemp() && op
[i
].getTemp().type() == RegType::sgpr
)
2069 if (!(i
== 0 || (op
[i
].isTemp() && op
[i
].getTemp().type() == RegType::vgpr
)))
2072 // TODO: would be better to check this before selecting a mul instr?
2076 if (mul_instr
->isVOP3()) {
2077 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2078 neg
[0] = vop3
->neg
[0];
2079 neg
[1] = vop3
->neg
[1];
2080 abs
[0] = vop3
->abs
[0];
2081 abs
[1] = vop3
->abs
[1];
2083 /* we cannot use these modifiers between mul and add */
2084 if (vop3
->clamp
|| vop3
->omod
)
2088 /* convert to mad */
2089 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2090 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2092 ctx
.uses
[op
[0].tempId()]++;
2094 ctx
.uses
[op
[1].tempId()]++;
2097 if (instr
->isVOP3()) {
2098 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2099 neg
[2] = vop3
->neg
[add_op_idx
];
2100 abs
[2] = vop3
->abs
[add_op_idx
];
2102 clamp
= vop3
->clamp
;
2103 /* abs of the multiplication result */
2104 if (vop3
->abs
[1 - add_op_idx
]) {
2110 /* neg of the multiplication result */
2111 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2114 if (instr
->opcode
== aco_opcode::v_sub_f32
) {
2115 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2117 } else if (instr
->opcode
== aco_opcode::v_subrev_f32
) {
2118 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2122 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2123 for (unsigned i
= 0; i
< 3; i
++)
2125 mad
->operands
[i
] = op
[i
];
2126 mad
->neg
[i
] = neg
[i
];
2127 mad
->abs
[i
] = abs
[i
];
2131 mad
->definitions
[0] = instr
->definitions
[0];
2133 /* mark this ssa_def to be re-checked for profitability and literals */
2134 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId(), need_vop3
);
2135 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2136 instr
.reset(mad
.release());
2140 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2141 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2142 for (unsigned i
= 0; i
< 2; i
++) {
2143 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2144 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2145 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2146 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2147 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2149 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2150 new_instr
->operands
[0] = Operand(0u);
2151 new_instr
->operands
[1] = instr
->operands
[!i
];
2152 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2153 new_instr
->definitions
[0] = instr
->definitions
[0];
2154 instr
.reset(new_instr
.release());
2155 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2159 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2160 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2161 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2162 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2163 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2164 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2165 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2166 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2167 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2168 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2169 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2170 combine_salu_lshl_add(ctx
, instr
);
2171 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2172 combine_salu_not_bitwise(ctx
, instr
);
2173 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2174 if (combine_inverse_comparison(ctx
, instr
)) ;
2175 else combine_salu_not_bitwise(ctx
, instr
);
2176 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
) {
2177 combine_salu_n2(ctx
, instr
);
2178 } else if (instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2179 if (combine_ordering_test(ctx
, instr
)) ;
2180 else if (combine_comparison_ordering(ctx
, instr
)) ;
2181 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2182 else combine_salu_n2(ctx
, instr
);
2184 aco_opcode min
, max
, min3
, max3
, med3
;
2185 bool some_gfx9_only
;
2186 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2187 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2188 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, instr
->opcode
== min
? min3
: max3
, "012", 1 | 2));
2189 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2195 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2197 const uint32_t threshold
= 4;
2199 /* Dead Code Elimination:
2200 * We remove instructions if they define temporaries which all are unused */
2201 const bool is_used
= instr
->definitions
.empty() ||
2202 std::any_of(instr
->definitions
.begin(), instr
->definitions
.end(),
2203 [&ctx
](const Definition
& def
) { return ctx
.uses
[def
.tempId()]; });
2209 /* convert split_vector into extract_vector if only one definition is ever used */
2210 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2211 unsigned num_used
= 0;
2213 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2214 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2219 if (num_used
== 1) {
2220 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2221 extract
->operands
[0] = instr
->operands
[0];
2222 extract
->operands
[1] = Operand((uint32_t) idx
);
2223 extract
->definitions
[0] = instr
->definitions
[idx
];
2224 instr
.reset(extract
.release());
2228 /* re-check mad instructions */
2229 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2230 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2231 /* first, check profitability */
2232 if (ctx
.uses
[info
->mul_temp_id
]) {
2233 ctx
.uses
[info
->mul_temp_id
]++;
2234 instr
.swap(info
->add_instr
);
2236 /* second, check possible literals */
2237 } else if (!info
->needs_vop3
) {
2238 uint32_t literal_idx
= 0;
2239 uint32_t literal_uses
= UINT32_MAX
;
2240 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2242 if (!instr
->operands
[i
].isTemp())
2244 /* if one of the operands is sgpr, we cannot add a literal somewhere else */
2245 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2246 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2247 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2250 literal_uses
= UINT32_MAX
;
2254 else if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2255 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2256 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2260 if (literal_uses
< threshold
) {
2261 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2262 info
->check_literal
= true;
2263 info
->literal_idx
= literal_idx
;
2269 /* check for literals */
2270 /* we do not apply the literals yet as we don't know if it is profitable */
2271 if (instr
->isSALU()) {
2272 uint32_t literal_idx
= 0;
2273 uint32_t literal_uses
= UINT32_MAX
;
2274 bool has_literal
= false;
2275 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2277 if (instr
->operands
[i
].isLiteral()) {
2281 if (!instr
->operands
[i
].isTemp())
2283 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2284 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2285 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2289 if (!has_literal
&& literal_uses
< threshold
) {
2290 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2291 if (ctx
.uses
[instr
->operands
[literal_idx
].tempId()] == 0)
2292 instr
->operands
[literal_idx
] = Operand(ctx
.info
[instr
->operands
[literal_idx
].tempId()].val
);
2294 } else if (instr
->isVALU() && valu_can_accept_literal(ctx
, instr
, 0) &&
2295 instr
->operands
[0].isTemp() &&
2296 ctx
.info
[instr
->operands
[0].tempId()].is_literal() &&
2297 ctx
.uses
[instr
->operands
[0].tempId()] < threshold
) {
2298 ctx
.uses
[instr
->operands
[0].tempId()]--;
2299 if (ctx
.uses
[instr
->operands
[0].tempId()] == 0)
2300 instr
->operands
[0] = Operand(ctx
.info
[instr
->operands
[0].tempId()].val
);
2306 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2308 /* Cleanup Dead Instructions */
2312 /* apply literals on SALU */
2313 if (instr
->isSALU()) {
2314 for (Operand
& op
: instr
->operands
) {
2319 if (ctx
.info
[op
.tempId()].is_literal() &&
2320 ctx
.uses
[op
.tempId()] == 0)
2321 op
= Operand(ctx
.info
[op
.tempId()].val
);
2325 /* apply literals on VALU */
2326 else if (instr
->isVALU() && !instr
->isVOP3() &&
2327 instr
->operands
[0].isTemp() &&
2328 ctx
.info
[instr
->operands
[0].tempId()].is_literal() &&
2329 ctx
.uses
[instr
->operands
[0].tempId()] == 0) {
2330 instr
->operands
[0] = Operand(ctx
.info
[instr
->operands
[0].tempId()].val
);
2333 /* apply literals on MAD */
2334 else if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2335 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2336 aco_ptr
<Instruction
> new_mad
;
2337 if (info
->check_literal
&& ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0) {
2338 if (info
->literal_idx
== 2) { /* add literal -> madak */
2339 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2340 new_mad
->operands
[0] = instr
->operands
[0];
2341 new_mad
->operands
[1] = instr
->operands
[1];
2342 } else { /* mul literal -> madmk */
2343 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2344 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2345 new_mad
->operands
[1] = instr
->operands
[2];
2347 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2348 new_mad
->definitions
[0] = instr
->definitions
[0];
2349 instr
.swap(new_mad
);
2353 ctx
.instructions
.emplace_back(std::move(instr
));
2357 void optimize(Program
* program
)
2360 ctx
.program
= program
;
2361 std::vector
<ssa_info
> info(program
->peekAllocationId());
2362 ctx
.info
= info
.data();
2364 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2365 for (Block
& block
: program
->blocks
) {
2366 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2367 label_instruction(ctx
, instr
);
2370 ctx
.uses
= std::move(dead_code_analysis(program
));
2372 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2373 for (Block
& block
: program
->blocks
) {
2374 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2375 combine_instruction(ctx
, instr
);
2378 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2379 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2380 Block
* block
= &(*it
);
2381 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2382 select_instruction(ctx
, *it
);
2385 /* 4. Add literals to instructions */
2386 for (Block
& block
: program
->blocks
) {
2387 ctx
.instructions
.clear();
2388 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2389 apply_literals(ctx
, instr
);
2390 block
.instructions
.swap(ctx
.instructions
);