2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant
= 1 << 1,
69 label_literal
= 1 << 6,
73 label_omod5
= 1 << 10,
74 label_omod_success
= 1 << 11,
75 label_clamp
= 1 << 12,
76 label_clamp_success
= 1 << 13,
77 label_undefined
= 1 << 14,
80 label_add_sub
= 1 << 17,
81 label_bitwise
= 1 << 18,
82 label_minmax
= 1 << 19,
84 label_uniform_bool
= 1 << 21,
85 label_constant_64bit
= 1 << 22,
86 label_uniform_bitwise
= 1 << 23,
87 label_scc_invert
= 1 << 24,
88 label_vcc_hint
= 1 << 25,
89 label_scc_needed
= 1 << 26,
92 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
|
93 label_add_sub
| label_bitwise
| label_uniform_bitwise
| label_minmax
| label_fcmp
;
94 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
|
95 label_omod2
| label_omod4
| label_omod5
| label_clamp
| label_scc_invert
;
96 static constexpr uint32_t val_labels
= label_constant
| label_constant_64bit
| label_literal
| label_mad
;
106 void add_label(Label new_label
)
108 /* Since all labels which use "instr" use it for the same thing
109 * (indicating the defining instruction), there is no need to clear
110 * any other instr labels. */
111 if (new_label
& instr_labels
)
112 label
&= ~temp_labels
; /* instr and temp alias */
114 if (new_label
& temp_labels
) {
115 label
&= ~temp_labels
;
116 label
&= ~instr_labels
; /* instr and temp alias */
119 if (new_label
& val_labels
)
120 label
&= ~val_labels
;
125 void set_vec(Instruction
* vec
)
127 add_label(label_vec
);
133 return label
& label_vec
;
136 void set_constant(uint32_t constant
)
138 add_label(label_constant
);
144 return label
& label_constant
;
147 void set_constant_64bit(uint32_t constant
)
149 add_label(label_constant_64bit
);
153 bool is_constant_64bit()
155 return label
& label_constant_64bit
;
158 void set_abs(Temp abs_temp
)
160 add_label(label_abs
);
166 return label
& label_abs
;
169 void set_neg(Temp neg_temp
)
171 add_label(label_neg
);
177 return label
& label_neg
;
180 void set_neg_abs(Temp neg_abs_temp
)
182 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
186 void set_mul(Instruction
* mul
)
188 add_label(label_mul
);
194 return label
& label_mul
;
197 void set_temp(Temp tmp
)
199 add_label(label_temp
);
205 return label
& label_temp
;
208 void set_literal(uint32_t lit
)
210 add_label(label_literal
);
216 return label
& label_literal
;
219 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
221 add_label(label_mad
);
228 return label
& label_mad
;
231 void set_omod2(Temp def
)
233 add_label(label_omod2
);
239 return label
& label_omod2
;
242 void set_omod4(Temp def
)
244 add_label(label_omod4
);
250 return label
& label_omod4
;
253 void set_omod5(Temp def
)
255 add_label(label_omod5
);
261 return label
& label_omod5
;
264 void set_omod_success(Instruction
* omod_instr
)
266 add_label(label_omod_success
);
270 bool is_omod_success()
272 return label
& label_omod_success
;
275 void set_clamp(Temp def
)
277 add_label(label_clamp
);
283 return label
& label_clamp
;
286 void set_clamp_success(Instruction
* clamp_instr
)
288 add_label(label_clamp_success
);
292 bool is_clamp_success()
294 return label
& label_clamp_success
;
299 add_label(label_undefined
);
304 return label
& label_undefined
;
307 void set_vcc(Temp vcc
)
309 add_label(label_vcc
);
315 return label
& label_vcc
;
318 bool is_constant_or_literal()
320 return is_constant() || is_literal();
323 void set_b2f(Temp val
)
325 add_label(label_b2f
);
331 return label
& label_b2f
;
334 void set_add_sub(Instruction
*add_sub_instr
)
336 add_label(label_add_sub
);
337 instr
= add_sub_instr
;
342 return label
& label_add_sub
;
345 void set_bitwise(Instruction
*bitwise_instr
)
347 add_label(label_bitwise
);
348 instr
= bitwise_instr
;
353 return label
& label_bitwise
;
356 void set_uniform_bitwise()
358 add_label(label_uniform_bitwise
);
361 bool is_uniform_bitwise()
363 return label
& label_uniform_bitwise
;
366 void set_minmax(Instruction
*minmax_instr
)
368 add_label(label_minmax
);
369 instr
= minmax_instr
;
374 return label
& label_minmax
;
377 void set_fcmp(Instruction
*fcmp_instr
)
379 add_label(label_fcmp
);
385 return label
& label_fcmp
;
388 void set_scc_needed()
390 add_label(label_scc_needed
);
395 return label
& label_scc_needed
;
398 void set_scc_invert(Temp scc_inv
)
400 add_label(label_scc_invert
);
406 return label
& label_scc_invert
;
409 void set_uniform_bool(Temp uniform_bool
)
411 add_label(label_uniform_bool
);
415 bool is_uniform_bool()
417 return label
& label_uniform_bool
;
422 add_label(label_vcc_hint
);
427 return label
& label_vcc_hint
;
433 std::vector
<aco_ptr
<Instruction
>> instructions
;
435 std::pair
<uint32_t,Temp
> last_literal
;
436 std::vector
<mad_info
> mad_infos
;
437 std::vector
<uint16_t> uses
;
440 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
442 if (instr
->operands
[0].isConstant() ||
443 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
446 switch (instr
->opcode
) {
447 case aco_opcode::v_add_f32
:
448 case aco_opcode::v_mul_f32
:
449 case aco_opcode::v_or_b32
:
450 case aco_opcode::v_and_b32
:
451 case aco_opcode::v_xor_b32
:
452 case aco_opcode::v_max_f32
:
453 case aco_opcode::v_min_f32
:
454 case aco_opcode::v_max_i32
:
455 case aco_opcode::v_min_i32
:
456 case aco_opcode::v_max_u32
:
457 case aco_opcode::v_min_u32
:
458 case aco_opcode::v_cmp_eq_f32
:
459 case aco_opcode::v_cmp_lg_f32
:
461 case aco_opcode::v_sub_f32
:
462 instr
->opcode
= aco_opcode::v_subrev_f32
;
464 case aco_opcode::v_cmp_lt_f32
:
465 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
467 case aco_opcode::v_cmp_ge_f32
:
468 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
470 case aco_opcode::v_cmp_lt_i32
:
471 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
478 bool can_use_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
483 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
486 if (instr
->isDPP() || instr
->isSDWA())
489 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
490 instr
->opcode
!= aco_opcode::v_madak_f32
&&
491 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
492 instr
->opcode
!= aco_opcode::v_madak_f16
&&
493 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
494 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
495 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
496 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
497 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
498 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
499 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
502 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
504 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
505 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
506 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
507 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
508 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
511 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
516 aco_ptr
<Instruction
> tmp
= std::move(instr
);
517 Format format
= asVOP3(tmp
->format
);
518 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
519 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
520 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
521 instr
->definitions
[i
] = tmp
->definitions
[i
];
522 if (instr
->definitions
[i
].isTemp()) {
523 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
524 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
525 info
.instr
= instr
.get();
530 /* only covers special cases */
531 bool can_accept_constant(aco_ptr
<Instruction
>& instr
, unsigned operand
)
533 switch (instr
->opcode
) {
534 case aco_opcode::v_interp_p2_f32
:
535 case aco_opcode::v_mac_f32
:
536 case aco_opcode::v_writelane_b32
:
537 case aco_opcode::v_writelane_b32_e64
:
538 case aco_opcode::v_cndmask_b32
:
540 case aco_opcode::s_addk_i32
:
541 case aco_opcode::s_mulk_i32
:
542 case aco_opcode::p_wqm
:
543 case aco_opcode::p_extract_vector
:
544 case aco_opcode::p_split_vector
:
545 case aco_opcode::v_readlane_b32
:
546 case aco_opcode::v_readlane_b32_e64
:
547 case aco_opcode::v_readfirstlane_b32
:
550 if ((instr
->format
== Format::MUBUF
||
551 instr
->format
== Format::MIMG
) &&
552 instr
->definitions
.size() == 1 &&
553 instr
->operands
.size() == 4) {
560 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
562 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
563 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
568 /* check constant bus and literal limitations */
569 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
571 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
572 Operand
literal32(s1
);
573 Operand
literal64(s2
);
574 unsigned num_sgprs
= 0;
575 unsigned sgpr
[] = {0, 0};
577 for (unsigned i
= 0; i
< num_operands
; i
++) {
578 Operand op
= operands
[i
];
580 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
581 /* two reads of the same SGPR count as 1 to the limit */
582 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
584 sgpr
[num_sgprs
++] = op
.tempId();
589 } else if (op
.isLiteral()) {
590 if (ctx
.program
->chip_class
< GFX10
)
593 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
595 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
598 /* Any number of 32-bit literals counts as only 1 to the limit. Same
599 * (but separately) for 64-bit literals. */
600 if (op
.size() == 1 && literal32
.isUndefined()) {
603 } else if (op
.size() == 2 && literal64
.isUndefined()) {
616 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
618 Operand op
= instr
->operands
[op_index
];
622 Temp tmp
= op
.getTemp();
623 if (!ctx
.info
[tmp
.id()].is_add_sub())
626 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
628 switch (add_instr
->opcode
) {
629 case aco_opcode::v_add_u32
:
630 case aco_opcode::v_add_co_u32
:
631 case aco_opcode::s_add_i32
:
632 case aco_opcode::s_add_u32
:
638 if (add_instr
->usesModifiers())
641 for (unsigned i
= 0; i
< 2; i
++) {
642 if (add_instr
->operands
[i
].isConstant()) {
643 *offset
= add_instr
->operands
[i
].constantValue();
644 } else if (add_instr
->operands
[i
].isTemp() &&
645 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
646 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
650 if (!add_instr
->operands
[!i
].isTemp())
653 uint32_t offset2
= 0;
654 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
657 *base
= add_instr
->operands
[!i
].getTemp();
665 Operand
get_constant_op(opt_ctx
&ctx
, uint32_t val
, bool is64bit
= false)
667 // TODO: this functions shouldn't be needed if we store Operand instead of value.
668 Operand
op(val
, is64bit
);
669 if (val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
670 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
674 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
676 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
677 ASSERTED
bool all_const
= false;
678 for (Operand
& op
: instr
->operands
)
679 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
680 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
683 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
685 if (!instr
->operands
[i
].isTemp())
688 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
689 /* propagate undef */
690 if (info
.is_undefined() && is_phi(instr
))
691 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
692 /* propagate reg->reg of same type */
693 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
694 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
695 info
= ctx
.info
[info
.temp
.id()];
698 /* SALU / PSEUDO: propagate inline constants */
699 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
700 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
701 instr
->operands
[i
].setTemp(info
.temp
);
702 info
= ctx
.info
[info
.temp
.id()];
703 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
704 /* propagate vgpr if it can take it */
705 switch (instr
->opcode
) {
706 case aco_opcode::p_create_vector
:
707 case aco_opcode::p_split_vector
:
708 case aco_opcode::p_extract_vector
:
709 case aco_opcode::p_phi
: {
710 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
711 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
713 instr
->operands
[i
] = Operand(info
.temp
);
714 info
= ctx
.info
[info
.temp
.id()];
722 if ((info
.is_constant() || info
.is_constant_64bit() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) && !instr
->operands
[i
].isFixed() && can_accept_constant(instr
, i
)) {
723 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
728 /* VALU: propagate neg, abs & inline constants */
729 else if (instr
->isVALU()) {
730 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
731 instr
->operands
[i
].setTemp(info
.temp
);
732 info
= ctx
.info
[info
.temp
.id()];
734 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
737 instr
->operands
[i
] = Operand(info
.temp
);
739 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
741 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
743 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
744 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
745 instr
->operands
[i
].setTemp(info
.temp
);
747 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
750 instr
->operands
[i
].setTemp(info
.temp
);
752 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
754 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
757 if ((info
.is_constant() || info
.is_constant_64bit()) && can_accept_constant(instr
, i
)) {
758 Operand op
= get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
759 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
760 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
761 instr
->operands
[i
] = op
;
763 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
764 instr
->operands
[i
] = instr
->operands
[0];
765 instr
->operands
[0] = op
;
767 } else if (can_use_VOP3(ctx
, instr
)) {
769 instr
->operands
[i
] = op
;
775 /* MUBUF: propagate constants and combine additions */
776 else if (instr
->format
== Format::MUBUF
) {
777 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
780 while (info
.is_temp())
781 info
= ctx
.info
[info
.temp
.id()];
783 if (mubuf
->offen
&& i
== 0 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
784 assert(!mubuf
->idxen
);
785 instr
->operands
[i
] = Operand(v1
);
786 mubuf
->offset
+= info
.val
;
787 mubuf
->offen
= false;
789 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
790 instr
->operands
[2] = Operand((uint32_t) 0);
791 mubuf
->offset
+= info
.val
;
793 } else if (mubuf
->offen
&& i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
794 assert(!mubuf
->idxen
);
795 instr
->operands
[i
].setTemp(base
);
796 mubuf
->offset
+= offset
;
798 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
799 instr
->operands
[i
].setTemp(base
);
800 mubuf
->offset
+= offset
;
805 /* DS: combine additions */
806 else if (instr
->format
== Format::DS
) {
808 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
811 bool has_usable_ds_offset
= ctx
.program
->chip_class
>= GFX7
;
812 if (has_usable_ds_offset
&&
813 i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) &&
814 base
.regClass() == instr
->operands
[i
].regClass() &&
815 instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
816 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
817 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
818 if (offset
% 4 == 0 &&
819 ds
->offset0
+ (offset
>> 2) <= 255 &&
820 ds
->offset1
+ (offset
>> 2) <= 255) {
821 instr
->operands
[i
].setTemp(base
);
822 ds
->offset0
+= offset
>> 2;
823 ds
->offset1
+= offset
>> 2;
826 if (ds
->offset0
+ offset
<= 65535) {
827 instr
->operands
[i
].setTemp(base
);
828 ds
->offset0
+= offset
;
834 /* SMEM: propagate constants and combine additions */
835 else if (instr
->format
== Format::SMEM
) {
837 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
840 if (i
== 1 && info
.is_constant_or_literal() &&
841 ((ctx
.program
->chip_class
== GFX6
&& info
.val
<= 0x3FF) ||
842 (ctx
.program
->chip_class
== GFX7
&& info
.val
<= 0xFFFFFFFF) ||
843 (ctx
.program
->chip_class
>= GFX8
&& info
.val
<= 0xFFFFF))) {
844 instr
->operands
[i
] = Operand(info
.val
);
846 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
847 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
849 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
850 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
854 smem
->operands
[1] = Operand(offset
);
855 smem
->operands
.back() = Operand(base
);
857 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
858 new_instr
->operands
[0] = smem
->operands
[0];
859 new_instr
->operands
[1] = Operand(offset
);
860 if (smem
->definitions
.empty())
861 new_instr
->operands
[2] = smem
->operands
[2];
862 new_instr
->operands
.back() = Operand(base
);
863 if (!smem
->definitions
.empty())
864 new_instr
->definitions
[0] = smem
->definitions
[0];
865 new_instr
->can_reorder
= smem
->can_reorder
;
866 new_instr
->barrier
= smem
->barrier
;
867 instr
.reset(new_instr
);
868 smem
= static_cast<SMEM_instruction
*>(instr
.get());
874 else if (instr
->format
== Format::PSEUDO_BRANCH
) {
875 if (ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
876 /* Flip the branch instruction to get rid of the scc_invert instruction */
877 instr
->opcode
= instr
->opcode
== aco_opcode::p_cbranch_z
? aco_opcode::p_cbranch_nz
: aco_opcode::p_cbranch_z
;
878 instr
->operands
[0].setTemp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
883 /* if this instruction doesn't define anything, return */
884 if (instr
->definitions
.empty())
887 switch (instr
->opcode
) {
888 case aco_opcode::p_create_vector
: {
889 unsigned num_ops
= instr
->operands
.size();
890 for (const Operand
& op
: instr
->operands
) {
891 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
892 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
894 if (num_ops
!= instr
->operands
.size()) {
895 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
896 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
897 instr
->definitions
[0] = old_vec
->definitions
[0];
899 for (Operand
& old_op
: old_vec
->operands
) {
900 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
901 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
902 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
903 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
904 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
905 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
906 instr
->operands
[k
++] = op
;
909 instr
->operands
[k
++] = old_op
;
912 assert(k
== num_ops
);
914 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
915 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
916 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
917 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
920 case aco_opcode::p_split_vector
: {
921 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
923 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
924 assert(instr
->definitions
.size() == vec
->operands
.size());
925 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
926 Operand vec_op
= vec
->operands
[i
];
927 if (vec_op
.isConstant()) {
928 if (vec_op
.isLiteral())
929 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
930 else if (vec_op
.size() == 1)
931 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
932 else if (vec_op
.size() == 2)
933 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant_64bit(vec_op
.constantValue());
935 assert(vec_op
.isTemp());
936 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
941 case aco_opcode::p_extract_vector
: { /* mov */
942 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
944 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
945 if (vec
->definitions
[0].getTemp().size() == vec
->operands
.size() && /* TODO: what about 64bit or other combinations? */
946 vec
->operands
[0].size() == instr
->definitions
[0].size()) {
948 /* convert this extract into a mov instruction */
949 Operand vec_op
= vec
->operands
[instr
->operands
[1].constantValue()];
950 bool is_vgpr
= instr
->definitions
[0].getTemp().type() == RegType::vgpr
;
951 aco_opcode opcode
= is_vgpr
? aco_opcode::v_mov_b32
: aco_opcode::s_mov_b32
;
952 Format format
= is_vgpr
? Format::VOP1
: Format::SOP1
;
953 instr
->opcode
= opcode
;
954 instr
->format
= format
;
955 while (instr
->operands
.size() > 1)
956 instr
->operands
.pop_back();
957 instr
->operands
[0] = vec_op
;
959 if (vec_op
.isConstant()) {
960 if (vec_op
.isLiteral())
961 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(vec_op
.constantValue());
962 else if (vec_op
.size() == 1)
963 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(vec_op
.constantValue());
964 else if (vec_op
.size() == 2)
965 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(vec_op
.constantValue());
968 assert(vec_op
.isTemp());
969 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vec_op
.getTemp());
974 case aco_opcode::s_mov_b32
: /* propagate */
975 case aco_opcode::s_mov_b64
:
976 case aco_opcode::v_mov_b32
:
977 case aco_opcode::p_as_uniform
:
978 if (instr
->definitions
[0].isFixed()) {
979 /* don't copy-propagate copies into fixed registers */
980 } else if (instr
->usesModifiers()) {
982 } else if (instr
->operands
[0].isConstant()) {
983 if (instr
->operands
[0].isLiteral())
984 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
985 else if (instr
->operands
[0].size() == 1)
986 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
987 else if (instr
->operands
[0].size() == 2)
988 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(instr
->operands
[0].constantValue());
989 } else if (instr
->operands
[0].isTemp()) {
990 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
992 assert(instr
->operands
[0].isFixed());
995 case aco_opcode::p_is_helper
:
996 if (!ctx
.program
->needs_wqm
)
997 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
999 case aco_opcode::s_movk_i32
: {
1000 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
1001 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
1002 if (v
<= 64 || v
>= 0xfffffff0)
1003 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1005 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1008 case aco_opcode::v_bfrev_b32
:
1009 case aco_opcode::s_brev_b32
: {
1010 if (instr
->operands
[0].isConstant()) {
1011 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
1012 if (v
<= 64 || v
>= 0xfffffff0)
1013 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1015 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1019 case aco_opcode::s_bfm_b32
: {
1020 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
1021 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
1022 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
1023 uint32_t v
= ((1u << size
) - 1u) << start
;
1024 if (v
<= 64 || v
>= 0xfffffff0)
1025 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1027 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1030 case aco_opcode::v_mul_f32
: { /* omod */
1031 /* TODO: try to move the negate/abs modifier to the consumer instead */
1032 if (instr
->usesModifiers())
1035 for (unsigned i
= 0; i
< 2; i
++) {
1036 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
1037 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
1038 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
1039 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
1040 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
1041 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
1042 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
1043 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000 &&
1044 !block
.fp_mode
.must_flush_denorms32
) { /* 1.0 */
1045 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
1054 case aco_opcode::v_and_b32
: /* abs */
1055 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x7FFFFFFF) &&
1056 instr
->operands
[1].isTemp() && instr
->operands
[1].getTemp().type() == RegType::vgpr
)
1057 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
1059 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1061 case aco_opcode::v_xor_b32
: { /* neg */
1062 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
1063 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
1064 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1065 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
1066 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
1067 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1068 instr
->opcode
= aco_opcode::v_or_b32
;
1069 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
1071 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
1075 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1079 case aco_opcode::v_med3_f32
: { /* clamp */
1080 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1081 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1082 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1083 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1087 bool found_zero
= false, found_one
= false;
1088 for (unsigned i
= 0; i
< 3; i
++)
1090 if (instr
->operands
[i
].constantEquals(0))
1092 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1097 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1098 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1102 case aco_opcode::v_cndmask_b32
:
1103 if (instr
->operands
[0].constantEquals(0) &&
1104 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
1105 instr
->operands
[2].isTemp())
1106 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1107 else if (instr
->operands
[0].constantEquals(0) &&
1108 instr
->operands
[1].constantEquals(0x3f800000u
) &&
1109 instr
->operands
[2].isTemp())
1110 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1112 ctx
.info
[instr
->operands
[2].tempId()].set_vcc_hint();
1114 case aco_opcode::v_cmp_lg_u32
:
1115 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1116 instr
->operands
[0].constantEquals(0) &&
1117 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1118 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1120 case aco_opcode::p_phi
:
1121 case aco_opcode::p_linear_phi
: {
1122 /* lower_bool_phis() can create phis like this */
1123 bool all_same_temp
= instr
->operands
[0].isTemp();
1124 /* this check is needed when moving uniform loop counters out of a divergent loop */
1126 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1127 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1128 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1129 all_same_temp
= false;
1131 if (all_same_temp
) {
1132 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1134 bool all_undef
= instr
->operands
[0].isUndefined();
1135 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1136 if (!instr
->operands
[i
].isUndefined())
1140 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1144 case aco_opcode::v_add_u32
:
1145 case aco_opcode::v_add_co_u32
:
1146 case aco_opcode::s_add_i32
:
1147 case aco_opcode::s_add_u32
:
1148 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1150 case aco_opcode::s_not_b32
:
1151 case aco_opcode::s_not_b64
:
1152 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1153 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1154 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1155 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1156 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1157 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1159 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1161 case aco_opcode::s_and_b32
:
1162 case aco_opcode::s_and_b64
:
1163 if (instr
->operands
[1].isFixed() && instr
->operands
[1].physReg() == exec
&& instr
->operands
[0].isTemp()) {
1164 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1165 /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
1166 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1167 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1169 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1170 /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
1171 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1172 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1177 case aco_opcode::s_or_b32
:
1178 case aco_opcode::s_or_b64
:
1179 case aco_opcode::s_xor_b32
:
1180 case aco_opcode::s_xor_b64
:
1181 if (std::all_of(instr
->operands
.begin(), instr
->operands
.end(), [&ctx
](const Operand
& op
) {
1182 return op
.isTemp() && (ctx
.info
[op
.tempId()].is_uniform_bool() || ctx
.info
[op
.tempId()].is_uniform_bitwise());
1184 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1187 case aco_opcode::s_lshl_b32
:
1188 case aco_opcode::v_or_b32
:
1189 case aco_opcode::v_lshlrev_b32
:
1190 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1192 case aco_opcode::v_min_f32
:
1193 case aco_opcode::v_min_f16
:
1194 case aco_opcode::v_min_u32
:
1195 case aco_opcode::v_min_i32
:
1196 case aco_opcode::v_min_u16
:
1197 case aco_opcode::v_min_i16
:
1198 case aco_opcode::v_max_f32
:
1199 case aco_opcode::v_max_f16
:
1200 case aco_opcode::v_max_u32
:
1201 case aco_opcode::v_max_i32
:
1202 case aco_opcode::v_max_u16
:
1203 case aco_opcode::v_max_i16
:
1204 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1206 case aco_opcode::v_cmp_lt_f32
:
1207 case aco_opcode::v_cmp_eq_f32
:
1208 case aco_opcode::v_cmp_le_f32
:
1209 case aco_opcode::v_cmp_gt_f32
:
1210 case aco_opcode::v_cmp_lg_f32
:
1211 case aco_opcode::v_cmp_ge_f32
:
1212 case aco_opcode::v_cmp_o_f32
:
1213 case aco_opcode::v_cmp_u_f32
:
1214 case aco_opcode::v_cmp_nge_f32
:
1215 case aco_opcode::v_cmp_nlg_f32
:
1216 case aco_opcode::v_cmp_ngt_f32
:
1217 case aco_opcode::v_cmp_nle_f32
:
1218 case aco_opcode::v_cmp_neq_f32
:
1219 case aco_opcode::v_cmp_nlt_f32
:
1220 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1222 case aco_opcode::s_cselect_b64
:
1223 case aco_opcode::s_cselect_b32
:
1224 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1225 instr
->operands
[1].constantEquals(0)) {
1226 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1227 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1229 if (instr
->operands
[2].isTemp() && ctx
.info
[instr
->operands
[2].tempId()].is_scc_invert()) {
1230 /* Flip the operands to get rid of the scc_invert instruction */
1231 std::swap(instr
->operands
[0], instr
->operands
[1]);
1232 instr
->operands
[2].setTemp(ctx
.info
[instr
->operands
[2].tempId()].temp
);
1235 case aco_opcode::p_wqm
:
1236 if (instr
->operands
[0].isTemp() &&
1237 ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1238 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1246 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1248 *ordered
= *unordered
= op
;
1250 #define CMP(ord, unord) \
1251 case aco_opcode::v_cmp_##ord##_f32:\
1252 case aco_opcode::v_cmp_n##unord##_f32:\
1253 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1254 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1255 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1269 aco_opcode
get_ordered(aco_opcode op
)
1271 aco_opcode ordered
, unordered
, inverse
;
1272 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1275 aco_opcode
get_unordered(aco_opcode op
)
1277 aco_opcode ordered
, unordered
, inverse
;
1278 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1281 aco_opcode
get_inverse(aco_opcode op
)
1283 aco_opcode ordered
, unordered
, inverse
;
1284 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1287 bool is_cmp(aco_opcode op
)
1289 aco_opcode ordered
, unordered
, inverse
;
1290 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1293 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1295 if (ctx
.info
[tmp
.id()].is_temp())
1296 return ctx
.info
[tmp
.id()].temp
.id();
1301 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1303 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1304 for (const Operand
& op
: instr
->operands
) {
1306 ctx
.uses
[op
.tempId()]--;
1311 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1313 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1315 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1318 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1320 if (instr
->definitions
.size() == 2) {
1321 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1322 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1329 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1330 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1331 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1333 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1335 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1338 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1340 bool neg
[2] = {false, false};
1341 bool abs
[2] = {false, false};
1343 Instruction
*op_instr
[2];
1346 for (unsigned i
= 0; i
< 2; i
++) {
1347 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1351 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1353 if (op_instr
[i
]->opcode
!= expected_cmp
)
1355 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1358 if (op_instr
[i
]->isVOP3()) {
1359 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1360 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1362 neg
[i
] = vop3
->neg
[0];
1363 abs
[i
] = vop3
->abs
[0];
1364 opsel
|= (vop3
->opsel
& 1) << i
;
1367 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1368 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1369 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1375 if (op
[1].type() == RegType::sgpr
)
1376 std::swap(op
[0], op
[1]);
1377 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1378 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1381 ctx
.uses
[op
[0].id()]++;
1382 ctx
.uses
[op
[1].id()]++;
1383 decrease_uses(ctx
, op_instr
[0]);
1384 decrease_uses(ctx
, op_instr
[1]);
1386 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1387 Instruction
*new_instr
;
1388 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1389 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1390 for (unsigned i
= 0; i
< 2; i
++) {
1391 vop3
->neg
[i
] = neg
[i
];
1392 vop3
->abs
[i
] = abs
[i
];
1394 vop3
->opsel
= opsel
;
1395 new_instr
= static_cast<Instruction
*>(vop3
);
1397 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1399 new_instr
->operands
[0] = Operand(op
[0]);
1400 new_instr
->operands
[1] = Operand(op
[1]);
1401 new_instr
->definitions
[0] = instr
->definitions
[0];
1403 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1404 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1406 instr
.reset(new_instr
);
1411 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1412 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1413 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1415 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1417 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1420 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1421 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1423 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1424 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1425 if (!nan_test
|| !cmp
)
1428 if (cmp
->opcode
== expected_nan_test
)
1429 std::swap(nan_test
, cmp
);
1430 else if (nan_test
->opcode
!= expected_nan_test
)
1433 if (!is_cmp(cmp
->opcode
))
1436 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1438 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1441 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1442 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1443 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1444 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1445 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1447 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1450 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1451 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1452 decrease_uses(ctx
, nan_test
);
1453 decrease_uses(ctx
, cmp
);
1455 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1456 Instruction
*new_instr
;
1457 if (cmp
->isVOP3()) {
1458 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1459 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1460 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1461 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1462 new_vop3
->clamp
= cmp_vop3
->clamp
;
1463 new_vop3
->omod
= cmp_vop3
->omod
;
1464 new_vop3
->opsel
= cmp_vop3
->opsel
;
1465 new_instr
= new_vop3
;
1467 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1469 new_instr
->operands
[0] = cmp
->operands
[0];
1470 new_instr
->operands
[1] = cmp
->operands
[1];
1471 new_instr
->definitions
[0] = instr
->definitions
[0];
1473 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1474 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1476 instr
.reset(new_instr
);
1481 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1482 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1483 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1485 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1487 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1490 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1492 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1493 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1495 if (!nan_test
|| !cmp
)
1498 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1499 if (cmp
->opcode
== expected_nan_test
)
1500 std::swap(nan_test
, cmp
);
1501 else if (nan_test
->opcode
!= expected_nan_test
)
1504 if (!is_cmp(cmp
->opcode
))
1507 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1509 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1512 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1513 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1514 if (prop_nan0
!= prop_nan1
)
1517 if (nan_test
->isVOP3()) {
1518 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1519 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1523 int constant_operand
= -1;
1524 for (unsigned i
= 0; i
< 2; i
++) {
1525 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1526 constant_operand
= !i
;
1530 if (constant_operand
== -1)
1534 if (cmp
->operands
[constant_operand
].isConstant()) {
1535 constant
= cmp
->operands
[constant_operand
].constantValue();
1536 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1537 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1538 unsigned id
= original_temp_id(ctx
, tmp
);
1539 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1541 constant
= ctx
.info
[id
].val
;
1547 memcpy(&constantf
, &constant
, 4);
1548 if (isnan(constantf
))
1551 if (cmp
->operands
[0].isTemp())
1552 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1553 if (cmp
->operands
[1].isTemp())
1554 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1555 decrease_uses(ctx
, nan_test
);
1556 decrease_uses(ctx
, cmp
);
1558 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1559 Instruction
*new_instr
;
1560 if (cmp
->isVOP3()) {
1561 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1562 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1563 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1564 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1565 new_vop3
->clamp
= cmp_vop3
->clamp
;
1566 new_vop3
->omod
= cmp_vop3
->omod
;
1567 new_vop3
->opsel
= cmp_vop3
->opsel
;
1568 new_instr
= new_vop3
;
1570 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1572 new_instr
->operands
[0] = cmp
->operands
[0];
1573 new_instr
->operands
[1] = cmp
->operands
[1];
1574 new_instr
->definitions
[0] = instr
->definitions
[0];
1576 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1577 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1579 instr
.reset(new_instr
);
1584 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1585 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1587 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1589 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1591 if (!instr
->operands
[0].isTemp())
1594 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1598 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1599 if (new_opcode
== aco_opcode::last_opcode
)
1602 if (cmp
->operands
[0].isTemp())
1603 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1604 if (cmp
->operands
[1].isTemp())
1605 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1606 decrease_uses(ctx
, cmp
);
1608 Instruction
*new_instr
;
1609 if (cmp
->isVOP3()) {
1610 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1611 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1612 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1613 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1614 new_vop3
->clamp
= cmp_vop3
->clamp
;
1615 new_vop3
->omod
= cmp_vop3
->omod
;
1616 new_vop3
->opsel
= cmp_vop3
->opsel
;
1617 new_instr
= new_vop3
;
1619 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1621 new_instr
->operands
[0] = cmp
->operands
[0];
1622 new_instr
->operands
[1] = cmp
->operands
[1];
1623 new_instr
->definitions
[0] = instr
->definitions
[0];
1625 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1626 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1628 instr
.reset(new_instr
);
1633 /* op1(op2(1, 2), 0) if swap = false
1634 * op1(0, op2(1, 2)) if swap = true */
1635 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1636 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1637 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1638 bool *op1_clamp
, uint8_t *op1_omod
,
1639 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1642 if (op1_instr
->opcode
!= op1
)
1645 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1646 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1649 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1650 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1652 /* don't support inbetween clamp/omod */
1653 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1656 /* get operands and modifiers and check inbetween modifiers */
1657 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1658 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1661 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1662 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1666 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1667 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1670 if (inbetween_opsel
)
1671 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1672 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1676 shuffle
[shuffle_str
[0] - '0'] = 0;
1677 shuffle
[shuffle_str
[1] - '0'] = 1;
1678 shuffle
[shuffle_str
[2] - '0'] = 2;
1680 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1681 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1682 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1683 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1684 *opsel
|= 1 << shuffle
[0];
1686 for (unsigned i
= 0; i
< 2; i
++) {
1687 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1688 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1689 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1690 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1691 *opsel
|= 1 << shuffle
[i
+ 1];
1694 /* check operands */
1695 if (!check_vop3_operands(ctx
, 3, operands
))
1701 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1702 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1703 bool clamp
, unsigned omod
)
1705 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1706 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1707 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1708 new_instr
->clamp
= clamp
;
1709 new_instr
->omod
= omod
;
1710 new_instr
->opsel
= opsel
;
1711 new_instr
->operands
[0] = operands
[0];
1712 new_instr
->operands
[1] = operands
[1];
1713 new_instr
->operands
[2] = operands
[2];
1714 new_instr
->definitions
[0] = instr
->definitions
[0];
1715 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1717 instr
.reset(new_instr
);
1720 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1722 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1723 (label_omod_success
| label_clamp_success
);
1725 for (unsigned swap
= 0; swap
< 2; swap
++) {
1726 if (!((1 << swap
) & ops
))
1729 Operand operands
[3];
1730 bool neg
[3], abs
[3], clamp
;
1731 uint8_t opsel
= 0, omod
= 0;
1732 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1733 instr
.get(), swap
, shuffle
,
1734 operands
, neg
, abs
, &opsel
,
1735 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1736 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1737 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1738 if (omod_clamp
& label_omod_success
)
1739 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1740 if (omod_clamp
& label_clamp_success
)
1741 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1748 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
1750 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
1753 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1754 (label_omod_success
| label_clamp_success
);
1756 /* min(-max(a, b), c) -> min3(-a, -b, c) *
1757 * max(-min(a, b), c) -> max3(-a, -b, c) */
1758 for (unsigned swap
= 0; swap
< 2; swap
++) {
1759 Operand operands
[3];
1760 bool neg
[3], abs
[3], clamp
;
1761 uint8_t opsel
= 0, omod
= 0;
1763 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
1764 instr
.get(), swap
, "012",
1765 operands
, neg
, abs
, &opsel
,
1766 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
1768 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1771 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1772 if (omod_clamp
& label_omod_success
)
1773 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1774 if (omod_clamp
& label_clamp_success
)
1775 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1782 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1783 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1784 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1785 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1786 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1787 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1788 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1791 if (!instr
->operands
[0].isTemp())
1793 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1796 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1799 switch (op2_instr
->opcode
) {
1800 case aco_opcode::s_and_b32
:
1801 case aco_opcode::s_or_b32
:
1802 case aco_opcode::s_xor_b32
:
1803 case aco_opcode::s_and_b64
:
1804 case aco_opcode::s_or_b64
:
1805 case aco_opcode::s_xor_b64
:
1811 /* create instruction */
1812 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1813 std::swap(instr
->definitions
[1], op2_instr
->definitions
[1]);
1814 ctx
.uses
[instr
->operands
[0].tempId()]--;
1815 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1817 switch (op2_instr
->opcode
) {
1818 case aco_opcode::s_and_b32
:
1819 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1821 case aco_opcode::s_or_b32
:
1822 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1824 case aco_opcode::s_xor_b32
:
1825 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1827 case aco_opcode::s_and_b64
:
1828 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1830 case aco_opcode::s_or_b64
:
1831 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1833 case aco_opcode::s_xor_b64
:
1834 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1843 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1844 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1845 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1846 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1847 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1849 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1852 for (unsigned i
= 0; i
< 2; i
++) {
1853 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1854 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1857 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1858 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1861 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1862 instr
->operands
[0] = instr
->operands
[!i
];
1863 instr
->operands
[1] = op2_instr
->operands
[0];
1864 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1866 switch (instr
->opcode
) {
1867 case aco_opcode::s_and_b32
:
1868 instr
->opcode
= aco_opcode::s_andn2_b32
;
1870 case aco_opcode::s_or_b32
:
1871 instr
->opcode
= aco_opcode::s_orn2_b32
;
1873 case aco_opcode::s_and_b64
:
1874 instr
->opcode
= aco_opcode::s_andn2_b64
;
1876 case aco_opcode::s_or_b64
:
1877 instr
->opcode
= aco_opcode::s_orn2_b64
;
1888 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1889 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1891 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1894 for (unsigned i
= 0; i
< 2; i
++) {
1895 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1896 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
|| !op2_instr
->operands
[1].isConstant())
1899 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1900 if (shift
< 1 || shift
> 4)
1903 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1904 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1907 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1908 instr
->operands
[1] = instr
->operands
[!i
];
1909 instr
->operands
[0] = op2_instr
->operands
[0];
1910 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1912 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1913 aco_opcode::s_lshl2_add_u32
,
1914 aco_opcode::s_lshl3_add_u32
,
1915 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1922 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1925 #define MINMAX(type, gfx9) \
1926 case aco_opcode::v_min_##type:\
1927 case aco_opcode::v_max_##type:\
1928 case aco_opcode::v_med3_##type:\
1929 *min = aco_opcode::v_min_##type;\
1930 *max = aco_opcode::v_max_##type;\
1931 *med3 = aco_opcode::v_med3_##type;\
1932 *min3 = aco_opcode::v_min3_##type;\
1933 *max3 = aco_opcode::v_max3_##type;\
1934 *some_gfx9_only = gfx9;\
1948 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1949 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1950 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1951 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1953 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
1954 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
1955 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
1956 aco_opcode other_op
;
1957 if (instr
->opcode
== min
)
1959 else if (instr
->opcode
== max
)
1964 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1965 (label_omod_success
| label_clamp_success
);
1967 for (unsigned swap
= 0; swap
< 2; swap
++) {
1968 Operand operands
[3];
1969 bool neg
[3], abs
[3], clamp
;
1970 uint8_t opsel
= 0, omod
= 0;
1971 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1972 "012", operands
, neg
, abs
, &opsel
,
1973 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1974 int const0_idx
= -1, const1_idx
= -1;
1975 uint32_t const0
= 0, const1
= 0;
1976 for (int i
= 0; i
< 3; i
++) {
1978 if (operands
[i
].isConstant()) {
1979 val
= operands
[i
].constantValue();
1980 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
1981 val
= ctx
.info
[operands
[i
].tempId()].val
;
1985 if (const0_idx
>= 0) {
1993 if (const0_idx
< 0 || const1_idx
< 0)
1996 if (opsel
& (1 << const0_idx
))
1998 if (opsel
& (1 << const1_idx
))
2001 int lower_idx
= const0_idx
;
2003 case aco_opcode::v_min_f32
:
2004 case aco_opcode::v_min_f16
: {
2005 float const0_f
, const1_f
;
2006 if (min
== aco_opcode::v_min_f32
) {
2007 memcpy(&const0_f
, &const0
, 4);
2008 memcpy(&const1_f
, &const1
, 4);
2010 const0_f
= _mesa_half_to_float(const0
);
2011 const1_f
= _mesa_half_to_float(const1
);
2013 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
2014 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
2015 if (neg
[const0_idx
]) const0_f
= -const0_f
;
2016 if (neg
[const1_idx
]) const1_f
= -const1_f
;
2017 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
2020 case aco_opcode::v_min_u32
: {
2021 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
2024 case aco_opcode::v_min_u16
: {
2025 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
2028 case aco_opcode::v_min_i32
: {
2029 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
2030 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
2031 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2034 case aco_opcode::v_min_i16
: {
2035 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
2036 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
2037 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2043 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
2045 if (instr
->opcode
== min
) {
2046 if (upper_idx
!= 0 || lower_idx
== 0)
2049 if (upper_idx
== 0 || lower_idx
!= 0)
2053 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2054 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2055 if (omod_clamp
& label_omod_success
)
2056 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2057 if (omod_clamp
& label_clamp_success
)
2058 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2068 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2070 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2071 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2072 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2074 /* find candidates and create the set of sgprs already read */
2075 unsigned sgpr_ids
[2] = {0, 0};
2076 uint32_t operand_mask
= 0;
2077 bool has_literal
= false;
2078 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2079 if (instr
->operands
[i
].isLiteral())
2081 if (!instr
->operands
[i
].isTemp())
2083 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2084 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
2085 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
2087 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
2088 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
2089 operand_mask
|= 1u << i
;
2091 unsigned max_sgprs
= 1;
2092 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2097 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2099 /* keep on applying sgprs until there is nothing left to be done */
2100 while (operand_mask
) {
2101 uint32_t sgpr_idx
= 0;
2102 uint32_t sgpr_info_id
= 0;
2103 uint32_t mask
= operand_mask
;
2106 unsigned i
= u_bit_scan(&mask
);
2107 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2108 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
2110 sgpr_info_id
= instr
->operands
[i
].tempId();
2113 operand_mask
&= ~(1u << sgpr_idx
);
2115 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2116 * definitively beneficial.
2117 * TODO: this is too conservative because later the use count could be reduced to 1 */
2118 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2121 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2122 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2123 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2126 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2127 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2128 } else if (can_swap_operands(instr
)) {
2129 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2130 instr
->operands
[0] = Operand(sgpr
);
2131 /* swap bits using a 4-entry LUT */
2132 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2133 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2134 } else if (can_use_VOP3(ctx
, instr
)) {
2135 to_VOP3(ctx
, instr
);
2136 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2142 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2143 ctx
.uses
[sgpr_info_id
]--;
2144 ctx
.uses
[sgpr
.id()]++;
2148 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2150 /* check if we could apply omod on predecessor */
2151 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
2152 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2153 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2155 unsigned idx
= op0
? 0 : 1;
2156 /* omod was successfully applied */
2157 /* if the omod instruction is v_mad, we also have to change the original add */
2158 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2159 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2160 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2161 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2162 add_instr
->definitions
[0] = instr
->definitions
[0];
2165 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2166 /* check if we have an additional clamp modifier */
2167 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2168 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2169 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2170 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2172 /* change definition ssa-id of modified instruction */
2173 omod_instr
->definitions
[0] = instr
->definitions
[0];
2175 /* change the definition of instr to something unused, e.g. the original omod def */
2176 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2177 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2180 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2181 /* in all other cases, label this instruction as option for multiply-add */
2182 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2186 /* check if we could apply clamp on predecessor */
2187 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
2189 bool found_zero
= false, found_one
= false;
2190 for (unsigned i
= 0; i
< 3; i
++)
2192 if (instr
->operands
[i
].constantEquals(0))
2194 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
2199 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2200 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2201 /* clamp was successfully applied */
2202 /* if the clamp instruction is v_mad, we also have to change the original add */
2203 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2204 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2205 add_instr
->definitions
[0] = instr
->definitions
[0];
2207 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2208 /* change definition ssa-id of modified instruction */
2209 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2211 /* change the definition of instr to something unused, e.g. the original omod def */
2212 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2213 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2218 /* omod has no effect if denormals are enabled */
2219 bool can_use_omod
= block
.fp_mode
.denorm32
== 0;
2221 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2222 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2223 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2224 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2225 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2226 to_VOP3(ctx
, instr
);
2227 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2228 def_info
.set_omod_success(instr
.get());
2229 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2230 to_VOP3(ctx
, instr
);
2231 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2232 def_info
.set_omod_success(instr
.get());
2233 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2234 to_VOP3(ctx
, instr
);
2235 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2236 def_info
.set_omod_success(instr
.get());
2237 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2238 to_VOP3(ctx
, instr
);
2239 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2240 def_info
.set_clamp_success(instr
.get());
2247 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2248 // this would mean that we'd have to fix the instruction uses while value propagation
2250 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2252 if (instr
->definitions
.empty() || is_dead(ctx
.uses
, instr
.get()))
2255 if (instr
->isVALU()) {
2256 if (can_apply_sgprs(instr
))
2257 apply_sgprs(ctx
, instr
);
2258 if (apply_omod_clamp(ctx
, block
, instr
))
2262 if (ctx
.info
[instr
->definitions
[0].tempId()].is_vcc_hint()) {
2263 instr
->definitions
[0].setHint(vcc
);
2266 /* TODO: There are still some peephole optimizations that could be done:
2267 * - abs(a - b) -> s_absdiff_i32
2268 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2269 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2270 * These aren't probably too interesting though.
2271 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2272 * probably more useful than the previously mentioned optimizations.
2273 * The various comparison optimizations also currently only work with 32-bit
2276 /* neg(mul(a, b)) -> mul(neg(a), b) */
2277 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2278 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2280 if (!ctx
.info
[val
.id()].is_mul())
2283 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2285 if (mul_instr
->operands
[0].isLiteral())
2287 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2290 /* convert to mul(neg(a), b) */
2291 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2292 Definition def
= instr
->definitions
[0];
2293 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2294 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2295 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2296 instr
->operands
[0] = mul_instr
->operands
[0];
2297 instr
->operands
[1] = mul_instr
->operands
[1];
2298 instr
->definitions
[0] = def
;
2299 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2300 if (mul_instr
->isVOP3()) {
2301 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2302 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2303 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2304 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2305 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2306 new_mul
->omod
= mul
->omod
;
2308 new_mul
->neg
[0] ^= true;
2309 new_mul
->clamp
= false;
2311 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2314 /* combine mul+add -> mad */
2315 else if ((instr
->opcode
== aco_opcode::v_add_f32
||
2316 instr
->opcode
== aco_opcode::v_sub_f32
||
2317 instr
->opcode
== aco_opcode::v_subrev_f32
) &&
2318 block
.fp_mode
.denorm32
== 0 && !block
.fp_mode
.preserve_signed_zero_inf_nan32
) {
2319 //TODO: we could use fma instead when denormals are enabled if the NIR isn't marked as precise
2321 uint32_t uses_src0
= UINT32_MAX
;
2322 uint32_t uses_src1
= UINT32_MAX
;
2323 Instruction
* mul_instr
= nullptr;
2324 unsigned add_op_idx
;
2325 /* check if any of the operands is a multiplication */
2326 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2327 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2328 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2329 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2331 /* find the 'best' mul instruction to combine with the add */
2332 if (uses_src0
< uses_src1
) {
2333 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2335 } else if (uses_src1
< uses_src0
) {
2336 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2338 } else if (uses_src0
!= UINT32_MAX
) {
2339 /* tiebreaker: quite random what to pick */
2340 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2341 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2344 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2349 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2350 bool neg
[3] = {false, false, false};
2351 bool abs
[3] = {false, false, false};
2354 op
[0] = mul_instr
->operands
[0];
2355 op
[1] = mul_instr
->operands
[1];
2356 op
[2] = instr
->operands
[add_op_idx
];
2357 // TODO: would be better to check this before selecting a mul instr?
2358 if (!check_vop3_operands(ctx
, 3, op
))
2361 if (mul_instr
->isVOP3()) {
2362 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2363 neg
[0] = vop3
->neg
[0];
2364 neg
[1] = vop3
->neg
[1];
2365 abs
[0] = vop3
->abs
[0];
2366 abs
[1] = vop3
->abs
[1];
2367 /* we cannot use these modifiers between mul and add */
2368 if (vop3
->clamp
|| vop3
->omod
)
2372 /* convert to mad */
2373 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2374 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2376 ctx
.uses
[op
[0].tempId()]++;
2378 ctx
.uses
[op
[1].tempId()]++;
2381 if (instr
->isVOP3()) {
2382 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2383 neg
[2] = vop3
->neg
[add_op_idx
];
2384 abs
[2] = vop3
->abs
[add_op_idx
];
2386 clamp
= vop3
->clamp
;
2387 /* abs of the multiplication result */
2388 if (vop3
->abs
[1 - add_op_idx
]) {
2394 /* neg of the multiplication result */
2395 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2397 if (instr
->opcode
== aco_opcode::v_sub_f32
)
2398 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2399 else if (instr
->opcode
== aco_opcode::v_subrev_f32
)
2400 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2402 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2403 for (unsigned i
= 0; i
< 3; i
++)
2405 mad
->operands
[i
] = op
[i
];
2406 mad
->neg
[i
] = neg
[i
];
2407 mad
->abs
[i
] = abs
[i
];
2411 mad
->definitions
[0] = instr
->definitions
[0];
2413 /* mark this ssa_def to be re-checked for profitability and literals */
2414 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2415 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2416 instr
.reset(mad
.release());
2420 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2421 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2422 for (unsigned i
= 0; i
< 2; i
++) {
2423 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2424 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2425 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2426 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2427 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2429 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2430 new_instr
->operands
[0] = Operand(0u);
2431 new_instr
->operands
[1] = instr
->operands
[!i
];
2432 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2433 new_instr
->definitions
[0] = instr
->definitions
[0];
2434 instr
.reset(new_instr
.release());
2435 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2439 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2440 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2441 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2442 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2443 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2444 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2445 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2446 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2447 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2448 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2449 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2450 combine_salu_lshl_add(ctx
, instr
);
2451 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2452 combine_salu_not_bitwise(ctx
, instr
);
2453 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2454 if (combine_inverse_comparison(ctx
, instr
)) ;
2455 else combine_salu_not_bitwise(ctx
, instr
);
2456 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2457 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2458 if (combine_ordering_test(ctx
, instr
)) ;
2459 else if (combine_comparison_ordering(ctx
, instr
)) ;
2460 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2461 else combine_salu_n2(ctx
, instr
);
2463 aco_opcode min
, max
, min3
, max3
, med3
;
2464 bool some_gfx9_only
;
2465 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2466 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2467 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2468 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2473 bool to_uniform_bool_instr(opt_ctx
&ctx
, aco_ptr
<Instruction
> &instr
)
2475 switch (instr
->opcode
) {
2476 case aco_opcode::s_and_b32
:
2477 case aco_opcode::s_and_b64
:
2478 instr
->opcode
= aco_opcode::s_and_b32
;
2480 case aco_opcode::s_or_b32
:
2481 case aco_opcode::s_or_b64
:
2482 instr
->opcode
= aco_opcode::s_or_b32
;
2484 case aco_opcode::s_xor_b32
:
2485 case aco_opcode::s_xor_b64
:
2486 instr
->opcode
= aco_opcode::s_absdiff_i32
;
2489 /* Don't transform other instructions. They are very unlikely to appear here. */
2493 for (Operand
&op
: instr
->operands
) {
2494 ctx
.uses
[op
.tempId()]--;
2496 if (ctx
.info
[op
.tempId()].is_uniform_bool()) {
2497 /* Just use the uniform boolean temp. */
2498 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
2499 } else if (ctx
.info
[op
.tempId()].is_uniform_bitwise()) {
2500 /* Use the SCC definition of the predecessor instruction.
2501 * This allows the predecessor to get picked up by the same optimization (if it has no divergent users),
2502 * and it also makes sure that the current instruction will keep working even if the predecessor won't be transformed.
2504 Instruction
*pred_instr
= ctx
.info
[op
.tempId()].instr
;
2505 assert(pred_instr
->definitions
.size() >= 2);
2506 assert(pred_instr
->definitions
[1].isFixed() && pred_instr
->definitions
[1].physReg() == scc
);
2507 op
.setTemp(pred_instr
->definitions
[1].getTemp());
2509 unreachable("Invalid operand on uniform bitwise instruction.");
2512 ctx
.uses
[op
.tempId()]++;
2515 instr
->definitions
[0].setTemp(Temp(instr
->definitions
[0].tempId(), s1
));
2516 assert(instr
->operands
[0].regClass() == s1
);
2517 assert(instr
->operands
[1].regClass() == s1
);
2521 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2523 const uint32_t threshold
= 4;
2525 if (is_dead(ctx
.uses
, instr
.get())) {
2530 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2531 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2532 unsigned num_used
= 0;
2534 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2535 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2541 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2542 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2543 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2547 for (Operand
& vec_op
: vec
->operands
) {
2548 if (off
== idx
* instr
->definitions
[0].size()) {
2552 off
+= vec_op
.size();
2554 if (off
!= instr
->operands
[0].size()) {
2555 ctx
.uses
[instr
->operands
[0].tempId()]--;
2556 for (Operand
& vec_op
: vec
->operands
) {
2557 if (vec_op
.isTemp())
2558 ctx
.uses
[vec_op
.tempId()]--;
2561 ctx
.uses
[op
.tempId()]++;
2563 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2564 extract
->operands
[0] = op
;
2565 extract
->definitions
[0] = instr
->definitions
[idx
];
2566 instr
.reset(extract
.release());
2572 if (!done
&& num_used
== 1) {
2573 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2574 extract
->operands
[0] = instr
->operands
[0];
2575 extract
->operands
[1] = Operand((uint32_t) idx
);
2576 extract
->definitions
[0] = instr
->definitions
[idx
];
2577 instr
.reset(extract
.release());
2581 mad_info
* mad_info
= NULL
;
2582 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2583 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2584 /* re-check mad instructions */
2585 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2586 ctx
.uses
[mad_info
->mul_temp_id
]++;
2587 if (instr
->operands
[0].isTemp())
2588 ctx
.uses
[instr
->operands
[0].tempId()]--;
2589 if (instr
->operands
[1].isTemp())
2590 ctx
.uses
[instr
->operands
[1].tempId()]--;
2591 instr
.swap(mad_info
->add_instr
);
2594 /* check literals */
2595 else if (!instr
->usesModifiers()) {
2596 bool sgpr_used
= false;
2597 uint32_t literal_idx
= 0;
2598 uint32_t literal_uses
= UINT32_MAX
;
2599 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2601 if (instr
->operands
[i
].isConstant() && i
> 0) {
2602 literal_uses
= UINT32_MAX
;
2605 if (!instr
->operands
[i
].isTemp())
2607 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2608 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2609 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2610 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2613 literal_uses
= UINT32_MAX
;
2616 /* don't break because we still need to check constants */
2617 } else if (!sgpr_used
&&
2618 ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2619 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2620 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2624 if (literal_uses
< threshold
) {
2625 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2626 mad_info
->check_literal
= true;
2627 mad_info
->literal_idx
= literal_idx
;
2633 /* Mark SCC needed, so the uniform boolean transformation won't swap the definitions when it isn't beneficial */
2634 if (instr
->format
== Format::PSEUDO_BRANCH
&&
2635 instr
->operands
.size() &&
2636 instr
->operands
[0].isTemp()) {
2637 ctx
.info
[instr
->operands
[0].tempId()].set_scc_needed();
2639 } else if ((instr
->opcode
== aco_opcode::s_cselect_b64
||
2640 instr
->opcode
== aco_opcode::s_cselect_b32
) &&
2641 instr
->operands
[2].isTemp()) {
2642 ctx
.info
[instr
->operands
[2].tempId()].set_scc_needed();
2645 /* check for literals */
2646 if (!instr
->isSALU() && !instr
->isVALU())
2649 /* Transform uniform bitwise boolean operations to 32-bit when there are no divergent uses. */
2650 if (instr
->definitions
.size() &&
2651 ctx
.uses
[instr
->definitions
[0].tempId()] == 0 &&
2652 ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bitwise()) {
2653 bool transform_done
= to_uniform_bool_instr(ctx
, instr
);
2655 if (transform_done
&& !ctx
.info
[instr
->definitions
[1].tempId()].is_scc_needed()) {
2656 /* Swap the two definition IDs in order to avoid overusing the SCC. This reduces extra moves generated by RA. */
2657 uint32_t def0_id
= instr
->definitions
[0].getTemp().id();
2658 uint32_t def1_id
= instr
->definitions
[1].getTemp().id();
2659 instr
->definitions
[0].setTemp(Temp(def1_id
, s1
));
2660 instr
->definitions
[1].setTemp(Temp(def0_id
, s1
));
2666 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
2667 return; /* some encodings can't ever take literals */
2669 /* we do not apply the literals yet as we don't know if it is profitable */
2670 Operand
current_literal(s1
);
2672 unsigned literal_id
= 0;
2673 unsigned literal_uses
= UINT32_MAX
;
2674 Operand
literal(s1
);
2675 unsigned num_operands
= 1;
2676 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
2677 num_operands
= instr
->operands
.size();
2678 /* catch VOP2 with a 3rd SGPR operand (e.g. v_cndmask_b32, v_addc_co_u32) */
2679 else if (instr
->isVALU() && instr
->operands
.size() >= 3)
2682 unsigned sgpr_ids
[2] = {0, 0};
2683 bool is_literal_sgpr
= false;
2686 /* choose a literal to apply */
2687 for (unsigned i
= 0; i
< num_operands
; i
++) {
2688 Operand op
= instr
->operands
[i
];
2690 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
2691 op
.tempId() != sgpr_ids
[0])
2692 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
2694 if (op
.isLiteral()) {
2695 current_literal
= op
;
2697 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal()) {
2701 if (!can_accept_constant(instr
, i
))
2704 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
2705 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
2707 literal
= Operand(ctx
.info
[op
.tempId()].val
);
2708 literal_uses
= ctx
.uses
[op
.tempId()];
2709 literal_id
= op
.tempId();
2712 mask
|= (op
.tempId() == literal_id
) << i
;
2716 /* don't go over the constant bus limit */
2717 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2718 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2719 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2720 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
2721 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2722 const_bus_limit
= 2;
2724 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2725 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
2728 if (literal_id
&& literal_uses
< threshold
&&
2729 (current_literal
.isUndefined() ||
2730 (current_literal
.size() == literal
.size() &&
2731 current_literal
.constantValue() == literal
.constantValue()))) {
2732 /* mark the literal to be applied */
2734 unsigned i
= u_bit_scan(&mask
);
2735 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
2736 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2742 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2744 /* Cleanup Dead Instructions */
2748 /* apply literals on MAD */
2749 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2750 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2751 if (info
->check_literal
&& ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0) {
2752 aco_ptr
<Instruction
> new_mad
;
2753 if (info
->literal_idx
== 2) { /* add literal -> madak */
2754 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2755 new_mad
->operands
[0] = instr
->operands
[0];
2756 new_mad
->operands
[1] = instr
->operands
[1];
2757 } else { /* mul literal -> madmk */
2758 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2759 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2760 new_mad
->operands
[1] = instr
->operands
[2];
2762 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2763 new_mad
->definitions
[0] = instr
->definitions
[0];
2764 ctx
.instructions
.emplace_back(std::move(new_mad
));
2769 /* apply literals on other SALU/VALU */
2770 if (instr
->isSALU() || instr
->isVALU()) {
2771 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2772 Operand op
= instr
->operands
[i
];
2773 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal() && ctx
.uses
[op
.tempId()] == 0) {
2774 Operand
literal(ctx
.info
[op
.tempId()].val
);
2775 if (instr
->isVALU() && i
> 0)
2776 to_VOP3(ctx
, instr
);
2777 instr
->operands
[i
] = literal
;
2782 ctx
.instructions
.emplace_back(std::move(instr
));
2786 void optimize(Program
* program
)
2789 ctx
.program
= program
;
2790 std::vector
<ssa_info
> info(program
->peekAllocationId());
2791 ctx
.info
= info
.data();
2793 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2794 for (Block
& block
: program
->blocks
) {
2795 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2796 label_instruction(ctx
, block
, instr
);
2799 ctx
.uses
= std::move(dead_code_analysis(program
));
2801 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2802 for (Block
& block
: program
->blocks
) {
2803 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2804 combine_instruction(ctx
, block
, instr
);
2807 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2808 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2809 Block
* block
= &(*it
);
2810 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2811 select_instruction(ctx
, *it
);
2814 /* 4. Add literals to instructions */
2815 for (Block
& block
: program
->blocks
) {
2816 ctx
.instructions
.clear();
2817 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2818 apply_literals(ctx
, instr
);
2819 block
.instructions
.swap(ctx
.instructions
);