2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
59 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
, bool vop3
)
60 : add_instr(std::move(instr
)), mul_temp_id(id
), needs_vop3(vop3
), check_literal(false) {}
65 label_constant
= 1 << 1,
70 label_literal
= 1 << 6,
74 label_omod5
= 1 << 10,
75 label_omod_success
= 1 << 11,
76 label_clamp
= 1 << 12,
77 label_clamp_success
= 1 << 13,
78 label_undefined
= 1 << 14,
81 label_add_sub
= 1 << 17,
82 label_bitwise
= 1 << 18,
83 label_minmax
= 1 << 19,
85 label_uniform_bool
= 1 << 21,
88 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
| label_add_sub
| label_bitwise
| label_minmax
| label_fcmp
;
89 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
;
90 static constexpr uint32_t val_labels
= label_constant
| label_literal
| label_mad
;
100 void add_label(Label new_label
)
102 /* Since all labels which use "instr" use it for the same thing
103 * (indicating the defining instruction), there is no need to clear
104 * any other instr labels. */
105 if (new_label
& instr_labels
)
106 label
&= ~temp_labels
; /* instr and temp alias */
108 if (new_label
& temp_labels
) {
109 label
&= ~temp_labels
;
110 label
&= ~instr_labels
; /* instr and temp alias */
113 if (new_label
& val_labels
)
114 label
&= ~val_labels
;
119 void set_vec(Instruction
* vec
)
121 add_label(label_vec
);
127 return label
& label_vec
;
130 void set_constant(uint32_t constant
)
132 add_label(label_constant
);
138 return label
& label_constant
;
141 void set_abs(Temp abs_temp
)
143 add_label(label_abs
);
149 return label
& label_abs
;
152 void set_neg(Temp neg_temp
)
154 add_label(label_neg
);
160 return label
& label_neg
;
163 void set_neg_abs(Temp neg_abs_temp
)
165 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
169 void set_mul(Instruction
* mul
)
171 add_label(label_mul
);
177 return label
& label_mul
;
180 void set_temp(Temp tmp
)
182 add_label(label_temp
);
188 return label
& label_temp
;
191 void set_literal(uint32_t lit
)
193 add_label(label_literal
);
199 return label
& label_literal
;
202 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
204 add_label(label_mad
);
211 return label
& label_mad
;
216 add_label(label_omod2
);
221 return label
& label_omod2
;
226 add_label(label_omod4
);
231 return label
& label_omod4
;
236 add_label(label_omod5
);
241 return label
& label_omod5
;
244 void set_omod_success(Instruction
* omod_instr
)
246 add_label(label_omod_success
);
250 bool is_omod_success()
252 return label
& label_omod_success
;
257 add_label(label_clamp
);
262 return label
& label_clamp
;
265 void set_clamp_success(Instruction
* clamp_instr
)
267 add_label(label_clamp_success
);
271 bool is_clamp_success()
273 return label
& label_clamp_success
;
278 add_label(label_undefined
);
283 return label
& label_undefined
;
286 void set_vcc(Temp vcc
)
288 add_label(label_vcc
);
294 return label
& label_vcc
;
297 bool is_constant_or_literal()
299 return is_constant() || is_literal();
302 void set_b2f(Temp val
)
304 add_label(label_b2f
);
310 return label
& label_b2f
;
313 void set_add_sub(Instruction
*add_sub_instr
)
315 add_label(label_add_sub
);
316 instr
= add_sub_instr
;
321 return label
& label_add_sub
;
324 void set_bitwise(Instruction
*bitwise_instr
)
326 add_label(label_bitwise
);
327 instr
= bitwise_instr
;
332 return label
& label_bitwise
;
335 void set_minmax(Instruction
*minmax_instr
)
337 add_label(label_minmax
);
338 instr
= minmax_instr
;
343 return label
& label_minmax
;
346 void set_fcmp(Instruction
*fcmp_instr
)
348 add_label(label_fcmp
);
354 return label
& label_fcmp
;
357 void set_uniform_bool(Temp uniform_bool
)
359 add_label(label_uniform_bool
);
363 bool is_uniform_bool()
365 return label
& label_uniform_bool
;
372 std::vector
<aco_ptr
<Instruction
>> instructions
;
374 std::pair
<uint32_t,Temp
> last_literal
;
375 std::vector
<mad_info
> mad_infos
;
376 std::vector
<uint16_t> uses
;
379 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
381 if (instr
->operands
[0].isConstant() ||
382 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
385 switch (instr
->opcode
) {
386 case aco_opcode::v_add_f32
:
387 case aco_opcode::v_mul_f32
:
388 case aco_opcode::v_or_b32
:
389 case aco_opcode::v_and_b32
:
390 case aco_opcode::v_xor_b32
:
391 case aco_opcode::v_max_f32
:
392 case aco_opcode::v_min_f32
:
393 case aco_opcode::v_cmp_eq_f32
:
394 case aco_opcode::v_cmp_lg_f32
:
396 case aco_opcode::v_sub_f32
:
397 instr
->opcode
= aco_opcode::v_subrev_f32
;
399 case aco_opcode::v_cmp_lt_f32
:
400 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
402 case aco_opcode::v_cmp_ge_f32
:
403 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
405 case aco_opcode::v_cmp_lt_i32
:
406 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
413 bool can_use_VOP3(aco_ptr
<Instruction
>& instr
)
415 if (instr
->operands
.size() && instr
->operands
[0].isLiteral())
418 if (instr
->isDPP() || instr
->isSDWA())
421 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
422 instr
->opcode
!= aco_opcode::v_madak_f32
&&
423 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
424 instr
->opcode
!= aco_opcode::v_madak_f16
&&
425 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
426 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
427 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
430 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
432 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
433 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
434 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
435 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
436 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
439 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
444 assert(!instr
->operands
[0].isLiteral());
445 aco_ptr
<Instruction
> tmp
= std::move(instr
);
446 Format format
= asVOP3(tmp
->format
);
447 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
448 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
449 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
450 instr
->definitions
[i
] = tmp
->definitions
[i
];
451 if (instr
->definitions
[i
].isTemp()) {
452 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
453 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
454 info
.instr
= instr
.get();
459 /* only covers special cases */
460 bool can_accept_constant(aco_ptr
<Instruction
>& instr
, unsigned operand
)
462 switch (instr
->opcode
) {
463 case aco_opcode::v_interp_p2_f32
:
464 case aco_opcode::v_mac_f32
:
465 case aco_opcode::v_writelane_b32
:
466 case aco_opcode::v_writelane_b32_e64
:
467 case aco_opcode::v_cndmask_b32
:
469 case aco_opcode::s_addk_i32
:
470 case aco_opcode::s_mulk_i32
:
471 case aco_opcode::p_wqm
:
472 case aco_opcode::p_extract_vector
:
473 case aco_opcode::p_split_vector
:
474 case aco_opcode::v_readlane_b32
:
475 case aco_opcode::v_readlane_b32_e64
:
476 case aco_opcode::v_readfirstlane_b32
:
479 if ((instr
->format
== Format::MUBUF
||
480 instr
->format
== Format::MIMG
) &&
481 instr
->definitions
.size() == 1 &&
482 instr
->operands
.size() == 4) {
489 bool valu_can_accept_literal(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, unsigned operand
)
491 /* instructions like v_cndmask_b32 can't take a literal because they always
493 if (instr
->operands
.size() >= 3 &&
494 instr
->operands
[2].isTemp() && instr
->operands
[2].regClass().type() == RegType::sgpr
)
497 // TODO: VOP3 can take a literal on GFX10
498 return !instr
->isSDWA() && !instr
->isDPP() && !instr
->isVOP3() &&
499 operand
== 0 && can_accept_constant(instr
, operand
);
502 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
504 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
505 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
510 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
512 Operand op
= instr
->operands
[op_index
];
516 Temp tmp
= op
.getTemp();
517 if (!ctx
.info
[tmp
.id()].is_add_sub())
520 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
522 switch (add_instr
->opcode
) {
523 case aco_opcode::v_add_u32
:
524 case aco_opcode::v_add_co_u32
:
525 case aco_opcode::s_add_i32
:
526 case aco_opcode::s_add_u32
:
532 if (add_instr
->usesModifiers())
535 for (unsigned i
= 0; i
< 2; i
++) {
536 if (add_instr
->operands
[i
].isConstant()) {
537 *offset
= add_instr
->operands
[i
].constantValue();
538 } else if (add_instr
->operands
[i
].isTemp() &&
539 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
540 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
544 if (!add_instr
->operands
[!i
].isTemp())
547 uint32_t offset2
= 0;
548 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
551 *base
= add_instr
->operands
[!i
].getTemp();
559 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
561 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
562 ASSERTED
bool all_const
= false;
563 for (Operand
& op
: instr
->operands
)
564 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
565 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
568 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
570 if (!instr
->operands
[i
].isTemp())
573 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
574 /* propagate undef */
575 if (info
.is_undefined() && is_phi(instr
))
576 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
577 /* propagate reg->reg of same type */
578 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
579 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
580 info
= ctx
.info
[info
.temp
.id()];
583 /* SALU / PSEUDO: propagate inline constants */
584 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
585 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
586 instr
->operands
[i
].setTemp(info
.temp
);
587 info
= ctx
.info
[info
.temp
.id()];
588 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
589 /* propagate vgpr if it can take it */
590 switch (instr
->opcode
) {
591 case aco_opcode::p_create_vector
:
592 case aco_opcode::p_split_vector
:
593 case aco_opcode::p_extract_vector
:
594 case aco_opcode::p_phi
: {
595 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
596 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
598 instr
->operands
[i
] = Operand(info
.temp
);
599 info
= ctx
.info
[info
.temp
.id()];
607 if ((info
.is_constant() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) && !instr
->operands
[i
].isFixed() && can_accept_constant(instr
, i
)) {
608 instr
->operands
[i
] = Operand(info
.val
);
613 /* VALU: propagate neg, abs & inline constants */
614 else if (instr
->isVALU()) {
615 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
616 instr
->operands
[i
].setTemp(info
.temp
);
617 info
= ctx
.info
[info
.temp
.id()];
619 if (info
.is_abs() && (can_use_VOP3(instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
622 instr
->operands
[i
] = Operand(info
.temp
);
624 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
626 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
628 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
629 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
630 instr
->operands
[i
].setTemp(info
.temp
);
632 } else if (info
.is_neg() && (can_use_VOP3(instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
635 instr
->operands
[i
].setTemp(info
.temp
);
637 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
639 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
642 if (info
.is_constant() && can_accept_constant(instr
, i
)) {
643 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
644 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
645 instr
->operands
[i
] = Operand(info
.val
);
647 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
648 instr
->operands
[i
] = instr
->operands
[0];
649 instr
->operands
[0] = Operand(info
.val
);
651 } else if (can_use_VOP3(instr
)) {
653 instr
->operands
[i
] = Operand(info
.val
);
659 /* MUBUF: propagate constants and combine additions */
660 else if (instr
->format
== Format::MUBUF
) {
661 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
664 while (info
.is_temp())
665 info
= ctx
.info
[info
.temp
.id()];
667 if (mubuf
->offen
&& i
== 0 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
668 assert(!mubuf
->idxen
);
669 instr
->operands
[i
] = Operand(v1
);
670 mubuf
->offset
+= info
.val
;
671 mubuf
->offen
= false;
673 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
674 instr
->operands
[2] = Operand((uint32_t) 0);
675 mubuf
->offset
+= info
.val
;
677 } else if (mubuf
->offen
&& i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
678 assert(!mubuf
->idxen
);
679 instr
->operands
[i
].setTemp(base
);
680 mubuf
->offset
+= offset
;
682 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
683 instr
->operands
[i
].setTemp(base
);
684 mubuf
->offset
+= offset
;
689 /* DS: combine additions */
690 else if (instr
->format
== Format::DS
) {
692 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
695 if (i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == instr
->operands
[i
].regClass()) {
696 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
697 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
698 if (offset
% 4 == 0 &&
699 ds
->offset0
+ (offset
>> 2) <= 255 &&
700 ds
->offset1
+ (offset
>> 2) <= 255) {
701 instr
->operands
[i
].setTemp(base
);
702 ds
->offset0
+= offset
>> 2;
703 ds
->offset1
+= offset
>> 2;
706 if (ds
->offset0
+ offset
<= 65535) {
707 instr
->operands
[i
].setTemp(base
);
708 ds
->offset0
+= offset
;
714 /* SMEM: propagate constants and combine additions */
715 else if (instr
->format
== Format::SMEM
) {
717 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
720 if (i
== 1 && info
.is_constant_or_literal() &&
721 (ctx
.program
->chip_class
< GFX8
|| info
.val
<= 0xFFFFF)) {
722 instr
->operands
[i
] = Operand(info
.val
);
724 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
725 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
727 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
728 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
732 smem
->operands
[1] = Operand(offset
);
733 smem
->operands
.back() = Operand(base
);
735 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
736 new_instr
->operands
[0] = smem
->operands
[0];
737 new_instr
->operands
[1] = Operand(offset
);
738 if (smem
->definitions
.empty())
739 new_instr
->operands
[2] = smem
->operands
[2];
740 new_instr
->operands
.back() = Operand(base
);
741 if (!smem
->definitions
.empty())
742 new_instr
->definitions
[0] = smem
->definitions
[0];
743 new_instr
->can_reorder
= smem
->can_reorder
;
744 new_instr
->barrier
= smem
->barrier
;
745 instr
.reset(new_instr
);
746 smem
= static_cast<SMEM_instruction
*>(instr
.get());
753 /* if this instruction doesn't define anything, return */
754 if (instr
->definitions
.empty())
757 switch (instr
->opcode
) {
758 case aco_opcode::p_create_vector
: {
759 unsigned num_ops
= instr
->operands
.size();
760 for (const Operand
& op
: instr
->operands
) {
761 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
762 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
764 if (num_ops
!= instr
->operands
.size()) {
765 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
766 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
767 instr
->definitions
[0] = old_vec
->definitions
[0];
769 for (Operand
& old_op
: old_vec
->operands
) {
770 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
771 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++)
772 instr
->operands
[k
++] = ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
774 instr
->operands
[k
++] = old_op
;
777 assert(k
== num_ops
);
779 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
780 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
781 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
782 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
785 case aco_opcode::p_split_vector
: {
786 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
788 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
789 assert(instr
->definitions
.size() == vec
->operands
.size());
790 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
791 Operand vec_op
= vec
->operands
[i
];
792 if (vec_op
.isConstant()) {
793 if (vec_op
.isLiteral())
794 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
795 else if (vec_op
.size() == 1)
796 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
798 assert(vec_op
.isTemp());
799 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
804 case aco_opcode::p_extract_vector
: { /* mov */
805 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
807 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
808 if (vec
->definitions
[0].getTemp().size() == vec
->operands
.size() && /* TODO: what about 64bit or other combinations? */
809 vec
->operands
[0].size() == instr
->definitions
[0].size()) {
811 /* convert this extract into a mov instruction */
812 Operand vec_op
= vec
->operands
[instr
->operands
[1].constantValue()];
813 bool is_vgpr
= instr
->definitions
[0].getTemp().type() == RegType::vgpr
;
814 aco_opcode opcode
= is_vgpr
? aco_opcode::v_mov_b32
: aco_opcode::s_mov_b32
;
815 Format format
= is_vgpr
? Format::VOP1
: Format::SOP1
;
816 instr
->opcode
= opcode
;
817 instr
->format
= format
;
818 instr
->operands
= {instr
->operands
.begin(), 1 };
819 instr
->operands
[0] = vec_op
;
821 if (vec_op
.isConstant()) {
822 if (vec_op
.isLiteral())
823 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(vec_op
.constantValue());
824 else if (vec_op
.size() == 1)
825 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(vec_op
.constantValue());
827 assert(vec_op
.isTemp());
828 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vec_op
.getTemp());
833 case aco_opcode::s_mov_b32
: /* propagate */
834 case aco_opcode::s_mov_b64
:
835 case aco_opcode::v_mov_b32
:
836 case aco_opcode::p_as_uniform
:
837 if (instr
->definitions
[0].isFixed()) {
838 /* don't copy-propagate copies into fixed registers */
839 } else if (instr
->usesModifiers()) {
841 } else if (instr
->operands
[0].isConstant()) {
842 if (instr
->operands
[0].isLiteral())
843 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
844 else if (instr
->operands
[0].size() == 1)
845 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
846 } else if (instr
->operands
[0].isTemp()) {
847 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
849 assert(instr
->operands
[0].isFixed());
852 case aco_opcode::p_is_helper
:
853 if (!ctx
.program
->needs_wqm
)
854 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
856 case aco_opcode::s_movk_i32
: {
857 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
858 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
859 if (v
<= 64 || v
>= 0xfffffff0)
860 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
862 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
865 case aco_opcode::v_bfrev_b32
:
866 case aco_opcode::s_brev_b32
: {
867 if (instr
->operands
[0].isConstant()) {
868 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
869 if (v
<= 64 || v
>= 0xfffffff0)
870 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
872 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
876 case aco_opcode::s_bfm_b32
: {
877 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
878 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
879 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
880 uint32_t v
= ((1u << size
) - 1u) << start
;
881 if (v
<= 64 || v
>= 0xfffffff0)
882 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
884 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
887 case aco_opcode::v_mul_f32
: { /* omod */
888 /* TODO: try to move the negate/abs modifier to the consumer instead */
889 if (instr
->usesModifiers())
892 for (unsigned i
= 0; i
< 2; i
++) {
893 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
894 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
895 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2();
896 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
897 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4();
898 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
899 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5();
900 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000 &&
901 !block
.fp_mode
.must_flush_denorms32
) { /* 1.0 */
902 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
911 case aco_opcode::v_and_b32
: /* abs */
912 if (instr
->operands
[0].constantEquals(0x7FFFFFFF) && instr
->operands
[1].isTemp())
913 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
915 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
917 case aco_opcode::v_xor_b32
: { /* neg */
918 if (instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
919 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
920 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
922 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
923 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
924 instr
->opcode
= aco_opcode::v_or_b32
;
925 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
927 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
931 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
935 case aco_opcode::v_med3_f32
: { /* clamp */
936 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
937 if (vop3
->abs
[0] || vop3
->neg
[0] || vop3
->opsel
[0] ||
938 vop3
->abs
[1] || vop3
->neg
[1] || vop3
->opsel
[1] ||
939 vop3
->abs
[2] || vop3
->neg
[2] || vop3
->opsel
[2] ||
944 bool found_zero
= false, found_one
= false;
945 for (unsigned i
= 0; i
< 3; i
++)
947 if (instr
->operands
[i
].constantEquals(0))
949 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
954 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
955 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp();
959 case aco_opcode::v_cndmask_b32
:
960 if (instr
->operands
[0].constantEquals(0) &&
961 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
962 instr
->operands
[2].isTemp())
963 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
964 else if (instr
->operands
[0].constantEquals(0) &&
965 instr
->operands
[1].constantEquals(0x3f800000u
) &&
966 instr
->operands
[2].isTemp())
967 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
969 case aco_opcode::v_cmp_lg_u32
:
970 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
971 instr
->operands
[0].constantEquals(0) &&
972 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
973 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
975 case aco_opcode::p_phi
:
976 case aco_opcode::p_linear_phi
: {
977 /* lower_bool_phis() can create phis like this */
978 bool all_same_temp
= instr
->operands
[0].isTemp();
979 /* this check is needed when moving uniform loop counters out of a divergent loop */
981 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
982 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
983 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
984 all_same_temp
= false;
987 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
989 bool all_undef
= instr
->operands
[0].isUndefined();
990 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
991 if (!instr
->operands
[i
].isUndefined())
995 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
999 case aco_opcode::v_add_u32
:
1000 case aco_opcode::v_add_co_u32
:
1001 case aco_opcode::s_add_i32
:
1002 case aco_opcode::s_add_u32
:
1003 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1005 case aco_opcode::s_and_b32
:
1006 case aco_opcode::s_and_b64
:
1007 if (instr
->operands
[1].isFixed() && instr
->operands
[1].physReg() == exec
&&
1008 instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1009 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1012 case aco_opcode::s_not_b32
:
1013 case aco_opcode::s_not_b64
:
1014 case aco_opcode::s_or_b32
:
1015 case aco_opcode::s_or_b64
:
1016 case aco_opcode::s_xor_b32
:
1017 case aco_opcode::s_xor_b64
:
1018 case aco_opcode::s_lshl_b32
:
1019 case aco_opcode::v_or_b32
:
1020 case aco_opcode::v_lshlrev_b32
:
1021 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1023 case aco_opcode::v_min_f32
:
1024 case aco_opcode::v_min_f16
:
1025 case aco_opcode::v_min_u32
:
1026 case aco_opcode::v_min_i32
:
1027 case aco_opcode::v_min_u16
:
1028 case aco_opcode::v_min_i16
:
1029 case aco_opcode::v_max_f32
:
1030 case aco_opcode::v_max_f16
:
1031 case aco_opcode::v_max_u32
:
1032 case aco_opcode::v_max_i32
:
1033 case aco_opcode::v_max_u16
:
1034 case aco_opcode::v_max_i16
:
1035 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1037 case aco_opcode::v_cmp_lt_f32
:
1038 case aco_opcode::v_cmp_eq_f32
:
1039 case aco_opcode::v_cmp_le_f32
:
1040 case aco_opcode::v_cmp_gt_f32
:
1041 case aco_opcode::v_cmp_lg_f32
:
1042 case aco_opcode::v_cmp_ge_f32
:
1043 case aco_opcode::v_cmp_o_f32
:
1044 case aco_opcode::v_cmp_u_f32
:
1045 case aco_opcode::v_cmp_nge_f32
:
1046 case aco_opcode::v_cmp_nlg_f32
:
1047 case aco_opcode::v_cmp_ngt_f32
:
1048 case aco_opcode::v_cmp_nle_f32
:
1049 case aco_opcode::v_cmp_neq_f32
:
1050 case aco_opcode::v_cmp_nlt_f32
:
1051 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1053 case aco_opcode::s_cselect_b64
:
1054 case aco_opcode::s_cselect_b32
:
1055 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1056 instr
->operands
[1].constantEquals(0)) {
1057 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1058 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1066 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1068 *ordered
= *unordered
= op
;
1070 #define CMP(ord, unord) \
1071 case aco_opcode::v_cmp_##ord##_f32:\
1072 case aco_opcode::v_cmp_n##unord##_f32:\
1073 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1074 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1075 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1089 aco_opcode
get_ordered(aco_opcode op
)
1091 aco_opcode ordered
, unordered
, inverse
;
1092 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1095 aco_opcode
get_unordered(aco_opcode op
)
1097 aco_opcode ordered
, unordered
, inverse
;
1098 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1101 aco_opcode
get_inverse(aco_opcode op
)
1103 aco_opcode ordered
, unordered
, inverse
;
1104 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1107 bool is_cmp(aco_opcode op
)
1109 aco_opcode ordered
, unordered
, inverse
;
1110 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1113 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1115 if (ctx
.info
[tmp
.id()].is_temp())
1116 return ctx
.info
[tmp
.id()].temp
.id();
1121 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1123 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1124 for (const Operand
& op
: instr
->operands
) {
1126 ctx
.uses
[op
.tempId()]--;
1131 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1133 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1135 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1138 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1140 if (instr
->definitions
.size() == 2) {
1141 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1142 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1149 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1150 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1151 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1153 if (instr
->opcode
!= aco_opcode::s_or_b64
&& instr
->opcode
!= aco_opcode::s_and_b64
)
1155 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1158 bool neg
[2] = {false, false};
1159 bool abs
[2] = {false, false};
1160 bool opsel
[2] = {false, false};
1161 Instruction
*op_instr
[2];
1164 for (unsigned i
= 0; i
< 2; i
++) {
1165 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1169 aco_opcode expected_cmp
= instr
->opcode
== aco_opcode::s_or_b64
?
1170 aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1172 if (op_instr
[i
]->opcode
!= expected_cmp
)
1174 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1177 if (op_instr
[i
]->isVOP3()) {
1178 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1179 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
[0] != vop3
->opsel
[1])
1181 neg
[i
] = vop3
->neg
[0];
1182 abs
[i
] = vop3
->abs
[0];
1183 opsel
[i
] = vop3
->opsel
[0];
1186 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1187 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1188 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1190 /* shouldn't happen yet, but best to be safe */
1191 if (op1
.type() != RegType::vgpr
)
1197 ctx
.uses
[op
[0].id()]++;
1198 ctx
.uses
[op
[1].id()]++;
1199 decrease_uses(ctx
, op_instr
[0]);
1200 decrease_uses(ctx
, op_instr
[1]);
1202 aco_opcode new_op
= instr
->opcode
== aco_opcode::s_or_b64
?
1203 aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1204 Instruction
*new_instr
;
1205 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
[0] || opsel
[1]) {
1206 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1207 for (unsigned i
= 0; i
< 2; i
++) {
1208 vop3
->neg
[i
] = neg
[i
];
1209 vop3
->abs
[i
] = abs
[i
];
1210 vop3
->opsel
[i
] = opsel
[i
];
1212 new_instr
= static_cast<Instruction
*>(vop3
);
1214 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1216 new_instr
->operands
[0] = Operand(op
[0]);
1217 new_instr
->operands
[1] = Operand(op
[1]);
1218 new_instr
->definitions
[0] = instr
->definitions
[0];
1220 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1221 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1223 instr
.reset(new_instr
);
1228 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1229 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1230 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1232 if (instr
->opcode
!= aco_opcode::s_or_b64
&& instr
->opcode
!= aco_opcode::s_and_b64
)
1234 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1237 aco_opcode expected_nan_test
= instr
->opcode
== aco_opcode::s_or_b64
?
1238 aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1240 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1241 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1242 if (!nan_test
|| !cmp
)
1245 if (cmp
->opcode
== expected_nan_test
)
1246 std::swap(nan_test
, cmp
);
1247 else if (nan_test
->opcode
!= expected_nan_test
)
1250 if (!is_cmp(cmp
->opcode
))
1253 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1255 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1258 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1259 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1260 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1261 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1262 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1264 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1267 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1268 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1269 decrease_uses(ctx
, nan_test
);
1270 decrease_uses(ctx
, cmp
);
1272 aco_opcode new_op
= instr
->opcode
== aco_opcode::s_or_b64
?
1273 get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1274 Instruction
*new_instr
;
1275 if (cmp
->isVOP3()) {
1276 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1277 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1278 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1279 memcpy(new_vop3
->opsel
, cmp_vop3
->opsel
, sizeof(new_vop3
->opsel
));
1280 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1281 new_vop3
->clamp
= cmp_vop3
->clamp
;
1282 new_vop3
->omod
= cmp_vop3
->omod
;
1283 new_instr
= new_vop3
;
1285 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1287 new_instr
->operands
[0] = cmp
->operands
[0];
1288 new_instr
->operands
[1] = cmp
->operands
[1];
1289 new_instr
->definitions
[0] = instr
->definitions
[0];
1291 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1292 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1294 instr
.reset(new_instr
);
1299 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1300 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1301 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1303 if (instr
->opcode
!= aco_opcode::s_or_b64
&& instr
->opcode
!= aco_opcode::s_and_b64
)
1305 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1308 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1309 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1311 if (!nan_test
|| !cmp
)
1314 aco_opcode expected_nan_test
= instr
->opcode
== aco_opcode::s_or_b64
?
1315 aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1316 if (cmp
->opcode
== expected_nan_test
)
1317 std::swap(nan_test
, cmp
);
1318 else if (nan_test
->opcode
!= expected_nan_test
)
1321 if (!is_cmp(cmp
->opcode
))
1324 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1326 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1329 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1330 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1331 if (prop_nan0
!= prop_nan1
)
1334 int constant_operand
= -1;
1335 for (unsigned i
= 0; i
< 2; i
++) {
1336 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1337 constant_operand
= !i
;
1341 if (constant_operand
== -1)
1345 if (cmp
->operands
[constant_operand
].isConstant()) {
1346 constant
= cmp
->operands
[constant_operand
].constantValue();
1347 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1348 unsigned id
= cmp
->operands
[constant_operand
].tempId();
1349 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1351 constant
= ctx
.info
[id
].val
;
1357 memcpy(&constantf
, &constant
, 4);
1358 if (isnan(constantf
))
1361 if (cmp
->operands
[0].isTemp())
1362 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1363 if (cmp
->operands
[1].isTemp())
1364 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1365 decrease_uses(ctx
, nan_test
);
1366 decrease_uses(ctx
, cmp
);
1368 aco_opcode new_op
= instr
->opcode
== aco_opcode::s_or_b64
?
1369 get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1370 Instruction
*new_instr
;
1371 if (cmp
->isVOP3()) {
1372 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1373 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1374 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1375 memcpy(new_vop3
->opsel
, cmp_vop3
->opsel
, sizeof(new_vop3
->opsel
));
1376 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1377 new_vop3
->clamp
= cmp_vop3
->clamp
;
1378 new_vop3
->omod
= cmp_vop3
->omod
;
1379 new_instr
= new_vop3
;
1381 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1383 new_instr
->operands
[0] = cmp
->operands
[0];
1384 new_instr
->operands
[1] = cmp
->operands
[1];
1385 new_instr
->definitions
[0] = instr
->definitions
[0];
1387 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1388 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1390 instr
.reset(new_instr
);
1395 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1396 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1398 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1400 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1402 if (!instr
->operands
[0].isTemp())
1405 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1409 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1410 if (new_opcode
== aco_opcode::last_opcode
)
1413 if (cmp
->operands
[0].isTemp())
1414 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1415 if (cmp
->operands
[1].isTemp())
1416 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1417 decrease_uses(ctx
, cmp
);
1419 Instruction
*new_instr
;
1420 if (cmp
->isVOP3()) {
1421 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1422 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1423 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1424 memcpy(new_vop3
->opsel
, cmp_vop3
->opsel
, sizeof(new_vop3
->opsel
));
1425 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1426 new_vop3
->clamp
= cmp_vop3
->clamp
;
1427 new_vop3
->omod
= cmp_vop3
->omod
;
1428 new_instr
= new_vop3
;
1430 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1432 new_instr
->operands
[0] = cmp
->operands
[0];
1433 new_instr
->operands
[1] = cmp
->operands
[1];
1434 new_instr
->definitions
[0] = instr
->definitions
[0];
1436 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1437 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1439 instr
.reset(new_instr
);
1444 /* op1(op2(1, 2), 0) if swap = false
1445 * op1(0, op2(1, 2)) if swap = true */
1446 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1447 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1448 Operand operands
[3], bool neg
[3], bool abs
[3], bool opsel
[3],
1449 bool *op1_clamp
, unsigned *op1_omod
,
1450 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1453 if (op1_instr
->opcode
!= op1
)
1456 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1457 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1460 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1461 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1463 /* don't support inbetween clamp/omod */
1464 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1467 /* get operands and modifiers and check inbetween modifiers */
1468 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1469 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1472 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1473 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1477 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1478 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1481 if (inbetween_opsel
)
1482 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
[swap
] : false;
1483 else if (op1_vop3
&& op1_vop3
->opsel
[swap
])
1487 shuffle
[shuffle_str
[0] - '0'] = 0;
1488 shuffle
[shuffle_str
[1] - '0'] = 1;
1489 shuffle
[shuffle_str
[2] - '0'] = 2;
1491 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1492 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1493 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1494 opsel
[shuffle
[0]] = op1_vop3
? op1_vop3
->opsel
[!swap
] : false;
1496 for (unsigned i
= 0; i
< 2; i
++) {
1497 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1498 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1499 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1500 opsel
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->opsel
[i
] : false;
1503 /* check operands */
1504 unsigned sgpr_id
= 0;
1505 for (unsigned i
= 0; i
< 3; i
++) {
1506 Operand op
= operands
[i
];
1507 if (op
.isLiteral()) {
1509 } else if (op
.isTemp() && op
.getTemp().type() == RegType::sgpr
) {
1510 if (sgpr_id
&& sgpr_id
!= op
.tempId())
1512 sgpr_id
= op
.tempId();
1519 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1520 Operand operands
[3], bool neg
[3], bool abs
[3], bool opsel
[3],
1521 bool clamp
, unsigned omod
)
1523 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1524 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1525 memcpy(new_instr
->opsel
, opsel
, sizeof(bool[3]));
1526 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1527 new_instr
->clamp
= clamp
;
1528 new_instr
->omod
= omod
;
1529 new_instr
->operands
[0] = operands
[0];
1530 new_instr
->operands
[1] = operands
[1];
1531 new_instr
->operands
[2] = operands
[2];
1532 new_instr
->definitions
[0] = instr
->definitions
[0];
1533 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1535 instr
.reset(new_instr
);
1538 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1540 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1541 (label_omod_success
| label_clamp_success
);
1543 for (unsigned swap
= 0; swap
< 2; swap
++) {
1544 if (!((1 << swap
) & ops
))
1547 Operand operands
[3];
1548 bool neg
[3], abs
[3], opsel
[3], clamp
;
1550 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1551 instr
.get(), swap
, shuffle
,
1552 operands
, neg
, abs
, opsel
,
1553 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1554 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1555 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1556 if (omod_clamp
& label_omod_success
)
1557 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1558 if (omod_clamp
& label_clamp_success
)
1559 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1566 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1567 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1568 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1569 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1570 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1571 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1572 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1575 if (!instr
->operands
[0].isTemp())
1577 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1580 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1583 switch (op2_instr
->opcode
) {
1584 case aco_opcode::s_and_b32
:
1585 case aco_opcode::s_or_b32
:
1586 case aco_opcode::s_xor_b32
:
1587 case aco_opcode::s_and_b64
:
1588 case aco_opcode::s_or_b64
:
1589 case aco_opcode::s_xor_b64
:
1595 /* create instruction */
1596 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1597 ctx
.uses
[instr
->operands
[0].tempId()]--;
1598 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1600 switch (op2_instr
->opcode
) {
1601 case aco_opcode::s_and_b32
:
1602 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1604 case aco_opcode::s_or_b32
:
1605 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1607 case aco_opcode::s_xor_b32
:
1608 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1610 case aco_opcode::s_and_b64
:
1611 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1613 case aco_opcode::s_or_b64
:
1614 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1616 case aco_opcode::s_xor_b64
:
1617 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1626 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1627 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1628 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1629 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1630 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1632 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1635 for (unsigned i
= 0; i
< 2; i
++) {
1636 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1637 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1640 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1641 instr
->operands
[0] = instr
->operands
[!i
];
1642 instr
->operands
[1] = op2_instr
->operands
[0];
1643 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1645 switch (instr
->opcode
) {
1646 case aco_opcode::s_and_b32
:
1647 instr
->opcode
= aco_opcode::s_andn2_b32
;
1649 case aco_opcode::s_or_b32
:
1650 instr
->opcode
= aco_opcode::s_orn2_b32
;
1652 case aco_opcode::s_and_b64
:
1653 instr
->opcode
= aco_opcode::s_andn2_b64
;
1655 case aco_opcode::s_or_b64
:
1656 instr
->opcode
= aco_opcode::s_orn2_b64
;
1667 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1668 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1670 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1673 for (unsigned i
= 0; i
< 2; i
++) {
1674 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1675 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
|| !op2_instr
->operands
[1].isConstant())
1678 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1679 if (shift
< 1 || shift
> 4)
1682 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1683 instr
->operands
[1] = instr
->operands
[!i
];
1684 instr
->operands
[0] = op2_instr
->operands
[0];
1685 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1687 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1688 aco_opcode::s_lshl2_add_u32
,
1689 aco_opcode::s_lshl3_add_u32
,
1690 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1697 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1700 #define MINMAX(type, gfx9) \
1701 case aco_opcode::v_min_##type:\
1702 case aco_opcode::v_max_##type:\
1703 case aco_opcode::v_med3_##type:\
1704 *min = aco_opcode::v_min_##type;\
1705 *max = aco_opcode::v_max_##type;\
1706 *med3 = aco_opcode::v_med3_##type;\
1707 *min3 = aco_opcode::v_min3_##type;\
1708 *max3 = aco_opcode::v_max3_##type;\
1709 *some_gfx9_only = gfx9;\
1723 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1724 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1725 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1726 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1728 aco_opcode other_op
;
1729 if (instr
->opcode
== min
)
1731 else if (instr
->opcode
== max
)
1736 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1737 (label_omod_success
| label_clamp_success
);
1739 for (unsigned swap
= 0; swap
< 2; swap
++) {
1740 Operand operands
[3];
1741 bool neg
[3], abs
[3], opsel
[3], clamp
, inbetween_neg
, inbetween_abs
;
1743 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1744 "012", operands
, neg
, abs
, opsel
,
1745 &clamp
, &omod
, &inbetween_neg
, &inbetween_abs
, NULL
)) {
1746 int const0_idx
= -1, const1_idx
= -1;
1747 uint32_t const0
= 0, const1
= 0;
1748 for (int i
= 0; i
< 3; i
++) {
1750 if (operands
[i
].isConstant()) {
1751 val
= operands
[i
].constantValue();
1752 } else if (operands
[i
].isTemp() && ctx
.uses
[operands
[i
].tempId()] == 1 &&
1753 ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
1754 val
= ctx
.info
[operands
[i
].tempId()].val
;
1758 if (const0_idx
>= 0) {
1766 if (const0_idx
< 0 || const1_idx
< 0)
1769 if (opsel
[const0_idx
])
1771 if (opsel
[const1_idx
])
1774 int lower_idx
= const0_idx
;
1776 case aco_opcode::v_min_f32
:
1777 case aco_opcode::v_min_f16
: {
1778 float const0_f
, const1_f
;
1779 if (min
== aco_opcode::v_min_f32
) {
1780 memcpy(&const0_f
, &const0
, 4);
1781 memcpy(&const1_f
, &const1
, 4);
1783 const0_f
= _mesa_half_to_float(const0
);
1784 const1_f
= _mesa_half_to_float(const1
);
1786 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
1787 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
1788 if (neg
[const0_idx
]) const0_f
= -const0_f
;
1789 if (neg
[const1_idx
]) const1_f
= -const1_f
;
1790 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
1793 case aco_opcode::v_min_u32
: {
1794 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
1797 case aco_opcode::v_min_u16
: {
1798 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
1801 case aco_opcode::v_min_i32
: {
1802 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
1803 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
1804 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1807 case aco_opcode::v_min_i16
: {
1808 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
1809 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
1810 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1816 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
1818 if (instr
->opcode
== min
) {
1819 if (upper_idx
!= 0 || lower_idx
== 0)
1822 if (upper_idx
== 0 || lower_idx
!= 0)
1826 neg
[1] ^= inbetween_neg
;
1827 neg
[2] ^= inbetween_neg
;
1828 abs
[1] |= inbetween_abs
;
1829 abs
[2] |= inbetween_abs
;
1831 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1832 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1833 if (omod_clamp
& label_omod_success
)
1834 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1835 if (omod_clamp
& label_clamp_success
)
1836 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1846 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1849 uint32_t sgpr_idx
= 0;
1850 uint32_t sgpr_info_id
= 0;
1851 bool has_sgpr
= false;
1852 uint32_t sgpr_ssa_id
= 0;
1853 /* find 'best' possible sgpr */
1854 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
1856 if (instr
->operands
[i
].isLiteral()) {
1860 if (!instr
->operands
[i
].isTemp())
1862 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
1864 sgpr_ssa_id
= instr
->operands
[i
].tempId();
1867 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
1868 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
1869 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
1870 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
1872 sgpr_info_id
= instr
->operands
[i
].tempId();
1876 if (!has_sgpr
&& sgpr_info_id
!= 0) {
1877 ssa_info
& info
= ctx
.info
[sgpr_info_id
];
1878 if (sgpr_idx
== 0 || instr
->isVOP3()) {
1879 instr
->operands
[sgpr_idx
] = Operand(info
.temp
);
1880 ctx
.uses
[sgpr_info_id
]--;
1881 ctx
.uses
[info
.temp
.id()]++;
1882 } else if (can_swap_operands(instr
)) {
1883 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
1884 instr
->operands
[0] = Operand(info
.temp
);
1885 ctx
.uses
[sgpr_info_id
]--;
1886 ctx
.uses
[info
.temp
.id()]++;
1887 } else if (can_use_VOP3(instr
)) {
1888 to_VOP3(ctx
, instr
);
1889 instr
->operands
[sgpr_idx
] = Operand(info
.temp
);
1890 ctx
.uses
[sgpr_info_id
]--;
1891 ctx
.uses
[info
.temp
.id()]++;
1894 /* we can have two sgprs on one instruction if it is the same sgpr! */
1895 } else if (sgpr_info_id
!= 0 &&
1896 sgpr_ssa_id
== sgpr_info_id
&&
1897 ctx
.uses
[sgpr_info_id
] == 1 &&
1898 can_use_VOP3(instr
)) {
1899 to_VOP3(ctx
, instr
);
1900 instr
->operands
[sgpr_idx
] = Operand(ctx
.info
[sgpr_info_id
].temp
);
1901 ctx
.uses
[sgpr_info_id
]--;
1902 ctx
.uses
[ctx
.info
[sgpr_info_id
].temp
.id()]++;
1906 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
1908 /* check if we could apply omod on predecessor */
1909 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
1910 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success()) {
1912 /* omod was successfully applied */
1913 /* if the omod instruction is v_mad, we also have to change the original add */
1914 if (ctx
.info
[instr
->operands
[1].tempId()].is_mad()) {
1915 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[1].tempId()].val
].add_instr
.get();
1916 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
1917 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
1918 add_instr
->definitions
[0] = instr
->definitions
[0];
1921 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
1922 /* check if we have an additional clamp modifier */
1923 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1) {
1924 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
1925 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
1927 /* change definition ssa-id of modified instruction */
1928 omod_instr
->definitions
[0] = instr
->definitions
[0];
1930 /* change the definition of instr to something unused, e.g. the original omod def */
1931 instr
->definitions
[0] = Definition(instr
->operands
[1].getTemp());
1932 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
1935 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
1936 /* in all other cases, label this instruction as option for multiply-add */
1937 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
1941 /* check if we could apply clamp on predecessor */
1942 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
1944 bool found_zero
= false, found_one
= false;
1945 for (unsigned i
= 0; i
< 3; i
++)
1947 if (instr
->operands
[i
].constantEquals(0))
1949 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1954 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
1955 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
1956 /* clamp was successfully applied */
1957 /* if the clamp instruction is v_mad, we also have to change the original add */
1958 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
1959 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
1960 add_instr
->definitions
[0] = instr
->definitions
[0];
1962 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
1963 /* change definition ssa-id of modified instruction */
1964 clamp_instr
->definitions
[0] = instr
->definitions
[0];
1966 /* change the definition of instr to something unused, e.g. the original omod def */
1967 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
1968 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
1973 /* omod has no effect if denormals are enabled */
1974 bool can_use_omod
= block
.fp_mode
.denorm32
== 0;
1976 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
1977 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
1978 can_use_VOP3(instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
1979 if (can_use_omod
&& ctx
.info
[instr
->definitions
[0].tempId()].is_omod2()) {
1980 to_VOP3(ctx
, instr
);
1981 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
1982 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1983 } else if (can_use_omod
&& ctx
.info
[instr
->definitions
[0].tempId()].is_omod4()) {
1984 to_VOP3(ctx
, instr
);
1985 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
1986 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1987 } else if (can_use_omod
&& ctx
.info
[instr
->definitions
[0].tempId()].is_omod5()) {
1988 to_VOP3(ctx
, instr
);
1989 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
1990 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1991 } else if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp()) {
1992 to_VOP3(ctx
, instr
);
1993 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
1994 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2001 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2002 // this would mean that we'd have to fix the instruction uses while value propagation
2004 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2006 if (instr
->definitions
.empty() || !ctx
.uses
[instr
->definitions
[0].tempId()])
2009 if (instr
->isVALU()) {
2010 if (can_apply_sgprs(instr
))
2011 apply_sgprs(ctx
, instr
);
2012 if (apply_omod_clamp(ctx
, block
, instr
))
2016 /* TODO: There are still some peephole optimizations that could be done:
2017 * - abs(a - b) -> s_absdiff_i32
2018 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2019 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2020 * These aren't probably too interesting though.
2021 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2022 * probably more useful than the previously mentioned optimizations.
2023 * The various comparison optimizations also currently only work with 32-bit
2026 /* neg(mul(a, b)) -> mul(neg(a), b) */
2027 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2028 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2030 if (!ctx
.info
[val
.id()].is_mul())
2033 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2035 if (mul_instr
->operands
[0].isLiteral())
2037 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2040 /* convert to mul(neg(a), b) */
2041 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2042 Definition def
= instr
->definitions
[0];
2043 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2044 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2045 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2046 instr
->operands
[0] = mul_instr
->operands
[0];
2047 instr
->operands
[1] = mul_instr
->operands
[1];
2048 instr
->definitions
[0] = def
;
2049 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2050 if (mul_instr
->isVOP3()) {
2051 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2052 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2053 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2054 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2055 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2056 new_mul
->omod
= mul
->omod
;
2058 new_mul
->neg
[0] ^= true;
2059 new_mul
->clamp
= false;
2061 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2064 /* combine mul+add -> mad */
2065 else if ((instr
->opcode
== aco_opcode::v_add_f32
||
2066 instr
->opcode
== aco_opcode::v_sub_f32
||
2067 instr
->opcode
== aco_opcode::v_subrev_f32
) &&
2068 block
.fp_mode
.denorm32
== 0 && !block
.fp_mode
.preserve_signed_zero_inf_nan32
) {
2069 //TODO: we could use fma instead when denormals are enabled if the NIR isn't marked as precise
2071 uint32_t uses_src0
= UINT32_MAX
;
2072 uint32_t uses_src1
= UINT32_MAX
;
2073 Instruction
* mul_instr
= nullptr;
2074 unsigned add_op_idx
;
2075 /* check if any of the operands is a multiplication */
2076 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2077 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2078 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2079 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2081 /* find the 'best' mul instruction to combine with the add */
2082 if (uses_src0
< uses_src1
) {
2083 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2085 } else if (uses_src1
< uses_src0
) {
2086 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2088 } else if (uses_src0
!= UINT32_MAX
) {
2089 /* tiebreaker: quite random what to pick */
2090 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2091 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2094 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2099 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2100 bool neg
[3] = {false, false, false};
2101 bool abs
[3] = {false, false, false};
2104 bool need_vop3
= false;
2106 op
[0] = mul_instr
->operands
[0];
2107 op
[1] = mul_instr
->operands
[1];
2108 op
[2] = instr
->operands
[add_op_idx
];
2109 for (unsigned i
= 0; i
< 3; i
++)
2111 if (op
[i
].isLiteral())
2113 if (op
[i
].isTemp() && op
[i
].getTemp().type() == RegType::sgpr
)
2115 if (!(i
== 0 || (op
[i
].isTemp() && op
[i
].getTemp().type() == RegType::vgpr
)))
2118 // TODO: would be better to check this before selecting a mul instr?
2122 if (mul_instr
->isVOP3()) {
2123 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2124 neg
[0] = vop3
->neg
[0];
2125 neg
[1] = vop3
->neg
[1];
2126 abs
[0] = vop3
->abs
[0];
2127 abs
[1] = vop3
->abs
[1];
2129 /* we cannot use these modifiers between mul and add */
2130 if (vop3
->clamp
|| vop3
->omod
)
2134 /* convert to mad */
2135 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2136 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2138 ctx
.uses
[op
[0].tempId()]++;
2140 ctx
.uses
[op
[1].tempId()]++;
2143 if (instr
->isVOP3()) {
2144 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2145 neg
[2] = vop3
->neg
[add_op_idx
];
2146 abs
[2] = vop3
->abs
[add_op_idx
];
2148 clamp
= vop3
->clamp
;
2149 /* abs of the multiplication result */
2150 if (vop3
->abs
[1 - add_op_idx
]) {
2156 /* neg of the multiplication result */
2157 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2160 if (instr
->opcode
== aco_opcode::v_sub_f32
) {
2161 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2163 } else if (instr
->opcode
== aco_opcode::v_subrev_f32
) {
2164 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2168 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2169 for (unsigned i
= 0; i
< 3; i
++)
2171 mad
->operands
[i
] = op
[i
];
2172 mad
->neg
[i
] = neg
[i
];
2173 mad
->abs
[i
] = abs
[i
];
2177 mad
->definitions
[0] = instr
->definitions
[0];
2179 /* mark this ssa_def to be re-checked for profitability and literals */
2180 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId(), need_vop3
);
2181 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2182 instr
.reset(mad
.release());
2186 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2187 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2188 for (unsigned i
= 0; i
< 2; i
++) {
2189 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2190 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2191 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2192 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2193 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2195 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2196 new_instr
->operands
[0] = Operand(0u);
2197 new_instr
->operands
[1] = instr
->operands
[!i
];
2198 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2199 new_instr
->definitions
[0] = instr
->definitions
[0];
2200 instr
.reset(new_instr
.release());
2201 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2205 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2206 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2207 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2208 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2209 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2210 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2211 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2212 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2213 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2214 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2215 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2216 combine_salu_lshl_add(ctx
, instr
);
2217 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2218 combine_salu_not_bitwise(ctx
, instr
);
2219 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2220 if (combine_inverse_comparison(ctx
, instr
)) ;
2221 else combine_salu_not_bitwise(ctx
, instr
);
2222 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
) {
2223 combine_salu_n2(ctx
, instr
);
2224 } else if (instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2225 if (combine_ordering_test(ctx
, instr
)) ;
2226 else if (combine_comparison_ordering(ctx
, instr
)) ;
2227 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2228 else combine_salu_n2(ctx
, instr
);
2230 aco_opcode min
, max
, min3
, max3
, med3
;
2231 bool some_gfx9_only
;
2232 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2233 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2234 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, instr
->opcode
== min
? min3
: max3
, "012", 1 | 2));
2235 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2241 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2243 const uint32_t threshold
= 4;
2245 /* Dead Code Elimination:
2246 * We remove instructions if they define temporaries which all are unused */
2247 const bool is_used
= instr
->definitions
.empty() ||
2248 std::any_of(instr
->definitions
.begin(), instr
->definitions
.end(),
2249 [&ctx
](const Definition
& def
) { return ctx
.uses
[def
.tempId()]; });
2255 /* convert split_vector into extract_vector if only one definition is ever used */
2256 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2257 unsigned num_used
= 0;
2259 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2260 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2265 if (num_used
== 1) {
2266 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2267 extract
->operands
[0] = instr
->operands
[0];
2268 extract
->operands
[1] = Operand((uint32_t) idx
);
2269 extract
->definitions
[0] = instr
->definitions
[idx
];
2270 instr
.reset(extract
.release());
2274 /* re-check mad instructions */
2275 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2276 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2277 /* first, check profitability */
2278 if (ctx
.uses
[info
->mul_temp_id
]) {
2279 ctx
.uses
[info
->mul_temp_id
]++;
2280 instr
.swap(info
->add_instr
);
2282 /* second, check possible literals */
2283 } else if (!info
->needs_vop3
) {
2284 uint32_t literal_idx
= 0;
2285 uint32_t literal_uses
= UINT32_MAX
;
2286 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2288 if (!instr
->operands
[i
].isTemp())
2290 /* if one of the operands is sgpr, we cannot add a literal somewhere else */
2291 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2292 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2293 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2296 literal_uses
= UINT32_MAX
;
2300 else if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2301 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2302 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2306 if (literal_uses
< threshold
) {
2307 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2308 info
->check_literal
= true;
2309 info
->literal_idx
= literal_idx
;
2315 /* check for literals */
2316 /* we do not apply the literals yet as we don't know if it is profitable */
2317 if (instr
->isSALU()) {
2318 uint32_t literal_idx
= 0;
2319 uint32_t literal_uses
= UINT32_MAX
;
2320 bool has_literal
= false;
2321 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2323 if (instr
->operands
[i
].isLiteral()) {
2327 if (!instr
->operands
[i
].isTemp())
2329 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2330 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2331 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2335 if (!has_literal
&& literal_uses
< threshold
) {
2336 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2337 if (ctx
.uses
[instr
->operands
[literal_idx
].tempId()] == 0)
2338 instr
->operands
[literal_idx
] = Operand(ctx
.info
[instr
->operands
[literal_idx
].tempId()].val
);
2340 } else if (instr
->isVALU() && valu_can_accept_literal(ctx
, instr
, 0) &&
2341 instr
->operands
[0].isTemp() &&
2342 ctx
.info
[instr
->operands
[0].tempId()].is_literal() &&
2343 ctx
.uses
[instr
->operands
[0].tempId()] < threshold
) {
2344 ctx
.uses
[instr
->operands
[0].tempId()]--;
2345 if (ctx
.uses
[instr
->operands
[0].tempId()] == 0)
2346 instr
->operands
[0] = Operand(ctx
.info
[instr
->operands
[0].tempId()].val
);
2352 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2354 /* Cleanup Dead Instructions */
2358 /* apply literals on SALU */
2359 if (instr
->isSALU()) {
2360 for (Operand
& op
: instr
->operands
) {
2365 if (ctx
.info
[op
.tempId()].is_literal() &&
2366 ctx
.uses
[op
.tempId()] == 0)
2367 op
= Operand(ctx
.info
[op
.tempId()].val
);
2371 /* apply literals on VALU */
2372 else if (instr
->isVALU() && !instr
->isVOP3() &&
2373 instr
->operands
[0].isTemp() &&
2374 ctx
.info
[instr
->operands
[0].tempId()].is_literal() &&
2375 ctx
.uses
[instr
->operands
[0].tempId()] == 0) {
2376 instr
->operands
[0] = Operand(ctx
.info
[instr
->operands
[0].tempId()].val
);
2379 /* apply literals on MAD */
2380 else if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2381 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2382 aco_ptr
<Instruction
> new_mad
;
2383 if (info
->check_literal
&& ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0) {
2384 if (info
->literal_idx
== 2) { /* add literal -> madak */
2385 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2386 new_mad
->operands
[0] = instr
->operands
[0];
2387 new_mad
->operands
[1] = instr
->operands
[1];
2388 } else { /* mul literal -> madmk */
2389 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2390 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2391 new_mad
->operands
[1] = instr
->operands
[2];
2393 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2394 new_mad
->definitions
[0] = instr
->definitions
[0];
2395 instr
.swap(new_mad
);
2399 ctx
.instructions
.emplace_back(std::move(instr
));
2403 void optimize(Program
* program
)
2406 ctx
.program
= program
;
2407 std::vector
<ssa_info
> info(program
->peekAllocationId());
2408 ctx
.info
= info
.data();
2410 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2411 for (Block
& block
: program
->blocks
) {
2412 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2413 label_instruction(ctx
, block
, instr
);
2416 ctx
.uses
= std::move(dead_code_analysis(program
));
2418 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2419 for (Block
& block
: program
->blocks
) {
2420 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2421 combine_instruction(ctx
, block
, instr
);
2424 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2425 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2426 Block
* block
= &(*it
);
2427 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2428 select_instruction(ctx
, *it
);
2431 /* 4. Add literals to instructions */
2432 for (Block
& block
: program
->blocks
) {
2433 ctx
.instructions
.clear();
2434 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2435 apply_literals(ctx
, instr
);
2436 block
.instructions
.swap(ctx
.instructions
);