2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
59 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
, bool vop3
)
60 : add_instr(std::move(instr
)), mul_temp_id(id
), needs_vop3(vop3
), check_literal(false) {}
65 label_constant
= 1 << 1,
70 label_literal
= 1 << 6,
74 label_omod5
= 1 << 10,
75 label_omod_success
= 1 << 11,
76 label_clamp
= 1 << 12,
77 label_clamp_success
= 1 << 13,
78 label_undefined
= 1 << 14,
81 label_add_sub
= 1 << 17,
82 label_bitwise
= 1 << 18,
83 label_minmax
= 1 << 19,
85 label_uniform_bool
= 1 << 21,
88 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
| label_add_sub
| label_bitwise
| label_minmax
| label_fcmp
;
89 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
| label_omod2
| label_omod4
| label_omod5
| label_clamp
;
90 static constexpr uint32_t val_labels
= label_constant
| label_literal
| label_mad
;
100 void add_label(Label new_label
)
102 /* Since all labels which use "instr" use it for the same thing
103 * (indicating the defining instruction), there is no need to clear
104 * any other instr labels. */
105 if (new_label
& instr_labels
)
106 label
&= ~temp_labels
; /* instr and temp alias */
108 if (new_label
& temp_labels
) {
109 label
&= ~temp_labels
;
110 label
&= ~instr_labels
; /* instr and temp alias */
113 if (new_label
& val_labels
)
114 label
&= ~val_labels
;
119 void set_vec(Instruction
* vec
)
121 add_label(label_vec
);
127 return label
& label_vec
;
130 void set_constant(uint32_t constant
)
132 add_label(label_constant
);
138 return label
& label_constant
;
141 void set_abs(Temp abs_temp
)
143 add_label(label_abs
);
149 return label
& label_abs
;
152 void set_neg(Temp neg_temp
)
154 add_label(label_neg
);
160 return label
& label_neg
;
163 void set_neg_abs(Temp neg_abs_temp
)
165 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
169 void set_mul(Instruction
* mul
)
171 add_label(label_mul
);
177 return label
& label_mul
;
180 void set_temp(Temp tmp
)
182 add_label(label_temp
);
188 return label
& label_temp
;
191 void set_literal(uint32_t lit
)
193 add_label(label_literal
);
199 return label
& label_literal
;
202 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
204 add_label(label_mad
);
211 return label
& label_mad
;
214 void set_omod2(Temp def
)
216 add_label(label_omod2
);
222 return label
& label_omod2
;
225 void set_omod4(Temp def
)
227 add_label(label_omod4
);
233 return label
& label_omod4
;
236 void set_omod5(Temp def
)
238 add_label(label_omod5
);
244 return label
& label_omod5
;
247 void set_omod_success(Instruction
* omod_instr
)
249 add_label(label_omod_success
);
253 bool is_omod_success()
255 return label
& label_omod_success
;
258 void set_clamp(Temp def
)
260 add_label(label_clamp
);
266 return label
& label_clamp
;
269 void set_clamp_success(Instruction
* clamp_instr
)
271 add_label(label_clamp_success
);
275 bool is_clamp_success()
277 return label
& label_clamp_success
;
282 add_label(label_undefined
);
287 return label
& label_undefined
;
290 void set_vcc(Temp vcc
)
292 add_label(label_vcc
);
298 return label
& label_vcc
;
301 bool is_constant_or_literal()
303 return is_constant() || is_literal();
306 void set_b2f(Temp val
)
308 add_label(label_b2f
);
314 return label
& label_b2f
;
317 void set_add_sub(Instruction
*add_sub_instr
)
319 add_label(label_add_sub
);
320 instr
= add_sub_instr
;
325 return label
& label_add_sub
;
328 void set_bitwise(Instruction
*bitwise_instr
)
330 add_label(label_bitwise
);
331 instr
= bitwise_instr
;
336 return label
& label_bitwise
;
339 void set_minmax(Instruction
*minmax_instr
)
341 add_label(label_minmax
);
342 instr
= minmax_instr
;
347 return label
& label_minmax
;
350 void set_fcmp(Instruction
*fcmp_instr
)
352 add_label(label_fcmp
);
358 return label
& label_fcmp
;
361 void set_uniform_bool(Temp uniform_bool
)
363 add_label(label_uniform_bool
);
367 bool is_uniform_bool()
369 return label
& label_uniform_bool
;
376 std::vector
<aco_ptr
<Instruction
>> instructions
;
378 std::pair
<uint32_t,Temp
> last_literal
;
379 std::vector
<mad_info
> mad_infos
;
380 std::vector
<uint16_t> uses
;
383 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
385 if (instr
->operands
[0].isConstant() ||
386 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
389 switch (instr
->opcode
) {
390 case aco_opcode::v_add_f32
:
391 case aco_opcode::v_mul_f32
:
392 case aco_opcode::v_or_b32
:
393 case aco_opcode::v_and_b32
:
394 case aco_opcode::v_xor_b32
:
395 case aco_opcode::v_max_f32
:
396 case aco_opcode::v_min_f32
:
397 case aco_opcode::v_cmp_eq_f32
:
398 case aco_opcode::v_cmp_lg_f32
:
400 case aco_opcode::v_sub_f32
:
401 instr
->opcode
= aco_opcode::v_subrev_f32
;
403 case aco_opcode::v_cmp_lt_f32
:
404 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
406 case aco_opcode::v_cmp_ge_f32
:
407 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
409 case aco_opcode::v_cmp_lt_i32
:
410 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
417 bool can_use_VOP3(aco_ptr
<Instruction
>& instr
)
422 if (instr
->operands
.size() && instr
->operands
[0].isLiteral())
425 if (instr
->isDPP() || instr
->isSDWA())
428 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
429 instr
->opcode
!= aco_opcode::v_madak_f32
&&
430 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
431 instr
->opcode
!= aco_opcode::v_madak_f16
&&
432 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
433 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
434 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
435 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
436 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
437 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
438 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
441 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
443 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
444 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
445 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
446 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
447 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
450 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
455 assert(!instr
->operands
[0].isLiteral());
456 aco_ptr
<Instruction
> tmp
= std::move(instr
);
457 Format format
= asVOP3(tmp
->format
);
458 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
459 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
460 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
461 instr
->definitions
[i
] = tmp
->definitions
[i
];
462 if (instr
->definitions
[i
].isTemp()) {
463 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
464 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
465 info
.instr
= instr
.get();
470 /* only covers special cases */
471 bool can_accept_constant(aco_ptr
<Instruction
>& instr
, unsigned operand
)
473 switch (instr
->opcode
) {
474 case aco_opcode::v_interp_p2_f32
:
475 case aco_opcode::v_mac_f32
:
476 case aco_opcode::v_writelane_b32
:
477 case aco_opcode::v_writelane_b32_e64
:
478 case aco_opcode::v_cndmask_b32
:
480 case aco_opcode::s_addk_i32
:
481 case aco_opcode::s_mulk_i32
:
482 case aco_opcode::p_wqm
:
483 case aco_opcode::p_extract_vector
:
484 case aco_opcode::p_split_vector
:
485 case aco_opcode::v_readlane_b32
:
486 case aco_opcode::v_readlane_b32_e64
:
487 case aco_opcode::v_readfirstlane_b32
:
490 if ((instr
->format
== Format::MUBUF
||
491 instr
->format
== Format::MIMG
) &&
492 instr
->definitions
.size() == 1 &&
493 instr
->operands
.size() == 4) {
500 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
502 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
503 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
508 /* check constant bus and literal limitations */
509 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
512 unsigned num_sgprs
= 0;
513 unsigned sgpr
[] = {0, 0};
515 for (unsigned i
= 0; i
< num_operands
; i
++) {
516 Operand op
= operands
[i
];
518 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
519 /* two reads of the same SGPR count as 1 to the limit */
520 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
522 sgpr
[num_sgprs
++] = op
.tempId();
527 } else if (op
.isLiteral()) {
535 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
537 Operand op
= instr
->operands
[op_index
];
541 Temp tmp
= op
.getTemp();
542 if (!ctx
.info
[tmp
.id()].is_add_sub())
545 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
547 switch (add_instr
->opcode
) {
548 case aco_opcode::v_add_u32
:
549 case aco_opcode::v_add_co_u32
:
550 case aco_opcode::s_add_i32
:
551 case aco_opcode::s_add_u32
:
557 if (add_instr
->usesModifiers())
560 for (unsigned i
= 0; i
< 2; i
++) {
561 if (add_instr
->operands
[i
].isConstant()) {
562 *offset
= add_instr
->operands
[i
].constantValue();
563 } else if (add_instr
->operands
[i
].isTemp() &&
564 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
565 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
569 if (!add_instr
->operands
[!i
].isTemp())
572 uint32_t offset2
= 0;
573 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
576 *base
= add_instr
->operands
[!i
].getTemp();
584 Operand
get_constant_op(opt_ctx
&ctx
, uint32_t val
)
586 // TODO: this functions shouldn't be needed if we store Operand instead of value.
588 if (val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
589 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
593 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
595 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
596 ASSERTED
bool all_const
= false;
597 for (Operand
& op
: instr
->operands
)
598 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
599 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
602 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
604 if (!instr
->operands
[i
].isTemp())
607 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
608 /* propagate undef */
609 if (info
.is_undefined() && is_phi(instr
))
610 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
611 /* propagate reg->reg of same type */
612 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
613 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
614 info
= ctx
.info
[info
.temp
.id()];
617 /* SALU / PSEUDO: propagate inline constants */
618 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
619 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
620 instr
->operands
[i
].setTemp(info
.temp
);
621 info
= ctx
.info
[info
.temp
.id()];
622 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
623 /* propagate vgpr if it can take it */
624 switch (instr
->opcode
) {
625 case aco_opcode::p_create_vector
:
626 case aco_opcode::p_split_vector
:
627 case aco_opcode::p_extract_vector
:
628 case aco_opcode::p_phi
: {
629 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
630 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
632 instr
->operands
[i
] = Operand(info
.temp
);
633 info
= ctx
.info
[info
.temp
.id()];
641 if ((info
.is_constant() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) && !instr
->operands
[i
].isFixed() && can_accept_constant(instr
, i
)) {
642 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
647 /* VALU: propagate neg, abs & inline constants */
648 else if (instr
->isVALU()) {
649 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
650 instr
->operands
[i
].setTemp(info
.temp
);
651 info
= ctx
.info
[info
.temp
.id()];
653 if (info
.is_abs() && (can_use_VOP3(instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
656 instr
->operands
[i
] = Operand(info
.temp
);
658 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
660 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
662 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
663 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
664 instr
->operands
[i
].setTemp(info
.temp
);
666 } else if (info
.is_neg() && (can_use_VOP3(instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
669 instr
->operands
[i
].setTemp(info
.temp
);
671 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
673 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
676 if (info
.is_constant() && can_accept_constant(instr
, i
)) {
677 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
678 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
679 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
681 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
682 instr
->operands
[i
] = instr
->operands
[0];
683 instr
->operands
[0] = get_constant_op(ctx
, info
.val
);
685 } else if (can_use_VOP3(instr
)) {
687 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
693 /* MUBUF: propagate constants and combine additions */
694 else if (instr
->format
== Format::MUBUF
) {
695 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
698 while (info
.is_temp())
699 info
= ctx
.info
[info
.temp
.id()];
701 if (mubuf
->offen
&& i
== 0 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
702 assert(!mubuf
->idxen
);
703 instr
->operands
[i
] = Operand(v1
);
704 mubuf
->offset
+= info
.val
;
705 mubuf
->offen
= false;
707 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
708 instr
->operands
[2] = Operand((uint32_t) 0);
709 mubuf
->offset
+= info
.val
;
711 } else if (mubuf
->offen
&& i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
712 assert(!mubuf
->idxen
);
713 instr
->operands
[i
].setTemp(base
);
714 mubuf
->offset
+= offset
;
716 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
717 instr
->operands
[i
].setTemp(base
);
718 mubuf
->offset
+= offset
;
723 /* DS: combine additions */
724 else if (instr
->format
== Format::DS
) {
726 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
729 if (i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == instr
->operands
[i
].regClass() && instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
730 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
731 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
732 if (offset
% 4 == 0 &&
733 ds
->offset0
+ (offset
>> 2) <= 255 &&
734 ds
->offset1
+ (offset
>> 2) <= 255) {
735 instr
->operands
[i
].setTemp(base
);
736 ds
->offset0
+= offset
>> 2;
737 ds
->offset1
+= offset
>> 2;
740 if (ds
->offset0
+ offset
<= 65535) {
741 instr
->operands
[i
].setTemp(base
);
742 ds
->offset0
+= offset
;
748 /* SMEM: propagate constants and combine additions */
749 else if (instr
->format
== Format::SMEM
) {
751 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
754 if (i
== 1 && info
.is_constant_or_literal() &&
755 (ctx
.program
->chip_class
< GFX8
|| info
.val
<= 0xFFFFF)) {
756 instr
->operands
[i
] = Operand(info
.val
);
758 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
759 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
761 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
762 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
766 smem
->operands
[1] = Operand(offset
);
767 smem
->operands
.back() = Operand(base
);
769 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
770 new_instr
->operands
[0] = smem
->operands
[0];
771 new_instr
->operands
[1] = Operand(offset
);
772 if (smem
->definitions
.empty())
773 new_instr
->operands
[2] = smem
->operands
[2];
774 new_instr
->operands
.back() = Operand(base
);
775 if (!smem
->definitions
.empty())
776 new_instr
->definitions
[0] = smem
->definitions
[0];
777 new_instr
->can_reorder
= smem
->can_reorder
;
778 new_instr
->barrier
= smem
->barrier
;
779 instr
.reset(new_instr
);
780 smem
= static_cast<SMEM_instruction
*>(instr
.get());
787 /* if this instruction doesn't define anything, return */
788 if (instr
->definitions
.empty())
791 switch (instr
->opcode
) {
792 case aco_opcode::p_create_vector
: {
793 unsigned num_ops
= instr
->operands
.size();
794 for (const Operand
& op
: instr
->operands
) {
795 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
796 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
798 if (num_ops
!= instr
->operands
.size()) {
799 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
800 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
801 instr
->definitions
[0] = old_vec
->definitions
[0];
803 for (Operand
& old_op
: old_vec
->operands
) {
804 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
805 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
806 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
807 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
808 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
809 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
810 instr
->operands
[k
++] = op
;
813 instr
->operands
[k
++] = old_op
;
816 assert(k
== num_ops
);
818 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
819 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
820 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
821 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
824 case aco_opcode::p_split_vector
: {
825 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
827 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
828 assert(instr
->definitions
.size() == vec
->operands
.size());
829 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
830 Operand vec_op
= vec
->operands
[i
];
831 if (vec_op
.isConstant()) {
832 if (vec_op
.isLiteral())
833 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
834 else if (vec_op
.size() == 1)
835 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
837 assert(vec_op
.isTemp());
838 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
843 case aco_opcode::p_extract_vector
: { /* mov */
844 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
846 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
847 if (vec
->definitions
[0].getTemp().size() == vec
->operands
.size() && /* TODO: what about 64bit or other combinations? */
848 vec
->operands
[0].size() == instr
->definitions
[0].size()) {
850 /* convert this extract into a mov instruction */
851 Operand vec_op
= vec
->operands
[instr
->operands
[1].constantValue()];
852 bool is_vgpr
= instr
->definitions
[0].getTemp().type() == RegType::vgpr
;
853 aco_opcode opcode
= is_vgpr
? aco_opcode::v_mov_b32
: aco_opcode::s_mov_b32
;
854 Format format
= is_vgpr
? Format::VOP1
: Format::SOP1
;
855 instr
->opcode
= opcode
;
856 instr
->format
= format
;
857 while (instr
->operands
.size() > 1)
858 instr
->operands
.pop_back();
859 instr
->operands
[0] = vec_op
;
861 if (vec_op
.isConstant()) {
862 if (vec_op
.isLiteral())
863 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(vec_op
.constantValue());
864 else if (vec_op
.size() == 1)
865 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(vec_op
.constantValue());
867 assert(vec_op
.isTemp());
868 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vec_op
.getTemp());
873 case aco_opcode::s_mov_b32
: /* propagate */
874 case aco_opcode::s_mov_b64
:
875 case aco_opcode::v_mov_b32
:
876 case aco_opcode::p_as_uniform
:
877 if (instr
->definitions
[0].isFixed()) {
878 /* don't copy-propagate copies into fixed registers */
879 } else if (instr
->usesModifiers()) {
881 } else if (instr
->operands
[0].isConstant()) {
882 if (instr
->operands
[0].isLiteral())
883 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
884 else if (instr
->operands
[0].size() == 1)
885 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
886 } else if (instr
->operands
[0].isTemp()) {
887 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
889 assert(instr
->operands
[0].isFixed());
892 case aco_opcode::p_is_helper
:
893 if (!ctx
.program
->needs_wqm
)
894 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
896 case aco_opcode::s_movk_i32
: {
897 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
898 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
899 if (v
<= 64 || v
>= 0xfffffff0)
900 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
902 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
905 case aco_opcode::v_bfrev_b32
:
906 case aco_opcode::s_brev_b32
: {
907 if (instr
->operands
[0].isConstant()) {
908 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
909 if (v
<= 64 || v
>= 0xfffffff0)
910 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
912 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
916 case aco_opcode::s_bfm_b32
: {
917 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
918 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
919 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
920 uint32_t v
= ((1u << size
) - 1u) << start
;
921 if (v
<= 64 || v
>= 0xfffffff0)
922 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
924 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
927 case aco_opcode::v_mul_f32
: { /* omod */
928 /* TODO: try to move the negate/abs modifier to the consumer instead */
929 if (instr
->usesModifiers())
932 for (unsigned i
= 0; i
< 2; i
++) {
933 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
934 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
935 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
936 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
937 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
938 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
939 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
940 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000 &&
941 !block
.fp_mode
.must_flush_denorms32
) { /* 1.0 */
942 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
951 case aco_opcode::v_and_b32
: /* abs */
952 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x7FFFFFFF) &&
953 instr
->operands
[1].isTemp() && instr
->operands
[1].getTemp().type() == RegType::vgpr
)
954 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
956 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
958 case aco_opcode::v_xor_b32
: { /* neg */
959 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
960 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
961 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
962 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
963 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
964 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
965 instr
->opcode
= aco_opcode::v_or_b32
;
966 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
968 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
972 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
976 case aco_opcode::v_med3_f32
: { /* clamp */
977 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
978 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
979 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
980 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
984 bool found_zero
= false, found_one
= false;
985 for (unsigned i
= 0; i
< 3; i
++)
987 if (instr
->operands
[i
].constantEquals(0))
989 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
994 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
995 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
999 case aco_opcode::v_cndmask_b32
:
1000 if (instr
->operands
[0].constantEquals(0) &&
1001 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
1002 instr
->operands
[2].isTemp())
1003 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1004 else if (instr
->operands
[0].constantEquals(0) &&
1005 instr
->operands
[1].constantEquals(0x3f800000u
) &&
1006 instr
->operands
[2].isTemp())
1007 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1009 case aco_opcode::v_cmp_lg_u32
:
1010 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1011 instr
->operands
[0].constantEquals(0) &&
1012 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1013 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1015 case aco_opcode::p_phi
:
1016 case aco_opcode::p_linear_phi
: {
1017 /* lower_bool_phis() can create phis like this */
1018 bool all_same_temp
= instr
->operands
[0].isTemp();
1019 /* this check is needed when moving uniform loop counters out of a divergent loop */
1021 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1022 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1023 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1024 all_same_temp
= false;
1026 if (all_same_temp
) {
1027 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1029 bool all_undef
= instr
->operands
[0].isUndefined();
1030 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1031 if (!instr
->operands
[i
].isUndefined())
1035 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1039 case aco_opcode::v_add_u32
:
1040 case aco_opcode::v_add_co_u32
:
1041 case aco_opcode::s_add_i32
:
1042 case aco_opcode::s_add_u32
:
1043 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1045 case aco_opcode::s_and_b32
:
1046 case aco_opcode::s_and_b64
:
1047 if (instr
->operands
[1].isFixed() && instr
->operands
[1].physReg() == exec
&&
1048 instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1049 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1052 case aco_opcode::s_not_b32
:
1053 case aco_opcode::s_not_b64
:
1054 case aco_opcode::s_or_b32
:
1055 case aco_opcode::s_or_b64
:
1056 case aco_opcode::s_xor_b32
:
1057 case aco_opcode::s_xor_b64
:
1058 case aco_opcode::s_lshl_b32
:
1059 case aco_opcode::v_or_b32
:
1060 case aco_opcode::v_lshlrev_b32
:
1061 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1063 case aco_opcode::v_min_f32
:
1064 case aco_opcode::v_min_f16
:
1065 case aco_opcode::v_min_u32
:
1066 case aco_opcode::v_min_i32
:
1067 case aco_opcode::v_min_u16
:
1068 case aco_opcode::v_min_i16
:
1069 case aco_opcode::v_max_f32
:
1070 case aco_opcode::v_max_f16
:
1071 case aco_opcode::v_max_u32
:
1072 case aco_opcode::v_max_i32
:
1073 case aco_opcode::v_max_u16
:
1074 case aco_opcode::v_max_i16
:
1075 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1077 case aco_opcode::v_cmp_lt_f32
:
1078 case aco_opcode::v_cmp_eq_f32
:
1079 case aco_opcode::v_cmp_le_f32
:
1080 case aco_opcode::v_cmp_gt_f32
:
1081 case aco_opcode::v_cmp_lg_f32
:
1082 case aco_opcode::v_cmp_ge_f32
:
1083 case aco_opcode::v_cmp_o_f32
:
1084 case aco_opcode::v_cmp_u_f32
:
1085 case aco_opcode::v_cmp_nge_f32
:
1086 case aco_opcode::v_cmp_nlg_f32
:
1087 case aco_opcode::v_cmp_ngt_f32
:
1088 case aco_opcode::v_cmp_nle_f32
:
1089 case aco_opcode::v_cmp_neq_f32
:
1090 case aco_opcode::v_cmp_nlt_f32
:
1091 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1093 case aco_opcode::s_cselect_b64
:
1094 case aco_opcode::s_cselect_b32
:
1095 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1096 instr
->operands
[1].constantEquals(0)) {
1097 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1098 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1106 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1108 *ordered
= *unordered
= op
;
1110 #define CMP(ord, unord) \
1111 case aco_opcode::v_cmp_##ord##_f32:\
1112 case aco_opcode::v_cmp_n##unord##_f32:\
1113 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1114 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1115 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1129 aco_opcode
get_ordered(aco_opcode op
)
1131 aco_opcode ordered
, unordered
, inverse
;
1132 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1135 aco_opcode
get_unordered(aco_opcode op
)
1137 aco_opcode ordered
, unordered
, inverse
;
1138 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1141 aco_opcode
get_inverse(aco_opcode op
)
1143 aco_opcode ordered
, unordered
, inverse
;
1144 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1147 bool is_cmp(aco_opcode op
)
1149 aco_opcode ordered
, unordered
, inverse
;
1150 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1153 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1155 if (ctx
.info
[tmp
.id()].is_temp())
1156 return ctx
.info
[tmp
.id()].temp
.id();
1161 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1163 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1164 for (const Operand
& op
: instr
->operands
) {
1166 ctx
.uses
[op
.tempId()]--;
1171 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1173 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1175 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1178 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1180 if (instr
->definitions
.size() == 2) {
1181 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1182 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1189 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1190 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1191 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1193 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1195 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1198 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1200 bool neg
[2] = {false, false};
1201 bool abs
[2] = {false, false};
1203 Instruction
*op_instr
[2];
1206 for (unsigned i
= 0; i
< 2; i
++) {
1207 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1211 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1213 if (op_instr
[i
]->opcode
!= expected_cmp
)
1215 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1218 if (op_instr
[i
]->isVOP3()) {
1219 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1220 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1222 neg
[i
] = vop3
->neg
[0];
1223 abs
[i
] = vop3
->abs
[0];
1224 opsel
|= (vop3
->opsel
& 1) << i
;
1227 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1228 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1229 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1235 if (op
[1].type() == RegType::sgpr
)
1236 std::swap(op
[0], op
[1]);
1237 //TODO: we can use two different SGPRs on GFX10
1238 if (op
[0].type() == RegType::sgpr
&& op
[1].type() == RegType::sgpr
)
1241 ctx
.uses
[op
[0].id()]++;
1242 ctx
.uses
[op
[1].id()]++;
1243 decrease_uses(ctx
, op_instr
[0]);
1244 decrease_uses(ctx
, op_instr
[1]);
1246 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1247 Instruction
*new_instr
;
1248 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
) {
1249 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1250 for (unsigned i
= 0; i
< 2; i
++) {
1251 vop3
->neg
[i
] = neg
[i
];
1252 vop3
->abs
[i
] = abs
[i
];
1254 vop3
->opsel
= opsel
;
1255 new_instr
= static_cast<Instruction
*>(vop3
);
1257 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1259 new_instr
->operands
[0] = Operand(op
[0]);
1260 new_instr
->operands
[1] = Operand(op
[1]);
1261 new_instr
->definitions
[0] = instr
->definitions
[0];
1263 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1264 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1266 instr
.reset(new_instr
);
1271 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1272 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1273 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1275 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1277 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1280 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1281 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1283 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1284 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1285 if (!nan_test
|| !cmp
)
1288 if (cmp
->opcode
== expected_nan_test
)
1289 std::swap(nan_test
, cmp
);
1290 else if (nan_test
->opcode
!= expected_nan_test
)
1293 if (!is_cmp(cmp
->opcode
))
1296 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1298 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1301 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1302 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1303 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1304 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1305 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1307 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1310 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1311 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1312 decrease_uses(ctx
, nan_test
);
1313 decrease_uses(ctx
, cmp
);
1315 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1316 Instruction
*new_instr
;
1317 if (cmp
->isVOP3()) {
1318 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1319 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1320 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1321 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1322 new_vop3
->clamp
= cmp_vop3
->clamp
;
1323 new_vop3
->omod
= cmp_vop3
->omod
;
1324 new_vop3
->opsel
= cmp_vop3
->opsel
;
1325 new_instr
= new_vop3
;
1327 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1329 new_instr
->operands
[0] = cmp
->operands
[0];
1330 new_instr
->operands
[1] = cmp
->operands
[1];
1331 new_instr
->definitions
[0] = instr
->definitions
[0];
1333 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1334 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1336 instr
.reset(new_instr
);
1341 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1342 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1343 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1345 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1347 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1350 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1352 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1353 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1355 if (!nan_test
|| !cmp
)
1358 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1359 if (cmp
->opcode
== expected_nan_test
)
1360 std::swap(nan_test
, cmp
);
1361 else if (nan_test
->opcode
!= expected_nan_test
)
1364 if (!is_cmp(cmp
->opcode
))
1367 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1369 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1372 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1373 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1374 if (prop_nan0
!= prop_nan1
)
1377 if (nan_test
->isVOP3()) {
1378 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1379 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1383 int constant_operand
= -1;
1384 for (unsigned i
= 0; i
< 2; i
++) {
1385 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1386 constant_operand
= !i
;
1390 if (constant_operand
== -1)
1394 if (cmp
->operands
[constant_operand
].isConstant()) {
1395 constant
= cmp
->operands
[constant_operand
].constantValue();
1396 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1397 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1398 unsigned id
= original_temp_id(ctx
, tmp
);
1399 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1401 constant
= ctx
.info
[id
].val
;
1407 memcpy(&constantf
, &constant
, 4);
1408 if (isnan(constantf
))
1411 if (cmp
->operands
[0].isTemp())
1412 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1413 if (cmp
->operands
[1].isTemp())
1414 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1415 decrease_uses(ctx
, nan_test
);
1416 decrease_uses(ctx
, cmp
);
1418 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1419 Instruction
*new_instr
;
1420 if (cmp
->isVOP3()) {
1421 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1422 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1423 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1424 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1425 new_vop3
->clamp
= cmp_vop3
->clamp
;
1426 new_vop3
->omod
= cmp_vop3
->omod
;
1427 new_vop3
->opsel
= cmp_vop3
->opsel
;
1428 new_instr
= new_vop3
;
1430 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1432 new_instr
->operands
[0] = cmp
->operands
[0];
1433 new_instr
->operands
[1] = cmp
->operands
[1];
1434 new_instr
->definitions
[0] = instr
->definitions
[0];
1436 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1437 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1439 instr
.reset(new_instr
);
1444 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1445 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1447 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1449 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1451 if (!instr
->operands
[0].isTemp())
1454 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1458 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1459 if (new_opcode
== aco_opcode::last_opcode
)
1462 if (cmp
->operands
[0].isTemp())
1463 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1464 if (cmp
->operands
[1].isTemp())
1465 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1466 decrease_uses(ctx
, cmp
);
1468 Instruction
*new_instr
;
1469 if (cmp
->isVOP3()) {
1470 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1471 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1472 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1473 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1474 new_vop3
->clamp
= cmp_vop3
->clamp
;
1475 new_vop3
->omod
= cmp_vop3
->omod
;
1476 new_vop3
->opsel
= cmp_vop3
->opsel
;
1477 new_instr
= new_vop3
;
1479 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1481 new_instr
->operands
[0] = cmp
->operands
[0];
1482 new_instr
->operands
[1] = cmp
->operands
[1];
1483 new_instr
->definitions
[0] = instr
->definitions
[0];
1485 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1486 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1488 instr
.reset(new_instr
);
1493 /* op1(op2(1, 2), 0) if swap = false
1494 * op1(0, op2(1, 2)) if swap = true */
1495 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1496 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1497 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1498 bool *op1_clamp
, uint8_t *op1_omod
,
1499 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1502 if (op1_instr
->opcode
!= op1
)
1505 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1506 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1509 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1510 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1512 /* don't support inbetween clamp/omod */
1513 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1516 /* get operands and modifiers and check inbetween modifiers */
1517 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1518 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1521 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1522 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1526 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1527 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1530 if (inbetween_opsel
)
1531 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1532 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1536 shuffle
[shuffle_str
[0] - '0'] = 0;
1537 shuffle
[shuffle_str
[1] - '0'] = 1;
1538 shuffle
[shuffle_str
[2] - '0'] = 2;
1540 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1541 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1542 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1543 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1544 *opsel
|= 1 << shuffle
[0];
1546 for (unsigned i
= 0; i
< 2; i
++) {
1547 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1548 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1549 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1550 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1551 *opsel
|= 1 << shuffle
[i
+ 1];
1554 /* check operands */
1555 if (!check_vop3_operands(ctx
, 3, operands
))
1561 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1562 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1563 bool clamp
, unsigned omod
)
1565 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1566 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1567 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1568 new_instr
->clamp
= clamp
;
1569 new_instr
->omod
= omod
;
1570 new_instr
->opsel
= opsel
;
1571 new_instr
->operands
[0] = operands
[0];
1572 new_instr
->operands
[1] = operands
[1];
1573 new_instr
->operands
[2] = operands
[2];
1574 new_instr
->definitions
[0] = instr
->definitions
[0];
1575 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1577 instr
.reset(new_instr
);
1580 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1582 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1583 (label_omod_success
| label_clamp_success
);
1585 for (unsigned swap
= 0; swap
< 2; swap
++) {
1586 if (!((1 << swap
) & ops
))
1589 Operand operands
[3];
1590 bool neg
[3], abs
[3], clamp
;
1591 uint8_t opsel
= 0, omod
= 0;
1592 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1593 instr
.get(), swap
, shuffle
,
1594 operands
, neg
, abs
, &opsel
,
1595 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1596 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1597 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1598 if (omod_clamp
& label_omod_success
)
1599 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1600 if (omod_clamp
& label_clamp_success
)
1601 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1608 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1609 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1610 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1611 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1612 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1613 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1614 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1617 if (!instr
->operands
[0].isTemp())
1619 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1622 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1625 switch (op2_instr
->opcode
) {
1626 case aco_opcode::s_and_b32
:
1627 case aco_opcode::s_or_b32
:
1628 case aco_opcode::s_xor_b32
:
1629 case aco_opcode::s_and_b64
:
1630 case aco_opcode::s_or_b64
:
1631 case aco_opcode::s_xor_b64
:
1637 /* create instruction */
1638 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1639 ctx
.uses
[instr
->operands
[0].tempId()]--;
1640 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1642 switch (op2_instr
->opcode
) {
1643 case aco_opcode::s_and_b32
:
1644 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1646 case aco_opcode::s_or_b32
:
1647 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1649 case aco_opcode::s_xor_b32
:
1650 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1652 case aco_opcode::s_and_b64
:
1653 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1655 case aco_opcode::s_or_b64
:
1656 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1658 case aco_opcode::s_xor_b64
:
1659 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1668 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1669 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1670 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1671 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1672 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1674 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1677 for (unsigned i
= 0; i
< 2; i
++) {
1678 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1679 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1682 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1683 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1686 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1687 instr
->operands
[0] = instr
->operands
[!i
];
1688 instr
->operands
[1] = op2_instr
->operands
[0];
1689 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1691 switch (instr
->opcode
) {
1692 case aco_opcode::s_and_b32
:
1693 instr
->opcode
= aco_opcode::s_andn2_b32
;
1695 case aco_opcode::s_or_b32
:
1696 instr
->opcode
= aco_opcode::s_orn2_b32
;
1698 case aco_opcode::s_and_b64
:
1699 instr
->opcode
= aco_opcode::s_andn2_b64
;
1701 case aco_opcode::s_or_b64
:
1702 instr
->opcode
= aco_opcode::s_orn2_b64
;
1713 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1714 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1716 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1719 for (unsigned i
= 0; i
< 2; i
++) {
1720 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1721 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
|| !op2_instr
->operands
[1].isConstant())
1724 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1725 if (shift
< 1 || shift
> 4)
1728 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1729 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1732 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1733 instr
->operands
[1] = instr
->operands
[!i
];
1734 instr
->operands
[0] = op2_instr
->operands
[0];
1735 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1737 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1738 aco_opcode::s_lshl2_add_u32
,
1739 aco_opcode::s_lshl3_add_u32
,
1740 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1747 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1750 #define MINMAX(type, gfx9) \
1751 case aco_opcode::v_min_##type:\
1752 case aco_opcode::v_max_##type:\
1753 case aco_opcode::v_med3_##type:\
1754 *min = aco_opcode::v_min_##type;\
1755 *max = aco_opcode::v_max_##type;\
1756 *med3 = aco_opcode::v_med3_##type;\
1757 *min3 = aco_opcode::v_min3_##type;\
1758 *max3 = aco_opcode::v_max3_##type;\
1759 *some_gfx9_only = gfx9;\
1773 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1774 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1775 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1776 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1778 aco_opcode other_op
;
1779 if (instr
->opcode
== min
)
1781 else if (instr
->opcode
== max
)
1786 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1787 (label_omod_success
| label_clamp_success
);
1789 for (unsigned swap
= 0; swap
< 2; swap
++) {
1790 Operand operands
[3];
1791 bool neg
[3], abs
[3], clamp
, inbetween_neg
, inbetween_abs
;
1792 uint8_t opsel
= 0, omod
= 0;
1793 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1794 "012", operands
, neg
, abs
, &opsel
,
1795 &clamp
, &omod
, &inbetween_neg
, &inbetween_abs
, NULL
)) {
1796 int const0_idx
= -1, const1_idx
= -1;
1797 uint32_t const0
= 0, const1
= 0;
1798 for (int i
= 0; i
< 3; i
++) {
1800 if (operands
[i
].isConstant()) {
1801 val
= operands
[i
].constantValue();
1802 } else if (operands
[i
].isTemp() && ctx
.uses
[operands
[i
].tempId()] == 1 &&
1803 ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
1804 val
= ctx
.info
[operands
[i
].tempId()].val
;
1808 if (const0_idx
>= 0) {
1816 if (const0_idx
< 0 || const1_idx
< 0)
1819 if (opsel
& (1 << const0_idx
))
1821 if (opsel
& (1 << const1_idx
))
1824 int lower_idx
= const0_idx
;
1826 case aco_opcode::v_min_f32
:
1827 case aco_opcode::v_min_f16
: {
1828 float const0_f
, const1_f
;
1829 if (min
== aco_opcode::v_min_f32
) {
1830 memcpy(&const0_f
, &const0
, 4);
1831 memcpy(&const1_f
, &const1
, 4);
1833 const0_f
= _mesa_half_to_float(const0
);
1834 const1_f
= _mesa_half_to_float(const1
);
1836 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
1837 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
1838 if (neg
[const0_idx
]) const0_f
= -const0_f
;
1839 if (neg
[const1_idx
]) const1_f
= -const1_f
;
1840 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
1843 case aco_opcode::v_min_u32
: {
1844 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
1847 case aco_opcode::v_min_u16
: {
1848 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
1851 case aco_opcode::v_min_i32
: {
1852 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
1853 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
1854 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1857 case aco_opcode::v_min_i16
: {
1858 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
1859 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
1860 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1866 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
1868 if (instr
->opcode
== min
) {
1869 if (upper_idx
!= 0 || lower_idx
== 0)
1872 if (upper_idx
== 0 || lower_idx
!= 0)
1876 neg
[1] ^= inbetween_neg
;
1877 neg
[2] ^= inbetween_neg
;
1878 abs
[1] |= inbetween_abs
;
1879 abs
[2] |= inbetween_abs
;
1881 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1882 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1883 if (omod_clamp
& label_omod_success
)
1884 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1885 if (omod_clamp
& label_clamp_success
)
1886 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1896 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1898 /* find candidates and create the set of sgprs already read */
1899 unsigned sgpr_ids
[2] = {0, 0};
1900 uint32_t operand_mask
= 0;
1901 bool has_literal
= false;
1902 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
1903 if (instr
->operands
[i
].isLiteral())
1905 if (!instr
->operands
[i
].isTemp())
1907 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
1908 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
1909 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
1911 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
1912 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
1913 operand_mask
|= 1u << i
;
1915 unsigned max_sgprs
= 1;
1919 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
1921 /* keep on applying sgprs until there is nothing left to be done */
1922 while (operand_mask
) {
1923 uint32_t sgpr_idx
= 0;
1924 uint32_t sgpr_info_id
= 0;
1925 uint32_t mask
= operand_mask
;
1928 unsigned i
= u_bit_scan(&mask
);
1929 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
1930 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
1932 sgpr_info_id
= instr
->operands
[i
].tempId();
1935 operand_mask
&= ~(1u << sgpr_idx
);
1937 /* Applying two sgprs require making it VOP3, so don't do it unless it's
1938 * definitively beneficial.
1939 * TODO: this is too conservative because later the use count could be reduced to 1 */
1940 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1)
1943 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
1944 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
1945 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
1948 if (sgpr_idx
== 0 || instr
->isVOP3()) {
1949 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
1950 } else if (can_swap_operands(instr
)) {
1951 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
1952 instr
->operands
[0] = Operand(sgpr
);
1953 /* swap bits using a 4-entry LUT */
1954 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
1955 operand_mask
= (operand_mask
& ~0x3) | swapped
;
1956 } else if (can_use_VOP3(instr
)) {
1957 to_VOP3(ctx
, instr
);
1958 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
1963 sgpr_ids
[num_sgprs
++] = sgpr
.id();
1964 ctx
.uses
[sgpr_info_id
]--;
1965 ctx
.uses
[sgpr
.id()]++;
1967 break; /* for testing purposes, only apply 1 new sgpr */
1971 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
1973 /* check if we could apply omod on predecessor */
1974 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
1975 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
1976 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
1978 unsigned idx
= op0
? 0 : 1;
1979 /* omod was successfully applied */
1980 /* if the omod instruction is v_mad, we also have to change the original add */
1981 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
1982 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
1983 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
1984 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
1985 add_instr
->definitions
[0] = instr
->definitions
[0];
1988 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
1989 /* check if we have an additional clamp modifier */
1990 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
1991 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
1992 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
1993 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
1995 /* change definition ssa-id of modified instruction */
1996 omod_instr
->definitions
[0] = instr
->definitions
[0];
1998 /* change the definition of instr to something unused, e.g. the original omod def */
1999 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2000 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2003 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2004 /* in all other cases, label this instruction as option for multiply-add */
2005 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2009 /* check if we could apply clamp on predecessor */
2010 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
2012 bool found_zero
= false, found_one
= false;
2013 for (unsigned i
= 0; i
< 3; i
++)
2015 if (instr
->operands
[i
].constantEquals(0))
2017 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
2022 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2023 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2024 /* clamp was successfully applied */
2025 /* if the clamp instruction is v_mad, we also have to change the original add */
2026 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2027 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2028 add_instr
->definitions
[0] = instr
->definitions
[0];
2030 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2031 /* change definition ssa-id of modified instruction */
2032 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2034 /* change the definition of instr to something unused, e.g. the original omod def */
2035 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2036 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2041 /* omod has no effect if denormals are enabled */
2042 bool can_use_omod
= block
.fp_mode
.denorm32
== 0;
2044 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2045 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2046 can_use_VOP3(instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2047 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2048 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2049 to_VOP3(ctx
, instr
);
2050 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2051 def_info
.set_omod_success(instr
.get());
2052 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2053 to_VOP3(ctx
, instr
);
2054 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2055 def_info
.set_omod_success(instr
.get());
2056 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2057 to_VOP3(ctx
, instr
);
2058 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2059 def_info
.set_omod_success(instr
.get());
2060 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2061 to_VOP3(ctx
, instr
);
2062 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2063 def_info
.set_clamp_success(instr
.get());
2070 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2071 // this would mean that we'd have to fix the instruction uses while value propagation
2073 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2075 if (instr
->definitions
.empty() || !ctx
.uses
[instr
->definitions
[0].tempId()])
2078 if (instr
->isVALU()) {
2079 if (can_apply_sgprs(instr
))
2080 apply_sgprs(ctx
, instr
);
2081 if (apply_omod_clamp(ctx
, block
, instr
))
2085 /* TODO: There are still some peephole optimizations that could be done:
2086 * - abs(a - b) -> s_absdiff_i32
2087 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2088 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2089 * These aren't probably too interesting though.
2090 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2091 * probably more useful than the previously mentioned optimizations.
2092 * The various comparison optimizations also currently only work with 32-bit
2095 /* neg(mul(a, b)) -> mul(neg(a), b) */
2096 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2097 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2099 if (!ctx
.info
[val
.id()].is_mul())
2102 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2104 if (mul_instr
->operands
[0].isLiteral())
2106 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2109 /* convert to mul(neg(a), b) */
2110 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2111 Definition def
= instr
->definitions
[0];
2112 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2113 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2114 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2115 instr
->operands
[0] = mul_instr
->operands
[0];
2116 instr
->operands
[1] = mul_instr
->operands
[1];
2117 instr
->definitions
[0] = def
;
2118 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2119 if (mul_instr
->isVOP3()) {
2120 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2121 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2122 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2123 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2124 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2125 new_mul
->omod
= mul
->omod
;
2127 new_mul
->neg
[0] ^= true;
2128 new_mul
->clamp
= false;
2130 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2133 /* combine mul+add -> mad */
2134 else if ((instr
->opcode
== aco_opcode::v_add_f32
||
2135 instr
->opcode
== aco_opcode::v_sub_f32
||
2136 instr
->opcode
== aco_opcode::v_subrev_f32
) &&
2137 block
.fp_mode
.denorm32
== 0 && !block
.fp_mode
.preserve_signed_zero_inf_nan32
) {
2138 //TODO: we could use fma instead when denormals are enabled if the NIR isn't marked as precise
2140 uint32_t uses_src0
= UINT32_MAX
;
2141 uint32_t uses_src1
= UINT32_MAX
;
2142 Instruction
* mul_instr
= nullptr;
2143 unsigned add_op_idx
;
2144 /* check if any of the operands is a multiplication */
2145 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2146 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2147 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2148 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2150 /* find the 'best' mul instruction to combine with the add */
2151 if (uses_src0
< uses_src1
) {
2152 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2154 } else if (uses_src1
< uses_src0
) {
2155 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2157 } else if (uses_src0
!= UINT32_MAX
) {
2158 /* tiebreaker: quite random what to pick */
2159 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2160 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2163 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2168 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2169 bool neg
[3] = {false, false, false};
2170 bool abs
[3] = {false, false, false};
2173 bool need_vop3
= false;
2174 op
[0] = mul_instr
->operands
[0];
2175 op
[1] = mul_instr
->operands
[1];
2176 op
[2] = instr
->operands
[add_op_idx
];
2177 // TODO: would be better to check this before selecting a mul instr?
2178 if (!check_vop3_operands(ctx
, 3, op
))
2181 for (unsigned i
= 0; i
< 3; i
++) {
2182 if (!(i
== 0 || (op
[i
].isTemp() && op
[i
].getTemp().type() == RegType::vgpr
)))
2186 if (mul_instr
->isVOP3()) {
2187 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2188 neg
[0] = vop3
->neg
[0];
2189 neg
[1] = vop3
->neg
[1];
2190 abs
[0] = vop3
->abs
[0];
2191 abs
[1] = vop3
->abs
[1];
2193 /* we cannot use these modifiers between mul and add */
2194 if (vop3
->clamp
|| vop3
->omod
)
2198 /* convert to mad */
2199 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2200 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2202 ctx
.uses
[op
[0].tempId()]++;
2204 ctx
.uses
[op
[1].tempId()]++;
2207 if (instr
->isVOP3()) {
2208 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2209 neg
[2] = vop3
->neg
[add_op_idx
];
2210 abs
[2] = vop3
->abs
[add_op_idx
];
2212 clamp
= vop3
->clamp
;
2213 /* abs of the multiplication result */
2214 if (vop3
->abs
[1 - add_op_idx
]) {
2220 /* neg of the multiplication result */
2221 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2224 if (instr
->opcode
== aco_opcode::v_sub_f32
) {
2225 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2227 } else if (instr
->opcode
== aco_opcode::v_subrev_f32
) {
2228 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2232 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2233 for (unsigned i
= 0; i
< 3; i
++)
2235 mad
->operands
[i
] = op
[i
];
2236 mad
->neg
[i
] = neg
[i
];
2237 mad
->abs
[i
] = abs
[i
];
2241 mad
->definitions
[0] = instr
->definitions
[0];
2243 /* mark this ssa_def to be re-checked for profitability and literals */
2244 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId(), need_vop3
);
2245 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2246 instr
.reset(mad
.release());
2250 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2251 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2252 for (unsigned i
= 0; i
< 2; i
++) {
2253 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2254 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2255 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2256 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2257 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2259 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2260 new_instr
->operands
[0] = Operand(0u);
2261 new_instr
->operands
[1] = instr
->operands
[!i
];
2262 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2263 new_instr
->definitions
[0] = instr
->definitions
[0];
2264 instr
.reset(new_instr
.release());
2265 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2269 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2270 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2271 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2272 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2273 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2274 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2275 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2276 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2277 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2278 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2279 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2280 combine_salu_lshl_add(ctx
, instr
);
2281 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2282 combine_salu_not_bitwise(ctx
, instr
);
2283 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2284 if (combine_inverse_comparison(ctx
, instr
)) ;
2285 else combine_salu_not_bitwise(ctx
, instr
);
2286 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2287 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2288 if (combine_ordering_test(ctx
, instr
)) ;
2289 else if (combine_comparison_ordering(ctx
, instr
)) ;
2290 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2291 else combine_salu_n2(ctx
, instr
);
2293 aco_opcode min
, max
, min3
, max3
, med3
;
2294 bool some_gfx9_only
;
2295 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2296 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2297 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, instr
->opcode
== min
? min3
: max3
, "012", 1 | 2));
2298 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2304 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2306 const uint32_t threshold
= 4;
2308 if (is_dead(ctx
.uses
, instr
.get())) {
2313 /* convert split_vector into extract_vector if only one definition is ever used */
2314 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2315 unsigned num_used
= 0;
2317 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2318 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2323 if (num_used
== 1) {
2324 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2325 extract
->operands
[0] = instr
->operands
[0];
2326 extract
->operands
[1] = Operand((uint32_t) idx
);
2327 extract
->definitions
[0] = instr
->definitions
[idx
];
2328 instr
.reset(extract
.release());
2332 /* re-check mad instructions */
2333 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2334 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2335 /* first, check profitability */
2336 if (ctx
.uses
[info
->mul_temp_id
]) {
2337 ctx
.uses
[info
->mul_temp_id
]++;
2338 if (instr
->operands
[0].isTemp())
2339 ctx
.uses
[instr
->operands
[0].tempId()]--;
2340 if (instr
->operands
[1].isTemp())
2341 ctx
.uses
[instr
->operands
[1].tempId()]--;
2342 instr
.swap(info
->add_instr
);
2344 /* second, check possible literals */
2345 } else if (!info
->needs_vop3
) {
2346 uint32_t literal_idx
= 0;
2347 uint32_t literal_uses
= UINT32_MAX
;
2348 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2350 if (!instr
->operands
[i
].isTemp())
2352 /* if one of the operands is sgpr, we cannot add a literal somewhere else */
2353 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2354 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2355 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2358 literal_uses
= UINT32_MAX
;
2362 else if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2363 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2364 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2368 if (literal_uses
< threshold
) {
2369 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2370 info
->check_literal
= true;
2371 info
->literal_idx
= literal_idx
;
2377 /* check for literals */
2378 if (!instr
->isSALU() && !instr
->isVALU())
2381 if (instr
->isSDWA() || instr
->isDPP() || instr
->isVOP3())
2382 return; /* some encodings can't ever take literals */
2384 /* we do not apply the literals yet as we don't know if it is profitable */
2385 Operand
current_literal(s1
);
2387 unsigned literal_id
= 0;
2388 unsigned literal_uses
= UINT32_MAX
;
2389 Operand
literal(s1
);
2390 unsigned num_operands
= instr
->isSALU() ? instr
->operands
.size() : 1;
2392 unsigned sgpr_ids
[2] = {0, 0};
2393 bool is_literal_sgpr
= false;
2396 /* choose a literal to apply */
2397 for (unsigned i
= 0; i
< num_operands
; i
++) {
2398 Operand op
= instr
->operands
[i
];
2399 if (op
.isLiteral()) {
2400 current_literal
= op
;
2402 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal()) {
2403 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
2404 op
.tempId() != sgpr_ids
[0])
2405 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
2409 if (!can_accept_constant(instr
, i
))
2412 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
2413 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
2415 literal
= Operand(ctx
.info
[op
.tempId()].val
);
2416 literal_uses
= ctx
.uses
[op
.tempId()];
2417 literal_id
= op
.tempId();
2420 mask
|= (op
.tempId() == literal_id
) << i
;
2424 /* don't go over the constant bus limit */
2425 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
2426 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2427 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
2430 if (literal_id
&& literal_uses
< threshold
&&
2431 (current_literal
.isUndefined() ||
2432 (current_literal
.size() == literal
.size() &&
2433 current_literal
.constantValue() == literal
.constantValue()))) {
2434 /* mark the literal to be applied */
2436 unsigned i
= u_bit_scan(&mask
);
2437 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
2438 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2444 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2446 /* Cleanup Dead Instructions */
2450 /* apply literals on MAD */
2451 bool literals_applied
= false;
2452 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2453 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2454 if (!info
->needs_vop3
) {
2455 aco_ptr
<Instruction
> new_mad
;
2456 if (info
->check_literal
&& ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0) {
2457 if (info
->literal_idx
== 2) { /* add literal -> madak */
2458 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2459 new_mad
->operands
[0] = instr
->operands
[0];
2460 new_mad
->operands
[1] = instr
->operands
[1];
2461 } else { /* mul literal -> madmk */
2462 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2463 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2464 new_mad
->operands
[1] = instr
->operands
[2];
2466 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2467 new_mad
->definitions
[0] = instr
->definitions
[0];
2468 instr
.swap(new_mad
);
2470 literals_applied
= true;
2474 /* apply literals on SALU/VALU */
2475 if (!literals_applied
&& (instr
->isSALU() || instr
->isVALU())) {
2476 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2477 Operand op
= instr
->operands
[i
];
2478 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal() && ctx
.uses
[op
.tempId()] == 0) {
2479 Operand
literal(ctx
.info
[op
.tempId()].val
);
2480 if (instr
->isVALU() && i
> 0)
2481 to_VOP3(ctx
, instr
);
2482 instr
->operands
[i
] = literal
;
2487 ctx
.instructions
.emplace_back(std::move(instr
));
2491 void optimize(Program
* program
)
2494 ctx
.program
= program
;
2495 std::vector
<ssa_info
> info(program
->peekAllocationId());
2496 ctx
.info
= info
.data();
2498 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2499 for (Block
& block
: program
->blocks
) {
2500 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2501 label_instruction(ctx
, block
, instr
);
2504 ctx
.uses
= std::move(dead_code_analysis(program
));
2506 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2507 for (Block
& block
: program
->blocks
) {
2508 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2509 combine_instruction(ctx
, block
, instr
);
2512 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2513 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2514 Block
* block
= &(*it
);
2515 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2516 select_instruction(ctx
, *it
);
2519 /* 4. Add literals to instructions */
2520 for (Block
& block
: program
->blocks
) {
2521 ctx
.instructions
.clear();
2522 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2523 apply_literals(ctx
, instr
);
2524 block
.instructions
.swap(ctx
.instructions
);