2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
59 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
, bool vop3
)
60 : add_instr(std::move(instr
)), mul_temp_id(id
), needs_vop3(vop3
), check_literal(false) {}
65 label_constant
= 1 << 1,
70 label_literal
= 1 << 6,
74 label_omod5
= 1 << 10,
75 label_omod_success
= 1 << 11,
76 label_clamp
= 1 << 12,
77 label_clamp_success
= 1 << 13,
78 label_undefined
= 1 << 14,
81 label_add_sub
= 1 << 17,
82 label_bitwise
= 1 << 18,
83 label_minmax
= 1 << 19,
85 label_uniform_bool
= 1 << 21,
88 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
| label_add_sub
| label_bitwise
| label_minmax
| label_fcmp
;
89 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
| label_omod2
| label_omod4
| label_omod5
| label_clamp
;
90 static constexpr uint32_t val_labels
= label_constant
| label_literal
| label_mad
;
100 void add_label(Label new_label
)
102 /* Since all labels which use "instr" use it for the same thing
103 * (indicating the defining instruction), there is no need to clear
104 * any other instr labels. */
105 if (new_label
& instr_labels
)
106 label
&= ~temp_labels
; /* instr and temp alias */
108 if (new_label
& temp_labels
) {
109 label
&= ~temp_labels
;
110 label
&= ~instr_labels
; /* instr and temp alias */
113 if (new_label
& val_labels
)
114 label
&= ~val_labels
;
119 void set_vec(Instruction
* vec
)
121 add_label(label_vec
);
127 return label
& label_vec
;
130 void set_constant(uint32_t constant
)
132 add_label(label_constant
);
138 return label
& label_constant
;
141 void set_abs(Temp abs_temp
)
143 add_label(label_abs
);
149 return label
& label_abs
;
152 void set_neg(Temp neg_temp
)
154 add_label(label_neg
);
160 return label
& label_neg
;
163 void set_neg_abs(Temp neg_abs_temp
)
165 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
169 void set_mul(Instruction
* mul
)
171 add_label(label_mul
);
177 return label
& label_mul
;
180 void set_temp(Temp tmp
)
182 add_label(label_temp
);
188 return label
& label_temp
;
191 void set_literal(uint32_t lit
)
193 add_label(label_literal
);
199 return label
& label_literal
;
202 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
204 add_label(label_mad
);
211 return label
& label_mad
;
214 void set_omod2(Temp def
)
216 add_label(label_omod2
);
222 return label
& label_omod2
;
225 void set_omod4(Temp def
)
227 add_label(label_omod4
);
233 return label
& label_omod4
;
236 void set_omod5(Temp def
)
238 add_label(label_omod5
);
244 return label
& label_omod5
;
247 void set_omod_success(Instruction
* omod_instr
)
249 add_label(label_omod_success
);
253 bool is_omod_success()
255 return label
& label_omod_success
;
258 void set_clamp(Temp def
)
260 add_label(label_clamp
);
266 return label
& label_clamp
;
269 void set_clamp_success(Instruction
* clamp_instr
)
271 add_label(label_clamp_success
);
275 bool is_clamp_success()
277 return label
& label_clamp_success
;
282 add_label(label_undefined
);
287 return label
& label_undefined
;
290 void set_vcc(Temp vcc
)
292 add_label(label_vcc
);
298 return label
& label_vcc
;
301 bool is_constant_or_literal()
303 return is_constant() || is_literal();
306 void set_b2f(Temp val
)
308 add_label(label_b2f
);
314 return label
& label_b2f
;
317 void set_add_sub(Instruction
*add_sub_instr
)
319 add_label(label_add_sub
);
320 instr
= add_sub_instr
;
325 return label
& label_add_sub
;
328 void set_bitwise(Instruction
*bitwise_instr
)
330 add_label(label_bitwise
);
331 instr
= bitwise_instr
;
336 return label
& label_bitwise
;
339 void set_minmax(Instruction
*minmax_instr
)
341 add_label(label_minmax
);
342 instr
= minmax_instr
;
347 return label
& label_minmax
;
350 void set_fcmp(Instruction
*fcmp_instr
)
352 add_label(label_fcmp
);
358 return label
& label_fcmp
;
361 void set_uniform_bool(Temp uniform_bool
)
363 add_label(label_uniform_bool
);
367 bool is_uniform_bool()
369 return label
& label_uniform_bool
;
376 std::vector
<aco_ptr
<Instruction
>> instructions
;
378 std::pair
<uint32_t,Temp
> last_literal
;
379 std::vector
<mad_info
> mad_infos
;
380 std::vector
<uint16_t> uses
;
383 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
385 if (instr
->operands
[0].isConstant() ||
386 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
389 switch (instr
->opcode
) {
390 case aco_opcode::v_add_f32
:
391 case aco_opcode::v_mul_f32
:
392 case aco_opcode::v_or_b32
:
393 case aco_opcode::v_and_b32
:
394 case aco_opcode::v_xor_b32
:
395 case aco_opcode::v_max_f32
:
396 case aco_opcode::v_min_f32
:
397 case aco_opcode::v_cmp_eq_f32
:
398 case aco_opcode::v_cmp_lg_f32
:
400 case aco_opcode::v_sub_f32
:
401 instr
->opcode
= aco_opcode::v_subrev_f32
;
403 case aco_opcode::v_cmp_lt_f32
:
404 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
406 case aco_opcode::v_cmp_ge_f32
:
407 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
409 case aco_opcode::v_cmp_lt_i32
:
410 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
417 bool can_use_VOP3(aco_ptr
<Instruction
>& instr
)
419 if (instr
->operands
.size() && instr
->operands
[0].isLiteral())
422 if (instr
->isDPP() || instr
->isSDWA())
425 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
426 instr
->opcode
!= aco_opcode::v_madak_f32
&&
427 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
428 instr
->opcode
!= aco_opcode::v_madak_f16
&&
429 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
430 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
431 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
434 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
436 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
437 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
438 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
439 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
440 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
443 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
448 assert(!instr
->operands
[0].isLiteral());
449 aco_ptr
<Instruction
> tmp
= std::move(instr
);
450 Format format
= asVOP3(tmp
->format
);
451 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
452 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
453 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
454 instr
->definitions
[i
] = tmp
->definitions
[i
];
455 if (instr
->definitions
[i
].isTemp()) {
456 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
457 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
458 info
.instr
= instr
.get();
463 /* only covers special cases */
464 bool can_accept_constant(aco_ptr
<Instruction
>& instr
, unsigned operand
)
466 switch (instr
->opcode
) {
467 case aco_opcode::v_interp_p2_f32
:
468 case aco_opcode::v_mac_f32
:
469 case aco_opcode::v_writelane_b32
:
470 case aco_opcode::v_writelane_b32_e64
:
471 case aco_opcode::v_cndmask_b32
:
473 case aco_opcode::s_addk_i32
:
474 case aco_opcode::s_mulk_i32
:
475 case aco_opcode::p_wqm
:
476 case aco_opcode::p_extract_vector
:
477 case aco_opcode::p_split_vector
:
478 case aco_opcode::v_readlane_b32
:
479 case aco_opcode::v_readlane_b32_e64
:
480 case aco_opcode::v_readfirstlane_b32
:
483 if ((instr
->format
== Format::MUBUF
||
484 instr
->format
== Format::MIMG
) &&
485 instr
->definitions
.size() == 1 &&
486 instr
->operands
.size() == 4) {
493 bool valu_can_accept_literal(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, unsigned operand
)
495 /* instructions like v_cndmask_b32 can't take a literal because they always
497 if (instr
->operands
.size() >= 3 &&
498 instr
->operands
[2].isTemp() && instr
->operands
[2].regClass().type() == RegType::sgpr
)
501 // TODO: VOP3 can take a literal on GFX10
502 return !instr
->isSDWA() && !instr
->isDPP() && !instr
->isVOP3() &&
503 operand
== 0 && can_accept_constant(instr
, operand
);
506 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
508 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
509 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
514 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
516 Operand op
= instr
->operands
[op_index
];
520 Temp tmp
= op
.getTemp();
521 if (!ctx
.info
[tmp
.id()].is_add_sub())
524 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
526 switch (add_instr
->opcode
) {
527 case aco_opcode::v_add_u32
:
528 case aco_opcode::v_add_co_u32
:
529 case aco_opcode::s_add_i32
:
530 case aco_opcode::s_add_u32
:
536 if (add_instr
->usesModifiers())
539 for (unsigned i
= 0; i
< 2; i
++) {
540 if (add_instr
->operands
[i
].isConstant()) {
541 *offset
= add_instr
->operands
[i
].constantValue();
542 } else if (add_instr
->operands
[i
].isTemp() &&
543 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
544 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
548 if (!add_instr
->operands
[!i
].isTemp())
551 uint32_t offset2
= 0;
552 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
555 *base
= add_instr
->operands
[!i
].getTemp();
563 Operand
get_constant_op(opt_ctx
&ctx
, uint32_t val
)
565 // TODO: this functions shouldn't be needed if we store Operand instead of value.
567 if (val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
568 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
572 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
574 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
575 ASSERTED
bool all_const
= false;
576 for (Operand
& op
: instr
->operands
)
577 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
578 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
581 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
583 if (!instr
->operands
[i
].isTemp())
586 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
587 /* propagate undef */
588 if (info
.is_undefined() && is_phi(instr
))
589 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
590 /* propagate reg->reg of same type */
591 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
592 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
593 info
= ctx
.info
[info
.temp
.id()];
596 /* SALU / PSEUDO: propagate inline constants */
597 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
598 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
599 instr
->operands
[i
].setTemp(info
.temp
);
600 info
= ctx
.info
[info
.temp
.id()];
601 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
602 /* propagate vgpr if it can take it */
603 switch (instr
->opcode
) {
604 case aco_opcode::p_create_vector
:
605 case aco_opcode::p_split_vector
:
606 case aco_opcode::p_extract_vector
:
607 case aco_opcode::p_phi
: {
608 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
609 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
611 instr
->operands
[i
] = Operand(info
.temp
);
612 info
= ctx
.info
[info
.temp
.id()];
620 if ((info
.is_constant() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) && !instr
->operands
[i
].isFixed() && can_accept_constant(instr
, i
)) {
621 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
626 /* VALU: propagate neg, abs & inline constants */
627 else if (instr
->isVALU()) {
628 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
629 instr
->operands
[i
].setTemp(info
.temp
);
630 info
= ctx
.info
[info
.temp
.id()];
632 if (info
.is_abs() && (can_use_VOP3(instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
635 instr
->operands
[i
] = Operand(info
.temp
);
637 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
639 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
641 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
642 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
643 instr
->operands
[i
].setTemp(info
.temp
);
645 } else if (info
.is_neg() && (can_use_VOP3(instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
648 instr
->operands
[i
].setTemp(info
.temp
);
650 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
652 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
655 if (info
.is_constant() && can_accept_constant(instr
, i
)) {
656 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
657 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
658 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
660 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
661 instr
->operands
[i
] = instr
->operands
[0];
662 instr
->operands
[0] = get_constant_op(ctx
, info
.val
);
664 } else if (can_use_VOP3(instr
)) {
666 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
672 /* MUBUF: propagate constants and combine additions */
673 else if (instr
->format
== Format::MUBUF
) {
674 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
677 while (info
.is_temp())
678 info
= ctx
.info
[info
.temp
.id()];
680 if (mubuf
->offen
&& i
== 0 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
681 assert(!mubuf
->idxen
);
682 instr
->operands
[i
] = Operand(v1
);
683 mubuf
->offset
+= info
.val
;
684 mubuf
->offen
= false;
686 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
687 instr
->operands
[2] = Operand((uint32_t) 0);
688 mubuf
->offset
+= info
.val
;
690 } else if (mubuf
->offen
&& i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
691 assert(!mubuf
->idxen
);
692 instr
->operands
[i
].setTemp(base
);
693 mubuf
->offset
+= offset
;
695 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
696 instr
->operands
[i
].setTemp(base
);
697 mubuf
->offset
+= offset
;
702 /* DS: combine additions */
703 else if (instr
->format
== Format::DS
) {
705 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
708 if (i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == instr
->operands
[i
].regClass() && instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
709 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
710 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
711 if (offset
% 4 == 0 &&
712 ds
->offset0
+ (offset
>> 2) <= 255 &&
713 ds
->offset1
+ (offset
>> 2) <= 255) {
714 instr
->operands
[i
].setTemp(base
);
715 ds
->offset0
+= offset
>> 2;
716 ds
->offset1
+= offset
>> 2;
719 if (ds
->offset0
+ offset
<= 65535) {
720 instr
->operands
[i
].setTemp(base
);
721 ds
->offset0
+= offset
;
727 /* SMEM: propagate constants and combine additions */
728 else if (instr
->format
== Format::SMEM
) {
730 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
733 if (i
== 1 && info
.is_constant_or_literal() &&
734 (ctx
.program
->chip_class
< GFX8
|| info
.val
<= 0xFFFFF)) {
735 instr
->operands
[i
] = Operand(info
.val
);
737 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
738 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
740 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
741 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
745 smem
->operands
[1] = Operand(offset
);
746 smem
->operands
.back() = Operand(base
);
748 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
749 new_instr
->operands
[0] = smem
->operands
[0];
750 new_instr
->operands
[1] = Operand(offset
);
751 if (smem
->definitions
.empty())
752 new_instr
->operands
[2] = smem
->operands
[2];
753 new_instr
->operands
.back() = Operand(base
);
754 if (!smem
->definitions
.empty())
755 new_instr
->definitions
[0] = smem
->definitions
[0];
756 new_instr
->can_reorder
= smem
->can_reorder
;
757 new_instr
->barrier
= smem
->barrier
;
758 instr
.reset(new_instr
);
759 smem
= static_cast<SMEM_instruction
*>(instr
.get());
766 /* if this instruction doesn't define anything, return */
767 if (instr
->definitions
.empty())
770 switch (instr
->opcode
) {
771 case aco_opcode::p_create_vector
: {
772 unsigned num_ops
= instr
->operands
.size();
773 for (const Operand
& op
: instr
->operands
) {
774 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
775 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
777 if (num_ops
!= instr
->operands
.size()) {
778 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
779 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
780 instr
->definitions
[0] = old_vec
->definitions
[0];
782 for (Operand
& old_op
: old_vec
->operands
) {
783 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
784 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
785 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
786 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
787 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
788 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
789 instr
->operands
[k
++] = op
;
792 instr
->operands
[k
++] = old_op
;
795 assert(k
== num_ops
);
797 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
798 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
799 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
800 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
803 case aco_opcode::p_split_vector
: {
804 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
806 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
807 assert(instr
->definitions
.size() == vec
->operands
.size());
808 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
809 Operand vec_op
= vec
->operands
[i
];
810 if (vec_op
.isConstant()) {
811 if (vec_op
.isLiteral())
812 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
813 else if (vec_op
.size() == 1)
814 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
816 assert(vec_op
.isTemp());
817 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
822 case aco_opcode::p_extract_vector
: { /* mov */
823 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
825 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
826 if (vec
->definitions
[0].getTemp().size() == vec
->operands
.size() && /* TODO: what about 64bit or other combinations? */
827 vec
->operands
[0].size() == instr
->definitions
[0].size()) {
829 /* convert this extract into a mov instruction */
830 Operand vec_op
= vec
->operands
[instr
->operands
[1].constantValue()];
831 bool is_vgpr
= instr
->definitions
[0].getTemp().type() == RegType::vgpr
;
832 aco_opcode opcode
= is_vgpr
? aco_opcode::v_mov_b32
: aco_opcode::s_mov_b32
;
833 Format format
= is_vgpr
? Format::VOP1
: Format::SOP1
;
834 instr
->opcode
= opcode
;
835 instr
->format
= format
;
836 while (instr
->operands
.size() > 1)
837 instr
->operands
.pop_back();
838 instr
->operands
[0] = vec_op
;
840 if (vec_op
.isConstant()) {
841 if (vec_op
.isLiteral())
842 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(vec_op
.constantValue());
843 else if (vec_op
.size() == 1)
844 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(vec_op
.constantValue());
846 assert(vec_op
.isTemp());
847 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vec_op
.getTemp());
852 case aco_opcode::s_mov_b32
: /* propagate */
853 case aco_opcode::s_mov_b64
:
854 case aco_opcode::v_mov_b32
:
855 case aco_opcode::p_as_uniform
:
856 if (instr
->definitions
[0].isFixed()) {
857 /* don't copy-propagate copies into fixed registers */
858 } else if (instr
->usesModifiers()) {
860 } else if (instr
->operands
[0].isConstant()) {
861 if (instr
->operands
[0].isLiteral())
862 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
863 else if (instr
->operands
[0].size() == 1)
864 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
865 } else if (instr
->operands
[0].isTemp()) {
866 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
868 assert(instr
->operands
[0].isFixed());
871 case aco_opcode::p_is_helper
:
872 if (!ctx
.program
->needs_wqm
)
873 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
875 case aco_opcode::s_movk_i32
: {
876 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
877 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
878 if (v
<= 64 || v
>= 0xfffffff0)
879 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
881 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
884 case aco_opcode::v_bfrev_b32
:
885 case aco_opcode::s_brev_b32
: {
886 if (instr
->operands
[0].isConstant()) {
887 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
888 if (v
<= 64 || v
>= 0xfffffff0)
889 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
891 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
895 case aco_opcode::s_bfm_b32
: {
896 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
897 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
898 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
899 uint32_t v
= ((1u << size
) - 1u) << start
;
900 if (v
<= 64 || v
>= 0xfffffff0)
901 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
903 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
906 case aco_opcode::v_mul_f32
: { /* omod */
907 /* TODO: try to move the negate/abs modifier to the consumer instead */
908 if (instr
->usesModifiers())
911 for (unsigned i
= 0; i
< 2; i
++) {
912 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
913 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
914 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
915 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
916 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
917 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
918 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
919 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000 &&
920 !block
.fp_mode
.must_flush_denorms32
) { /* 1.0 */
921 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
930 case aco_opcode::v_and_b32
: /* abs */
931 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x7FFFFFFF) &&
932 instr
->operands
[1].isTemp() && instr
->operands
[1].getTemp().type() == RegType::vgpr
)
933 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
935 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
937 case aco_opcode::v_xor_b32
: { /* neg */
938 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
939 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
940 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
941 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
942 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
943 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
944 instr
->opcode
= aco_opcode::v_or_b32
;
945 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
947 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
951 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
955 case aco_opcode::v_med3_f32
: { /* clamp */
956 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
957 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
958 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
959 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
963 bool found_zero
= false, found_one
= false;
964 for (unsigned i
= 0; i
< 3; i
++)
966 if (instr
->operands
[i
].constantEquals(0))
968 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
973 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
974 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
978 case aco_opcode::v_cndmask_b32
:
979 if (instr
->operands
[0].constantEquals(0) &&
980 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
981 instr
->operands
[2].isTemp())
982 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
983 else if (instr
->operands
[0].constantEquals(0) &&
984 instr
->operands
[1].constantEquals(0x3f800000u
) &&
985 instr
->operands
[2].isTemp())
986 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
988 case aco_opcode::v_cmp_lg_u32
:
989 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
990 instr
->operands
[0].constantEquals(0) &&
991 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
992 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
994 case aco_opcode::p_phi
:
995 case aco_opcode::p_linear_phi
: {
996 /* lower_bool_phis() can create phis like this */
997 bool all_same_temp
= instr
->operands
[0].isTemp();
998 /* this check is needed when moving uniform loop counters out of a divergent loop */
1000 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1001 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1002 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1003 all_same_temp
= false;
1005 if (all_same_temp
) {
1006 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1008 bool all_undef
= instr
->operands
[0].isUndefined();
1009 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1010 if (!instr
->operands
[i
].isUndefined())
1014 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1018 case aco_opcode::v_add_u32
:
1019 case aco_opcode::v_add_co_u32
:
1020 case aco_opcode::s_add_i32
:
1021 case aco_opcode::s_add_u32
:
1022 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1024 case aco_opcode::s_and_b32
:
1025 case aco_opcode::s_and_b64
:
1026 if (instr
->operands
[1].isFixed() && instr
->operands
[1].physReg() == exec
&&
1027 instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1028 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1031 case aco_opcode::s_not_b32
:
1032 case aco_opcode::s_not_b64
:
1033 case aco_opcode::s_or_b32
:
1034 case aco_opcode::s_or_b64
:
1035 case aco_opcode::s_xor_b32
:
1036 case aco_opcode::s_xor_b64
:
1037 case aco_opcode::s_lshl_b32
:
1038 case aco_opcode::v_or_b32
:
1039 case aco_opcode::v_lshlrev_b32
:
1040 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1042 case aco_opcode::v_min_f32
:
1043 case aco_opcode::v_min_f16
:
1044 case aco_opcode::v_min_u32
:
1045 case aco_opcode::v_min_i32
:
1046 case aco_opcode::v_min_u16
:
1047 case aco_opcode::v_min_i16
:
1048 case aco_opcode::v_max_f32
:
1049 case aco_opcode::v_max_f16
:
1050 case aco_opcode::v_max_u32
:
1051 case aco_opcode::v_max_i32
:
1052 case aco_opcode::v_max_u16
:
1053 case aco_opcode::v_max_i16
:
1054 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1056 case aco_opcode::v_cmp_lt_f32
:
1057 case aco_opcode::v_cmp_eq_f32
:
1058 case aco_opcode::v_cmp_le_f32
:
1059 case aco_opcode::v_cmp_gt_f32
:
1060 case aco_opcode::v_cmp_lg_f32
:
1061 case aco_opcode::v_cmp_ge_f32
:
1062 case aco_opcode::v_cmp_o_f32
:
1063 case aco_opcode::v_cmp_u_f32
:
1064 case aco_opcode::v_cmp_nge_f32
:
1065 case aco_opcode::v_cmp_nlg_f32
:
1066 case aco_opcode::v_cmp_ngt_f32
:
1067 case aco_opcode::v_cmp_nle_f32
:
1068 case aco_opcode::v_cmp_neq_f32
:
1069 case aco_opcode::v_cmp_nlt_f32
:
1070 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1072 case aco_opcode::s_cselect_b64
:
1073 case aco_opcode::s_cselect_b32
:
1074 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1075 instr
->operands
[1].constantEquals(0)) {
1076 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1077 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1085 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1087 *ordered
= *unordered
= op
;
1089 #define CMP(ord, unord) \
1090 case aco_opcode::v_cmp_##ord##_f32:\
1091 case aco_opcode::v_cmp_n##unord##_f32:\
1092 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1093 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1094 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1108 aco_opcode
get_ordered(aco_opcode op
)
1110 aco_opcode ordered
, unordered
, inverse
;
1111 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1114 aco_opcode
get_unordered(aco_opcode op
)
1116 aco_opcode ordered
, unordered
, inverse
;
1117 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1120 aco_opcode
get_inverse(aco_opcode op
)
1122 aco_opcode ordered
, unordered
, inverse
;
1123 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1126 bool is_cmp(aco_opcode op
)
1128 aco_opcode ordered
, unordered
, inverse
;
1129 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1132 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1134 if (ctx
.info
[tmp
.id()].is_temp())
1135 return ctx
.info
[tmp
.id()].temp
.id();
1140 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1142 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1143 for (const Operand
& op
: instr
->operands
) {
1145 ctx
.uses
[op
.tempId()]--;
1150 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1152 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1154 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1157 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1159 if (instr
->definitions
.size() == 2) {
1160 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1161 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1168 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1169 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1170 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1172 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1174 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1177 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1179 bool neg
[2] = {false, false};
1180 bool abs
[2] = {false, false};
1182 Instruction
*op_instr
[2];
1185 for (unsigned i
= 0; i
< 2; i
++) {
1186 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1190 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1192 if (op_instr
[i
]->opcode
!= expected_cmp
)
1194 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1197 if (op_instr
[i
]->isVOP3()) {
1198 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1199 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1201 neg
[i
] = vop3
->neg
[0];
1202 abs
[i
] = vop3
->abs
[0];
1203 opsel
|= (vop3
->opsel
& 1) << i
;
1206 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1207 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1208 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1210 /* shouldn't happen yet, but best to be safe */
1211 if (op1
.type() != RegType::vgpr
)
1217 ctx
.uses
[op
[0].id()]++;
1218 ctx
.uses
[op
[1].id()]++;
1219 decrease_uses(ctx
, op_instr
[0]);
1220 decrease_uses(ctx
, op_instr
[1]);
1222 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1223 Instruction
*new_instr
;
1224 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
) {
1225 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1226 for (unsigned i
= 0; i
< 2; i
++) {
1227 vop3
->neg
[i
] = neg
[i
];
1228 vop3
->abs
[i
] = abs
[i
];
1230 vop3
->opsel
= opsel
;
1231 new_instr
= static_cast<Instruction
*>(vop3
);
1233 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1235 new_instr
->operands
[0] = Operand(op
[0]);
1236 new_instr
->operands
[1] = Operand(op
[1]);
1237 new_instr
->definitions
[0] = instr
->definitions
[0];
1239 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1240 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1242 instr
.reset(new_instr
);
1247 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1248 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1249 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1251 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1253 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1256 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1257 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1259 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1260 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1261 if (!nan_test
|| !cmp
)
1264 if (cmp
->opcode
== expected_nan_test
)
1265 std::swap(nan_test
, cmp
);
1266 else if (nan_test
->opcode
!= expected_nan_test
)
1269 if (!is_cmp(cmp
->opcode
))
1272 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1274 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1277 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1278 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1279 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1280 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1281 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1283 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1286 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1287 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1288 decrease_uses(ctx
, nan_test
);
1289 decrease_uses(ctx
, cmp
);
1291 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1292 Instruction
*new_instr
;
1293 if (cmp
->isVOP3()) {
1294 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1295 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1296 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1297 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1298 new_vop3
->clamp
= cmp_vop3
->clamp
;
1299 new_vop3
->omod
= cmp_vop3
->omod
;
1300 new_vop3
->opsel
= cmp_vop3
->opsel
;
1301 new_instr
= new_vop3
;
1303 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1305 new_instr
->operands
[0] = cmp
->operands
[0];
1306 new_instr
->operands
[1] = cmp
->operands
[1];
1307 new_instr
->definitions
[0] = instr
->definitions
[0];
1309 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1310 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1312 instr
.reset(new_instr
);
1317 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1318 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1319 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1321 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1323 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1326 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1328 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1329 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1331 if (!nan_test
|| !cmp
)
1334 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1335 if (cmp
->opcode
== expected_nan_test
)
1336 std::swap(nan_test
, cmp
);
1337 else if (nan_test
->opcode
!= expected_nan_test
)
1340 if (!is_cmp(cmp
->opcode
))
1343 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1345 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1348 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1349 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1350 if (prop_nan0
!= prop_nan1
)
1353 if (nan_test
->isVOP3()) {
1354 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1355 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1359 int constant_operand
= -1;
1360 for (unsigned i
= 0; i
< 2; i
++) {
1361 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1362 constant_operand
= !i
;
1366 if (constant_operand
== -1)
1370 if (cmp
->operands
[constant_operand
].isConstant()) {
1371 constant
= cmp
->operands
[constant_operand
].constantValue();
1372 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1373 unsigned id
= cmp
->operands
[constant_operand
].tempId();
1374 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1376 constant
= ctx
.info
[id
].val
;
1382 memcpy(&constantf
, &constant
, 4);
1383 if (isnan(constantf
))
1386 if (cmp
->operands
[0].isTemp())
1387 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1388 if (cmp
->operands
[1].isTemp())
1389 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1390 decrease_uses(ctx
, nan_test
);
1391 decrease_uses(ctx
, cmp
);
1393 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1394 Instruction
*new_instr
;
1395 if (cmp
->isVOP3()) {
1396 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1397 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1398 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1399 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1400 new_vop3
->clamp
= cmp_vop3
->clamp
;
1401 new_vop3
->omod
= cmp_vop3
->omod
;
1402 new_vop3
->opsel
= cmp_vop3
->opsel
;
1403 new_instr
= new_vop3
;
1405 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1407 new_instr
->operands
[0] = cmp
->operands
[0];
1408 new_instr
->operands
[1] = cmp
->operands
[1];
1409 new_instr
->definitions
[0] = instr
->definitions
[0];
1411 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1412 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1414 instr
.reset(new_instr
);
1419 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1420 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1422 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1424 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1426 if (!instr
->operands
[0].isTemp())
1429 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1433 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1434 if (new_opcode
== aco_opcode::last_opcode
)
1437 if (cmp
->operands
[0].isTemp())
1438 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1439 if (cmp
->operands
[1].isTemp())
1440 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1441 decrease_uses(ctx
, cmp
);
1443 Instruction
*new_instr
;
1444 if (cmp
->isVOP3()) {
1445 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1446 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1447 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1448 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1449 new_vop3
->clamp
= cmp_vop3
->clamp
;
1450 new_vop3
->omod
= cmp_vop3
->omod
;
1451 new_vop3
->opsel
= cmp_vop3
->opsel
;
1452 new_instr
= new_vop3
;
1454 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1456 new_instr
->operands
[0] = cmp
->operands
[0];
1457 new_instr
->operands
[1] = cmp
->operands
[1];
1458 new_instr
->definitions
[0] = instr
->definitions
[0];
1460 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1461 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1463 instr
.reset(new_instr
);
1468 /* op1(op2(1, 2), 0) if swap = false
1469 * op1(0, op2(1, 2)) if swap = true */
1470 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1471 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1472 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1473 bool *op1_clamp
, uint8_t *op1_omod
,
1474 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1477 if (op1_instr
->opcode
!= op1
)
1480 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1481 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1484 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1485 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1487 /* don't support inbetween clamp/omod */
1488 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1491 /* get operands and modifiers and check inbetween modifiers */
1492 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1493 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1496 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1497 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1501 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1502 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1505 if (inbetween_opsel
)
1506 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1507 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1511 shuffle
[shuffle_str
[0] - '0'] = 0;
1512 shuffle
[shuffle_str
[1] - '0'] = 1;
1513 shuffle
[shuffle_str
[2] - '0'] = 2;
1515 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1516 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1517 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1518 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1519 *opsel
|= 1 << shuffle
[0];
1521 for (unsigned i
= 0; i
< 2; i
++) {
1522 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1523 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1524 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1525 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1526 *opsel
|= 1 << shuffle
[i
+ 1];
1529 /* check operands */
1530 unsigned sgpr_id
= 0;
1531 for (unsigned i
= 0; i
< 3; i
++) {
1532 Operand op
= operands
[i
];
1533 if (op
.isLiteral()) {
1535 } else if (op
.isTemp() && op
.getTemp().type() == RegType::sgpr
) {
1536 if (sgpr_id
&& sgpr_id
!= op
.tempId())
1538 sgpr_id
= op
.tempId();
1545 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1546 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1547 bool clamp
, unsigned omod
)
1549 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1550 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1551 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1552 new_instr
->clamp
= clamp
;
1553 new_instr
->omod
= omod
;
1554 new_instr
->opsel
= opsel
;
1555 new_instr
->operands
[0] = operands
[0];
1556 new_instr
->operands
[1] = operands
[1];
1557 new_instr
->operands
[2] = operands
[2];
1558 new_instr
->definitions
[0] = instr
->definitions
[0];
1559 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1561 instr
.reset(new_instr
);
1564 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1566 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1567 (label_omod_success
| label_clamp_success
);
1569 for (unsigned swap
= 0; swap
< 2; swap
++) {
1570 if (!((1 << swap
) & ops
))
1573 Operand operands
[3];
1574 bool neg
[3], abs
[3], clamp
;
1575 uint8_t opsel
= 0, omod
= 0;
1576 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1577 instr
.get(), swap
, shuffle
,
1578 operands
, neg
, abs
, &opsel
,
1579 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1580 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1581 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1582 if (omod_clamp
& label_omod_success
)
1583 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1584 if (omod_clamp
& label_clamp_success
)
1585 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1592 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1593 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1594 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1595 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1596 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1597 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1598 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1601 if (!instr
->operands
[0].isTemp())
1603 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1606 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1609 switch (op2_instr
->opcode
) {
1610 case aco_opcode::s_and_b32
:
1611 case aco_opcode::s_or_b32
:
1612 case aco_opcode::s_xor_b32
:
1613 case aco_opcode::s_and_b64
:
1614 case aco_opcode::s_or_b64
:
1615 case aco_opcode::s_xor_b64
:
1621 /* create instruction */
1622 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1623 ctx
.uses
[instr
->operands
[0].tempId()]--;
1624 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1626 switch (op2_instr
->opcode
) {
1627 case aco_opcode::s_and_b32
:
1628 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1630 case aco_opcode::s_or_b32
:
1631 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1633 case aco_opcode::s_xor_b32
:
1634 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1636 case aco_opcode::s_and_b64
:
1637 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1639 case aco_opcode::s_or_b64
:
1640 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1642 case aco_opcode::s_xor_b64
:
1643 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1652 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1653 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1654 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1655 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1656 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1658 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1661 for (unsigned i
= 0; i
< 2; i
++) {
1662 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1663 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1666 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1667 instr
->operands
[0] = instr
->operands
[!i
];
1668 instr
->operands
[1] = op2_instr
->operands
[0];
1669 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1671 switch (instr
->opcode
) {
1672 case aco_opcode::s_and_b32
:
1673 instr
->opcode
= aco_opcode::s_andn2_b32
;
1675 case aco_opcode::s_or_b32
:
1676 instr
->opcode
= aco_opcode::s_orn2_b32
;
1678 case aco_opcode::s_and_b64
:
1679 instr
->opcode
= aco_opcode::s_andn2_b64
;
1681 case aco_opcode::s_or_b64
:
1682 instr
->opcode
= aco_opcode::s_orn2_b64
;
1693 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1694 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1696 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1699 for (unsigned i
= 0; i
< 2; i
++) {
1700 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1701 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
|| !op2_instr
->operands
[1].isConstant())
1704 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1705 if (shift
< 1 || shift
> 4)
1708 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1709 instr
->operands
[1] = instr
->operands
[!i
];
1710 instr
->operands
[0] = op2_instr
->operands
[0];
1711 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1713 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1714 aco_opcode::s_lshl2_add_u32
,
1715 aco_opcode::s_lshl3_add_u32
,
1716 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1723 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1726 #define MINMAX(type, gfx9) \
1727 case aco_opcode::v_min_##type:\
1728 case aco_opcode::v_max_##type:\
1729 case aco_opcode::v_med3_##type:\
1730 *min = aco_opcode::v_min_##type;\
1731 *max = aco_opcode::v_max_##type;\
1732 *med3 = aco_opcode::v_med3_##type;\
1733 *min3 = aco_opcode::v_min3_##type;\
1734 *max3 = aco_opcode::v_max3_##type;\
1735 *some_gfx9_only = gfx9;\
1749 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1750 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1751 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1752 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1754 aco_opcode other_op
;
1755 if (instr
->opcode
== min
)
1757 else if (instr
->opcode
== max
)
1762 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1763 (label_omod_success
| label_clamp_success
);
1765 for (unsigned swap
= 0; swap
< 2; swap
++) {
1766 Operand operands
[3];
1767 bool neg
[3], abs
[3], clamp
, inbetween_neg
, inbetween_abs
;
1768 uint8_t opsel
= 0, omod
= 0;
1769 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1770 "012", operands
, neg
, abs
, &opsel
,
1771 &clamp
, &omod
, &inbetween_neg
, &inbetween_abs
, NULL
)) {
1772 int const0_idx
= -1, const1_idx
= -1;
1773 uint32_t const0
= 0, const1
= 0;
1774 for (int i
= 0; i
< 3; i
++) {
1776 if (operands
[i
].isConstant()) {
1777 val
= operands
[i
].constantValue();
1778 } else if (operands
[i
].isTemp() && ctx
.uses
[operands
[i
].tempId()] == 1 &&
1779 ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
1780 val
= ctx
.info
[operands
[i
].tempId()].val
;
1784 if (const0_idx
>= 0) {
1792 if (const0_idx
< 0 || const1_idx
< 0)
1795 if (opsel
& (1 << const0_idx
))
1797 if (opsel
& (1 << const1_idx
))
1800 int lower_idx
= const0_idx
;
1802 case aco_opcode::v_min_f32
:
1803 case aco_opcode::v_min_f16
: {
1804 float const0_f
, const1_f
;
1805 if (min
== aco_opcode::v_min_f32
) {
1806 memcpy(&const0_f
, &const0
, 4);
1807 memcpy(&const1_f
, &const1
, 4);
1809 const0_f
= _mesa_half_to_float(const0
);
1810 const1_f
= _mesa_half_to_float(const1
);
1812 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
1813 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
1814 if (neg
[const0_idx
]) const0_f
= -const0_f
;
1815 if (neg
[const1_idx
]) const1_f
= -const1_f
;
1816 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
1819 case aco_opcode::v_min_u32
: {
1820 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
1823 case aco_opcode::v_min_u16
: {
1824 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
1827 case aco_opcode::v_min_i32
: {
1828 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
1829 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
1830 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1833 case aco_opcode::v_min_i16
: {
1834 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
1835 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
1836 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1842 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
1844 if (instr
->opcode
== min
) {
1845 if (upper_idx
!= 0 || lower_idx
== 0)
1848 if (upper_idx
== 0 || lower_idx
!= 0)
1852 neg
[1] ^= inbetween_neg
;
1853 neg
[2] ^= inbetween_neg
;
1854 abs
[1] |= inbetween_abs
;
1855 abs
[2] |= inbetween_abs
;
1857 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1858 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1859 if (omod_clamp
& label_omod_success
)
1860 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1861 if (omod_clamp
& label_clamp_success
)
1862 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1872 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1875 uint32_t sgpr_idx
= 0;
1876 uint32_t sgpr_info_id
= 0;
1877 bool has_sgpr
= false;
1878 uint32_t sgpr_ssa_id
= 0;
1879 /* find 'best' possible sgpr */
1880 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
1882 if (instr
->operands
[i
].isLiteral()) {
1886 if (!instr
->operands
[i
].isTemp())
1888 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
1890 sgpr_ssa_id
= instr
->operands
[i
].tempId();
1893 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
1894 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
1895 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
1896 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
1898 sgpr_info_id
= instr
->operands
[i
].tempId();
1902 if (!has_sgpr
&& sgpr_info_id
!= 0) {
1903 ssa_info
& info
= ctx
.info
[sgpr_info_id
];
1904 if (sgpr_idx
== 0 || instr
->isVOP3()) {
1905 instr
->operands
[sgpr_idx
] = Operand(info
.temp
);
1906 ctx
.uses
[sgpr_info_id
]--;
1907 ctx
.uses
[info
.temp
.id()]++;
1908 } else if (can_swap_operands(instr
)) {
1909 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
1910 instr
->operands
[0] = Operand(info
.temp
);
1911 ctx
.uses
[sgpr_info_id
]--;
1912 ctx
.uses
[info
.temp
.id()]++;
1913 } else if (can_use_VOP3(instr
)) {
1914 to_VOP3(ctx
, instr
);
1915 instr
->operands
[sgpr_idx
] = Operand(info
.temp
);
1916 ctx
.uses
[sgpr_info_id
]--;
1917 ctx
.uses
[info
.temp
.id()]++;
1920 /* we can have two sgprs on one instruction if it is the same sgpr! */
1921 } else if (sgpr_info_id
!= 0 &&
1922 sgpr_ssa_id
== sgpr_info_id
&&
1923 ctx
.uses
[sgpr_info_id
] == 1 &&
1924 can_use_VOP3(instr
)) {
1925 to_VOP3(ctx
, instr
);
1926 instr
->operands
[sgpr_idx
] = Operand(ctx
.info
[sgpr_info_id
].temp
);
1927 ctx
.uses
[sgpr_info_id
]--;
1928 ctx
.uses
[ctx
.info
[sgpr_info_id
].temp
.id()]++;
1932 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
1934 /* check if we could apply omod on predecessor */
1935 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
1936 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
1937 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
1939 unsigned idx
= op0
? 0 : 1;
1940 /* omod was successfully applied */
1941 /* if the omod instruction is v_mad, we also have to change the original add */
1942 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
1943 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
1944 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
1945 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
1946 add_instr
->definitions
[0] = instr
->definitions
[0];
1949 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
1950 /* check if we have an additional clamp modifier */
1951 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
1952 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
1953 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
1954 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
1956 /* change definition ssa-id of modified instruction */
1957 omod_instr
->definitions
[0] = instr
->definitions
[0];
1959 /* change the definition of instr to something unused, e.g. the original omod def */
1960 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
1961 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
1964 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
1965 /* in all other cases, label this instruction as option for multiply-add */
1966 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
1970 /* check if we could apply clamp on predecessor */
1971 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
1973 bool found_zero
= false, found_one
= false;
1974 for (unsigned i
= 0; i
< 3; i
++)
1976 if (instr
->operands
[i
].constantEquals(0))
1978 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1983 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
1984 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
1985 /* clamp was successfully applied */
1986 /* if the clamp instruction is v_mad, we also have to change the original add */
1987 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
1988 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
1989 add_instr
->definitions
[0] = instr
->definitions
[0];
1991 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
1992 /* change definition ssa-id of modified instruction */
1993 clamp_instr
->definitions
[0] = instr
->definitions
[0];
1995 /* change the definition of instr to something unused, e.g. the original omod def */
1996 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
1997 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2002 /* omod has no effect if denormals are enabled */
2003 bool can_use_omod
= block
.fp_mode
.denorm32
== 0;
2005 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2006 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2007 can_use_VOP3(instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2008 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2009 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2010 to_VOP3(ctx
, instr
);
2011 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2012 def_info
.set_omod_success(instr
.get());
2013 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2014 to_VOP3(ctx
, instr
);
2015 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2016 def_info
.set_omod_success(instr
.get());
2017 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2018 to_VOP3(ctx
, instr
);
2019 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2020 def_info
.set_omod_success(instr
.get());
2021 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2022 to_VOP3(ctx
, instr
);
2023 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2024 def_info
.set_clamp_success(instr
.get());
2031 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2032 // this would mean that we'd have to fix the instruction uses while value propagation
2034 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2036 if (instr
->definitions
.empty() || !ctx
.uses
[instr
->definitions
[0].tempId()])
2039 if (instr
->isVALU()) {
2040 if (can_apply_sgprs(instr
))
2041 apply_sgprs(ctx
, instr
);
2042 if (apply_omod_clamp(ctx
, block
, instr
))
2046 /* TODO: There are still some peephole optimizations that could be done:
2047 * - abs(a - b) -> s_absdiff_i32
2048 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2049 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2050 * These aren't probably too interesting though.
2051 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2052 * probably more useful than the previously mentioned optimizations.
2053 * The various comparison optimizations also currently only work with 32-bit
2056 /* neg(mul(a, b)) -> mul(neg(a), b) */
2057 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2058 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2060 if (!ctx
.info
[val
.id()].is_mul())
2063 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2065 if (mul_instr
->operands
[0].isLiteral())
2067 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2070 /* convert to mul(neg(a), b) */
2071 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2072 Definition def
= instr
->definitions
[0];
2073 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2074 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2075 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2076 instr
->operands
[0] = mul_instr
->operands
[0];
2077 instr
->operands
[1] = mul_instr
->operands
[1];
2078 instr
->definitions
[0] = def
;
2079 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2080 if (mul_instr
->isVOP3()) {
2081 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2082 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2083 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2084 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2085 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2086 new_mul
->omod
= mul
->omod
;
2088 new_mul
->neg
[0] ^= true;
2089 new_mul
->clamp
= false;
2091 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2094 /* combine mul+add -> mad */
2095 else if ((instr
->opcode
== aco_opcode::v_add_f32
||
2096 instr
->opcode
== aco_opcode::v_sub_f32
||
2097 instr
->opcode
== aco_opcode::v_subrev_f32
) &&
2098 block
.fp_mode
.denorm32
== 0 && !block
.fp_mode
.preserve_signed_zero_inf_nan32
) {
2099 //TODO: we could use fma instead when denormals are enabled if the NIR isn't marked as precise
2101 uint32_t uses_src0
= UINT32_MAX
;
2102 uint32_t uses_src1
= UINT32_MAX
;
2103 Instruction
* mul_instr
= nullptr;
2104 unsigned add_op_idx
;
2105 /* check if any of the operands is a multiplication */
2106 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2107 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2108 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2109 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2111 /* find the 'best' mul instruction to combine with the add */
2112 if (uses_src0
< uses_src1
) {
2113 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2115 } else if (uses_src1
< uses_src0
) {
2116 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2118 } else if (uses_src0
!= UINT32_MAX
) {
2119 /* tiebreaker: quite random what to pick */
2120 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2121 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2124 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2129 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2130 bool neg
[3] = {false, false, false};
2131 bool abs
[3] = {false, false, false};
2134 bool need_vop3
= false;
2136 op
[0] = mul_instr
->operands
[0];
2137 op
[1] = mul_instr
->operands
[1];
2138 op
[2] = instr
->operands
[add_op_idx
];
2139 for (unsigned i
= 0; i
< 3; i
++)
2141 if (op
[i
].isLiteral())
2143 if (op
[i
].isTemp() && op
[i
].getTemp().type() == RegType::sgpr
)
2145 if (!(i
== 0 || (op
[i
].isTemp() && op
[i
].getTemp().type() == RegType::vgpr
)))
2148 // TODO: would be better to check this before selecting a mul instr?
2152 if (mul_instr
->isVOP3()) {
2153 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2154 neg
[0] = vop3
->neg
[0];
2155 neg
[1] = vop3
->neg
[1];
2156 abs
[0] = vop3
->abs
[0];
2157 abs
[1] = vop3
->abs
[1];
2159 /* we cannot use these modifiers between mul and add */
2160 if (vop3
->clamp
|| vop3
->omod
)
2164 /* convert to mad */
2165 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2166 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2168 ctx
.uses
[op
[0].tempId()]++;
2170 ctx
.uses
[op
[1].tempId()]++;
2173 if (instr
->isVOP3()) {
2174 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2175 neg
[2] = vop3
->neg
[add_op_idx
];
2176 abs
[2] = vop3
->abs
[add_op_idx
];
2178 clamp
= vop3
->clamp
;
2179 /* abs of the multiplication result */
2180 if (vop3
->abs
[1 - add_op_idx
]) {
2186 /* neg of the multiplication result */
2187 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2190 if (instr
->opcode
== aco_opcode::v_sub_f32
) {
2191 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2193 } else if (instr
->opcode
== aco_opcode::v_subrev_f32
) {
2194 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2198 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2199 for (unsigned i
= 0; i
< 3; i
++)
2201 mad
->operands
[i
] = op
[i
];
2202 mad
->neg
[i
] = neg
[i
];
2203 mad
->abs
[i
] = abs
[i
];
2207 mad
->definitions
[0] = instr
->definitions
[0];
2209 /* mark this ssa_def to be re-checked for profitability and literals */
2210 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId(), need_vop3
);
2211 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2212 instr
.reset(mad
.release());
2216 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2217 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2218 for (unsigned i
= 0; i
< 2; i
++) {
2219 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2220 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2221 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2222 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2223 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2225 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2226 new_instr
->operands
[0] = Operand(0u);
2227 new_instr
->operands
[1] = instr
->operands
[!i
];
2228 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2229 new_instr
->definitions
[0] = instr
->definitions
[0];
2230 instr
.reset(new_instr
.release());
2231 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2235 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2236 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2237 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2238 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2239 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2240 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2241 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2242 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2243 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2244 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2245 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2246 combine_salu_lshl_add(ctx
, instr
);
2247 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2248 combine_salu_not_bitwise(ctx
, instr
);
2249 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2250 if (combine_inverse_comparison(ctx
, instr
)) ;
2251 else combine_salu_not_bitwise(ctx
, instr
);
2252 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2253 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2254 if (combine_ordering_test(ctx
, instr
)) ;
2255 else if (combine_comparison_ordering(ctx
, instr
)) ;
2256 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2257 else combine_salu_n2(ctx
, instr
);
2259 aco_opcode min
, max
, min3
, max3
, med3
;
2260 bool some_gfx9_only
;
2261 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2262 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2263 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, instr
->opcode
== min
? min3
: max3
, "012", 1 | 2));
2264 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2270 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2272 const uint32_t threshold
= 4;
2274 if (is_dead(ctx
.uses
, instr
.get())) {
2279 /* convert split_vector into extract_vector if only one definition is ever used */
2280 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2281 unsigned num_used
= 0;
2283 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2284 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2289 if (num_used
== 1) {
2290 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2291 extract
->operands
[0] = instr
->operands
[0];
2292 extract
->operands
[1] = Operand((uint32_t) idx
);
2293 extract
->definitions
[0] = instr
->definitions
[idx
];
2294 instr
.reset(extract
.release());
2298 /* re-check mad instructions */
2299 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2300 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2301 /* first, check profitability */
2302 if (ctx
.uses
[info
->mul_temp_id
]) {
2303 ctx
.uses
[info
->mul_temp_id
]++;
2304 instr
.swap(info
->add_instr
);
2306 /* second, check possible literals */
2307 } else if (!info
->needs_vop3
) {
2308 uint32_t literal_idx
= 0;
2309 uint32_t literal_uses
= UINT32_MAX
;
2310 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2312 if (!instr
->operands
[i
].isTemp())
2314 /* if one of the operands is sgpr, we cannot add a literal somewhere else */
2315 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2316 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2317 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2320 literal_uses
= UINT32_MAX
;
2324 else if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2325 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2326 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2330 if (literal_uses
< threshold
) {
2331 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2332 info
->check_literal
= true;
2333 info
->literal_idx
= literal_idx
;
2339 /* check for literals */
2340 /* we do not apply the literals yet as we don't know if it is profitable */
2341 if (instr
->isSALU()) {
2342 uint32_t literal_idx
= 0;
2343 uint32_t literal_uses
= UINT32_MAX
;
2344 bool has_literal
= false;
2345 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2347 if (instr
->operands
[i
].isLiteral()) {
2351 if (!instr
->operands
[i
].isTemp())
2353 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2354 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2355 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2359 if (!has_literal
&& literal_uses
< threshold
) {
2360 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2361 if (ctx
.uses
[instr
->operands
[literal_idx
].tempId()] == 0)
2362 instr
->operands
[literal_idx
] = Operand(ctx
.info
[instr
->operands
[literal_idx
].tempId()].val
);
2364 } else if (instr
->isVALU() && valu_can_accept_literal(ctx
, instr
, 0) &&
2365 instr
->operands
[0].isTemp() &&
2366 ctx
.info
[instr
->operands
[0].tempId()].is_literal() &&
2367 ctx
.uses
[instr
->operands
[0].tempId()] < threshold
) {
2368 ctx
.uses
[instr
->operands
[0].tempId()]--;
2369 if (ctx
.uses
[instr
->operands
[0].tempId()] == 0)
2370 instr
->operands
[0] = Operand(ctx
.info
[instr
->operands
[0].tempId()].val
);
2376 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2378 /* Cleanup Dead Instructions */
2382 /* apply literals on SALU */
2383 if (instr
->isSALU()) {
2384 for (Operand
& op
: instr
->operands
) {
2389 if (ctx
.info
[op
.tempId()].is_literal() &&
2390 ctx
.uses
[op
.tempId()] == 0)
2391 op
= Operand(ctx
.info
[op
.tempId()].val
);
2395 /* apply literals on VALU */
2396 else if (instr
->isVALU() && !instr
->isVOP3() &&
2397 instr
->operands
[0].isTemp() &&
2398 ctx
.info
[instr
->operands
[0].tempId()].is_literal() &&
2399 ctx
.uses
[instr
->operands
[0].tempId()] == 0) {
2400 instr
->operands
[0] = Operand(ctx
.info
[instr
->operands
[0].tempId()].val
);
2403 /* apply literals on MAD */
2404 else if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2405 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2406 aco_ptr
<Instruction
> new_mad
;
2407 if (info
->check_literal
&& ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0) {
2408 if (info
->literal_idx
== 2) { /* add literal -> madak */
2409 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2410 new_mad
->operands
[0] = instr
->operands
[0];
2411 new_mad
->operands
[1] = instr
->operands
[1];
2412 } else { /* mul literal -> madmk */
2413 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2414 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2415 new_mad
->operands
[1] = instr
->operands
[2];
2417 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2418 new_mad
->definitions
[0] = instr
->definitions
[0];
2419 instr
.swap(new_mad
);
2423 ctx
.instructions
.emplace_back(std::move(instr
));
2427 void optimize(Program
* program
)
2430 ctx
.program
= program
;
2431 std::vector
<ssa_info
> info(program
->peekAllocationId());
2432 ctx
.info
= info
.data();
2434 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2435 for (Block
& block
: program
->blocks
) {
2436 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2437 label_instruction(ctx
, block
, instr
);
2440 ctx
.uses
= std::move(dead_code_analysis(program
));
2442 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2443 for (Block
& block
: program
->blocks
) {
2444 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2445 combine_instruction(ctx
, block
, instr
);
2448 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2449 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2450 Block
* block
= &(*it
);
2451 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2452 select_instruction(ctx
, *it
);
2455 /* 4. Add literals to instructions */
2456 for (Block
& block
: program
->blocks
) {
2457 ctx
.instructions
.clear();
2458 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2459 apply_literals(ctx
, instr
);
2460 block
.instructions
.swap(ctx
.instructions
);