2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant
= 1 << 1,
69 label_literal
= 1 << 6,
73 label_omod5
= 1 << 10,
74 label_omod_success
= 1 << 11,
75 label_clamp
= 1 << 12,
76 label_clamp_success
= 1 << 13,
77 label_undefined
= 1 << 14,
80 label_add_sub
= 1 << 17,
81 label_bitwise
= 1 << 18,
82 label_minmax
= 1 << 19,
84 label_uniform_bool
= 1 << 21,
85 label_constant_64bit
= 1 << 22,
86 label_uniform_bitwise
= 1 << 23,
87 label_scc_invert
= 1 << 24,
88 label_vcc_hint
= 1 << 25,
89 label_scc_needed
= 1 << 26,
92 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
|
93 label_add_sub
| label_bitwise
| label_uniform_bitwise
| label_minmax
| label_fcmp
;
94 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
|
95 label_omod2
| label_omod4
| label_omod5
| label_clamp
| label_scc_invert
;
96 static constexpr uint32_t val_labels
= label_constant
| label_constant_64bit
| label_literal
| label_mad
;
106 void add_label(Label new_label
)
108 /* Since all labels which use "instr" use it for the same thing
109 * (indicating the defining instruction), there is no need to clear
110 * any other instr labels. */
111 if (new_label
& instr_labels
)
112 label
&= ~temp_labels
; /* instr and temp alias */
114 if (new_label
& temp_labels
) {
115 label
&= ~temp_labels
;
116 label
&= ~instr_labels
; /* instr and temp alias */
119 if (new_label
& val_labels
)
120 label
&= ~val_labels
;
125 void set_vec(Instruction
* vec
)
127 add_label(label_vec
);
133 return label
& label_vec
;
136 void set_constant(uint32_t constant
)
138 add_label(label_constant
);
144 return label
& label_constant
;
147 void set_constant_64bit(uint32_t constant
)
149 add_label(label_constant_64bit
);
153 bool is_constant_64bit()
155 return label
& label_constant_64bit
;
158 void set_abs(Temp abs_temp
)
160 add_label(label_abs
);
166 return label
& label_abs
;
169 void set_neg(Temp neg_temp
)
171 add_label(label_neg
);
177 return label
& label_neg
;
180 void set_neg_abs(Temp neg_abs_temp
)
182 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
186 void set_mul(Instruction
* mul
)
188 add_label(label_mul
);
194 return label
& label_mul
;
197 void set_temp(Temp tmp
)
199 add_label(label_temp
);
205 return label
& label_temp
;
208 void set_literal(uint32_t lit
)
210 add_label(label_literal
);
216 return label
& label_literal
;
219 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
221 add_label(label_mad
);
228 return label
& label_mad
;
231 void set_omod2(Temp def
)
233 add_label(label_omod2
);
239 return label
& label_omod2
;
242 void set_omod4(Temp def
)
244 add_label(label_omod4
);
250 return label
& label_omod4
;
253 void set_omod5(Temp def
)
255 add_label(label_omod5
);
261 return label
& label_omod5
;
264 void set_omod_success(Instruction
* omod_instr
)
266 add_label(label_omod_success
);
270 bool is_omod_success()
272 return label
& label_omod_success
;
275 void set_clamp(Temp def
)
277 add_label(label_clamp
);
283 return label
& label_clamp
;
286 void set_clamp_success(Instruction
* clamp_instr
)
288 add_label(label_clamp_success
);
292 bool is_clamp_success()
294 return label
& label_clamp_success
;
299 add_label(label_undefined
);
304 return label
& label_undefined
;
307 void set_vcc(Temp vcc
)
309 add_label(label_vcc
);
315 return label
& label_vcc
;
318 bool is_constant_or_literal()
320 return is_constant() || is_literal();
323 void set_b2f(Temp val
)
325 add_label(label_b2f
);
331 return label
& label_b2f
;
334 void set_add_sub(Instruction
*add_sub_instr
)
336 add_label(label_add_sub
);
337 instr
= add_sub_instr
;
342 return label
& label_add_sub
;
345 void set_bitwise(Instruction
*bitwise_instr
)
347 add_label(label_bitwise
);
348 instr
= bitwise_instr
;
353 return label
& label_bitwise
;
356 void set_uniform_bitwise()
358 add_label(label_uniform_bitwise
);
361 bool is_uniform_bitwise()
363 return label
& label_uniform_bitwise
;
366 void set_minmax(Instruction
*minmax_instr
)
368 add_label(label_minmax
);
369 instr
= minmax_instr
;
374 return label
& label_minmax
;
377 void set_fcmp(Instruction
*fcmp_instr
)
379 add_label(label_fcmp
);
385 return label
& label_fcmp
;
388 void set_scc_needed()
390 add_label(label_scc_needed
);
395 return label
& label_scc_needed
;
398 void set_scc_invert(Temp scc_inv
)
400 add_label(label_scc_invert
);
406 return label
& label_scc_invert
;
409 void set_uniform_bool(Temp uniform_bool
)
411 add_label(label_uniform_bool
);
415 bool is_uniform_bool()
417 return label
& label_uniform_bool
;
422 add_label(label_vcc_hint
);
427 return label
& label_vcc_hint
;
433 std::vector
<aco_ptr
<Instruction
>> instructions
;
435 std::pair
<uint32_t,Temp
> last_literal
;
436 std::vector
<mad_info
> mad_infos
;
437 std::vector
<uint16_t> uses
;
440 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
442 if (instr
->operands
[0].isConstant() ||
443 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
446 switch (instr
->opcode
) {
447 case aco_opcode::v_add_f32
:
448 case aco_opcode::v_mul_f32
:
449 case aco_opcode::v_or_b32
:
450 case aco_opcode::v_and_b32
:
451 case aco_opcode::v_xor_b32
:
452 case aco_opcode::v_max_f32
:
453 case aco_opcode::v_min_f32
:
454 case aco_opcode::v_max_i32
:
455 case aco_opcode::v_min_i32
:
456 case aco_opcode::v_max_u32
:
457 case aco_opcode::v_min_u32
:
458 case aco_opcode::v_cmp_eq_f32
:
459 case aco_opcode::v_cmp_lg_f32
:
461 case aco_opcode::v_sub_f32
:
462 instr
->opcode
= aco_opcode::v_subrev_f32
;
464 case aco_opcode::v_cmp_lt_f32
:
465 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
467 case aco_opcode::v_cmp_ge_f32
:
468 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
470 case aco_opcode::v_cmp_lt_i32
:
471 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
478 bool can_use_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
483 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
486 if (instr
->isDPP() || instr
->isSDWA())
489 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
490 instr
->opcode
!= aco_opcode::v_madak_f32
&&
491 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
492 instr
->opcode
!= aco_opcode::v_madak_f16
&&
493 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
494 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
495 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
496 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
497 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
498 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
499 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
502 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
504 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
505 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
506 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
507 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
508 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
511 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
516 aco_ptr
<Instruction
> tmp
= std::move(instr
);
517 Format format
= asVOP3(tmp
->format
);
518 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
519 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
520 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
521 instr
->definitions
[i
] = tmp
->definitions
[i
];
522 if (instr
->definitions
[i
].isTemp()) {
523 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
524 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
525 info
.instr
= instr
.get();
530 /* only covers special cases */
531 bool alu_can_accept_constant(aco_opcode opcode
, unsigned operand
)
534 case aco_opcode::v_interp_p2_f32
:
535 case aco_opcode::v_mac_f32
:
536 case aco_opcode::v_writelane_b32
:
537 case aco_opcode::v_writelane_b32_e64
:
538 case aco_opcode::v_cndmask_b32
:
540 case aco_opcode::s_addk_i32
:
541 case aco_opcode::s_mulk_i32
:
542 case aco_opcode::p_wqm
:
543 case aco_opcode::p_extract_vector
:
544 case aco_opcode::p_split_vector
:
545 case aco_opcode::v_readlane_b32
:
546 case aco_opcode::v_readlane_b32_e64
:
547 case aco_opcode::v_readfirstlane_b32
:
554 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
556 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
557 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
562 /* check constant bus and literal limitations */
563 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
565 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
566 Operand
literal32(s1
);
567 Operand
literal64(s2
);
568 unsigned num_sgprs
= 0;
569 unsigned sgpr
[] = {0, 0};
571 for (unsigned i
= 0; i
< num_operands
; i
++) {
572 Operand op
= operands
[i
];
574 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
575 /* two reads of the same SGPR count as 1 to the limit */
576 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
578 sgpr
[num_sgprs
++] = op
.tempId();
583 } else if (op
.isLiteral()) {
584 if (ctx
.program
->chip_class
< GFX10
)
587 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
589 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
592 /* Any number of 32-bit literals counts as only 1 to the limit. Same
593 * (but separately) for 64-bit literals. */
594 if (op
.size() == 1 && literal32
.isUndefined()) {
597 } else if (op
.size() == 2 && literal64
.isUndefined()) {
610 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
612 Operand op
= instr
->operands
[op_index
];
616 Temp tmp
= op
.getTemp();
617 if (!ctx
.info
[tmp
.id()].is_add_sub())
620 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
622 switch (add_instr
->opcode
) {
623 case aco_opcode::v_add_u32
:
624 case aco_opcode::v_add_co_u32
:
625 case aco_opcode::v_add_co_u32_e64
:
626 case aco_opcode::s_add_i32
:
627 case aco_opcode::s_add_u32
:
633 if (add_instr
->usesModifiers())
636 for (unsigned i
= 0; i
< 2; i
++) {
637 if (add_instr
->operands
[i
].isConstant()) {
638 *offset
= add_instr
->operands
[i
].constantValue();
639 } else if (add_instr
->operands
[i
].isTemp() &&
640 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
641 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
645 if (!add_instr
->operands
[!i
].isTemp())
648 uint32_t offset2
= 0;
649 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
652 *base
= add_instr
->operands
[!i
].getTemp();
660 Operand
get_constant_op(opt_ctx
&ctx
, uint32_t val
, bool is64bit
= false)
662 // TODO: this functions shouldn't be needed if we store Operand instead of value.
663 Operand
op(val
, is64bit
);
664 if (val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
665 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
669 bool fixed_to_exec(Operand op
)
671 return op
.isFixed() && op
.physReg() == exec
;
674 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
676 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
677 ASSERTED
bool all_const
= false;
678 for (Operand
& op
: instr
->operands
)
679 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
680 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
683 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
685 if (!instr
->operands
[i
].isTemp())
688 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
689 /* propagate undef */
690 if (info
.is_undefined() && is_phi(instr
))
691 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
692 /* propagate reg->reg of same type */
693 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
694 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
695 info
= ctx
.info
[info
.temp
.id()];
698 /* SALU / PSEUDO: propagate inline constants */
699 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
700 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
701 instr
->operands
[i
].setTemp(info
.temp
);
702 info
= ctx
.info
[info
.temp
.id()];
703 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
704 /* propagate vgpr if it can take it */
705 switch (instr
->opcode
) {
706 case aco_opcode::p_create_vector
:
707 case aco_opcode::p_split_vector
:
708 case aco_opcode::p_extract_vector
:
709 case aco_opcode::p_phi
: {
710 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
711 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
713 instr
->operands
[i
] = Operand(info
.temp
);
714 info
= ctx
.info
[info
.temp
.id()];
722 if ((info
.is_constant() || info
.is_constant_64bit() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) &&
723 !instr
->operands
[i
].isFixed() && alu_can_accept_constant(instr
->opcode
, i
)) {
724 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
729 /* VALU: propagate neg, abs & inline constants */
730 else if (instr
->isVALU()) {
731 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
732 instr
->operands
[i
].setTemp(info
.temp
);
733 info
= ctx
.info
[info
.temp
.id()];
735 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
738 instr
->operands
[i
] = Operand(info
.temp
);
740 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
742 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
744 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
745 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
746 instr
->operands
[i
].setTemp(info
.temp
);
748 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
751 instr
->operands
[i
].setTemp(info
.temp
);
753 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
755 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
758 if ((info
.is_constant() || info
.is_constant_64bit()) && alu_can_accept_constant(instr
->opcode
, i
)) {
759 Operand op
= get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
760 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
761 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
762 instr
->operands
[i
] = op
;
764 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
765 instr
->operands
[i
] = instr
->operands
[0];
766 instr
->operands
[0] = op
;
768 } else if (can_use_VOP3(ctx
, instr
)) {
770 instr
->operands
[i
] = op
;
776 /* MUBUF: propagate constants and combine additions */
777 else if (instr
->format
== Format::MUBUF
) {
778 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
781 while (info
.is_temp())
782 info
= ctx
.info
[info
.temp
.id()];
784 if (mubuf
->offen
&& i
== 1 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
785 assert(!mubuf
->idxen
);
786 instr
->operands
[1] = Operand(v1
);
787 mubuf
->offset
+= info
.val
;
788 mubuf
->offen
= false;
790 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
791 instr
->operands
[2] = Operand((uint32_t) 0);
792 mubuf
->offset
+= info
.val
;
794 } else if (mubuf
->offen
&& i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
795 assert(!mubuf
->idxen
);
796 instr
->operands
[1].setTemp(base
);
797 mubuf
->offset
+= offset
;
799 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
800 instr
->operands
[i
].setTemp(base
);
801 mubuf
->offset
+= offset
;
806 /* DS: combine additions */
807 else if (instr
->format
== Format::DS
) {
809 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
812 bool has_usable_ds_offset
= ctx
.program
->chip_class
>= GFX7
;
813 if (has_usable_ds_offset
&&
814 i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) &&
815 base
.regClass() == instr
->operands
[i
].regClass() &&
816 instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
817 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
818 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
819 unsigned mask
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 0x7 : 0x3;
820 unsigned shifts
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 3 : 2;
822 if ((offset
& mask
) == 0 &&
823 ds
->offset0
+ (offset
>> shifts
) <= 255 &&
824 ds
->offset1
+ (offset
>> shifts
) <= 255) {
825 instr
->operands
[i
].setTemp(base
);
826 ds
->offset0
+= offset
>> shifts
;
827 ds
->offset1
+= offset
>> shifts
;
830 if (ds
->offset0
+ offset
<= 65535) {
831 instr
->operands
[i
].setTemp(base
);
832 ds
->offset0
+= offset
;
838 /* SMEM: propagate constants and combine additions */
839 else if (instr
->format
== Format::SMEM
) {
841 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
844 if (i
== 1 && info
.is_constant_or_literal() &&
845 ((ctx
.program
->chip_class
== GFX6
&& info
.val
<= 0x3FF) ||
846 (ctx
.program
->chip_class
== GFX7
&& info
.val
<= 0xFFFFFFFF) ||
847 (ctx
.program
->chip_class
>= GFX8
&& info
.val
<= 0xFFFFF))) {
848 instr
->operands
[i
] = Operand(info
.val
);
850 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
851 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
853 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
854 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
858 smem
->operands
[1] = Operand(offset
);
859 smem
->operands
.back() = Operand(base
);
861 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
862 new_instr
->operands
[0] = smem
->operands
[0];
863 new_instr
->operands
[1] = Operand(offset
);
864 if (smem
->definitions
.empty())
865 new_instr
->operands
[2] = smem
->operands
[2];
866 new_instr
->operands
.back() = Operand(base
);
867 if (!smem
->definitions
.empty())
868 new_instr
->definitions
[0] = smem
->definitions
[0];
869 new_instr
->can_reorder
= smem
->can_reorder
;
870 new_instr
->barrier
= smem
->barrier
;
871 instr
.reset(new_instr
);
872 smem
= static_cast<SMEM_instruction
*>(instr
.get());
878 else if (instr
->format
== Format::PSEUDO_BRANCH
) {
879 if (ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
880 /* Flip the branch instruction to get rid of the scc_invert instruction */
881 instr
->opcode
= instr
->opcode
== aco_opcode::p_cbranch_z
? aco_opcode::p_cbranch_nz
: aco_opcode::p_cbranch_z
;
882 instr
->operands
[0].setTemp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
887 /* if this instruction doesn't define anything, return */
888 if (instr
->definitions
.empty())
891 switch (instr
->opcode
) {
892 case aco_opcode::p_create_vector
: {
893 unsigned num_ops
= instr
->operands
.size();
894 for (const Operand
& op
: instr
->operands
) {
895 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
896 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
898 if (num_ops
!= instr
->operands
.size()) {
899 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
900 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
901 instr
->definitions
[0] = old_vec
->definitions
[0];
903 for (Operand
& old_op
: old_vec
->operands
) {
904 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
905 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
906 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
907 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
908 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
909 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
910 instr
->operands
[k
++] = op
;
913 instr
->operands
[k
++] = old_op
;
916 assert(k
== num_ops
);
918 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
919 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
920 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
921 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
924 case aco_opcode::p_split_vector
: {
925 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
927 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
928 assert(instr
->definitions
.size() == vec
->operands
.size());
929 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
930 Operand vec_op
= vec
->operands
[i
];
931 if (vec_op
.isConstant()) {
932 if (vec_op
.isLiteral())
933 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
934 else if (vec_op
.size() == 1)
935 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
936 else if (vec_op
.size() == 2)
937 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant_64bit(vec_op
.constantValue());
939 assert(vec_op
.isTemp());
940 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
945 case aco_opcode::p_extract_vector
: { /* mov */
946 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
948 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
949 if (vec
->definitions
[0].getTemp().size() == vec
->operands
.size() && /* TODO: what about 64bit or other combinations? */
950 vec
->operands
[0].size() == instr
->definitions
[0].size()) {
952 /* convert this extract into a mov instruction */
953 Operand vec_op
= vec
->operands
[instr
->operands
[1].constantValue()];
954 bool is_vgpr
= instr
->definitions
[0].getTemp().type() == RegType::vgpr
;
955 aco_opcode opcode
= is_vgpr
? aco_opcode::v_mov_b32
: aco_opcode::s_mov_b32
;
956 Format format
= is_vgpr
? Format::VOP1
: Format::SOP1
;
957 instr
->opcode
= opcode
;
958 instr
->format
= format
;
959 while (instr
->operands
.size() > 1)
960 instr
->operands
.pop_back();
961 instr
->operands
[0] = vec_op
;
963 if (vec_op
.isConstant()) {
964 if (vec_op
.isLiteral())
965 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(vec_op
.constantValue());
966 else if (vec_op
.size() == 1)
967 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(vec_op
.constantValue());
968 else if (vec_op
.size() == 2)
969 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(vec_op
.constantValue());
972 assert(vec_op
.isTemp());
973 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vec_op
.getTemp());
978 case aco_opcode::s_mov_b32
: /* propagate */
979 case aco_opcode::s_mov_b64
:
980 case aco_opcode::v_mov_b32
:
981 case aco_opcode::p_as_uniform
:
982 if (instr
->definitions
[0].isFixed()) {
983 /* don't copy-propagate copies into fixed registers */
984 } else if (instr
->usesModifiers()) {
986 } else if (instr
->operands
[0].isConstant()) {
987 if (instr
->operands
[0].isLiteral())
988 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
989 else if (instr
->operands
[0].size() == 1)
990 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
991 else if (instr
->operands
[0].size() == 2)
992 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(instr
->operands
[0].constantValue());
993 } else if (instr
->operands
[0].isTemp()) {
994 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
996 assert(instr
->operands
[0].isFixed());
999 case aco_opcode::p_is_helper
:
1000 if (!ctx
.program
->needs_wqm
)
1001 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
1003 case aco_opcode::s_movk_i32
: {
1004 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
1005 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
1006 if (v
<= 64 || v
>= 0xfffffff0)
1007 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1009 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1012 case aco_opcode::v_bfrev_b32
:
1013 case aco_opcode::s_brev_b32
: {
1014 if (instr
->operands
[0].isConstant()) {
1015 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
1016 if (v
<= 64 || v
>= 0xfffffff0)
1017 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1019 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1023 case aco_opcode::s_bfm_b32
: {
1024 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
1025 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
1026 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
1027 uint32_t v
= ((1u << size
) - 1u) << start
;
1028 if (v
<= 64 || v
>= 0xfffffff0)
1029 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1031 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1034 case aco_opcode::v_mul_f32
: { /* omod */
1035 /* TODO: try to move the negate/abs modifier to the consumer instead */
1036 if (instr
->usesModifiers())
1039 for (unsigned i
= 0; i
< 2; i
++) {
1040 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
1041 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
1042 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
1043 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
1044 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
1045 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
1046 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
1047 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000 &&
1048 !block
.fp_mode
.must_flush_denorms32
) { /* 1.0 */
1049 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
1058 case aco_opcode::v_and_b32
: /* abs */
1059 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x7FFFFFFF) &&
1060 instr
->operands
[1].isTemp() && instr
->operands
[1].getTemp().type() == RegType::vgpr
)
1061 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
1063 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1065 case aco_opcode::v_xor_b32
: { /* neg */
1066 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
1067 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
1068 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1069 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
1070 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
1071 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1072 instr
->opcode
= aco_opcode::v_or_b32
;
1073 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
1075 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
1079 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1083 case aco_opcode::v_med3_f32
: { /* clamp */
1084 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1085 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1086 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1087 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1091 bool found_zero
= false, found_one
= false;
1092 for (unsigned i
= 0; i
< 3; i
++)
1094 if (instr
->operands
[i
].constantEquals(0))
1096 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1101 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1102 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1106 case aco_opcode::v_cndmask_b32
:
1107 if (instr
->operands
[0].constantEquals(0) &&
1108 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
1109 instr
->operands
[2].isTemp())
1110 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1111 else if (instr
->operands
[0].constantEquals(0) &&
1112 instr
->operands
[1].constantEquals(0x3f800000u
) &&
1113 instr
->operands
[2].isTemp())
1114 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1116 ctx
.info
[instr
->operands
[2].tempId()].set_vcc_hint();
1118 case aco_opcode::v_cmp_lg_u32
:
1119 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1120 instr
->operands
[0].constantEquals(0) &&
1121 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1122 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1124 case aco_opcode::p_phi
:
1125 case aco_opcode::p_linear_phi
: {
1126 /* lower_bool_phis() can create phis like this */
1127 bool all_same_temp
= instr
->operands
[0].isTemp();
1128 /* this check is needed when moving uniform loop counters out of a divergent loop */
1130 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1131 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1132 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1133 all_same_temp
= false;
1135 if (all_same_temp
) {
1136 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1138 bool all_undef
= instr
->operands
[0].isUndefined();
1139 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1140 if (!instr
->operands
[i
].isUndefined())
1144 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1148 case aco_opcode::v_add_u32
:
1149 case aco_opcode::v_add_co_u32
:
1150 case aco_opcode::v_add_co_u32_e64
:
1151 case aco_opcode::s_add_i32
:
1152 case aco_opcode::s_add_u32
:
1153 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1155 case aco_opcode::s_not_b32
:
1156 case aco_opcode::s_not_b64
:
1157 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1158 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1159 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1160 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1161 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1162 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1164 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1166 case aco_opcode::s_and_b32
:
1167 case aco_opcode::s_and_b64
:
1168 if (fixed_to_exec(instr
->operands
[1]) && instr
->operands
[0].isTemp()) {
1169 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1170 /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
1171 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1172 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1174 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1175 /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
1176 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1177 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1182 case aco_opcode::s_or_b32
:
1183 case aco_opcode::s_or_b64
:
1184 case aco_opcode::s_xor_b32
:
1185 case aco_opcode::s_xor_b64
:
1186 if (std::all_of(instr
->operands
.begin(), instr
->operands
.end(), [&ctx
](const Operand
& op
) {
1187 return op
.isTemp() && (ctx
.info
[op
.tempId()].is_uniform_bool() || ctx
.info
[op
.tempId()].is_uniform_bitwise());
1189 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1192 case aco_opcode::s_lshl_b32
:
1193 case aco_opcode::v_or_b32
:
1194 case aco_opcode::v_lshlrev_b32
:
1195 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1197 case aco_opcode::v_min_f32
:
1198 case aco_opcode::v_min_f16
:
1199 case aco_opcode::v_min_u32
:
1200 case aco_opcode::v_min_i32
:
1201 case aco_opcode::v_min_u16
:
1202 case aco_opcode::v_min_i16
:
1203 case aco_opcode::v_max_f32
:
1204 case aco_opcode::v_max_f16
:
1205 case aco_opcode::v_max_u32
:
1206 case aco_opcode::v_max_i32
:
1207 case aco_opcode::v_max_u16
:
1208 case aco_opcode::v_max_i16
:
1209 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1211 case aco_opcode::v_cmp_lt_f32
:
1212 case aco_opcode::v_cmp_eq_f32
:
1213 case aco_opcode::v_cmp_le_f32
:
1214 case aco_opcode::v_cmp_gt_f32
:
1215 case aco_opcode::v_cmp_lg_f32
:
1216 case aco_opcode::v_cmp_ge_f32
:
1217 case aco_opcode::v_cmp_o_f32
:
1218 case aco_opcode::v_cmp_u_f32
:
1219 case aco_opcode::v_cmp_nge_f32
:
1220 case aco_opcode::v_cmp_nlg_f32
:
1221 case aco_opcode::v_cmp_ngt_f32
:
1222 case aco_opcode::v_cmp_nle_f32
:
1223 case aco_opcode::v_cmp_neq_f32
:
1224 case aco_opcode::v_cmp_nlt_f32
:
1225 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1227 case aco_opcode::s_cselect_b64
:
1228 case aco_opcode::s_cselect_b32
:
1229 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1230 instr
->operands
[1].constantEquals(0)) {
1231 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1232 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1234 if (instr
->operands
[2].isTemp() && ctx
.info
[instr
->operands
[2].tempId()].is_scc_invert()) {
1235 /* Flip the operands to get rid of the scc_invert instruction */
1236 std::swap(instr
->operands
[0], instr
->operands
[1]);
1237 instr
->operands
[2].setTemp(ctx
.info
[instr
->operands
[2].tempId()].temp
);
1240 case aco_opcode::p_wqm
:
1241 if (instr
->operands
[0].isTemp() &&
1242 ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1243 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1251 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1253 *ordered
= *unordered
= op
;
1255 #define CMP(ord, unord) \
1256 case aco_opcode::v_cmp_##ord##_f32:\
1257 case aco_opcode::v_cmp_n##unord##_f32:\
1258 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1259 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1260 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1274 aco_opcode
get_ordered(aco_opcode op
)
1276 aco_opcode ordered
, unordered
, inverse
;
1277 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1280 aco_opcode
get_unordered(aco_opcode op
)
1282 aco_opcode ordered
, unordered
, inverse
;
1283 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1286 aco_opcode
get_inverse(aco_opcode op
)
1288 aco_opcode ordered
, unordered
, inverse
;
1289 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1292 bool is_cmp(aco_opcode op
)
1294 aco_opcode ordered
, unordered
, inverse
;
1295 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1298 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1300 if (ctx
.info
[tmp
.id()].is_temp())
1301 return ctx
.info
[tmp
.id()].temp
.id();
1306 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1308 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1309 for (const Operand
& op
: instr
->operands
) {
1311 ctx
.uses
[op
.tempId()]--;
1316 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1318 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1320 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1323 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1325 if (instr
->definitions
.size() == 2) {
1326 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1327 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1334 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1335 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1336 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1338 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1340 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1343 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1345 bool neg
[2] = {false, false};
1346 bool abs
[2] = {false, false};
1348 Instruction
*op_instr
[2];
1351 for (unsigned i
= 0; i
< 2; i
++) {
1352 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1356 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1358 if (op_instr
[i
]->opcode
!= expected_cmp
)
1360 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1363 if (op_instr
[i
]->isVOP3()) {
1364 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1365 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1367 neg
[i
] = vop3
->neg
[0];
1368 abs
[i
] = vop3
->abs
[0];
1369 opsel
|= (vop3
->opsel
& 1) << i
;
1372 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1373 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1374 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1380 if (op
[1].type() == RegType::sgpr
)
1381 std::swap(op
[0], op
[1]);
1382 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1383 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1386 ctx
.uses
[op
[0].id()]++;
1387 ctx
.uses
[op
[1].id()]++;
1388 decrease_uses(ctx
, op_instr
[0]);
1389 decrease_uses(ctx
, op_instr
[1]);
1391 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1392 Instruction
*new_instr
;
1393 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1394 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1395 for (unsigned i
= 0; i
< 2; i
++) {
1396 vop3
->neg
[i
] = neg
[i
];
1397 vop3
->abs
[i
] = abs
[i
];
1399 vop3
->opsel
= opsel
;
1400 new_instr
= static_cast<Instruction
*>(vop3
);
1402 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1404 new_instr
->operands
[0] = Operand(op
[0]);
1405 new_instr
->operands
[1] = Operand(op
[1]);
1406 new_instr
->definitions
[0] = instr
->definitions
[0];
1408 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1409 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1411 instr
.reset(new_instr
);
1416 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1417 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1418 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1420 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1422 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1425 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1426 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1428 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1429 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1430 if (!nan_test
|| !cmp
)
1433 if (cmp
->opcode
== expected_nan_test
)
1434 std::swap(nan_test
, cmp
);
1435 else if (nan_test
->opcode
!= expected_nan_test
)
1438 if (!is_cmp(cmp
->opcode
))
1441 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1443 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1446 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1447 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1448 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1449 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1450 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1452 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1455 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1456 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1457 decrease_uses(ctx
, nan_test
);
1458 decrease_uses(ctx
, cmp
);
1460 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1461 Instruction
*new_instr
;
1462 if (cmp
->isVOP3()) {
1463 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1464 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1465 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1466 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1467 new_vop3
->clamp
= cmp_vop3
->clamp
;
1468 new_vop3
->omod
= cmp_vop3
->omod
;
1469 new_vop3
->opsel
= cmp_vop3
->opsel
;
1470 new_instr
= new_vop3
;
1472 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1474 new_instr
->operands
[0] = cmp
->operands
[0];
1475 new_instr
->operands
[1] = cmp
->operands
[1];
1476 new_instr
->definitions
[0] = instr
->definitions
[0];
1478 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1479 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1481 instr
.reset(new_instr
);
1486 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1487 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1488 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1490 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1492 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1495 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1497 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1498 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1500 if (!nan_test
|| !cmp
)
1503 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1504 if (cmp
->opcode
== expected_nan_test
)
1505 std::swap(nan_test
, cmp
);
1506 else if (nan_test
->opcode
!= expected_nan_test
)
1509 if (!is_cmp(cmp
->opcode
))
1512 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1514 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1517 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1518 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1519 if (prop_nan0
!= prop_nan1
)
1522 if (nan_test
->isVOP3()) {
1523 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1524 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1528 int constant_operand
= -1;
1529 for (unsigned i
= 0; i
< 2; i
++) {
1530 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1531 constant_operand
= !i
;
1535 if (constant_operand
== -1)
1539 if (cmp
->operands
[constant_operand
].isConstant()) {
1540 constant
= cmp
->operands
[constant_operand
].constantValue();
1541 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1542 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1543 unsigned id
= original_temp_id(ctx
, tmp
);
1544 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1546 constant
= ctx
.info
[id
].val
;
1552 memcpy(&constantf
, &constant
, 4);
1553 if (isnan(constantf
))
1556 if (cmp
->operands
[0].isTemp())
1557 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1558 if (cmp
->operands
[1].isTemp())
1559 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1560 decrease_uses(ctx
, nan_test
);
1561 decrease_uses(ctx
, cmp
);
1563 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1564 Instruction
*new_instr
;
1565 if (cmp
->isVOP3()) {
1566 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1567 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1568 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1569 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1570 new_vop3
->clamp
= cmp_vop3
->clamp
;
1571 new_vop3
->omod
= cmp_vop3
->omod
;
1572 new_vop3
->opsel
= cmp_vop3
->opsel
;
1573 new_instr
= new_vop3
;
1575 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1577 new_instr
->operands
[0] = cmp
->operands
[0];
1578 new_instr
->operands
[1] = cmp
->operands
[1];
1579 new_instr
->definitions
[0] = instr
->definitions
[0];
1581 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1582 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1584 instr
.reset(new_instr
);
1589 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1590 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1592 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1594 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1596 if (!instr
->operands
[0].isTemp())
1599 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1603 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1604 if (new_opcode
== aco_opcode::last_opcode
)
1607 if (cmp
->operands
[0].isTemp())
1608 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1609 if (cmp
->operands
[1].isTemp())
1610 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1611 decrease_uses(ctx
, cmp
);
1613 Instruction
*new_instr
;
1614 if (cmp
->isVOP3()) {
1615 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1616 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1617 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1618 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1619 new_vop3
->clamp
= cmp_vop3
->clamp
;
1620 new_vop3
->omod
= cmp_vop3
->omod
;
1621 new_vop3
->opsel
= cmp_vop3
->opsel
;
1622 new_instr
= new_vop3
;
1624 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1626 new_instr
->operands
[0] = cmp
->operands
[0];
1627 new_instr
->operands
[1] = cmp
->operands
[1];
1628 new_instr
->definitions
[0] = instr
->definitions
[0];
1630 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1631 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1633 instr
.reset(new_instr
);
1638 /* op1(op2(1, 2), 0) if swap = false
1639 * op1(0, op2(1, 2)) if swap = true */
1640 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1641 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1642 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1643 bool *op1_clamp
, uint8_t *op1_omod
,
1644 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1647 if (op1_instr
->opcode
!= op1
)
1650 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1651 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1653 if (fixed_to_exec(op2_instr
->operands
[0]) || fixed_to_exec(op2_instr
->operands
[1]))
1656 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1657 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1659 /* don't support inbetween clamp/omod */
1660 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1663 /* get operands and modifiers and check inbetween modifiers */
1664 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1665 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1668 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1669 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1673 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1674 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1677 if (inbetween_opsel
)
1678 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1679 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1683 shuffle
[shuffle_str
[0] - '0'] = 0;
1684 shuffle
[shuffle_str
[1] - '0'] = 1;
1685 shuffle
[shuffle_str
[2] - '0'] = 2;
1687 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1688 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1689 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1690 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1691 *opsel
|= 1 << shuffle
[0];
1693 for (unsigned i
= 0; i
< 2; i
++) {
1694 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1695 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1696 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1697 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1698 *opsel
|= 1 << shuffle
[i
+ 1];
1701 /* check operands */
1702 if (!check_vop3_operands(ctx
, 3, operands
))
1708 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1709 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1710 bool clamp
, unsigned omod
)
1712 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1713 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1714 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1715 new_instr
->clamp
= clamp
;
1716 new_instr
->omod
= omod
;
1717 new_instr
->opsel
= opsel
;
1718 new_instr
->operands
[0] = operands
[0];
1719 new_instr
->operands
[1] = operands
[1];
1720 new_instr
->operands
[2] = operands
[2];
1721 new_instr
->definitions
[0] = instr
->definitions
[0];
1722 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1724 instr
.reset(new_instr
);
1727 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1729 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1730 (label_omod_success
| label_clamp_success
);
1732 for (unsigned swap
= 0; swap
< 2; swap
++) {
1733 if (!((1 << swap
) & ops
))
1736 Operand operands
[3];
1737 bool neg
[3], abs
[3], clamp
;
1738 uint8_t opsel
= 0, omod
= 0;
1739 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1740 instr
.get(), swap
, shuffle
,
1741 operands
, neg
, abs
, &opsel
,
1742 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1743 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1744 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1745 if (omod_clamp
& label_omod_success
)
1746 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1747 if (omod_clamp
& label_clamp_success
)
1748 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1755 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
1757 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
1760 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1761 (label_omod_success
| label_clamp_success
);
1763 /* min(-max(a, b), c) -> min3(-a, -b, c) *
1764 * max(-min(a, b), c) -> max3(-a, -b, c) */
1765 for (unsigned swap
= 0; swap
< 2; swap
++) {
1766 Operand operands
[3];
1767 bool neg
[3], abs
[3], clamp
;
1768 uint8_t opsel
= 0, omod
= 0;
1770 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
1771 instr
.get(), swap
, "012",
1772 operands
, neg
, abs
, &opsel
,
1773 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
1775 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1778 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1779 if (omod_clamp
& label_omod_success
)
1780 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1781 if (omod_clamp
& label_clamp_success
)
1782 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1789 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1790 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1791 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1792 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1793 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1794 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1795 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1798 if (!instr
->operands
[0].isTemp())
1800 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1803 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1806 switch (op2_instr
->opcode
) {
1807 case aco_opcode::s_and_b32
:
1808 case aco_opcode::s_or_b32
:
1809 case aco_opcode::s_xor_b32
:
1810 case aco_opcode::s_and_b64
:
1811 case aco_opcode::s_or_b64
:
1812 case aco_opcode::s_xor_b64
:
1818 /* create instruction */
1819 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1820 std::swap(instr
->definitions
[1], op2_instr
->definitions
[1]);
1821 ctx
.uses
[instr
->operands
[0].tempId()]--;
1822 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1824 switch (op2_instr
->opcode
) {
1825 case aco_opcode::s_and_b32
:
1826 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1828 case aco_opcode::s_or_b32
:
1829 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1831 case aco_opcode::s_xor_b32
:
1832 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1834 case aco_opcode::s_and_b64
:
1835 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1837 case aco_opcode::s_or_b64
:
1838 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1840 case aco_opcode::s_xor_b64
:
1841 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1850 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1851 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1852 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1853 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1854 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1856 if (instr
->definitions
[0].isTemp() && ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bool())
1859 for (unsigned i
= 0; i
< 2; i
++) {
1860 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1861 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1863 if (ctx
.uses
[op2_instr
->definitions
[1].tempId()] || fixed_to_exec(op2_instr
->operands
[0]))
1866 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1867 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1870 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1871 instr
->operands
[0] = instr
->operands
[!i
];
1872 instr
->operands
[1] = op2_instr
->operands
[0];
1873 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1875 switch (instr
->opcode
) {
1876 case aco_opcode::s_and_b32
:
1877 instr
->opcode
= aco_opcode::s_andn2_b32
;
1879 case aco_opcode::s_or_b32
:
1880 instr
->opcode
= aco_opcode::s_orn2_b32
;
1882 case aco_opcode::s_and_b64
:
1883 instr
->opcode
= aco_opcode::s_andn2_b64
;
1885 case aco_opcode::s_or_b64
:
1886 instr
->opcode
= aco_opcode::s_orn2_b64
;
1897 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1898 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1900 if (instr
->opcode
== aco_opcode::s_add_i32
&& ctx
.uses
[instr
->definitions
[1].tempId()])
1903 for (unsigned i
= 0; i
< 2; i
++) {
1904 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1905 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
||
1906 ctx
.uses
[op2_instr
->definitions
[1].tempId()])
1908 if (!op2_instr
->operands
[1].isConstant() || fixed_to_exec(op2_instr
->operands
[0]))
1911 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1912 if (shift
< 1 || shift
> 4)
1915 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1916 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1919 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1920 instr
->operands
[1] = instr
->operands
[!i
];
1921 instr
->operands
[0] = op2_instr
->operands
[0];
1922 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1924 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1925 aco_opcode::s_lshl2_add_u32
,
1926 aco_opcode::s_lshl3_add_u32
,
1927 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1934 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1937 #define MINMAX(type, gfx9) \
1938 case aco_opcode::v_min_##type:\
1939 case aco_opcode::v_max_##type:\
1940 case aco_opcode::v_med3_##type:\
1941 *min = aco_opcode::v_min_##type;\
1942 *max = aco_opcode::v_max_##type;\
1943 *med3 = aco_opcode::v_med3_##type;\
1944 *min3 = aco_opcode::v_min3_##type;\
1945 *max3 = aco_opcode::v_max3_##type;\
1946 *some_gfx9_only = gfx9;\
1960 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1961 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1962 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1963 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1965 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
1966 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
1967 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
1968 aco_opcode other_op
;
1969 if (instr
->opcode
== min
)
1971 else if (instr
->opcode
== max
)
1976 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1977 (label_omod_success
| label_clamp_success
);
1979 for (unsigned swap
= 0; swap
< 2; swap
++) {
1980 Operand operands
[3];
1981 bool neg
[3], abs
[3], clamp
;
1982 uint8_t opsel
= 0, omod
= 0;
1983 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1984 "012", operands
, neg
, abs
, &opsel
,
1985 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1986 int const0_idx
= -1, const1_idx
= -1;
1987 uint32_t const0
= 0, const1
= 0;
1988 for (int i
= 0; i
< 3; i
++) {
1990 if (operands
[i
].isConstant()) {
1991 val
= operands
[i
].constantValue();
1992 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
1993 val
= ctx
.info
[operands
[i
].tempId()].val
;
1997 if (const0_idx
>= 0) {
2005 if (const0_idx
< 0 || const1_idx
< 0)
2008 if (opsel
& (1 << const0_idx
))
2010 if (opsel
& (1 << const1_idx
))
2013 int lower_idx
= const0_idx
;
2015 case aco_opcode::v_min_f32
:
2016 case aco_opcode::v_min_f16
: {
2017 float const0_f
, const1_f
;
2018 if (min
== aco_opcode::v_min_f32
) {
2019 memcpy(&const0_f
, &const0
, 4);
2020 memcpy(&const1_f
, &const1
, 4);
2022 const0_f
= _mesa_half_to_float(const0
);
2023 const1_f
= _mesa_half_to_float(const1
);
2025 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
2026 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
2027 if (neg
[const0_idx
]) const0_f
= -const0_f
;
2028 if (neg
[const1_idx
]) const1_f
= -const1_f
;
2029 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
2032 case aco_opcode::v_min_u32
: {
2033 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
2036 case aco_opcode::v_min_u16
: {
2037 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
2040 case aco_opcode::v_min_i32
: {
2041 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
2042 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
2043 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2046 case aco_opcode::v_min_i16
: {
2047 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
2048 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
2049 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2055 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
2057 if (instr
->opcode
== min
) {
2058 if (upper_idx
!= 0 || lower_idx
== 0)
2061 if (upper_idx
== 0 || lower_idx
!= 0)
2065 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2066 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2067 if (omod_clamp
& label_omod_success
)
2068 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2069 if (omod_clamp
& label_clamp_success
)
2070 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2080 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2082 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2083 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2084 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2086 /* find candidates and create the set of sgprs already read */
2087 unsigned sgpr_ids
[2] = {0, 0};
2088 uint32_t operand_mask
= 0;
2089 bool has_literal
= false;
2090 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2091 if (instr
->operands
[i
].isLiteral())
2093 if (!instr
->operands
[i
].isTemp())
2095 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2096 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
2097 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
2099 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
2100 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
2101 operand_mask
|= 1u << i
;
2103 unsigned max_sgprs
= 1;
2104 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2109 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2111 /* keep on applying sgprs until there is nothing left to be done */
2112 while (operand_mask
) {
2113 uint32_t sgpr_idx
= 0;
2114 uint32_t sgpr_info_id
= 0;
2115 uint32_t mask
= operand_mask
;
2118 unsigned i
= u_bit_scan(&mask
);
2119 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2120 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
2122 sgpr_info_id
= instr
->operands
[i
].tempId();
2125 operand_mask
&= ~(1u << sgpr_idx
);
2127 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2128 * definitively beneficial.
2129 * TODO: this is too conservative because later the use count could be reduced to 1 */
2130 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2133 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2134 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2135 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2138 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2139 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2140 } else if (can_swap_operands(instr
)) {
2141 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2142 instr
->operands
[0] = Operand(sgpr
);
2143 /* swap bits using a 4-entry LUT */
2144 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2145 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2146 } else if (can_use_VOP3(ctx
, instr
)) {
2147 to_VOP3(ctx
, instr
);
2148 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2154 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2155 ctx
.uses
[sgpr_info_id
]--;
2156 ctx
.uses
[sgpr
.id()]++;
2160 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2162 /* check if we could apply omod on predecessor */
2163 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
2164 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2165 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2167 unsigned idx
= op0
? 0 : 1;
2168 /* omod was successfully applied */
2169 /* if the omod instruction is v_mad, we also have to change the original add */
2170 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2171 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2172 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2173 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2174 add_instr
->definitions
[0] = instr
->definitions
[0];
2177 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2178 /* check if we have an additional clamp modifier */
2179 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2180 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2181 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2182 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2184 /* change definition ssa-id of modified instruction */
2185 omod_instr
->definitions
[0] = instr
->definitions
[0];
2187 /* change the definition of instr to something unused, e.g. the original omod def */
2188 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2189 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2192 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2193 /* in all other cases, label this instruction as option for multiply-add */
2194 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2198 /* check if we could apply clamp on predecessor */
2199 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
2201 bool found_zero
= false, found_one
= false;
2202 for (unsigned i
= 0; i
< 3; i
++)
2204 if (instr
->operands
[i
].constantEquals(0))
2206 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
2211 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2212 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2213 /* clamp was successfully applied */
2214 /* if the clamp instruction is v_mad, we also have to change the original add */
2215 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2216 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2217 add_instr
->definitions
[0] = instr
->definitions
[0];
2219 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2220 /* change definition ssa-id of modified instruction */
2221 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2223 /* change the definition of instr to something unused, e.g. the original omod def */
2224 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2225 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2230 /* omod has no effect if denormals are enabled */
2231 bool can_use_omod
= block
.fp_mode
.denorm32
== 0;
2233 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2234 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2235 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2236 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2237 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2238 to_VOP3(ctx
, instr
);
2239 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2240 def_info
.set_omod_success(instr
.get());
2241 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2242 to_VOP3(ctx
, instr
);
2243 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2244 def_info
.set_omod_success(instr
.get());
2245 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2246 to_VOP3(ctx
, instr
);
2247 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2248 def_info
.set_omod_success(instr
.get());
2249 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2250 to_VOP3(ctx
, instr
);
2251 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2252 def_info
.set_clamp_success(instr
.get());
2259 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2260 // this would mean that we'd have to fix the instruction uses while value propagation
2262 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2264 if (instr
->definitions
.empty() || is_dead(ctx
.uses
, instr
.get()))
2267 if (instr
->isVALU()) {
2268 if (can_apply_sgprs(instr
))
2269 apply_sgprs(ctx
, instr
);
2270 if (apply_omod_clamp(ctx
, block
, instr
))
2274 if (ctx
.info
[instr
->definitions
[0].tempId()].is_vcc_hint()) {
2275 instr
->definitions
[0].setHint(vcc
);
2278 /* TODO: There are still some peephole optimizations that could be done:
2279 * - abs(a - b) -> s_absdiff_i32
2280 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2281 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2282 * These aren't probably too interesting though.
2283 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2284 * probably more useful than the previously mentioned optimizations.
2285 * The various comparison optimizations also currently only work with 32-bit
2288 /* neg(mul(a, b)) -> mul(neg(a), b) */
2289 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2290 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2292 if (!ctx
.info
[val
.id()].is_mul())
2295 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2297 if (mul_instr
->operands
[0].isLiteral())
2299 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2302 /* convert to mul(neg(a), b) */
2303 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2304 Definition def
= instr
->definitions
[0];
2305 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2306 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2307 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2308 instr
->operands
[0] = mul_instr
->operands
[0];
2309 instr
->operands
[1] = mul_instr
->operands
[1];
2310 instr
->definitions
[0] = def
;
2311 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2312 if (mul_instr
->isVOP3()) {
2313 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2314 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2315 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2316 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2317 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2318 new_mul
->omod
= mul
->omod
;
2320 new_mul
->neg
[0] ^= true;
2321 new_mul
->clamp
= false;
2323 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2326 /* combine mul+add -> mad */
2327 else if ((instr
->opcode
== aco_opcode::v_add_f32
||
2328 instr
->opcode
== aco_opcode::v_sub_f32
||
2329 instr
->opcode
== aco_opcode::v_subrev_f32
) &&
2330 block
.fp_mode
.denorm32
== 0 && !block
.fp_mode
.preserve_signed_zero_inf_nan32
) {
2331 //TODO: we could use fma instead when denormals are enabled if the NIR isn't marked as precise
2333 uint32_t uses_src0
= UINT32_MAX
;
2334 uint32_t uses_src1
= UINT32_MAX
;
2335 Instruction
* mul_instr
= nullptr;
2336 unsigned add_op_idx
;
2337 /* check if any of the operands is a multiplication */
2338 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2339 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2340 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2341 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2343 /* find the 'best' mul instruction to combine with the add */
2344 if (uses_src0
< uses_src1
) {
2345 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2347 } else if (uses_src1
< uses_src0
) {
2348 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2350 } else if (uses_src0
!= UINT32_MAX
) {
2351 /* tiebreaker: quite random what to pick */
2352 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2353 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2356 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2361 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2362 bool neg
[3] = {false, false, false};
2363 bool abs
[3] = {false, false, false};
2366 op
[0] = mul_instr
->operands
[0];
2367 op
[1] = mul_instr
->operands
[1];
2368 op
[2] = instr
->operands
[add_op_idx
];
2369 // TODO: would be better to check this before selecting a mul instr?
2370 if (!check_vop3_operands(ctx
, 3, op
))
2373 if (mul_instr
->isVOP3()) {
2374 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2375 neg
[0] = vop3
->neg
[0];
2376 neg
[1] = vop3
->neg
[1];
2377 abs
[0] = vop3
->abs
[0];
2378 abs
[1] = vop3
->abs
[1];
2379 /* we cannot use these modifiers between mul and add */
2380 if (vop3
->clamp
|| vop3
->omod
)
2384 /* convert to mad */
2385 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2386 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2388 ctx
.uses
[op
[0].tempId()]++;
2390 ctx
.uses
[op
[1].tempId()]++;
2393 if (instr
->isVOP3()) {
2394 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2395 neg
[2] = vop3
->neg
[add_op_idx
];
2396 abs
[2] = vop3
->abs
[add_op_idx
];
2398 clamp
= vop3
->clamp
;
2399 /* abs of the multiplication result */
2400 if (vop3
->abs
[1 - add_op_idx
]) {
2406 /* neg of the multiplication result */
2407 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2409 if (instr
->opcode
== aco_opcode::v_sub_f32
)
2410 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2411 else if (instr
->opcode
== aco_opcode::v_subrev_f32
)
2412 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2414 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2415 for (unsigned i
= 0; i
< 3; i
++)
2417 mad
->operands
[i
] = op
[i
];
2418 mad
->neg
[i
] = neg
[i
];
2419 mad
->abs
[i
] = abs
[i
];
2423 mad
->definitions
[0] = instr
->definitions
[0];
2425 /* mark this ssa_def to be re-checked for profitability and literals */
2426 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2427 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2428 instr
.reset(mad
.release());
2432 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2433 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2434 for (unsigned i
= 0; i
< 2; i
++) {
2435 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2436 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2437 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2438 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2439 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2441 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2442 new_instr
->operands
[0] = Operand(0u);
2443 new_instr
->operands
[1] = instr
->operands
[!i
];
2444 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2445 new_instr
->definitions
[0] = instr
->definitions
[0];
2446 instr
.reset(new_instr
.release());
2447 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2451 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2452 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2453 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2454 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2455 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2456 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2457 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2458 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2459 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2460 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2461 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2462 combine_salu_lshl_add(ctx
, instr
);
2463 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2464 combine_salu_not_bitwise(ctx
, instr
);
2465 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2466 if (combine_inverse_comparison(ctx
, instr
)) ;
2467 else combine_salu_not_bitwise(ctx
, instr
);
2468 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2469 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2470 if (combine_ordering_test(ctx
, instr
)) ;
2471 else if (combine_comparison_ordering(ctx
, instr
)) ;
2472 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2473 else combine_salu_n2(ctx
, instr
);
2475 aco_opcode min
, max
, min3
, max3
, med3
;
2476 bool some_gfx9_only
;
2477 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2478 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2479 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2480 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2485 bool to_uniform_bool_instr(opt_ctx
&ctx
, aco_ptr
<Instruction
> &instr
)
2487 switch (instr
->opcode
) {
2488 case aco_opcode::s_and_b32
:
2489 case aco_opcode::s_and_b64
:
2490 instr
->opcode
= aco_opcode::s_and_b32
;
2492 case aco_opcode::s_or_b32
:
2493 case aco_opcode::s_or_b64
:
2494 instr
->opcode
= aco_opcode::s_or_b32
;
2496 case aco_opcode::s_xor_b32
:
2497 case aco_opcode::s_xor_b64
:
2498 instr
->opcode
= aco_opcode::s_absdiff_i32
;
2501 /* Don't transform other instructions. They are very unlikely to appear here. */
2505 for (Operand
&op
: instr
->operands
) {
2506 ctx
.uses
[op
.tempId()]--;
2508 if (ctx
.info
[op
.tempId()].is_uniform_bool()) {
2509 /* Just use the uniform boolean temp. */
2510 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
2511 } else if (ctx
.info
[op
.tempId()].is_uniform_bitwise()) {
2512 /* Use the SCC definition of the predecessor instruction.
2513 * This allows the predecessor to get picked up by the same optimization (if it has no divergent users),
2514 * and it also makes sure that the current instruction will keep working even if the predecessor won't be transformed.
2516 Instruction
*pred_instr
= ctx
.info
[op
.tempId()].instr
;
2517 assert(pred_instr
->definitions
.size() >= 2);
2518 assert(pred_instr
->definitions
[1].isFixed() && pred_instr
->definitions
[1].physReg() == scc
);
2519 op
.setTemp(pred_instr
->definitions
[1].getTemp());
2521 unreachable("Invalid operand on uniform bitwise instruction.");
2524 ctx
.uses
[op
.tempId()]++;
2527 instr
->definitions
[0].setTemp(Temp(instr
->definitions
[0].tempId(), s1
));
2528 assert(instr
->operands
[0].regClass() == s1
);
2529 assert(instr
->operands
[1].regClass() == s1
);
2533 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2535 const uint32_t threshold
= 4;
2537 if (is_dead(ctx
.uses
, instr
.get())) {
2542 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2543 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2544 unsigned num_used
= 0;
2546 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2547 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2553 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2554 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2555 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2559 for (Operand
& vec_op
: vec
->operands
) {
2560 if (off
== idx
* instr
->definitions
[0].size()) {
2564 off
+= vec_op
.size();
2566 if (off
!= instr
->operands
[0].size()) {
2567 ctx
.uses
[instr
->operands
[0].tempId()]--;
2568 for (Operand
& vec_op
: vec
->operands
) {
2569 if (vec_op
.isTemp())
2570 ctx
.uses
[vec_op
.tempId()]--;
2573 ctx
.uses
[op
.tempId()]++;
2575 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2576 extract
->operands
[0] = op
;
2577 extract
->definitions
[0] = instr
->definitions
[idx
];
2578 instr
.reset(extract
.release());
2584 if (!done
&& num_used
== 1) {
2585 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2586 extract
->operands
[0] = instr
->operands
[0];
2587 extract
->operands
[1] = Operand((uint32_t) idx
);
2588 extract
->definitions
[0] = instr
->definitions
[idx
];
2589 instr
.reset(extract
.release());
2593 mad_info
* mad_info
= NULL
;
2594 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2595 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2596 /* re-check mad instructions */
2597 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2598 ctx
.uses
[mad_info
->mul_temp_id
]++;
2599 if (instr
->operands
[0].isTemp())
2600 ctx
.uses
[instr
->operands
[0].tempId()]--;
2601 if (instr
->operands
[1].isTemp())
2602 ctx
.uses
[instr
->operands
[1].tempId()]--;
2603 instr
.swap(mad_info
->add_instr
);
2606 /* check literals */
2607 else if (!instr
->usesModifiers()) {
2608 bool sgpr_used
= false;
2609 uint32_t literal_idx
= 0;
2610 uint32_t literal_uses
= UINT32_MAX
;
2611 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2613 if (instr
->operands
[i
].isConstant() && i
> 0) {
2614 literal_uses
= UINT32_MAX
;
2617 if (!instr
->operands
[i
].isTemp())
2619 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2620 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2621 if (!sgpr_used
&& ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2622 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2625 literal_uses
= UINT32_MAX
;
2628 /* don't break because we still need to check constants */
2629 } else if (!sgpr_used
&&
2630 ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2631 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2632 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2637 /* Limit the number of literals to apply to not increase the code
2638 * size too much, but always apply literals for v_mad->v_madak
2639 * because both instructions are 64-bit and this doesn't increase
2641 * TODO: try to apply the literals earlier to lower the number of
2642 * uses below threshold
2644 if (literal_uses
< threshold
|| literal_idx
== 2) {
2645 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2646 mad_info
->check_literal
= true;
2647 mad_info
->literal_idx
= literal_idx
;
2653 /* Mark SCC needed, so the uniform boolean transformation won't swap the definitions when it isn't beneficial */
2654 if (instr
->format
== Format::PSEUDO_BRANCH
&&
2655 instr
->operands
.size() &&
2656 instr
->operands
[0].isTemp()) {
2657 ctx
.info
[instr
->operands
[0].tempId()].set_scc_needed();
2659 } else if ((instr
->opcode
== aco_opcode::s_cselect_b64
||
2660 instr
->opcode
== aco_opcode::s_cselect_b32
) &&
2661 instr
->operands
[2].isTemp()) {
2662 ctx
.info
[instr
->operands
[2].tempId()].set_scc_needed();
2665 /* check for literals */
2666 if (!instr
->isSALU() && !instr
->isVALU())
2669 /* Transform uniform bitwise boolean operations to 32-bit when there are no divergent uses. */
2670 if (instr
->definitions
.size() &&
2671 ctx
.uses
[instr
->definitions
[0].tempId()] == 0 &&
2672 ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bitwise()) {
2673 bool transform_done
= to_uniform_bool_instr(ctx
, instr
);
2675 if (transform_done
&& !ctx
.info
[instr
->definitions
[1].tempId()].is_scc_needed()) {
2676 /* Swap the two definition IDs in order to avoid overusing the SCC. This reduces extra moves generated by RA. */
2677 uint32_t def0_id
= instr
->definitions
[0].getTemp().id();
2678 uint32_t def1_id
= instr
->definitions
[1].getTemp().id();
2679 instr
->definitions
[0].setTemp(Temp(def1_id
, s1
));
2680 instr
->definitions
[1].setTemp(Temp(def0_id
, s1
));
2686 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
2687 return; /* some encodings can't ever take literals */
2689 /* we do not apply the literals yet as we don't know if it is profitable */
2690 Operand
current_literal(s1
);
2692 unsigned literal_id
= 0;
2693 unsigned literal_uses
= UINT32_MAX
;
2694 Operand
literal(s1
);
2695 unsigned num_operands
= 1;
2696 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
2697 num_operands
= instr
->operands
.size();
2698 /* catch VOP2 with a 3rd SGPR operand (e.g. v_cndmask_b32, v_addc_co_u32) */
2699 else if (instr
->isVALU() && instr
->operands
.size() >= 3)
2702 unsigned sgpr_ids
[2] = {0, 0};
2703 bool is_literal_sgpr
= false;
2706 /* choose a literal to apply */
2707 for (unsigned i
= 0; i
< num_operands
; i
++) {
2708 Operand op
= instr
->operands
[i
];
2710 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
2711 op
.tempId() != sgpr_ids
[0])
2712 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
2714 if (op
.isLiteral()) {
2715 current_literal
= op
;
2717 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal()) {
2721 if (!alu_can_accept_constant(instr
->opcode
, i
))
2724 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
2725 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
2727 literal
= Operand(ctx
.info
[op
.tempId()].val
);
2728 literal_uses
= ctx
.uses
[op
.tempId()];
2729 literal_id
= op
.tempId();
2732 mask
|= (op
.tempId() == literal_id
) << i
;
2736 /* don't go over the constant bus limit */
2737 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2738 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2739 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2740 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
2741 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2742 const_bus_limit
= 2;
2744 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2745 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
2748 if (literal_id
&& literal_uses
< threshold
&&
2749 (current_literal
.isUndefined() ||
2750 (current_literal
.size() == literal
.size() &&
2751 current_literal
.constantValue() == literal
.constantValue()))) {
2752 /* mark the literal to be applied */
2754 unsigned i
= u_bit_scan(&mask
);
2755 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
2756 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2762 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2764 /* Cleanup Dead Instructions */
2768 /* apply literals on MAD */
2769 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2770 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2771 if (info
->check_literal
&&
2772 (ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0 || info
->literal_idx
== 2)) {
2773 aco_ptr
<Instruction
> new_mad
;
2774 if (info
->literal_idx
== 2) { /* add literal -> madak */
2775 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2776 new_mad
->operands
[0] = instr
->operands
[0];
2777 new_mad
->operands
[1] = instr
->operands
[1];
2778 } else { /* mul literal -> madmk */
2779 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2780 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2781 new_mad
->operands
[1] = instr
->operands
[2];
2783 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2784 new_mad
->definitions
[0] = instr
->definitions
[0];
2785 ctx
.instructions
.emplace_back(std::move(new_mad
));
2790 /* apply literals on other SALU/VALU */
2791 if (instr
->isSALU() || instr
->isVALU()) {
2792 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2793 Operand op
= instr
->operands
[i
];
2794 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal() && ctx
.uses
[op
.tempId()] == 0) {
2795 Operand
literal(ctx
.info
[op
.tempId()].val
);
2796 if (instr
->isVALU() && i
> 0)
2797 to_VOP3(ctx
, instr
);
2798 instr
->operands
[i
] = literal
;
2803 ctx
.instructions
.emplace_back(std::move(instr
));
2807 void optimize(Program
* program
)
2810 ctx
.program
= program
;
2811 std::vector
<ssa_info
> info(program
->peekAllocationId());
2812 ctx
.info
= info
.data();
2814 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2815 for (Block
& block
: program
->blocks
) {
2816 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2817 label_instruction(ctx
, block
, instr
);
2820 ctx
.uses
= std::move(dead_code_analysis(program
));
2822 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2823 for (Block
& block
: program
->blocks
) {
2824 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2825 combine_instruction(ctx
, block
, instr
);
2828 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2829 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2830 Block
* block
= &(*it
);
2831 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2832 select_instruction(ctx
, *it
);
2835 /* 4. Add literals to instructions */
2836 for (Block
& block
: program
->blocks
) {
2837 ctx
.instructions
.clear();
2838 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2839 apply_literals(ctx
, instr
);
2840 block
.instructions
.swap(ctx
.instructions
);