2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant
= 1 << 1,
69 label_literal
= 1 << 6,
73 label_omod5
= 1 << 10,
74 label_omod_success
= 1 << 11,
75 label_clamp
= 1 << 12,
76 label_clamp_success
= 1 << 13,
77 label_undefined
= 1 << 14,
80 label_add_sub
= 1 << 17,
81 label_bitwise
= 1 << 18,
82 label_minmax
= 1 << 19,
84 label_uniform_bool
= 1 << 21,
85 label_constant_64bit
= 1 << 22,
86 label_uniform_bitwise
= 1 << 23,
87 label_scc_invert
= 1 << 24,
88 label_vcc_hint
= 1 << 25,
89 label_scc_needed
= 1 << 26,
92 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
|
93 label_add_sub
| label_bitwise
| label_uniform_bitwise
| label_minmax
| label_fcmp
;
94 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
|
95 label_omod2
| label_omod4
| label_omod5
| label_clamp
| label_scc_invert
;
96 static constexpr uint32_t val_labels
= label_constant
| label_constant_64bit
| label_literal
| label_mad
;
106 void add_label(Label new_label
)
108 /* Since all labels which use "instr" use it for the same thing
109 * (indicating the defining instruction), there is no need to clear
110 * any other instr labels. */
111 if (new_label
& instr_labels
)
112 label
&= ~temp_labels
; /* instr and temp alias */
114 if (new_label
& temp_labels
) {
115 label
&= ~temp_labels
;
116 label
&= ~instr_labels
; /* instr and temp alias */
119 if (new_label
& val_labels
)
120 label
&= ~val_labels
;
125 void set_vec(Instruction
* vec
)
127 add_label(label_vec
);
133 return label
& label_vec
;
136 void set_constant(uint32_t constant
)
138 add_label(label_constant
);
144 return label
& label_constant
;
147 void set_constant_64bit(uint32_t constant
)
149 add_label(label_constant_64bit
);
153 bool is_constant_64bit()
155 return label
& label_constant_64bit
;
158 void set_abs(Temp abs_temp
)
160 add_label(label_abs
);
166 return label
& label_abs
;
169 void set_neg(Temp neg_temp
)
171 add_label(label_neg
);
177 return label
& label_neg
;
180 void set_neg_abs(Temp neg_abs_temp
)
182 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
186 void set_mul(Instruction
* mul
)
188 add_label(label_mul
);
194 return label
& label_mul
;
197 void set_temp(Temp tmp
)
199 add_label(label_temp
);
205 return label
& label_temp
;
208 void set_literal(uint32_t lit
)
210 add_label(label_literal
);
216 return label
& label_literal
;
219 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
221 add_label(label_mad
);
228 return label
& label_mad
;
231 void set_omod2(Temp def
)
233 add_label(label_omod2
);
239 return label
& label_omod2
;
242 void set_omod4(Temp def
)
244 add_label(label_omod4
);
250 return label
& label_omod4
;
253 void set_omod5(Temp def
)
255 add_label(label_omod5
);
261 return label
& label_omod5
;
264 void set_omod_success(Instruction
* omod_instr
)
266 add_label(label_omod_success
);
270 bool is_omod_success()
272 return label
& label_omod_success
;
275 void set_clamp(Temp def
)
277 add_label(label_clamp
);
283 return label
& label_clamp
;
286 void set_clamp_success(Instruction
* clamp_instr
)
288 add_label(label_clamp_success
);
292 bool is_clamp_success()
294 return label
& label_clamp_success
;
299 add_label(label_undefined
);
304 return label
& label_undefined
;
307 void set_vcc(Temp vcc
)
309 add_label(label_vcc
);
315 return label
& label_vcc
;
318 bool is_constant_or_literal()
320 return is_constant() || is_literal();
323 void set_b2f(Temp val
)
325 add_label(label_b2f
);
331 return label
& label_b2f
;
334 void set_add_sub(Instruction
*add_sub_instr
)
336 add_label(label_add_sub
);
337 instr
= add_sub_instr
;
342 return label
& label_add_sub
;
345 void set_bitwise(Instruction
*bitwise_instr
)
347 add_label(label_bitwise
);
348 instr
= bitwise_instr
;
353 return label
& label_bitwise
;
356 void set_uniform_bitwise()
358 add_label(label_uniform_bitwise
);
361 bool is_uniform_bitwise()
363 return label
& label_uniform_bitwise
;
366 void set_minmax(Instruction
*minmax_instr
)
368 add_label(label_minmax
);
369 instr
= minmax_instr
;
374 return label
& label_minmax
;
377 void set_fcmp(Instruction
*fcmp_instr
)
379 add_label(label_fcmp
);
385 return label
& label_fcmp
;
388 void set_scc_needed()
390 add_label(label_scc_needed
);
395 return label
& label_scc_needed
;
398 void set_scc_invert(Temp scc_inv
)
400 add_label(label_scc_invert
);
406 return label
& label_scc_invert
;
409 void set_uniform_bool(Temp uniform_bool
)
411 add_label(label_uniform_bool
);
415 bool is_uniform_bool()
417 return label
& label_uniform_bool
;
422 add_label(label_vcc_hint
);
427 return label
& label_vcc_hint
;
433 std::vector
<aco_ptr
<Instruction
>> instructions
;
435 std::pair
<uint32_t,Temp
> last_literal
;
436 std::vector
<mad_info
> mad_infos
;
437 std::vector
<uint16_t> uses
;
440 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
442 if (instr
->operands
[0].isConstant() ||
443 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
446 switch (instr
->opcode
) {
447 case aco_opcode::v_add_f32
:
448 case aco_opcode::v_mul_f32
:
449 case aco_opcode::v_or_b32
:
450 case aco_opcode::v_and_b32
:
451 case aco_opcode::v_xor_b32
:
452 case aco_opcode::v_max_f32
:
453 case aco_opcode::v_min_f32
:
454 case aco_opcode::v_max_i32
:
455 case aco_opcode::v_min_i32
:
456 case aco_opcode::v_max_u32
:
457 case aco_opcode::v_min_u32
:
458 case aco_opcode::v_cmp_eq_f32
:
459 case aco_opcode::v_cmp_lg_f32
:
461 case aco_opcode::v_sub_f32
:
462 instr
->opcode
= aco_opcode::v_subrev_f32
;
464 case aco_opcode::v_cmp_lt_f32
:
465 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
467 case aco_opcode::v_cmp_ge_f32
:
468 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
470 case aco_opcode::v_cmp_lt_i32
:
471 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
478 bool can_use_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
483 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
486 if (instr
->isDPP() || instr
->isSDWA())
489 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
490 instr
->opcode
!= aco_opcode::v_madak_f32
&&
491 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
492 instr
->opcode
!= aco_opcode::v_madak_f16
&&
493 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
494 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
495 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
496 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
497 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
498 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
499 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
502 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
504 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
505 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
506 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
507 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
508 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
511 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
516 aco_ptr
<Instruction
> tmp
= std::move(instr
);
517 Format format
= asVOP3(tmp
->format
);
518 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
519 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
520 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
521 instr
->definitions
[i
] = tmp
->definitions
[i
];
522 if (instr
->definitions
[i
].isTemp()) {
523 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
524 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
525 info
.instr
= instr
.get();
530 /* only covers special cases */
531 bool alu_can_accept_constant(aco_opcode opcode
, unsigned operand
)
534 case aco_opcode::v_interp_p2_f32
:
535 case aco_opcode::v_mac_f32
:
536 case aco_opcode::v_writelane_b32
:
537 case aco_opcode::v_writelane_b32_e64
:
538 case aco_opcode::v_cndmask_b32
:
540 case aco_opcode::s_addk_i32
:
541 case aco_opcode::s_mulk_i32
:
542 case aco_opcode::p_wqm
:
543 case aco_opcode::p_extract_vector
:
544 case aco_opcode::p_split_vector
:
545 case aco_opcode::v_readlane_b32
:
546 case aco_opcode::v_readlane_b32_e64
:
547 case aco_opcode::v_readfirstlane_b32
:
554 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
556 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
557 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
562 /* check constant bus and literal limitations */
563 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
565 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
566 Operand
literal32(s1
);
567 Operand
literal64(s2
);
568 unsigned num_sgprs
= 0;
569 unsigned sgpr
[] = {0, 0};
571 for (unsigned i
= 0; i
< num_operands
; i
++) {
572 Operand op
= operands
[i
];
574 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
575 /* two reads of the same SGPR count as 1 to the limit */
576 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
578 sgpr
[num_sgprs
++] = op
.tempId();
583 } else if (op
.isLiteral()) {
584 if (ctx
.program
->chip_class
< GFX10
)
587 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
589 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
592 /* Any number of 32-bit literals counts as only 1 to the limit. Same
593 * (but separately) for 64-bit literals. */
594 if (op
.size() == 1 && literal32
.isUndefined()) {
597 } else if (op
.size() == 2 && literal64
.isUndefined()) {
610 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
612 Operand op
= instr
->operands
[op_index
];
616 Temp tmp
= op
.getTemp();
617 if (!ctx
.info
[tmp
.id()].is_add_sub())
620 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
622 switch (add_instr
->opcode
) {
623 case aco_opcode::v_add_u32
:
624 case aco_opcode::v_add_co_u32
:
625 case aco_opcode::s_add_i32
:
626 case aco_opcode::s_add_u32
:
632 if (add_instr
->usesModifiers())
635 for (unsigned i
= 0; i
< 2; i
++) {
636 if (add_instr
->operands
[i
].isConstant()) {
637 *offset
= add_instr
->operands
[i
].constantValue();
638 } else if (add_instr
->operands
[i
].isTemp() &&
639 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
640 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
644 if (!add_instr
->operands
[!i
].isTemp())
647 uint32_t offset2
= 0;
648 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
651 *base
= add_instr
->operands
[!i
].getTemp();
659 Operand
get_constant_op(opt_ctx
&ctx
, uint32_t val
, bool is64bit
= false)
661 // TODO: this functions shouldn't be needed if we store Operand instead of value.
662 Operand
op(val
, is64bit
);
663 if (val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
664 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
668 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
670 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
671 ASSERTED
bool all_const
= false;
672 for (Operand
& op
: instr
->operands
)
673 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
674 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
677 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
679 if (!instr
->operands
[i
].isTemp())
682 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
683 /* propagate undef */
684 if (info
.is_undefined() && is_phi(instr
))
685 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
686 /* propagate reg->reg of same type */
687 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
688 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
689 info
= ctx
.info
[info
.temp
.id()];
692 /* SALU / PSEUDO: propagate inline constants */
693 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
694 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
695 instr
->operands
[i
].setTemp(info
.temp
);
696 info
= ctx
.info
[info
.temp
.id()];
697 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
698 /* propagate vgpr if it can take it */
699 switch (instr
->opcode
) {
700 case aco_opcode::p_create_vector
:
701 case aco_opcode::p_split_vector
:
702 case aco_opcode::p_extract_vector
:
703 case aco_opcode::p_phi
: {
704 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
705 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
707 instr
->operands
[i
] = Operand(info
.temp
);
708 info
= ctx
.info
[info
.temp
.id()];
716 if ((info
.is_constant() || info
.is_constant_64bit() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) &&
717 !instr
->operands
[i
].isFixed() && alu_can_accept_constant(instr
->opcode
, i
)) {
718 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
723 /* VALU: propagate neg, abs & inline constants */
724 else if (instr
->isVALU()) {
725 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
726 instr
->operands
[i
].setTemp(info
.temp
);
727 info
= ctx
.info
[info
.temp
.id()];
729 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
732 instr
->operands
[i
] = Operand(info
.temp
);
734 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
736 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
738 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
739 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
740 instr
->operands
[i
].setTemp(info
.temp
);
742 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
745 instr
->operands
[i
].setTemp(info
.temp
);
747 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
749 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
752 if ((info
.is_constant() || info
.is_constant_64bit()) && alu_can_accept_constant(instr
->opcode
, i
)) {
753 Operand op
= get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
754 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
755 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
756 instr
->operands
[i
] = op
;
758 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
759 instr
->operands
[i
] = instr
->operands
[0];
760 instr
->operands
[0] = op
;
762 } else if (can_use_VOP3(ctx
, instr
)) {
764 instr
->operands
[i
] = op
;
770 /* MUBUF: propagate constants and combine additions */
771 else if (instr
->format
== Format::MUBUF
) {
772 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
775 while (info
.is_temp())
776 info
= ctx
.info
[info
.temp
.id()];
778 if (mubuf
->offen
&& i
== 1 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
779 assert(!mubuf
->idxen
);
780 instr
->operands
[1] = Operand(v1
);
781 mubuf
->offset
+= info
.val
;
782 mubuf
->offen
= false;
784 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
785 instr
->operands
[2] = Operand((uint32_t) 0);
786 mubuf
->offset
+= info
.val
;
788 } else if (mubuf
->offen
&& i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
789 assert(!mubuf
->idxen
);
790 instr
->operands
[1].setTemp(base
);
791 mubuf
->offset
+= offset
;
793 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
794 instr
->operands
[i
].setTemp(base
);
795 mubuf
->offset
+= offset
;
800 /* DS: combine additions */
801 else if (instr
->format
== Format::DS
) {
803 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
806 bool has_usable_ds_offset
= ctx
.program
->chip_class
>= GFX7
;
807 if (has_usable_ds_offset
&&
808 i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) &&
809 base
.regClass() == instr
->operands
[i
].regClass() &&
810 instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
811 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
812 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
813 if (offset
% 4 == 0 &&
814 ds
->offset0
+ (offset
>> 2) <= 255 &&
815 ds
->offset1
+ (offset
>> 2) <= 255) {
816 instr
->operands
[i
].setTemp(base
);
817 ds
->offset0
+= offset
>> 2;
818 ds
->offset1
+= offset
>> 2;
821 if (ds
->offset0
+ offset
<= 65535) {
822 instr
->operands
[i
].setTemp(base
);
823 ds
->offset0
+= offset
;
829 /* SMEM: propagate constants and combine additions */
830 else if (instr
->format
== Format::SMEM
) {
832 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
835 if (i
== 1 && info
.is_constant_or_literal() &&
836 ((ctx
.program
->chip_class
== GFX6
&& info
.val
<= 0x3FF) ||
837 (ctx
.program
->chip_class
== GFX7
&& info
.val
<= 0xFFFFFFFF) ||
838 (ctx
.program
->chip_class
>= GFX8
&& info
.val
<= 0xFFFFF))) {
839 instr
->operands
[i
] = Operand(info
.val
);
841 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
842 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
844 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
845 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
849 smem
->operands
[1] = Operand(offset
);
850 smem
->operands
.back() = Operand(base
);
852 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
853 new_instr
->operands
[0] = smem
->operands
[0];
854 new_instr
->operands
[1] = Operand(offset
);
855 if (smem
->definitions
.empty())
856 new_instr
->operands
[2] = smem
->operands
[2];
857 new_instr
->operands
.back() = Operand(base
);
858 if (!smem
->definitions
.empty())
859 new_instr
->definitions
[0] = smem
->definitions
[0];
860 new_instr
->can_reorder
= smem
->can_reorder
;
861 new_instr
->barrier
= smem
->barrier
;
862 instr
.reset(new_instr
);
863 smem
= static_cast<SMEM_instruction
*>(instr
.get());
869 else if (instr
->format
== Format::PSEUDO_BRANCH
) {
870 if (ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
871 /* Flip the branch instruction to get rid of the scc_invert instruction */
872 instr
->opcode
= instr
->opcode
== aco_opcode::p_cbranch_z
? aco_opcode::p_cbranch_nz
: aco_opcode::p_cbranch_z
;
873 instr
->operands
[0].setTemp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
878 /* if this instruction doesn't define anything, return */
879 if (instr
->definitions
.empty())
882 switch (instr
->opcode
) {
883 case aco_opcode::p_create_vector
: {
884 unsigned num_ops
= instr
->operands
.size();
885 for (const Operand
& op
: instr
->operands
) {
886 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
887 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
889 if (num_ops
!= instr
->operands
.size()) {
890 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
891 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
892 instr
->definitions
[0] = old_vec
->definitions
[0];
894 for (Operand
& old_op
: old_vec
->operands
) {
895 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
896 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
897 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
898 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
899 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
900 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
901 instr
->operands
[k
++] = op
;
904 instr
->operands
[k
++] = old_op
;
907 assert(k
== num_ops
);
909 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
910 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
911 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
912 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
915 case aco_opcode::p_split_vector
: {
916 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
918 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
919 assert(instr
->definitions
.size() == vec
->operands
.size());
920 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
921 Operand vec_op
= vec
->operands
[i
];
922 if (vec_op
.isConstant()) {
923 if (vec_op
.isLiteral())
924 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
925 else if (vec_op
.size() == 1)
926 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
927 else if (vec_op
.size() == 2)
928 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant_64bit(vec_op
.constantValue());
930 assert(vec_op
.isTemp());
931 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
936 case aco_opcode::p_extract_vector
: { /* mov */
937 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
939 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
940 if (vec
->definitions
[0].getTemp().size() == vec
->operands
.size() && /* TODO: what about 64bit or other combinations? */
941 vec
->operands
[0].size() == instr
->definitions
[0].size()) {
943 /* convert this extract into a mov instruction */
944 Operand vec_op
= vec
->operands
[instr
->operands
[1].constantValue()];
945 bool is_vgpr
= instr
->definitions
[0].getTemp().type() == RegType::vgpr
;
946 aco_opcode opcode
= is_vgpr
? aco_opcode::v_mov_b32
: aco_opcode::s_mov_b32
;
947 Format format
= is_vgpr
? Format::VOP1
: Format::SOP1
;
948 instr
->opcode
= opcode
;
949 instr
->format
= format
;
950 while (instr
->operands
.size() > 1)
951 instr
->operands
.pop_back();
952 instr
->operands
[0] = vec_op
;
954 if (vec_op
.isConstant()) {
955 if (vec_op
.isLiteral())
956 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(vec_op
.constantValue());
957 else if (vec_op
.size() == 1)
958 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(vec_op
.constantValue());
959 else if (vec_op
.size() == 2)
960 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(vec_op
.constantValue());
963 assert(vec_op
.isTemp());
964 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vec_op
.getTemp());
969 case aco_opcode::s_mov_b32
: /* propagate */
970 case aco_opcode::s_mov_b64
:
971 case aco_opcode::v_mov_b32
:
972 case aco_opcode::p_as_uniform
:
973 if (instr
->definitions
[0].isFixed()) {
974 /* don't copy-propagate copies into fixed registers */
975 } else if (instr
->usesModifiers()) {
977 } else if (instr
->operands
[0].isConstant()) {
978 if (instr
->operands
[0].isLiteral())
979 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
980 else if (instr
->operands
[0].size() == 1)
981 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
982 else if (instr
->operands
[0].size() == 2)
983 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(instr
->operands
[0].constantValue());
984 } else if (instr
->operands
[0].isTemp()) {
985 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
987 assert(instr
->operands
[0].isFixed());
990 case aco_opcode::p_is_helper
:
991 if (!ctx
.program
->needs_wqm
)
992 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
994 case aco_opcode::s_movk_i32
: {
995 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
996 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
997 if (v
<= 64 || v
>= 0xfffffff0)
998 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1000 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1003 case aco_opcode::v_bfrev_b32
:
1004 case aco_opcode::s_brev_b32
: {
1005 if (instr
->operands
[0].isConstant()) {
1006 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
1007 if (v
<= 64 || v
>= 0xfffffff0)
1008 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1010 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1014 case aco_opcode::s_bfm_b32
: {
1015 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
1016 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
1017 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
1018 uint32_t v
= ((1u << size
) - 1u) << start
;
1019 if (v
<= 64 || v
>= 0xfffffff0)
1020 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1022 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1025 case aco_opcode::v_mul_f32
: { /* omod */
1026 /* TODO: try to move the negate/abs modifier to the consumer instead */
1027 if (instr
->usesModifiers())
1030 for (unsigned i
= 0; i
< 2; i
++) {
1031 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
1032 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
1033 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
1034 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
1035 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
1036 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
1037 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
1038 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000 &&
1039 !block
.fp_mode
.must_flush_denorms32
) { /* 1.0 */
1040 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
1049 case aco_opcode::v_and_b32
: /* abs */
1050 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x7FFFFFFF) &&
1051 instr
->operands
[1].isTemp() && instr
->operands
[1].getTemp().type() == RegType::vgpr
)
1052 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
1054 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1056 case aco_opcode::v_xor_b32
: { /* neg */
1057 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
1058 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
1059 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1060 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
1061 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
1062 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1063 instr
->opcode
= aco_opcode::v_or_b32
;
1064 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
1066 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
1070 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1074 case aco_opcode::v_med3_f32
: { /* clamp */
1075 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1076 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1077 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1078 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1082 bool found_zero
= false, found_one
= false;
1083 for (unsigned i
= 0; i
< 3; i
++)
1085 if (instr
->operands
[i
].constantEquals(0))
1087 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1092 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1093 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1097 case aco_opcode::v_cndmask_b32
:
1098 if (instr
->operands
[0].constantEquals(0) &&
1099 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
1100 instr
->operands
[2].isTemp())
1101 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1102 else if (instr
->operands
[0].constantEquals(0) &&
1103 instr
->operands
[1].constantEquals(0x3f800000u
) &&
1104 instr
->operands
[2].isTemp())
1105 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1107 ctx
.info
[instr
->operands
[2].tempId()].set_vcc_hint();
1109 case aco_opcode::v_cmp_lg_u32
:
1110 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1111 instr
->operands
[0].constantEquals(0) &&
1112 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1113 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1115 case aco_opcode::p_phi
:
1116 case aco_opcode::p_linear_phi
: {
1117 /* lower_bool_phis() can create phis like this */
1118 bool all_same_temp
= instr
->operands
[0].isTemp();
1119 /* this check is needed when moving uniform loop counters out of a divergent loop */
1121 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1122 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1123 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1124 all_same_temp
= false;
1126 if (all_same_temp
) {
1127 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1129 bool all_undef
= instr
->operands
[0].isUndefined();
1130 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1131 if (!instr
->operands
[i
].isUndefined())
1135 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1139 case aco_opcode::v_add_u32
:
1140 case aco_opcode::v_add_co_u32
:
1141 case aco_opcode::s_add_i32
:
1142 case aco_opcode::s_add_u32
:
1143 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1145 case aco_opcode::s_not_b32
:
1146 case aco_opcode::s_not_b64
:
1147 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1148 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1149 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1150 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1151 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1152 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1154 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1156 case aco_opcode::s_and_b32
:
1157 case aco_opcode::s_and_b64
:
1158 if (instr
->operands
[1].isFixed() && instr
->operands
[1].physReg() == exec
&& instr
->operands
[0].isTemp()) {
1159 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1160 /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
1161 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1162 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1164 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1165 /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
1166 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1167 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1172 case aco_opcode::s_or_b32
:
1173 case aco_opcode::s_or_b64
:
1174 case aco_opcode::s_xor_b32
:
1175 case aco_opcode::s_xor_b64
:
1176 if (std::all_of(instr
->operands
.begin(), instr
->operands
.end(), [&ctx
](const Operand
& op
) {
1177 return op
.isTemp() && (ctx
.info
[op
.tempId()].is_uniform_bool() || ctx
.info
[op
.tempId()].is_uniform_bitwise());
1179 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1182 case aco_opcode::s_lshl_b32
:
1183 case aco_opcode::v_or_b32
:
1184 case aco_opcode::v_lshlrev_b32
:
1185 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1187 case aco_opcode::v_min_f32
:
1188 case aco_opcode::v_min_f16
:
1189 case aco_opcode::v_min_u32
:
1190 case aco_opcode::v_min_i32
:
1191 case aco_opcode::v_min_u16
:
1192 case aco_opcode::v_min_i16
:
1193 case aco_opcode::v_max_f32
:
1194 case aco_opcode::v_max_f16
:
1195 case aco_opcode::v_max_u32
:
1196 case aco_opcode::v_max_i32
:
1197 case aco_opcode::v_max_u16
:
1198 case aco_opcode::v_max_i16
:
1199 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1201 case aco_opcode::v_cmp_lt_f32
:
1202 case aco_opcode::v_cmp_eq_f32
:
1203 case aco_opcode::v_cmp_le_f32
:
1204 case aco_opcode::v_cmp_gt_f32
:
1205 case aco_opcode::v_cmp_lg_f32
:
1206 case aco_opcode::v_cmp_ge_f32
:
1207 case aco_opcode::v_cmp_o_f32
:
1208 case aco_opcode::v_cmp_u_f32
:
1209 case aco_opcode::v_cmp_nge_f32
:
1210 case aco_opcode::v_cmp_nlg_f32
:
1211 case aco_opcode::v_cmp_ngt_f32
:
1212 case aco_opcode::v_cmp_nle_f32
:
1213 case aco_opcode::v_cmp_neq_f32
:
1214 case aco_opcode::v_cmp_nlt_f32
:
1215 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1217 case aco_opcode::s_cselect_b64
:
1218 case aco_opcode::s_cselect_b32
:
1219 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1220 instr
->operands
[1].constantEquals(0)) {
1221 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1222 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1224 if (instr
->operands
[2].isTemp() && ctx
.info
[instr
->operands
[2].tempId()].is_scc_invert()) {
1225 /* Flip the operands to get rid of the scc_invert instruction */
1226 std::swap(instr
->operands
[0], instr
->operands
[1]);
1227 instr
->operands
[2].setTemp(ctx
.info
[instr
->operands
[2].tempId()].temp
);
1230 case aco_opcode::p_wqm
:
1231 if (instr
->operands
[0].isTemp() &&
1232 ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1233 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1241 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1243 *ordered
= *unordered
= op
;
1245 #define CMP(ord, unord) \
1246 case aco_opcode::v_cmp_##ord##_f32:\
1247 case aco_opcode::v_cmp_n##unord##_f32:\
1248 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1249 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1250 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1264 aco_opcode
get_ordered(aco_opcode op
)
1266 aco_opcode ordered
, unordered
, inverse
;
1267 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1270 aco_opcode
get_unordered(aco_opcode op
)
1272 aco_opcode ordered
, unordered
, inverse
;
1273 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1276 aco_opcode
get_inverse(aco_opcode op
)
1278 aco_opcode ordered
, unordered
, inverse
;
1279 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1282 bool is_cmp(aco_opcode op
)
1284 aco_opcode ordered
, unordered
, inverse
;
1285 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1288 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1290 if (ctx
.info
[tmp
.id()].is_temp())
1291 return ctx
.info
[tmp
.id()].temp
.id();
1296 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1298 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1299 for (const Operand
& op
: instr
->operands
) {
1301 ctx
.uses
[op
.tempId()]--;
1306 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1308 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1310 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1313 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1315 if (instr
->definitions
.size() == 2) {
1316 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1317 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1324 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1325 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1326 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1328 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1330 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1333 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1335 bool neg
[2] = {false, false};
1336 bool abs
[2] = {false, false};
1338 Instruction
*op_instr
[2];
1341 for (unsigned i
= 0; i
< 2; i
++) {
1342 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1346 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1348 if (op_instr
[i
]->opcode
!= expected_cmp
)
1350 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1353 if (op_instr
[i
]->isVOP3()) {
1354 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1355 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1357 neg
[i
] = vop3
->neg
[0];
1358 abs
[i
] = vop3
->abs
[0];
1359 opsel
|= (vop3
->opsel
& 1) << i
;
1362 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1363 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1364 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1370 if (op
[1].type() == RegType::sgpr
)
1371 std::swap(op
[0], op
[1]);
1372 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1373 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1376 ctx
.uses
[op
[0].id()]++;
1377 ctx
.uses
[op
[1].id()]++;
1378 decrease_uses(ctx
, op_instr
[0]);
1379 decrease_uses(ctx
, op_instr
[1]);
1381 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1382 Instruction
*new_instr
;
1383 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1384 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1385 for (unsigned i
= 0; i
< 2; i
++) {
1386 vop3
->neg
[i
] = neg
[i
];
1387 vop3
->abs
[i
] = abs
[i
];
1389 vop3
->opsel
= opsel
;
1390 new_instr
= static_cast<Instruction
*>(vop3
);
1392 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1394 new_instr
->operands
[0] = Operand(op
[0]);
1395 new_instr
->operands
[1] = Operand(op
[1]);
1396 new_instr
->definitions
[0] = instr
->definitions
[0];
1398 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1399 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1401 instr
.reset(new_instr
);
1406 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1407 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1408 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1410 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1412 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1415 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1416 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1418 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1419 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1420 if (!nan_test
|| !cmp
)
1423 if (cmp
->opcode
== expected_nan_test
)
1424 std::swap(nan_test
, cmp
);
1425 else if (nan_test
->opcode
!= expected_nan_test
)
1428 if (!is_cmp(cmp
->opcode
))
1431 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1433 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1436 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1437 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1438 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1439 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1440 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1442 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1445 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1446 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1447 decrease_uses(ctx
, nan_test
);
1448 decrease_uses(ctx
, cmp
);
1450 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1451 Instruction
*new_instr
;
1452 if (cmp
->isVOP3()) {
1453 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1454 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1455 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1456 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1457 new_vop3
->clamp
= cmp_vop3
->clamp
;
1458 new_vop3
->omod
= cmp_vop3
->omod
;
1459 new_vop3
->opsel
= cmp_vop3
->opsel
;
1460 new_instr
= new_vop3
;
1462 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1464 new_instr
->operands
[0] = cmp
->operands
[0];
1465 new_instr
->operands
[1] = cmp
->operands
[1];
1466 new_instr
->definitions
[0] = instr
->definitions
[0];
1468 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1469 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1471 instr
.reset(new_instr
);
1476 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1477 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1478 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1480 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1482 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1485 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1487 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1488 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1490 if (!nan_test
|| !cmp
)
1493 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1494 if (cmp
->opcode
== expected_nan_test
)
1495 std::swap(nan_test
, cmp
);
1496 else if (nan_test
->opcode
!= expected_nan_test
)
1499 if (!is_cmp(cmp
->opcode
))
1502 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1504 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1507 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1508 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1509 if (prop_nan0
!= prop_nan1
)
1512 if (nan_test
->isVOP3()) {
1513 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1514 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1518 int constant_operand
= -1;
1519 for (unsigned i
= 0; i
< 2; i
++) {
1520 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1521 constant_operand
= !i
;
1525 if (constant_operand
== -1)
1529 if (cmp
->operands
[constant_operand
].isConstant()) {
1530 constant
= cmp
->operands
[constant_operand
].constantValue();
1531 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1532 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1533 unsigned id
= original_temp_id(ctx
, tmp
);
1534 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1536 constant
= ctx
.info
[id
].val
;
1542 memcpy(&constantf
, &constant
, 4);
1543 if (isnan(constantf
))
1546 if (cmp
->operands
[0].isTemp())
1547 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1548 if (cmp
->operands
[1].isTemp())
1549 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1550 decrease_uses(ctx
, nan_test
);
1551 decrease_uses(ctx
, cmp
);
1553 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1554 Instruction
*new_instr
;
1555 if (cmp
->isVOP3()) {
1556 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1557 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1558 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1559 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1560 new_vop3
->clamp
= cmp_vop3
->clamp
;
1561 new_vop3
->omod
= cmp_vop3
->omod
;
1562 new_vop3
->opsel
= cmp_vop3
->opsel
;
1563 new_instr
= new_vop3
;
1565 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1567 new_instr
->operands
[0] = cmp
->operands
[0];
1568 new_instr
->operands
[1] = cmp
->operands
[1];
1569 new_instr
->definitions
[0] = instr
->definitions
[0];
1571 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1572 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1574 instr
.reset(new_instr
);
1579 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1580 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1582 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1584 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1586 if (!instr
->operands
[0].isTemp())
1589 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1593 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1594 if (new_opcode
== aco_opcode::last_opcode
)
1597 if (cmp
->operands
[0].isTemp())
1598 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1599 if (cmp
->operands
[1].isTemp())
1600 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1601 decrease_uses(ctx
, cmp
);
1603 Instruction
*new_instr
;
1604 if (cmp
->isVOP3()) {
1605 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1606 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1607 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1608 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1609 new_vop3
->clamp
= cmp_vop3
->clamp
;
1610 new_vop3
->omod
= cmp_vop3
->omod
;
1611 new_vop3
->opsel
= cmp_vop3
->opsel
;
1612 new_instr
= new_vop3
;
1614 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1616 new_instr
->operands
[0] = cmp
->operands
[0];
1617 new_instr
->operands
[1] = cmp
->operands
[1];
1618 new_instr
->definitions
[0] = instr
->definitions
[0];
1620 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1621 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1623 instr
.reset(new_instr
);
1628 /* op1(op2(1, 2), 0) if swap = false
1629 * op1(0, op2(1, 2)) if swap = true */
1630 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1631 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1632 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1633 bool *op1_clamp
, uint8_t *op1_omod
,
1634 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1637 if (op1_instr
->opcode
!= op1
)
1640 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1641 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1644 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1645 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1647 /* don't support inbetween clamp/omod */
1648 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1651 /* get operands and modifiers and check inbetween modifiers */
1652 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1653 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1656 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1657 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1661 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1662 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1665 if (inbetween_opsel
)
1666 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1667 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1671 shuffle
[shuffle_str
[0] - '0'] = 0;
1672 shuffle
[shuffle_str
[1] - '0'] = 1;
1673 shuffle
[shuffle_str
[2] - '0'] = 2;
1675 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1676 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1677 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1678 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1679 *opsel
|= 1 << shuffle
[0];
1681 for (unsigned i
= 0; i
< 2; i
++) {
1682 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1683 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1684 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1685 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1686 *opsel
|= 1 << shuffle
[i
+ 1];
1689 /* check operands */
1690 if (!check_vop3_operands(ctx
, 3, operands
))
1696 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1697 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1698 bool clamp
, unsigned omod
)
1700 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1701 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1702 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1703 new_instr
->clamp
= clamp
;
1704 new_instr
->omod
= omod
;
1705 new_instr
->opsel
= opsel
;
1706 new_instr
->operands
[0] = operands
[0];
1707 new_instr
->operands
[1] = operands
[1];
1708 new_instr
->operands
[2] = operands
[2];
1709 new_instr
->definitions
[0] = instr
->definitions
[0];
1710 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1712 instr
.reset(new_instr
);
1715 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1717 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1718 (label_omod_success
| label_clamp_success
);
1720 for (unsigned swap
= 0; swap
< 2; swap
++) {
1721 if (!((1 << swap
) & ops
))
1724 Operand operands
[3];
1725 bool neg
[3], abs
[3], clamp
;
1726 uint8_t opsel
= 0, omod
= 0;
1727 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1728 instr
.get(), swap
, shuffle
,
1729 operands
, neg
, abs
, &opsel
,
1730 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1731 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1732 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1733 if (omod_clamp
& label_omod_success
)
1734 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1735 if (omod_clamp
& label_clamp_success
)
1736 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1743 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
1745 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
1748 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1749 (label_omod_success
| label_clamp_success
);
1751 /* min(-max(a, b), c) -> min3(-a, -b, c) *
1752 * max(-min(a, b), c) -> max3(-a, -b, c) */
1753 for (unsigned swap
= 0; swap
< 2; swap
++) {
1754 Operand operands
[3];
1755 bool neg
[3], abs
[3], clamp
;
1756 uint8_t opsel
= 0, omod
= 0;
1758 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
1759 instr
.get(), swap
, "012",
1760 operands
, neg
, abs
, &opsel
,
1761 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
1763 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1766 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1767 if (omod_clamp
& label_omod_success
)
1768 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1769 if (omod_clamp
& label_clamp_success
)
1770 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1777 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1778 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1779 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1780 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1781 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1782 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1783 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1786 if (!instr
->operands
[0].isTemp())
1788 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1791 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1794 switch (op2_instr
->opcode
) {
1795 case aco_opcode::s_and_b32
:
1796 case aco_opcode::s_or_b32
:
1797 case aco_opcode::s_xor_b32
:
1798 case aco_opcode::s_and_b64
:
1799 case aco_opcode::s_or_b64
:
1800 case aco_opcode::s_xor_b64
:
1806 /* create instruction */
1807 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1808 std::swap(instr
->definitions
[1], op2_instr
->definitions
[1]);
1809 ctx
.uses
[instr
->operands
[0].tempId()]--;
1810 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1812 switch (op2_instr
->opcode
) {
1813 case aco_opcode::s_and_b32
:
1814 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1816 case aco_opcode::s_or_b32
:
1817 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1819 case aco_opcode::s_xor_b32
:
1820 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1822 case aco_opcode::s_and_b64
:
1823 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1825 case aco_opcode::s_or_b64
:
1826 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1828 case aco_opcode::s_xor_b64
:
1829 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1838 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1839 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1840 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1841 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1842 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1844 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1847 if (instr
->definitions
[0].isTemp() && ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bool())
1850 for (unsigned i
= 0; i
< 2; i
++) {
1851 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1852 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1855 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1856 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1859 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1860 instr
->operands
[0] = instr
->operands
[!i
];
1861 instr
->operands
[1] = op2_instr
->operands
[0];
1862 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1864 switch (instr
->opcode
) {
1865 case aco_opcode::s_and_b32
:
1866 instr
->opcode
= aco_opcode::s_andn2_b32
;
1868 case aco_opcode::s_or_b32
:
1869 instr
->opcode
= aco_opcode::s_orn2_b32
;
1871 case aco_opcode::s_and_b64
:
1872 instr
->opcode
= aco_opcode::s_andn2_b64
;
1874 case aco_opcode::s_or_b64
:
1875 instr
->opcode
= aco_opcode::s_orn2_b64
;
1886 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1887 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1889 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1892 for (unsigned i
= 0; i
< 2; i
++) {
1893 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1894 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
|| !op2_instr
->operands
[1].isConstant())
1897 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1898 if (shift
< 1 || shift
> 4)
1901 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1902 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1905 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1906 instr
->operands
[1] = instr
->operands
[!i
];
1907 instr
->operands
[0] = op2_instr
->operands
[0];
1908 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1910 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1911 aco_opcode::s_lshl2_add_u32
,
1912 aco_opcode::s_lshl3_add_u32
,
1913 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1920 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1923 #define MINMAX(type, gfx9) \
1924 case aco_opcode::v_min_##type:\
1925 case aco_opcode::v_max_##type:\
1926 case aco_opcode::v_med3_##type:\
1927 *min = aco_opcode::v_min_##type;\
1928 *max = aco_opcode::v_max_##type;\
1929 *med3 = aco_opcode::v_med3_##type;\
1930 *min3 = aco_opcode::v_min3_##type;\
1931 *max3 = aco_opcode::v_max3_##type;\
1932 *some_gfx9_only = gfx9;\
1946 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1947 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1948 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1949 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1951 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
1952 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
1953 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
1954 aco_opcode other_op
;
1955 if (instr
->opcode
== min
)
1957 else if (instr
->opcode
== max
)
1962 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1963 (label_omod_success
| label_clamp_success
);
1965 for (unsigned swap
= 0; swap
< 2; swap
++) {
1966 Operand operands
[3];
1967 bool neg
[3], abs
[3], clamp
;
1968 uint8_t opsel
= 0, omod
= 0;
1969 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1970 "012", operands
, neg
, abs
, &opsel
,
1971 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1972 int const0_idx
= -1, const1_idx
= -1;
1973 uint32_t const0
= 0, const1
= 0;
1974 for (int i
= 0; i
< 3; i
++) {
1976 if (operands
[i
].isConstant()) {
1977 val
= operands
[i
].constantValue();
1978 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
1979 val
= ctx
.info
[operands
[i
].tempId()].val
;
1983 if (const0_idx
>= 0) {
1991 if (const0_idx
< 0 || const1_idx
< 0)
1994 if (opsel
& (1 << const0_idx
))
1996 if (opsel
& (1 << const1_idx
))
1999 int lower_idx
= const0_idx
;
2001 case aco_opcode::v_min_f32
:
2002 case aco_opcode::v_min_f16
: {
2003 float const0_f
, const1_f
;
2004 if (min
== aco_opcode::v_min_f32
) {
2005 memcpy(&const0_f
, &const0
, 4);
2006 memcpy(&const1_f
, &const1
, 4);
2008 const0_f
= _mesa_half_to_float(const0
);
2009 const1_f
= _mesa_half_to_float(const1
);
2011 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
2012 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
2013 if (neg
[const0_idx
]) const0_f
= -const0_f
;
2014 if (neg
[const1_idx
]) const1_f
= -const1_f
;
2015 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
2018 case aco_opcode::v_min_u32
: {
2019 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
2022 case aco_opcode::v_min_u16
: {
2023 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
2026 case aco_opcode::v_min_i32
: {
2027 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
2028 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
2029 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2032 case aco_opcode::v_min_i16
: {
2033 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
2034 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
2035 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2041 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
2043 if (instr
->opcode
== min
) {
2044 if (upper_idx
!= 0 || lower_idx
== 0)
2047 if (upper_idx
== 0 || lower_idx
!= 0)
2051 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2052 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2053 if (omod_clamp
& label_omod_success
)
2054 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2055 if (omod_clamp
& label_clamp_success
)
2056 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2066 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2068 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2069 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2070 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2072 /* find candidates and create the set of sgprs already read */
2073 unsigned sgpr_ids
[2] = {0, 0};
2074 uint32_t operand_mask
= 0;
2075 bool has_literal
= false;
2076 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2077 if (instr
->operands
[i
].isLiteral())
2079 if (!instr
->operands
[i
].isTemp())
2081 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2082 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
2083 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
2085 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
2086 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
2087 operand_mask
|= 1u << i
;
2089 unsigned max_sgprs
= 1;
2090 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2095 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2097 /* keep on applying sgprs until there is nothing left to be done */
2098 while (operand_mask
) {
2099 uint32_t sgpr_idx
= 0;
2100 uint32_t sgpr_info_id
= 0;
2101 uint32_t mask
= operand_mask
;
2104 unsigned i
= u_bit_scan(&mask
);
2105 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2106 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
2108 sgpr_info_id
= instr
->operands
[i
].tempId();
2111 operand_mask
&= ~(1u << sgpr_idx
);
2113 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2114 * definitively beneficial.
2115 * TODO: this is too conservative because later the use count could be reduced to 1 */
2116 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2119 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2120 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2121 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2124 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2125 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2126 } else if (can_swap_operands(instr
)) {
2127 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2128 instr
->operands
[0] = Operand(sgpr
);
2129 /* swap bits using a 4-entry LUT */
2130 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2131 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2132 } else if (can_use_VOP3(ctx
, instr
)) {
2133 to_VOP3(ctx
, instr
);
2134 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2140 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2141 ctx
.uses
[sgpr_info_id
]--;
2142 ctx
.uses
[sgpr
.id()]++;
2146 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2148 /* check if we could apply omod on predecessor */
2149 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
2150 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2151 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2153 unsigned idx
= op0
? 0 : 1;
2154 /* omod was successfully applied */
2155 /* if the omod instruction is v_mad, we also have to change the original add */
2156 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2157 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2158 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2159 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2160 add_instr
->definitions
[0] = instr
->definitions
[0];
2163 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2164 /* check if we have an additional clamp modifier */
2165 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2166 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2167 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2168 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2170 /* change definition ssa-id of modified instruction */
2171 omod_instr
->definitions
[0] = instr
->definitions
[0];
2173 /* change the definition of instr to something unused, e.g. the original omod def */
2174 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2175 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2178 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2179 /* in all other cases, label this instruction as option for multiply-add */
2180 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2184 /* check if we could apply clamp on predecessor */
2185 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
2187 bool found_zero
= false, found_one
= false;
2188 for (unsigned i
= 0; i
< 3; i
++)
2190 if (instr
->operands
[i
].constantEquals(0))
2192 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
2197 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2198 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2199 /* clamp was successfully applied */
2200 /* if the clamp instruction is v_mad, we also have to change the original add */
2201 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2202 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2203 add_instr
->definitions
[0] = instr
->definitions
[0];
2205 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2206 /* change definition ssa-id of modified instruction */
2207 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2209 /* change the definition of instr to something unused, e.g. the original omod def */
2210 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2211 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2216 /* omod has no effect if denormals are enabled */
2217 bool can_use_omod
= block
.fp_mode
.denorm32
== 0;
2219 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2220 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2221 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2222 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2223 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2224 to_VOP3(ctx
, instr
);
2225 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2226 def_info
.set_omod_success(instr
.get());
2227 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2228 to_VOP3(ctx
, instr
);
2229 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2230 def_info
.set_omod_success(instr
.get());
2231 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2232 to_VOP3(ctx
, instr
);
2233 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2234 def_info
.set_omod_success(instr
.get());
2235 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2236 to_VOP3(ctx
, instr
);
2237 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2238 def_info
.set_clamp_success(instr
.get());
2245 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2246 // this would mean that we'd have to fix the instruction uses while value propagation
2248 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2250 if (instr
->definitions
.empty() || is_dead(ctx
.uses
, instr
.get()))
2253 if (instr
->isVALU()) {
2254 if (can_apply_sgprs(instr
))
2255 apply_sgprs(ctx
, instr
);
2256 if (apply_omod_clamp(ctx
, block
, instr
))
2260 if (ctx
.info
[instr
->definitions
[0].tempId()].is_vcc_hint()) {
2261 instr
->definitions
[0].setHint(vcc
);
2264 /* TODO: There are still some peephole optimizations that could be done:
2265 * - abs(a - b) -> s_absdiff_i32
2266 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2267 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2268 * These aren't probably too interesting though.
2269 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2270 * probably more useful than the previously mentioned optimizations.
2271 * The various comparison optimizations also currently only work with 32-bit
2274 /* neg(mul(a, b)) -> mul(neg(a), b) */
2275 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2276 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2278 if (!ctx
.info
[val
.id()].is_mul())
2281 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2283 if (mul_instr
->operands
[0].isLiteral())
2285 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2288 /* convert to mul(neg(a), b) */
2289 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2290 Definition def
= instr
->definitions
[0];
2291 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2292 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2293 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2294 instr
->operands
[0] = mul_instr
->operands
[0];
2295 instr
->operands
[1] = mul_instr
->operands
[1];
2296 instr
->definitions
[0] = def
;
2297 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2298 if (mul_instr
->isVOP3()) {
2299 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2300 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2301 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2302 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2303 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2304 new_mul
->omod
= mul
->omod
;
2306 new_mul
->neg
[0] ^= true;
2307 new_mul
->clamp
= false;
2309 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2312 /* combine mul+add -> mad */
2313 else if ((instr
->opcode
== aco_opcode::v_add_f32
||
2314 instr
->opcode
== aco_opcode::v_sub_f32
||
2315 instr
->opcode
== aco_opcode::v_subrev_f32
) &&
2316 block
.fp_mode
.denorm32
== 0 && !block
.fp_mode
.preserve_signed_zero_inf_nan32
) {
2317 //TODO: we could use fma instead when denormals are enabled if the NIR isn't marked as precise
2319 uint32_t uses_src0
= UINT32_MAX
;
2320 uint32_t uses_src1
= UINT32_MAX
;
2321 Instruction
* mul_instr
= nullptr;
2322 unsigned add_op_idx
;
2323 /* check if any of the operands is a multiplication */
2324 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2325 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2326 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2327 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2329 /* find the 'best' mul instruction to combine with the add */
2330 if (uses_src0
< uses_src1
) {
2331 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2333 } else if (uses_src1
< uses_src0
) {
2334 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2336 } else if (uses_src0
!= UINT32_MAX
) {
2337 /* tiebreaker: quite random what to pick */
2338 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2339 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2342 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2347 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2348 bool neg
[3] = {false, false, false};
2349 bool abs
[3] = {false, false, false};
2352 op
[0] = mul_instr
->operands
[0];
2353 op
[1] = mul_instr
->operands
[1];
2354 op
[2] = instr
->operands
[add_op_idx
];
2355 // TODO: would be better to check this before selecting a mul instr?
2356 if (!check_vop3_operands(ctx
, 3, op
))
2359 if (mul_instr
->isVOP3()) {
2360 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2361 neg
[0] = vop3
->neg
[0];
2362 neg
[1] = vop3
->neg
[1];
2363 abs
[0] = vop3
->abs
[0];
2364 abs
[1] = vop3
->abs
[1];
2365 /* we cannot use these modifiers between mul and add */
2366 if (vop3
->clamp
|| vop3
->omod
)
2370 /* convert to mad */
2371 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2372 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2374 ctx
.uses
[op
[0].tempId()]++;
2376 ctx
.uses
[op
[1].tempId()]++;
2379 if (instr
->isVOP3()) {
2380 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2381 neg
[2] = vop3
->neg
[add_op_idx
];
2382 abs
[2] = vop3
->abs
[add_op_idx
];
2384 clamp
= vop3
->clamp
;
2385 /* abs of the multiplication result */
2386 if (vop3
->abs
[1 - add_op_idx
]) {
2392 /* neg of the multiplication result */
2393 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2395 if (instr
->opcode
== aco_opcode::v_sub_f32
)
2396 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2397 else if (instr
->opcode
== aco_opcode::v_subrev_f32
)
2398 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2400 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2401 for (unsigned i
= 0; i
< 3; i
++)
2403 mad
->operands
[i
] = op
[i
];
2404 mad
->neg
[i
] = neg
[i
];
2405 mad
->abs
[i
] = abs
[i
];
2409 mad
->definitions
[0] = instr
->definitions
[0];
2411 /* mark this ssa_def to be re-checked for profitability and literals */
2412 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2413 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2414 instr
.reset(mad
.release());
2418 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2419 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2420 for (unsigned i
= 0; i
< 2; i
++) {
2421 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2422 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2423 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2424 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2425 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2427 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2428 new_instr
->operands
[0] = Operand(0u);
2429 new_instr
->operands
[1] = instr
->operands
[!i
];
2430 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2431 new_instr
->definitions
[0] = instr
->definitions
[0];
2432 instr
.reset(new_instr
.release());
2433 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2437 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2438 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2439 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2440 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2441 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2442 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2443 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2444 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2445 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2446 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2447 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2448 combine_salu_lshl_add(ctx
, instr
);
2449 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2450 combine_salu_not_bitwise(ctx
, instr
);
2451 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2452 if (combine_inverse_comparison(ctx
, instr
)) ;
2453 else combine_salu_not_bitwise(ctx
, instr
);
2454 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2455 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2456 if (combine_ordering_test(ctx
, instr
)) ;
2457 else if (combine_comparison_ordering(ctx
, instr
)) ;
2458 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2459 else combine_salu_n2(ctx
, instr
);
2461 aco_opcode min
, max
, min3
, max3
, med3
;
2462 bool some_gfx9_only
;
2463 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2464 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2465 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2466 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2471 bool to_uniform_bool_instr(opt_ctx
&ctx
, aco_ptr
<Instruction
> &instr
)
2473 switch (instr
->opcode
) {
2474 case aco_opcode::s_and_b32
:
2475 case aco_opcode::s_and_b64
:
2476 instr
->opcode
= aco_opcode::s_and_b32
;
2478 case aco_opcode::s_or_b32
:
2479 case aco_opcode::s_or_b64
:
2480 instr
->opcode
= aco_opcode::s_or_b32
;
2482 case aco_opcode::s_xor_b32
:
2483 case aco_opcode::s_xor_b64
:
2484 instr
->opcode
= aco_opcode::s_absdiff_i32
;
2487 /* Don't transform other instructions. They are very unlikely to appear here. */
2491 for (Operand
&op
: instr
->operands
) {
2492 ctx
.uses
[op
.tempId()]--;
2494 if (ctx
.info
[op
.tempId()].is_uniform_bool()) {
2495 /* Just use the uniform boolean temp. */
2496 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
2497 } else if (ctx
.info
[op
.tempId()].is_uniform_bitwise()) {
2498 /* Use the SCC definition of the predecessor instruction.
2499 * This allows the predecessor to get picked up by the same optimization (if it has no divergent users),
2500 * and it also makes sure that the current instruction will keep working even if the predecessor won't be transformed.
2502 Instruction
*pred_instr
= ctx
.info
[op
.tempId()].instr
;
2503 assert(pred_instr
->definitions
.size() >= 2);
2504 assert(pred_instr
->definitions
[1].isFixed() && pred_instr
->definitions
[1].physReg() == scc
);
2505 op
.setTemp(pred_instr
->definitions
[1].getTemp());
2507 unreachable("Invalid operand on uniform bitwise instruction.");
2510 ctx
.uses
[op
.tempId()]++;
2513 instr
->definitions
[0].setTemp(Temp(instr
->definitions
[0].tempId(), s1
));
2514 assert(instr
->operands
[0].regClass() == s1
);
2515 assert(instr
->operands
[1].regClass() == s1
);
2519 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2521 const uint32_t threshold
= 4;
2523 if (is_dead(ctx
.uses
, instr
.get())) {
2528 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2529 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2530 unsigned num_used
= 0;
2532 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2533 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2539 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2540 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2541 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2545 for (Operand
& vec_op
: vec
->operands
) {
2546 if (off
== idx
* instr
->definitions
[0].size()) {
2550 off
+= vec_op
.size();
2552 if (off
!= instr
->operands
[0].size()) {
2553 ctx
.uses
[instr
->operands
[0].tempId()]--;
2554 for (Operand
& vec_op
: vec
->operands
) {
2555 if (vec_op
.isTemp())
2556 ctx
.uses
[vec_op
.tempId()]--;
2559 ctx
.uses
[op
.tempId()]++;
2561 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2562 extract
->operands
[0] = op
;
2563 extract
->definitions
[0] = instr
->definitions
[idx
];
2564 instr
.reset(extract
.release());
2570 if (!done
&& num_used
== 1) {
2571 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2572 extract
->operands
[0] = instr
->operands
[0];
2573 extract
->operands
[1] = Operand((uint32_t) idx
);
2574 extract
->definitions
[0] = instr
->definitions
[idx
];
2575 instr
.reset(extract
.release());
2579 mad_info
* mad_info
= NULL
;
2580 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2581 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2582 /* re-check mad instructions */
2583 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2584 ctx
.uses
[mad_info
->mul_temp_id
]++;
2585 if (instr
->operands
[0].isTemp())
2586 ctx
.uses
[instr
->operands
[0].tempId()]--;
2587 if (instr
->operands
[1].isTemp())
2588 ctx
.uses
[instr
->operands
[1].tempId()]--;
2589 instr
.swap(mad_info
->add_instr
);
2592 /* check literals */
2593 else if (!instr
->usesModifiers()) {
2594 bool sgpr_used
= false;
2595 uint32_t literal_idx
= 0;
2596 uint32_t literal_uses
= UINT32_MAX
;
2597 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2599 if (instr
->operands
[i
].isConstant() && i
> 0) {
2600 literal_uses
= UINT32_MAX
;
2603 if (!instr
->operands
[i
].isTemp())
2605 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2606 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2607 if (!sgpr_used
&& ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2608 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2611 literal_uses
= UINT32_MAX
;
2614 /* don't break because we still need to check constants */
2615 } else if (!sgpr_used
&&
2616 ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2617 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2618 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2622 if (literal_uses
< threshold
) {
2623 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2624 mad_info
->check_literal
= true;
2625 mad_info
->literal_idx
= literal_idx
;
2631 /* Mark SCC needed, so the uniform boolean transformation won't swap the definitions when it isn't beneficial */
2632 if (instr
->format
== Format::PSEUDO_BRANCH
&&
2633 instr
->operands
.size() &&
2634 instr
->operands
[0].isTemp()) {
2635 ctx
.info
[instr
->operands
[0].tempId()].set_scc_needed();
2637 } else if ((instr
->opcode
== aco_opcode::s_cselect_b64
||
2638 instr
->opcode
== aco_opcode::s_cselect_b32
) &&
2639 instr
->operands
[2].isTemp()) {
2640 ctx
.info
[instr
->operands
[2].tempId()].set_scc_needed();
2643 /* check for literals */
2644 if (!instr
->isSALU() && !instr
->isVALU())
2647 /* Transform uniform bitwise boolean operations to 32-bit when there are no divergent uses. */
2648 if (instr
->definitions
.size() &&
2649 ctx
.uses
[instr
->definitions
[0].tempId()] == 0 &&
2650 ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bitwise()) {
2651 bool transform_done
= to_uniform_bool_instr(ctx
, instr
);
2653 if (transform_done
&& !ctx
.info
[instr
->definitions
[1].tempId()].is_scc_needed()) {
2654 /* Swap the two definition IDs in order to avoid overusing the SCC. This reduces extra moves generated by RA. */
2655 uint32_t def0_id
= instr
->definitions
[0].getTemp().id();
2656 uint32_t def1_id
= instr
->definitions
[1].getTemp().id();
2657 instr
->definitions
[0].setTemp(Temp(def1_id
, s1
));
2658 instr
->definitions
[1].setTemp(Temp(def0_id
, s1
));
2664 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
2665 return; /* some encodings can't ever take literals */
2667 /* we do not apply the literals yet as we don't know if it is profitable */
2668 Operand
current_literal(s1
);
2670 unsigned literal_id
= 0;
2671 unsigned literal_uses
= UINT32_MAX
;
2672 Operand
literal(s1
);
2673 unsigned num_operands
= 1;
2674 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
2675 num_operands
= instr
->operands
.size();
2676 /* catch VOP2 with a 3rd SGPR operand (e.g. v_cndmask_b32, v_addc_co_u32) */
2677 else if (instr
->isVALU() && instr
->operands
.size() >= 3)
2680 unsigned sgpr_ids
[2] = {0, 0};
2681 bool is_literal_sgpr
= false;
2684 /* choose a literal to apply */
2685 for (unsigned i
= 0; i
< num_operands
; i
++) {
2686 Operand op
= instr
->operands
[i
];
2688 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
2689 op
.tempId() != sgpr_ids
[0])
2690 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
2692 if (op
.isLiteral()) {
2693 current_literal
= op
;
2695 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal()) {
2699 if (!alu_can_accept_constant(instr
->opcode
, i
))
2702 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
2703 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
2705 literal
= Operand(ctx
.info
[op
.tempId()].val
);
2706 literal_uses
= ctx
.uses
[op
.tempId()];
2707 literal_id
= op
.tempId();
2710 mask
|= (op
.tempId() == literal_id
) << i
;
2714 /* don't go over the constant bus limit */
2715 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2716 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2717 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2718 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
2719 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2720 const_bus_limit
= 2;
2722 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2723 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
2726 if (literal_id
&& literal_uses
< threshold
&&
2727 (current_literal
.isUndefined() ||
2728 (current_literal
.size() == literal
.size() &&
2729 current_literal
.constantValue() == literal
.constantValue()))) {
2730 /* mark the literal to be applied */
2732 unsigned i
= u_bit_scan(&mask
);
2733 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
2734 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2740 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2742 /* Cleanup Dead Instructions */
2746 /* apply literals on MAD */
2747 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2748 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2749 if (info
->check_literal
&& ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0) {
2750 aco_ptr
<Instruction
> new_mad
;
2751 if (info
->literal_idx
== 2) { /* add literal -> madak */
2752 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2753 new_mad
->operands
[0] = instr
->operands
[0];
2754 new_mad
->operands
[1] = instr
->operands
[1];
2755 } else { /* mul literal -> madmk */
2756 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2757 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2758 new_mad
->operands
[1] = instr
->operands
[2];
2760 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2761 new_mad
->definitions
[0] = instr
->definitions
[0];
2762 ctx
.instructions
.emplace_back(std::move(new_mad
));
2767 /* apply literals on other SALU/VALU */
2768 if (instr
->isSALU() || instr
->isVALU()) {
2769 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2770 Operand op
= instr
->operands
[i
];
2771 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal() && ctx
.uses
[op
.tempId()] == 0) {
2772 Operand
literal(ctx
.info
[op
.tempId()].val
);
2773 if (instr
->isVALU() && i
> 0)
2774 to_VOP3(ctx
, instr
);
2775 instr
->operands
[i
] = literal
;
2780 ctx
.instructions
.emplace_back(std::move(instr
));
2784 void optimize(Program
* program
)
2787 ctx
.program
= program
;
2788 std::vector
<ssa_info
> info(program
->peekAllocationId());
2789 ctx
.info
= info
.data();
2791 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2792 for (Block
& block
: program
->blocks
) {
2793 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2794 label_instruction(ctx
, block
, instr
);
2797 ctx
.uses
= std::move(dead_code_analysis(program
));
2799 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2800 for (Block
& block
: program
->blocks
) {
2801 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2802 combine_instruction(ctx
, block
, instr
);
2805 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2806 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2807 Block
* block
= &(*it
);
2808 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2809 select_instruction(ctx
, *it
);
2812 /* 4. Add literals to instructions */
2813 for (Block
& block
: program
->blocks
) {
2814 ctx
.instructions
.clear();
2815 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2816 apply_literals(ctx
, instr
);
2817 block
.instructions
.swap(ctx
.instructions
);