2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant
= 1 << 1,
69 label_literal
= 1 << 6,
73 label_omod5
= 1 << 10,
74 label_omod_success
= 1 << 11,
75 label_clamp
= 1 << 12,
76 label_clamp_success
= 1 << 13,
77 label_undefined
= 1 << 14,
80 label_add_sub
= 1 << 17,
81 label_bitwise
= 1 << 18,
82 label_minmax
= 1 << 19,
84 label_uniform_bool
= 1 << 21,
85 label_constant_64bit
= 1 << 22,
86 label_uniform_bitwise
= 1 << 23,
87 label_scc_invert
= 1 << 24,
90 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
|
91 label_add_sub
| label_bitwise
| label_uniform_bitwise
| label_minmax
| label_fcmp
;
92 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
|
93 label_omod2
| label_omod4
| label_omod5
| label_clamp
| label_scc_invert
;
94 static constexpr uint32_t val_labels
= label_constant
| label_constant_64bit
| label_literal
| label_mad
;
104 void add_label(Label new_label
)
106 /* Since all labels which use "instr" use it for the same thing
107 * (indicating the defining instruction), there is no need to clear
108 * any other instr labels. */
109 if (new_label
& instr_labels
)
110 label
&= ~temp_labels
; /* instr and temp alias */
112 if (new_label
& temp_labels
) {
113 label
&= ~temp_labels
;
114 label
&= ~instr_labels
; /* instr and temp alias */
117 if (new_label
& val_labels
)
118 label
&= ~val_labels
;
123 void set_vec(Instruction
* vec
)
125 add_label(label_vec
);
131 return label
& label_vec
;
134 void set_constant(uint32_t constant
)
136 add_label(label_constant
);
142 return label
& label_constant
;
145 void set_constant_64bit(uint32_t constant
)
147 add_label(label_constant_64bit
);
151 bool is_constant_64bit()
153 return label
& label_constant_64bit
;
156 void set_abs(Temp abs_temp
)
158 add_label(label_abs
);
164 return label
& label_abs
;
167 void set_neg(Temp neg_temp
)
169 add_label(label_neg
);
175 return label
& label_neg
;
178 void set_neg_abs(Temp neg_abs_temp
)
180 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
184 void set_mul(Instruction
* mul
)
186 add_label(label_mul
);
192 return label
& label_mul
;
195 void set_temp(Temp tmp
)
197 add_label(label_temp
);
203 return label
& label_temp
;
206 void set_literal(uint32_t lit
)
208 add_label(label_literal
);
214 return label
& label_literal
;
217 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
219 add_label(label_mad
);
226 return label
& label_mad
;
229 void set_omod2(Temp def
)
231 add_label(label_omod2
);
237 return label
& label_omod2
;
240 void set_omod4(Temp def
)
242 add_label(label_omod4
);
248 return label
& label_omod4
;
251 void set_omod5(Temp def
)
253 add_label(label_omod5
);
259 return label
& label_omod5
;
262 void set_omod_success(Instruction
* omod_instr
)
264 add_label(label_omod_success
);
268 bool is_omod_success()
270 return label
& label_omod_success
;
273 void set_clamp(Temp def
)
275 add_label(label_clamp
);
281 return label
& label_clamp
;
284 void set_clamp_success(Instruction
* clamp_instr
)
286 add_label(label_clamp_success
);
290 bool is_clamp_success()
292 return label
& label_clamp_success
;
297 add_label(label_undefined
);
302 return label
& label_undefined
;
305 void set_vcc(Temp vcc
)
307 add_label(label_vcc
);
313 return label
& label_vcc
;
316 bool is_constant_or_literal()
318 return is_constant() || is_literal();
321 void set_b2f(Temp val
)
323 add_label(label_b2f
);
329 return label
& label_b2f
;
332 void set_add_sub(Instruction
*add_sub_instr
)
334 add_label(label_add_sub
);
335 instr
= add_sub_instr
;
340 return label
& label_add_sub
;
343 void set_bitwise(Instruction
*bitwise_instr
)
345 add_label(label_bitwise
);
346 instr
= bitwise_instr
;
351 return label
& label_bitwise
;
354 void set_uniform_bitwise()
356 add_label(label_uniform_bitwise
);
359 bool is_uniform_bitwise()
361 return label
& label_uniform_bitwise
;
364 void set_minmax(Instruction
*minmax_instr
)
366 add_label(label_minmax
);
367 instr
= minmax_instr
;
372 return label
& label_minmax
;
375 void set_fcmp(Instruction
*fcmp_instr
)
377 add_label(label_fcmp
);
383 return label
& label_fcmp
;
386 void set_scc_invert(Temp scc_inv
)
388 add_label(label_scc_invert
);
394 return label
& label_scc_invert
;
397 void set_uniform_bool(Temp uniform_bool
)
399 add_label(label_uniform_bool
);
403 bool is_uniform_bool()
405 return label
& label_uniform_bool
;
412 std::vector
<aco_ptr
<Instruction
>> instructions
;
414 std::pair
<uint32_t,Temp
> last_literal
;
415 std::vector
<mad_info
> mad_infos
;
416 std::vector
<uint16_t> uses
;
419 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
421 if (instr
->operands
[0].isConstant() ||
422 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
425 switch (instr
->opcode
) {
426 case aco_opcode::v_add_f32
:
427 case aco_opcode::v_mul_f32
:
428 case aco_opcode::v_or_b32
:
429 case aco_opcode::v_and_b32
:
430 case aco_opcode::v_xor_b32
:
431 case aco_opcode::v_max_f32
:
432 case aco_opcode::v_min_f32
:
433 case aco_opcode::v_max_i32
:
434 case aco_opcode::v_min_i32
:
435 case aco_opcode::v_max_u32
:
436 case aco_opcode::v_min_u32
:
437 case aco_opcode::v_cmp_eq_f32
:
438 case aco_opcode::v_cmp_lg_f32
:
440 case aco_opcode::v_sub_f32
:
441 instr
->opcode
= aco_opcode::v_subrev_f32
;
443 case aco_opcode::v_cmp_lt_f32
:
444 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
446 case aco_opcode::v_cmp_ge_f32
:
447 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
449 case aco_opcode::v_cmp_lt_i32
:
450 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
457 bool can_use_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
462 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
465 if (instr
->isDPP() || instr
->isSDWA())
468 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
469 instr
->opcode
!= aco_opcode::v_madak_f32
&&
470 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
471 instr
->opcode
!= aco_opcode::v_madak_f16
&&
472 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
473 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
474 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
475 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
476 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
477 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
478 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
481 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
483 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
484 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
485 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
486 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
487 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
490 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
495 aco_ptr
<Instruction
> tmp
= std::move(instr
);
496 Format format
= asVOP3(tmp
->format
);
497 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
498 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
499 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
500 instr
->definitions
[i
] = tmp
->definitions
[i
];
501 if (instr
->definitions
[i
].isTemp()) {
502 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
503 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
504 info
.instr
= instr
.get();
509 /* only covers special cases */
510 bool can_accept_constant(aco_ptr
<Instruction
>& instr
, unsigned operand
)
512 switch (instr
->opcode
) {
513 case aco_opcode::v_interp_p2_f32
:
514 case aco_opcode::v_mac_f32
:
515 case aco_opcode::v_writelane_b32
:
516 case aco_opcode::v_writelane_b32_e64
:
517 case aco_opcode::v_cndmask_b32
:
519 case aco_opcode::s_addk_i32
:
520 case aco_opcode::s_mulk_i32
:
521 case aco_opcode::p_wqm
:
522 case aco_opcode::p_extract_vector
:
523 case aco_opcode::p_split_vector
:
524 case aco_opcode::v_readlane_b32
:
525 case aco_opcode::v_readlane_b32_e64
:
526 case aco_opcode::v_readfirstlane_b32
:
529 if ((instr
->format
== Format::MUBUF
||
530 instr
->format
== Format::MIMG
) &&
531 instr
->definitions
.size() == 1 &&
532 instr
->operands
.size() == 4) {
539 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
541 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
542 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
547 /* check constant bus and literal limitations */
548 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
550 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
551 Operand
literal32(s1
);
552 Operand
literal64(s2
);
553 unsigned num_sgprs
= 0;
554 unsigned sgpr
[] = {0, 0};
556 for (unsigned i
= 0; i
< num_operands
; i
++) {
557 Operand op
= operands
[i
];
559 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
560 /* two reads of the same SGPR count as 1 to the limit */
561 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
563 sgpr
[num_sgprs
++] = op
.tempId();
568 } else if (op
.isLiteral()) {
569 if (ctx
.program
->chip_class
< GFX10
)
572 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
574 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
577 /* Any number of 32-bit literals counts as only 1 to the limit. Same
578 * (but separately) for 64-bit literals. */
579 if (op
.size() == 1 && literal32
.isUndefined()) {
582 } else if (op
.size() == 2 && literal64
.isUndefined()) {
595 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
597 Operand op
= instr
->operands
[op_index
];
601 Temp tmp
= op
.getTemp();
602 if (!ctx
.info
[tmp
.id()].is_add_sub())
605 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
607 switch (add_instr
->opcode
) {
608 case aco_opcode::v_add_u32
:
609 case aco_opcode::v_add_co_u32
:
610 case aco_opcode::s_add_i32
:
611 case aco_opcode::s_add_u32
:
617 if (add_instr
->usesModifiers())
620 for (unsigned i
= 0; i
< 2; i
++) {
621 if (add_instr
->operands
[i
].isConstant()) {
622 *offset
= add_instr
->operands
[i
].constantValue();
623 } else if (add_instr
->operands
[i
].isTemp() &&
624 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
625 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
629 if (!add_instr
->operands
[!i
].isTemp())
632 uint32_t offset2
= 0;
633 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
636 *base
= add_instr
->operands
[!i
].getTemp();
644 Operand
get_constant_op(opt_ctx
&ctx
, uint32_t val
, bool is64bit
= false)
646 // TODO: this functions shouldn't be needed if we store Operand instead of value.
647 Operand
op(val
, is64bit
);
648 if (val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
649 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
653 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
655 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
656 ASSERTED
bool all_const
= false;
657 for (Operand
& op
: instr
->operands
)
658 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
659 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
662 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
664 if (!instr
->operands
[i
].isTemp())
667 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
668 /* propagate undef */
669 if (info
.is_undefined() && is_phi(instr
))
670 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
671 /* propagate reg->reg of same type */
672 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
673 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
674 info
= ctx
.info
[info
.temp
.id()];
677 /* SALU / PSEUDO: propagate inline constants */
678 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
679 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
680 instr
->operands
[i
].setTemp(info
.temp
);
681 info
= ctx
.info
[info
.temp
.id()];
682 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
683 /* propagate vgpr if it can take it */
684 switch (instr
->opcode
) {
685 case aco_opcode::p_create_vector
:
686 case aco_opcode::p_split_vector
:
687 case aco_opcode::p_extract_vector
:
688 case aco_opcode::p_phi
: {
689 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
690 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
692 instr
->operands
[i
] = Operand(info
.temp
);
693 info
= ctx
.info
[info
.temp
.id()];
701 if ((info
.is_constant() || info
.is_constant_64bit() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) && !instr
->operands
[i
].isFixed() && can_accept_constant(instr
, i
)) {
702 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
707 /* VALU: propagate neg, abs & inline constants */
708 else if (instr
->isVALU()) {
709 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
710 instr
->operands
[i
].setTemp(info
.temp
);
711 info
= ctx
.info
[info
.temp
.id()];
713 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
716 instr
->operands
[i
] = Operand(info
.temp
);
718 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
720 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
722 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
723 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
724 instr
->operands
[i
].setTemp(info
.temp
);
726 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
729 instr
->operands
[i
].setTemp(info
.temp
);
731 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
733 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
736 if ((info
.is_constant() || info
.is_constant_64bit()) && can_accept_constant(instr
, i
)) {
737 Operand op
= get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
738 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
739 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
740 instr
->operands
[i
] = op
;
742 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
743 instr
->operands
[i
] = instr
->operands
[0];
744 instr
->operands
[0] = op
;
746 } else if (can_use_VOP3(ctx
, instr
)) {
748 instr
->operands
[i
] = op
;
754 /* MUBUF: propagate constants and combine additions */
755 else if (instr
->format
== Format::MUBUF
) {
756 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
759 while (info
.is_temp())
760 info
= ctx
.info
[info
.temp
.id()];
762 if (mubuf
->offen
&& i
== 0 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
763 assert(!mubuf
->idxen
);
764 instr
->operands
[i
] = Operand(v1
);
765 mubuf
->offset
+= info
.val
;
766 mubuf
->offen
= false;
768 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
769 instr
->operands
[2] = Operand((uint32_t) 0);
770 mubuf
->offset
+= info
.val
;
772 } else if (mubuf
->offen
&& i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
773 assert(!mubuf
->idxen
);
774 instr
->operands
[i
].setTemp(base
);
775 mubuf
->offset
+= offset
;
777 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
778 instr
->operands
[i
].setTemp(base
);
779 mubuf
->offset
+= offset
;
784 /* DS: combine additions */
785 else if (instr
->format
== Format::DS
) {
787 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
790 bool has_usable_ds_offset
= ctx
.program
->chip_class
>= GFX7
;
791 if (has_usable_ds_offset
&&
792 i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) &&
793 base
.regClass() == instr
->operands
[i
].regClass() &&
794 instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
795 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
796 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
797 if (offset
% 4 == 0 &&
798 ds
->offset0
+ (offset
>> 2) <= 255 &&
799 ds
->offset1
+ (offset
>> 2) <= 255) {
800 instr
->operands
[i
].setTemp(base
);
801 ds
->offset0
+= offset
>> 2;
802 ds
->offset1
+= offset
>> 2;
805 if (ds
->offset0
+ offset
<= 65535) {
806 instr
->operands
[i
].setTemp(base
);
807 ds
->offset0
+= offset
;
813 /* SMEM: propagate constants and combine additions */
814 else if (instr
->format
== Format::SMEM
) {
816 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
819 if (i
== 1 && info
.is_constant_or_literal() &&
820 (ctx
.program
->chip_class
< GFX8
|| info
.val
<= 0xFFFFF)) {
821 instr
->operands
[i
] = Operand(info
.val
);
823 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
824 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
826 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
827 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
831 smem
->operands
[1] = Operand(offset
);
832 smem
->operands
.back() = Operand(base
);
834 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
835 new_instr
->operands
[0] = smem
->operands
[0];
836 new_instr
->operands
[1] = Operand(offset
);
837 if (smem
->definitions
.empty())
838 new_instr
->operands
[2] = smem
->operands
[2];
839 new_instr
->operands
.back() = Operand(base
);
840 if (!smem
->definitions
.empty())
841 new_instr
->definitions
[0] = smem
->definitions
[0];
842 new_instr
->can_reorder
= smem
->can_reorder
;
843 new_instr
->barrier
= smem
->barrier
;
844 instr
.reset(new_instr
);
845 smem
= static_cast<SMEM_instruction
*>(instr
.get());
851 else if (instr
->format
== Format::PSEUDO_BRANCH
) {
852 if (ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
853 /* Flip the branch instruction to get rid of the scc_invert instruction */
854 instr
->opcode
= instr
->opcode
== aco_opcode::p_cbranch_z
? aco_opcode::p_cbranch_nz
: aco_opcode::p_cbranch_z
;
855 instr
->operands
[0].setTemp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
860 /* if this instruction doesn't define anything, return */
861 if (instr
->definitions
.empty())
864 switch (instr
->opcode
) {
865 case aco_opcode::p_create_vector
: {
866 unsigned num_ops
= instr
->operands
.size();
867 for (const Operand
& op
: instr
->operands
) {
868 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
869 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
871 if (num_ops
!= instr
->operands
.size()) {
872 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
873 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
874 instr
->definitions
[0] = old_vec
->definitions
[0];
876 for (Operand
& old_op
: old_vec
->operands
) {
877 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
878 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
879 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
880 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
881 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
882 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
883 instr
->operands
[k
++] = op
;
886 instr
->operands
[k
++] = old_op
;
889 assert(k
== num_ops
);
891 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
892 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
893 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
894 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
897 case aco_opcode::p_split_vector
: {
898 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
900 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
901 assert(instr
->definitions
.size() == vec
->operands
.size());
902 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
903 Operand vec_op
= vec
->operands
[i
];
904 if (vec_op
.isConstant()) {
905 if (vec_op
.isLiteral())
906 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
907 else if (vec_op
.size() == 1)
908 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
909 else if (vec_op
.size() == 2)
910 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant_64bit(vec_op
.constantValue());
912 assert(vec_op
.isTemp());
913 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
918 case aco_opcode::p_extract_vector
: { /* mov */
919 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
921 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
922 if (vec
->definitions
[0].getTemp().size() == vec
->operands
.size() && /* TODO: what about 64bit or other combinations? */
923 vec
->operands
[0].size() == instr
->definitions
[0].size()) {
925 /* convert this extract into a mov instruction */
926 Operand vec_op
= vec
->operands
[instr
->operands
[1].constantValue()];
927 bool is_vgpr
= instr
->definitions
[0].getTemp().type() == RegType::vgpr
;
928 aco_opcode opcode
= is_vgpr
? aco_opcode::v_mov_b32
: aco_opcode::s_mov_b32
;
929 Format format
= is_vgpr
? Format::VOP1
: Format::SOP1
;
930 instr
->opcode
= opcode
;
931 instr
->format
= format
;
932 while (instr
->operands
.size() > 1)
933 instr
->operands
.pop_back();
934 instr
->operands
[0] = vec_op
;
936 if (vec_op
.isConstant()) {
937 if (vec_op
.isLiteral())
938 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(vec_op
.constantValue());
939 else if (vec_op
.size() == 1)
940 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(vec_op
.constantValue());
941 else if (vec_op
.size() == 2)
942 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(vec_op
.constantValue());
945 assert(vec_op
.isTemp());
946 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vec_op
.getTemp());
951 case aco_opcode::s_mov_b32
: /* propagate */
952 case aco_opcode::s_mov_b64
:
953 case aco_opcode::v_mov_b32
:
954 case aco_opcode::p_as_uniform
:
955 if (instr
->definitions
[0].isFixed()) {
956 /* don't copy-propagate copies into fixed registers */
957 } else if (instr
->usesModifiers()) {
959 } else if (instr
->operands
[0].isConstant()) {
960 if (instr
->operands
[0].isLiteral())
961 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
962 else if (instr
->operands
[0].size() == 1)
963 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
964 else if (instr
->operands
[0].size() == 2)
965 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(instr
->operands
[0].constantValue());
966 } else if (instr
->operands
[0].isTemp()) {
967 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
969 assert(instr
->operands
[0].isFixed());
972 case aco_opcode::p_is_helper
:
973 if (!ctx
.program
->needs_wqm
)
974 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
976 case aco_opcode::s_movk_i32
: {
977 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
978 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
979 if (v
<= 64 || v
>= 0xfffffff0)
980 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
982 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
985 case aco_opcode::v_bfrev_b32
:
986 case aco_opcode::s_brev_b32
: {
987 if (instr
->operands
[0].isConstant()) {
988 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
989 if (v
<= 64 || v
>= 0xfffffff0)
990 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
992 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
996 case aco_opcode::s_bfm_b32
: {
997 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
998 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
999 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
1000 uint32_t v
= ((1u << size
) - 1u) << start
;
1001 if (v
<= 64 || v
>= 0xfffffff0)
1002 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1004 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1007 case aco_opcode::v_mul_f32
: { /* omod */
1008 /* TODO: try to move the negate/abs modifier to the consumer instead */
1009 if (instr
->usesModifiers())
1012 for (unsigned i
= 0; i
< 2; i
++) {
1013 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
1014 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
1015 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
1016 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
1017 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
1018 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
1019 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
1020 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000 &&
1021 !block
.fp_mode
.must_flush_denorms32
) { /* 1.0 */
1022 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
1031 case aco_opcode::v_and_b32
: /* abs */
1032 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x7FFFFFFF) &&
1033 instr
->operands
[1].isTemp() && instr
->operands
[1].getTemp().type() == RegType::vgpr
)
1034 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
1036 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1038 case aco_opcode::v_xor_b32
: { /* neg */
1039 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
1040 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
1041 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1042 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
1043 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
1044 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1045 instr
->opcode
= aco_opcode::v_or_b32
;
1046 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
1048 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
1052 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1056 case aco_opcode::v_med3_f32
: { /* clamp */
1057 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1058 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1059 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1060 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1064 bool found_zero
= false, found_one
= false;
1065 for (unsigned i
= 0; i
< 3; i
++)
1067 if (instr
->operands
[i
].constantEquals(0))
1069 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1074 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1075 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1079 case aco_opcode::v_cndmask_b32
:
1080 if (instr
->operands
[0].constantEquals(0) &&
1081 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
1082 instr
->operands
[2].isTemp())
1083 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1084 else if (instr
->operands
[0].constantEquals(0) &&
1085 instr
->operands
[1].constantEquals(0x3f800000u
) &&
1086 instr
->operands
[2].isTemp())
1087 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1089 case aco_opcode::v_cmp_lg_u32
:
1090 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1091 instr
->operands
[0].constantEquals(0) &&
1092 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1093 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1095 case aco_opcode::p_phi
:
1096 case aco_opcode::p_linear_phi
: {
1097 /* lower_bool_phis() can create phis like this */
1098 bool all_same_temp
= instr
->operands
[0].isTemp();
1099 /* this check is needed when moving uniform loop counters out of a divergent loop */
1101 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1102 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1103 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1104 all_same_temp
= false;
1106 if (all_same_temp
) {
1107 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1109 bool all_undef
= instr
->operands
[0].isUndefined();
1110 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1111 if (!instr
->operands
[i
].isUndefined())
1115 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1119 case aco_opcode::v_add_u32
:
1120 case aco_opcode::v_add_co_u32
:
1121 case aco_opcode::s_add_i32
:
1122 case aco_opcode::s_add_u32
:
1123 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1125 case aco_opcode::s_not_b32
:
1126 case aco_opcode::s_not_b64
:
1127 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1128 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1129 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1130 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1131 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1132 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1134 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1136 case aco_opcode::s_and_b32
:
1137 case aco_opcode::s_and_b64
:
1138 if (instr
->operands
[1].isFixed() && instr
->operands
[1].physReg() == exec
&& instr
->operands
[0].isTemp()) {
1139 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1140 /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
1141 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1142 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1144 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1145 /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
1146 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1147 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1152 case aco_opcode::s_or_b32
:
1153 case aco_opcode::s_or_b64
:
1154 case aco_opcode::s_xor_b32
:
1155 case aco_opcode::s_xor_b64
:
1156 if (std::all_of(instr
->operands
.begin(), instr
->operands
.end(), [&ctx
](const Operand
& op
) {
1157 return op
.isTemp() && (ctx
.info
[op
.tempId()].is_uniform_bool() || ctx
.info
[op
.tempId()].is_uniform_bitwise());
1159 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1162 case aco_opcode::s_lshl_b32
:
1163 case aco_opcode::v_or_b32
:
1164 case aco_opcode::v_lshlrev_b32
:
1165 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1167 case aco_opcode::v_min_f32
:
1168 case aco_opcode::v_min_f16
:
1169 case aco_opcode::v_min_u32
:
1170 case aco_opcode::v_min_i32
:
1171 case aco_opcode::v_min_u16
:
1172 case aco_opcode::v_min_i16
:
1173 case aco_opcode::v_max_f32
:
1174 case aco_opcode::v_max_f16
:
1175 case aco_opcode::v_max_u32
:
1176 case aco_opcode::v_max_i32
:
1177 case aco_opcode::v_max_u16
:
1178 case aco_opcode::v_max_i16
:
1179 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1181 case aco_opcode::v_cmp_lt_f32
:
1182 case aco_opcode::v_cmp_eq_f32
:
1183 case aco_opcode::v_cmp_le_f32
:
1184 case aco_opcode::v_cmp_gt_f32
:
1185 case aco_opcode::v_cmp_lg_f32
:
1186 case aco_opcode::v_cmp_ge_f32
:
1187 case aco_opcode::v_cmp_o_f32
:
1188 case aco_opcode::v_cmp_u_f32
:
1189 case aco_opcode::v_cmp_nge_f32
:
1190 case aco_opcode::v_cmp_nlg_f32
:
1191 case aco_opcode::v_cmp_ngt_f32
:
1192 case aco_opcode::v_cmp_nle_f32
:
1193 case aco_opcode::v_cmp_neq_f32
:
1194 case aco_opcode::v_cmp_nlt_f32
:
1195 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1197 case aco_opcode::s_cselect_b64
:
1198 case aco_opcode::s_cselect_b32
:
1199 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1200 instr
->operands
[1].constantEquals(0)) {
1201 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1202 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1204 if (instr
->operands
[2].isTemp() && ctx
.info
[instr
->operands
[2].tempId()].is_scc_invert()) {
1205 /* Flip the operands to get rid of the scc_invert instruction */
1206 std::swap(instr
->operands
[0], instr
->operands
[1]);
1207 instr
->operands
[2].setTemp(ctx
.info
[instr
->operands
[2].tempId()].temp
);
1210 case aco_opcode::p_wqm
:
1211 if (instr
->operands
[0].isTemp() &&
1212 ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1213 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1221 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1223 *ordered
= *unordered
= op
;
1225 #define CMP(ord, unord) \
1226 case aco_opcode::v_cmp_##ord##_f32:\
1227 case aco_opcode::v_cmp_n##unord##_f32:\
1228 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1229 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1230 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1244 aco_opcode
get_ordered(aco_opcode op
)
1246 aco_opcode ordered
, unordered
, inverse
;
1247 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1250 aco_opcode
get_unordered(aco_opcode op
)
1252 aco_opcode ordered
, unordered
, inverse
;
1253 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1256 aco_opcode
get_inverse(aco_opcode op
)
1258 aco_opcode ordered
, unordered
, inverse
;
1259 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1262 bool is_cmp(aco_opcode op
)
1264 aco_opcode ordered
, unordered
, inverse
;
1265 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1268 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1270 if (ctx
.info
[tmp
.id()].is_temp())
1271 return ctx
.info
[tmp
.id()].temp
.id();
1276 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1278 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1279 for (const Operand
& op
: instr
->operands
) {
1281 ctx
.uses
[op
.tempId()]--;
1286 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1288 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1290 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1293 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1295 if (instr
->definitions
.size() == 2) {
1296 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1297 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1304 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1305 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1306 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1308 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1310 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1313 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1315 bool neg
[2] = {false, false};
1316 bool abs
[2] = {false, false};
1318 Instruction
*op_instr
[2];
1321 for (unsigned i
= 0; i
< 2; i
++) {
1322 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1326 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1328 if (op_instr
[i
]->opcode
!= expected_cmp
)
1330 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1333 if (op_instr
[i
]->isVOP3()) {
1334 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1335 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1337 neg
[i
] = vop3
->neg
[0];
1338 abs
[i
] = vop3
->abs
[0];
1339 opsel
|= (vop3
->opsel
& 1) << i
;
1342 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1343 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1344 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1350 if (op
[1].type() == RegType::sgpr
)
1351 std::swap(op
[0], op
[1]);
1352 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1353 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1356 ctx
.uses
[op
[0].id()]++;
1357 ctx
.uses
[op
[1].id()]++;
1358 decrease_uses(ctx
, op_instr
[0]);
1359 decrease_uses(ctx
, op_instr
[1]);
1361 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1362 Instruction
*new_instr
;
1363 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1364 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1365 for (unsigned i
= 0; i
< 2; i
++) {
1366 vop3
->neg
[i
] = neg
[i
];
1367 vop3
->abs
[i
] = abs
[i
];
1369 vop3
->opsel
= opsel
;
1370 new_instr
= static_cast<Instruction
*>(vop3
);
1372 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1374 new_instr
->operands
[0] = Operand(op
[0]);
1375 new_instr
->operands
[1] = Operand(op
[1]);
1376 new_instr
->definitions
[0] = instr
->definitions
[0];
1378 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1379 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1381 instr
.reset(new_instr
);
1386 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1387 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1388 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1390 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1392 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1395 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1396 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1398 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1399 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1400 if (!nan_test
|| !cmp
)
1403 if (cmp
->opcode
== expected_nan_test
)
1404 std::swap(nan_test
, cmp
);
1405 else if (nan_test
->opcode
!= expected_nan_test
)
1408 if (!is_cmp(cmp
->opcode
))
1411 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1413 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1416 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1417 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1418 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1419 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1420 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1422 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1425 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1426 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1427 decrease_uses(ctx
, nan_test
);
1428 decrease_uses(ctx
, cmp
);
1430 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1431 Instruction
*new_instr
;
1432 if (cmp
->isVOP3()) {
1433 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1434 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1435 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1436 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1437 new_vop3
->clamp
= cmp_vop3
->clamp
;
1438 new_vop3
->omod
= cmp_vop3
->omod
;
1439 new_vop3
->opsel
= cmp_vop3
->opsel
;
1440 new_instr
= new_vop3
;
1442 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1444 new_instr
->operands
[0] = cmp
->operands
[0];
1445 new_instr
->operands
[1] = cmp
->operands
[1];
1446 new_instr
->definitions
[0] = instr
->definitions
[0];
1448 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1449 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1451 instr
.reset(new_instr
);
1456 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1457 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1458 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1460 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1462 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1465 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1467 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1468 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1470 if (!nan_test
|| !cmp
)
1473 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1474 if (cmp
->opcode
== expected_nan_test
)
1475 std::swap(nan_test
, cmp
);
1476 else if (nan_test
->opcode
!= expected_nan_test
)
1479 if (!is_cmp(cmp
->opcode
))
1482 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1484 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1487 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1488 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1489 if (prop_nan0
!= prop_nan1
)
1492 if (nan_test
->isVOP3()) {
1493 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1494 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1498 int constant_operand
= -1;
1499 for (unsigned i
= 0; i
< 2; i
++) {
1500 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1501 constant_operand
= !i
;
1505 if (constant_operand
== -1)
1509 if (cmp
->operands
[constant_operand
].isConstant()) {
1510 constant
= cmp
->operands
[constant_operand
].constantValue();
1511 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1512 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1513 unsigned id
= original_temp_id(ctx
, tmp
);
1514 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1516 constant
= ctx
.info
[id
].val
;
1522 memcpy(&constantf
, &constant
, 4);
1523 if (isnan(constantf
))
1526 if (cmp
->operands
[0].isTemp())
1527 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1528 if (cmp
->operands
[1].isTemp())
1529 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1530 decrease_uses(ctx
, nan_test
);
1531 decrease_uses(ctx
, cmp
);
1533 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1534 Instruction
*new_instr
;
1535 if (cmp
->isVOP3()) {
1536 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1537 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1538 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1539 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1540 new_vop3
->clamp
= cmp_vop3
->clamp
;
1541 new_vop3
->omod
= cmp_vop3
->omod
;
1542 new_vop3
->opsel
= cmp_vop3
->opsel
;
1543 new_instr
= new_vop3
;
1545 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1547 new_instr
->operands
[0] = cmp
->operands
[0];
1548 new_instr
->operands
[1] = cmp
->operands
[1];
1549 new_instr
->definitions
[0] = instr
->definitions
[0];
1551 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1552 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1554 instr
.reset(new_instr
);
1559 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1560 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1562 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1564 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1566 if (!instr
->operands
[0].isTemp())
1569 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1573 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1574 if (new_opcode
== aco_opcode::last_opcode
)
1577 if (cmp
->operands
[0].isTemp())
1578 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1579 if (cmp
->operands
[1].isTemp())
1580 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1581 decrease_uses(ctx
, cmp
);
1583 Instruction
*new_instr
;
1584 if (cmp
->isVOP3()) {
1585 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1586 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1587 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1588 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1589 new_vop3
->clamp
= cmp_vop3
->clamp
;
1590 new_vop3
->omod
= cmp_vop3
->omod
;
1591 new_vop3
->opsel
= cmp_vop3
->opsel
;
1592 new_instr
= new_vop3
;
1594 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1596 new_instr
->operands
[0] = cmp
->operands
[0];
1597 new_instr
->operands
[1] = cmp
->operands
[1];
1598 new_instr
->definitions
[0] = instr
->definitions
[0];
1600 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1601 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1603 instr
.reset(new_instr
);
1608 /* op1(op2(1, 2), 0) if swap = false
1609 * op1(0, op2(1, 2)) if swap = true */
1610 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1611 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1612 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1613 bool *op1_clamp
, uint8_t *op1_omod
,
1614 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1617 if (op1_instr
->opcode
!= op1
)
1620 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1621 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1624 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1625 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1627 /* don't support inbetween clamp/omod */
1628 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1631 /* get operands and modifiers and check inbetween modifiers */
1632 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1633 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1636 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1637 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1641 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1642 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1645 if (inbetween_opsel
)
1646 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1647 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1651 shuffle
[shuffle_str
[0] - '0'] = 0;
1652 shuffle
[shuffle_str
[1] - '0'] = 1;
1653 shuffle
[shuffle_str
[2] - '0'] = 2;
1655 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1656 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1657 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1658 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1659 *opsel
|= 1 << shuffle
[0];
1661 for (unsigned i
= 0; i
< 2; i
++) {
1662 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1663 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1664 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1665 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1666 *opsel
|= 1 << shuffle
[i
+ 1];
1669 /* check operands */
1670 if (!check_vop3_operands(ctx
, 3, operands
))
1676 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1677 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1678 bool clamp
, unsigned omod
)
1680 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1681 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1682 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1683 new_instr
->clamp
= clamp
;
1684 new_instr
->omod
= omod
;
1685 new_instr
->opsel
= opsel
;
1686 new_instr
->operands
[0] = operands
[0];
1687 new_instr
->operands
[1] = operands
[1];
1688 new_instr
->operands
[2] = operands
[2];
1689 new_instr
->definitions
[0] = instr
->definitions
[0];
1690 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1692 instr
.reset(new_instr
);
1695 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1697 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1698 (label_omod_success
| label_clamp_success
);
1700 for (unsigned swap
= 0; swap
< 2; swap
++) {
1701 if (!((1 << swap
) & ops
))
1704 Operand operands
[3];
1705 bool neg
[3], abs
[3], clamp
;
1706 uint8_t opsel
= 0, omod
= 0;
1707 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1708 instr
.get(), swap
, shuffle
,
1709 operands
, neg
, abs
, &opsel
,
1710 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1711 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1712 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1713 if (omod_clamp
& label_omod_success
)
1714 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1715 if (omod_clamp
& label_clamp_success
)
1716 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1723 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
1725 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
1728 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1729 (label_omod_success
| label_clamp_success
);
1731 /* min(-max(a, b), c) -> min3(-a, -b, c) *
1732 * max(-min(a, b), c) -> max3(-a, -b, c) */
1733 for (unsigned swap
= 0; swap
< 2; swap
++) {
1734 Operand operands
[3];
1735 bool neg
[3], abs
[3], clamp
;
1736 uint8_t opsel
= 0, omod
= 0;
1738 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
1739 instr
.get(), swap
, "012",
1740 operands
, neg
, abs
, &opsel
,
1741 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
1743 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1746 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1747 if (omod_clamp
& label_omod_success
)
1748 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1749 if (omod_clamp
& label_clamp_success
)
1750 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1757 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1758 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1759 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1760 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1761 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1762 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1763 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1766 if (!instr
->operands
[0].isTemp())
1768 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1771 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1774 switch (op2_instr
->opcode
) {
1775 case aco_opcode::s_and_b32
:
1776 case aco_opcode::s_or_b32
:
1777 case aco_opcode::s_xor_b32
:
1778 case aco_opcode::s_and_b64
:
1779 case aco_opcode::s_or_b64
:
1780 case aco_opcode::s_xor_b64
:
1786 /* create instruction */
1787 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1788 ctx
.uses
[instr
->operands
[0].tempId()]--;
1789 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1791 switch (op2_instr
->opcode
) {
1792 case aco_opcode::s_and_b32
:
1793 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1795 case aco_opcode::s_or_b32
:
1796 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1798 case aco_opcode::s_xor_b32
:
1799 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1801 case aco_opcode::s_and_b64
:
1802 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1804 case aco_opcode::s_or_b64
:
1805 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1807 case aco_opcode::s_xor_b64
:
1808 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1817 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1818 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1819 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1820 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1821 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1823 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1826 for (unsigned i
= 0; i
< 2; i
++) {
1827 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1828 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1831 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1832 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1835 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1836 instr
->operands
[0] = instr
->operands
[!i
];
1837 instr
->operands
[1] = op2_instr
->operands
[0];
1838 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1840 switch (instr
->opcode
) {
1841 case aco_opcode::s_and_b32
:
1842 instr
->opcode
= aco_opcode::s_andn2_b32
;
1844 case aco_opcode::s_or_b32
:
1845 instr
->opcode
= aco_opcode::s_orn2_b32
;
1847 case aco_opcode::s_and_b64
:
1848 instr
->opcode
= aco_opcode::s_andn2_b64
;
1850 case aco_opcode::s_or_b64
:
1851 instr
->opcode
= aco_opcode::s_orn2_b64
;
1862 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1863 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1865 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1868 for (unsigned i
= 0; i
< 2; i
++) {
1869 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1870 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
|| !op2_instr
->operands
[1].isConstant())
1873 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1874 if (shift
< 1 || shift
> 4)
1877 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1878 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1881 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1882 instr
->operands
[1] = instr
->operands
[!i
];
1883 instr
->operands
[0] = op2_instr
->operands
[0];
1884 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1886 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1887 aco_opcode::s_lshl2_add_u32
,
1888 aco_opcode::s_lshl3_add_u32
,
1889 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1896 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1899 #define MINMAX(type, gfx9) \
1900 case aco_opcode::v_min_##type:\
1901 case aco_opcode::v_max_##type:\
1902 case aco_opcode::v_med3_##type:\
1903 *min = aco_opcode::v_min_##type;\
1904 *max = aco_opcode::v_max_##type;\
1905 *med3 = aco_opcode::v_med3_##type;\
1906 *min3 = aco_opcode::v_min3_##type;\
1907 *max3 = aco_opcode::v_max3_##type;\
1908 *some_gfx9_only = gfx9;\
1922 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1923 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1924 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1925 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1927 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
1928 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
1929 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
1930 aco_opcode other_op
;
1931 if (instr
->opcode
== min
)
1933 else if (instr
->opcode
== max
)
1938 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1939 (label_omod_success
| label_clamp_success
);
1941 for (unsigned swap
= 0; swap
< 2; swap
++) {
1942 Operand operands
[3];
1943 bool neg
[3], abs
[3], clamp
;
1944 uint8_t opsel
= 0, omod
= 0;
1945 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1946 "012", operands
, neg
, abs
, &opsel
,
1947 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1948 int const0_idx
= -1, const1_idx
= -1;
1949 uint32_t const0
= 0, const1
= 0;
1950 for (int i
= 0; i
< 3; i
++) {
1952 if (operands
[i
].isConstant()) {
1953 val
= operands
[i
].constantValue();
1954 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
1955 val
= ctx
.info
[operands
[i
].tempId()].val
;
1959 if (const0_idx
>= 0) {
1967 if (const0_idx
< 0 || const1_idx
< 0)
1970 if (opsel
& (1 << const0_idx
))
1972 if (opsel
& (1 << const1_idx
))
1975 int lower_idx
= const0_idx
;
1977 case aco_opcode::v_min_f32
:
1978 case aco_opcode::v_min_f16
: {
1979 float const0_f
, const1_f
;
1980 if (min
== aco_opcode::v_min_f32
) {
1981 memcpy(&const0_f
, &const0
, 4);
1982 memcpy(&const1_f
, &const1
, 4);
1984 const0_f
= _mesa_half_to_float(const0
);
1985 const1_f
= _mesa_half_to_float(const1
);
1987 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
1988 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
1989 if (neg
[const0_idx
]) const0_f
= -const0_f
;
1990 if (neg
[const1_idx
]) const1_f
= -const1_f
;
1991 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
1994 case aco_opcode::v_min_u32
: {
1995 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
1998 case aco_opcode::v_min_u16
: {
1999 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
2002 case aco_opcode::v_min_i32
: {
2003 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
2004 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
2005 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2008 case aco_opcode::v_min_i16
: {
2009 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
2010 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
2011 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2017 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
2019 if (instr
->opcode
== min
) {
2020 if (upper_idx
!= 0 || lower_idx
== 0)
2023 if (upper_idx
== 0 || lower_idx
!= 0)
2027 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2028 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2029 if (omod_clamp
& label_omod_success
)
2030 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2031 if (omod_clamp
& label_clamp_success
)
2032 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2042 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2044 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2045 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2046 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2048 /* find candidates and create the set of sgprs already read */
2049 unsigned sgpr_ids
[2] = {0, 0};
2050 uint32_t operand_mask
= 0;
2051 bool has_literal
= false;
2052 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2053 if (instr
->operands
[i
].isLiteral())
2055 if (!instr
->operands
[i
].isTemp())
2057 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2058 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
2059 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
2061 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
2062 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
2063 operand_mask
|= 1u << i
;
2065 unsigned max_sgprs
= 1;
2066 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2071 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2073 /* keep on applying sgprs until there is nothing left to be done */
2074 while (operand_mask
) {
2075 uint32_t sgpr_idx
= 0;
2076 uint32_t sgpr_info_id
= 0;
2077 uint32_t mask
= operand_mask
;
2080 unsigned i
= u_bit_scan(&mask
);
2081 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2082 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
2084 sgpr_info_id
= instr
->operands
[i
].tempId();
2087 operand_mask
&= ~(1u << sgpr_idx
);
2089 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2090 * definitively beneficial.
2091 * TODO: this is too conservative because later the use count could be reduced to 1 */
2092 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2095 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2096 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2097 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2100 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2101 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2102 } else if (can_swap_operands(instr
)) {
2103 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2104 instr
->operands
[0] = Operand(sgpr
);
2105 /* swap bits using a 4-entry LUT */
2106 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2107 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2108 } else if (can_use_VOP3(ctx
, instr
)) {
2109 to_VOP3(ctx
, instr
);
2110 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2116 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2117 ctx
.uses
[sgpr_info_id
]--;
2118 ctx
.uses
[sgpr
.id()]++;
2122 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2124 /* check if we could apply omod on predecessor */
2125 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
2126 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2127 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2129 unsigned idx
= op0
? 0 : 1;
2130 /* omod was successfully applied */
2131 /* if the omod instruction is v_mad, we also have to change the original add */
2132 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2133 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2134 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2135 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2136 add_instr
->definitions
[0] = instr
->definitions
[0];
2139 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2140 /* check if we have an additional clamp modifier */
2141 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2142 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2143 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2144 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2146 /* change definition ssa-id of modified instruction */
2147 omod_instr
->definitions
[0] = instr
->definitions
[0];
2149 /* change the definition of instr to something unused, e.g. the original omod def */
2150 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2151 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2154 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2155 /* in all other cases, label this instruction as option for multiply-add */
2156 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2160 /* check if we could apply clamp on predecessor */
2161 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
2163 bool found_zero
= false, found_one
= false;
2164 for (unsigned i
= 0; i
< 3; i
++)
2166 if (instr
->operands
[i
].constantEquals(0))
2168 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
2173 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2174 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2175 /* clamp was successfully applied */
2176 /* if the clamp instruction is v_mad, we also have to change the original add */
2177 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2178 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2179 add_instr
->definitions
[0] = instr
->definitions
[0];
2181 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2182 /* change definition ssa-id of modified instruction */
2183 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2185 /* change the definition of instr to something unused, e.g. the original omod def */
2186 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2187 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2192 /* omod has no effect if denormals are enabled */
2193 bool can_use_omod
= block
.fp_mode
.denorm32
== 0;
2195 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2196 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2197 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2198 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2199 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2200 to_VOP3(ctx
, instr
);
2201 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2202 def_info
.set_omod_success(instr
.get());
2203 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2204 to_VOP3(ctx
, instr
);
2205 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2206 def_info
.set_omod_success(instr
.get());
2207 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2208 to_VOP3(ctx
, instr
);
2209 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2210 def_info
.set_omod_success(instr
.get());
2211 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2212 to_VOP3(ctx
, instr
);
2213 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2214 def_info
.set_clamp_success(instr
.get());
2221 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2222 // this would mean that we'd have to fix the instruction uses while value propagation
2224 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2226 if (instr
->definitions
.empty() || is_dead(ctx
.uses
, instr
.get()))
2229 if (instr
->isVALU()) {
2230 if (can_apply_sgprs(instr
))
2231 apply_sgprs(ctx
, instr
);
2232 if (apply_omod_clamp(ctx
, block
, instr
))
2236 /* TODO: There are still some peephole optimizations that could be done:
2237 * - abs(a - b) -> s_absdiff_i32
2238 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2239 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2240 * These aren't probably too interesting though.
2241 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2242 * probably more useful than the previously mentioned optimizations.
2243 * The various comparison optimizations also currently only work with 32-bit
2246 /* neg(mul(a, b)) -> mul(neg(a), b) */
2247 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2248 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2250 if (!ctx
.info
[val
.id()].is_mul())
2253 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2255 if (mul_instr
->operands
[0].isLiteral())
2257 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2260 /* convert to mul(neg(a), b) */
2261 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2262 Definition def
= instr
->definitions
[0];
2263 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2264 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2265 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2266 instr
->operands
[0] = mul_instr
->operands
[0];
2267 instr
->operands
[1] = mul_instr
->operands
[1];
2268 instr
->definitions
[0] = def
;
2269 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2270 if (mul_instr
->isVOP3()) {
2271 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2272 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2273 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2274 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2275 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2276 new_mul
->omod
= mul
->omod
;
2278 new_mul
->neg
[0] ^= true;
2279 new_mul
->clamp
= false;
2281 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2284 /* combine mul+add -> mad */
2285 else if ((instr
->opcode
== aco_opcode::v_add_f32
||
2286 instr
->opcode
== aco_opcode::v_sub_f32
||
2287 instr
->opcode
== aco_opcode::v_subrev_f32
) &&
2288 block
.fp_mode
.denorm32
== 0 && !block
.fp_mode
.preserve_signed_zero_inf_nan32
) {
2289 //TODO: we could use fma instead when denormals are enabled if the NIR isn't marked as precise
2291 uint32_t uses_src0
= UINT32_MAX
;
2292 uint32_t uses_src1
= UINT32_MAX
;
2293 Instruction
* mul_instr
= nullptr;
2294 unsigned add_op_idx
;
2295 /* check if any of the operands is a multiplication */
2296 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2297 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2298 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2299 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2301 /* find the 'best' mul instruction to combine with the add */
2302 if (uses_src0
< uses_src1
) {
2303 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2305 } else if (uses_src1
< uses_src0
) {
2306 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2308 } else if (uses_src0
!= UINT32_MAX
) {
2309 /* tiebreaker: quite random what to pick */
2310 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2311 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2314 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2319 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2320 bool neg
[3] = {false, false, false};
2321 bool abs
[3] = {false, false, false};
2324 op
[0] = mul_instr
->operands
[0];
2325 op
[1] = mul_instr
->operands
[1];
2326 op
[2] = instr
->operands
[add_op_idx
];
2327 // TODO: would be better to check this before selecting a mul instr?
2328 if (!check_vop3_operands(ctx
, 3, op
))
2331 if (mul_instr
->isVOP3()) {
2332 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2333 neg
[0] = vop3
->neg
[0];
2334 neg
[1] = vop3
->neg
[1];
2335 abs
[0] = vop3
->abs
[0];
2336 abs
[1] = vop3
->abs
[1];
2337 /* we cannot use these modifiers between mul and add */
2338 if (vop3
->clamp
|| vop3
->omod
)
2342 /* convert to mad */
2343 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2344 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2346 ctx
.uses
[op
[0].tempId()]++;
2348 ctx
.uses
[op
[1].tempId()]++;
2351 if (instr
->isVOP3()) {
2352 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2353 neg
[2] = vop3
->neg
[add_op_idx
];
2354 abs
[2] = vop3
->abs
[add_op_idx
];
2356 clamp
= vop3
->clamp
;
2357 /* abs of the multiplication result */
2358 if (vop3
->abs
[1 - add_op_idx
]) {
2364 /* neg of the multiplication result */
2365 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2367 if (instr
->opcode
== aco_opcode::v_sub_f32
)
2368 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2369 else if (instr
->opcode
== aco_opcode::v_subrev_f32
)
2370 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2372 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2373 for (unsigned i
= 0; i
< 3; i
++)
2375 mad
->operands
[i
] = op
[i
];
2376 mad
->neg
[i
] = neg
[i
];
2377 mad
->abs
[i
] = abs
[i
];
2381 mad
->definitions
[0] = instr
->definitions
[0];
2383 /* mark this ssa_def to be re-checked for profitability and literals */
2384 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2385 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2386 instr
.reset(mad
.release());
2390 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2391 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2392 for (unsigned i
= 0; i
< 2; i
++) {
2393 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2394 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2395 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2396 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2397 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2399 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2400 new_instr
->operands
[0] = Operand(0u);
2401 new_instr
->operands
[1] = instr
->operands
[!i
];
2402 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2403 new_instr
->definitions
[0] = instr
->definitions
[0];
2404 instr
.reset(new_instr
.release());
2405 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2409 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2410 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2411 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2412 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2413 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2414 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2415 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2416 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2417 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2418 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2419 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2420 combine_salu_lshl_add(ctx
, instr
);
2421 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2422 combine_salu_not_bitwise(ctx
, instr
);
2423 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2424 if (combine_inverse_comparison(ctx
, instr
)) ;
2425 else combine_salu_not_bitwise(ctx
, instr
);
2426 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2427 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2428 if (combine_ordering_test(ctx
, instr
)) ;
2429 else if (combine_comparison_ordering(ctx
, instr
)) ;
2430 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2431 else combine_salu_n2(ctx
, instr
);
2433 aco_opcode min
, max
, min3
, max3
, med3
;
2434 bool some_gfx9_only
;
2435 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2436 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2437 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2438 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2444 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2446 const uint32_t threshold
= 4;
2448 if (is_dead(ctx
.uses
, instr
.get())) {
2453 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2454 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2455 unsigned num_used
= 0;
2457 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2458 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2464 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2465 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2466 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2470 for (Operand
& vec_op
: vec
->operands
) {
2471 if (off
== idx
* instr
->definitions
[0].size()) {
2475 off
+= vec_op
.size();
2477 if (off
!= instr
->operands
[0].size()) {
2478 ctx
.uses
[instr
->operands
[0].tempId()]--;
2479 for (Operand
& vec_op
: vec
->operands
) {
2480 if (vec_op
.isTemp())
2481 ctx
.uses
[vec_op
.tempId()]--;
2484 ctx
.uses
[op
.tempId()]++;
2486 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2487 extract
->operands
[0] = op
;
2488 extract
->definitions
[0] = instr
->definitions
[idx
];
2489 instr
.reset(extract
.release());
2495 if (!done
&& num_used
== 1) {
2496 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2497 extract
->operands
[0] = instr
->operands
[0];
2498 extract
->operands
[1] = Operand((uint32_t) idx
);
2499 extract
->definitions
[0] = instr
->definitions
[idx
];
2500 instr
.reset(extract
.release());
2504 mad_info
* mad_info
= NULL
;
2505 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2506 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2507 /* re-check mad instructions */
2508 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2509 ctx
.uses
[mad_info
->mul_temp_id
]++;
2510 if (instr
->operands
[0].isTemp())
2511 ctx
.uses
[instr
->operands
[0].tempId()]--;
2512 if (instr
->operands
[1].isTemp())
2513 ctx
.uses
[instr
->operands
[1].tempId()]--;
2514 instr
.swap(mad_info
->add_instr
);
2517 /* check literals */
2518 else if (!instr
->usesModifiers()) {
2519 bool sgpr_used
= false;
2520 uint32_t literal_idx
= 0;
2521 uint32_t literal_uses
= UINT32_MAX
;
2522 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2524 if (instr
->operands
[i
].isConstant() && i
> 0) {
2525 literal_uses
= UINT32_MAX
;
2528 if (!instr
->operands
[i
].isTemp())
2530 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2531 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2532 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2533 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2536 literal_uses
= UINT32_MAX
;
2539 /* don't break because we still need to check constants */
2540 } else if (!sgpr_used
&&
2541 ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2542 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2543 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2547 if (literal_uses
< threshold
) {
2548 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2549 mad_info
->check_literal
= true;
2550 mad_info
->literal_idx
= literal_idx
;
2556 /* check for literals */
2557 if (!instr
->isSALU() && !instr
->isVALU())
2560 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
2561 return; /* some encodings can't ever take literals */
2563 /* we do not apply the literals yet as we don't know if it is profitable */
2564 Operand
current_literal(s1
);
2566 unsigned literal_id
= 0;
2567 unsigned literal_uses
= UINT32_MAX
;
2568 Operand
literal(s1
);
2569 unsigned num_operands
= 1;
2570 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
2571 num_operands
= instr
->operands
.size();
2573 unsigned sgpr_ids
[2] = {0, 0};
2574 bool is_literal_sgpr
= false;
2577 /* choose a literal to apply */
2578 for (unsigned i
= 0; i
< num_operands
; i
++) {
2579 Operand op
= instr
->operands
[i
];
2580 if (op
.isLiteral()) {
2581 current_literal
= op
;
2583 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal()) {
2584 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
2585 op
.tempId() != sgpr_ids
[0])
2586 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
2590 if (!can_accept_constant(instr
, i
))
2593 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
2594 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
2596 literal
= Operand(ctx
.info
[op
.tempId()].val
);
2597 literal_uses
= ctx
.uses
[op
.tempId()];
2598 literal_id
= op
.tempId();
2601 mask
|= (op
.tempId() == literal_id
) << i
;
2605 /* don't go over the constant bus limit */
2606 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2607 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2608 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2609 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
2610 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2611 const_bus_limit
= 2;
2613 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2614 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
2617 if (literal_id
&& literal_uses
< threshold
&&
2618 (current_literal
.isUndefined() ||
2619 (current_literal
.size() == literal
.size() &&
2620 current_literal
.constantValue() == literal
.constantValue()))) {
2621 /* mark the literal to be applied */
2623 unsigned i
= u_bit_scan(&mask
);
2624 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
2625 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2631 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2633 /* Cleanup Dead Instructions */
2637 /* apply literals on MAD */
2638 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2639 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2640 if (info
->check_literal
&& ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0) {
2641 aco_ptr
<Instruction
> new_mad
;
2642 if (info
->literal_idx
== 2) { /* add literal -> madak */
2643 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2644 new_mad
->operands
[0] = instr
->operands
[0];
2645 new_mad
->operands
[1] = instr
->operands
[1];
2646 } else { /* mul literal -> madmk */
2647 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2648 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2649 new_mad
->operands
[1] = instr
->operands
[2];
2651 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2652 new_mad
->definitions
[0] = instr
->definitions
[0];
2653 ctx
.instructions
.emplace_back(std::move(new_mad
));
2658 /* apply literals on other SALU/VALU */
2659 if (instr
->isSALU() || instr
->isVALU()) {
2660 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2661 Operand op
= instr
->operands
[i
];
2662 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal() && ctx
.uses
[op
.tempId()] == 0) {
2663 Operand
literal(ctx
.info
[op
.tempId()].val
);
2664 if (instr
->isVALU() && i
> 0)
2665 to_VOP3(ctx
, instr
);
2666 instr
->operands
[i
] = literal
;
2671 ctx
.instructions
.emplace_back(std::move(instr
));
2675 void optimize(Program
* program
)
2678 ctx
.program
= program
;
2679 std::vector
<ssa_info
> info(program
->peekAllocationId());
2680 ctx
.info
= info
.data();
2682 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2683 for (Block
& block
: program
->blocks
) {
2684 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2685 label_instruction(ctx
, block
, instr
);
2688 ctx
.uses
= std::move(dead_code_analysis(program
));
2690 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2691 for (Block
& block
: program
->blocks
) {
2692 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2693 combine_instruction(ctx
, block
, instr
);
2696 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2697 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2698 Block
* block
= &(*it
);
2699 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2700 select_instruction(ctx
, *it
);
2703 /* 4. Add literals to instructions */
2704 for (Block
& block
: program
->blocks
) {
2705 ctx
.instructions
.clear();
2706 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2707 apply_literals(ctx
, instr
);
2708 block
.instructions
.swap(ctx
.instructions
);