2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant
= 1 << 1,
69 label_literal
= 1 << 6,
73 label_omod5
= 1 << 10,
74 label_omod_success
= 1 << 11,
75 label_clamp
= 1 << 12,
76 label_clamp_success
= 1 << 13,
77 label_undefined
= 1 << 14,
80 label_add_sub
= 1 << 17,
81 label_bitwise
= 1 << 18,
82 label_minmax
= 1 << 19,
84 label_uniform_bool
= 1 << 21,
85 label_constant_64bit
= 1 << 22,
86 label_uniform_bitwise
= 1 << 23,
87 label_scc_invert
= 1 << 24,
88 label_vcc_hint
= 1 << 25,
89 label_scc_needed
= 1 << 26,
93 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
|
94 label_add_sub
| label_bitwise
| label_uniform_bitwise
| label_minmax
| label_fcmp
;
95 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
|
96 label_omod2
| label_omod4
| label_omod5
| label_clamp
| label_scc_invert
| label_b2i
;
97 static constexpr uint32_t val_labels
= label_constant
| label_constant_64bit
| label_literal
| label_mad
;
107 ssa_info() : label(0) {}
109 void add_label(Label new_label
)
111 /* Since all labels which use "instr" use it for the same thing
112 * (indicating the defining instruction), there is no need to clear
113 * any other instr labels. */
114 if (new_label
& instr_labels
)
115 label
&= ~temp_labels
; /* instr and temp alias */
117 if (new_label
& temp_labels
) {
118 label
&= ~temp_labels
;
119 label
&= ~instr_labels
; /* instr and temp alias */
122 if (new_label
& val_labels
)
123 label
&= ~val_labels
;
128 void set_vec(Instruction
* vec
)
130 add_label(label_vec
);
136 return label
& label_vec
;
139 void set_constant(uint32_t constant
)
141 add_label(label_constant
);
147 return label
& label_constant
;
150 void set_constant_64bit(uint32_t constant
)
152 add_label(label_constant_64bit
);
156 bool is_constant_64bit()
158 return label
& label_constant_64bit
;
161 void set_abs(Temp abs_temp
)
163 add_label(label_abs
);
169 return label
& label_abs
;
172 void set_neg(Temp neg_temp
)
174 add_label(label_neg
);
180 return label
& label_neg
;
183 void set_neg_abs(Temp neg_abs_temp
)
185 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
189 void set_mul(Instruction
* mul
)
191 add_label(label_mul
);
197 return label
& label_mul
;
200 void set_temp(Temp tmp
)
202 add_label(label_temp
);
208 return label
& label_temp
;
211 void set_literal(uint32_t lit
)
213 add_label(label_literal
);
219 return label
& label_literal
;
222 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
224 add_label(label_mad
);
231 return label
& label_mad
;
234 void set_omod2(Temp def
)
236 add_label(label_omod2
);
242 return label
& label_omod2
;
245 void set_omod4(Temp def
)
247 add_label(label_omod4
);
253 return label
& label_omod4
;
256 void set_omod5(Temp def
)
258 add_label(label_omod5
);
264 return label
& label_omod5
;
267 void set_omod_success(Instruction
* omod_instr
)
269 add_label(label_omod_success
);
273 bool is_omod_success()
275 return label
& label_omod_success
;
278 void set_clamp(Temp def
)
280 add_label(label_clamp
);
286 return label
& label_clamp
;
289 void set_clamp_success(Instruction
* clamp_instr
)
291 add_label(label_clamp_success
);
295 bool is_clamp_success()
297 return label
& label_clamp_success
;
302 add_label(label_undefined
);
307 return label
& label_undefined
;
310 void set_vcc(Temp vcc
)
312 add_label(label_vcc
);
318 return label
& label_vcc
;
321 bool is_constant_or_literal()
323 return is_constant() || is_literal();
326 void set_b2f(Temp val
)
328 add_label(label_b2f
);
334 return label
& label_b2f
;
337 void set_add_sub(Instruction
*add_sub_instr
)
339 add_label(label_add_sub
);
340 instr
= add_sub_instr
;
345 return label
& label_add_sub
;
348 void set_bitwise(Instruction
*bitwise_instr
)
350 add_label(label_bitwise
);
351 instr
= bitwise_instr
;
356 return label
& label_bitwise
;
359 void set_uniform_bitwise()
361 add_label(label_uniform_bitwise
);
364 bool is_uniform_bitwise()
366 return label
& label_uniform_bitwise
;
369 void set_minmax(Instruction
*minmax_instr
)
371 add_label(label_minmax
);
372 instr
= minmax_instr
;
377 return label
& label_minmax
;
380 void set_fcmp(Instruction
*fcmp_instr
)
382 add_label(label_fcmp
);
388 return label
& label_fcmp
;
391 void set_scc_needed()
393 add_label(label_scc_needed
);
398 return label
& label_scc_needed
;
401 void set_scc_invert(Temp scc_inv
)
403 add_label(label_scc_invert
);
409 return label
& label_scc_invert
;
412 void set_uniform_bool(Temp uniform_bool
)
414 add_label(label_uniform_bool
);
418 bool is_uniform_bool()
420 return label
& label_uniform_bool
;
425 add_label(label_vcc_hint
);
430 return label
& label_vcc_hint
;
433 void set_b2i(Temp val
)
435 add_label(label_b2i
);
441 return label
& label_b2i
;
448 std::vector
<aco_ptr
<Instruction
>> instructions
;
450 std::pair
<uint32_t,Temp
> last_literal
;
451 std::vector
<mad_info
> mad_infos
;
452 std::vector
<uint16_t> uses
;
455 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
457 if (instr
->operands
[0].isConstant() ||
458 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
461 switch (instr
->opcode
) {
462 case aco_opcode::v_add_f32
:
463 case aco_opcode::v_mul_f32
:
464 case aco_opcode::v_or_b32
:
465 case aco_opcode::v_and_b32
:
466 case aco_opcode::v_xor_b32
:
467 case aco_opcode::v_max_f32
:
468 case aco_opcode::v_min_f32
:
469 case aco_opcode::v_max_i32
:
470 case aco_opcode::v_min_i32
:
471 case aco_opcode::v_max_u32
:
472 case aco_opcode::v_min_u32
:
473 case aco_opcode::v_cmp_eq_f32
:
474 case aco_opcode::v_cmp_lg_f32
:
476 case aco_opcode::v_sub_f32
:
477 instr
->opcode
= aco_opcode::v_subrev_f32
;
479 case aco_opcode::v_cmp_lt_f32
:
480 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
482 case aco_opcode::v_cmp_ge_f32
:
483 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
485 case aco_opcode::v_cmp_lt_i32
:
486 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
493 bool can_use_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
498 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
501 if (instr
->isDPP() || instr
->isSDWA())
504 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
505 instr
->opcode
!= aco_opcode::v_madak_f32
&&
506 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
507 instr
->opcode
!= aco_opcode::v_madak_f16
&&
508 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
509 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
510 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
511 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
512 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
513 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
514 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
517 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
519 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
520 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
521 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
522 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
523 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
526 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
531 aco_ptr
<Instruction
> tmp
= std::move(instr
);
532 Format format
= asVOP3(tmp
->format
);
533 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
534 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
535 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
536 instr
->definitions
[i
] = tmp
->definitions
[i
];
537 if (instr
->definitions
[i
].isTemp()) {
538 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
539 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
540 info
.instr
= instr
.get();
545 /* only covers special cases */
546 bool alu_can_accept_constant(aco_opcode opcode
, unsigned operand
)
549 case aco_opcode::v_interp_p2_f32
:
550 case aco_opcode::v_mac_f32
:
551 case aco_opcode::v_writelane_b32
:
552 case aco_opcode::v_writelane_b32_e64
:
553 case aco_opcode::v_cndmask_b32
:
555 case aco_opcode::s_addk_i32
:
556 case aco_opcode::s_mulk_i32
:
557 case aco_opcode::p_wqm
:
558 case aco_opcode::p_extract_vector
:
559 case aco_opcode::p_split_vector
:
560 case aco_opcode::v_readlane_b32
:
561 case aco_opcode::v_readlane_b32_e64
:
562 case aco_opcode::v_readfirstlane_b32
:
569 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
571 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
572 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
577 /* check constant bus and literal limitations */
578 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
580 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
581 Operand
literal32(s1
);
582 Operand
literal64(s2
);
583 unsigned num_sgprs
= 0;
584 unsigned sgpr
[] = {0, 0};
586 for (unsigned i
= 0; i
< num_operands
; i
++) {
587 Operand op
= operands
[i
];
589 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
590 /* two reads of the same SGPR count as 1 to the limit */
591 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
593 sgpr
[num_sgprs
++] = op
.tempId();
598 } else if (op
.isLiteral()) {
599 if (ctx
.program
->chip_class
< GFX10
)
602 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
604 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
607 /* Any number of 32-bit literals counts as only 1 to the limit. Same
608 * (but separately) for 64-bit literals. */
609 if (op
.size() == 1 && literal32
.isUndefined()) {
612 } else if (op
.size() == 2 && literal64
.isUndefined()) {
625 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
627 Operand op
= instr
->operands
[op_index
];
631 Temp tmp
= op
.getTemp();
632 if (!ctx
.info
[tmp
.id()].is_add_sub())
635 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
637 switch (add_instr
->opcode
) {
638 case aco_opcode::v_add_u32
:
639 case aco_opcode::v_add_co_u32
:
640 case aco_opcode::v_add_co_u32_e64
:
641 case aco_opcode::s_add_i32
:
642 case aco_opcode::s_add_u32
:
648 if (add_instr
->usesModifiers())
651 for (unsigned i
= 0; i
< 2; i
++) {
652 if (add_instr
->operands
[i
].isConstant()) {
653 *offset
= add_instr
->operands
[i
].constantValue();
654 } else if (add_instr
->operands
[i
].isTemp() &&
655 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
656 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
660 if (!add_instr
->operands
[!i
].isTemp())
663 uint32_t offset2
= 0;
664 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
667 *base
= add_instr
->operands
[!i
].getTemp();
675 Operand
get_constant_op(opt_ctx
&ctx
, uint32_t val
, bool is64bit
= false)
677 // TODO: this functions shouldn't be needed if we store Operand instead of value.
678 Operand
op(val
, is64bit
);
679 if (val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
680 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
684 bool fixed_to_exec(Operand op
)
686 return op
.isFixed() && op
.physReg() == exec
;
689 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
691 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
692 ASSERTED
bool all_const
= false;
693 for (Operand
& op
: instr
->operands
)
694 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
695 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
698 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
700 if (!instr
->operands
[i
].isTemp())
703 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
704 /* propagate undef */
705 if (info
.is_undefined() && is_phi(instr
))
706 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
707 /* propagate reg->reg of same type */
708 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
709 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
710 info
= ctx
.info
[info
.temp
.id()];
713 /* SALU / PSEUDO: propagate inline constants */
714 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
715 const bool is_subdword
= std::any_of(instr
->definitions
.begin(), instr
->definitions
.end(),
716 [] (const Definition
& def
) { return def
.regClass().is_subdword();});
717 // TODO: optimize SGPR and constant propagation for subdword pseudo instructions on gfx9+
721 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
722 instr
->operands
[i
].setTemp(info
.temp
);
723 info
= ctx
.info
[info
.temp
.id()];
724 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
725 /* propagate vgpr if it can take it */
726 switch (instr
->opcode
) {
727 case aco_opcode::p_create_vector
:
728 case aco_opcode::p_split_vector
:
729 case aco_opcode::p_extract_vector
:
730 case aco_opcode::p_phi
: {
731 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
732 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
734 instr
->operands
[i
] = Operand(info
.temp
);
735 info
= ctx
.info
[info
.temp
.id()];
743 if ((info
.is_constant() || info
.is_constant_64bit() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) &&
744 !instr
->operands
[i
].isFixed() && alu_can_accept_constant(instr
->opcode
, i
)) {
745 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
750 /* VALU: propagate neg, abs & inline constants */
751 else if (instr
->isVALU()) {
752 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
753 instr
->operands
[i
].setTemp(info
.temp
);
754 info
= ctx
.info
[info
.temp
.id()];
756 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
759 instr
->operands
[i
] = Operand(info
.temp
);
761 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
763 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
765 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
766 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
767 instr
->operands
[i
].setTemp(info
.temp
);
769 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
772 instr
->operands
[i
].setTemp(info
.temp
);
774 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
776 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
779 if ((info
.is_constant() || info
.is_constant_64bit()) && alu_can_accept_constant(instr
->opcode
, i
)) {
780 Operand op
= get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
781 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
782 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
783 instr
->operands
[i
] = op
;
785 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
786 instr
->operands
[i
] = instr
->operands
[0];
787 instr
->operands
[0] = op
;
789 } else if (can_use_VOP3(ctx
, instr
)) {
791 instr
->operands
[i
] = op
;
797 /* MUBUF: propagate constants and combine additions */
798 else if (instr
->format
== Format::MUBUF
) {
799 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
802 while (info
.is_temp())
803 info
= ctx
.info
[info
.temp
.id()];
805 if (mubuf
->offen
&& i
== 1 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
806 assert(!mubuf
->idxen
);
807 instr
->operands
[1] = Operand(v1
);
808 mubuf
->offset
+= info
.val
;
809 mubuf
->offen
= false;
811 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
812 instr
->operands
[2] = Operand((uint32_t) 0);
813 mubuf
->offset
+= info
.val
;
815 } else if (mubuf
->offen
&& i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
816 assert(!mubuf
->idxen
);
817 instr
->operands
[1].setTemp(base
);
818 mubuf
->offset
+= offset
;
820 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
821 instr
->operands
[i
].setTemp(base
);
822 mubuf
->offset
+= offset
;
827 /* DS: combine additions */
828 else if (instr
->format
== Format::DS
) {
830 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
833 bool has_usable_ds_offset
= ctx
.program
->chip_class
>= GFX7
;
834 if (has_usable_ds_offset
&&
835 i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) &&
836 base
.regClass() == instr
->operands
[i
].regClass() &&
837 instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
838 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
839 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
840 unsigned mask
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 0x7 : 0x3;
841 unsigned shifts
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 3 : 2;
843 if ((offset
& mask
) == 0 &&
844 ds
->offset0
+ (offset
>> shifts
) <= 255 &&
845 ds
->offset1
+ (offset
>> shifts
) <= 255) {
846 instr
->operands
[i
].setTemp(base
);
847 ds
->offset0
+= offset
>> shifts
;
848 ds
->offset1
+= offset
>> shifts
;
851 if (ds
->offset0
+ offset
<= 65535) {
852 instr
->operands
[i
].setTemp(base
);
853 ds
->offset0
+= offset
;
859 /* SMEM: propagate constants and combine additions */
860 else if (instr
->format
== Format::SMEM
) {
862 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
865 if (i
== 1 && info
.is_constant_or_literal() &&
866 ((ctx
.program
->chip_class
== GFX6
&& info
.val
<= 0x3FF) ||
867 (ctx
.program
->chip_class
== GFX7
&& info
.val
<= 0xFFFFFFFF) ||
868 (ctx
.program
->chip_class
>= GFX8
&& info
.val
<= 0xFFFFF))) {
869 instr
->operands
[i
] = Operand(info
.val
);
871 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
872 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
874 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
875 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
879 smem
->operands
[1] = Operand(offset
);
880 smem
->operands
.back() = Operand(base
);
882 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
883 new_instr
->operands
[0] = smem
->operands
[0];
884 new_instr
->operands
[1] = Operand(offset
);
885 if (smem
->definitions
.empty())
886 new_instr
->operands
[2] = smem
->operands
[2];
887 new_instr
->operands
.back() = Operand(base
);
888 if (!smem
->definitions
.empty())
889 new_instr
->definitions
[0] = smem
->definitions
[0];
890 new_instr
->can_reorder
= smem
->can_reorder
;
891 new_instr
->barrier
= smem
->barrier
;
892 new_instr
->glc
= smem
->glc
;
893 new_instr
->dlc
= smem
->dlc
;
894 new_instr
->nv
= smem
->nv
;
895 new_instr
->disable_wqm
= smem
->disable_wqm
;
896 instr
.reset(new_instr
);
897 smem
= static_cast<SMEM_instruction
*>(instr
.get());
903 else if (instr
->format
== Format::PSEUDO_BRANCH
) {
904 if (ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
905 /* Flip the branch instruction to get rid of the scc_invert instruction */
906 instr
->opcode
= instr
->opcode
== aco_opcode::p_cbranch_z
? aco_opcode::p_cbranch_nz
: aco_opcode::p_cbranch_z
;
907 instr
->operands
[0].setTemp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
912 /* if this instruction doesn't define anything, return */
913 if (instr
->definitions
.empty())
916 switch (instr
->opcode
) {
917 case aco_opcode::p_create_vector
: {
918 bool copy_prop
= instr
->operands
.size() == 1 && instr
->operands
[0].isTemp() &&
919 instr
->operands
[0].regClass() == instr
->definitions
[0].regClass();
921 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
925 unsigned num_ops
= instr
->operands
.size();
926 for (const Operand
& op
: instr
->operands
) {
927 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
928 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
930 if (num_ops
!= instr
->operands
.size()) {
931 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
932 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
933 instr
->definitions
[0] = old_vec
->definitions
[0];
935 for (Operand
& old_op
: old_vec
->operands
) {
936 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
937 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
938 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
939 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
940 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
941 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
942 instr
->operands
[k
++] = op
;
945 instr
->operands
[k
++] = old_op
;
948 assert(k
== num_ops
);
951 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
954 case aco_opcode::p_split_vector
: {
955 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
957 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
958 unsigned split_offset
= 0;
959 unsigned vec_offset
= 0;
960 unsigned vec_index
= 0;
961 for (unsigned i
= 0; i
< instr
->definitions
.size(); split_offset
+= instr
->definitions
[i
++].bytes()) {
962 while (vec_offset
< split_offset
&& vec_index
< vec
->operands
.size())
963 vec_offset
+= vec
->operands
[vec_index
++].bytes();
965 if (vec_offset
!= split_offset
|| vec
->operands
[vec_index
].bytes() != instr
->definitions
[i
].bytes())
968 Operand vec_op
= vec
->operands
[vec_index
];
969 if (vec_op
.isConstant()) {
970 if (vec_op
.isLiteral())
971 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
972 else if (vec_op
.size() == 1)
973 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
974 else if (vec_op
.size() == 2)
975 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant_64bit(vec_op
.constantValue());
976 } else if (vec_op
.isUndefined()) {
977 ctx
.info
[instr
->definitions
[i
].tempId()].set_undefined();
979 assert(vec_op
.isTemp());
980 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
985 case aco_opcode::p_extract_vector
: { /* mov */
986 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
989 /* check if we index directly into a vector element */
990 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
991 const unsigned index
= instr
->operands
[1].constantValue();
992 const unsigned dst_offset
= index
* instr
->definitions
[0].bytes();
995 for (const Operand
& op
: vec
->operands
) {
996 if (offset
< dst_offset
) {
997 offset
+= op
.bytes();
999 } else if (offset
!= dst_offset
|| op
.bytes() != instr
->definitions
[0].bytes()) {
1003 /* convert this extract into a copy instruction */
1004 instr
->opcode
= aco_opcode::p_parallelcopy
;
1005 instr
->operands
.pop_back();
1006 instr
->operands
[0] = op
;
1008 if (op
.isConstant()) {
1010 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(op
.constantValue());
1011 else if (op
.size() == 1)
1012 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(op
.constantValue());
1013 else if (op
.size() == 2)
1014 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(op
.constantValue());
1015 } else if (op
.isUndefined()) {
1016 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1018 assert(op
.isTemp());
1019 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(op
.getTemp());
1025 case aco_opcode::s_mov_b32
: /* propagate */
1026 case aco_opcode::s_mov_b64
:
1027 case aco_opcode::v_mov_b32
:
1028 case aco_opcode::p_as_uniform
:
1029 if (instr
->definitions
[0].isFixed()) {
1030 /* don't copy-propagate copies into fixed registers */
1031 } else if (instr
->usesModifiers()) {
1033 } else if (instr
->operands
[0].isConstant()) {
1034 if (instr
->operands
[0].isLiteral())
1035 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
1036 else if (instr
->operands
[0].size() == 1)
1037 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
1038 else if (instr
->operands
[0].size() == 2)
1039 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(instr
->operands
[0].constantValue());
1040 } else if (instr
->operands
[0].isTemp()) {
1041 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1043 assert(instr
->operands
[0].isFixed());
1046 case aco_opcode::p_is_helper
:
1047 if (!ctx
.program
->needs_wqm
)
1048 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
1050 case aco_opcode::s_movk_i32
: {
1051 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
1052 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
1053 if (v
<= 64 || v
>= 0xfffffff0)
1054 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1056 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1059 case aco_opcode::v_bfrev_b32
:
1060 case aco_opcode::s_brev_b32
: {
1061 if (instr
->operands
[0].isConstant()) {
1062 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
1063 if (v
<= 64 || v
>= 0xfffffff0)
1064 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1066 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1070 case aco_opcode::s_bfm_b32
: {
1071 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
1072 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
1073 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
1074 uint32_t v
= ((1u << size
) - 1u) << start
;
1075 if (v
<= 64 || v
>= 0xfffffff0)
1076 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1078 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1082 case aco_opcode::v_mul_f32
: { /* omod */
1083 /* TODO: try to move the negate/abs modifier to the consumer instead */
1084 if (instr
->usesModifiers())
1087 for (unsigned i
= 0; i
< 2; i
++) {
1088 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
1089 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
1090 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
1091 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
1092 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
1093 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
1094 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
1095 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000 &&
1096 !block
.fp_mode
.must_flush_denorms32
) { /* 1.0 */
1097 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
1106 case aco_opcode::v_and_b32
: /* abs */
1107 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x7FFFFFFF) &&
1108 instr
->operands
[1].isTemp() && instr
->operands
[1].getTemp().type() == RegType::vgpr
)
1109 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
1111 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1113 case aco_opcode::v_xor_b32
: { /* neg */
1114 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
1115 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
1116 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1117 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
1118 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
1119 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1120 instr
->opcode
= aco_opcode::v_or_b32
;
1121 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
1123 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
1127 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1131 case aco_opcode::v_med3_f32
: { /* clamp */
1132 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1133 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1134 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1135 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1139 bool found_zero
= false, found_one
= false;
1140 for (unsigned i
= 0; i
< 3; i
++)
1142 if (instr
->operands
[i
].constantEquals(0))
1144 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1149 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1150 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1154 case aco_opcode::v_cndmask_b32
:
1155 if (instr
->operands
[0].constantEquals(0) &&
1156 instr
->operands
[1].constantEquals(0xFFFFFFFF))
1157 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1158 else if (instr
->operands
[0].constantEquals(0) &&
1159 instr
->operands
[1].constantEquals(0x3f800000u
))
1160 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1161 else if (instr
->operands
[0].constantEquals(0) &&
1162 instr
->operands
[1].constantEquals(1))
1163 ctx
.info
[instr
->definitions
[0].tempId()].set_b2i(instr
->operands
[2].getTemp());
1165 ctx
.info
[instr
->operands
[2].tempId()].set_vcc_hint();
1167 case aco_opcode::v_cmp_lg_u32
:
1168 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1169 instr
->operands
[0].constantEquals(0) &&
1170 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1171 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1173 case aco_opcode::p_phi
:
1174 case aco_opcode::p_linear_phi
: {
1175 /* lower_bool_phis() can create phis like this */
1176 bool all_same_temp
= instr
->operands
[0].isTemp();
1177 /* this check is needed when moving uniform loop counters out of a divergent loop */
1179 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1180 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1181 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1182 all_same_temp
= false;
1184 if (all_same_temp
) {
1185 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1187 bool all_undef
= instr
->operands
[0].isUndefined();
1188 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1189 if (!instr
->operands
[i
].isUndefined())
1193 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1197 case aco_opcode::v_add_u32
:
1198 case aco_opcode::v_add_co_u32
:
1199 case aco_opcode::v_add_co_u32_e64
:
1200 case aco_opcode::s_add_i32
:
1201 case aco_opcode::s_add_u32
:
1202 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1204 case aco_opcode::s_not_b32
:
1205 case aco_opcode::s_not_b64
:
1206 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1207 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1208 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1209 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1210 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1211 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1213 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1215 case aco_opcode::s_and_b32
:
1216 case aco_opcode::s_and_b64
:
1217 if (fixed_to_exec(instr
->operands
[1]) && instr
->operands
[0].isTemp()) {
1218 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1219 /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
1220 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1221 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1223 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1224 /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
1225 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1226 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1231 case aco_opcode::s_or_b32
:
1232 case aco_opcode::s_or_b64
:
1233 case aco_opcode::s_xor_b32
:
1234 case aco_opcode::s_xor_b64
:
1235 if (std::all_of(instr
->operands
.begin(), instr
->operands
.end(), [&ctx
](const Operand
& op
) {
1236 return op
.isTemp() && (ctx
.info
[op
.tempId()].is_uniform_bool() || ctx
.info
[op
.tempId()].is_uniform_bitwise());
1238 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1241 case aco_opcode::s_lshl_b32
:
1242 case aco_opcode::v_or_b32
:
1243 case aco_opcode::v_lshlrev_b32
:
1244 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1246 case aco_opcode::v_min_f32
:
1247 case aco_opcode::v_min_f16
:
1248 case aco_opcode::v_min_u32
:
1249 case aco_opcode::v_min_i32
:
1250 case aco_opcode::v_min_u16
:
1251 case aco_opcode::v_min_i16
:
1252 case aco_opcode::v_max_f32
:
1253 case aco_opcode::v_max_f16
:
1254 case aco_opcode::v_max_u32
:
1255 case aco_opcode::v_max_i32
:
1256 case aco_opcode::v_max_u16
:
1257 case aco_opcode::v_max_i16
:
1258 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1260 case aco_opcode::v_cmp_lt_f32
:
1261 case aco_opcode::v_cmp_eq_f32
:
1262 case aco_opcode::v_cmp_le_f32
:
1263 case aco_opcode::v_cmp_gt_f32
:
1264 case aco_opcode::v_cmp_lg_f32
:
1265 case aco_opcode::v_cmp_ge_f32
:
1266 case aco_opcode::v_cmp_o_f32
:
1267 case aco_opcode::v_cmp_u_f32
:
1268 case aco_opcode::v_cmp_nge_f32
:
1269 case aco_opcode::v_cmp_nlg_f32
:
1270 case aco_opcode::v_cmp_ngt_f32
:
1271 case aco_opcode::v_cmp_nle_f32
:
1272 case aco_opcode::v_cmp_neq_f32
:
1273 case aco_opcode::v_cmp_nlt_f32
:
1274 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1276 case aco_opcode::s_cselect_b64
:
1277 case aco_opcode::s_cselect_b32
:
1278 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1279 instr
->operands
[1].constantEquals(0)) {
1280 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1281 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1283 if (instr
->operands
[2].isTemp() && ctx
.info
[instr
->operands
[2].tempId()].is_scc_invert()) {
1284 /* Flip the operands to get rid of the scc_invert instruction */
1285 std::swap(instr
->operands
[0], instr
->operands
[1]);
1286 instr
->operands
[2].setTemp(ctx
.info
[instr
->operands
[2].tempId()].temp
);
1289 case aco_opcode::p_wqm
:
1290 if (instr
->operands
[0].isTemp() &&
1291 ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1292 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1300 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1302 *ordered
= *unordered
= op
;
1304 #define CMP(ord, unord) \
1305 case aco_opcode::v_cmp_##ord##_f32:\
1306 case aco_opcode::v_cmp_n##unord##_f32:\
1307 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1308 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1309 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1323 aco_opcode
get_ordered(aco_opcode op
)
1325 aco_opcode ordered
, unordered
, inverse
;
1326 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1329 aco_opcode
get_unordered(aco_opcode op
)
1331 aco_opcode ordered
, unordered
, inverse
;
1332 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1335 aco_opcode
get_inverse(aco_opcode op
)
1337 aco_opcode ordered
, unordered
, inverse
;
1338 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1341 bool is_cmp(aco_opcode op
)
1343 aco_opcode ordered
, unordered
, inverse
;
1344 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1347 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1349 if (ctx
.info
[tmp
.id()].is_temp())
1350 return ctx
.info
[tmp
.id()].temp
.id();
1355 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1357 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1358 for (const Operand
& op
: instr
->operands
) {
1360 ctx
.uses
[op
.tempId()]--;
1365 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1367 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1369 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1372 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1374 if (instr
->definitions
.size() == 2) {
1375 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1376 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1383 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1384 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1385 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1387 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1389 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1392 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1394 bool neg
[2] = {false, false};
1395 bool abs
[2] = {false, false};
1397 Instruction
*op_instr
[2];
1400 for (unsigned i
= 0; i
< 2; i
++) {
1401 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1405 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1407 if (op_instr
[i
]->opcode
!= expected_cmp
)
1409 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1412 if (op_instr
[i
]->isVOP3()) {
1413 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1414 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1416 neg
[i
] = vop3
->neg
[0];
1417 abs
[i
] = vop3
->abs
[0];
1418 opsel
|= (vop3
->opsel
& 1) << i
;
1421 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1422 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1423 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1429 if (op
[1].type() == RegType::sgpr
)
1430 std::swap(op
[0], op
[1]);
1431 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1432 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1435 ctx
.uses
[op
[0].id()]++;
1436 ctx
.uses
[op
[1].id()]++;
1437 decrease_uses(ctx
, op_instr
[0]);
1438 decrease_uses(ctx
, op_instr
[1]);
1440 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1441 Instruction
*new_instr
;
1442 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1443 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1444 for (unsigned i
= 0; i
< 2; i
++) {
1445 vop3
->neg
[i
] = neg
[i
];
1446 vop3
->abs
[i
] = abs
[i
];
1448 vop3
->opsel
= opsel
;
1449 new_instr
= static_cast<Instruction
*>(vop3
);
1451 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1453 new_instr
->operands
[0] = Operand(op
[0]);
1454 new_instr
->operands
[1] = Operand(op
[1]);
1455 new_instr
->definitions
[0] = instr
->definitions
[0];
1457 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1458 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1460 instr
.reset(new_instr
);
1465 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1466 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1467 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1469 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1471 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1474 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1475 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1477 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1478 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1479 if (!nan_test
|| !cmp
)
1482 if (cmp
->opcode
== expected_nan_test
)
1483 std::swap(nan_test
, cmp
);
1484 else if (nan_test
->opcode
!= expected_nan_test
)
1487 if (!is_cmp(cmp
->opcode
))
1490 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1492 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1495 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1496 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1497 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1498 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1499 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1501 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1504 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1505 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1506 decrease_uses(ctx
, nan_test
);
1507 decrease_uses(ctx
, cmp
);
1509 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1510 Instruction
*new_instr
;
1511 if (cmp
->isVOP3()) {
1512 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1513 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1514 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1515 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1516 new_vop3
->clamp
= cmp_vop3
->clamp
;
1517 new_vop3
->omod
= cmp_vop3
->omod
;
1518 new_vop3
->opsel
= cmp_vop3
->opsel
;
1519 new_instr
= new_vop3
;
1521 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1523 new_instr
->operands
[0] = cmp
->operands
[0];
1524 new_instr
->operands
[1] = cmp
->operands
[1];
1525 new_instr
->definitions
[0] = instr
->definitions
[0];
1527 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1528 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1530 instr
.reset(new_instr
);
1535 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1536 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1537 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1539 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1541 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1544 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1546 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1547 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1549 if (!nan_test
|| !cmp
)
1552 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1553 if (cmp
->opcode
== expected_nan_test
)
1554 std::swap(nan_test
, cmp
);
1555 else if (nan_test
->opcode
!= expected_nan_test
)
1558 if (!is_cmp(cmp
->opcode
))
1561 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1563 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1566 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1567 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1568 if (prop_nan0
!= prop_nan1
)
1571 if (nan_test
->isVOP3()) {
1572 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1573 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1577 int constant_operand
= -1;
1578 for (unsigned i
= 0; i
< 2; i
++) {
1579 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1580 constant_operand
= !i
;
1584 if (constant_operand
== -1)
1588 if (cmp
->operands
[constant_operand
].isConstant()) {
1589 constant
= cmp
->operands
[constant_operand
].constantValue();
1590 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1591 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1592 unsigned id
= original_temp_id(ctx
, tmp
);
1593 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1595 constant
= ctx
.info
[id
].val
;
1601 memcpy(&constantf
, &constant
, 4);
1602 if (isnan(constantf
))
1605 if (cmp
->operands
[0].isTemp())
1606 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1607 if (cmp
->operands
[1].isTemp())
1608 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1609 decrease_uses(ctx
, nan_test
);
1610 decrease_uses(ctx
, cmp
);
1612 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1613 Instruction
*new_instr
;
1614 if (cmp
->isVOP3()) {
1615 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1616 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1617 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1618 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1619 new_vop3
->clamp
= cmp_vop3
->clamp
;
1620 new_vop3
->omod
= cmp_vop3
->omod
;
1621 new_vop3
->opsel
= cmp_vop3
->opsel
;
1622 new_instr
= new_vop3
;
1624 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1626 new_instr
->operands
[0] = cmp
->operands
[0];
1627 new_instr
->operands
[1] = cmp
->operands
[1];
1628 new_instr
->definitions
[0] = instr
->definitions
[0];
1630 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1631 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1633 instr
.reset(new_instr
);
1638 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1639 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1641 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1643 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1645 if (!instr
->operands
[0].isTemp())
1648 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1652 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1653 if (new_opcode
== aco_opcode::last_opcode
)
1656 if (cmp
->operands
[0].isTemp())
1657 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1658 if (cmp
->operands
[1].isTemp())
1659 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1660 decrease_uses(ctx
, cmp
);
1662 Instruction
*new_instr
;
1663 if (cmp
->isVOP3()) {
1664 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1665 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1666 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1667 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1668 new_vop3
->clamp
= cmp_vop3
->clamp
;
1669 new_vop3
->omod
= cmp_vop3
->omod
;
1670 new_vop3
->opsel
= cmp_vop3
->opsel
;
1671 new_instr
= new_vop3
;
1673 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1675 new_instr
->operands
[0] = cmp
->operands
[0];
1676 new_instr
->operands
[1] = cmp
->operands
[1];
1677 new_instr
->definitions
[0] = instr
->definitions
[0];
1679 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1680 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1682 instr
.reset(new_instr
);
1687 /* op1(op2(1, 2), 0) if swap = false
1688 * op1(0, op2(1, 2)) if swap = true */
1689 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1690 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1691 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1692 bool *op1_clamp
, uint8_t *op1_omod
,
1693 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1696 if (op1_instr
->opcode
!= op1
)
1699 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1700 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1702 if (fixed_to_exec(op2_instr
->operands
[0]) || fixed_to_exec(op2_instr
->operands
[1]))
1705 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1706 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1708 /* don't support inbetween clamp/omod */
1709 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1712 /* get operands and modifiers and check inbetween modifiers */
1713 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1714 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1717 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1718 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1722 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1723 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1726 if (inbetween_opsel
)
1727 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1728 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1732 shuffle
[shuffle_str
[0] - '0'] = 0;
1733 shuffle
[shuffle_str
[1] - '0'] = 1;
1734 shuffle
[shuffle_str
[2] - '0'] = 2;
1736 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1737 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1738 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1739 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1740 *opsel
|= 1 << shuffle
[0];
1742 for (unsigned i
= 0; i
< 2; i
++) {
1743 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1744 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1745 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1746 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1747 *opsel
|= 1 << shuffle
[i
+ 1];
1750 /* check operands */
1751 if (!check_vop3_operands(ctx
, 3, operands
))
1757 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1758 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1759 bool clamp
, unsigned omod
)
1761 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1762 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1763 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1764 new_instr
->clamp
= clamp
;
1765 new_instr
->omod
= omod
;
1766 new_instr
->opsel
= opsel
;
1767 new_instr
->operands
[0] = operands
[0];
1768 new_instr
->operands
[1] = operands
[1];
1769 new_instr
->operands
[2] = operands
[2];
1770 new_instr
->definitions
[0] = instr
->definitions
[0];
1771 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1773 instr
.reset(new_instr
);
1776 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1778 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1779 (label_omod_success
| label_clamp_success
);
1781 for (unsigned swap
= 0; swap
< 2; swap
++) {
1782 if (!((1 << swap
) & ops
))
1785 Operand operands
[3];
1786 bool neg
[3], abs
[3], clamp
;
1787 uint8_t opsel
= 0, omod
= 0;
1788 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1789 instr
.get(), swap
, shuffle
,
1790 operands
, neg
, abs
, &opsel
,
1791 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1792 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1793 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1794 if (omod_clamp
& label_omod_success
)
1795 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1796 if (omod_clamp
& label_clamp_success
)
1797 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1804 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
1806 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
1809 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1810 (label_omod_success
| label_clamp_success
);
1812 /* min(-max(a, b), c) -> min3(-a, -b, c) *
1813 * max(-min(a, b), c) -> max3(-a, -b, c) */
1814 for (unsigned swap
= 0; swap
< 2; swap
++) {
1815 Operand operands
[3];
1816 bool neg
[3], abs
[3], clamp
;
1817 uint8_t opsel
= 0, omod
= 0;
1819 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
1820 instr
.get(), swap
, "012",
1821 operands
, neg
, abs
, &opsel
,
1822 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
1824 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1827 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1828 if (omod_clamp
& label_omod_success
)
1829 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1830 if (omod_clamp
& label_clamp_success
)
1831 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1838 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1839 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1840 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1841 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1842 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1843 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1844 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1847 if (!instr
->operands
[0].isTemp())
1849 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1852 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1855 switch (op2_instr
->opcode
) {
1856 case aco_opcode::s_and_b32
:
1857 case aco_opcode::s_or_b32
:
1858 case aco_opcode::s_xor_b32
:
1859 case aco_opcode::s_and_b64
:
1860 case aco_opcode::s_or_b64
:
1861 case aco_opcode::s_xor_b64
:
1867 /* create instruction */
1868 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1869 std::swap(instr
->definitions
[1], op2_instr
->definitions
[1]);
1870 ctx
.uses
[instr
->operands
[0].tempId()]--;
1871 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1873 switch (op2_instr
->opcode
) {
1874 case aco_opcode::s_and_b32
:
1875 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1877 case aco_opcode::s_or_b32
:
1878 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1880 case aco_opcode::s_xor_b32
:
1881 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1883 case aco_opcode::s_and_b64
:
1884 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1886 case aco_opcode::s_or_b64
:
1887 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1889 case aco_opcode::s_xor_b64
:
1890 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1899 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1900 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1901 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1902 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1903 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1905 if (instr
->definitions
[0].isTemp() && ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bool())
1908 for (unsigned i
= 0; i
< 2; i
++) {
1909 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1910 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1912 if (ctx
.uses
[op2_instr
->definitions
[1].tempId()] || fixed_to_exec(op2_instr
->operands
[0]))
1915 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1916 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1919 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1920 instr
->operands
[0] = instr
->operands
[!i
];
1921 instr
->operands
[1] = op2_instr
->operands
[0];
1922 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1924 switch (instr
->opcode
) {
1925 case aco_opcode::s_and_b32
:
1926 instr
->opcode
= aco_opcode::s_andn2_b32
;
1928 case aco_opcode::s_or_b32
:
1929 instr
->opcode
= aco_opcode::s_orn2_b32
;
1931 case aco_opcode::s_and_b64
:
1932 instr
->opcode
= aco_opcode::s_andn2_b64
;
1934 case aco_opcode::s_or_b64
:
1935 instr
->opcode
= aco_opcode::s_orn2_b64
;
1946 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1947 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1949 if (instr
->opcode
== aco_opcode::s_add_i32
&& ctx
.uses
[instr
->definitions
[1].tempId()])
1952 for (unsigned i
= 0; i
< 2; i
++) {
1953 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1954 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
||
1955 ctx
.uses
[op2_instr
->definitions
[1].tempId()])
1957 if (!op2_instr
->operands
[1].isConstant() || fixed_to_exec(op2_instr
->operands
[0]))
1960 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1961 if (shift
< 1 || shift
> 4)
1964 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1965 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1968 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1969 instr
->operands
[1] = instr
->operands
[!i
];
1970 instr
->operands
[0] = op2_instr
->operands
[0];
1971 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1973 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1974 aco_opcode::s_lshl2_add_u32
,
1975 aco_opcode::s_lshl3_add_u32
,
1976 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1983 bool combine_add_sub_b2i(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode new_op
, uint8_t ops
)
1985 if (instr
->usesModifiers())
1988 for (unsigned i
= 0; i
< 2; i
++) {
1989 if (!((1 << i
) & ops
))
1991 if (instr
->operands
[i
].isTemp() &&
1992 ctx
.info
[instr
->operands
[i
].tempId()].is_b2i() &&
1993 ctx
.uses
[instr
->operands
[i
].tempId()] == 1) {
1995 aco_ptr
<Instruction
> new_instr
;
1996 if (instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
1997 new_instr
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 2));
1998 } else if (ctx
.program
->chip_class
>= GFX10
||
1999 (instr
->operands
[!i
].isConstant() && !instr
->operands
[!i
].isLiteral())) {
2000 new_instr
.reset(create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOP2
), 3, 2));
2004 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2005 new_instr
->definitions
[0] = instr
->definitions
[0];
2006 new_instr
->definitions
[1] = instr
->definitions
.size() == 2 ? instr
->definitions
[1] :
2007 Definition(ctx
.program
->allocateId(), ctx
.program
->lane_mask
);
2008 new_instr
->definitions
[1].setHint(vcc
);
2009 new_instr
->operands
[0] = Operand(0u);
2010 new_instr
->operands
[1] = instr
->operands
[!i
];
2011 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2012 instr
= std::move(new_instr
);
2013 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2021 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
2024 #define MINMAX(type, gfx9) \
2025 case aco_opcode::v_min_##type:\
2026 case aco_opcode::v_max_##type:\
2027 case aco_opcode::v_med3_##type:\
2028 *min = aco_opcode::v_min_##type;\
2029 *max = aco_opcode::v_max_##type;\
2030 *med3 = aco_opcode::v_med3_##type;\
2031 *min3 = aco_opcode::v_min3_##type;\
2032 *max3 = aco_opcode::v_max3_##type;\
2033 *some_gfx9_only = gfx9;\
2047 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
2048 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
2049 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
2050 aco_opcode min
, aco_opcode max
, aco_opcode med
)
2052 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
2053 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
2054 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
2055 aco_opcode other_op
;
2056 if (instr
->opcode
== min
)
2058 else if (instr
->opcode
== max
)
2063 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
2064 (label_omod_success
| label_clamp_success
);
2066 for (unsigned swap
= 0; swap
< 2; swap
++) {
2067 Operand operands
[3];
2068 bool neg
[3], abs
[3], clamp
;
2069 uint8_t opsel
= 0, omod
= 0;
2070 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
2071 "012", operands
, neg
, abs
, &opsel
,
2072 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
2073 int const0_idx
= -1, const1_idx
= -1;
2074 uint32_t const0
= 0, const1
= 0;
2075 for (int i
= 0; i
< 3; i
++) {
2077 if (operands
[i
].isConstant()) {
2078 val
= operands
[i
].constantValue();
2079 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
2080 val
= ctx
.info
[operands
[i
].tempId()].val
;
2084 if (const0_idx
>= 0) {
2092 if (const0_idx
< 0 || const1_idx
< 0)
2095 if (opsel
& (1 << const0_idx
))
2097 if (opsel
& (1 << const1_idx
))
2100 int lower_idx
= const0_idx
;
2102 case aco_opcode::v_min_f32
:
2103 case aco_opcode::v_min_f16
: {
2104 float const0_f
, const1_f
;
2105 if (min
== aco_opcode::v_min_f32
) {
2106 memcpy(&const0_f
, &const0
, 4);
2107 memcpy(&const1_f
, &const1
, 4);
2109 const0_f
= _mesa_half_to_float(const0
);
2110 const1_f
= _mesa_half_to_float(const1
);
2112 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
2113 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
2114 if (neg
[const0_idx
]) const0_f
= -const0_f
;
2115 if (neg
[const1_idx
]) const1_f
= -const1_f
;
2116 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
2119 case aco_opcode::v_min_u32
: {
2120 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
2123 case aco_opcode::v_min_u16
: {
2124 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
2127 case aco_opcode::v_min_i32
: {
2128 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
2129 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
2130 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2133 case aco_opcode::v_min_i16
: {
2134 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
2135 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
2136 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2142 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
2144 if (instr
->opcode
== min
) {
2145 if (upper_idx
!= 0 || lower_idx
== 0)
2148 if (upper_idx
== 0 || lower_idx
!= 0)
2152 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2153 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2154 if (omod_clamp
& label_omod_success
)
2155 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2156 if (omod_clamp
& label_clamp_success
)
2157 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2167 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2169 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2170 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2171 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2173 /* find candidates and create the set of sgprs already read */
2174 unsigned sgpr_ids
[2] = {0, 0};
2175 uint32_t operand_mask
= 0;
2176 bool has_literal
= false;
2177 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2178 if (instr
->operands
[i
].isLiteral())
2180 if (!instr
->operands
[i
].isTemp())
2182 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2183 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
2184 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
2186 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
2187 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
2188 operand_mask
|= 1u << i
;
2190 unsigned max_sgprs
= 1;
2191 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2196 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2198 /* keep on applying sgprs until there is nothing left to be done */
2199 while (operand_mask
) {
2200 uint32_t sgpr_idx
= 0;
2201 uint32_t sgpr_info_id
= 0;
2202 uint32_t mask
= operand_mask
;
2205 unsigned i
= u_bit_scan(&mask
);
2206 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2207 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
2209 sgpr_info_id
= instr
->operands
[i
].tempId();
2212 operand_mask
&= ~(1u << sgpr_idx
);
2214 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2215 * definitively beneficial.
2216 * TODO: this is too conservative because later the use count could be reduced to 1 */
2217 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2220 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2221 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2222 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2225 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2226 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2227 } else if (can_swap_operands(instr
)) {
2228 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2229 instr
->operands
[0] = Operand(sgpr
);
2230 /* swap bits using a 4-entry LUT */
2231 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2232 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2233 } else if (can_use_VOP3(ctx
, instr
)) {
2234 to_VOP3(ctx
, instr
);
2235 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2241 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2242 ctx
.uses
[sgpr_info_id
]--;
2243 ctx
.uses
[sgpr
.id()]++;
2247 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2249 /* check if we could apply omod on predecessor */
2250 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
2251 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2252 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2254 unsigned idx
= op0
? 0 : 1;
2255 /* omod was successfully applied */
2256 /* if the omod instruction is v_mad, we also have to change the original add */
2257 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2258 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2259 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2260 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2261 add_instr
->definitions
[0] = instr
->definitions
[0];
2264 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2265 /* check if we have an additional clamp modifier */
2266 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2267 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2268 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2269 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2271 /* change definition ssa-id of modified instruction */
2272 omod_instr
->definitions
[0] = instr
->definitions
[0];
2274 /* change the definition of instr to something unused, e.g. the original omod def */
2275 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2276 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2279 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2280 /* in all other cases, label this instruction as option for multiply-add */
2281 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2285 /* check if we could apply clamp on predecessor */
2286 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
2288 bool found_zero
= false, found_one
= false;
2289 for (unsigned i
= 0; i
< 3; i
++)
2291 if (instr
->operands
[i
].constantEquals(0))
2293 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
2298 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2299 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2300 /* clamp was successfully applied */
2301 /* if the clamp instruction is v_mad, we also have to change the original add */
2302 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2303 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2304 add_instr
->definitions
[0] = instr
->definitions
[0];
2306 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2307 /* change definition ssa-id of modified instruction */
2308 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2310 /* change the definition of instr to something unused, e.g. the original omod def */
2311 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2312 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2317 /* omod has no effect if denormals are enabled */
2318 bool can_use_omod
= block
.fp_mode
.denorm32
== 0;
2320 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2321 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2322 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2323 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2324 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2325 to_VOP3(ctx
, instr
);
2326 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2327 def_info
.set_omod_success(instr
.get());
2328 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2329 to_VOP3(ctx
, instr
);
2330 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2331 def_info
.set_omod_success(instr
.get());
2332 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2333 to_VOP3(ctx
, instr
);
2334 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2335 def_info
.set_omod_success(instr
.get());
2336 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2337 to_VOP3(ctx
, instr
);
2338 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2339 def_info
.set_clamp_success(instr
.get());
2346 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2347 // this would mean that we'd have to fix the instruction uses while value propagation
2349 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2351 if (instr
->definitions
.empty() || is_dead(ctx
.uses
, instr
.get()))
2354 if (instr
->isVALU()) {
2355 if (can_apply_sgprs(instr
))
2356 apply_sgprs(ctx
, instr
);
2357 if (apply_omod_clamp(ctx
, block
, instr
))
2361 if (ctx
.info
[instr
->definitions
[0].tempId()].is_vcc_hint()) {
2362 instr
->definitions
[0].setHint(vcc
);
2365 /* TODO: There are still some peephole optimizations that could be done:
2366 * - abs(a - b) -> s_absdiff_i32
2367 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2368 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2369 * These aren't probably too interesting though.
2370 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2371 * probably more useful than the previously mentioned optimizations.
2372 * The various comparison optimizations also currently only work with 32-bit
2375 /* neg(mul(a, b)) -> mul(neg(a), b) */
2376 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2377 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2379 if (!ctx
.info
[val
.id()].is_mul())
2382 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2384 if (mul_instr
->operands
[0].isLiteral())
2386 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2389 /* convert to mul(neg(a), b) */
2390 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2391 Definition def
= instr
->definitions
[0];
2392 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2393 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2394 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2395 instr
->operands
[0] = mul_instr
->operands
[0];
2396 instr
->operands
[1] = mul_instr
->operands
[1];
2397 instr
->definitions
[0] = def
;
2398 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2399 if (mul_instr
->isVOP3()) {
2400 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2401 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2402 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2403 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2404 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2405 new_mul
->omod
= mul
->omod
;
2407 new_mul
->neg
[0] ^= true;
2408 new_mul
->clamp
= false;
2410 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2413 /* combine mul+add -> mad */
2414 else if ((instr
->opcode
== aco_opcode::v_add_f32
||
2415 instr
->opcode
== aco_opcode::v_sub_f32
||
2416 instr
->opcode
== aco_opcode::v_subrev_f32
) &&
2417 block
.fp_mode
.denorm32
== 0 && !block
.fp_mode
.preserve_signed_zero_inf_nan32
) {
2418 //TODO: we could use fma instead when denormals are enabled if the NIR isn't marked as precise
2420 uint32_t uses_src0
= UINT32_MAX
;
2421 uint32_t uses_src1
= UINT32_MAX
;
2422 Instruction
* mul_instr
= nullptr;
2423 unsigned add_op_idx
;
2424 /* check if any of the operands is a multiplication */
2425 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2426 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2427 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2428 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2430 /* find the 'best' mul instruction to combine with the add */
2431 if (uses_src0
< uses_src1
) {
2432 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2434 } else if (uses_src1
< uses_src0
) {
2435 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2437 } else if (uses_src0
!= UINT32_MAX
) {
2438 /* tiebreaker: quite random what to pick */
2439 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2440 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2443 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2448 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2449 bool neg
[3] = {false, false, false};
2450 bool abs
[3] = {false, false, false};
2453 op
[0] = mul_instr
->operands
[0];
2454 op
[1] = mul_instr
->operands
[1];
2455 op
[2] = instr
->operands
[add_op_idx
];
2456 // TODO: would be better to check this before selecting a mul instr?
2457 if (!check_vop3_operands(ctx
, 3, op
))
2460 if (mul_instr
->isVOP3()) {
2461 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2462 neg
[0] = vop3
->neg
[0];
2463 neg
[1] = vop3
->neg
[1];
2464 abs
[0] = vop3
->abs
[0];
2465 abs
[1] = vop3
->abs
[1];
2466 /* we cannot use these modifiers between mul and add */
2467 if (vop3
->clamp
|| vop3
->omod
)
2471 /* convert to mad */
2472 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2473 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2475 ctx
.uses
[op
[0].tempId()]++;
2477 ctx
.uses
[op
[1].tempId()]++;
2480 if (instr
->isVOP3()) {
2481 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2482 neg
[2] = vop3
->neg
[add_op_idx
];
2483 abs
[2] = vop3
->abs
[add_op_idx
];
2485 clamp
= vop3
->clamp
;
2486 /* abs of the multiplication result */
2487 if (vop3
->abs
[1 - add_op_idx
]) {
2493 /* neg of the multiplication result */
2494 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2496 if (instr
->opcode
== aco_opcode::v_sub_f32
)
2497 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2498 else if (instr
->opcode
== aco_opcode::v_subrev_f32
)
2499 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2501 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2502 for (unsigned i
= 0; i
< 3; i
++)
2504 mad
->operands
[i
] = op
[i
];
2505 mad
->neg
[i
] = neg
[i
];
2506 mad
->abs
[i
] = abs
[i
];
2510 mad
->definitions
[0] = instr
->definitions
[0];
2512 /* mark this ssa_def to be re-checked for profitability and literals */
2513 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2514 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2515 instr
.reset(mad
.release());
2519 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2520 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2521 for (unsigned i
= 0; i
< 2; i
++) {
2522 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2523 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2524 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2525 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2526 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2528 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2529 new_instr
->operands
[0] = Operand(0u);
2530 new_instr
->operands
[1] = instr
->operands
[!i
];
2531 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2532 new_instr
->definitions
[0] = instr
->definitions
[0];
2533 instr
.reset(new_instr
.release());
2534 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2538 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2539 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2540 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2541 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2542 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2543 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_or_b32
, "120", 1 | 2)) ;
2544 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2545 } else if (instr
->opcode
== aco_opcode::v_add_u32
) {
2546 if (combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2)) ;
2547 else if (ctx
.program
->chip_class
>= GFX9
) {
2548 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2549 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2550 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_i32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2551 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2552 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2553 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_add_u32
, "120", 1 | 2)) ;
2554 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2556 } else if (instr
->opcode
== aco_opcode::v_add_co_u32
||
2557 instr
->opcode
== aco_opcode::v_add_co_u32_e64
) {
2558 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2);
2559 } else if (instr
->opcode
== aco_opcode::v_sub_u32
||
2560 instr
->opcode
== aco_opcode::v_sub_co_u32
||
2561 instr
->opcode
== aco_opcode::v_sub_co_u32_e64
) {
2562 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 2);
2563 } else if (instr
->opcode
== aco_opcode::v_subrev_u32
||
2564 instr
->opcode
== aco_opcode::v_subrev_co_u32
||
2565 instr
->opcode
== aco_opcode::v_subrev_co_u32_e64
) {
2566 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 1);
2567 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2568 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2569 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2570 combine_salu_lshl_add(ctx
, instr
);
2571 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2572 combine_salu_not_bitwise(ctx
, instr
);
2573 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2574 if (combine_inverse_comparison(ctx
, instr
)) ;
2575 else combine_salu_not_bitwise(ctx
, instr
);
2576 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2577 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2578 if (combine_ordering_test(ctx
, instr
)) ;
2579 else if (combine_comparison_ordering(ctx
, instr
)) ;
2580 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2581 else combine_salu_n2(ctx
, instr
);
2583 aco_opcode min
, max
, min3
, max3
, med3
;
2584 bool some_gfx9_only
;
2585 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2586 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2587 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2588 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2593 bool to_uniform_bool_instr(opt_ctx
&ctx
, aco_ptr
<Instruction
> &instr
)
2595 switch (instr
->opcode
) {
2596 case aco_opcode::s_and_b32
:
2597 case aco_opcode::s_and_b64
:
2598 instr
->opcode
= aco_opcode::s_and_b32
;
2600 case aco_opcode::s_or_b32
:
2601 case aco_opcode::s_or_b64
:
2602 instr
->opcode
= aco_opcode::s_or_b32
;
2604 case aco_opcode::s_xor_b32
:
2605 case aco_opcode::s_xor_b64
:
2606 instr
->opcode
= aco_opcode::s_absdiff_i32
;
2609 /* Don't transform other instructions. They are very unlikely to appear here. */
2613 for (Operand
&op
: instr
->operands
) {
2614 ctx
.uses
[op
.tempId()]--;
2616 if (ctx
.info
[op
.tempId()].is_uniform_bool()) {
2617 /* Just use the uniform boolean temp. */
2618 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
2619 } else if (ctx
.info
[op
.tempId()].is_uniform_bitwise()) {
2620 /* Use the SCC definition of the predecessor instruction.
2621 * This allows the predecessor to get picked up by the same optimization (if it has no divergent users),
2622 * and it also makes sure that the current instruction will keep working even if the predecessor won't be transformed.
2624 Instruction
*pred_instr
= ctx
.info
[op
.tempId()].instr
;
2625 assert(pred_instr
->definitions
.size() >= 2);
2626 assert(pred_instr
->definitions
[1].isFixed() && pred_instr
->definitions
[1].physReg() == scc
);
2627 op
.setTemp(pred_instr
->definitions
[1].getTemp());
2629 unreachable("Invalid operand on uniform bitwise instruction.");
2632 ctx
.uses
[op
.tempId()]++;
2635 instr
->definitions
[0].setTemp(Temp(instr
->definitions
[0].tempId(), s1
));
2636 assert(instr
->operands
[0].regClass() == s1
);
2637 assert(instr
->operands
[1].regClass() == s1
);
2641 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2643 const uint32_t threshold
= 4;
2645 if (is_dead(ctx
.uses
, instr
.get())) {
2650 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2651 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2652 unsigned num_used
= 0;
2654 unsigned split_offset
= 0;
2655 for (unsigned i
= 0, offset
= 0; i
< instr
->definitions
.size(); offset
+= instr
->definitions
[i
++].bytes()) {
2656 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2659 split_offset
= offset
;
2663 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2664 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2665 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2669 for (Operand
& vec_op
: vec
->operands
) {
2670 if (off
== split_offset
) {
2674 off
+= vec_op
.bytes();
2676 if (off
!= instr
->operands
[0].bytes() && op
.bytes() == instr
->definitions
[idx
].bytes()) {
2677 ctx
.uses
[instr
->operands
[0].tempId()]--;
2678 for (Operand
& vec_op
: vec
->operands
) {
2679 if (vec_op
.isTemp())
2680 ctx
.uses
[vec_op
.tempId()]--;
2683 ctx
.uses
[op
.tempId()]++;
2685 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2686 extract
->operands
[0] = op
;
2687 extract
->definitions
[0] = instr
->definitions
[idx
];
2688 instr
.reset(extract
.release());
2694 if (!done
&& num_used
== 1 &&
2695 instr
->operands
[0].bytes() % instr
->definitions
[idx
].bytes() == 0 &&
2696 split_offset
% instr
->definitions
[idx
].bytes() == 0) {
2697 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2698 extract
->operands
[0] = instr
->operands
[0];
2699 extract
->operands
[1] = Operand((uint32_t) split_offset
/ instr
->definitions
[idx
].bytes());
2700 extract
->definitions
[0] = instr
->definitions
[idx
];
2701 instr
.reset(extract
.release());
2705 mad_info
* mad_info
= NULL
;
2706 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2707 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2708 /* re-check mad instructions */
2709 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2710 ctx
.uses
[mad_info
->mul_temp_id
]++;
2711 if (instr
->operands
[0].isTemp())
2712 ctx
.uses
[instr
->operands
[0].tempId()]--;
2713 if (instr
->operands
[1].isTemp())
2714 ctx
.uses
[instr
->operands
[1].tempId()]--;
2715 instr
.swap(mad_info
->add_instr
);
2718 /* check literals */
2719 else if (!instr
->usesModifiers()) {
2720 bool sgpr_used
= false;
2721 uint32_t literal_idx
= 0;
2722 uint32_t literal_uses
= UINT32_MAX
;
2723 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2725 if (instr
->operands
[i
].isConstant() && i
> 0) {
2726 literal_uses
= UINT32_MAX
;
2729 if (!instr
->operands
[i
].isTemp())
2731 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2732 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2733 if (!sgpr_used
&& ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2734 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2737 literal_uses
= UINT32_MAX
;
2740 /* don't break because we still need to check constants */
2741 } else if (!sgpr_used
&&
2742 ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2743 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2744 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2749 /* Limit the number of literals to apply to not increase the code
2750 * size too much, but always apply literals for v_mad->v_madak
2751 * because both instructions are 64-bit and this doesn't increase
2753 * TODO: try to apply the literals earlier to lower the number of
2754 * uses below threshold
2756 if (literal_uses
< threshold
|| literal_idx
== 2) {
2757 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2758 mad_info
->check_literal
= true;
2759 mad_info
->literal_idx
= literal_idx
;
2765 /* Mark SCC needed, so the uniform boolean transformation won't swap the definitions when it isn't beneficial */
2766 if (instr
->format
== Format::PSEUDO_BRANCH
&&
2767 instr
->operands
.size() &&
2768 instr
->operands
[0].isTemp()) {
2769 ctx
.info
[instr
->operands
[0].tempId()].set_scc_needed();
2771 } else if ((instr
->opcode
== aco_opcode::s_cselect_b64
||
2772 instr
->opcode
== aco_opcode::s_cselect_b32
) &&
2773 instr
->operands
[2].isTemp()) {
2774 ctx
.info
[instr
->operands
[2].tempId()].set_scc_needed();
2777 /* check for literals */
2778 if (!instr
->isSALU() && !instr
->isVALU())
2781 /* Transform uniform bitwise boolean operations to 32-bit when there are no divergent uses. */
2782 if (instr
->definitions
.size() &&
2783 ctx
.uses
[instr
->definitions
[0].tempId()] == 0 &&
2784 ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bitwise()) {
2785 bool transform_done
= to_uniform_bool_instr(ctx
, instr
);
2787 if (transform_done
&& !ctx
.info
[instr
->definitions
[1].tempId()].is_scc_needed()) {
2788 /* Swap the two definition IDs in order to avoid overusing the SCC. This reduces extra moves generated by RA. */
2789 uint32_t def0_id
= instr
->definitions
[0].getTemp().id();
2790 uint32_t def1_id
= instr
->definitions
[1].getTemp().id();
2791 instr
->definitions
[0].setTemp(Temp(def1_id
, s1
));
2792 instr
->definitions
[1].setTemp(Temp(def0_id
, s1
));
2798 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
2799 return; /* some encodings can't ever take literals */
2801 /* we do not apply the literals yet as we don't know if it is profitable */
2802 Operand
current_literal(s1
);
2804 unsigned literal_id
= 0;
2805 unsigned literal_uses
= UINT32_MAX
;
2806 Operand
literal(s1
);
2807 unsigned num_operands
= 1;
2808 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
2809 num_operands
= instr
->operands
.size();
2810 /* catch VOP2 with a 3rd SGPR operand (e.g. v_cndmask_b32, v_addc_co_u32) */
2811 else if (instr
->isVALU() && instr
->operands
.size() >= 3)
2814 unsigned sgpr_ids
[2] = {0, 0};
2815 bool is_literal_sgpr
= false;
2818 /* choose a literal to apply */
2819 for (unsigned i
= 0; i
< num_operands
; i
++) {
2820 Operand op
= instr
->operands
[i
];
2822 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
2823 op
.tempId() != sgpr_ids
[0])
2824 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
2826 if (op
.isLiteral()) {
2827 current_literal
= op
;
2829 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal()) {
2833 if (!alu_can_accept_constant(instr
->opcode
, i
))
2836 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
2837 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
2839 literal
= Operand(ctx
.info
[op
.tempId()].val
);
2840 literal_uses
= ctx
.uses
[op
.tempId()];
2841 literal_id
= op
.tempId();
2844 mask
|= (op
.tempId() == literal_id
) << i
;
2848 /* don't go over the constant bus limit */
2849 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2850 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2851 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2852 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
2853 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2854 const_bus_limit
= 2;
2856 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2857 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
2860 if (literal_id
&& literal_uses
< threshold
&&
2861 (current_literal
.isUndefined() ||
2862 (current_literal
.size() == literal
.size() &&
2863 current_literal
.constantValue() == literal
.constantValue()))) {
2864 /* mark the literal to be applied */
2866 unsigned i
= u_bit_scan(&mask
);
2867 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
2868 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2874 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2876 /* Cleanup Dead Instructions */
2880 /* apply literals on MAD */
2881 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2882 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2883 if (info
->check_literal
&&
2884 (ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0 || info
->literal_idx
== 2)) {
2885 aco_ptr
<Instruction
> new_mad
;
2886 if (info
->literal_idx
== 2) { /* add literal -> madak */
2887 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2888 new_mad
->operands
[0] = instr
->operands
[0];
2889 new_mad
->operands
[1] = instr
->operands
[1];
2890 } else { /* mul literal -> madmk */
2891 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2892 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2893 new_mad
->operands
[1] = instr
->operands
[2];
2895 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2896 new_mad
->definitions
[0] = instr
->definitions
[0];
2897 ctx
.instructions
.emplace_back(std::move(new_mad
));
2902 /* apply literals on other SALU/VALU */
2903 if (instr
->isSALU() || instr
->isVALU()) {
2904 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2905 Operand op
= instr
->operands
[i
];
2906 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal() && ctx
.uses
[op
.tempId()] == 0) {
2907 Operand
literal(ctx
.info
[op
.tempId()].val
);
2908 if (instr
->isVALU() && i
> 0)
2909 to_VOP3(ctx
, instr
);
2910 instr
->operands
[i
] = literal
;
2915 ctx
.instructions
.emplace_back(std::move(instr
));
2919 void optimize(Program
* program
)
2922 ctx
.program
= program
;
2923 std::vector
<ssa_info
> info(program
->peekAllocationId());
2924 ctx
.info
= info
.data();
2926 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2927 for (Block
& block
: program
->blocks
) {
2928 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2929 label_instruction(ctx
, block
, instr
);
2932 ctx
.uses
= std::move(dead_code_analysis(program
));
2934 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2935 for (Block
& block
: program
->blocks
) {
2936 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2937 combine_instruction(ctx
, block
, instr
);
2940 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2941 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2942 Block
* block
= &(*it
);
2943 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2944 select_instruction(ctx
, *it
);
2947 /* 4. Add literals to instructions */
2948 for (Block
& block
: program
->blocks
) {
2949 ctx
.instructions
.clear();
2950 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2951 apply_literals(ctx
, instr
);
2952 block
.instructions
.swap(ctx
.instructions
);