2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant
= 1 << 1,
69 label_literal
= 1 << 6,
73 label_omod5
= 1 << 10,
74 label_omod_success
= 1 << 11,
75 label_clamp
= 1 << 12,
76 label_clamp_success
= 1 << 13,
77 label_undefined
= 1 << 14,
80 label_add_sub
= 1 << 17,
81 label_bitwise
= 1 << 18,
82 label_minmax
= 1 << 19,
84 label_uniform_bool
= 1 << 21,
87 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
| label_add_sub
| label_bitwise
| label_minmax
| label_fcmp
;
88 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
| label_omod2
| label_omod4
| label_omod5
| label_clamp
;
89 static constexpr uint32_t val_labels
= label_constant
| label_literal
| label_mad
;
99 void add_label(Label new_label
)
101 /* Since all labels which use "instr" use it for the same thing
102 * (indicating the defining instruction), there is no need to clear
103 * any other instr labels. */
104 if (new_label
& instr_labels
)
105 label
&= ~temp_labels
; /* instr and temp alias */
107 if (new_label
& temp_labels
) {
108 label
&= ~temp_labels
;
109 label
&= ~instr_labels
; /* instr and temp alias */
112 if (new_label
& val_labels
)
113 label
&= ~val_labels
;
118 void set_vec(Instruction
* vec
)
120 add_label(label_vec
);
126 return label
& label_vec
;
129 void set_constant(uint32_t constant
)
131 add_label(label_constant
);
137 return label
& label_constant
;
140 void set_abs(Temp abs_temp
)
142 add_label(label_abs
);
148 return label
& label_abs
;
151 void set_neg(Temp neg_temp
)
153 add_label(label_neg
);
159 return label
& label_neg
;
162 void set_neg_abs(Temp neg_abs_temp
)
164 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
168 void set_mul(Instruction
* mul
)
170 add_label(label_mul
);
176 return label
& label_mul
;
179 void set_temp(Temp tmp
)
181 add_label(label_temp
);
187 return label
& label_temp
;
190 void set_literal(uint32_t lit
)
192 add_label(label_literal
);
198 return label
& label_literal
;
201 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
203 add_label(label_mad
);
210 return label
& label_mad
;
213 void set_omod2(Temp def
)
215 add_label(label_omod2
);
221 return label
& label_omod2
;
224 void set_omod4(Temp def
)
226 add_label(label_omod4
);
232 return label
& label_omod4
;
235 void set_omod5(Temp def
)
237 add_label(label_omod5
);
243 return label
& label_omod5
;
246 void set_omod_success(Instruction
* omod_instr
)
248 add_label(label_omod_success
);
252 bool is_omod_success()
254 return label
& label_omod_success
;
257 void set_clamp(Temp def
)
259 add_label(label_clamp
);
265 return label
& label_clamp
;
268 void set_clamp_success(Instruction
* clamp_instr
)
270 add_label(label_clamp_success
);
274 bool is_clamp_success()
276 return label
& label_clamp_success
;
281 add_label(label_undefined
);
286 return label
& label_undefined
;
289 void set_vcc(Temp vcc
)
291 add_label(label_vcc
);
297 return label
& label_vcc
;
300 bool is_constant_or_literal()
302 return is_constant() || is_literal();
305 void set_b2f(Temp val
)
307 add_label(label_b2f
);
313 return label
& label_b2f
;
316 void set_add_sub(Instruction
*add_sub_instr
)
318 add_label(label_add_sub
);
319 instr
= add_sub_instr
;
324 return label
& label_add_sub
;
327 void set_bitwise(Instruction
*bitwise_instr
)
329 add_label(label_bitwise
);
330 instr
= bitwise_instr
;
335 return label
& label_bitwise
;
338 void set_minmax(Instruction
*minmax_instr
)
340 add_label(label_minmax
);
341 instr
= minmax_instr
;
346 return label
& label_minmax
;
349 void set_fcmp(Instruction
*fcmp_instr
)
351 add_label(label_fcmp
);
357 return label
& label_fcmp
;
360 void set_uniform_bool(Temp uniform_bool
)
362 add_label(label_uniform_bool
);
366 bool is_uniform_bool()
368 return label
& label_uniform_bool
;
375 std::vector
<aco_ptr
<Instruction
>> instructions
;
377 std::pair
<uint32_t,Temp
> last_literal
;
378 std::vector
<mad_info
> mad_infos
;
379 std::vector
<uint16_t> uses
;
382 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
384 if (instr
->operands
[0].isConstant() ||
385 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
388 switch (instr
->opcode
) {
389 case aco_opcode::v_add_f32
:
390 case aco_opcode::v_mul_f32
:
391 case aco_opcode::v_or_b32
:
392 case aco_opcode::v_and_b32
:
393 case aco_opcode::v_xor_b32
:
394 case aco_opcode::v_max_f32
:
395 case aco_opcode::v_min_f32
:
396 case aco_opcode::v_max_i32
:
397 case aco_opcode::v_min_i32
:
398 case aco_opcode::v_max_u32
:
399 case aco_opcode::v_min_u32
:
400 case aco_opcode::v_cmp_eq_f32
:
401 case aco_opcode::v_cmp_lg_f32
:
403 case aco_opcode::v_sub_f32
:
404 instr
->opcode
= aco_opcode::v_subrev_f32
;
406 case aco_opcode::v_cmp_lt_f32
:
407 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
409 case aco_opcode::v_cmp_ge_f32
:
410 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
412 case aco_opcode::v_cmp_lt_i32
:
413 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
420 bool can_use_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
425 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
428 if (instr
->isDPP() || instr
->isSDWA())
431 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
432 instr
->opcode
!= aco_opcode::v_madak_f32
&&
433 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
434 instr
->opcode
!= aco_opcode::v_madak_f16
&&
435 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
436 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
437 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
438 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
439 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
440 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
441 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
444 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
446 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
447 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
448 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
449 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
450 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
453 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
458 aco_ptr
<Instruction
> tmp
= std::move(instr
);
459 Format format
= asVOP3(tmp
->format
);
460 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
461 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
462 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
463 instr
->definitions
[i
] = tmp
->definitions
[i
];
464 if (instr
->definitions
[i
].isTemp()) {
465 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
466 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
467 info
.instr
= instr
.get();
472 /* only covers special cases */
473 bool can_accept_constant(aco_ptr
<Instruction
>& instr
, unsigned operand
)
475 switch (instr
->opcode
) {
476 case aco_opcode::v_interp_p2_f32
:
477 case aco_opcode::v_mac_f32
:
478 case aco_opcode::v_writelane_b32
:
479 case aco_opcode::v_writelane_b32_e64
:
480 case aco_opcode::v_cndmask_b32
:
482 case aco_opcode::s_addk_i32
:
483 case aco_opcode::s_mulk_i32
:
484 case aco_opcode::p_wqm
:
485 case aco_opcode::p_extract_vector
:
486 case aco_opcode::p_split_vector
:
487 case aco_opcode::v_readlane_b32
:
488 case aco_opcode::v_readlane_b32_e64
:
489 case aco_opcode::v_readfirstlane_b32
:
492 if ((instr
->format
== Format::MUBUF
||
493 instr
->format
== Format::MIMG
) &&
494 instr
->definitions
.size() == 1 &&
495 instr
->operands
.size() == 4) {
502 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
504 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
505 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
510 /* check constant bus and literal limitations */
511 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
513 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
514 Operand
literal32(s1
);
515 Operand
literal64(s2
);
516 unsigned num_sgprs
= 0;
517 unsigned sgpr
[] = {0, 0};
519 for (unsigned i
= 0; i
< num_operands
; i
++) {
520 Operand op
= operands
[i
];
522 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
523 /* two reads of the same SGPR count as 1 to the limit */
524 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
526 sgpr
[num_sgprs
++] = op
.tempId();
531 } else if (op
.isLiteral()) {
532 if (ctx
.program
->chip_class
< GFX10
)
535 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
537 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
540 /* Any number of 32-bit literals counts as only 1 to the limit. Same
541 * (but separately) for 64-bit literals. */
542 if (op
.size() == 1 && literal32
.isUndefined()) {
545 } else if (op
.size() == 2 && literal64
.isUndefined()) {
558 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
560 Operand op
= instr
->operands
[op_index
];
564 Temp tmp
= op
.getTemp();
565 if (!ctx
.info
[tmp
.id()].is_add_sub())
568 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
570 switch (add_instr
->opcode
) {
571 case aco_opcode::v_add_u32
:
572 case aco_opcode::v_add_co_u32
:
573 case aco_opcode::s_add_i32
:
574 case aco_opcode::s_add_u32
:
580 if (add_instr
->usesModifiers())
583 for (unsigned i
= 0; i
< 2; i
++) {
584 if (add_instr
->operands
[i
].isConstant()) {
585 *offset
= add_instr
->operands
[i
].constantValue();
586 } else if (add_instr
->operands
[i
].isTemp() &&
587 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
588 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
592 if (!add_instr
->operands
[!i
].isTemp())
595 uint32_t offset2
= 0;
596 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
599 *base
= add_instr
->operands
[!i
].getTemp();
607 Operand
get_constant_op(opt_ctx
&ctx
, uint32_t val
)
609 // TODO: this functions shouldn't be needed if we store Operand instead of value.
611 if (val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
612 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
616 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
618 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
619 ASSERTED
bool all_const
= false;
620 for (Operand
& op
: instr
->operands
)
621 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
622 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
625 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
627 if (!instr
->operands
[i
].isTemp())
630 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
631 /* propagate undef */
632 if (info
.is_undefined() && is_phi(instr
))
633 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
634 /* propagate reg->reg of same type */
635 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
636 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
637 info
= ctx
.info
[info
.temp
.id()];
640 /* SALU / PSEUDO: propagate inline constants */
641 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
642 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
643 instr
->operands
[i
].setTemp(info
.temp
);
644 info
= ctx
.info
[info
.temp
.id()];
645 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
646 /* propagate vgpr if it can take it */
647 switch (instr
->opcode
) {
648 case aco_opcode::p_create_vector
:
649 case aco_opcode::p_split_vector
:
650 case aco_opcode::p_extract_vector
:
651 case aco_opcode::p_phi
: {
652 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
653 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
655 instr
->operands
[i
] = Operand(info
.temp
);
656 info
= ctx
.info
[info
.temp
.id()];
664 if ((info
.is_constant() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) && !instr
->operands
[i
].isFixed() && can_accept_constant(instr
, i
)) {
665 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
670 /* VALU: propagate neg, abs & inline constants */
671 else if (instr
->isVALU()) {
672 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
673 instr
->operands
[i
].setTemp(info
.temp
);
674 info
= ctx
.info
[info
.temp
.id()];
676 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
679 instr
->operands
[i
] = Operand(info
.temp
);
681 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
683 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
685 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
686 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
687 instr
->operands
[i
].setTemp(info
.temp
);
689 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
692 instr
->operands
[i
].setTemp(info
.temp
);
694 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
696 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
699 if (info
.is_constant() && can_accept_constant(instr
, i
)) {
700 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
701 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
702 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
704 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
705 instr
->operands
[i
] = instr
->operands
[0];
706 instr
->operands
[0] = get_constant_op(ctx
, info
.val
);
708 } else if (can_use_VOP3(ctx
, instr
)) {
710 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
716 /* MUBUF: propagate constants and combine additions */
717 else if (instr
->format
== Format::MUBUF
) {
718 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
721 while (info
.is_temp())
722 info
= ctx
.info
[info
.temp
.id()];
724 if (mubuf
->offen
&& i
== 0 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
725 assert(!mubuf
->idxen
);
726 instr
->operands
[i
] = Operand(v1
);
727 mubuf
->offset
+= info
.val
;
728 mubuf
->offen
= false;
730 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
731 instr
->operands
[2] = Operand((uint32_t) 0);
732 mubuf
->offset
+= info
.val
;
734 } else if (mubuf
->offen
&& i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
735 assert(!mubuf
->idxen
);
736 instr
->operands
[i
].setTemp(base
);
737 mubuf
->offset
+= offset
;
739 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
740 instr
->operands
[i
].setTemp(base
);
741 mubuf
->offset
+= offset
;
746 /* DS: combine additions */
747 else if (instr
->format
== Format::DS
) {
749 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
752 if (i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == instr
->operands
[i
].regClass() && instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
753 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
754 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
755 if (offset
% 4 == 0 &&
756 ds
->offset0
+ (offset
>> 2) <= 255 &&
757 ds
->offset1
+ (offset
>> 2) <= 255) {
758 instr
->operands
[i
].setTemp(base
);
759 ds
->offset0
+= offset
>> 2;
760 ds
->offset1
+= offset
>> 2;
763 if (ds
->offset0
+ offset
<= 65535) {
764 instr
->operands
[i
].setTemp(base
);
765 ds
->offset0
+= offset
;
771 /* SMEM: propagate constants and combine additions */
772 else if (instr
->format
== Format::SMEM
) {
774 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
777 if (i
== 1 && info
.is_constant_or_literal() &&
778 (ctx
.program
->chip_class
< GFX8
|| info
.val
<= 0xFFFFF)) {
779 instr
->operands
[i
] = Operand(info
.val
);
781 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
782 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
784 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
785 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
789 smem
->operands
[1] = Operand(offset
);
790 smem
->operands
.back() = Operand(base
);
792 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
793 new_instr
->operands
[0] = smem
->operands
[0];
794 new_instr
->operands
[1] = Operand(offset
);
795 if (smem
->definitions
.empty())
796 new_instr
->operands
[2] = smem
->operands
[2];
797 new_instr
->operands
.back() = Operand(base
);
798 if (!smem
->definitions
.empty())
799 new_instr
->definitions
[0] = smem
->definitions
[0];
800 new_instr
->can_reorder
= smem
->can_reorder
;
801 new_instr
->barrier
= smem
->barrier
;
802 instr
.reset(new_instr
);
803 smem
= static_cast<SMEM_instruction
*>(instr
.get());
810 /* if this instruction doesn't define anything, return */
811 if (instr
->definitions
.empty())
814 switch (instr
->opcode
) {
815 case aco_opcode::p_create_vector
: {
816 unsigned num_ops
= instr
->operands
.size();
817 for (const Operand
& op
: instr
->operands
) {
818 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
819 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
821 if (num_ops
!= instr
->operands
.size()) {
822 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
823 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
824 instr
->definitions
[0] = old_vec
->definitions
[0];
826 for (Operand
& old_op
: old_vec
->operands
) {
827 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
828 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
829 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
830 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
831 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
832 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
833 instr
->operands
[k
++] = op
;
836 instr
->operands
[k
++] = old_op
;
839 assert(k
== num_ops
);
841 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
842 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
843 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
844 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
847 case aco_opcode::p_split_vector
: {
848 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
850 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
851 assert(instr
->definitions
.size() == vec
->operands
.size());
852 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
853 Operand vec_op
= vec
->operands
[i
];
854 if (vec_op
.isConstant()) {
855 if (vec_op
.isLiteral())
856 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
857 else if (vec_op
.size() == 1)
858 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
860 assert(vec_op
.isTemp());
861 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
866 case aco_opcode::p_extract_vector
: { /* mov */
867 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
869 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
870 if (vec
->definitions
[0].getTemp().size() == vec
->operands
.size() && /* TODO: what about 64bit or other combinations? */
871 vec
->operands
[0].size() == instr
->definitions
[0].size()) {
873 /* convert this extract into a mov instruction */
874 Operand vec_op
= vec
->operands
[instr
->operands
[1].constantValue()];
875 bool is_vgpr
= instr
->definitions
[0].getTemp().type() == RegType::vgpr
;
876 aco_opcode opcode
= is_vgpr
? aco_opcode::v_mov_b32
: aco_opcode::s_mov_b32
;
877 Format format
= is_vgpr
? Format::VOP1
: Format::SOP1
;
878 instr
->opcode
= opcode
;
879 instr
->format
= format
;
880 while (instr
->operands
.size() > 1)
881 instr
->operands
.pop_back();
882 instr
->operands
[0] = vec_op
;
884 if (vec_op
.isConstant()) {
885 if (vec_op
.isLiteral())
886 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(vec_op
.constantValue());
887 else if (vec_op
.size() == 1)
888 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(vec_op
.constantValue());
890 assert(vec_op
.isTemp());
891 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vec_op
.getTemp());
896 case aco_opcode::s_mov_b32
: /* propagate */
897 case aco_opcode::s_mov_b64
:
898 case aco_opcode::v_mov_b32
:
899 case aco_opcode::p_as_uniform
:
900 if (instr
->definitions
[0].isFixed()) {
901 /* don't copy-propagate copies into fixed registers */
902 } else if (instr
->usesModifiers()) {
904 } else if (instr
->operands
[0].isConstant()) {
905 if (instr
->operands
[0].isLiteral())
906 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
907 else if (instr
->operands
[0].size() == 1)
908 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
909 } else if (instr
->operands
[0].isTemp()) {
910 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
912 assert(instr
->operands
[0].isFixed());
915 case aco_opcode::p_is_helper
:
916 if (!ctx
.program
->needs_wqm
)
917 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
919 case aco_opcode::s_movk_i32
: {
920 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
921 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
922 if (v
<= 64 || v
>= 0xfffffff0)
923 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
925 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
928 case aco_opcode::v_bfrev_b32
:
929 case aco_opcode::s_brev_b32
: {
930 if (instr
->operands
[0].isConstant()) {
931 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
932 if (v
<= 64 || v
>= 0xfffffff0)
933 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
935 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
939 case aco_opcode::s_bfm_b32
: {
940 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
941 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
942 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
943 uint32_t v
= ((1u << size
) - 1u) << start
;
944 if (v
<= 64 || v
>= 0xfffffff0)
945 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
947 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
950 case aco_opcode::v_mul_f32
: { /* omod */
951 /* TODO: try to move the negate/abs modifier to the consumer instead */
952 if (instr
->usesModifiers())
955 for (unsigned i
= 0; i
< 2; i
++) {
956 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
957 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
958 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
959 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
960 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
961 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
962 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
963 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000 &&
964 !block
.fp_mode
.must_flush_denorms32
) { /* 1.0 */
965 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
974 case aco_opcode::v_and_b32
: /* abs */
975 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x7FFFFFFF) &&
976 instr
->operands
[1].isTemp() && instr
->operands
[1].getTemp().type() == RegType::vgpr
)
977 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
979 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
981 case aco_opcode::v_xor_b32
: { /* neg */
982 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
983 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
984 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
985 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
986 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
987 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
988 instr
->opcode
= aco_opcode::v_or_b32
;
989 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
991 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
995 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
999 case aco_opcode::v_med3_f32
: { /* clamp */
1000 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1001 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1002 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1003 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1007 bool found_zero
= false, found_one
= false;
1008 for (unsigned i
= 0; i
< 3; i
++)
1010 if (instr
->operands
[i
].constantEquals(0))
1012 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1017 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1018 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1022 case aco_opcode::v_cndmask_b32
:
1023 if (instr
->operands
[0].constantEquals(0) &&
1024 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
1025 instr
->operands
[2].isTemp())
1026 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1027 else if (instr
->operands
[0].constantEquals(0) &&
1028 instr
->operands
[1].constantEquals(0x3f800000u
) &&
1029 instr
->operands
[2].isTemp())
1030 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1032 case aco_opcode::v_cmp_lg_u32
:
1033 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1034 instr
->operands
[0].constantEquals(0) &&
1035 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1036 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1038 case aco_opcode::p_phi
:
1039 case aco_opcode::p_linear_phi
: {
1040 /* lower_bool_phis() can create phis like this */
1041 bool all_same_temp
= instr
->operands
[0].isTemp();
1042 /* this check is needed when moving uniform loop counters out of a divergent loop */
1044 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1045 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1046 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1047 all_same_temp
= false;
1049 if (all_same_temp
) {
1050 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1052 bool all_undef
= instr
->operands
[0].isUndefined();
1053 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1054 if (!instr
->operands
[i
].isUndefined())
1058 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1062 case aco_opcode::v_add_u32
:
1063 case aco_opcode::v_add_co_u32
:
1064 case aco_opcode::s_add_i32
:
1065 case aco_opcode::s_add_u32
:
1066 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1068 case aco_opcode::s_and_b32
:
1069 case aco_opcode::s_and_b64
:
1070 if (instr
->operands
[1].isFixed() && instr
->operands
[1].physReg() == exec
&&
1071 instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1072 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1075 case aco_opcode::s_not_b32
:
1076 case aco_opcode::s_not_b64
:
1077 case aco_opcode::s_or_b32
:
1078 case aco_opcode::s_or_b64
:
1079 case aco_opcode::s_xor_b32
:
1080 case aco_opcode::s_xor_b64
:
1081 case aco_opcode::s_lshl_b32
:
1082 case aco_opcode::v_or_b32
:
1083 case aco_opcode::v_lshlrev_b32
:
1084 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1086 case aco_opcode::v_min_f32
:
1087 case aco_opcode::v_min_f16
:
1088 case aco_opcode::v_min_u32
:
1089 case aco_opcode::v_min_i32
:
1090 case aco_opcode::v_min_u16
:
1091 case aco_opcode::v_min_i16
:
1092 case aco_opcode::v_max_f32
:
1093 case aco_opcode::v_max_f16
:
1094 case aco_opcode::v_max_u32
:
1095 case aco_opcode::v_max_i32
:
1096 case aco_opcode::v_max_u16
:
1097 case aco_opcode::v_max_i16
:
1098 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1100 case aco_opcode::v_cmp_lt_f32
:
1101 case aco_opcode::v_cmp_eq_f32
:
1102 case aco_opcode::v_cmp_le_f32
:
1103 case aco_opcode::v_cmp_gt_f32
:
1104 case aco_opcode::v_cmp_lg_f32
:
1105 case aco_opcode::v_cmp_ge_f32
:
1106 case aco_opcode::v_cmp_o_f32
:
1107 case aco_opcode::v_cmp_u_f32
:
1108 case aco_opcode::v_cmp_nge_f32
:
1109 case aco_opcode::v_cmp_nlg_f32
:
1110 case aco_opcode::v_cmp_ngt_f32
:
1111 case aco_opcode::v_cmp_nle_f32
:
1112 case aco_opcode::v_cmp_neq_f32
:
1113 case aco_opcode::v_cmp_nlt_f32
:
1114 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1116 case aco_opcode::s_cselect_b64
:
1117 case aco_opcode::s_cselect_b32
:
1118 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1119 instr
->operands
[1].constantEquals(0)) {
1120 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1121 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1129 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1131 *ordered
= *unordered
= op
;
1133 #define CMP(ord, unord) \
1134 case aco_opcode::v_cmp_##ord##_f32:\
1135 case aco_opcode::v_cmp_n##unord##_f32:\
1136 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1137 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1138 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1152 aco_opcode
get_ordered(aco_opcode op
)
1154 aco_opcode ordered
, unordered
, inverse
;
1155 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1158 aco_opcode
get_unordered(aco_opcode op
)
1160 aco_opcode ordered
, unordered
, inverse
;
1161 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1164 aco_opcode
get_inverse(aco_opcode op
)
1166 aco_opcode ordered
, unordered
, inverse
;
1167 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1170 bool is_cmp(aco_opcode op
)
1172 aco_opcode ordered
, unordered
, inverse
;
1173 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1176 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1178 if (ctx
.info
[tmp
.id()].is_temp())
1179 return ctx
.info
[tmp
.id()].temp
.id();
1184 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1186 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1187 for (const Operand
& op
: instr
->operands
) {
1189 ctx
.uses
[op
.tempId()]--;
1194 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1196 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1198 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1201 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1203 if (instr
->definitions
.size() == 2) {
1204 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1205 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1212 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1213 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1214 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1216 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1218 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1221 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1223 bool neg
[2] = {false, false};
1224 bool abs
[2] = {false, false};
1226 Instruction
*op_instr
[2];
1229 for (unsigned i
= 0; i
< 2; i
++) {
1230 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1234 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1236 if (op_instr
[i
]->opcode
!= expected_cmp
)
1238 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1241 if (op_instr
[i
]->isVOP3()) {
1242 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1243 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1245 neg
[i
] = vop3
->neg
[0];
1246 abs
[i
] = vop3
->abs
[0];
1247 opsel
|= (vop3
->opsel
& 1) << i
;
1250 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1251 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1252 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1258 if (op
[1].type() == RegType::sgpr
)
1259 std::swap(op
[0], op
[1]);
1260 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1261 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1264 ctx
.uses
[op
[0].id()]++;
1265 ctx
.uses
[op
[1].id()]++;
1266 decrease_uses(ctx
, op_instr
[0]);
1267 decrease_uses(ctx
, op_instr
[1]);
1269 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1270 Instruction
*new_instr
;
1271 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1272 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1273 for (unsigned i
= 0; i
< 2; i
++) {
1274 vop3
->neg
[i
] = neg
[i
];
1275 vop3
->abs
[i
] = abs
[i
];
1277 vop3
->opsel
= opsel
;
1278 new_instr
= static_cast<Instruction
*>(vop3
);
1280 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1282 new_instr
->operands
[0] = Operand(op
[0]);
1283 new_instr
->operands
[1] = Operand(op
[1]);
1284 new_instr
->definitions
[0] = instr
->definitions
[0];
1286 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1287 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1289 instr
.reset(new_instr
);
1294 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1295 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1296 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1298 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1300 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1303 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1304 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1306 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1307 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1308 if (!nan_test
|| !cmp
)
1311 if (cmp
->opcode
== expected_nan_test
)
1312 std::swap(nan_test
, cmp
);
1313 else if (nan_test
->opcode
!= expected_nan_test
)
1316 if (!is_cmp(cmp
->opcode
))
1319 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1321 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1324 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1325 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1326 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1327 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1328 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1330 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1333 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1334 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1335 decrease_uses(ctx
, nan_test
);
1336 decrease_uses(ctx
, cmp
);
1338 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1339 Instruction
*new_instr
;
1340 if (cmp
->isVOP3()) {
1341 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1342 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1343 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1344 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1345 new_vop3
->clamp
= cmp_vop3
->clamp
;
1346 new_vop3
->omod
= cmp_vop3
->omod
;
1347 new_vop3
->opsel
= cmp_vop3
->opsel
;
1348 new_instr
= new_vop3
;
1350 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1352 new_instr
->operands
[0] = cmp
->operands
[0];
1353 new_instr
->operands
[1] = cmp
->operands
[1];
1354 new_instr
->definitions
[0] = instr
->definitions
[0];
1356 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1357 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1359 instr
.reset(new_instr
);
1364 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1365 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1366 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1368 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1370 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1373 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1375 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1376 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1378 if (!nan_test
|| !cmp
)
1381 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1382 if (cmp
->opcode
== expected_nan_test
)
1383 std::swap(nan_test
, cmp
);
1384 else if (nan_test
->opcode
!= expected_nan_test
)
1387 if (!is_cmp(cmp
->opcode
))
1390 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1392 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1395 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1396 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1397 if (prop_nan0
!= prop_nan1
)
1400 if (nan_test
->isVOP3()) {
1401 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1402 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1406 int constant_operand
= -1;
1407 for (unsigned i
= 0; i
< 2; i
++) {
1408 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1409 constant_operand
= !i
;
1413 if (constant_operand
== -1)
1417 if (cmp
->operands
[constant_operand
].isConstant()) {
1418 constant
= cmp
->operands
[constant_operand
].constantValue();
1419 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1420 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1421 unsigned id
= original_temp_id(ctx
, tmp
);
1422 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1424 constant
= ctx
.info
[id
].val
;
1430 memcpy(&constantf
, &constant
, 4);
1431 if (isnan(constantf
))
1434 if (cmp
->operands
[0].isTemp())
1435 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1436 if (cmp
->operands
[1].isTemp())
1437 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1438 decrease_uses(ctx
, nan_test
);
1439 decrease_uses(ctx
, cmp
);
1441 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1442 Instruction
*new_instr
;
1443 if (cmp
->isVOP3()) {
1444 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1445 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1446 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1447 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1448 new_vop3
->clamp
= cmp_vop3
->clamp
;
1449 new_vop3
->omod
= cmp_vop3
->omod
;
1450 new_vop3
->opsel
= cmp_vop3
->opsel
;
1451 new_instr
= new_vop3
;
1453 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1455 new_instr
->operands
[0] = cmp
->operands
[0];
1456 new_instr
->operands
[1] = cmp
->operands
[1];
1457 new_instr
->definitions
[0] = instr
->definitions
[0];
1459 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1460 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1462 instr
.reset(new_instr
);
1467 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1468 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1470 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1472 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1474 if (!instr
->operands
[0].isTemp())
1477 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1481 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1482 if (new_opcode
== aco_opcode::last_opcode
)
1485 if (cmp
->operands
[0].isTemp())
1486 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1487 if (cmp
->operands
[1].isTemp())
1488 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1489 decrease_uses(ctx
, cmp
);
1491 Instruction
*new_instr
;
1492 if (cmp
->isVOP3()) {
1493 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1494 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1495 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1496 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1497 new_vop3
->clamp
= cmp_vop3
->clamp
;
1498 new_vop3
->omod
= cmp_vop3
->omod
;
1499 new_vop3
->opsel
= cmp_vop3
->opsel
;
1500 new_instr
= new_vop3
;
1502 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1504 new_instr
->operands
[0] = cmp
->operands
[0];
1505 new_instr
->operands
[1] = cmp
->operands
[1];
1506 new_instr
->definitions
[0] = instr
->definitions
[0];
1508 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1509 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1511 instr
.reset(new_instr
);
1516 /* op1(op2(1, 2), 0) if swap = false
1517 * op1(0, op2(1, 2)) if swap = true */
1518 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1519 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1520 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1521 bool *op1_clamp
, uint8_t *op1_omod
,
1522 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1525 if (op1_instr
->opcode
!= op1
)
1528 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1529 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1532 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1533 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1535 /* don't support inbetween clamp/omod */
1536 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1539 /* get operands and modifiers and check inbetween modifiers */
1540 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1541 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1544 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1545 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1549 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1550 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1553 if (inbetween_opsel
)
1554 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1555 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1559 shuffle
[shuffle_str
[0] - '0'] = 0;
1560 shuffle
[shuffle_str
[1] - '0'] = 1;
1561 shuffle
[shuffle_str
[2] - '0'] = 2;
1563 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1564 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1565 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1566 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1567 *opsel
|= 1 << shuffle
[0];
1569 for (unsigned i
= 0; i
< 2; i
++) {
1570 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1571 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1572 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1573 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1574 *opsel
|= 1 << shuffle
[i
+ 1];
1577 /* check operands */
1578 if (!check_vop3_operands(ctx
, 3, operands
))
1584 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1585 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1586 bool clamp
, unsigned omod
)
1588 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1589 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1590 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1591 new_instr
->clamp
= clamp
;
1592 new_instr
->omod
= omod
;
1593 new_instr
->opsel
= opsel
;
1594 new_instr
->operands
[0] = operands
[0];
1595 new_instr
->operands
[1] = operands
[1];
1596 new_instr
->operands
[2] = operands
[2];
1597 new_instr
->definitions
[0] = instr
->definitions
[0];
1598 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1600 instr
.reset(new_instr
);
1603 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1605 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1606 (label_omod_success
| label_clamp_success
);
1608 for (unsigned swap
= 0; swap
< 2; swap
++) {
1609 if (!((1 << swap
) & ops
))
1612 Operand operands
[3];
1613 bool neg
[3], abs
[3], clamp
;
1614 uint8_t opsel
= 0, omod
= 0;
1615 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1616 instr
.get(), swap
, shuffle
,
1617 operands
, neg
, abs
, &opsel
,
1618 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1619 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1620 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1621 if (omod_clamp
& label_omod_success
)
1622 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1623 if (omod_clamp
& label_clamp_success
)
1624 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1631 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
1633 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
1636 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1637 (label_omod_success
| label_clamp_success
);
1639 /* min(-max(a, b), c) -> min3(-a, -b, c) *
1640 * max(-min(a, b), c) -> max3(-a, -b, c) */
1641 for (unsigned swap
= 0; swap
< 2; swap
++) {
1642 Operand operands
[3];
1643 bool neg
[3], abs
[3], clamp
;
1644 uint8_t opsel
= 0, omod
= 0;
1646 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
1647 instr
.get(), swap
, "012",
1648 operands
, neg
, abs
, &opsel
,
1649 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
1651 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1654 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1655 if (omod_clamp
& label_omod_success
)
1656 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1657 if (omod_clamp
& label_clamp_success
)
1658 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1665 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1666 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1667 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1668 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1669 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1670 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1671 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1674 if (!instr
->operands
[0].isTemp())
1676 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1679 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1682 switch (op2_instr
->opcode
) {
1683 case aco_opcode::s_and_b32
:
1684 case aco_opcode::s_or_b32
:
1685 case aco_opcode::s_xor_b32
:
1686 case aco_opcode::s_and_b64
:
1687 case aco_opcode::s_or_b64
:
1688 case aco_opcode::s_xor_b64
:
1694 /* create instruction */
1695 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1696 ctx
.uses
[instr
->operands
[0].tempId()]--;
1697 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1699 switch (op2_instr
->opcode
) {
1700 case aco_opcode::s_and_b32
:
1701 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1703 case aco_opcode::s_or_b32
:
1704 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1706 case aco_opcode::s_xor_b32
:
1707 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1709 case aco_opcode::s_and_b64
:
1710 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1712 case aco_opcode::s_or_b64
:
1713 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1715 case aco_opcode::s_xor_b64
:
1716 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1725 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1726 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1727 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1728 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1729 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1731 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1734 for (unsigned i
= 0; i
< 2; i
++) {
1735 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1736 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1739 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1740 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1743 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1744 instr
->operands
[0] = instr
->operands
[!i
];
1745 instr
->operands
[1] = op2_instr
->operands
[0];
1746 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1748 switch (instr
->opcode
) {
1749 case aco_opcode::s_and_b32
:
1750 instr
->opcode
= aco_opcode::s_andn2_b32
;
1752 case aco_opcode::s_or_b32
:
1753 instr
->opcode
= aco_opcode::s_orn2_b32
;
1755 case aco_opcode::s_and_b64
:
1756 instr
->opcode
= aco_opcode::s_andn2_b64
;
1758 case aco_opcode::s_or_b64
:
1759 instr
->opcode
= aco_opcode::s_orn2_b64
;
1770 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1771 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1773 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1776 for (unsigned i
= 0; i
< 2; i
++) {
1777 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1778 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
|| !op2_instr
->operands
[1].isConstant())
1781 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1782 if (shift
< 1 || shift
> 4)
1785 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1786 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1789 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1790 instr
->operands
[1] = instr
->operands
[!i
];
1791 instr
->operands
[0] = op2_instr
->operands
[0];
1792 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1794 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1795 aco_opcode::s_lshl2_add_u32
,
1796 aco_opcode::s_lshl3_add_u32
,
1797 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1804 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1807 #define MINMAX(type, gfx9) \
1808 case aco_opcode::v_min_##type:\
1809 case aco_opcode::v_max_##type:\
1810 case aco_opcode::v_med3_##type:\
1811 *min = aco_opcode::v_min_##type;\
1812 *max = aco_opcode::v_max_##type;\
1813 *med3 = aco_opcode::v_med3_##type;\
1814 *min3 = aco_opcode::v_min3_##type;\
1815 *max3 = aco_opcode::v_max3_##type;\
1816 *some_gfx9_only = gfx9;\
1830 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1831 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1832 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1833 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1835 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
1836 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
1837 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
1838 aco_opcode other_op
;
1839 if (instr
->opcode
== min
)
1841 else if (instr
->opcode
== max
)
1846 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1847 (label_omod_success
| label_clamp_success
);
1849 for (unsigned swap
= 0; swap
< 2; swap
++) {
1850 Operand operands
[3];
1851 bool neg
[3], abs
[3], clamp
;
1852 uint8_t opsel
= 0, omod
= 0;
1853 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1854 "012", operands
, neg
, abs
, &opsel
,
1855 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1856 int const0_idx
= -1, const1_idx
= -1;
1857 uint32_t const0
= 0, const1
= 0;
1858 for (int i
= 0; i
< 3; i
++) {
1860 if (operands
[i
].isConstant()) {
1861 val
= operands
[i
].constantValue();
1862 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
1863 val
= ctx
.info
[operands
[i
].tempId()].val
;
1867 if (const0_idx
>= 0) {
1875 if (const0_idx
< 0 || const1_idx
< 0)
1878 if (opsel
& (1 << const0_idx
))
1880 if (opsel
& (1 << const1_idx
))
1883 int lower_idx
= const0_idx
;
1885 case aco_opcode::v_min_f32
:
1886 case aco_opcode::v_min_f16
: {
1887 float const0_f
, const1_f
;
1888 if (min
== aco_opcode::v_min_f32
) {
1889 memcpy(&const0_f
, &const0
, 4);
1890 memcpy(&const1_f
, &const1
, 4);
1892 const0_f
= _mesa_half_to_float(const0
);
1893 const1_f
= _mesa_half_to_float(const1
);
1895 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
1896 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
1897 if (neg
[const0_idx
]) const0_f
= -const0_f
;
1898 if (neg
[const1_idx
]) const1_f
= -const1_f
;
1899 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
1902 case aco_opcode::v_min_u32
: {
1903 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
1906 case aco_opcode::v_min_u16
: {
1907 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
1910 case aco_opcode::v_min_i32
: {
1911 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
1912 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
1913 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1916 case aco_opcode::v_min_i16
: {
1917 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
1918 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
1919 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1925 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
1927 if (instr
->opcode
== min
) {
1928 if (upper_idx
!= 0 || lower_idx
== 0)
1931 if (upper_idx
== 0 || lower_idx
!= 0)
1935 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1936 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1937 if (omod_clamp
& label_omod_success
)
1938 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1939 if (omod_clamp
& label_clamp_success
)
1940 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1950 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1952 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
1953 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
1954 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
1956 /* find candidates and create the set of sgprs already read */
1957 unsigned sgpr_ids
[2] = {0, 0};
1958 uint32_t operand_mask
= 0;
1959 bool has_literal
= false;
1960 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
1961 if (instr
->operands
[i
].isLiteral())
1963 if (!instr
->operands
[i
].isTemp())
1965 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
1966 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
1967 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
1969 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
1970 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
1971 operand_mask
|= 1u << i
;
1973 unsigned max_sgprs
= 1;
1974 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
1979 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
1981 /* keep on applying sgprs until there is nothing left to be done */
1982 while (operand_mask
) {
1983 uint32_t sgpr_idx
= 0;
1984 uint32_t sgpr_info_id
= 0;
1985 uint32_t mask
= operand_mask
;
1988 unsigned i
= u_bit_scan(&mask
);
1989 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
1990 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
1992 sgpr_info_id
= instr
->operands
[i
].tempId();
1995 operand_mask
&= ~(1u << sgpr_idx
);
1997 /* Applying two sgprs require making it VOP3, so don't do it unless it's
1998 * definitively beneficial.
1999 * TODO: this is too conservative because later the use count could be reduced to 1 */
2000 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2003 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2004 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2005 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2008 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2009 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2010 } else if (can_swap_operands(instr
)) {
2011 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2012 instr
->operands
[0] = Operand(sgpr
);
2013 /* swap bits using a 4-entry LUT */
2014 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2015 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2016 } else if (can_use_VOP3(ctx
, instr
)) {
2017 to_VOP3(ctx
, instr
);
2018 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2023 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2024 ctx
.uses
[sgpr_info_id
]--;
2025 ctx
.uses
[sgpr
.id()]++;
2029 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2031 /* check if we could apply omod on predecessor */
2032 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
2033 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2034 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2036 unsigned idx
= op0
? 0 : 1;
2037 /* omod was successfully applied */
2038 /* if the omod instruction is v_mad, we also have to change the original add */
2039 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2040 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2041 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2042 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2043 add_instr
->definitions
[0] = instr
->definitions
[0];
2046 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2047 /* check if we have an additional clamp modifier */
2048 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2049 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2050 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2051 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2053 /* change definition ssa-id of modified instruction */
2054 omod_instr
->definitions
[0] = instr
->definitions
[0];
2056 /* change the definition of instr to something unused, e.g. the original omod def */
2057 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2058 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2061 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2062 /* in all other cases, label this instruction as option for multiply-add */
2063 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2067 /* check if we could apply clamp on predecessor */
2068 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
2070 bool found_zero
= false, found_one
= false;
2071 for (unsigned i
= 0; i
< 3; i
++)
2073 if (instr
->operands
[i
].constantEquals(0))
2075 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
2080 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2081 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2082 /* clamp was successfully applied */
2083 /* if the clamp instruction is v_mad, we also have to change the original add */
2084 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2085 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2086 add_instr
->definitions
[0] = instr
->definitions
[0];
2088 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2089 /* change definition ssa-id of modified instruction */
2090 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2092 /* change the definition of instr to something unused, e.g. the original omod def */
2093 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2094 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2099 /* omod has no effect if denormals are enabled */
2100 bool can_use_omod
= block
.fp_mode
.denorm32
== 0;
2102 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2103 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2104 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2105 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2106 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2107 to_VOP3(ctx
, instr
);
2108 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2109 def_info
.set_omod_success(instr
.get());
2110 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2111 to_VOP3(ctx
, instr
);
2112 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2113 def_info
.set_omod_success(instr
.get());
2114 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2115 to_VOP3(ctx
, instr
);
2116 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2117 def_info
.set_omod_success(instr
.get());
2118 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2119 to_VOP3(ctx
, instr
);
2120 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2121 def_info
.set_clamp_success(instr
.get());
2128 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2129 // this would mean that we'd have to fix the instruction uses while value propagation
2131 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2133 if (instr
->definitions
.empty() || !ctx
.uses
[instr
->definitions
[0].tempId()])
2136 if (instr
->isVALU()) {
2137 if (can_apply_sgprs(instr
))
2138 apply_sgprs(ctx
, instr
);
2139 if (apply_omod_clamp(ctx
, block
, instr
))
2143 /* TODO: There are still some peephole optimizations that could be done:
2144 * - abs(a - b) -> s_absdiff_i32
2145 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2146 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2147 * These aren't probably too interesting though.
2148 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2149 * probably more useful than the previously mentioned optimizations.
2150 * The various comparison optimizations also currently only work with 32-bit
2153 /* neg(mul(a, b)) -> mul(neg(a), b) */
2154 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2155 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2157 if (!ctx
.info
[val
.id()].is_mul())
2160 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2162 if (mul_instr
->operands
[0].isLiteral())
2164 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2167 /* convert to mul(neg(a), b) */
2168 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2169 Definition def
= instr
->definitions
[0];
2170 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2171 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2172 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2173 instr
->operands
[0] = mul_instr
->operands
[0];
2174 instr
->operands
[1] = mul_instr
->operands
[1];
2175 instr
->definitions
[0] = def
;
2176 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2177 if (mul_instr
->isVOP3()) {
2178 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2179 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2180 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2181 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2182 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2183 new_mul
->omod
= mul
->omod
;
2185 new_mul
->neg
[0] ^= true;
2186 new_mul
->clamp
= false;
2188 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2191 /* combine mul+add -> mad */
2192 else if ((instr
->opcode
== aco_opcode::v_add_f32
||
2193 instr
->opcode
== aco_opcode::v_sub_f32
||
2194 instr
->opcode
== aco_opcode::v_subrev_f32
) &&
2195 block
.fp_mode
.denorm32
== 0 && !block
.fp_mode
.preserve_signed_zero_inf_nan32
) {
2196 //TODO: we could use fma instead when denormals are enabled if the NIR isn't marked as precise
2198 uint32_t uses_src0
= UINT32_MAX
;
2199 uint32_t uses_src1
= UINT32_MAX
;
2200 Instruction
* mul_instr
= nullptr;
2201 unsigned add_op_idx
;
2202 /* check if any of the operands is a multiplication */
2203 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2204 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2205 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2206 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2208 /* find the 'best' mul instruction to combine with the add */
2209 if (uses_src0
< uses_src1
) {
2210 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2212 } else if (uses_src1
< uses_src0
) {
2213 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2215 } else if (uses_src0
!= UINT32_MAX
) {
2216 /* tiebreaker: quite random what to pick */
2217 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2218 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2221 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2226 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2227 bool neg
[3] = {false, false, false};
2228 bool abs
[3] = {false, false, false};
2231 op
[0] = mul_instr
->operands
[0];
2232 op
[1] = mul_instr
->operands
[1];
2233 op
[2] = instr
->operands
[add_op_idx
];
2234 // TODO: would be better to check this before selecting a mul instr?
2235 if (!check_vop3_operands(ctx
, 3, op
))
2238 if (mul_instr
->isVOP3()) {
2239 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2240 neg
[0] = vop3
->neg
[0];
2241 neg
[1] = vop3
->neg
[1];
2242 abs
[0] = vop3
->abs
[0];
2243 abs
[1] = vop3
->abs
[1];
2244 /* we cannot use these modifiers between mul and add */
2245 if (vop3
->clamp
|| vop3
->omod
)
2249 /* convert to mad */
2250 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2251 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2253 ctx
.uses
[op
[0].tempId()]++;
2255 ctx
.uses
[op
[1].tempId()]++;
2258 if (instr
->isVOP3()) {
2259 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2260 neg
[2] = vop3
->neg
[add_op_idx
];
2261 abs
[2] = vop3
->abs
[add_op_idx
];
2263 clamp
= vop3
->clamp
;
2264 /* abs of the multiplication result */
2265 if (vop3
->abs
[1 - add_op_idx
]) {
2271 /* neg of the multiplication result */
2272 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2274 if (instr
->opcode
== aco_opcode::v_sub_f32
)
2275 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2276 else if (instr
->opcode
== aco_opcode::v_subrev_f32
)
2277 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2279 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2280 for (unsigned i
= 0; i
< 3; i
++)
2282 mad
->operands
[i
] = op
[i
];
2283 mad
->neg
[i
] = neg
[i
];
2284 mad
->abs
[i
] = abs
[i
];
2288 mad
->definitions
[0] = instr
->definitions
[0];
2290 /* mark this ssa_def to be re-checked for profitability and literals */
2291 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2292 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2293 instr
.reset(mad
.release());
2297 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2298 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2299 for (unsigned i
= 0; i
< 2; i
++) {
2300 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2301 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2302 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2303 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2304 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2306 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2307 new_instr
->operands
[0] = Operand(0u);
2308 new_instr
->operands
[1] = instr
->operands
[!i
];
2309 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2310 new_instr
->definitions
[0] = instr
->definitions
[0];
2311 instr
.reset(new_instr
.release());
2312 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2316 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2317 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2318 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2319 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2320 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2321 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2322 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2323 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2324 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2325 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2326 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2327 combine_salu_lshl_add(ctx
, instr
);
2328 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2329 combine_salu_not_bitwise(ctx
, instr
);
2330 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2331 if (combine_inverse_comparison(ctx
, instr
)) ;
2332 else combine_salu_not_bitwise(ctx
, instr
);
2333 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2334 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2335 if (combine_ordering_test(ctx
, instr
)) ;
2336 else if (combine_comparison_ordering(ctx
, instr
)) ;
2337 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2338 else combine_salu_n2(ctx
, instr
);
2340 aco_opcode min
, max
, min3
, max3
, med3
;
2341 bool some_gfx9_only
;
2342 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2343 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2344 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2345 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2351 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2353 const uint32_t threshold
= 4;
2355 if (is_dead(ctx
.uses
, instr
.get())) {
2360 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2361 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2362 unsigned num_used
= 0;
2364 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2365 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2371 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2372 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2373 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2377 for (Operand
& vec_op
: vec
->operands
) {
2378 if (off
== idx
* instr
->definitions
[0].size()) {
2382 off
+= vec_op
.size();
2384 if (off
!= instr
->operands
[0].size()) {
2385 ctx
.uses
[instr
->operands
[0].tempId()]--;
2386 for (Operand
& vec_op
: vec
->operands
) {
2387 if (vec_op
.isTemp())
2388 ctx
.uses
[vec_op
.tempId()]--;
2391 ctx
.uses
[op
.tempId()]++;
2393 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2394 extract
->operands
[0] = op
;
2395 extract
->definitions
[0] = instr
->definitions
[idx
];
2396 instr
.reset(extract
.release());
2402 if (!done
&& num_used
== 1) {
2403 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2404 extract
->operands
[0] = instr
->operands
[0];
2405 extract
->operands
[1] = Operand((uint32_t) idx
);
2406 extract
->definitions
[0] = instr
->definitions
[idx
];
2407 instr
.reset(extract
.release());
2411 mad_info
* mad_info
= NULL
;
2412 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2413 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2414 /* re-check mad instructions */
2415 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2416 ctx
.uses
[mad_info
->mul_temp_id
]++;
2417 if (instr
->operands
[0].isTemp())
2418 ctx
.uses
[instr
->operands
[0].tempId()]--;
2419 if (instr
->operands
[1].isTemp())
2420 ctx
.uses
[instr
->operands
[1].tempId()]--;
2421 instr
.swap(mad_info
->add_instr
);
2424 /* check literals */
2425 else if (!instr
->usesModifiers()) {
2426 bool sgpr_used
= false;
2427 uint32_t literal_idx
= 0;
2428 uint32_t literal_uses
= UINT32_MAX
;
2429 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2431 if (instr
->operands
[i
].isConstant() && i
> 0) {
2432 literal_uses
= UINT32_MAX
;
2435 if (!instr
->operands
[i
].isTemp())
2437 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2438 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2439 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2440 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2443 literal_uses
= UINT32_MAX
;
2446 /* don't break because we still need to check constants */
2447 } else if (!sgpr_used
&&
2448 ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2449 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2450 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2454 if (literal_uses
< threshold
) {
2455 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2456 mad_info
->check_literal
= true;
2457 mad_info
->literal_idx
= literal_idx
;
2463 /* check for literals */
2464 if (!instr
->isSALU() && !instr
->isVALU())
2467 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
2468 return; /* some encodings can't ever take literals */
2470 /* we do not apply the literals yet as we don't know if it is profitable */
2471 Operand
current_literal(s1
);
2473 unsigned literal_id
= 0;
2474 unsigned literal_uses
= UINT32_MAX
;
2475 Operand
literal(s1
);
2476 unsigned num_operands
= 1;
2477 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
2478 num_operands
= instr
->operands
.size();
2480 unsigned sgpr_ids
[2] = {0, 0};
2481 bool is_literal_sgpr
= false;
2484 /* choose a literal to apply */
2485 for (unsigned i
= 0; i
< num_operands
; i
++) {
2486 Operand op
= instr
->operands
[i
];
2487 if (op
.isLiteral()) {
2488 current_literal
= op
;
2490 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal()) {
2491 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
2492 op
.tempId() != sgpr_ids
[0])
2493 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
2497 if (!can_accept_constant(instr
, i
))
2500 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
2501 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
2503 literal
= Operand(ctx
.info
[op
.tempId()].val
);
2504 literal_uses
= ctx
.uses
[op
.tempId()];
2505 literal_id
= op
.tempId();
2508 mask
|= (op
.tempId() == literal_id
) << i
;
2512 /* don't go over the constant bus limit */
2513 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2514 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2515 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2516 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
2517 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2518 const_bus_limit
= 2;
2520 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2521 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
2524 if (literal_id
&& literal_uses
< threshold
&&
2525 (current_literal
.isUndefined() ||
2526 (current_literal
.size() == literal
.size() &&
2527 current_literal
.constantValue() == literal
.constantValue()))) {
2528 /* mark the literal to be applied */
2530 unsigned i
= u_bit_scan(&mask
);
2531 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
2532 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2538 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2540 /* Cleanup Dead Instructions */
2544 /* apply literals on MAD */
2545 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2546 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2547 if (info
->check_literal
&& ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0) {
2548 aco_ptr
<Instruction
> new_mad
;
2549 if (info
->literal_idx
== 2) { /* add literal -> madak */
2550 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2551 new_mad
->operands
[0] = instr
->operands
[0];
2552 new_mad
->operands
[1] = instr
->operands
[1];
2553 } else { /* mul literal -> madmk */
2554 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2555 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2556 new_mad
->operands
[1] = instr
->operands
[2];
2558 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2559 new_mad
->definitions
[0] = instr
->definitions
[0];
2560 ctx
.instructions
.emplace_back(std::move(new_mad
));
2565 /* apply literals on other SALU/VALU */
2566 if (instr
->isSALU() || instr
->isVALU()) {
2567 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2568 Operand op
= instr
->operands
[i
];
2569 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal() && ctx
.uses
[op
.tempId()] == 0) {
2570 Operand
literal(ctx
.info
[op
.tempId()].val
);
2571 if (instr
->isVALU() && i
> 0)
2572 to_VOP3(ctx
, instr
);
2573 instr
->operands
[i
] = literal
;
2578 ctx
.instructions
.emplace_back(std::move(instr
));
2582 void optimize(Program
* program
)
2585 ctx
.program
= program
;
2586 std::vector
<ssa_info
> info(program
->peekAllocationId());
2587 ctx
.info
= info
.data();
2589 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2590 for (Block
& block
: program
->blocks
) {
2591 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2592 label_instruction(ctx
, block
, instr
);
2595 ctx
.uses
= std::move(dead_code_analysis(program
));
2597 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2598 for (Block
& block
: program
->blocks
) {
2599 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2600 combine_instruction(ctx
, block
, instr
);
2603 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2604 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2605 Block
* block
= &(*it
);
2606 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2607 select_instruction(ctx
, *it
);
2610 /* 4. Add literals to instructions */
2611 for (Block
& block
: program
->blocks
) {
2612 ctx
.instructions
.clear();
2613 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2614 apply_literals(ctx
, instr
);
2615 block
.instructions
.swap(ctx
.instructions
);