src/amd/compiler/aco_validate.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "aco_ir.h"
  26
  27 #include <array>
  28 #include <map>
  29
  30 namespace aco {
  31
  32 static void aco_log(Program *program, const char *prefix,
  33                     const char *file, unsigned line,
  34                     const char *fmt, va_list args)
  35 {
  36    char *msg;
  37
  38    msg = ralloc_strdup(NULL, prefix);
  39
  40    ralloc_asprintf_append(&msg, "    In file %s:%u\n", file, line);
  41    ralloc_asprintf_append(&msg, "    ");
  42    ralloc_vasprintf_append(&msg, fmt, args);
  43
  44    /* TODO: log messages via callback if available too. */
  45
  46    fprintf(stderr, "%s\n", msg);
  47
  48    ralloc_free(msg);
  49 }
  50
  51 void _aco_perfwarn(Program *program, const char *file, unsigned line,
  52                    const char *fmt, ...)
  53 {
  54    va_list args;
  55
  56    va_start(args, fmt);
  57    aco_log(program, "ACO PERFWARN:\n", file, line, fmt, args);
  58    va_end(args);
  59 }
  60
  61 void _aco_err(Program *program, const char *file, unsigned line,
  62               const char *fmt, ...)
  63 {
  64    va_list args;
  65
  66    va_start(args, fmt);
  67    aco_log(program, "ACO ERROR:\n", file, line, fmt, args);
  68    va_end(args);
  69 }
  70
  71 bool validate_ir(Program* program)
  72 {
  73    bool is_valid = true;
  74    auto check = [&program, &is_valid](bool check, const char * msg, aco::Instruction * instr) -> void {
  75       if (!check) {
  76          char *out;
  77          size_t outsize;
  78          FILE *memf = open_memstream(&out, &outsize);
  79
  80          fprintf(memf, "%s: ", msg);
  81          aco_print_instr(instr, memf);
  82          fclose(memf);
  83
  84          aco_err(program, out);
  85          free(out);
  86
  87          is_valid = false;
  88       }
  89    };
  90
  91    auto check_block = [&program, &is_valid](bool check, const char * msg, aco::Block * block) -> void {
  92       if (!check) {
  93          aco_err(program, "%s: BB%u", msg, block->index);
  94          is_valid = false;
  95       }
  96    };
  97
  98    for (Block& block : program->blocks) {
  99       for (aco_ptr<Instruction>& instr : block.instructions) {
 100
 101          /* check base format */
 102          Format base_format = instr->format;
 103          base_format = (Format)((uint32_t)base_format & ~(uint32_t)Format::SDWA);
 104          base_format = (Format)((uint32_t)base_format & ~(uint32_t)Format::DPP);
 105          if ((uint32_t)base_format & (uint32_t)Format::VOP1)
 106             base_format = Format::VOP1;
 107          else if ((uint32_t)base_format & (uint32_t)Format::VOP2)
 108             base_format = Format::VOP2;
 109          else if ((uint32_t)base_format & (uint32_t)Format::VOPC)
 110             base_format = Format::VOPC;
 111          else if ((uint32_t)base_format & (uint32_t)Format::VINTRP) {
 112             if (instr->opcode == aco_opcode::v_interp_p1ll_f16 ||
 113                 instr->opcode == aco_opcode::v_interp_p1lv_f16 ||
 114                 instr->opcode == aco_opcode::v_interp_p2_legacy_f16 ||
 115                 instr->opcode == aco_opcode::v_interp_p2_f16) {
 116                /* v_interp_*_fp16 are considered VINTRP by the compiler but
 117                 * they are emitted as VOP3.
 118                 */
 119                base_format = Format::VOP3;
 120             } else {
 121                base_format = Format::VINTRP;
 122             }
 123          }
 124          check(base_format == instr_info.format[(int)instr->opcode], "Wrong base format for instruction", instr.get());
 125
 126          /* check VOP3 modifiers */
 127          if (((uint32_t)instr->format & (uint32_t)Format::VOP3) && instr->format != Format::VOP3) {
 128             check(base_format == Format::VOP2 ||
 129                   base_format == Format::VOP1 ||
 130                   base_format == Format::VOPC ||
 131                   base_format == Format::VINTRP,
 132                   "Format cannot have VOP3A/VOP3B applied", instr.get());
 133          }
 134
 135          /* check SDWA */
 136          if (instr->isSDWA()) {
 137             check(base_format == Format::VOP2 ||
 138                   base_format == Format::VOP1 ||
 139                   base_format == Format::VOPC,
 140                   "Format cannot have SDWA applied", instr.get());
 141
 142             check(program->chip_class >= GFX8, "SDWA is GFX8+ only", instr.get());
 143
 144             SDWA_instruction *sdwa = static_cast<SDWA_instruction*>(instr.get());
 145             check(sdwa->omod == 0 || program->chip_class >= GFX9, "SDWA omod only supported on GFX9+", instr.get());
 146             if (base_format == Format::VOPC) {
 147                check(sdwa->clamp == false || program->chip_class == GFX8, "SDWA VOPC clamp only supported on GFX8", instr.get());
 148                check((instr->definitions[0].isFixed() && instr->definitions[0].physReg() == vcc) ||
 149                      program->chip_class >= GFX9,
 150                      "SDWA+VOPC definition must be fixed to vcc on GFX8", instr.get());
 151             }
 152
 153             if (instr->operands.size() >= 3) {
 154                check(instr->operands[2].isFixed() && instr->operands[2].physReg() == vcc,
 155                      "3rd operand must be fixed to vcc with SDWA", instr.get());
 156             }
 157             if (instr->definitions.size() >= 2) {
 158                check(instr->definitions[1].isFixed() && instr->definitions[1].physReg() == vcc,
 159                      "2nd definition must be fixed to vcc with SDWA", instr.get());
 160             }
 161
 162             check(instr->opcode != aco_opcode::v_madmk_f32 &&
 163                   instr->opcode != aco_opcode::v_madak_f32 &&
 164                   instr->opcode != aco_opcode::v_madmk_f16 &&
 165                   instr->opcode != aco_opcode::v_madak_f16 &&
 166                   instr->opcode != aco_opcode::v_readfirstlane_b32 &&
 167                   instr->opcode != aco_opcode::v_clrexcp &&
 168                   instr->opcode != aco_opcode::v_swap_b32,
 169                   "SDWA can't be used with this opcode", instr.get());
 170             if (program->chip_class != GFX8) {
 171                check(instr->opcode != aco_opcode::v_mac_f32 &&
 172                      instr->opcode != aco_opcode::v_mac_f16 &&
 173                      instr->opcode != aco_opcode::v_fmac_f32 &&
 174                      instr->opcode != aco_opcode::v_fmac_f16,
 175                      "SDWA can't be used with this opcode", instr.get());
 176             }
 177
 178             for (unsigned i = 0; i < MIN2(instr->operands.size(), 2); i++) {
 179                if (instr->operands[i].hasRegClass() && instr->operands[i].regClass().is_subdword())
 180                   check((sdwa->sel[i] & sdwa_asuint) == (sdwa_isra | instr->operands[i].bytes()), "Unexpected SDWA sel for sub-dword operand", instr.get());
 181             }
 182             if (instr->definitions[0].regClass().is_subdword())
 183                check((sdwa->dst_sel & sdwa_asuint) == (sdwa_isra | instr->definitions[0].bytes()), "Unexpected SDWA sel for sub-dword definition", instr.get());
 184          }
 185
 186          /* check opsel */
 187          if (instr->isVOP3()) {
 188             VOP3A_instruction *vop3 = static_cast<VOP3A_instruction*>(instr.get());
 189             check(vop3->opsel == 0 || program->chip_class >= GFX9, "Opsel is only supported on GFX9+", instr.get());
 190
 191             for (unsigned i = 0; i < 3; i++) {
 192                if (i >= instr->operands.size() ||
 193                    (instr->operands[i].hasRegClass() && instr->operands[i].regClass().is_subdword() && !instr->operands[i].isFixed()))
 194                   check((vop3->opsel & (1 << i)) == 0, "Unexpected opsel for operand", instr.get());
 195             }
 196             if (instr->definitions[0].regClass().is_subdword() && !instr->definitions[0].isFixed())
 197                check((vop3->opsel & (1 << 3)) == 0, "Unexpected opsel for sub-dword definition", instr.get());
 198          }
 199
 200          /* check for undefs */
 201          for (unsigned i = 0; i < instr->operands.size(); i++) {
 202             if (instr->operands[i].isUndefined()) {
 203                bool flat = instr->format == Format::FLAT || instr->format == Format::SCRATCH || instr->format == Format::GLOBAL;
 204                bool can_be_undef = is_phi(instr) || instr->format == Format::EXP ||
 205                                    instr->format == Format::PSEUDO_REDUCTION ||
 206                                    instr->opcode == aco_opcode::p_create_vector ||
 207                                    (flat && i == 1) || (instr->format == Format::MIMG && i == 1) ||
 208                                    ((instr->format == Format::MUBUF || instr->format == Format::MTBUF) && i == 1);
 209                check(can_be_undef, "Undefs can only be used in certain operands", instr.get());
 210             } else {
 211                check(instr->operands[i].isFixed() || instr->operands[i].isTemp() || instr->operands[i].isConstant(), "Uninitialized Operand", instr.get());
 212             }
 213          }
 214
 215          /* check subdword definitions */
 216          for (unsigned i = 0; i < instr->definitions.size(); i++) {
 217             if (instr->definitions[i].regClass().is_subdword())
 218                check(instr->format == Format::PSEUDO || instr->definitions[i].bytes() <= 4, "Only Pseudo instructions can write subdword registers larger than 4 bytes", instr.get());
 219          }
 220
 221          if (instr->isSALU() || instr->isVALU()) {
 222             /* check literals */
 223             Operand literal(s1);
 224             for (unsigned i = 0; i < instr->operands.size(); i++)
 225             {
 226                Operand op = instr->operands[i];
 227                if (!op.isLiteral())
 228                   continue;
 229
 230                check(instr->format == Format::SOP1 ||
 231                      instr->format == Format::SOP2 ||
 232                      instr->format == Format::SOPC ||
 233                      instr->format == Format::VOP1 ||
 234                      instr->format == Format::VOP2 ||
 235                      instr->format == Format::VOPC ||
 236                      (instr->isVOP3() && program->chip_class >= GFX10),
 237                      "Literal applied on wrong instruction format", instr.get());
 238
 239                check(literal.isUndefined() || (literal.size() == op.size() && literal.constantValue() == op.constantValue()), "Only 1 Literal allowed", instr.get());
 240                literal = op;
 241                check(!instr->isVALU() || instr->isVOP3() || i == 0 || i == 2, "Wrong source position for Literal argument", instr.get());
 242             }
 243
 244             /* check num sgprs for VALU */
 245             if (instr->isVALU()) {
 246                bool is_shift64 = instr->opcode == aco_opcode::v_lshlrev_b64 ||
 247                                  instr->opcode == aco_opcode::v_lshrrev_b64 ||
 248                                  instr->opcode == aco_opcode::v_ashrrev_i64;
 249                unsigned const_bus_limit = 1;
 250                if (program->chip_class >= GFX10 && !is_shift64)
 251                   const_bus_limit = 2;
 252
 253                uint32_t scalar_mask = instr->isVOP3() ? 0x7 : 0x5;
 254                if (instr->isSDWA())
 255                   scalar_mask = program->chip_class >= GFX9 ? 0x7 : 0x4;
 256
 257                if ((int) instr->format & (int) Format::VOPC ||
 258                    instr->opcode == aco_opcode::v_readfirstlane_b32 ||
 259                    instr->opcode == aco_opcode::v_readlane_b32 ||
 260                    instr->opcode == aco_opcode::v_readlane_b32_e64) {
 261                   check(instr->definitions[0].getTemp().type() == RegType::sgpr,
 262                         "Wrong Definition type for VALU instruction", instr.get());
 263                } else {
 264                   check(instr->definitions[0].getTemp().type() == RegType::vgpr,
 265                         "Wrong Definition type for VALU instruction", instr.get());
 266                }
 267
 268                unsigned num_sgprs = 0;
 269                unsigned sgpr[] = {0, 0};
 270                for (unsigned i = 0; i < instr->operands.size(); i++)
 271                {
 272                   Operand op = instr->operands[i];
 273                   if (instr->opcode == aco_opcode::v_readfirstlane_b32 ||
 274                       instr->opcode == aco_opcode::v_readlane_b32 ||
 275                       instr->opcode == aco_opcode::v_readlane_b32_e64) {
 276                      check(i != 1 ||
 277                            (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
 278                            op.isConstant(),
 279                            "Must be a SGPR or a constant", instr.get());
 280                      check(i == 1 ||
 281                            (op.isTemp() && op.regClass().type() == RegType::vgpr && op.bytes() <= 4),
 282                            "Wrong Operand type for VALU instruction", instr.get());
 283                      continue;
 284                   }
 285
 286                   if (instr->opcode == aco_opcode::v_writelane_b32 ||
 287                       instr->opcode == aco_opcode::v_writelane_b32_e64) {
 288                      check(i != 2 ||
 289                            (op.isTemp() && op.regClass().type() == RegType::vgpr && op.bytes() <= 4),
 290                            "Wrong Operand type for VALU instruction", instr.get());
 291                      check(i == 2 ||
 292                            (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
 293                            op.isConstant(),
 294                            "Must be a SGPR or a constant", instr.get());
 295                      continue;
 296                   }
 297                   if (op.isTemp() && instr->operands[i].regClass().type() == RegType::sgpr) {
 298                      check(scalar_mask & (1 << i), "Wrong source position for SGPR argument", instr.get());
 299
 300                      if (op.tempId() != sgpr[0] && op.tempId() != sgpr[1]) {
 301                         if (num_sgprs < 2)
 302                            sgpr[num_sgprs++] = op.tempId();
 303                      }
 304                   }
 305
 306                   if (op.isConstant() && !op.isLiteral())
 307                      check(scalar_mask & (1 << i), "Wrong source position for constant argument", instr.get());
 308                }
 309                check(num_sgprs + (literal.isUndefined() ? 0 : 1) <= const_bus_limit, "Too many SGPRs/literals", instr.get());
 310             }
 311
 312             if (instr->format == Format::SOP1 || instr->format == Format::SOP2) {
 313                check(instr->definitions[0].getTemp().type() == RegType::sgpr, "Wrong Definition type for SALU instruction", instr.get());
 314                for (const Operand& op : instr->operands) {
 315                  check(op.isConstant() || op.regClass().type() <= RegType::sgpr,
 316                        "Wrong Operand type for SALU instruction", instr.get());
 317             }
 318          }
 319          }
 320
 321          switch (instr->format) {
 322          case Format::PSEUDO: {
 323             bool is_subdword = false;
 324             bool has_const_sgpr = false;
 325             bool has_literal = false;
 326             for (Definition def : instr->definitions)
 327                is_subdword |= def.regClass().is_subdword();
 328             for (unsigned i = 0; i < instr->operands.size(); i++) {
 329                if (instr->opcode == aco_opcode::p_extract_vector && i == 1)
 330                   continue;
 331                Operand op = instr->operands[i];
 332                is_subdword |= op.hasRegClass() && op.regClass().is_subdword();
 333                has_const_sgpr |= op.isConstant() || (op.hasRegClass() && op.regClass().type() == RegType::sgpr);
 334                has_literal |= op.isLiteral();
 335             }
 336
 337             check(!is_subdword || !has_const_sgpr || program->chip_class >= GFX9,
 338                   "Sub-dword pseudo instructions can only take constants or SGPRs on GFX9+", instr.get());
 339             check(!is_subdword || !has_literal, "Sub-dword pseudo instructions cannot take literals", instr.get());
 340
 341             if (instr->opcode == aco_opcode::p_create_vector) {
 342                unsigned size = 0;
 343                for (const Operand& op : instr->operands) {
 344                   size += op.bytes();
 345                }
 346                check(size == instr->definitions[0].bytes(), "Definition size does not match operand sizes", instr.get());
 347                if (instr->definitions[0].getTemp().type() == RegType::sgpr) {
 348                   for (const Operand& op : instr->operands) {
 349                      check(op.isConstant() || op.regClass().type() == RegType::sgpr,
 350                            "Wrong Operand type for scalar vector", instr.get());
 351                   }
 352                }
 353             } else if (instr->opcode == aco_opcode::p_extract_vector) {
 354                check((instr->operands[0].isTemp()) && instr->operands[1].isConstant(), "Wrong Operand types", instr.get());
 355                check((instr->operands[1].constantValue() + 1) * instr->definitions[0].bytes() <= instr->operands[0].bytes(), "Index out of range", instr.get());
 356                check(instr->definitions[0].getTemp().type() == RegType::vgpr || instr->operands[0].regClass().type() == RegType::sgpr,
 357                      "Cannot extract SGPR value from VGPR vector", instr.get());
 358             } else if (instr->opcode == aco_opcode::p_parallelcopy) {
 359                check(instr->definitions.size() == instr->operands.size(), "Number of Operands does not match number of Definitions", instr.get());
 360                for (unsigned i = 0; i < instr->operands.size(); i++) {
 361                   if (instr->operands[i].isTemp())
 362                      check((instr->definitions[i].getTemp().type() == instr->operands[i].regClass().type()) ||
 363                            (instr->definitions[i].getTemp().type() == RegType::vgpr && instr->operands[i].regClass().type() == RegType::sgpr),
 364                            "Operand and Definition types do not match", instr.get());
 365                }
 366             } else if (instr->opcode == aco_opcode::p_phi) {
 367                check(instr->operands.size() == block.logical_preds.size(), "Number of Operands does not match number of predecessors", instr.get());
 368                check(instr->definitions[0].getTemp().type() == RegType::vgpr, "Logical Phi Definition must be vgpr", instr.get());
 369             } else if (instr->opcode == aco_opcode::p_linear_phi) {
 370                for (const Operand& op : instr->operands)
 371                   check(!op.isTemp() || op.getTemp().is_linear(), "Wrong Operand type", instr.get());
 372                check(instr->operands.size() == block.linear_preds.size(), "Number of Operands does not match number of predecessors", instr.get());
 373             }
 374             break;
 375          }
 376          case Format::SMEM: {
 377             if (instr->operands.size() >= 1)
 378                check(instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::sgpr, "SMEM operands must be sgpr", instr.get());
 379             if (instr->operands.size() >= 2)
 380                check(instr->operands[1].isConstant() || (instr->operands[1].isTemp() && instr->operands[1].regClass().type() == RegType::sgpr),
 381                      "SMEM offset must be constant or sgpr", instr.get());
 382             if (!instr->definitions.empty())
 383                check(instr->definitions[0].getTemp().type() == RegType::sgpr, "SMEM result must be sgpr", instr.get());
 384             break;
 385          }
 386          case Format::MTBUF:
 387          case Format::MUBUF: {
 388             check(instr->operands.size() > 1, "VMEM instructions must have at least one operand", instr.get());
 389             check(instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::vgpr,
 390                   "VADDR must be in vgpr for VMEM instructions", instr.get());
 391             check(instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::sgpr, "VMEM resource constant must be sgpr", instr.get());
 392             check(instr->operands.size() < 4 || (instr->operands[3].isTemp() && instr->operands[3].regClass().type() == RegType::vgpr), "VMEM write data must be vgpr", instr.get());
 393             break;
 394          }
 395          case Format::MIMG: {
 396             check(instr->operands.size() == 3, "MIMG instructions must have exactly 3 operands", instr.get());
 397             check(instr->operands[0].hasRegClass() && (instr->operands[0].regClass() == s4 || instr->operands[0].regClass() == s8),
 398                   "MIMG operands[0] (resource constant) must be in 4 or 8 SGPRs", instr.get());
 399             if (instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::sgpr)
 400                check(instr->operands[1].regClass() == s4, "MIMG operands[1] (sampler constant) must be 4 SGPRs", instr.get());
 401             else if (instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::vgpr)
 402                check((instr->definitions.empty() || instr->definitions[0].regClass() == instr->operands[1].regClass() ||
 403                      instr->opcode == aco_opcode::image_atomic_cmpswap || instr->opcode == aco_opcode::image_atomic_fcmpswap),
 404                      "MIMG operands[1] (VDATA) must be the same as definitions[0] for atomics", instr.get());
 405             check(instr->operands[2].hasRegClass() && instr->operands[2].regClass().type() == RegType::vgpr,
 406                   "MIMG operands[2] (VADDR) must be VGPR", instr.get());
 407             check(instr->definitions.empty() || (instr->definitions[0].isTemp() && instr->definitions[0].regClass().type() == RegType::vgpr),
 408                   "MIMG definitions[0] (VDATA) must be VGPR", instr.get());
 409             break;
 410          }
 411          case Format::DS: {
 412             for (const Operand& op : instr->operands) {
 413                check((op.isTemp() && op.regClass().type() == RegType::vgpr) || op.physReg() == m0,
 414                      "Only VGPRs are valid DS instruction operands", instr.get());
 415             }
 416             if (!instr->definitions.empty())
 417                check(instr->definitions[0].getTemp().type() == RegType::vgpr, "DS instruction must return VGPR", instr.get());
 418             break;
 419          }
 420          case Format::EXP: {
 421             for (unsigned i = 0; i < 4; i++)
 422                check(instr->operands[i].hasRegClass() && instr->operands[i].regClass().type() == RegType::vgpr,
 423                      "Only VGPRs are valid Export arguments", instr.get());
 424             break;
 425          }
 426          case Format::FLAT:
 427             check(instr->operands[1].isUndefined(), "Flat instructions don't support SADDR", instr.get());
 428             /* fallthrough */
 429          case Format::GLOBAL:
 430          case Format::SCRATCH: {
 431             check(instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::vgpr, "FLAT/GLOBAL/SCRATCH address must be vgpr", instr.get());
 432             check(instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::sgpr,
 433                   "FLAT/GLOBAL/SCRATCH sgpr address must be undefined or sgpr", instr.get());
 434             if (!instr->definitions.empty())
 435                check(instr->definitions[0].getTemp().type() == RegType::vgpr, "FLAT/GLOBAL/SCRATCH result must be vgpr", instr.get());
 436             else
 437                check(instr->operands[2].regClass().type() == RegType::vgpr, "FLAT/GLOBAL/SCRATCH data must be vgpr", instr.get());
 438             break;
 439          }
 440          default:
 441             break;
 442          }
 443       }
 444    }
 445
 446    /* validate CFG */
 447    for (unsigned i = 0; i < program->blocks.size(); i++) {
 448       Block& block = program->blocks[i];
 449       check_block(block.index == i, "block.index must match actual index", &block);
 450
 451       /* predecessors/successors should be sorted */
 452       for (unsigned j = 0; j + 1 < block.linear_preds.size(); j++)
 453          check_block(block.linear_preds[j] < block.linear_preds[j + 1], "linear predecessors must be sorted", &block);
 454       for (unsigned j = 0; j + 1 < block.logical_preds.size(); j++)
 455          check_block(block.logical_preds[j] < block.logical_preds[j + 1], "logical predecessors must be sorted", &block);
 456       for (unsigned j = 0; j + 1 < block.linear_succs.size(); j++)
 457          check_block(block.linear_succs[j] < block.linear_succs[j + 1], "linear successors must be sorted", &block);
 458       for (unsigned j = 0; j + 1 < block.logical_succs.size(); j++)
 459          check_block(block.logical_succs[j] < block.logical_succs[j + 1], "logical successors must be sorted", &block);
 460
 461       /* critical edges are not allowed */
 462       if (block.linear_preds.size() > 1) {
 463          for (unsigned pred : block.linear_preds)
 464             check_block(program->blocks[pred].linear_succs.size() == 1, "linear critical edges are not allowed", &program->blocks[pred]);
 465          for (unsigned pred : block.logical_preds)
 466             check_block(program->blocks[pred].logical_succs.size() == 1, "logical critical edges are not allowed", &program->blocks[pred]);
 467       }
 468    }
 469
 470    return is_valid;
 471 }
 472
 473 /* RA validation */
 474 namespace {
 475
 476 struct Location {
 477    Location() : block(NULL), instr(NULL) {}
 478
 479    Block *block;
 480    Instruction *instr; //NULL if it's the block's live-in
 481 };
 482
 483 struct Assignment {
 484    Location defloc;
 485    Location firstloc;
 486    PhysReg reg;
 487 };
 488
 489 bool ra_fail(Program *program, Location loc, Location loc2, const char *fmt, ...) {
 490    va_list args;
 491    va_start(args, fmt);
 492    char msg[1024];
 493    vsprintf(msg, fmt, args);
 494    va_end(args);
 495
 496    char *out;
 497    size_t outsize;
 498    FILE *memf = open_memstream(&out, &outsize);
 499
 500    fprintf(memf, "RA error found at instruction in BB%d:\n", loc.block->index);
 501    if (loc.instr) {
 502       aco_print_instr(loc.instr, memf);
 503       fprintf(memf, "\n%s", msg);
 504    } else {
 505       fprintf(memf, "%s", msg);
 506    }
 507    if (loc2.block) {
 508       fprintf(memf, " in BB%d:\n", loc2.block->index);
 509       aco_print_instr(loc2.instr, memf);
 510    }
 511    fprintf(memf, "\n\n");
 512
 513    aco_err(program, out);
 514    free(out);
 515
 516    return true;
 517 }
 518
 519 bool validate_subdword_operand(chip_class chip, const aco_ptr<Instruction>& instr, unsigned index)
 520 {
 521    Operand op = instr->operands[index];
 522    unsigned byte = op.physReg().byte();
 523
 524    if (instr->opcode == aco_opcode::p_as_uniform)
 525       return byte == 0;
 526    if (instr->format == Format::PSEUDO && chip >= GFX8)
 527       return true;
 528    if (instr->isSDWA() && (static_cast<SDWA_instruction *>(instr.get())->sel[index] & sdwa_asuint) == (sdwa_isra | op.bytes()))
 529       return true;
 530    if (byte == 2 && can_use_opsel(chip, instr->opcode, index, 1))
 531       return true;
 532
 533    switch (instr->opcode) {
 534    case aco_opcode::v_cvt_f32_ubyte1:
 535       if (byte == 1)
 536          return true;
 537       break;
 538    case aco_opcode::v_cvt_f32_ubyte2:
 539       if (byte == 2)
 540          return true;
 541       break;
 542    case aco_opcode::v_cvt_f32_ubyte3:
 543       if (byte == 3)
 544          return true;
 545       break;
 546    case aco_opcode::ds_write_b8_d16_hi:
 547    case aco_opcode::ds_write_b16_d16_hi:
 548       if (byte == 2 && index == 1)
 549          return true;
 550       break;
 551    case aco_opcode::buffer_store_byte_d16_hi:
 552    case aco_opcode::buffer_store_short_d16_hi:
 553       if (byte == 2 && index == 3)
 554          return true;
 555       break;
 556    case aco_opcode::flat_store_byte_d16_hi:
 557    case aco_opcode::flat_store_short_d16_hi:
 558    case aco_opcode::scratch_store_byte_d16_hi:
 559    case aco_opcode::scratch_store_short_d16_hi:
 560    case aco_opcode::global_store_byte_d16_hi:
 561    case aco_opcode::global_store_short_d16_hi:
 562       if (byte == 2 && index == 2)
 563          return true;
 564    default:
 565       break;
 566    }
 567
 568    return byte == 0;
 569 }
 570
 571 bool validate_subdword_definition(chip_class chip, const aco_ptr<Instruction>& instr)
 572 {
 573    Definition def = instr->definitions[0];
 574    unsigned byte = def.physReg().byte();
 575
 576    if (instr->format == Format::PSEUDO && chip >= GFX8)
 577       return true;
 578    if (instr->isSDWA() && static_cast<SDWA_instruction *>(instr.get())->dst_sel == (sdwa_isra | def.bytes()))
 579       return true;
 580    if (byte == 2 && can_use_opsel(chip, instr->opcode, -1, 1))
 581       return true;
 582
 583    switch (instr->opcode) {
 584    case aco_opcode::buffer_load_ubyte_d16_hi:
 585    case aco_opcode::buffer_load_short_d16_hi:
 586    case aco_opcode::flat_load_ubyte_d16_hi:
 587    case aco_opcode::flat_load_short_d16_hi:
 588    case aco_opcode::scratch_load_ubyte_d16_hi:
 589    case aco_opcode::scratch_load_short_d16_hi:
 590    case aco_opcode::global_load_ubyte_d16_hi:
 591    case aco_opcode::global_load_short_d16_hi:
 592    case aco_opcode::ds_read_u8_d16_hi:
 593    case aco_opcode::ds_read_u16_d16_hi:
 594       return byte == 2;
 595    default:
 596       break;
 597    }
 598
 599    return byte == 0;
 600 }
 601
 602 unsigned get_subdword_bytes_written(Program *program, const aco_ptr<Instruction>& instr, unsigned index)
 603 {
 604    chip_class chip = program->chip_class;
 605    Definition def = instr->definitions[index];
 606
 607    if (instr->format == Format::PSEUDO)
 608       return chip >= GFX8 ? def.bytes() : def.size() * 4u;
 609    if (instr->isSDWA() && static_cast<SDWA_instruction *>(instr.get())->dst_sel == (sdwa_isra | def.bytes()))
 610       return def.bytes();
 611
 612    switch (instr->opcode) {
 613    case aco_opcode::buffer_load_ubyte_d16:
 614    case aco_opcode::buffer_load_short_d16:
 615    case aco_opcode::flat_load_ubyte_d16:
 616    case aco_opcode::flat_load_short_d16:
 617    case aco_opcode::scratch_load_ubyte_d16:
 618    case aco_opcode::scratch_load_short_d16:
 619    case aco_opcode::global_load_ubyte_d16:
 620    case aco_opcode::global_load_short_d16:
 621    case aco_opcode::ds_read_u8_d16:
 622    case aco_opcode::ds_read_u16_d16:
 623    case aco_opcode::buffer_load_ubyte_d16_hi:
 624    case aco_opcode::buffer_load_short_d16_hi:
 625    case aco_opcode::flat_load_ubyte_d16_hi:
 626    case aco_opcode::flat_load_short_d16_hi:
 627    case aco_opcode::scratch_load_ubyte_d16_hi:
 628    case aco_opcode::scratch_load_short_d16_hi:
 629    case aco_opcode::global_load_ubyte_d16_hi:
 630    case aco_opcode::global_load_short_d16_hi:
 631    case aco_opcode::ds_read_u8_d16_hi:
 632    case aco_opcode::ds_read_u16_d16_hi:
 633       return program->sram_ecc_enabled ? 4 : 2;
 634    case aco_opcode::v_mad_f16:
 635    case aco_opcode::v_mad_u16:
 636    case aco_opcode::v_mad_i16:
 637    case aco_opcode::v_fma_f16:
 638    case aco_opcode::v_div_fixup_f16:
 639    case aco_opcode::v_interp_p2_f16:
 640       if (chip >= GFX9)
 641          return 2;
 642    default:
 643       break;
 644    }
 645
 646    return MAX2(chip >= GFX10 ? def.bytes() : 4, instr_info.definition_size[(int)instr->opcode] / 8u);
 647 }
 648
 649 } /* end namespace */
 650
 651 bool validate_ra(Program *program, const struct radv_nir_compiler_options *options) {
 652    if (!(debug_flags & DEBUG_VALIDATE_RA))
 653       return false;
 654
 655    bool err = false;
 656    aco::live live_vars = aco::live_var_analysis(program, options);
 657    std::vector<std::vector<Temp>> phi_sgpr_ops(program->blocks.size());
 658
 659    std::map<unsigned, Assignment> assignments;
 660    for (Block& block : program->blocks) {
 661       Location loc;
 662       loc.block = &block;
 663       for (aco_ptr<Instruction>& instr : block.instructions) {
 664          if (instr->opcode == aco_opcode::p_phi) {
 665             for (unsigned i = 0; i < instr->operands.size(); i++) {
 666                if (instr->operands[i].isTemp() &&
 667                    instr->operands[i].getTemp().type() == RegType::sgpr &&
 668                    instr->operands[i].isFirstKill())
 669                   phi_sgpr_ops[block.logical_preds[i]].emplace_back(instr->operands[i].getTemp());
 670             }
 671          }
 672
 673          loc.instr = instr.get();
 674          for (unsigned i = 0; i < instr->operands.size(); i++) {
 675             Operand& op = instr->operands[i];
 676             if (!op.isTemp())
 677                continue;
 678             if (!op.isFixed())
 679                err |= ra_fail(program, loc, Location(), "Operand %d is not assigned a register", i);
 680             if (assignments.count(op.tempId()) && assignments[op.tempId()].reg != op.physReg())
 681                err |= ra_fail(program, loc, assignments.at(op.tempId()).firstloc, "Operand %d has an inconsistent register assignment with instruction", i);
 682             if ((op.getTemp().type() == RegType::vgpr && op.physReg().reg_b + op.bytes() > (256 + program->config->num_vgprs) * 4) ||
 683                 (op.getTemp().type() == RegType::sgpr && op.physReg() + op.size() > program->config->num_sgprs && op.physReg() < program->sgpr_limit))
 684                err |= ra_fail(program, loc, assignments.at(op.tempId()).firstloc, "Operand %d has an out-of-bounds register assignment", i);
 685             if (op.physReg() == vcc && !program->needs_vcc)
 686                err |= ra_fail(program, loc, Location(), "Operand %d fixed to vcc but needs_vcc=false", i);
 687             if (op.regClass().is_subdword() && !validate_subdword_operand(program->chip_class, instr, i))
 688                err |= ra_fail(program, loc, Location(), "Operand %d not aligned correctly", i);
 689             if (!assignments[op.tempId()].firstloc.block)
 690                assignments[op.tempId()].firstloc = loc;
 691             if (!assignments[op.tempId()].defloc.block)
 692                assignments[op.tempId()].reg = op.physReg();
 693          }
 694
 695          for (unsigned i = 0; i < instr->definitions.size(); i++) {
 696             Definition& def = instr->definitions[i];
 697             if (!def.isTemp())
 698                continue;
 699             if (!def.isFixed())
 700                err |= ra_fail(program, loc, Location(), "Definition %d is not assigned a register", i);
 701             if (assignments[def.tempId()].defloc.block)
 702                err |= ra_fail(program, loc, assignments.at(def.tempId()).defloc, "Temporary %%%d also defined by instruction", def.tempId());
 703             if ((def.getTemp().type() == RegType::vgpr && def.physReg().reg_b + def.bytes() > (256 + program->config->num_vgprs) * 4) ||
 704                 (def.getTemp().type() == RegType::sgpr && def.physReg() + def.size() > program->config->num_sgprs && def.physReg() < program->sgpr_limit))
 705                err |= ra_fail(program, loc, assignments.at(def.tempId()).firstloc, "Definition %d has an out-of-bounds register assignment", i);
 706             if (def.physReg() == vcc && !program->needs_vcc)
 707                err |= ra_fail(program, loc, Location(), "Definition %d fixed to vcc but needs_vcc=false", i);
 708             if (def.regClass().is_subdword() && !validate_subdword_definition(program->chip_class, instr))
 709                err |= ra_fail(program, loc, Location(), "Definition %d not aligned correctly", i);
 710             if (!assignments[def.tempId()].firstloc.block)
 711                assignments[def.tempId()].firstloc = loc;
 712             assignments[def.tempId()].defloc = loc;
 713             assignments[def.tempId()].reg = def.physReg();
 714          }
 715       }
 716    }
 717
 718    for (Block& block : program->blocks) {
 719       Location loc;
 720       loc.block = &block;
 721
 722       std::array<unsigned, 2048> regs; /* register file in bytes */
 723       regs.fill(0);
 724
 725       std::set<Temp> live;
 726       live.insert(live_vars.live_out[block.index].begin(), live_vars.live_out[block.index].end());
 727       /* remove killed p_phi sgpr operands */
 728       for (Temp tmp : phi_sgpr_ops[block.index])
 729          live.erase(tmp);
 730
 731       /* check live out */
 732       for (Temp tmp : live) {
 733          PhysReg reg = assignments.at(tmp.id()).reg;
 734          for (unsigned i = 0; i < tmp.bytes(); i++) {
 735             if (regs[reg.reg_b + i]) {
 736                err |= ra_fail(program, loc, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i, tmp.id(), regs[reg.reg_b + i]);
 737             }
 738             regs[reg.reg_b + i] = tmp.id();
 739          }
 740       }
 741       regs.fill(0);
 742
 743       for (auto it = block.instructions.rbegin(); it != block.instructions.rend(); ++it) {
 744          aco_ptr<Instruction>& instr = *it;
 745
 746          /* check killed p_phi sgpr operands */
 747          if (instr->opcode == aco_opcode::p_logical_end) {
 748             for (Temp tmp : phi_sgpr_ops[block.index]) {
 749                PhysReg reg = assignments.at(tmp.id()).reg;
 750                for (unsigned i = 0; i < tmp.bytes(); i++) {
 751                   if (regs[reg.reg_b + i])
 752                      err |= ra_fail(program, loc, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i, tmp.id(), regs[reg.reg_b + i]);
 753                }
 754                live.emplace(tmp);
 755             }
 756          }
 757
 758          for (const Definition& def : instr->definitions) {
 759             if (!def.isTemp())
 760                continue;
 761             live.erase(def.getTemp());
 762          }
 763
 764          /* don't count phi operands as live-in, since they are actually
 765           * killed when they are copied at the predecessor */
 766          if (instr->opcode != aco_opcode::p_phi && instr->opcode != aco_opcode::p_linear_phi) {
 767             for (const Operand& op : instr->operands) {
 768                if (!op.isTemp())
 769                   continue;
 770                live.insert(op.getTemp());
 771             }
 772          }
 773       }
 774
 775       for (Temp tmp : live) {
 776          PhysReg reg = assignments.at(tmp.id()).reg;
 777          for (unsigned i = 0; i < tmp.bytes(); i++)
 778             regs[reg.reg_b + i] = tmp.id();
 779       }
 780
 781       for (aco_ptr<Instruction>& instr : block.instructions) {
 782          loc.instr = instr.get();
 783
 784          /* remove killed p_phi operands from regs */
 785          if (instr->opcode == aco_opcode::p_logical_end) {
 786             for (Temp tmp : phi_sgpr_ops[block.index]) {
 787                PhysReg reg = assignments.at(tmp.id()).reg;
 788                for (unsigned i = 0; i < tmp.bytes(); i++)
 789                   regs[reg.reg_b + i] = 0;
 790             }
 791          }
 792
 793          if (instr->opcode != aco_opcode::p_phi && instr->opcode != aco_opcode::p_linear_phi) {
 794             for (const Operand& op : instr->operands) {
 795                if (!op.isTemp())
 796                   continue;
 797                if (op.isFirstKillBeforeDef()) {
 798                   for (unsigned j = 0; j < op.getTemp().bytes(); j++)
 799                      regs[op.physReg().reg_b + j] = 0;
 800                }
 801             }
 802          }
 803
 804          for (unsigned i = 0; i < instr->definitions.size(); i++) {
 805             Definition& def = instr->definitions[i];
 806             if (!def.isTemp())
 807                continue;
 808             Temp tmp = def.getTemp();
 809             PhysReg reg = assignments.at(tmp.id()).reg;
 810             for (unsigned j = 0; j < tmp.bytes(); j++) {
 811                if (regs[reg.reg_b + j])
 812                   err |= ra_fail(program, loc, assignments.at(regs[reg.reg_b + j]).defloc, "Assignment of element %d of %%%d already taken by %%%d from instruction", i, tmp.id(), regs[reg.reg_b + j]);
 813                regs[reg.reg_b + j] = tmp.id();
 814             }
 815             if (def.regClass().is_subdword() && def.bytes() < 4) {
 816                unsigned written = get_subdword_bytes_written(program, instr, i);
 817                /* If written=4, the instruction still might write the upper half. In that case, it's the lower half that isn't preserved */
 818                for (unsigned j = reg.byte() & ~(written - 1); j < written; j++) {
 819                   unsigned written_reg = reg.reg() * 4u + j;
 820                   if (regs[written_reg] && regs[written_reg] != def.tempId())
 821                      err |= ra_fail(program, loc, assignments.at(regs[written_reg]).defloc, "Assignment of element %d of %%%d overwrites the full register taken by %%%d from instruction", i, tmp.id(), regs[written_reg]);
 822                }
 823             }
 824          }
 825
 826          for (const Definition& def : instr->definitions) {
 827             if (!def.isTemp())
 828                continue;
 829             if (def.isKill()) {
 830                for (unsigned j = 0; j < def.getTemp().bytes(); j++)
 831                   regs[def.physReg().reg_b + j] = 0;
 832             }
 833          }
 834
 835          if (instr->opcode != aco_opcode::p_phi && instr->opcode != aco_opcode::p_linear_phi) {
 836             for (const Operand& op : instr->operands) {
 837                if (!op.isTemp())
 838                   continue;
 839                if (op.isLateKill() && op.isFirstKill()) {
 840                   for (unsigned j = 0; j < op.getTemp().bytes(); j++)
 841                      regs[op.physReg().reg_b + j] = 0;
 842                }
 843             }
 844          }
 845       }
 846    }
 847
 848    return err;
 849 }
 850 }