projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: use vk_error() everywhere an error is returned
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
83 const struct radv_dynamic_state *src)
84 {
85 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
86 uint32_t copy_mask = src->mask;
87 uint32_t dest_mask = 0;
88
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
91 */
92 dest->viewport.count = src->viewport.count;
93 dest->scissor.count = src->scissor.count;
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
96 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
97 src->viewport.count * sizeof(VkViewport))) {
98 typed_memcpy(dest->viewport.viewports,
99 src->viewport.viewports,
100 src->viewport.count);
101 dest_mask |= 1 << VK_DYNAMIC_STATE_VIEWPORT;
102 }
103 }
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
106 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
107 src->scissor.count * sizeof(VkRect2D))) {
108 typed_memcpy(dest->scissor.scissors,
109 src->scissor.scissors, src->scissor.count);
110 dest_mask |= 1 << VK_DYNAMIC_STATE_SCISSOR;
111 }
112 }
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
115 if (dest->line_width != src->line_width) {
116 dest->line_width = src->line_width;
117 dest_mask |= 1 << VK_DYNAMIC_STATE_LINE_WIDTH;
118 }
119 }
120
121 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
122 if (memcmp(&dest->depth_bias, &src->depth_bias,
123 sizeof(src->depth_bias))) {
124 dest->depth_bias = src->depth_bias;
125 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BIAS;
126 }
127 }
128
129 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
130 if (memcmp(&dest->blend_constants, &src->blend_constants,
131 sizeof(src->blend_constants))) {
132 typed_memcpy(dest->blend_constants,
133 src->blend_constants, 4);
134 dest_mask |= 1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS;
135 }
136 }
137
138 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
139 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
140 sizeof(src->depth_bounds))) {
141 dest->depth_bounds = src->depth_bounds;
142 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS;
143 }
144 }
145
146 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
147 if (memcmp(&dest->stencil_compare_mask,
148 &src->stencil_compare_mask,
149 sizeof(src->stencil_compare_mask))) {
150 dest->stencil_compare_mask = src->stencil_compare_mask;
151 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK;
152 }
153 }
154
155 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
156 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
157 sizeof(src->stencil_write_mask))) {
158 dest->stencil_write_mask = src->stencil_write_mask;
159 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK;
160 }
161 }
162
163 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
164 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
165 sizeof(src->stencil_reference))) {
166 dest->stencil_reference = src->stencil_reference;
167 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE;
168 }
169 }
170
171 cmd_buffer->state.dirty |= dest_mask;
172 }
173
174 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
175 {
176 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
177 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
178 }
179
180 enum ring_type radv_queue_family_to_ring(int f) {
181 switch (f) {
182 case RADV_QUEUE_GENERAL:
183 return RING_GFX;
184 case RADV_QUEUE_COMPUTE:
185 return RING_COMPUTE;
186 case RADV_QUEUE_TRANSFER:
187 return RING_DMA;
188 default:
189 unreachable("Unknown queue family");
190 }
191 }
192
193 static VkResult radv_create_cmd_buffer(
194 struct radv_device * device,
195 struct radv_cmd_pool * pool,
196 VkCommandBufferLevel level,
197 VkCommandBuffer* pCommandBuffer)
198 {
199 struct radv_cmd_buffer *cmd_buffer;
200 unsigned ring;
201 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
203 if (cmd_buffer == NULL)
204 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
205
206 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
207 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
208 cmd_buffer->device = device;
209 cmd_buffer->pool = pool;
210 cmd_buffer->level = level;
211
212 if (pool) {
213 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
214 cmd_buffer->queue_family_index = pool->queue_family_index;
215
216 } else {
217 /* Init the pool_link so we can safefly call list_del when we destroy
218 * the command buffer
219 */
220 list_inithead(&cmd_buffer->pool_link);
221 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
222 }
223
224 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
225
226 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
227 if (!cmd_buffer->cs) {
228 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
229 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
230 }
231
232 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
233
234 cmd_buffer->upload.offset = 0;
235 cmd_buffer->upload.size = 0;
236 list_inithead(&cmd_buffer->upload.list);
237
238 return VK_SUCCESS;
239 }
240
241 static void
242 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
243 {
244 list_del(&cmd_buffer->pool_link);
245
246 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
247 &cmd_buffer->upload.list, list) {
248 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
249 list_del(&up->list);
250 free(up);
251 }
252
253 if (cmd_buffer->upload.upload_bo)
254 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
255 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
256 free(cmd_buffer->push_descriptors.set.mapped_ptr);
257 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
258 }
259
260 static VkResult
261 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
262 {
263
264 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
265
266 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
267 &cmd_buffer->upload.list, list) {
268 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
269 list_del(&up->list);
270 free(up);
271 }
272
273 cmd_buffer->push_constant_stages = 0;
274 cmd_buffer->scratch_size_needed = 0;
275 cmd_buffer->compute_scratch_size_needed = 0;
276 cmd_buffer->esgs_ring_size_needed = 0;
277 cmd_buffer->gsvs_ring_size_needed = 0;
278 cmd_buffer->tess_rings_needed = false;
279 cmd_buffer->sample_positions_needed = false;
280
281 if (cmd_buffer->upload.upload_bo)
282 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
283 cmd_buffer->upload.upload_bo, 8);
284 cmd_buffer->upload.offset = 0;
285
286 cmd_buffer->record_result = VK_SUCCESS;
287
288 cmd_buffer->ring_offsets_idx = -1;
289
290 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
291 void *fence_ptr;
292 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
293 &cmd_buffer->gfx9_fence_offset,
294 &fence_ptr);
295 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
296 }
297
298 return cmd_buffer->record_result;
299 }
300
301 static bool
302 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
303 uint64_t min_needed)
304 {
305 uint64_t new_size;
306 struct radeon_winsys_bo *bo;
307 struct radv_cmd_buffer_upload *upload;
308 struct radv_device *device = cmd_buffer->device;
309
310 new_size = MAX2(min_needed, 16 * 1024);
311 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
312
313 bo = device->ws->buffer_create(device->ws,
314 new_size, 4096,
315 RADEON_DOMAIN_GTT,
316 RADEON_FLAG_CPU_ACCESS|
317 RADEON_FLAG_NO_INTERPROCESS_SHARING);
318
319 if (!bo) {
320 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
321 return false;
322 }
323
324 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
325 if (cmd_buffer->upload.upload_bo) {
326 upload = malloc(sizeof(*upload));
327
328 if (!upload) {
329 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
330 device->ws->buffer_destroy(bo);
331 return false;
332 }
333
334 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
335 list_add(&upload->list, &cmd_buffer->upload.list);
336 }
337
338 cmd_buffer->upload.upload_bo = bo;
339 cmd_buffer->upload.size = new_size;
340 cmd_buffer->upload.offset = 0;
341 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
342
343 if (!cmd_buffer->upload.map) {
344 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
345 return false;
346 }
347
348 return true;
349 }
350
351 bool
352 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
353 unsigned size,
354 unsigned alignment,
355 unsigned *out_offset,
356 void **ptr)
357 {
358 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
359 if (offset + size > cmd_buffer->upload.size) {
360 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
361 return false;
362 offset = 0;
363 }
364
365 *out_offset = offset;
366 *ptr = cmd_buffer->upload.map + offset;
367
368 cmd_buffer->upload.offset = offset + size;
369 return true;
370 }
371
372 bool
373 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
374 unsigned size, unsigned alignment,
375 const void *data, unsigned *out_offset)
376 {
377 uint8_t *ptr;
378
379 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
380 out_offset, (void **)&ptr))
381 return false;
382
383 if (ptr)
384 memcpy(ptr, data, size);
385
386 return true;
387 }
388
389 static void
390 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
391 unsigned count, const uint32_t *data)
392 {
393 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
394 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
395 S_370_WR_CONFIRM(1) |
396 S_370_ENGINE_SEL(V_370_ME));
397 radeon_emit(cs, va);
398 radeon_emit(cs, va >> 32);
399 radeon_emit_array(cs, data, count);
400 }
401
402 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
403 {
404 struct radv_device *device = cmd_buffer->device;
405 struct radeon_winsys_cs *cs = cmd_buffer->cs;
406 uint64_t va;
407
408 if (!device->trace_bo)
409 return;
410
411 va = radv_buffer_get_va(device->trace_bo);
412 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
413 va += 4;
414
415 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
416
417 ++cmd_buffer->state.trace_id;
418 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
419 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
420 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
421 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
422 }
423
424 static void
425 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
426 {
427 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
428 enum radv_cmd_flush_bits flags;
429
430 /* Force wait for graphics/compute engines to be idle. */
431 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
432 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
433
434 si_cs_emit_cache_flush(cmd_buffer->cs, false,
435 cmd_buffer->device->physical_device->rad_info.chip_class,
436 NULL, 0,
437 radv_cmd_buffer_uses_mec(cmd_buffer),
438 flags);
439 }
440
441 radv_cmd_buffer_trace_emit(cmd_buffer);
442 }
443
444 static void
445 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
446 struct radv_pipeline *pipeline, enum ring_type ring)
447 {
448 struct radv_device *device = cmd_buffer->device;
449 struct radeon_winsys_cs *cs = cmd_buffer->cs;
450 uint32_t data[2];
451 uint64_t va;
452
453 if (!device->trace_bo)
454 return;
455
456 va = radv_buffer_get_va(device->trace_bo);
457
458 switch (ring) {
459 case RING_GFX:
460 va += 8;
461 break;
462 case RING_COMPUTE:
463 va += 16;
464 break;
465 default:
466 assert(!"invalid ring type");
467 }
468
469 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
470 cmd_buffer->cs, 6);
471
472 data[0] = (uintptr_t)pipeline;
473 data[1] = (uintptr_t)pipeline >> 32;
474
475 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
476 radv_emit_write_data_packet(cs, va, 2, data);
477 }
478
479 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
480 struct radv_descriptor_set *set,
481 unsigned idx)
482 {
483 cmd_buffer->descriptors[idx] = set;
484 if (set)
485 cmd_buffer->state.valid_descriptors |= (1u << idx);
486 else
487 cmd_buffer->state.valid_descriptors &= ~(1u << idx);
488 cmd_buffer->state.descriptors_dirty |= (1u << idx);
489
490 }
491
492 static void
493 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
494 {
495 struct radv_device *device = cmd_buffer->device;
496 struct radeon_winsys_cs *cs = cmd_buffer->cs;
497 uint32_t data[MAX_SETS * 2] = {};
498 uint64_t va;
499 unsigned i;
500 va = radv_buffer_get_va(device->trace_bo) + 24;
501
502 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
503 cmd_buffer->cs, 4 + MAX_SETS * 2);
504
505 for_each_bit(i, cmd_buffer->state.valid_descriptors) {
506 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
507 data[i * 2] = (uintptr_t)set;
508 data[i * 2 + 1] = (uintptr_t)set >> 32;
509 }
510
511 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
512 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
513 }
514
515 static void
516 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
517 struct radv_pipeline *pipeline)
518 {
519 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
520 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
521 8);
522 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
523 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
524
525 if (cmd_buffer->device->physical_device->has_rbplus) {
526
527 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
528 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
529
530 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
531 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
532 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
533 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
534 }
535 }
536
537 static void
538 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
539 struct radv_pipeline *pipeline)
540 {
541 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
542 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
543 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
544
545 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
546 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
547 }
548
549 struct ac_userdata_info *
550 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
551 gl_shader_stage stage,
552 int idx)
553 {
554 if (stage == MESA_SHADER_VERTEX) {
555 if (pipeline->shaders[MESA_SHADER_VERTEX])
556 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
557 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
558 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
559 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
560 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
561 } else if (stage == MESA_SHADER_TESS_EVAL) {
562 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
563 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
564 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
565 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
566 }
567 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
568 }
569
570 static void
571 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
572 struct radv_pipeline *pipeline,
573 gl_shader_stage stage,
574 int idx, uint64_t va)
575 {
576 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
577 uint32_t base_reg = pipeline->user_data_0[stage];
578 if (loc->sgpr_idx == -1)
579 return;
580 assert(loc->num_sgprs == 2);
581 assert(!loc->indirect);
582 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
583 radeon_emit(cmd_buffer->cs, va);
584 radeon_emit(cmd_buffer->cs, va >> 32);
585 }
586
587 static void
588 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
589 struct radv_pipeline *pipeline)
590 {
591 int num_samples = pipeline->graphics.ms.num_samples;
592 struct radv_multisample_state *ms = &pipeline->graphics.ms;
593 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
594
595 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
596 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
597 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
598
599 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
600 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
601
602 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
603 return;
604
605 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
606 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
607 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
608
609 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
610
611 /* GFX9: Flush DFSM when the AA mode changes. */
612 if (cmd_buffer->device->dfsm_allowed) {
613 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
614 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
615 }
616 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
617 uint32_t offset;
618 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
619 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
620 if (loc->sgpr_idx == -1)
621 return;
622 assert(loc->num_sgprs == 1);
623 assert(!loc->indirect);
624 switch (num_samples) {
625 default:
626 offset = 0;
627 break;
628 case 2:
629 offset = 1;
630 break;
631 case 4:
632 offset = 3;
633 break;
634 case 8:
635 offset = 7;
636 break;
637 case 16:
638 offset = 15;
639 break;
640 }
641
642 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
643 cmd_buffer->sample_positions_needed = true;
644 }
645 }
646
647 static void
648 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
649 struct radv_pipeline *pipeline)
650 {
651 struct radv_raster_state *raster = &pipeline->graphics.raster;
652
653 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
654 raster->pa_cl_clip_cntl);
655 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
656 raster->spi_interp_control);
657 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
658 raster->pa_su_vtx_cntl);
659 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
660 raster->pa_su_sc_mode_cntl);
661 }
662
663 static inline void
664 radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
665 unsigned size)
666 {
667 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
668 si_cp_dma_prefetch(cmd_buffer, va, size);
669 }
670
671 static void
672 radv_emit_VBO_descriptors_prefetch(struct radv_cmd_buffer *cmd_buffer)
673 {
674 if (cmd_buffer->state.vb_prefetch_dirty) {
675 radv_emit_prefetch_TC_L2_async(cmd_buffer,
676 cmd_buffer->state.vb_va,
677 cmd_buffer->state.vb_size);
678 cmd_buffer->state.vb_prefetch_dirty = false;
679 }
680 }
681
682 static void
683 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
684 struct radv_shader_variant *shader)
685 {
686 struct radeon_winsys *ws = cmd_buffer->device->ws;
687 struct radeon_winsys_cs *cs = cmd_buffer->cs;
688 uint64_t va;
689
690 if (!shader)
691 return;
692
693 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
694
695 radv_cs_add_buffer(ws, cs, shader->bo, 8);
696 radv_emit_prefetch_TC_L2_async(cmd_buffer, va, shader->code_size);
697 }
698
699 static void
700 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
701 struct radv_pipeline *pipeline)
702 {
703 radv_emit_shader_prefetch(cmd_buffer,
704 pipeline->shaders[MESA_SHADER_VERTEX]);
705 radv_emit_VBO_descriptors_prefetch(cmd_buffer);
706 radv_emit_shader_prefetch(cmd_buffer,
707 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
708 radv_emit_shader_prefetch(cmd_buffer,
709 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
710 radv_emit_shader_prefetch(cmd_buffer,
711 pipeline->shaders[MESA_SHADER_GEOMETRY]);
712 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
713 radv_emit_shader_prefetch(cmd_buffer,
714 pipeline->shaders[MESA_SHADER_FRAGMENT]);
715 }
716
717 static void
718 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
719 struct radv_pipeline *pipeline,
720 struct radv_shader_variant *shader)
721 {
722 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
723
724 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
725 pipeline->graphics.vs.spi_vs_out_config);
726
727 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
728 pipeline->graphics.vs.spi_shader_pos_format);
729
730 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
731 radeon_emit(cmd_buffer->cs, va >> 8);
732 radeon_emit(cmd_buffer->cs, va >> 40);
733 radeon_emit(cmd_buffer->cs, shader->rsrc1);
734 radeon_emit(cmd_buffer->cs, shader->rsrc2);
735
736 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
737 S_028818_VTX_W0_FMT(1) |
738 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
739 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
740 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
741
742
743 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
744 pipeline->graphics.vs.pa_cl_vs_out_cntl);
745
746 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
747 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
748 pipeline->graphics.vs.vgt_reuse_off);
749 }
750
751 static void
752 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
753 struct radv_pipeline *pipeline,
754 struct radv_shader_variant *shader)
755 {
756 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
757
758 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
759 radeon_emit(cmd_buffer->cs, va >> 8);
760 radeon_emit(cmd_buffer->cs, va >> 40);
761 radeon_emit(cmd_buffer->cs, shader->rsrc1);
762 radeon_emit(cmd_buffer->cs, shader->rsrc2);
763 }
764
765 static void
766 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
767 struct radv_shader_variant *shader)
768 {
769 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
770 uint32_t rsrc2 = shader->rsrc2;
771
772 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
773 radeon_emit(cmd_buffer->cs, va >> 8);
774 radeon_emit(cmd_buffer->cs, va >> 40);
775
776 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
777 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
778 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
779 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
780
781 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
782 radeon_emit(cmd_buffer->cs, shader->rsrc1);
783 radeon_emit(cmd_buffer->cs, rsrc2);
784 }
785
786 static void
787 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
788 struct radv_shader_variant *shader)
789 {
790 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
791
792 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
793 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
794 radeon_emit(cmd_buffer->cs, va >> 8);
795 radeon_emit(cmd_buffer->cs, va >> 40);
796
797 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
798 radeon_emit(cmd_buffer->cs, shader->rsrc1);
799 radeon_emit(cmd_buffer->cs, shader->rsrc2 |
800 S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
801 } else {
802 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
803 radeon_emit(cmd_buffer->cs, va >> 8);
804 radeon_emit(cmd_buffer->cs, va >> 40);
805 radeon_emit(cmd_buffer->cs, shader->rsrc1);
806 radeon_emit(cmd_buffer->cs, shader->rsrc2);
807 }
808 }
809
810 static void
811 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
812 struct radv_pipeline *pipeline)
813 {
814 struct radv_shader_variant *vs;
815
816 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
817
818 /* Skip shaders merged into HS/GS */
819 vs = pipeline->shaders[MESA_SHADER_VERTEX];
820 if (!vs)
821 return;
822
823 if (vs->info.vs.as_ls)
824 radv_emit_hw_ls(cmd_buffer, vs);
825 else if (vs->info.vs.as_es)
826 radv_emit_hw_es(cmd_buffer, pipeline, vs);
827 else
828 radv_emit_hw_vs(cmd_buffer, pipeline, vs);
829 }
830
831
832 static void
833 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
834 struct radv_pipeline *pipeline)
835 {
836 if (!radv_pipeline_has_tess(pipeline))
837 return;
838
839 struct radv_shader_variant *tes, *tcs;
840
841 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
842 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
843
844 if (tes) {
845 if (tes->info.tes.as_es)
846 radv_emit_hw_es(cmd_buffer, pipeline, tes);
847 else
848 radv_emit_hw_vs(cmd_buffer, pipeline, tes);
849 }
850
851 radv_emit_hw_hs(cmd_buffer, tcs);
852
853 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
854 pipeline->graphics.tess.tf_param);
855
856 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
857 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
858 pipeline->graphics.tess.ls_hs_config);
859 else
860 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
861 pipeline->graphics.tess.ls_hs_config);
862
863 struct ac_userdata_info *loc;
864
865 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
866 if (loc->sgpr_idx != -1) {
867 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
868 assert(loc->num_sgprs == 4);
869 assert(!loc->indirect);
870 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
871 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
872 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
873 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
874 pipeline->graphics.tess.num_tcs_input_cp << 26);
875 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
876 }
877
878 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
879 if (loc->sgpr_idx != -1) {
880 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
881 assert(loc->num_sgprs == 1);
882 assert(!loc->indirect);
883
884 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
885 pipeline->graphics.tess.offchip_layout);
886 }
887
888 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
889 if (loc->sgpr_idx != -1) {
890 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX];
891 assert(loc->num_sgprs == 1);
892 assert(!loc->indirect);
893
894 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
895 pipeline->graphics.tess.tcs_in_layout);
896 }
897 }
898
899 static void
900 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
901 struct radv_pipeline *pipeline)
902 {
903 struct radv_shader_variant *gs;
904 uint64_t va;
905
906 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
907
908 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
909 if (!gs)
910 return;
911
912 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
913
914 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
915 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
916 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
917 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
918
919 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
920
921 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
922
923 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
924 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
925 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
926 radeon_emit(cmd_buffer->cs, 0);
927 radeon_emit(cmd_buffer->cs, 0);
928 radeon_emit(cmd_buffer->cs, 0);
929
930 uint32_t gs_num_invocations = gs->info.gs.invocations;
931 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
932 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
933 S_028B90_ENABLE(gs_num_invocations > 0));
934
935 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
936 pipeline->graphics.gs.vgt_esgs_ring_itemsize);
937
938 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
939
940 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
941 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
942 radeon_emit(cmd_buffer->cs, va >> 8);
943 radeon_emit(cmd_buffer->cs, va >> 40);
944
945 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
946 radeon_emit(cmd_buffer->cs, gs->rsrc1);
947 radeon_emit(cmd_buffer->cs, gs->rsrc2 |
948 S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
949
950 radeon_set_context_reg(cmd_buffer->cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
951 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
952 } else {
953 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
954 radeon_emit(cmd_buffer->cs, va >> 8);
955 radeon_emit(cmd_buffer->cs, va >> 40);
956 radeon_emit(cmd_buffer->cs, gs->rsrc1);
957 radeon_emit(cmd_buffer->cs, gs->rsrc2);
958 }
959
960 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
961
962 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
963 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
964 if (loc->sgpr_idx != -1) {
965 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
966 uint32_t num_entries = 64;
967 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
968
969 if (is_vi)
970 num_entries *= stride;
971
972 stride = S_008F04_STRIDE(stride);
973 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
974 radeon_emit(cmd_buffer->cs, stride);
975 radeon_emit(cmd_buffer->cs, num_entries);
976 }
977 }
978
979 static void
980 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
981 struct radv_pipeline *pipeline)
982 {
983 struct radv_shader_variant *ps;
984 uint64_t va;
985 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
986 struct radv_blend_state *blend = &pipeline->graphics.blend;
987 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
988
989 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
990 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
991
992 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
993 radeon_emit(cmd_buffer->cs, va >> 8);
994 radeon_emit(cmd_buffer->cs, va >> 40);
995 radeon_emit(cmd_buffer->cs, ps->rsrc1);
996 radeon_emit(cmd_buffer->cs, ps->rsrc2);
997
998 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
999 pipeline->graphics.db_shader_control);
1000
1001 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
1002 ps->config.spi_ps_input_ena);
1003
1004 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
1005 ps->config.spi_ps_input_addr);
1006
1007 if (ps->info.info.ps.force_persample)
1008 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1009
1010 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
1011 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
1012
1013 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1014
1015 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
1016 pipeline->graphics.shader_z_format);
1017
1018 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
1019
1020 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
1021 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
1022
1023 if (cmd_buffer->device->dfsm_allowed) {
1024 /* optimise this? */
1025 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1026 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
1027 }
1028
1029 if (pipeline->graphics.ps_input_cntl_num) {
1030 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
1031 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
1032 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
1033 }
1034 }
1035 }
1036
1037 static void
1038 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
1039 struct radv_pipeline *pipeline)
1040 {
1041 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1042
1043 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
1044 return;
1045
1046 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1047 pipeline->graphics.vtx_reuse_depth);
1048 }
1049
1050 static void
1051 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1052 {
1053 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1054
1055 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1056 return;
1057
1058 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
1059 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
1060 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
1061 radv_update_multisample_state(cmd_buffer, pipeline);
1062 radv_emit_vertex_shader(cmd_buffer, pipeline);
1063 radv_emit_tess_shaders(cmd_buffer, pipeline);
1064 radv_emit_geometry_shader(cmd_buffer, pipeline);
1065 radv_emit_fragment_shader(cmd_buffer, pipeline);
1066 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
1067
1068 cmd_buffer->scratch_size_needed =
1069 MAX2(cmd_buffer->scratch_size_needed,
1070 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1071
1072 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
1073 S_0286E8_WAVES(pipeline->max_waves) |
1074 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1075
1076 if (!cmd_buffer->state.emitted_pipeline ||
1077 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1078 pipeline->graphics.can_use_guardband)
1079 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1080
1081 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1082
1083 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1084 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
1085 } else {
1086 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
1087 }
1088 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
1089
1090 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1091
1092 cmd_buffer->state.emitted_pipeline = pipeline;
1093
1094 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1095 }
1096
1097 static void
1098 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1099 {
1100 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1101 cmd_buffer->state.dynamic.viewport.viewports);
1102 }
1103
1104 static void
1105 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1106 {
1107 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1108
1109 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1110 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1111 si_emit_cache_flush(cmd_buffer);
1112 }
1113 si_write_scissors(cmd_buffer->cs, 0, count,
1114 cmd_buffer->state.dynamic.scissor.scissors,
1115 cmd_buffer->state.dynamic.viewport.viewports,
1116 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1117 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1118 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1119 }
1120
1121 static void
1122 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1123 {
1124 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1125
1126 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1127 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1128 }
1129
1130 static void
1131 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1132 {
1133 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1134
1135 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1136 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1137 }
1138
1139 static void
1140 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1141 {
1142 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1143
1144 radeon_set_context_reg_seq(cmd_buffer->cs,
1145 R_028430_DB_STENCILREFMASK, 2);
1146 radeon_emit(cmd_buffer->cs,
1147 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1148 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1149 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1150 S_028430_STENCILOPVAL(1));
1151 radeon_emit(cmd_buffer->cs,
1152 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1153 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1154 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1155 S_028434_STENCILOPVAL_BF(1));
1156 }
1157
1158 static void
1159 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1160 {
1161 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1162
1163 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1164 fui(d->depth_bounds.min));
1165 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1166 fui(d->depth_bounds.max));
1167 }
1168
1169 static void
1170 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1171 {
1172 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1173 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1174 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1175 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1176
1177 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1178 radeon_set_context_reg_seq(cmd_buffer->cs,
1179 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1180 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1181 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1182 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1183 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1184 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1185 }
1186 }
1187
1188 static void
1189 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1190 int index,
1191 struct radv_color_buffer_info *cb)
1192 {
1193 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1194
1195 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1196 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1197 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1198 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1199 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1200 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1201 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1202 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1203 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1204 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1205 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1206 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1207 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1208
1209 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1210 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1211 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1212
1213 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1214 cb->gfx9_epitch);
1215 } else {
1216 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1217 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1218 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1219 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1220 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1221 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1222 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1223 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1224 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1225 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1226 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1227 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1228
1229 if (is_vi) { /* DCC BASE */
1230 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1231 }
1232 }
1233 }
1234
1235 static void
1236 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1237 struct radv_ds_buffer_info *ds,
1238 struct radv_image *image,
1239 VkImageLayout layout)
1240 {
1241 uint32_t db_z_info = ds->db_z_info;
1242 uint32_t db_stencil_info = ds->db_stencil_info;
1243
1244 if (!radv_layout_has_htile(image, layout,
1245 radv_image_queue_family_mask(image,
1246 cmd_buffer->queue_family_index,
1247 cmd_buffer->queue_family_index))) {
1248 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1249 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1250 }
1251
1252 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1253 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1254
1255
1256 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1257 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1258 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1259 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1260 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1261
1262 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1263 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1264 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1265 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1266 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1267 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1268 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1269 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1270 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1271 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1272 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1273
1274 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1275 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1276 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1277 } else {
1278 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1279
1280 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1281 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1282 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1283 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1284 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1285 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1286 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1287 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1288 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1289 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1290
1291 }
1292
1293 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1294 ds->pa_su_poly_offset_db_fmt_cntl);
1295 }
1296
1297 void
1298 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1299 struct radv_image *image,
1300 VkClearDepthStencilValue ds_clear_value,
1301 VkImageAspectFlags aspects)
1302 {
1303 uint64_t va = radv_buffer_get_va(image->bo);
1304 va += image->offset + image->clear_value_offset;
1305 unsigned reg_offset = 0, reg_count = 0;
1306
1307 if (!image->surface.htile_size || !aspects)
1308 return;
1309
1310 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1311 ++reg_count;
1312 } else {
1313 ++reg_offset;
1314 va += 4;
1315 }
1316 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1317 ++reg_count;
1318
1319 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, image->bo, 8);
1320
1321 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1322 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1323 S_370_WR_CONFIRM(1) |
1324 S_370_ENGINE_SEL(V_370_PFP));
1325 radeon_emit(cmd_buffer->cs, va);
1326 radeon_emit(cmd_buffer->cs, va >> 32);
1327 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1328 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1329 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1330 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1331
1332 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1333 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1334 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1335 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1336 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1337 }
1338
1339 static void
1340 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1341 struct radv_image *image)
1342 {
1343 uint64_t va = radv_buffer_get_va(image->bo);
1344 va += image->offset + image->clear_value_offset;
1345
1346 if (!image->surface.htile_size)
1347 return;
1348
1349
1350 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1351 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1352 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1353 COPY_DATA_COUNT_SEL);
1354 radeon_emit(cmd_buffer->cs, va);
1355 radeon_emit(cmd_buffer->cs, va >> 32);
1356 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1357 radeon_emit(cmd_buffer->cs, 0);
1358
1359 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1360 radeon_emit(cmd_buffer->cs, 0);
1361 }
1362
1363 /*
1364 *with DCC some colors don't require CMASK elimiation before being
1365 * used as a texture. This sets a predicate value to determine if the
1366 * cmask eliminate is required.
1367 */
1368 void
1369 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1370 struct radv_image *image,
1371 bool value)
1372 {
1373 uint64_t pred_val = value;
1374 uint64_t va = radv_buffer_get_va(image->bo);
1375 va += image->offset + image->dcc_pred_offset;
1376
1377 if (!image->surface.dcc_size)
1378 return;
1379
1380 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, image->bo, 8);
1381
1382 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1383 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1384 S_370_WR_CONFIRM(1) |
1385 S_370_ENGINE_SEL(V_370_PFP));
1386 radeon_emit(cmd_buffer->cs, va);
1387 radeon_emit(cmd_buffer->cs, va >> 32);
1388 radeon_emit(cmd_buffer->cs, pred_val);
1389 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1390 }
1391
1392 void
1393 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1394 struct radv_image *image,
1395 int idx,
1396 uint32_t color_values[2])
1397 {
1398 uint64_t va = radv_buffer_get_va(image->bo);
1399 va += image->offset + image->clear_value_offset;
1400
1401 if (!image->cmask.size && !image->surface.dcc_size)
1402 return;
1403
1404 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, image->bo, 8);
1405
1406 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1407 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1408 S_370_WR_CONFIRM(1) |
1409 S_370_ENGINE_SEL(V_370_PFP));
1410 radeon_emit(cmd_buffer->cs, va);
1411 radeon_emit(cmd_buffer->cs, va >> 32);
1412 radeon_emit(cmd_buffer->cs, color_values[0]);
1413 radeon_emit(cmd_buffer->cs, color_values[1]);
1414
1415 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1416 radeon_emit(cmd_buffer->cs, color_values[0]);
1417 radeon_emit(cmd_buffer->cs, color_values[1]);
1418 }
1419
1420 static void
1421 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1422 struct radv_image *image,
1423 int idx)
1424 {
1425 uint64_t va = radv_buffer_get_va(image->bo);
1426 va += image->offset + image->clear_value_offset;
1427
1428 if (!image->cmask.size && !image->surface.dcc_size)
1429 return;
1430
1431 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1432
1433 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1434 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1435 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1436 COPY_DATA_COUNT_SEL);
1437 radeon_emit(cmd_buffer->cs, va);
1438 radeon_emit(cmd_buffer->cs, va >> 32);
1439 radeon_emit(cmd_buffer->cs, reg >> 2);
1440 radeon_emit(cmd_buffer->cs, 0);
1441
1442 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1443 radeon_emit(cmd_buffer->cs, 0);
1444 }
1445
1446 static void
1447 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1448 {
1449 int i;
1450 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1451 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1452
1453 /* this may happen for inherited secondary recording */
1454 if (!framebuffer)
1455 return;
1456
1457 for (i = 0; i < 8; ++i) {
1458 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1459 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1460 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1461 continue;
1462 }
1463
1464 int idx = subpass->color_attachments[i].attachment;
1465 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1466
1467 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1468
1469 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1470 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1471
1472 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1473 }
1474
1475 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1476 int idx = subpass->depth_stencil_attachment.attachment;
1477 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1478 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1479 struct radv_image *image = att->attachment->image;
1480 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1481 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1482 cmd_buffer->queue_family_index,
1483 cmd_buffer->queue_family_index);
1484 /* We currently don't support writing decompressed HTILE */
1485 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1486 radv_layout_is_htile_compressed(image, layout, queue_mask));
1487
1488 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1489
1490 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1491 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1492 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1493 }
1494 radv_load_depth_clear_regs(cmd_buffer, image);
1495 } else {
1496 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1497 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1498 else
1499 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1500
1501 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1502 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1503 }
1504 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1505 S_028208_BR_X(framebuffer->width) |
1506 S_028208_BR_Y(framebuffer->height));
1507
1508 if (cmd_buffer->device->dfsm_allowed) {
1509 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1510 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1511 }
1512
1513 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1514 }
1515
1516 static void
1517 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1518 {
1519 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1520
1521 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1522 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1523 2, cmd_buffer->state.index_type);
1524 } else {
1525 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1526 radeon_emit(cs, cmd_buffer->state.index_type);
1527 }
1528
1529 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1530 radeon_emit(cs, cmd_buffer->state.index_va);
1531 radeon_emit(cs, cmd_buffer->state.index_va >> 32);
1532
1533 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1534 radeon_emit(cs, cmd_buffer->state.max_index_count);
1535
1536 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1537 }
1538
1539 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1540 {
1541 uint32_t db_count_control;
1542
1543 if(!cmd_buffer->state.active_occlusion_queries) {
1544 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1545 db_count_control = 0;
1546 } else {
1547 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1548 }
1549 } else {
1550 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1551 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1552 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1553 S_028004_ZPASS_ENABLE(1) |
1554 S_028004_SLICE_EVEN_ENABLE(1) |
1555 S_028004_SLICE_ODD_ENABLE(1);
1556 } else {
1557 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1558 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1559 }
1560 }
1561
1562 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1563 }
1564
1565 static void
1566 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1567 {
1568 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1569 return;
1570
1571 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1572 radv_emit_viewport(cmd_buffer);
1573
1574 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1575 radv_emit_scissor(cmd_buffer);
1576
1577 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1578 radv_emit_line_width(cmd_buffer);
1579
1580 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1581 radv_emit_blend_constants(cmd_buffer);
1582
1583 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1584 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1585 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1586 radv_emit_stencil(cmd_buffer);
1587
1588 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1589 radv_emit_depth_bounds(cmd_buffer);
1590
1591 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1592 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1593 radv_emit_depth_biais(cmd_buffer);
1594
1595 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_ALL;
1596 }
1597
1598 static void
1599 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1600 struct radv_pipeline *pipeline,
1601 int idx,
1602 uint64_t va,
1603 gl_shader_stage stage)
1604 {
1605 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1606 uint32_t base_reg = pipeline->user_data_0[stage];
1607
1608 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1609 return;
1610
1611 assert(!desc_set_loc->indirect);
1612 assert(desc_set_loc->num_sgprs == 2);
1613 radeon_set_sh_reg_seq(cmd_buffer->cs,
1614 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1615 radeon_emit(cmd_buffer->cs, va);
1616 radeon_emit(cmd_buffer->cs, va >> 32);
1617 }
1618
1619 static void
1620 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1621 VkShaderStageFlags stages,
1622 struct radv_descriptor_set *set,
1623 unsigned idx)
1624 {
1625 if (cmd_buffer->state.pipeline) {
1626 radv_foreach_stage(stage, stages) {
1627 if (cmd_buffer->state.pipeline->shaders[stage])
1628 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1629 idx, set->va,
1630 stage);
1631 }
1632 }
1633
1634 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1635 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1636 idx, set->va,
1637 MESA_SHADER_COMPUTE);
1638 }
1639
1640 static void
1641 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1642 {
1643 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1644 unsigned bo_offset;
1645
1646 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1647 set->mapped_ptr,
1648 &bo_offset))
1649 return;
1650
1651 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1652 set->va += bo_offset;
1653 }
1654
1655 static void
1656 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1657 {
1658 uint32_t size = MAX_SETS * 2 * 4;
1659 uint32_t offset;
1660 void *ptr;
1661
1662 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1663 256, &offset, &ptr))
1664 return;
1665
1666 for (unsigned i = 0; i < MAX_SETS; i++) {
1667 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1668 uint64_t set_va = 0;
1669 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1670 if (cmd_buffer->state.valid_descriptors & (1u << i))
1671 set_va = set->va;
1672 uptr[0] = set_va & 0xffffffff;
1673 uptr[1] = set_va >> 32;
1674 }
1675
1676 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1677 va += offset;
1678
1679 if (cmd_buffer->state.pipeline) {
1680 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1681 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1682 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1683
1684 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1685 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1686 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1687
1688 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1689 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1690 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1691
1692 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1693 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1694 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1695
1696 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1697 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1698 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1699 }
1700
1701 if (cmd_buffer->state.compute_pipeline)
1702 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1703 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1704 }
1705
1706 static void
1707 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1708 VkShaderStageFlags stages)
1709 {
1710 unsigned i;
1711
1712 if (!cmd_buffer->state.descriptors_dirty)
1713 return;
1714
1715 if (cmd_buffer->state.push_descriptors_dirty)
1716 radv_flush_push_descriptors(cmd_buffer);
1717
1718 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1719 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1720 radv_flush_indirect_descriptor_sets(cmd_buffer);
1721 }
1722
1723 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1724 cmd_buffer->cs,
1725 MAX_SETS * MESA_SHADER_STAGES * 4);
1726
1727 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1728 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1729 if (!(cmd_buffer->state.valid_descriptors & (1u << i)))
1730 continue;
1731
1732 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1733 }
1734 cmd_buffer->state.descriptors_dirty = 0;
1735 cmd_buffer->state.push_descriptors_dirty = false;
1736
1737 if (cmd_buffer->device->trace_bo)
1738 radv_save_descriptors(cmd_buffer);
1739
1740 assert(cmd_buffer->cs->cdw <= cdw_max);
1741 }
1742
1743 static void
1744 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1745 struct radv_pipeline *pipeline,
1746 VkShaderStageFlags stages)
1747 {
1748 struct radv_pipeline_layout *layout = pipeline->layout;
1749 unsigned offset;
1750 void *ptr;
1751 uint64_t va;
1752
1753 stages &= cmd_buffer->push_constant_stages;
1754 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1755 return;
1756
1757 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1758 16 * layout->dynamic_offset_count,
1759 256, &offset, &ptr))
1760 return;
1761
1762 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1763 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1764 16 * layout->dynamic_offset_count);
1765
1766 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1767 va += offset;
1768
1769 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1770 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1771
1772 radv_foreach_stage(stage, stages) {
1773 if (pipeline->shaders[stage]) {
1774 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1775 AC_UD_PUSH_CONSTANTS, va);
1776 }
1777 }
1778
1779 cmd_buffer->push_constant_stages &= ~stages;
1780 assert(cmd_buffer->cs->cdw <= cdw_max);
1781 }
1782
1783 static bool
1784 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1785 {
1786 struct radv_device *device = cmd_buffer->device;
1787
1788 if ((pipeline_is_dirty || cmd_buffer->state.vb_dirty) &&
1789 cmd_buffer->state.pipeline->vertex_elements.count &&
1790 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1791 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1792 unsigned vb_offset;
1793 void *vb_ptr;
1794 uint32_t i = 0;
1795 uint32_t count = velems->count;
1796 uint64_t va;
1797
1798 /* allocate some descriptor state for vertex buffers */
1799 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1800 &vb_offset, &vb_ptr))
1801 return false;
1802
1803 for (i = 0; i < count; i++) {
1804 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1805 uint32_t offset;
1806 int vb = velems->binding[i];
1807 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1808 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1809
1810 radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer->bo, 8);
1811 va = radv_buffer_get_va(buffer->bo);
1812
1813 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1814 va += offset + buffer->offset;
1815 desc[0] = va;
1816 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1817 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1818 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1819 else
1820 desc[2] = buffer->size - offset;
1821 desc[3] = velems->rsrc_word3[i];
1822 }
1823
1824 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1825 va += vb_offset;
1826
1827 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1828 AC_UD_VS_VERTEX_BUFFERS, va);
1829
1830 cmd_buffer->state.vb_va = va;
1831 cmd_buffer->state.vb_size = count * 16;
1832 cmd_buffer->state.vb_prefetch_dirty = true;
1833 }
1834 cmd_buffer->state.vb_dirty = false;
1835
1836 return true;
1837 }
1838
1839 static bool
1840 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1841 {
1842 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1843 return false;
1844
1845 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1846 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1847 VK_SHADER_STAGE_ALL_GRAPHICS);
1848
1849 return true;
1850 }
1851
1852 static void
1853 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1854 bool instanced_draw, bool indirect_draw,
1855 uint32_t draw_vertex_count)
1856 {
1857 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1858 struct radv_cmd_state *state = &cmd_buffer->state;
1859 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1860 uint32_t ia_multi_vgt_param;
1861 int32_t primitive_reset_en;
1862
1863 /* Draw state. */
1864 ia_multi_vgt_param =
1865 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1866 indirect_draw, draw_vertex_count);
1867
1868 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1869 if (info->chip_class >= GFX9) {
1870 radeon_set_uconfig_reg_idx(cs,
1871 R_030960_IA_MULTI_VGT_PARAM,
1872 4, ia_multi_vgt_param);
1873 } else if (info->chip_class >= CIK) {
1874 radeon_set_context_reg_idx(cs,
1875 R_028AA8_IA_MULTI_VGT_PARAM,
1876 1, ia_multi_vgt_param);
1877 } else {
1878 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1879 ia_multi_vgt_param);
1880 }
1881 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1882 }
1883
1884 /* Primitive restart. */
1885 primitive_reset_en =
1886 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1887
1888 if (primitive_reset_en != state->last_primitive_reset_en) {
1889 state->last_primitive_reset_en = primitive_reset_en;
1890 if (info->chip_class >= GFX9) {
1891 radeon_set_uconfig_reg(cs,
1892 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1893 primitive_reset_en);
1894 } else {
1895 radeon_set_context_reg(cs,
1896 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1897 primitive_reset_en);
1898 }
1899 }
1900
1901 if (primitive_reset_en) {
1902 uint32_t primitive_reset_index =
1903 state->index_type ? 0xffffffffu : 0xffffu;
1904
1905 if (primitive_reset_index != state->last_primitive_reset_index) {
1906 radeon_set_context_reg(cs,
1907 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1908 primitive_reset_index);
1909 state->last_primitive_reset_index = primitive_reset_index;
1910 }
1911 }
1912 }
1913
1914 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1915 VkPipelineStageFlags src_stage_mask)
1916 {
1917 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1918 VK_PIPELINE_STAGE_TRANSFER_BIT |
1919 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1920 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1921 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1922 }
1923
1924 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1925 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1926 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1927 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1928 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1929 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1930 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1931 VK_PIPELINE_STAGE_TRANSFER_BIT |
1932 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1933 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1934 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1935 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1936 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1937 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1938 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1939 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1940 }
1941 }
1942
1943 static enum radv_cmd_flush_bits
1944 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1945 VkAccessFlags src_flags)
1946 {
1947 enum radv_cmd_flush_bits flush_bits = 0;
1948 uint32_t b;
1949 for_each_bit(b, src_flags) {
1950 switch ((VkAccessFlagBits)(1 << b)) {
1951 case VK_ACCESS_SHADER_WRITE_BIT:
1952 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1953 break;
1954 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1955 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1956 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1957 break;
1958 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1959 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1960 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1961 break;
1962 case VK_ACCESS_TRANSFER_WRITE_BIT:
1963 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1964 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1965 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1966 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1967 RADV_CMD_FLAG_INV_GLOBAL_L2;
1968 break;
1969 default:
1970 break;
1971 }
1972 }
1973 return flush_bits;
1974 }
1975
1976 static enum radv_cmd_flush_bits
1977 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1978 VkAccessFlags dst_flags,
1979 struct radv_image *image)
1980 {
1981 enum radv_cmd_flush_bits flush_bits = 0;
1982 uint32_t b;
1983 for_each_bit(b, dst_flags) {
1984 switch ((VkAccessFlagBits)(1 << b)) {
1985 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1986 case VK_ACCESS_INDEX_READ_BIT:
1987 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1988 break;
1989 case VK_ACCESS_UNIFORM_READ_BIT:
1990 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1991 break;
1992 case VK_ACCESS_SHADER_READ_BIT:
1993 case VK_ACCESS_TRANSFER_READ_BIT:
1994 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1995 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1996 RADV_CMD_FLAG_INV_GLOBAL_L2;
1997 break;
1998 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1999 /* TODO: change to image && when the image gets passed
2000 * through from the subpass. */
2001 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2002 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2003 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2004 break;
2005 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2006 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2007 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2008 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2009 break;
2010 default:
2011 break;
2012 }
2013 }
2014 return flush_bits;
2015 }
2016
2017 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2018 {
2019 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
2020 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2021 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2022 NULL);
2023 }
2024
2025 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2026 VkAttachmentReference att)
2027 {
2028 unsigned idx = att.attachment;
2029 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2030 VkImageSubresourceRange range;
2031 range.aspectMask = 0;
2032 range.baseMipLevel = view->base_mip;
2033 range.levelCount = 1;
2034 range.baseArrayLayer = view->base_layer;
2035 range.layerCount = cmd_buffer->state.framebuffer->layers;
2036
2037 radv_handle_image_transition(cmd_buffer,
2038 view->image,
2039 cmd_buffer->state.attachments[idx].current_layout,
2040 att.layout, 0, 0, &range,
2041 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2042
2043 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2044
2045
2046 }
2047
2048 void
2049 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2050 const struct radv_subpass *subpass, bool transitions)
2051 {
2052 if (transitions) {
2053 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2054
2055 for (unsigned i = 0; i < subpass->color_count; ++i) {
2056 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2057 radv_handle_subpass_image_transition(cmd_buffer,
2058 subpass->color_attachments[i]);
2059 }
2060
2061 for (unsigned i = 0; i < subpass->input_count; ++i) {
2062 radv_handle_subpass_image_transition(cmd_buffer,
2063 subpass->input_attachments[i]);
2064 }
2065
2066 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2067 radv_handle_subpass_image_transition(cmd_buffer,
2068 subpass->depth_stencil_attachment);
2069 }
2070 }
2071
2072 cmd_buffer->state.subpass = subpass;
2073
2074 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2075 }
2076
2077 static VkResult
2078 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2079 struct radv_render_pass *pass,
2080 const VkRenderPassBeginInfo *info)
2081 {
2082 struct radv_cmd_state *state = &cmd_buffer->state;
2083
2084 if (pass->attachment_count == 0) {
2085 state->attachments = NULL;
2086 return VK_SUCCESS;
2087 }
2088
2089 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2090 pass->attachment_count *
2091 sizeof(state->attachments[0]),
2092 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2093 if (state->attachments == NULL) {
2094 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2095 return cmd_buffer->record_result;
2096 }
2097
2098 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2099 struct radv_render_pass_attachment *att = &pass->attachments[i];
2100 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2101 VkImageAspectFlags clear_aspects = 0;
2102
2103 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2104 /* color attachment */
2105 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2106 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2107 }
2108 } else {
2109 /* depthstencil attachment */
2110 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2111 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2112 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2113 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2114 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2115 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2116 }
2117 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2118 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2119 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2120 }
2121 }
2122
2123 state->attachments[i].pending_clear_aspects = clear_aspects;
2124 state->attachments[i].cleared_views = 0;
2125 if (clear_aspects && info) {
2126 assert(info->clearValueCount > i);
2127 state->attachments[i].clear_value = info->pClearValues[i];
2128 }
2129
2130 state->attachments[i].current_layout = att->initial_layout;
2131 }
2132
2133 return VK_SUCCESS;
2134 }
2135
2136 VkResult radv_AllocateCommandBuffers(
2137 VkDevice _device,
2138 const VkCommandBufferAllocateInfo *pAllocateInfo,
2139 VkCommandBuffer *pCommandBuffers)
2140 {
2141 RADV_FROM_HANDLE(radv_device, device, _device);
2142 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2143
2144 VkResult result = VK_SUCCESS;
2145 uint32_t i;
2146
2147 memset(pCommandBuffers, 0,
2148 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
2149
2150 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2151
2152 if (!list_empty(&pool->free_cmd_buffers)) {
2153 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2154
2155 list_del(&cmd_buffer->pool_link);
2156 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2157
2158 result = radv_reset_cmd_buffer(cmd_buffer);
2159 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2160 cmd_buffer->level = pAllocateInfo->level;
2161
2162 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2163 } else {
2164 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2165 &pCommandBuffers[i]);
2166 }
2167 if (result != VK_SUCCESS)
2168 break;
2169 }
2170
2171 if (result != VK_SUCCESS)
2172 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2173 i, pCommandBuffers);
2174
2175 return result;
2176 }
2177
2178 void radv_FreeCommandBuffers(
2179 VkDevice device,
2180 VkCommandPool commandPool,
2181 uint32_t commandBufferCount,
2182 const VkCommandBuffer *pCommandBuffers)
2183 {
2184 for (uint32_t i = 0; i < commandBufferCount; i++) {
2185 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2186
2187 if (cmd_buffer) {
2188 if (cmd_buffer->pool) {
2189 list_del(&cmd_buffer->pool_link);
2190 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2191 } else
2192 radv_cmd_buffer_destroy(cmd_buffer);
2193
2194 }
2195 }
2196 }
2197
2198 VkResult radv_ResetCommandBuffer(
2199 VkCommandBuffer commandBuffer,
2200 VkCommandBufferResetFlags flags)
2201 {
2202 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2203 return radv_reset_cmd_buffer(cmd_buffer);
2204 }
2205
2206 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2207 {
2208 struct radv_device *device = cmd_buffer->device;
2209 if (device->gfx_init) {
2210 uint64_t va = radv_buffer_get_va(device->gfx_init);
2211 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2212 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2213 radeon_emit(cmd_buffer->cs, va);
2214 radeon_emit(cmd_buffer->cs, va >> 32);
2215 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2216 } else
2217 si_init_config(cmd_buffer);
2218 }
2219
2220 VkResult radv_BeginCommandBuffer(
2221 VkCommandBuffer commandBuffer,
2222 const VkCommandBufferBeginInfo *pBeginInfo)
2223 {
2224 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2225 VkResult result;
2226
2227 result = radv_reset_cmd_buffer(cmd_buffer);
2228 if (result != VK_SUCCESS)
2229 return result;
2230
2231 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2232 cmd_buffer->state.last_primitive_reset_en = -1;
2233 cmd_buffer->usage_flags = pBeginInfo->flags;
2234
2235 /* setup initial configuration into command buffer */
2236 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2237 switch (cmd_buffer->queue_family_index) {
2238 case RADV_QUEUE_GENERAL:
2239 emit_gfx_buffer_state(cmd_buffer);
2240 break;
2241 case RADV_QUEUE_COMPUTE:
2242 si_init_compute(cmd_buffer);
2243 break;
2244 case RADV_QUEUE_TRANSFER:
2245 default:
2246 break;
2247 }
2248 }
2249
2250 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2251 assert(pBeginInfo->pInheritanceInfo);
2252 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2253 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2254
2255 struct radv_subpass *subpass =
2256 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2257
2258 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2259 if (result != VK_SUCCESS)
2260 return result;
2261
2262 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2263 }
2264
2265 radv_cmd_buffer_trace_emit(cmd_buffer);
2266 return result;
2267 }
2268
2269 void radv_CmdBindVertexBuffers(
2270 VkCommandBuffer commandBuffer,
2271 uint32_t firstBinding,
2272 uint32_t bindingCount,
2273 const VkBuffer* pBuffers,
2274 const VkDeviceSize* pOffsets)
2275 {
2276 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2277 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2278 bool changed = false;
2279
2280 /* We have to defer setting up vertex buffer since we need the buffer
2281 * stride from the pipeline. */
2282
2283 assert(firstBinding + bindingCount <= MAX_VBS);
2284 for (uint32_t i = 0; i < bindingCount; i++) {
2285 uint32_t idx = firstBinding + i;
2286
2287 if (!changed &&
2288 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2289 vb[idx].offset != pOffsets[i])) {
2290 changed = true;
2291 }
2292
2293 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2294 vb[idx].offset = pOffsets[i];
2295 }
2296
2297 if (!changed) {
2298 /* No state changes. */
2299 return;
2300 }
2301
2302 cmd_buffer->state.vb_dirty = true;
2303 }
2304
2305 void radv_CmdBindIndexBuffer(
2306 VkCommandBuffer commandBuffer,
2307 VkBuffer buffer,
2308 VkDeviceSize offset,
2309 VkIndexType indexType)
2310 {
2311 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2312 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2313
2314 if (cmd_buffer->state.index_buffer == index_buffer &&
2315 cmd_buffer->state.index_offset == offset &&
2316 cmd_buffer->state.index_type == indexType) {
2317 /* No state changes. */
2318 return;
2319 }
2320
2321 cmd_buffer->state.index_buffer = index_buffer;
2322 cmd_buffer->state.index_offset = offset;
2323 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2324 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2325 cmd_buffer->state.index_va += index_buffer->offset + offset;
2326
2327 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2328 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2329 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2330 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2331 }
2332
2333
2334 static void
2335 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2336 struct radv_descriptor_set *set, unsigned idx)
2337 {
2338 struct radeon_winsys *ws = cmd_buffer->device->ws;
2339
2340 radv_set_descriptor_set(cmd_buffer, set, idx);
2341 if (!set)
2342 return;
2343
2344 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2345
2346 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2347 if (set->descriptors[j])
2348 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2349
2350 if(set->bo)
2351 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2352 }
2353
2354 void radv_CmdBindDescriptorSets(
2355 VkCommandBuffer commandBuffer,
2356 VkPipelineBindPoint pipelineBindPoint,
2357 VkPipelineLayout _layout,
2358 uint32_t firstSet,
2359 uint32_t descriptorSetCount,
2360 const VkDescriptorSet* pDescriptorSets,
2361 uint32_t dynamicOffsetCount,
2362 const uint32_t* pDynamicOffsets)
2363 {
2364 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2365 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2366 unsigned dyn_idx = 0;
2367
2368 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2369 unsigned idx = i + firstSet;
2370 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2371 radv_bind_descriptor_set(cmd_buffer, set, idx);
2372
2373 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2374 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2375 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2376 assert(dyn_idx < dynamicOffsetCount);
2377
2378 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2379 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2380 dst[0] = va;
2381 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2382 dst[2] = range->size;
2383 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2384 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2385 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2386 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2387 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2388 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2389 cmd_buffer->push_constant_stages |=
2390 set->layout->dynamic_shader_stages;
2391 }
2392 }
2393 }
2394
2395 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2396 struct radv_descriptor_set *set,
2397 struct radv_descriptor_set_layout *layout)
2398 {
2399 set->size = layout->size;
2400 set->layout = layout;
2401
2402 if (cmd_buffer->push_descriptors.capacity < set->size) {
2403 size_t new_size = MAX2(set->size, 1024);
2404 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2405 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2406
2407 free(set->mapped_ptr);
2408 set->mapped_ptr = malloc(new_size);
2409
2410 if (!set->mapped_ptr) {
2411 cmd_buffer->push_descriptors.capacity = 0;
2412 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2413 return false;
2414 }
2415
2416 cmd_buffer->push_descriptors.capacity = new_size;
2417 }
2418
2419 return true;
2420 }
2421
2422 void radv_meta_push_descriptor_set(
2423 struct radv_cmd_buffer* cmd_buffer,
2424 VkPipelineBindPoint pipelineBindPoint,
2425 VkPipelineLayout _layout,
2426 uint32_t set,
2427 uint32_t descriptorWriteCount,
2428 const VkWriteDescriptorSet* pDescriptorWrites)
2429 {
2430 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2431 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2432 unsigned bo_offset;
2433
2434 assert(set == 0);
2435 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2436
2437 push_set->size = layout->set[set].layout->size;
2438 push_set->layout = layout->set[set].layout;
2439
2440 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2441 &bo_offset,
2442 (void**) &push_set->mapped_ptr))
2443 return;
2444
2445 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2446 push_set->va += bo_offset;
2447
2448 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2449 radv_descriptor_set_to_handle(push_set),
2450 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2451
2452 radv_set_descriptor_set(cmd_buffer, push_set, set);
2453 }
2454
2455 void radv_CmdPushDescriptorSetKHR(
2456 VkCommandBuffer commandBuffer,
2457 VkPipelineBindPoint pipelineBindPoint,
2458 VkPipelineLayout _layout,
2459 uint32_t set,
2460 uint32_t descriptorWriteCount,
2461 const VkWriteDescriptorSet* pDescriptorWrites)
2462 {
2463 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2464 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2465 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2466
2467 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2468
2469 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2470 return;
2471
2472 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2473 radv_descriptor_set_to_handle(push_set),
2474 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2475
2476 radv_set_descriptor_set(cmd_buffer, push_set, set);
2477 cmd_buffer->state.push_descriptors_dirty = true;
2478 }
2479
2480 void radv_CmdPushDescriptorSetWithTemplateKHR(
2481 VkCommandBuffer commandBuffer,
2482 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2483 VkPipelineLayout _layout,
2484 uint32_t set,
2485 const void* pData)
2486 {
2487 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2488 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2489 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2490
2491 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2492
2493 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2494 return;
2495
2496 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2497 descriptorUpdateTemplate, pData);
2498
2499 radv_set_descriptor_set(cmd_buffer, push_set, set);
2500 cmd_buffer->state.push_descriptors_dirty = true;
2501 }
2502
2503 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2504 VkPipelineLayout layout,
2505 VkShaderStageFlags stageFlags,
2506 uint32_t offset,
2507 uint32_t size,
2508 const void* pValues)
2509 {
2510 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2511 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2512 cmd_buffer->push_constant_stages |= stageFlags;
2513 }
2514
2515 VkResult radv_EndCommandBuffer(
2516 VkCommandBuffer commandBuffer)
2517 {
2518 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2519
2520 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2521 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2522 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2523 si_emit_cache_flush(cmd_buffer);
2524 }
2525
2526 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2527
2528 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2529 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2530
2531 return cmd_buffer->record_result;
2532 }
2533
2534 static void
2535 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2536 {
2537 struct radv_shader_variant *compute_shader;
2538 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2539 uint64_t va;
2540
2541 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2542 return;
2543
2544 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2545
2546 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2547 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2548
2549 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2550 cmd_buffer->cs, 16);
2551
2552 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2553 radeon_emit(cmd_buffer->cs, va >> 8);
2554 radeon_emit(cmd_buffer->cs, va >> 40);
2555
2556 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2557 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2558 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2559
2560
2561 cmd_buffer->compute_scratch_size_needed =
2562 MAX2(cmd_buffer->compute_scratch_size_needed,
2563 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2564
2565 /* change these once we have scratch support */
2566 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2567 S_00B860_WAVES(pipeline->max_waves) |
2568 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2569
2570 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2571 radeon_emit(cmd_buffer->cs,
2572 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2573 radeon_emit(cmd_buffer->cs,
2574 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2575 radeon_emit(cmd_buffer->cs,
2576 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2577
2578 assert(cmd_buffer->cs->cdw <= cdw_max);
2579 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2580 }
2581
2582 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2583 {
2584 cmd_buffer->state.descriptors_dirty |= cmd_buffer->state.valid_descriptors;
2585 }
2586
2587 void radv_CmdBindPipeline(
2588 VkCommandBuffer commandBuffer,
2589 VkPipelineBindPoint pipelineBindPoint,
2590 VkPipeline _pipeline)
2591 {
2592 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2593 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2594
2595 switch (pipelineBindPoint) {
2596 case VK_PIPELINE_BIND_POINT_COMPUTE:
2597 if (cmd_buffer->state.compute_pipeline == pipeline)
2598 return;
2599 radv_mark_descriptor_sets_dirty(cmd_buffer);
2600
2601 cmd_buffer->state.compute_pipeline = pipeline;
2602 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2603 break;
2604 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2605 if (cmd_buffer->state.pipeline == pipeline)
2606 return;
2607 radv_mark_descriptor_sets_dirty(cmd_buffer);
2608
2609 cmd_buffer->state.pipeline = pipeline;
2610 if (!pipeline)
2611 break;
2612
2613 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2614 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2615
2616 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2617
2618 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2619 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2620 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2621 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2622
2623 if (radv_pipeline_has_tess(pipeline))
2624 cmd_buffer->tess_rings_needed = true;
2625
2626 if (radv_pipeline_has_gs(pipeline)) {
2627 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2628 AC_UD_SCRATCH_RING_OFFSETS);
2629 if (cmd_buffer->ring_offsets_idx == -1)
2630 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2631 else if (loc->sgpr_idx != -1)
2632 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2633 }
2634 break;
2635 default:
2636 assert(!"invalid bind point");
2637 break;
2638 }
2639 }
2640
2641 void radv_CmdSetViewport(
2642 VkCommandBuffer commandBuffer,
2643 uint32_t firstViewport,
2644 uint32_t viewportCount,
2645 const VkViewport* pViewports)
2646 {
2647 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2648 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2649
2650 assert(firstViewport < MAX_VIEWPORTS);
2651 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2652
2653 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2654 pViewports, viewportCount * sizeof(*pViewports));
2655
2656 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2657 }
2658
2659 void radv_CmdSetScissor(
2660 VkCommandBuffer commandBuffer,
2661 uint32_t firstScissor,
2662 uint32_t scissorCount,
2663 const VkRect2D* pScissors)
2664 {
2665 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2666 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2667
2668 assert(firstScissor < MAX_SCISSORS);
2669 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2670
2671 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2672 pScissors, scissorCount * sizeof(*pScissors));
2673 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2674 }
2675
2676 void radv_CmdSetLineWidth(
2677 VkCommandBuffer commandBuffer,
2678 float lineWidth)
2679 {
2680 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2681 cmd_buffer->state.dynamic.line_width = lineWidth;
2682 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2683 }
2684
2685 void radv_CmdSetDepthBias(
2686 VkCommandBuffer commandBuffer,
2687 float depthBiasConstantFactor,
2688 float depthBiasClamp,
2689 float depthBiasSlopeFactor)
2690 {
2691 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2692
2693 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2694 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2695 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2696
2697 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2698 }
2699
2700 void radv_CmdSetBlendConstants(
2701 VkCommandBuffer commandBuffer,
2702 const float blendConstants[4])
2703 {
2704 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2705
2706 memcpy(cmd_buffer->state.dynamic.blend_constants,
2707 blendConstants, sizeof(float) * 4);
2708
2709 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2710 }
2711
2712 void radv_CmdSetDepthBounds(
2713 VkCommandBuffer commandBuffer,
2714 float minDepthBounds,
2715 float maxDepthBounds)
2716 {
2717 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2718
2719 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2720 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2721
2722 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2723 }
2724
2725 void radv_CmdSetStencilCompareMask(
2726 VkCommandBuffer commandBuffer,
2727 VkStencilFaceFlags faceMask,
2728 uint32_t compareMask)
2729 {
2730 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2731
2732 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2733 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2734 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2735 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2736
2737 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2738 }
2739
2740 void radv_CmdSetStencilWriteMask(
2741 VkCommandBuffer commandBuffer,
2742 VkStencilFaceFlags faceMask,
2743 uint32_t writeMask)
2744 {
2745 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2746
2747 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2748 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2749 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2750 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2751
2752 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2753 }
2754
2755 void radv_CmdSetStencilReference(
2756 VkCommandBuffer commandBuffer,
2757 VkStencilFaceFlags faceMask,
2758 uint32_t reference)
2759 {
2760 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2761
2762 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2763 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2764 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2765 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2766
2767 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2768 }
2769
2770 void radv_CmdExecuteCommands(
2771 VkCommandBuffer commandBuffer,
2772 uint32_t commandBufferCount,
2773 const VkCommandBuffer* pCmdBuffers)
2774 {
2775 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2776
2777 assert(commandBufferCount > 0);
2778
2779 /* Emit pending flushes on primary prior to executing secondary */
2780 si_emit_cache_flush(primary);
2781
2782 for (uint32_t i = 0; i < commandBufferCount; i++) {
2783 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2784
2785 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2786 secondary->scratch_size_needed);
2787 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2788 secondary->compute_scratch_size_needed);
2789
2790 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2791 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2792 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2793 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2794 if (secondary->tess_rings_needed)
2795 primary->tess_rings_needed = true;
2796 if (secondary->sample_positions_needed)
2797 primary->sample_positions_needed = true;
2798
2799 if (secondary->ring_offsets_idx != -1) {
2800 if (primary->ring_offsets_idx == -1)
2801 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2802 else
2803 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2804 }
2805 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2806
2807
2808 /* When the secondary command buffer is compute only we don't
2809 * need to re-emit the current graphics pipeline.
2810 */
2811 if (secondary->state.emitted_pipeline) {
2812 primary->state.emitted_pipeline =
2813 secondary->state.emitted_pipeline;
2814 }
2815
2816 /* When the secondary command buffer is graphics only we don't
2817 * need to re-emit the current compute pipeline.
2818 */
2819 if (secondary->state.emitted_compute_pipeline) {
2820 primary->state.emitted_compute_pipeline =
2821 secondary->state.emitted_compute_pipeline;
2822 }
2823
2824 /* Only re-emit the draw packets when needed. */
2825 if (secondary->state.last_primitive_reset_en != -1) {
2826 primary->state.last_primitive_reset_en =
2827 secondary->state.last_primitive_reset_en;
2828 }
2829
2830 if (secondary->state.last_primitive_reset_index) {
2831 primary->state.last_primitive_reset_index =
2832 secondary->state.last_primitive_reset_index;
2833 }
2834
2835 if (secondary->state.last_ia_multi_vgt_param) {
2836 primary->state.last_ia_multi_vgt_param =
2837 secondary->state.last_ia_multi_vgt_param;
2838 }
2839 }
2840
2841 /* After executing commands from secondary buffers we have to dirty
2842 * some states.
2843 */
2844 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2845 RADV_CMD_DIRTY_INDEX_BUFFER |
2846 RADV_CMD_DIRTY_DYNAMIC_ALL;
2847 radv_mark_descriptor_sets_dirty(primary);
2848 }
2849
2850 VkResult radv_CreateCommandPool(
2851 VkDevice _device,
2852 const VkCommandPoolCreateInfo* pCreateInfo,
2853 const VkAllocationCallbacks* pAllocator,
2854 VkCommandPool* pCmdPool)
2855 {
2856 RADV_FROM_HANDLE(radv_device, device, _device);
2857 struct radv_cmd_pool *pool;
2858
2859 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2860 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2861 if (pool == NULL)
2862 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2863
2864 if (pAllocator)
2865 pool->alloc = *pAllocator;
2866 else
2867 pool->alloc = device->alloc;
2868
2869 list_inithead(&pool->cmd_buffers);
2870 list_inithead(&pool->free_cmd_buffers);
2871
2872 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2873
2874 *pCmdPool = radv_cmd_pool_to_handle(pool);
2875
2876 return VK_SUCCESS;
2877
2878 }
2879
2880 void radv_DestroyCommandPool(
2881 VkDevice _device,
2882 VkCommandPool commandPool,
2883 const VkAllocationCallbacks* pAllocator)
2884 {
2885 RADV_FROM_HANDLE(radv_device, device, _device);
2886 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2887
2888 if (!pool)
2889 return;
2890
2891 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2892 &pool->cmd_buffers, pool_link) {
2893 radv_cmd_buffer_destroy(cmd_buffer);
2894 }
2895
2896 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2897 &pool->free_cmd_buffers, pool_link) {
2898 radv_cmd_buffer_destroy(cmd_buffer);
2899 }
2900
2901 vk_free2(&device->alloc, pAllocator, pool);
2902 }
2903
2904 VkResult radv_ResetCommandPool(
2905 VkDevice device,
2906 VkCommandPool commandPool,
2907 VkCommandPoolResetFlags flags)
2908 {
2909 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2910 VkResult result;
2911
2912 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2913 &pool->cmd_buffers, pool_link) {
2914 result = radv_reset_cmd_buffer(cmd_buffer);
2915 if (result != VK_SUCCESS)
2916 return result;
2917 }
2918
2919 return VK_SUCCESS;
2920 }
2921
2922 void radv_TrimCommandPoolKHR(
2923 VkDevice device,
2924 VkCommandPool commandPool,
2925 VkCommandPoolTrimFlagsKHR flags)
2926 {
2927 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2928
2929 if (!pool)
2930 return;
2931
2932 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2933 &pool->free_cmd_buffers, pool_link) {
2934 radv_cmd_buffer_destroy(cmd_buffer);
2935 }
2936 }
2937
2938 void radv_CmdBeginRenderPass(
2939 VkCommandBuffer commandBuffer,
2940 const VkRenderPassBeginInfo* pRenderPassBegin,
2941 VkSubpassContents contents)
2942 {
2943 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2944 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2945 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2946
2947 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2948 cmd_buffer->cs, 2048);
2949 MAYBE_UNUSED VkResult result;
2950
2951 cmd_buffer->state.framebuffer = framebuffer;
2952 cmd_buffer->state.pass = pass;
2953 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2954
2955 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2956 if (result != VK_SUCCESS)
2957 return;
2958
2959 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2960 assert(cmd_buffer->cs->cdw <= cdw_max);
2961
2962 radv_cmd_buffer_clear_subpass(cmd_buffer);
2963 }
2964
2965 void radv_CmdNextSubpass(
2966 VkCommandBuffer commandBuffer,
2967 VkSubpassContents contents)
2968 {
2969 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2970
2971 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2972
2973 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2974 2048);
2975
2976 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2977 radv_cmd_buffer_clear_subpass(cmd_buffer);
2978 }
2979
2980 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2981 {
2982 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2983 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2984 if (!pipeline->shaders[stage])
2985 continue;
2986 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2987 if (loc->sgpr_idx == -1)
2988 continue;
2989 uint32_t base_reg = pipeline->user_data_0[stage];
2990 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2991
2992 }
2993 if (pipeline->gs_copy_shader) {
2994 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2995 if (loc->sgpr_idx != -1) {
2996 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2997 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2998 }
2999 }
3000 }
3001
3002 static void
3003 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3004 uint32_t vertex_count)
3005 {
3006 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3007 radeon_emit(cmd_buffer->cs, vertex_count);
3008 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3009 S_0287F0_USE_OPAQUE(0));
3010 }
3011
3012 static void
3013 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3014 uint64_t index_va,
3015 uint32_t index_count)
3016 {
3017 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3018 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3019 radeon_emit(cmd_buffer->cs, index_va);
3020 radeon_emit(cmd_buffer->cs, index_va >> 32);
3021 radeon_emit(cmd_buffer->cs, index_count);
3022 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3023 }
3024
3025 static void
3026 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3027 bool indexed,
3028 uint32_t draw_count,
3029 uint64_t count_va,
3030 uint32_t stride)
3031 {
3032 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3033 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3034 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3035 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
3036 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3037 assert(base_reg);
3038
3039 if (draw_count == 1 && !count_va && !draw_id_enable) {
3040 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3041 PKT3_DRAW_INDIRECT, 3, false));
3042 radeon_emit(cs, 0);
3043 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3044 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3045 radeon_emit(cs, di_src_sel);
3046 } else {
3047 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3048 PKT3_DRAW_INDIRECT_MULTI,
3049 8, false));
3050 radeon_emit(cs, 0);
3051 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3052 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3053 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3054 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3055 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3056 radeon_emit(cs, draw_count); /* count */
3057 radeon_emit(cs, count_va); /* count_addr */
3058 radeon_emit(cs, count_va >> 32);
3059 radeon_emit(cs, stride); /* stride */
3060 radeon_emit(cs, di_src_sel);
3061 }
3062 }
3063
3064 struct radv_draw_info {
3065 /**
3066 * Number of vertices.
3067 */
3068 uint32_t count;
3069
3070 /**
3071 * Index of the first vertex.
3072 */
3073 int32_t vertex_offset;
3074
3075 /**
3076 * First instance id.
3077 */
3078 uint32_t first_instance;
3079
3080 /**
3081 * Number of instances.
3082 */
3083 uint32_t instance_count;
3084
3085 /**
3086 * First index (indexed draws only).
3087 */
3088 uint32_t first_index;
3089
3090 /**
3091 * Whether it's an indexed draw.
3092 */
3093 bool indexed;
3094
3095 /**
3096 * Indirect draw parameters resource.
3097 */
3098 struct radv_buffer *indirect;
3099 uint64_t indirect_offset;
3100 uint32_t stride;
3101
3102 /**
3103 * Draw count parameters resource.
3104 */
3105 struct radv_buffer *count_buffer;
3106 uint64_t count_buffer_offset;
3107 };
3108
3109 static void
3110 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3111 const struct radv_draw_info *info)
3112 {
3113 struct radv_cmd_state *state = &cmd_buffer->state;
3114 struct radeon_winsys *ws = cmd_buffer->device->ws;
3115 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3116
3117 if (info->indirect) {
3118 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3119 uint64_t count_va = 0;
3120
3121 va += info->indirect->offset + info->indirect_offset;
3122
3123 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3124
3125 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3126 radeon_emit(cs, 1);
3127 radeon_emit(cs, va);
3128 radeon_emit(cs, va >> 32);
3129
3130 if (info->count_buffer) {
3131 count_va = radv_buffer_get_va(info->count_buffer->bo);
3132 count_va += info->count_buffer->offset +
3133 info->count_buffer_offset;
3134
3135 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3136 }
3137
3138 if (!state->subpass->view_mask) {
3139 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3140 info->indexed,
3141 info->count,
3142 count_va,
3143 info->stride);
3144 } else {
3145 unsigned i;
3146 for_each_bit(i, state->subpass->view_mask) {
3147 radv_emit_view_index(cmd_buffer, i);
3148
3149 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3150 info->indexed,
3151 info->count,
3152 count_va,
3153 info->stride);
3154 }
3155 }
3156 } else {
3157 assert(state->pipeline->graphics.vtx_base_sgpr);
3158 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3159 state->pipeline->graphics.vtx_emit_num);
3160 radeon_emit(cs, info->vertex_offset);
3161 radeon_emit(cs, info->first_instance);
3162 if (state->pipeline->graphics.vtx_emit_num == 3)
3163 radeon_emit(cs, 0);
3164
3165 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
3166 radeon_emit(cs, info->instance_count);
3167
3168 if (info->indexed) {
3169 int index_size = state->index_type ? 4 : 2;
3170 uint64_t index_va;
3171
3172 index_va = state->index_va;
3173 index_va += info->first_index * index_size;
3174
3175 if (!state->subpass->view_mask) {
3176 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3177 index_va,
3178 info->count);
3179 } else {
3180 unsigned i;
3181 for_each_bit(i, state->subpass->view_mask) {
3182 radv_emit_view_index(cmd_buffer, i);
3183
3184 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3185 index_va,
3186 info->count);
3187 }
3188 }
3189 } else {
3190 if (!state->subpass->view_mask) {
3191 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3192 } else {
3193 unsigned i;
3194 for_each_bit(i, state->subpass->view_mask) {
3195 radv_emit_view_index(cmd_buffer, i);
3196
3197 radv_cs_emit_draw_packet(cmd_buffer,
3198 info->count);
3199 }
3200 }
3201 }
3202 }
3203 }
3204
3205 static void
3206 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3207 const struct radv_draw_info *info)
3208 {
3209 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3210 radv_emit_graphics_pipeline(cmd_buffer);
3211
3212 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3213 radv_emit_framebuffer_state(cmd_buffer);
3214
3215 if (info->indexed) {
3216 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3217 radv_emit_index_buffer(cmd_buffer);
3218 } else {
3219 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3220 * so the state must be re-emitted before the next indexed
3221 * draw.
3222 */
3223 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
3224 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3225 }
3226
3227 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3228
3229 radv_emit_draw_registers(cmd_buffer, info->indexed,
3230 info->instance_count > 1, info->indirect,
3231 info->indirect ? 0 : info->count);
3232 }
3233
3234 static void
3235 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3236 const struct radv_draw_info *info)
3237 {
3238 bool pipeline_is_dirty =
3239 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3240 cmd_buffer->state.pipeline &&
3241 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3242
3243 MAYBE_UNUSED unsigned cdw_max =
3244 radeon_check_space(cmd_buffer->device->ws,
3245 cmd_buffer->cs, 4096);
3246
3247 /* Use optimal packet order based on whether we need to sync the
3248 * pipeline.
3249 */
3250 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3251 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3252 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3253 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3254 /* If we have to wait for idle, set all states first, so that
3255 * all SET packets are processed in parallel with previous draw
3256 * calls. Then upload descriptors, set shader pointers, and
3257 * draw, and prefetch at the end. This ensures that the time
3258 * the CUs are idle is very short. (there are only SET_SH
3259 * packets between the wait and the draw)
3260 */
3261 radv_emit_all_graphics_states(cmd_buffer, info);
3262 si_emit_cache_flush(cmd_buffer);
3263 /* <-- CUs are idle here --> */
3264
3265 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3266 return;
3267
3268 radv_emit_draw_packets(cmd_buffer, info);
3269 /* <-- CUs are busy here --> */
3270
3271 /* Start prefetches after the draw has been started. Both will
3272 * run in parallel, but starting the draw first is more
3273 * important.
3274 */
3275 if (pipeline_is_dirty) {
3276 radv_emit_prefetch(cmd_buffer,
3277 cmd_buffer->state.pipeline);
3278 }
3279 } else {
3280 /* If we don't wait for idle, start prefetches first, then set
3281 * states, and draw at the end.
3282 */
3283 si_emit_cache_flush(cmd_buffer);
3284
3285 if (pipeline_is_dirty) {
3286 radv_emit_prefetch(cmd_buffer,
3287 cmd_buffer->state.pipeline);
3288 }
3289
3290 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3291 return;
3292
3293 radv_emit_all_graphics_states(cmd_buffer, info);
3294 radv_emit_draw_packets(cmd_buffer, info);
3295 }
3296
3297 assert(cmd_buffer->cs->cdw <= cdw_max);
3298 radv_cmd_buffer_after_draw(cmd_buffer);
3299 }
3300
3301 void radv_CmdDraw(
3302 VkCommandBuffer commandBuffer,
3303 uint32_t vertexCount,
3304 uint32_t instanceCount,
3305 uint32_t firstVertex,
3306 uint32_t firstInstance)
3307 {
3308 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3309 struct radv_draw_info info = {};
3310
3311 info.count = vertexCount;
3312 info.instance_count = instanceCount;
3313 info.first_instance = firstInstance;
3314 info.vertex_offset = firstVertex;
3315
3316 radv_draw(cmd_buffer, &info);
3317 }
3318
3319 void radv_CmdDrawIndexed(
3320 VkCommandBuffer commandBuffer,
3321 uint32_t indexCount,
3322 uint32_t instanceCount,
3323 uint32_t firstIndex,
3324 int32_t vertexOffset,
3325 uint32_t firstInstance)
3326 {
3327 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3328 struct radv_draw_info info = {};
3329
3330 info.indexed = true;
3331 info.count = indexCount;
3332 info.instance_count = instanceCount;
3333 info.first_index = firstIndex;
3334 info.vertex_offset = vertexOffset;
3335 info.first_instance = firstInstance;
3336
3337 radv_draw(cmd_buffer, &info);
3338 }
3339
3340 void radv_CmdDrawIndirect(
3341 VkCommandBuffer commandBuffer,
3342 VkBuffer _buffer,
3343 VkDeviceSize offset,
3344 uint32_t drawCount,
3345 uint32_t stride)
3346 {
3347 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3348 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3349 struct radv_draw_info info = {};
3350
3351 info.count = drawCount;
3352 info.indirect = buffer;
3353 info.indirect_offset = offset;
3354 info.stride = stride;
3355
3356 radv_draw(cmd_buffer, &info);
3357 }
3358
3359 void radv_CmdDrawIndexedIndirect(
3360 VkCommandBuffer commandBuffer,
3361 VkBuffer _buffer,
3362 VkDeviceSize offset,
3363 uint32_t drawCount,
3364 uint32_t stride)
3365 {
3366 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3367 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3368 struct radv_draw_info info = {};
3369
3370 info.indexed = true;
3371 info.count = drawCount;
3372 info.indirect = buffer;
3373 info.indirect_offset = offset;
3374 info.stride = stride;
3375
3376 radv_draw(cmd_buffer, &info);
3377 }
3378
3379 void radv_CmdDrawIndirectCountAMD(
3380 VkCommandBuffer commandBuffer,
3381 VkBuffer _buffer,
3382 VkDeviceSize offset,
3383 VkBuffer _countBuffer,
3384 VkDeviceSize countBufferOffset,
3385 uint32_t maxDrawCount,
3386 uint32_t stride)
3387 {
3388 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3389 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3390 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3391 struct radv_draw_info info = {};
3392
3393 info.count = maxDrawCount;
3394 info.indirect = buffer;
3395 info.indirect_offset = offset;
3396 info.count_buffer = count_buffer;
3397 info.count_buffer_offset = countBufferOffset;
3398 info.stride = stride;
3399
3400 radv_draw(cmd_buffer, &info);
3401 }
3402
3403 void radv_CmdDrawIndexedIndirectCountAMD(
3404 VkCommandBuffer commandBuffer,
3405 VkBuffer _buffer,
3406 VkDeviceSize offset,
3407 VkBuffer _countBuffer,
3408 VkDeviceSize countBufferOffset,
3409 uint32_t maxDrawCount,
3410 uint32_t stride)
3411 {
3412 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3413 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3414 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3415 struct radv_draw_info info = {};
3416
3417 info.indexed = true;
3418 info.count = maxDrawCount;
3419 info.indirect = buffer;
3420 info.indirect_offset = offset;
3421 info.count_buffer = count_buffer;
3422 info.count_buffer_offset = countBufferOffset;
3423 info.stride = stride;
3424
3425 radv_draw(cmd_buffer, &info);
3426 }
3427
3428 struct radv_dispatch_info {
3429 /**
3430 * Determine the layout of the grid (in block units) to be used.
3431 */
3432 uint32_t blocks[3];
3433
3434 /**
3435 * Whether it's an unaligned compute dispatch.
3436 */
3437 bool unaligned;
3438
3439 /**
3440 * Indirect compute parameters resource.
3441 */
3442 struct radv_buffer *indirect;
3443 uint64_t indirect_offset;
3444 };
3445
3446 static void
3447 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3448 const struct radv_dispatch_info *info)
3449 {
3450 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3451 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3452 struct radeon_winsys *ws = cmd_buffer->device->ws;
3453 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3454 struct ac_userdata_info *loc;
3455 unsigned dispatch_initiator;
3456 uint8_t grid_used;
3457
3458 grid_used = compute_shader->info.info.cs.grid_components_used;
3459
3460 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3461 AC_UD_CS_GRID_SIZE);
3462
3463 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3464
3465 dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
3466 S_00B800_FORCE_START_AT_000(1);
3467
3468 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3469 /* If the KMD allows it (there is a KMD hw register for it),
3470 * allow launching waves out-of-order.
3471 */
3472 dispatch_initiator |= S_00B800_ORDER_MODE(1);
3473 }
3474
3475 if (info->indirect) {
3476 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3477
3478 va += info->indirect->offset + info->indirect_offset;
3479
3480 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3481
3482 if (loc->sgpr_idx != -1) {
3483 for (unsigned i = 0; i < grid_used; ++i) {
3484 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3485 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3486 COPY_DATA_DST_SEL(COPY_DATA_REG));
3487 radeon_emit(cs, (va + 4 * i));
3488 radeon_emit(cs, (va + 4 * i) >> 32);
3489 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3490 + loc->sgpr_idx * 4) >> 2) + i);
3491 radeon_emit(cs, 0);
3492 }
3493 }
3494
3495 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3496 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3497 PKT3_SHADER_TYPE_S(1));
3498 radeon_emit(cs, va);
3499 radeon_emit(cs, va >> 32);
3500 radeon_emit(cs, dispatch_initiator);
3501 } else {
3502 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3503 PKT3_SHADER_TYPE_S(1));
3504 radeon_emit(cs, 1);
3505 radeon_emit(cs, va);
3506 radeon_emit(cs, va >> 32);
3507
3508 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3509 PKT3_SHADER_TYPE_S(1));
3510 radeon_emit(cs, 0);
3511 radeon_emit(cs, dispatch_initiator);
3512 }
3513 } else {
3514 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3515
3516 if (info->unaligned) {
3517 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3518 unsigned remainder[3];
3519
3520 /* If aligned, these should be an entire block size,
3521 * not 0.
3522 */
3523 remainder[0] = blocks[0] + cs_block_size[0] -
3524 align_u32_npot(blocks[0], cs_block_size[0]);
3525 remainder[1] = blocks[1] + cs_block_size[1] -
3526 align_u32_npot(blocks[1], cs_block_size[1]);
3527 remainder[2] = blocks[2] + cs_block_size[2] -
3528 align_u32_npot(blocks[2], cs_block_size[2]);
3529
3530 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3531 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3532 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3533
3534 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3535 radeon_emit(cs,
3536 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3537 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3538 radeon_emit(cs,
3539 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3540 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3541 radeon_emit(cs,
3542 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3543 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3544
3545 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3546 }
3547
3548 if (loc->sgpr_idx != -1) {
3549 assert(!loc->indirect);
3550 assert(loc->num_sgprs == grid_used);
3551
3552 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3553 loc->sgpr_idx * 4, grid_used);
3554 radeon_emit(cs, blocks[0]);
3555 if (grid_used > 1)
3556 radeon_emit(cs, blocks[1]);
3557 if (grid_used > 2)
3558 radeon_emit(cs, blocks[2]);
3559 }
3560
3561 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3562 PKT3_SHADER_TYPE_S(1));
3563 radeon_emit(cs, blocks[0]);
3564 radeon_emit(cs, blocks[1]);
3565 radeon_emit(cs, blocks[2]);
3566 radeon_emit(cs, dispatch_initiator);
3567 }
3568
3569 assert(cmd_buffer->cs->cdw <= cdw_max);
3570 }
3571
3572 static void
3573 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3574 {
3575 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3576 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3577 VK_SHADER_STAGE_COMPUTE_BIT);
3578 }
3579
3580 static void
3581 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3582 const struct radv_dispatch_info *info)
3583 {
3584 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3585 bool pipeline_is_dirty = pipeline &&
3586 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3587
3588 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3589 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3590 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3591 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3592 /* If we have to wait for idle, set all states first, so that
3593 * all SET packets are processed in parallel with previous draw
3594 * calls. Then upload descriptors, set shader pointers, and
3595 * dispatch, and prefetch at the end. This ensures that the
3596 * time the CUs are idle is very short. (there are only SET_SH
3597 * packets between the wait and the draw)
3598 */
3599 radv_emit_compute_pipeline(cmd_buffer);
3600 si_emit_cache_flush(cmd_buffer);
3601 /* <-- CUs are idle here --> */
3602
3603 radv_upload_compute_shader_descriptors(cmd_buffer);
3604
3605 radv_emit_dispatch_packets(cmd_buffer, info);
3606 /* <-- CUs are busy here --> */
3607
3608 /* Start prefetches after the dispatch has been started. Both
3609 * will run in parallel, but starting the dispatch first is
3610 * more important.
3611 */
3612 if (pipeline_is_dirty) {
3613 radv_emit_shader_prefetch(cmd_buffer,
3614 pipeline->shaders[MESA_SHADER_COMPUTE]);
3615 }
3616 } else {
3617 /* If we don't wait for idle, start prefetches first, then set
3618 * states, and dispatch at the end.
3619 */
3620 si_emit_cache_flush(cmd_buffer);
3621
3622 if (pipeline_is_dirty) {
3623 radv_emit_shader_prefetch(cmd_buffer,
3624 pipeline->shaders[MESA_SHADER_COMPUTE]);
3625 }
3626
3627 radv_upload_compute_shader_descriptors(cmd_buffer);
3628
3629 radv_emit_compute_pipeline(cmd_buffer);
3630 radv_emit_dispatch_packets(cmd_buffer, info);
3631 }
3632
3633 radv_cmd_buffer_after_draw(cmd_buffer);
3634 }
3635
3636 void radv_CmdDispatch(
3637 VkCommandBuffer commandBuffer,
3638 uint32_t x,
3639 uint32_t y,
3640 uint32_t z)
3641 {
3642 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3643 struct radv_dispatch_info info = {};
3644
3645 info.blocks[0] = x;
3646 info.blocks[1] = y;
3647 info.blocks[2] = z;
3648
3649 radv_dispatch(cmd_buffer, &info);
3650 }
3651
3652 void radv_CmdDispatchIndirect(
3653 VkCommandBuffer commandBuffer,
3654 VkBuffer _buffer,
3655 VkDeviceSize offset)
3656 {
3657 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3658 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3659 struct radv_dispatch_info info = {};
3660
3661 info.indirect = buffer;
3662 info.indirect_offset = offset;
3663
3664 radv_dispatch(cmd_buffer, &info);
3665 }
3666
3667 void radv_unaligned_dispatch(
3668 struct radv_cmd_buffer *cmd_buffer,
3669 uint32_t x,
3670 uint32_t y,
3671 uint32_t z)
3672 {
3673 struct radv_dispatch_info info = {};
3674
3675 info.blocks[0] = x;
3676 info.blocks[1] = y;
3677 info.blocks[2] = z;
3678 info.unaligned = 1;
3679
3680 radv_dispatch(cmd_buffer, &info);
3681 }
3682
3683 void radv_CmdEndRenderPass(
3684 VkCommandBuffer commandBuffer)
3685 {
3686 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3687
3688 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3689
3690 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3691
3692 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3693 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3694 radv_handle_subpass_image_transition(cmd_buffer,
3695 (VkAttachmentReference){i, layout});
3696 }
3697
3698 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3699
3700 cmd_buffer->state.pass = NULL;
3701 cmd_buffer->state.subpass = NULL;
3702 cmd_buffer->state.attachments = NULL;
3703 cmd_buffer->state.framebuffer = NULL;
3704 }
3705
3706 /*
3707 * For HTILE we have the following interesting clear words:
3708 * 0x0000030f: Uncompressed.
3709 * 0xfffffff0: Clear depth to 1.0
3710 * 0x00000000: Clear depth to 0.0
3711 */
3712 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3713 struct radv_image *image,
3714 const VkImageSubresourceRange *range,
3715 uint32_t clear_word)
3716 {
3717 assert(range->baseMipLevel == 0);
3718 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3719 unsigned layer_count = radv_get_layerCount(image, range);
3720 uint64_t size = image->surface.htile_slice_size * layer_count;
3721 uint64_t offset = image->offset + image->htile_offset +
3722 image->surface.htile_slice_size * range->baseArrayLayer;
3723 struct radv_cmd_state *state = &cmd_buffer->state;
3724
3725 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3726 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3727
3728 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3729 size, clear_word);
3730
3731 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3732 }
3733
3734 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3735 struct radv_image *image,
3736 VkImageLayout src_layout,
3737 VkImageLayout dst_layout,
3738 unsigned src_queue_mask,
3739 unsigned dst_queue_mask,
3740 const VkImageSubresourceRange *range,
3741 VkImageAspectFlags pending_clears)
3742 {
3743 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3744 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3745 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3746 cmd_buffer->state.render_area.extent.width == image->info.width &&
3747 cmd_buffer->state.render_area.extent.height == image->info.height) {
3748 /* The clear will initialize htile. */
3749 return;
3750 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3751 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3752 /* TODO: merge with the clear if applicable */
3753 radv_initialize_htile(cmd_buffer, image, range, 0);
3754 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3755 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3756 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3757 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3758 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3759 VkImageSubresourceRange local_range = *range;
3760 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3761 local_range.baseMipLevel = 0;
3762 local_range.levelCount = 1;
3763
3764 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3765 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3766
3767 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3768
3769 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3770 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3771 }
3772 }
3773
3774 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3775 struct radv_image *image, uint32_t value)
3776 {
3777 struct radv_cmd_state *state = &cmd_buffer->state;
3778
3779 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3780 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3781
3782 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3783 image->offset + image->cmask.offset,
3784 image->cmask.size, value);
3785
3786 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3787 }
3788
3789 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3790 struct radv_image *image,
3791 VkImageLayout src_layout,
3792 VkImageLayout dst_layout,
3793 unsigned src_queue_mask,
3794 unsigned dst_queue_mask,
3795 const VkImageSubresourceRange *range)
3796 {
3797 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3798 if (image->fmask.size)
3799 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3800 else
3801 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3802 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3803 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3804 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3805 }
3806 }
3807
3808 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3809 struct radv_image *image, uint32_t value)
3810 {
3811 struct radv_cmd_state *state = &cmd_buffer->state;
3812
3813 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3814 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3815
3816 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3817 image->offset + image->dcc_offset,
3818 image->surface.dcc_size, value);
3819
3820 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3821 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3822 }
3823
3824 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3825 struct radv_image *image,
3826 VkImageLayout src_layout,
3827 VkImageLayout dst_layout,
3828 unsigned src_queue_mask,
3829 unsigned dst_queue_mask,
3830 const VkImageSubresourceRange *range)
3831 {
3832 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3833 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3834 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3835 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3836 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3837 }
3838 }
3839
3840 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3841 struct radv_image *image,
3842 VkImageLayout src_layout,
3843 VkImageLayout dst_layout,
3844 uint32_t src_family,
3845 uint32_t dst_family,
3846 const VkImageSubresourceRange *range,
3847 VkImageAspectFlags pending_clears)
3848 {
3849 if (image->exclusive && src_family != dst_family) {
3850 /* This is an acquire or a release operation and there will be
3851 * a corresponding release/acquire. Do the transition in the
3852 * most flexible queue. */
3853
3854 assert(src_family == cmd_buffer->queue_family_index ||
3855 dst_family == cmd_buffer->queue_family_index);
3856
3857 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3858 return;
3859
3860 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3861 (src_family == RADV_QUEUE_GENERAL ||
3862 dst_family == RADV_QUEUE_GENERAL))
3863 return;
3864 }
3865
3866 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3867 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3868
3869 if (image->surface.htile_size)
3870 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3871 dst_layout, src_queue_mask,
3872 dst_queue_mask, range,
3873 pending_clears);
3874
3875 if (image->cmask.size || image->fmask.size)
3876 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3877 dst_layout, src_queue_mask,
3878 dst_queue_mask, range);
3879
3880 if (image->surface.dcc_size)
3881 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3882 dst_layout, src_queue_mask,
3883 dst_queue_mask, range);
3884 }
3885
3886 void radv_CmdPipelineBarrier(
3887 VkCommandBuffer commandBuffer,
3888 VkPipelineStageFlags srcStageMask,
3889 VkPipelineStageFlags destStageMask,
3890 VkBool32 byRegion,
3891 uint32_t memoryBarrierCount,
3892 const VkMemoryBarrier* pMemoryBarriers,
3893 uint32_t bufferMemoryBarrierCount,
3894 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3895 uint32_t imageMemoryBarrierCount,
3896 const VkImageMemoryBarrier* pImageMemoryBarriers)
3897 {
3898 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3899 enum radv_cmd_flush_bits src_flush_bits = 0;
3900 enum radv_cmd_flush_bits dst_flush_bits = 0;
3901
3902 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3903 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3904 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3905 NULL);
3906 }
3907
3908 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3909 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3910 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3911 NULL);
3912 }
3913
3914 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3915 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3916 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3917 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3918 image);
3919 }
3920
3921 radv_stage_flush(cmd_buffer, srcStageMask);
3922 cmd_buffer->state.flush_bits |= src_flush_bits;
3923
3924 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3925 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3926 radv_handle_image_transition(cmd_buffer, image,
3927 pImageMemoryBarriers[i].oldLayout,
3928 pImageMemoryBarriers[i].newLayout,
3929 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3930 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3931 &pImageMemoryBarriers[i].subresourceRange,
3932 0);
3933 }
3934
3935 cmd_buffer->state.flush_bits |= dst_flush_bits;
3936 }
3937
3938
3939 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3940 struct radv_event *event,
3941 VkPipelineStageFlags stageMask,
3942 unsigned value)
3943 {
3944 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3945 uint64_t va = radv_buffer_get_va(event->bo);
3946
3947 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3948
3949 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3950
3951 /* TODO: this is overkill. Probably should figure something out from
3952 * the stage mask. */
3953
3954 si_cs_emit_write_event_eop(cs,
3955 cmd_buffer->state.predicating,
3956 cmd_buffer->device->physical_device->rad_info.chip_class,
3957 false,
3958 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3959 1, va, 2, value);
3960
3961 assert(cmd_buffer->cs->cdw <= cdw_max);
3962 }
3963
3964 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3965 VkEvent _event,
3966 VkPipelineStageFlags stageMask)
3967 {
3968 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3969 RADV_FROM_HANDLE(radv_event, event, _event);
3970
3971 write_event(cmd_buffer, event, stageMask, 1);
3972 }
3973
3974 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3975 VkEvent _event,
3976 VkPipelineStageFlags stageMask)
3977 {
3978 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3979 RADV_FROM_HANDLE(radv_event, event, _event);
3980
3981 write_event(cmd_buffer, event, stageMask, 0);
3982 }
3983
3984 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3985 uint32_t eventCount,
3986 const VkEvent* pEvents,
3987 VkPipelineStageFlags srcStageMask,
3988 VkPipelineStageFlags dstStageMask,
3989 uint32_t memoryBarrierCount,
3990 const VkMemoryBarrier* pMemoryBarriers,
3991 uint32_t bufferMemoryBarrierCount,
3992 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3993 uint32_t imageMemoryBarrierCount,
3994 const VkImageMemoryBarrier* pImageMemoryBarriers)
3995 {
3996 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3997 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3998
3999 for (unsigned i = 0; i < eventCount; ++i) {
4000 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4001 uint64_t va = radv_buffer_get_va(event->bo);
4002
4003 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4004
4005 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4006
4007 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4008 assert(cmd_buffer->cs->cdw <= cdw_max);
4009 }
4010
4011
4012 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4013 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4014
4015 radv_handle_image_transition(cmd_buffer, image,
4016 pImageMemoryBarriers[i].oldLayout,
4017 pImageMemoryBarriers[i].newLayout,
4018 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4019 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4020 &pImageMemoryBarriers[i].subresourceRange,
4021 0);
4022 }
4023
4024 /* TODO: figure out how to do memory barriers without waiting */
4025 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4026 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4027 RADV_CMD_FLAG_INV_VMEM_L1 |
4028 RADV_CMD_FLAG_INV_SMEM_L1;
4029 }