projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: fix VK_EXT_conditional_rendering visibility
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 VkImageAspectFlags pending_clears);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109
110 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
111 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
112 src->viewport.count * sizeof(VkViewport))) {
113 typed_memcpy(dest->viewport.viewports,
114 src->viewport.viewports,
115 src->viewport.count);
116 dest_mask |= RADV_DYNAMIC_VIEWPORT;
117 }
118 }
119
120 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
121 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
122 src->scissor.count * sizeof(VkRect2D))) {
123 typed_memcpy(dest->scissor.scissors,
124 src->scissor.scissors, src->scissor.count);
125 dest_mask |= RADV_DYNAMIC_SCISSOR;
126 }
127 }
128
129 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
130 if (dest->line_width != src->line_width) {
131 dest->line_width = src->line_width;
132 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
137 if (memcmp(&dest->depth_bias, &src->depth_bias,
138 sizeof(src->depth_bias))) {
139 dest->depth_bias = src->depth_bias;
140 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
145 if (memcmp(&dest->blend_constants, &src->blend_constants,
146 sizeof(src->blend_constants))) {
147 typed_memcpy(dest->blend_constants,
148 src->blend_constants, 4);
149 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
150 }
151 }
152
153 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
154 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
155 sizeof(src->depth_bounds))) {
156 dest->depth_bounds = src->depth_bounds;
157 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
158 }
159 }
160
161 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
162 if (memcmp(&dest->stencil_compare_mask,
163 &src->stencil_compare_mask,
164 sizeof(src->stencil_compare_mask))) {
165 dest->stencil_compare_mask = src->stencil_compare_mask;
166 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
167 }
168 }
169
170 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
171 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
172 sizeof(src->stencil_write_mask))) {
173 dest->stencil_write_mask = src->stencil_write_mask;
174 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
175 }
176 }
177
178 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
179 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
180 sizeof(src->stencil_reference))) {
181 dest->stencil_reference = src->stencil_reference;
182 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
183 }
184 }
185
186 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
187 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
188 src->discard_rectangle.count * sizeof(VkRect2D))) {
189 typed_memcpy(dest->discard_rectangle.rectangles,
190 src->discard_rectangle.rectangles,
191 src->discard_rectangle.count);
192 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
193 }
194 }
195
196 cmd_buffer->state.dirty |= dest_mask;
197 }
198
199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
200 {
201 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
202 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
203 }
204
205 enum ring_type radv_queue_family_to_ring(int f) {
206 switch (f) {
207 case RADV_QUEUE_GENERAL:
208 return RING_GFX;
209 case RADV_QUEUE_COMPUTE:
210 return RING_COMPUTE;
211 case RADV_QUEUE_TRANSFER:
212 return RING_DMA;
213 default:
214 unreachable("Unknown queue family");
215 }
216 }
217
218 static VkResult radv_create_cmd_buffer(
219 struct radv_device * device,
220 struct radv_cmd_pool * pool,
221 VkCommandBufferLevel level,
222 VkCommandBuffer* pCommandBuffer)
223 {
224 struct radv_cmd_buffer *cmd_buffer;
225 unsigned ring;
226 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
228 if (cmd_buffer == NULL)
229 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
230
231 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
232 cmd_buffer->device = device;
233 cmd_buffer->pool = pool;
234 cmd_buffer->level = level;
235
236 if (pool) {
237 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
238 cmd_buffer->queue_family_index = pool->queue_family_index;
239
240 } else {
241 /* Init the pool_link so we can safely call list_del when we destroy
242 * the command buffer
243 */
244 list_inithead(&cmd_buffer->pool_link);
245 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
246 }
247
248 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
249
250 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
251 if (!cmd_buffer->cs) {
252 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
253 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
254 }
255
256 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
257
258 list_inithead(&cmd_buffer->upload.list);
259
260 return VK_SUCCESS;
261 }
262
263 static void
264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
265 {
266 list_del(&cmd_buffer->pool_link);
267
268 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
269 &cmd_buffer->upload.list, list) {
270 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
271 list_del(&up->list);
272 free(up);
273 }
274
275 if (cmd_buffer->upload.upload_bo)
276 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
277 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
278
279 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
280 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
281
282 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
283 }
284
285 static VkResult
286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
287 {
288
289 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
290
291 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
292 &cmd_buffer->upload.list, list) {
293 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
294 list_del(&up->list);
295 free(up);
296 }
297
298 cmd_buffer->push_constant_stages = 0;
299 cmd_buffer->scratch_size_needed = 0;
300 cmd_buffer->compute_scratch_size_needed = 0;
301 cmd_buffer->esgs_ring_size_needed = 0;
302 cmd_buffer->gsvs_ring_size_needed = 0;
303 cmd_buffer->tess_rings_needed = false;
304 cmd_buffer->sample_positions_needed = false;
305
306 if (cmd_buffer->upload.upload_bo)
307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
308 cmd_buffer->upload.upload_bo);
309 cmd_buffer->upload.offset = 0;
310
311 cmd_buffer->record_result = VK_SUCCESS;
312
313 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
314 cmd_buffer->descriptors[i].dirty = 0;
315 cmd_buffer->descriptors[i].valid = 0;
316 cmd_buffer->descriptors[i].push_dirty = false;
317 }
318
319 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
320 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
321 unsigned eop_bug_offset;
322 void *fence_ptr;
323
324 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
325 &cmd_buffer->gfx9_fence_offset,
326 &fence_ptr);
327 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
328
329 /* Allocate a buffer for the EOP bug on GFX9. */
330 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
331 &eop_bug_offset, &fence_ptr);
332 cmd_buffer->gfx9_eop_bug_va =
333 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
334 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
335 }
336
337 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
338
339 return cmd_buffer->record_result;
340 }
341
342 static bool
343 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
344 uint64_t min_needed)
345 {
346 uint64_t new_size;
347 struct radeon_winsys_bo *bo;
348 struct radv_cmd_buffer_upload *upload;
349 struct radv_device *device = cmd_buffer->device;
350
351 new_size = MAX2(min_needed, 16 * 1024);
352 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
353
354 bo = device->ws->buffer_create(device->ws,
355 new_size, 4096,
356 RADEON_DOMAIN_GTT,
357 RADEON_FLAG_CPU_ACCESS|
358 RADEON_FLAG_NO_INTERPROCESS_SHARING |
359 RADEON_FLAG_32BIT);
360
361 if (!bo) {
362 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
363 return false;
364 }
365
366 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
367 if (cmd_buffer->upload.upload_bo) {
368 upload = malloc(sizeof(*upload));
369
370 if (!upload) {
371 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
372 device->ws->buffer_destroy(bo);
373 return false;
374 }
375
376 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
377 list_add(&upload->list, &cmd_buffer->upload.list);
378 }
379
380 cmd_buffer->upload.upload_bo = bo;
381 cmd_buffer->upload.size = new_size;
382 cmd_buffer->upload.offset = 0;
383 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
384
385 if (!cmd_buffer->upload.map) {
386 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
387 return false;
388 }
389
390 return true;
391 }
392
393 bool
394 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
395 unsigned size,
396 unsigned alignment,
397 unsigned *out_offset,
398 void **ptr)
399 {
400 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
401 if (offset + size > cmd_buffer->upload.size) {
402 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
403 return false;
404 offset = 0;
405 }
406
407 *out_offset = offset;
408 *ptr = cmd_buffer->upload.map + offset;
409
410 cmd_buffer->upload.offset = offset + size;
411 return true;
412 }
413
414 bool
415 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
416 unsigned size, unsigned alignment,
417 const void *data, unsigned *out_offset)
418 {
419 uint8_t *ptr;
420
421 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
422 out_offset, (void **)&ptr))
423 return false;
424
425 if (ptr)
426 memcpy(ptr, data, size);
427
428 return true;
429 }
430
431 static void
432 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
433 unsigned count, const uint32_t *data)
434 {
435 struct radeon_cmdbuf *cs = cmd_buffer->cs;
436
437 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
438
439 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
440 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
441 S_370_WR_CONFIRM(1) |
442 S_370_ENGINE_SEL(V_370_ME));
443 radeon_emit(cs, va);
444 radeon_emit(cs, va >> 32);
445 radeon_emit_array(cs, data, count);
446 }
447
448 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
449 {
450 struct radv_device *device = cmd_buffer->device;
451 struct radeon_cmdbuf *cs = cmd_buffer->cs;
452 uint64_t va;
453
454 va = radv_buffer_get_va(device->trace_bo);
455 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
456 va += 4;
457
458 ++cmd_buffer->state.trace_id;
459 radv_emit_write_data_packet(cmd_buffer, va, 1,
460 &cmd_buffer->state.trace_id);
461
462 radeon_check_space(cmd_buffer->device->ws, cs, 2);
463
464 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
465 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
466 }
467
468 static void
469 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
470 enum radv_cmd_flush_bits flags)
471 {
472 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
473 uint32_t *ptr = NULL;
474 uint64_t va = 0;
475
476 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
477 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
478
479 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
480 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
481 cmd_buffer->gfx9_fence_offset;
482 ptr = &cmd_buffer->gfx9_fence_idx;
483 }
484
485 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
486
487 /* Force wait for graphics or compute engines to be idle. */
488 si_cs_emit_cache_flush(cmd_buffer->cs,
489 cmd_buffer->device->physical_device->rad_info.chip_class,
490 ptr, va,
491 radv_cmd_buffer_uses_mec(cmd_buffer),
492 flags, cmd_buffer->gfx9_eop_bug_va);
493 }
494
495 if (unlikely(cmd_buffer->device->trace_bo))
496 radv_cmd_buffer_trace_emit(cmd_buffer);
497 }
498
499 static void
500 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
501 struct radv_pipeline *pipeline, enum ring_type ring)
502 {
503 struct radv_device *device = cmd_buffer->device;
504 uint32_t data[2];
505 uint64_t va;
506
507 va = radv_buffer_get_va(device->trace_bo);
508
509 switch (ring) {
510 case RING_GFX:
511 va += 8;
512 break;
513 case RING_COMPUTE:
514 va += 16;
515 break;
516 default:
517 assert(!"invalid ring type");
518 }
519
520 data[0] = (uintptr_t)pipeline;
521 data[1] = (uintptr_t)pipeline >> 32;
522
523 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
524 }
525
526 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
527 VkPipelineBindPoint bind_point,
528 struct radv_descriptor_set *set,
529 unsigned idx)
530 {
531 struct radv_descriptor_state *descriptors_state =
532 radv_get_descriptors_state(cmd_buffer, bind_point);
533
534 descriptors_state->sets[idx] = set;
535
536 descriptors_state->valid |= (1u << idx); /* active descriptors */
537 descriptors_state->dirty |= (1u << idx);
538 }
539
540 static void
541 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
542 VkPipelineBindPoint bind_point)
543 {
544 struct radv_descriptor_state *descriptors_state =
545 radv_get_descriptors_state(cmd_buffer, bind_point);
546 struct radv_device *device = cmd_buffer->device;
547 uint32_t data[MAX_SETS * 2] = {};
548 uint64_t va;
549 unsigned i;
550 va = radv_buffer_get_va(device->trace_bo) + 24;
551
552 for_each_bit(i, descriptors_state->valid) {
553 struct radv_descriptor_set *set = descriptors_state->sets[i];
554 data[i * 2] = (uintptr_t)set;
555 data[i * 2 + 1] = (uintptr_t)set >> 32;
556 }
557
558 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
559 }
560
561 struct radv_userdata_info *
562 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
563 gl_shader_stage stage,
564 int idx)
565 {
566 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
567 return &shader->info.user_sgprs_locs.shader_data[idx];
568 }
569
570 static void
571 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
572 struct radv_pipeline *pipeline,
573 gl_shader_stage stage,
574 int idx, uint64_t va)
575 {
576 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
577 uint32_t base_reg = pipeline->user_data_0[stage];
578 if (loc->sgpr_idx == -1)
579 return;
580
581 assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
582 assert(!loc->indirect);
583
584 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
585 base_reg + loc->sgpr_idx * 4, va, false);
586 }
587
588 static void
589 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
590 struct radv_pipeline *pipeline,
591 struct radv_descriptor_state *descriptors_state,
592 gl_shader_stage stage)
593 {
594 struct radv_device *device = cmd_buffer->device;
595 struct radeon_cmdbuf *cs = cmd_buffer->cs;
596 uint32_t sh_base = pipeline->user_data_0[stage];
597 struct radv_userdata_locations *locs =
598 &pipeline->shaders[stage]->info.user_sgprs_locs;
599 unsigned mask = locs->descriptor_sets_enabled;
600
601 mask &= descriptors_state->dirty & descriptors_state->valid;
602
603 while (mask) {
604 int start, count;
605
606 u_bit_scan_consecutive_range(&mask, &start, &count);
607
608 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
609 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
610
611 radv_emit_shader_pointer_head(cs, sh_offset, count,
612 HAVE_32BIT_POINTERS);
613 for (int i = 0; i < count; i++) {
614 struct radv_descriptor_set *set =
615 descriptors_state->sets[start + i];
616
617 radv_emit_shader_pointer_body(device, cs, set->va,
618 HAVE_32BIT_POINTERS);
619 }
620 }
621 }
622
623 static void
624 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
625 struct radv_pipeline *pipeline)
626 {
627 int num_samples = pipeline->graphics.ms.num_samples;
628 struct radv_multisample_state *ms = &pipeline->graphics.ms;
629 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
630
631 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
632 cmd_buffer->sample_positions_needed = true;
633
634 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
635 return;
636
637 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
638 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
639 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
640
641 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
642
643 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
644
645 /* GFX9: Flush DFSM when the AA mode changes. */
646 if (cmd_buffer->device->dfsm_allowed) {
647 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
648 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
649 }
650 }
651
652 static void
653 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
654 struct radv_shader_variant *shader)
655 {
656 uint64_t va;
657
658 if (!shader)
659 return;
660
661 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
662
663 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
664 }
665
666 static void
667 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
668 struct radv_pipeline *pipeline,
669 bool vertex_stage_only)
670 {
671 struct radv_cmd_state *state = &cmd_buffer->state;
672 uint32_t mask = state->prefetch_L2_mask;
673
674 if (vertex_stage_only) {
675 /* Fast prefetch path for starting draws as soon as possible.
676 */
677 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
678 RADV_PREFETCH_VBO_DESCRIPTORS);
679 }
680
681 if (mask & RADV_PREFETCH_VS)
682 radv_emit_shader_prefetch(cmd_buffer,
683 pipeline->shaders[MESA_SHADER_VERTEX]);
684
685 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
686 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
687
688 if (mask & RADV_PREFETCH_TCS)
689 radv_emit_shader_prefetch(cmd_buffer,
690 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
691
692 if (mask & RADV_PREFETCH_TES)
693 radv_emit_shader_prefetch(cmd_buffer,
694 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
695
696 if (mask & RADV_PREFETCH_GS) {
697 radv_emit_shader_prefetch(cmd_buffer,
698 pipeline->shaders[MESA_SHADER_GEOMETRY]);
699 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
700 }
701
702 if (mask & RADV_PREFETCH_PS)
703 radv_emit_shader_prefetch(cmd_buffer,
704 pipeline->shaders[MESA_SHADER_FRAGMENT]);
705
706 state->prefetch_L2_mask &= ~mask;
707 }
708
709 static void
710 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
711 {
712 if (!cmd_buffer->device->physical_device->rbplus_allowed)
713 return;
714
715 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
716 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
717 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
718
719 unsigned sx_ps_downconvert = 0;
720 unsigned sx_blend_opt_epsilon = 0;
721 unsigned sx_blend_opt_control = 0;
722
723 for (unsigned i = 0; i < subpass->color_count; ++i) {
724 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
725 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
726 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
727 continue;
728 }
729
730 int idx = subpass->color_attachments[i].attachment;
731 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
732
733 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
734 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
735 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
736 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
737
738 bool has_alpha, has_rgb;
739
740 /* Set if RGB and A are present. */
741 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
742
743 if (format == V_028C70_COLOR_8 ||
744 format == V_028C70_COLOR_16 ||
745 format == V_028C70_COLOR_32)
746 has_rgb = !has_alpha;
747 else
748 has_rgb = true;
749
750 /* Check the colormask and export format. */
751 if (!(colormask & 0x7))
752 has_rgb = false;
753 if (!(colormask & 0x8))
754 has_alpha = false;
755
756 if (spi_format == V_028714_SPI_SHADER_ZERO) {
757 has_rgb = false;
758 has_alpha = false;
759 }
760
761 /* Disable value checking for disabled channels. */
762 if (!has_rgb)
763 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
764 if (!has_alpha)
765 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
766
767 /* Enable down-conversion for 32bpp and smaller formats. */
768 switch (format) {
769 case V_028C70_COLOR_8:
770 case V_028C70_COLOR_8_8:
771 case V_028C70_COLOR_8_8_8_8:
772 /* For 1 and 2-channel formats, use the superset thereof. */
773 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
774 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
775 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
776 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
777 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
778 }
779 break;
780
781 case V_028C70_COLOR_5_6_5:
782 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
783 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
784 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
785 }
786 break;
787
788 case V_028C70_COLOR_1_5_5_5:
789 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
790 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
791 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
792 }
793 break;
794
795 case V_028C70_COLOR_4_4_4_4:
796 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
797 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
798 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
799 }
800 break;
801
802 case V_028C70_COLOR_32:
803 if (swap == V_028C70_SWAP_STD &&
804 spi_format == V_028714_SPI_SHADER_32_R)
805 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
806 else if (swap == V_028C70_SWAP_ALT_REV &&
807 spi_format == V_028714_SPI_SHADER_32_AR)
808 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
809 break;
810
811 case V_028C70_COLOR_16:
812 case V_028C70_COLOR_16_16:
813 /* For 1-channel formats, use the superset thereof. */
814 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
815 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
816 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
817 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
818 if (swap == V_028C70_SWAP_STD ||
819 swap == V_028C70_SWAP_STD_REV)
820 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
821 else
822 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
823 }
824 break;
825
826 case V_028C70_COLOR_10_11_11:
827 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
828 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
829 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
830 }
831 break;
832
833 case V_028C70_COLOR_2_10_10_10:
834 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
835 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
836 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
837 }
838 break;
839 }
840 }
841
842 for (unsigned i = subpass->color_count; i < 8; ++i) {
843 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
844 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
845 }
846 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
847 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
848 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
849 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
850 }
851
852 static void
853 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
854 {
855 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
856
857 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
858 return;
859
860 radv_update_multisample_state(cmd_buffer, pipeline);
861
862 cmd_buffer->scratch_size_needed =
863 MAX2(cmd_buffer->scratch_size_needed,
864 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
865
866 if (!cmd_buffer->state.emitted_pipeline ||
867 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
868 pipeline->graphics.can_use_guardband)
869 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
870
871 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
872
873 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
874 if (!pipeline->shaders[i])
875 continue;
876
877 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
878 pipeline->shaders[i]->bo);
879 }
880
881 if (radv_pipeline_has_gs(pipeline))
882 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
883 pipeline->gs_copy_shader->bo);
884
885 if (unlikely(cmd_buffer->device->trace_bo))
886 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
887
888 cmd_buffer->state.emitted_pipeline = pipeline;
889
890 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
891 }
892
893 static void
894 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
895 {
896 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
897 cmd_buffer->state.dynamic.viewport.viewports);
898 }
899
900 static void
901 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
902 {
903 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
904
905 si_write_scissors(cmd_buffer->cs, 0, count,
906 cmd_buffer->state.dynamic.scissor.scissors,
907 cmd_buffer->state.dynamic.viewport.viewports,
908 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
909 }
910
911 static void
912 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
913 {
914 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
915 return;
916
917 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
918 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
919 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
920 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
921 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
922 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
923 S_028214_BR_Y(rect.offset.y + rect.extent.height));
924 }
925 }
926
927 static void
928 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
929 {
930 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
931
932 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
933 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
934 }
935
936 static void
937 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
938 {
939 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
940
941 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
942 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
943 }
944
945 static void
946 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
947 {
948 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
949
950 radeon_set_context_reg_seq(cmd_buffer->cs,
951 R_028430_DB_STENCILREFMASK, 2);
952 radeon_emit(cmd_buffer->cs,
953 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
954 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
955 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
956 S_028430_STENCILOPVAL(1));
957 radeon_emit(cmd_buffer->cs,
958 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
959 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
960 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
961 S_028434_STENCILOPVAL_BF(1));
962 }
963
964 static void
965 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
966 {
967 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
968
969 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
970 fui(d->depth_bounds.min));
971 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
972 fui(d->depth_bounds.max));
973 }
974
975 static void
976 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
977 {
978 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
979 unsigned slope = fui(d->depth_bias.slope * 16.0f);
980 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
981
982
983 radeon_set_context_reg_seq(cmd_buffer->cs,
984 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
985 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
986 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
987 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
988 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
989 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
990 }
991
992 static void
993 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
994 int index,
995 struct radv_attachment_info *att,
996 struct radv_image *image,
997 VkImageLayout layout)
998 {
999 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1000 struct radv_color_buffer_info *cb = &att->cb;
1001 uint32_t cb_color_info = cb->cb_color_info;
1002
1003 if (!radv_layout_dcc_compressed(image, layout,
1004 radv_image_queue_family_mask(image,
1005 cmd_buffer->queue_family_index,
1006 cmd_buffer->queue_family_index))) {
1007 cb_color_info &= C_028C70_DCC_ENABLE;
1008 }
1009
1010 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1011 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1012 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1013 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1014 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1015 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1016 radeon_emit(cmd_buffer->cs, cb_color_info);
1017 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1018 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1019 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1020 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1021 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1022 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1023
1024 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1025 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1026 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1027
1028 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1029 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1030 } else {
1031 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1032 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1033 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1034 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1035 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1036 radeon_emit(cmd_buffer->cs, cb_color_info);
1037 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1038 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1039 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1040 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1041 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1042 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1043
1044 if (is_vi) { /* DCC BASE */
1045 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1046 }
1047 }
1048 }
1049
1050 static void
1051 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1052 struct radv_ds_buffer_info *ds,
1053 struct radv_image *image, VkImageLayout layout,
1054 bool requires_cond_write)
1055 {
1056 uint32_t db_z_info = ds->db_z_info;
1057 uint32_t db_z_info_reg;
1058
1059 if (!radv_image_is_tc_compat_htile(image))
1060 return;
1061
1062 if (!radv_layout_has_htile(image, layout,
1063 radv_image_queue_family_mask(image,
1064 cmd_buffer->queue_family_index,
1065 cmd_buffer->queue_family_index))) {
1066 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1067 }
1068
1069 db_z_info &= C_028040_ZRANGE_PRECISION;
1070
1071 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1072 db_z_info_reg = R_028038_DB_Z_INFO;
1073 } else {
1074 db_z_info_reg = R_028040_DB_Z_INFO;
1075 }
1076
1077 /* When we don't know the last fast clear value we need to emit a
1078 * conditional packet, otherwise we can update DB_Z_INFO directly.
1079 */
1080 if (requires_cond_write) {
1081 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
1082
1083 const uint32_t write_space = 0 << 8; /* register */
1084 const uint32_t poll_space = 1 << 4; /* memory */
1085 const uint32_t function = 3 << 0; /* equal to the reference */
1086 const uint32_t options = write_space | poll_space | function;
1087 radeon_emit(cmd_buffer->cs, options);
1088
1089 /* poll address - location of the depth clear value */
1090 uint64_t va = radv_buffer_get_va(image->bo);
1091 va += image->offset + image->clear_value_offset;
1092
1093 /* In presence of stencil format, we have to adjust the base
1094 * address because the first value is the stencil clear value.
1095 */
1096 if (vk_format_is_stencil(image->vk_format))
1097 va += 4;
1098
1099 radeon_emit(cmd_buffer->cs, va);
1100 radeon_emit(cmd_buffer->cs, va >> 32);
1101
1102 radeon_emit(cmd_buffer->cs, fui(0.0f)); /* reference value */
1103 radeon_emit(cmd_buffer->cs, (uint32_t)-1); /* comparison mask */
1104 radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
1105 radeon_emit(cmd_buffer->cs, 0u); /* write address high */
1106 radeon_emit(cmd_buffer->cs, db_z_info);
1107 } else {
1108 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1109 }
1110 }
1111
1112 static void
1113 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1114 struct radv_ds_buffer_info *ds,
1115 struct radv_image *image,
1116 VkImageLayout layout)
1117 {
1118 uint32_t db_z_info = ds->db_z_info;
1119 uint32_t db_stencil_info = ds->db_stencil_info;
1120
1121 if (!radv_layout_has_htile(image, layout,
1122 radv_image_queue_family_mask(image,
1123 cmd_buffer->queue_family_index,
1124 cmd_buffer->queue_family_index))) {
1125 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1126 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1127 }
1128
1129 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1130 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1131
1132
1133 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1134 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1135 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1136 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1137 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1138
1139 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1140 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1141 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1142 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1143 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1144 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1145 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1146 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1147 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1148 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1149 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1150
1151 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1152 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1153 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1154 } else {
1155 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1156
1157 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1158 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1159 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1160 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1161 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1162 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1163 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1164 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1165 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1166 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1167
1168 }
1169
1170 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1171 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1172
1173 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1174 ds->pa_su_poly_offset_db_fmt_cntl);
1175 }
1176
1177 /**
1178 * Update the fast clear depth/stencil values if the image is bound as a
1179 * depth/stencil buffer.
1180 */
1181 static void
1182 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1183 struct radv_image *image,
1184 VkClearDepthStencilValue ds_clear_value,
1185 VkImageAspectFlags aspects)
1186 {
1187 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1188 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1189 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1190 struct radv_attachment_info *att;
1191 uint32_t att_idx;
1192
1193 if (!framebuffer || !subpass)
1194 return;
1195
1196 att_idx = subpass->depth_stencil_attachment.attachment;
1197 if (att_idx == VK_ATTACHMENT_UNUSED)
1198 return;
1199
1200 att = &framebuffer->attachments[att_idx];
1201 if (att->attachment->image != image)
1202 return;
1203
1204 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1205 radeon_emit(cs, ds_clear_value.stencil);
1206 radeon_emit(cs, fui(ds_clear_value.depth));
1207
1208 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1209 * only needed when clearing Z to 0.0.
1210 */
1211 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1212 ds_clear_value.depth == 0.0) {
1213 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1214
1215 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1216 layout, false);
1217 }
1218 }
1219
1220 /**
1221 * Set the clear depth/stencil values to the image's metadata.
1222 */
1223 static void
1224 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1225 struct radv_image *image,
1226 VkClearDepthStencilValue ds_clear_value,
1227 VkImageAspectFlags aspects)
1228 {
1229 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1230 uint64_t va = radv_buffer_get_va(image->bo);
1231 unsigned reg_offset = 0, reg_count = 0;
1232
1233 va += image->offset + image->clear_value_offset;
1234
1235 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1236 ++reg_count;
1237 } else {
1238 ++reg_offset;
1239 va += 4;
1240 }
1241 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1242 ++reg_count;
1243
1244 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1245 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1246 S_370_WR_CONFIRM(1) |
1247 S_370_ENGINE_SEL(V_370_PFP));
1248 radeon_emit(cs, va);
1249 radeon_emit(cs, va >> 32);
1250 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1251 radeon_emit(cs, ds_clear_value.stencil);
1252 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1253 radeon_emit(cs, fui(ds_clear_value.depth));
1254 }
1255
1256 /**
1257 * Update the clear depth/stencil values for this image.
1258 */
1259 void
1260 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1261 struct radv_image *image,
1262 VkClearDepthStencilValue ds_clear_value,
1263 VkImageAspectFlags aspects)
1264 {
1265 assert(radv_image_has_htile(image));
1266
1267 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1268
1269 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1270 aspects);
1271 }
1272
1273 /**
1274 * Load the clear depth/stencil values from the image's metadata.
1275 */
1276 static void
1277 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1278 struct radv_image *image)
1279 {
1280 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1281 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1282 uint64_t va = radv_buffer_get_va(image->bo);
1283 unsigned reg_offset = 0, reg_count = 0;
1284
1285 va += image->offset + image->clear_value_offset;
1286
1287 if (!radv_image_has_htile(image))
1288 return;
1289
1290 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1291 ++reg_count;
1292 } else {
1293 ++reg_offset;
1294 va += 4;
1295 }
1296 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1297 ++reg_count;
1298
1299 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1300 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1301 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1302 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1303 radeon_emit(cs, va);
1304 radeon_emit(cs, va >> 32);
1305 radeon_emit(cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1306 radeon_emit(cs, 0);
1307
1308 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1309 radeon_emit(cs, 0);
1310 }
1311
1312 /*
1313 * With DCC some colors don't require CMASK elimination before being
1314 * used as a texture. This sets a predicate value to determine if the
1315 * cmask eliminate is required.
1316 */
1317 void
1318 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1319 struct radv_image *image,
1320 bool value)
1321 {
1322 uint64_t pred_val = value;
1323 uint64_t va = radv_buffer_get_va(image->bo);
1324 va += image->offset + image->dcc_pred_offset;
1325
1326 assert(radv_image_has_dcc(image));
1327
1328 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1329 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1330 S_370_WR_CONFIRM(1) |
1331 S_370_ENGINE_SEL(V_370_PFP));
1332 radeon_emit(cmd_buffer->cs, va);
1333 radeon_emit(cmd_buffer->cs, va >> 32);
1334 radeon_emit(cmd_buffer->cs, pred_val);
1335 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1336 }
1337
1338 /**
1339 * Update the fast clear color values if the image is bound as a color buffer.
1340 */
1341 static void
1342 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1343 struct radv_image *image,
1344 int cb_idx,
1345 uint32_t color_values[2])
1346 {
1347 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1348 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1349 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1350 struct radv_attachment_info *att;
1351 uint32_t att_idx;
1352
1353 if (!framebuffer || !subpass)
1354 return;
1355
1356 att_idx = subpass->color_attachments[cb_idx].attachment;
1357 if (att_idx == VK_ATTACHMENT_UNUSED)
1358 return;
1359
1360 att = &framebuffer->attachments[att_idx];
1361 if (att->attachment->image != image)
1362 return;
1363
1364 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1365 radeon_emit(cs, color_values[0]);
1366 radeon_emit(cs, color_values[1]);
1367 }
1368
1369 /**
1370 * Set the clear color values to the image's metadata.
1371 */
1372 static void
1373 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1374 struct radv_image *image,
1375 uint32_t color_values[2])
1376 {
1377 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1378 uint64_t va = radv_buffer_get_va(image->bo);
1379
1380 va += image->offset + image->clear_value_offset;
1381
1382 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1383
1384 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1385 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1386 S_370_WR_CONFIRM(1) |
1387 S_370_ENGINE_SEL(V_370_PFP));
1388 radeon_emit(cs, va);
1389 radeon_emit(cs, va >> 32);
1390 radeon_emit(cs, color_values[0]);
1391 radeon_emit(cs, color_values[1]);
1392 }
1393
1394 /**
1395 * Update the clear color values for this image.
1396 */
1397 void
1398 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1399 struct radv_image *image,
1400 int cb_idx,
1401 uint32_t color_values[2])
1402 {
1403 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1404
1405 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1406
1407 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1408 color_values);
1409 }
1410
1411 /**
1412 * Load the clear color values from the image's metadata.
1413 */
1414 static void
1415 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1416 struct radv_image *image,
1417 int cb_idx)
1418 {
1419 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1420 uint64_t va = radv_buffer_get_va(image->bo);
1421
1422 va += image->offset + image->clear_value_offset;
1423
1424 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1425 return;
1426
1427 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1428
1429 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1430 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1431 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1432 COPY_DATA_COUNT_SEL);
1433 radeon_emit(cs, va);
1434 radeon_emit(cs, va >> 32);
1435 radeon_emit(cs, reg >> 2);
1436 radeon_emit(cs, 0);
1437
1438 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1439 radeon_emit(cs, 0);
1440 }
1441
1442 static void
1443 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1444 {
1445 int i;
1446 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1447 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1448
1449 /* this may happen for inherited secondary recording */
1450 if (!framebuffer)
1451 return;
1452
1453 for (i = 0; i < 8; ++i) {
1454 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1455 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1456 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1457 continue;
1458 }
1459
1460 int idx = subpass->color_attachments[i].attachment;
1461 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1462 struct radv_image *image = att->attachment->image;
1463 VkImageLayout layout = subpass->color_attachments[i].layout;
1464
1465 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1466
1467 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1468 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1469
1470 radv_load_color_clear_metadata(cmd_buffer, image, i);
1471 }
1472
1473 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1474 int idx = subpass->depth_stencil_attachment.attachment;
1475 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1476 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1477 struct radv_image *image = att->attachment->image;
1478 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1479 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1480 cmd_buffer->queue_family_index,
1481 cmd_buffer->queue_family_index);
1482 /* We currently don't support writing decompressed HTILE */
1483 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1484 radv_layout_is_htile_compressed(image, layout, queue_mask));
1485
1486 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1487
1488 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1489 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1490 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1491 }
1492 radv_load_ds_clear_metadata(cmd_buffer, image);
1493 } else {
1494 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1495 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1496 else
1497 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1498
1499 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1500 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1501 }
1502 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1503 S_028208_BR_X(framebuffer->width) |
1504 S_028208_BR_Y(framebuffer->height));
1505
1506 if (cmd_buffer->device->dfsm_allowed) {
1507 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1508 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1509 }
1510
1511 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1512 }
1513
1514 static void
1515 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1516 {
1517 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1518 struct radv_cmd_state *state = &cmd_buffer->state;
1519
1520 if (state->index_type != state->last_index_type) {
1521 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1522 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1523 2, state->index_type);
1524 } else {
1525 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1526 radeon_emit(cs, state->index_type);
1527 }
1528
1529 state->last_index_type = state->index_type;
1530 }
1531
1532 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1533 radeon_emit(cs, state->index_va);
1534 radeon_emit(cs, state->index_va >> 32);
1535
1536 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1537 radeon_emit(cs, state->max_index_count);
1538
1539 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1540 }
1541
1542 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1543 {
1544 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1545 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1546 uint32_t pa_sc_mode_cntl_1 =
1547 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1548 uint32_t db_count_control;
1549
1550 if(!cmd_buffer->state.active_occlusion_queries) {
1551 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1552 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1553 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1554 has_perfect_queries) {
1555 /* Re-enable out-of-order rasterization if the
1556 * bound pipeline supports it and if it's has
1557 * been disabled before starting any perfect
1558 * occlusion queries.
1559 */
1560 radeon_set_context_reg(cmd_buffer->cs,
1561 R_028A4C_PA_SC_MODE_CNTL_1,
1562 pa_sc_mode_cntl_1);
1563 }
1564 }
1565 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1566 } else {
1567 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1568 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1569
1570 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1571 db_count_control =
1572 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1573 S_028004_SAMPLE_RATE(sample_rate) |
1574 S_028004_ZPASS_ENABLE(1) |
1575 S_028004_SLICE_EVEN_ENABLE(1) |
1576 S_028004_SLICE_ODD_ENABLE(1);
1577
1578 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1579 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1580 has_perfect_queries) {
1581 /* If the bound pipeline has enabled
1582 * out-of-order rasterization, we should
1583 * disable it before starting any perfect
1584 * occlusion queries.
1585 */
1586 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1587
1588 radeon_set_context_reg(cmd_buffer->cs,
1589 R_028A4C_PA_SC_MODE_CNTL_1,
1590 pa_sc_mode_cntl_1);
1591 }
1592 } else {
1593 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1594 S_028004_SAMPLE_RATE(sample_rate);
1595 }
1596 }
1597
1598 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1599 }
1600
1601 static void
1602 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1603 {
1604 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1605
1606 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1607 radv_emit_viewport(cmd_buffer);
1608
1609 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1610 !cmd_buffer->device->physical_device->has_scissor_bug)
1611 radv_emit_scissor(cmd_buffer);
1612
1613 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1614 radv_emit_line_width(cmd_buffer);
1615
1616 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1617 radv_emit_blend_constants(cmd_buffer);
1618
1619 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1620 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1621 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1622 radv_emit_stencil(cmd_buffer);
1623
1624 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1625 radv_emit_depth_bounds(cmd_buffer);
1626
1627 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1628 radv_emit_depth_bias(cmd_buffer);
1629
1630 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1631 radv_emit_discard_rectangle(cmd_buffer);
1632
1633 cmd_buffer->state.dirty &= ~states;
1634 }
1635
1636 static void
1637 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1638 VkPipelineBindPoint bind_point)
1639 {
1640 struct radv_descriptor_state *descriptors_state =
1641 radv_get_descriptors_state(cmd_buffer, bind_point);
1642 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1643 unsigned bo_offset;
1644
1645 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1646 set->mapped_ptr,
1647 &bo_offset))
1648 return;
1649
1650 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1651 set->va += bo_offset;
1652 }
1653
1654 static void
1655 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1656 VkPipelineBindPoint bind_point)
1657 {
1658 struct radv_descriptor_state *descriptors_state =
1659 radv_get_descriptors_state(cmd_buffer, bind_point);
1660 uint32_t size = MAX_SETS * 2 * 4;
1661 uint32_t offset;
1662 void *ptr;
1663
1664 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1665 256, &offset, &ptr))
1666 return;
1667
1668 for (unsigned i = 0; i < MAX_SETS; i++) {
1669 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1670 uint64_t set_va = 0;
1671 struct radv_descriptor_set *set = descriptors_state->sets[i];
1672 if (descriptors_state->valid & (1u << i))
1673 set_va = set->va;
1674 uptr[0] = set_va & 0xffffffff;
1675 uptr[1] = set_va >> 32;
1676 }
1677
1678 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1679 va += offset;
1680
1681 if (cmd_buffer->state.pipeline) {
1682 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1683 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1684 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1685
1686 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1687 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1688 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1689
1690 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1691 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1692 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1693
1694 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1695 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1696 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1697
1698 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1699 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1700 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1701 }
1702
1703 if (cmd_buffer->state.compute_pipeline)
1704 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1705 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1706 }
1707
1708 static void
1709 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1710 VkShaderStageFlags stages)
1711 {
1712 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1713 VK_PIPELINE_BIND_POINT_COMPUTE :
1714 VK_PIPELINE_BIND_POINT_GRAPHICS;
1715 struct radv_descriptor_state *descriptors_state =
1716 radv_get_descriptors_state(cmd_buffer, bind_point);
1717
1718 if (!descriptors_state->dirty)
1719 return;
1720
1721 if (descriptors_state->push_dirty)
1722 radv_flush_push_descriptors(cmd_buffer, bind_point);
1723
1724 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1725 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1726 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1727 }
1728
1729 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1730 cmd_buffer->cs,
1731 MAX_SETS * MESA_SHADER_STAGES * 4);
1732
1733 if (cmd_buffer->state.pipeline) {
1734 radv_foreach_stage(stage, stages) {
1735 if (!cmd_buffer->state.pipeline->shaders[stage])
1736 continue;
1737
1738 radv_emit_descriptor_pointers(cmd_buffer,
1739 cmd_buffer->state.pipeline,
1740 descriptors_state, stage);
1741 }
1742 }
1743
1744 if (cmd_buffer->state.compute_pipeline &&
1745 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1746 radv_emit_descriptor_pointers(cmd_buffer,
1747 cmd_buffer->state.compute_pipeline,
1748 descriptors_state,
1749 MESA_SHADER_COMPUTE);
1750 }
1751
1752 descriptors_state->dirty = 0;
1753 descriptors_state->push_dirty = false;
1754
1755 assert(cmd_buffer->cs->cdw <= cdw_max);
1756
1757 if (unlikely(cmd_buffer->device->trace_bo))
1758 radv_save_descriptors(cmd_buffer, bind_point);
1759 }
1760
1761 static void
1762 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1763 VkShaderStageFlags stages)
1764 {
1765 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1766 ? cmd_buffer->state.compute_pipeline
1767 : cmd_buffer->state.pipeline;
1768 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1769 VK_PIPELINE_BIND_POINT_COMPUTE :
1770 VK_PIPELINE_BIND_POINT_GRAPHICS;
1771 struct radv_descriptor_state *descriptors_state =
1772 radv_get_descriptors_state(cmd_buffer, bind_point);
1773 struct radv_pipeline_layout *layout = pipeline->layout;
1774 struct radv_shader_variant *shader, *prev_shader;
1775 unsigned offset;
1776 void *ptr;
1777 uint64_t va;
1778
1779 stages &= cmd_buffer->push_constant_stages;
1780 if (!stages ||
1781 (!layout->push_constant_size && !layout->dynamic_offset_count))
1782 return;
1783
1784 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1785 16 * layout->dynamic_offset_count,
1786 256, &offset, &ptr))
1787 return;
1788
1789 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1790 memcpy((char*)ptr + layout->push_constant_size,
1791 descriptors_state->dynamic_buffers,
1792 16 * layout->dynamic_offset_count);
1793
1794 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1795 va += offset;
1796
1797 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1798 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1799
1800 prev_shader = NULL;
1801 radv_foreach_stage(stage, stages) {
1802 shader = radv_get_shader(pipeline, stage);
1803
1804 /* Avoid redundantly emitting the address for merged stages. */
1805 if (shader && shader != prev_shader) {
1806 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1807 AC_UD_PUSH_CONSTANTS, va);
1808
1809 prev_shader = shader;
1810 }
1811 }
1812
1813 cmd_buffer->push_constant_stages &= ~stages;
1814 assert(cmd_buffer->cs->cdw <= cdw_max);
1815 }
1816
1817 static void
1818 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1819 bool pipeline_is_dirty)
1820 {
1821 if ((pipeline_is_dirty ||
1822 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1823 cmd_buffer->state.pipeline->vertex_elements.count &&
1824 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1825 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1826 unsigned vb_offset;
1827 void *vb_ptr;
1828 uint32_t i = 0;
1829 uint32_t count = velems->count;
1830 uint64_t va;
1831
1832 /* allocate some descriptor state for vertex buffers */
1833 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1834 &vb_offset, &vb_ptr))
1835 return;
1836
1837 for (i = 0; i < count; i++) {
1838 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1839 uint32_t offset;
1840 int vb = velems->binding[i];
1841 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1842 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1843
1844 va = radv_buffer_get_va(buffer->bo);
1845
1846 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1847 va += offset + buffer->offset;
1848 desc[0] = va;
1849 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1850 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1851 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1852 else
1853 desc[2] = buffer->size - offset;
1854 desc[3] = velems->rsrc_word3[i];
1855 }
1856
1857 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1858 va += vb_offset;
1859
1860 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1861 AC_UD_VS_VERTEX_BUFFERS, va);
1862
1863 cmd_buffer->state.vb_va = va;
1864 cmd_buffer->state.vb_size = count * 16;
1865 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1866 }
1867 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1868 }
1869
1870 static void
1871 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1872 {
1873 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1874 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1875 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1876 }
1877
1878 static void
1879 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1880 bool instanced_draw, bool indirect_draw,
1881 uint32_t draw_vertex_count)
1882 {
1883 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1884 struct radv_cmd_state *state = &cmd_buffer->state;
1885 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1886 uint32_t ia_multi_vgt_param;
1887 int32_t primitive_reset_en;
1888
1889 /* Draw state. */
1890 ia_multi_vgt_param =
1891 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1892 indirect_draw, draw_vertex_count);
1893
1894 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1895 if (info->chip_class >= GFX9) {
1896 radeon_set_uconfig_reg_idx(cs,
1897 R_030960_IA_MULTI_VGT_PARAM,
1898 4, ia_multi_vgt_param);
1899 } else if (info->chip_class >= CIK) {
1900 radeon_set_context_reg_idx(cs,
1901 R_028AA8_IA_MULTI_VGT_PARAM,
1902 1, ia_multi_vgt_param);
1903 } else {
1904 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1905 ia_multi_vgt_param);
1906 }
1907 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1908 }
1909
1910 /* Primitive restart. */
1911 primitive_reset_en =
1912 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1913
1914 if (primitive_reset_en != state->last_primitive_reset_en) {
1915 state->last_primitive_reset_en = primitive_reset_en;
1916 if (info->chip_class >= GFX9) {
1917 radeon_set_uconfig_reg(cs,
1918 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1919 primitive_reset_en);
1920 } else {
1921 radeon_set_context_reg(cs,
1922 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1923 primitive_reset_en);
1924 }
1925 }
1926
1927 if (primitive_reset_en) {
1928 uint32_t primitive_reset_index =
1929 state->index_type ? 0xffffffffu : 0xffffu;
1930
1931 if (primitive_reset_index != state->last_primitive_reset_index) {
1932 radeon_set_context_reg(cs,
1933 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1934 primitive_reset_index);
1935 state->last_primitive_reset_index = primitive_reset_index;
1936 }
1937 }
1938 }
1939
1940 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1941 VkPipelineStageFlags src_stage_mask)
1942 {
1943 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1944 VK_PIPELINE_STAGE_TRANSFER_BIT |
1945 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1946 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1947 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1948 }
1949
1950 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1951 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1952 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1953 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1954 VK_PIPELINE_STAGE_TRANSFER_BIT |
1955 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1956 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1957 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1958 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1959 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1960 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1961 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
1962 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1963 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1964 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT)) {
1965 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1966 }
1967 }
1968
1969 static enum radv_cmd_flush_bits
1970 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1971 VkAccessFlags src_flags,
1972 struct radv_image *image)
1973 {
1974 bool flush_CB_meta = true, flush_DB_meta = true;
1975 enum radv_cmd_flush_bits flush_bits = 0;
1976 uint32_t b;
1977
1978 if (image) {
1979 if (!radv_image_has_CB_metadata(image))
1980 flush_CB_meta = false;
1981 if (!radv_image_has_htile(image))
1982 flush_DB_meta = false;
1983 }
1984
1985 for_each_bit(b, src_flags) {
1986 switch ((VkAccessFlagBits)(1 << b)) {
1987 case VK_ACCESS_SHADER_WRITE_BIT:
1988 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1989 break;
1990 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1991 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
1992 if (flush_CB_meta)
1993 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1994 break;
1995 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1996 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
1997 if (flush_DB_meta)
1998 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1999 break;
2000 case VK_ACCESS_TRANSFER_WRITE_BIT:
2001 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2002 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2003 RADV_CMD_FLAG_INV_GLOBAL_L2;
2004
2005 if (flush_CB_meta)
2006 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2007 if (flush_DB_meta)
2008 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2009 break;
2010 default:
2011 break;
2012 }
2013 }
2014 return flush_bits;
2015 }
2016
2017 static enum radv_cmd_flush_bits
2018 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2019 VkAccessFlags dst_flags,
2020 struct radv_image *image)
2021 {
2022 bool flush_CB_meta = true, flush_DB_meta = true;
2023 enum radv_cmd_flush_bits flush_bits = 0;
2024 bool flush_CB = true, flush_DB = true;
2025 bool image_is_coherent = false;
2026 uint32_t b;
2027
2028 if (image) {
2029 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2030 flush_CB = false;
2031 flush_DB = false;
2032 }
2033
2034 if (!radv_image_has_CB_metadata(image))
2035 flush_CB_meta = false;
2036 if (!radv_image_has_htile(image))
2037 flush_DB_meta = false;
2038
2039 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2040 if (image->info.samples == 1 &&
2041 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2042 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2043 !vk_format_is_stencil(image->vk_format)) {
2044 /* Single-sample color and single-sample depth
2045 * (not stencil) are coherent with shaders on
2046 * GFX9.
2047 */
2048 image_is_coherent = true;
2049 }
2050 }
2051 }
2052
2053 for_each_bit(b, dst_flags) {
2054 switch ((VkAccessFlagBits)(1 << b)) {
2055 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2056 case VK_ACCESS_INDEX_READ_BIT:
2057 break;
2058 case VK_ACCESS_UNIFORM_READ_BIT:
2059 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2060 break;
2061 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2062 case VK_ACCESS_TRANSFER_READ_BIT:
2063 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2064 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2065 RADV_CMD_FLAG_INV_GLOBAL_L2;
2066 break;
2067 case VK_ACCESS_SHADER_READ_BIT:
2068 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2069
2070 if (!image_is_coherent)
2071 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2072 break;
2073 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2074 if (flush_CB)
2075 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2076 if (flush_CB_meta)
2077 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2078 break;
2079 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2080 if (flush_DB)
2081 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2082 if (flush_DB_meta)
2083 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2084 break;
2085 default:
2086 break;
2087 }
2088 }
2089 return flush_bits;
2090 }
2091
2092 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2093 const struct radv_subpass_barrier *barrier)
2094 {
2095 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2096 NULL);
2097 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2098 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2099 NULL);
2100 }
2101
2102 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2103 struct radv_subpass_attachment att)
2104 {
2105 unsigned idx = att.attachment;
2106 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2107 VkImageSubresourceRange range;
2108 range.aspectMask = 0;
2109 range.baseMipLevel = view->base_mip;
2110 range.levelCount = 1;
2111 range.baseArrayLayer = view->base_layer;
2112 range.layerCount = cmd_buffer->state.framebuffer->layers;
2113
2114 radv_handle_image_transition(cmd_buffer,
2115 view->image,
2116 cmd_buffer->state.attachments[idx].current_layout,
2117 att.layout, 0, 0, &range,
2118 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2119
2120 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2121
2122
2123 }
2124
2125 void
2126 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2127 const struct radv_subpass *subpass, bool transitions)
2128 {
2129 if (transitions) {
2130 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2131
2132 for (unsigned i = 0; i < subpass->color_count; ++i) {
2133 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2134 radv_handle_subpass_image_transition(cmd_buffer,
2135 subpass->color_attachments[i]);
2136 }
2137
2138 for (unsigned i = 0; i < subpass->input_count; ++i) {
2139 radv_handle_subpass_image_transition(cmd_buffer,
2140 subpass->input_attachments[i]);
2141 }
2142
2143 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2144 radv_handle_subpass_image_transition(cmd_buffer,
2145 subpass->depth_stencil_attachment);
2146 }
2147 }
2148
2149 cmd_buffer->state.subpass = subpass;
2150
2151 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2152 }
2153
2154 static VkResult
2155 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2156 struct radv_render_pass *pass,
2157 const VkRenderPassBeginInfo *info)
2158 {
2159 struct radv_cmd_state *state = &cmd_buffer->state;
2160
2161 if (pass->attachment_count == 0) {
2162 state->attachments = NULL;
2163 return VK_SUCCESS;
2164 }
2165
2166 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2167 pass->attachment_count *
2168 sizeof(state->attachments[0]),
2169 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2170 if (state->attachments == NULL) {
2171 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2172 return cmd_buffer->record_result;
2173 }
2174
2175 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2176 struct radv_render_pass_attachment *att = &pass->attachments[i];
2177 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2178 VkImageAspectFlags clear_aspects = 0;
2179
2180 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2181 /* color attachment */
2182 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2183 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2184 }
2185 } else {
2186 /* depthstencil attachment */
2187 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2188 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2189 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2190 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2191 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2192 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2193 }
2194 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2195 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2196 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2197 }
2198 }
2199
2200 state->attachments[i].pending_clear_aspects = clear_aspects;
2201 state->attachments[i].cleared_views = 0;
2202 if (clear_aspects && info) {
2203 assert(info->clearValueCount > i);
2204 state->attachments[i].clear_value = info->pClearValues[i];
2205 }
2206
2207 state->attachments[i].current_layout = att->initial_layout;
2208 }
2209
2210 return VK_SUCCESS;
2211 }
2212
2213 VkResult radv_AllocateCommandBuffers(
2214 VkDevice _device,
2215 const VkCommandBufferAllocateInfo *pAllocateInfo,
2216 VkCommandBuffer *pCommandBuffers)
2217 {
2218 RADV_FROM_HANDLE(radv_device, device, _device);
2219 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2220
2221 VkResult result = VK_SUCCESS;
2222 uint32_t i;
2223
2224 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2225
2226 if (!list_empty(&pool->free_cmd_buffers)) {
2227 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2228
2229 list_del(&cmd_buffer->pool_link);
2230 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2231
2232 result = radv_reset_cmd_buffer(cmd_buffer);
2233 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2234 cmd_buffer->level = pAllocateInfo->level;
2235
2236 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2237 } else {
2238 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2239 &pCommandBuffers[i]);
2240 }
2241 if (result != VK_SUCCESS)
2242 break;
2243 }
2244
2245 if (result != VK_SUCCESS) {
2246 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2247 i, pCommandBuffers);
2248
2249 /* From the Vulkan 1.0.66 spec:
2250 *
2251 * "vkAllocateCommandBuffers can be used to create multiple
2252 * command buffers. If the creation of any of those command
2253 * buffers fails, the implementation must destroy all
2254 * successfully created command buffer objects from this
2255 * command, set all entries of the pCommandBuffers array to
2256 * NULL and return the error."
2257 */
2258 memset(pCommandBuffers, 0,
2259 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2260 }
2261
2262 return result;
2263 }
2264
2265 void radv_FreeCommandBuffers(
2266 VkDevice device,
2267 VkCommandPool commandPool,
2268 uint32_t commandBufferCount,
2269 const VkCommandBuffer *pCommandBuffers)
2270 {
2271 for (uint32_t i = 0; i < commandBufferCount; i++) {
2272 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2273
2274 if (cmd_buffer) {
2275 if (cmd_buffer->pool) {
2276 list_del(&cmd_buffer->pool_link);
2277 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2278 } else
2279 radv_cmd_buffer_destroy(cmd_buffer);
2280
2281 }
2282 }
2283 }
2284
2285 VkResult radv_ResetCommandBuffer(
2286 VkCommandBuffer commandBuffer,
2287 VkCommandBufferResetFlags flags)
2288 {
2289 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2290 return radv_reset_cmd_buffer(cmd_buffer);
2291 }
2292
2293 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2294 {
2295 struct radv_device *device = cmd_buffer->device;
2296 if (device->gfx_init) {
2297 uint64_t va = radv_buffer_get_va(device->gfx_init);
2298 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init);
2299 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2300 radeon_emit(cmd_buffer->cs, va);
2301 radeon_emit(cmd_buffer->cs, va >> 32);
2302 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2303 } else
2304 si_init_config(cmd_buffer);
2305 }
2306
2307 VkResult radv_BeginCommandBuffer(
2308 VkCommandBuffer commandBuffer,
2309 const VkCommandBufferBeginInfo *pBeginInfo)
2310 {
2311 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2312 VkResult result = VK_SUCCESS;
2313
2314 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2315 /* If the command buffer has already been resetted with
2316 * vkResetCommandBuffer, no need to do it again.
2317 */
2318 result = radv_reset_cmd_buffer(cmd_buffer);
2319 if (result != VK_SUCCESS)
2320 return result;
2321 }
2322
2323 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2324 cmd_buffer->state.last_primitive_reset_en = -1;
2325 cmd_buffer->state.last_index_type = -1;
2326 cmd_buffer->state.last_num_instances = -1;
2327 cmd_buffer->state.last_vertex_offset = -1;
2328 cmd_buffer->state.last_first_instance = -1;
2329 cmd_buffer->state.predication_type = -1;
2330 cmd_buffer->usage_flags = pBeginInfo->flags;
2331
2332 /* setup initial configuration into command buffer */
2333 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2334 switch (cmd_buffer->queue_family_index) {
2335 case RADV_QUEUE_GENERAL:
2336 emit_gfx_buffer_state(cmd_buffer);
2337 break;
2338 case RADV_QUEUE_COMPUTE:
2339 si_init_compute(cmd_buffer);
2340 break;
2341 case RADV_QUEUE_TRANSFER:
2342 default:
2343 break;
2344 }
2345 }
2346
2347 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2348 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2349 assert(pBeginInfo->pInheritanceInfo);
2350 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2351 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2352
2353 struct radv_subpass *subpass =
2354 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2355
2356 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2357 if (result != VK_SUCCESS)
2358 return result;
2359
2360 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2361 }
2362
2363 if (unlikely(cmd_buffer->device->trace_bo)) {
2364 struct radv_device *device = cmd_buffer->device;
2365
2366 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2367 device->trace_bo);
2368
2369 radv_cmd_buffer_trace_emit(cmd_buffer);
2370 }
2371
2372 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2373
2374 return result;
2375 }
2376
2377 void radv_CmdBindVertexBuffers(
2378 VkCommandBuffer commandBuffer,
2379 uint32_t firstBinding,
2380 uint32_t bindingCount,
2381 const VkBuffer* pBuffers,
2382 const VkDeviceSize* pOffsets)
2383 {
2384 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2385 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2386 bool changed = false;
2387
2388 /* We have to defer setting up vertex buffer since we need the buffer
2389 * stride from the pipeline. */
2390
2391 assert(firstBinding + bindingCount <= MAX_VBS);
2392 for (uint32_t i = 0; i < bindingCount; i++) {
2393 uint32_t idx = firstBinding + i;
2394
2395 if (!changed &&
2396 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2397 vb[idx].offset != pOffsets[i])) {
2398 changed = true;
2399 }
2400
2401 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2402 vb[idx].offset = pOffsets[i];
2403
2404 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2405 vb[idx].buffer->bo);
2406 }
2407
2408 if (!changed) {
2409 /* No state changes. */
2410 return;
2411 }
2412
2413 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2414 }
2415
2416 void radv_CmdBindIndexBuffer(
2417 VkCommandBuffer commandBuffer,
2418 VkBuffer buffer,
2419 VkDeviceSize offset,
2420 VkIndexType indexType)
2421 {
2422 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2423 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2424
2425 if (cmd_buffer->state.index_buffer == index_buffer &&
2426 cmd_buffer->state.index_offset == offset &&
2427 cmd_buffer->state.index_type == indexType) {
2428 /* No state changes. */
2429 return;
2430 }
2431
2432 cmd_buffer->state.index_buffer = index_buffer;
2433 cmd_buffer->state.index_offset = offset;
2434 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2435 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2436 cmd_buffer->state.index_va += index_buffer->offset + offset;
2437
2438 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2439 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2440 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2441 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2442 }
2443
2444
2445 static void
2446 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2447 VkPipelineBindPoint bind_point,
2448 struct radv_descriptor_set *set, unsigned idx)
2449 {
2450 struct radeon_winsys *ws = cmd_buffer->device->ws;
2451
2452 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2453
2454 assert(set);
2455 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2456
2457 if (!cmd_buffer->device->use_global_bo_list) {
2458 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2459 if (set->descriptors[j])
2460 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2461 }
2462
2463 if(set->bo)
2464 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2465 }
2466
2467 void radv_CmdBindDescriptorSets(
2468 VkCommandBuffer commandBuffer,
2469 VkPipelineBindPoint pipelineBindPoint,
2470 VkPipelineLayout _layout,
2471 uint32_t firstSet,
2472 uint32_t descriptorSetCount,
2473 const VkDescriptorSet* pDescriptorSets,
2474 uint32_t dynamicOffsetCount,
2475 const uint32_t* pDynamicOffsets)
2476 {
2477 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2478 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2479 unsigned dyn_idx = 0;
2480
2481 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2482 struct radv_descriptor_state *descriptors_state =
2483 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2484
2485 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2486 unsigned idx = i + firstSet;
2487 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2488 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2489
2490 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2491 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2492 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2493 assert(dyn_idx < dynamicOffsetCount);
2494
2495 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2496 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2497 dst[0] = va;
2498 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2499 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2500 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2501 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2502 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2503 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2504 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2505 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2506 cmd_buffer->push_constant_stages |=
2507 set->layout->dynamic_shader_stages;
2508 }
2509 }
2510 }
2511
2512 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2513 struct radv_descriptor_set *set,
2514 struct radv_descriptor_set_layout *layout,
2515 VkPipelineBindPoint bind_point)
2516 {
2517 struct radv_descriptor_state *descriptors_state =
2518 radv_get_descriptors_state(cmd_buffer, bind_point);
2519 set->size = layout->size;
2520 set->layout = layout;
2521
2522 if (descriptors_state->push_set.capacity < set->size) {
2523 size_t new_size = MAX2(set->size, 1024);
2524 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2525 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2526
2527 free(set->mapped_ptr);
2528 set->mapped_ptr = malloc(new_size);
2529
2530 if (!set->mapped_ptr) {
2531 descriptors_state->push_set.capacity = 0;
2532 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2533 return false;
2534 }
2535
2536 descriptors_state->push_set.capacity = new_size;
2537 }
2538
2539 return true;
2540 }
2541
2542 void radv_meta_push_descriptor_set(
2543 struct radv_cmd_buffer* cmd_buffer,
2544 VkPipelineBindPoint pipelineBindPoint,
2545 VkPipelineLayout _layout,
2546 uint32_t set,
2547 uint32_t descriptorWriteCount,
2548 const VkWriteDescriptorSet* pDescriptorWrites)
2549 {
2550 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2551 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2552 unsigned bo_offset;
2553
2554 assert(set == 0);
2555 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2556
2557 push_set->size = layout->set[set].layout->size;
2558 push_set->layout = layout->set[set].layout;
2559
2560 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2561 &bo_offset,
2562 (void**) &push_set->mapped_ptr))
2563 return;
2564
2565 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2566 push_set->va += bo_offset;
2567
2568 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2569 radv_descriptor_set_to_handle(push_set),
2570 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2571
2572 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2573 }
2574
2575 void radv_CmdPushDescriptorSetKHR(
2576 VkCommandBuffer commandBuffer,
2577 VkPipelineBindPoint pipelineBindPoint,
2578 VkPipelineLayout _layout,
2579 uint32_t set,
2580 uint32_t descriptorWriteCount,
2581 const VkWriteDescriptorSet* pDescriptorWrites)
2582 {
2583 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2584 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2585 struct radv_descriptor_state *descriptors_state =
2586 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2587 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2588
2589 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2590
2591 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2592 layout->set[set].layout,
2593 pipelineBindPoint))
2594 return;
2595
2596 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2597 radv_descriptor_set_to_handle(push_set),
2598 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2599
2600 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2601 descriptors_state->push_dirty = true;
2602 }
2603
2604 void radv_CmdPushDescriptorSetWithTemplateKHR(
2605 VkCommandBuffer commandBuffer,
2606 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2607 VkPipelineLayout _layout,
2608 uint32_t set,
2609 const void* pData)
2610 {
2611 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2612 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2613 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2614 struct radv_descriptor_state *descriptors_state =
2615 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2616 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2617
2618 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2619
2620 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2621 layout->set[set].layout,
2622 templ->bind_point))
2623 return;
2624
2625 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2626 descriptorUpdateTemplate, pData);
2627
2628 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2629 descriptors_state->push_dirty = true;
2630 }
2631
2632 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2633 VkPipelineLayout layout,
2634 VkShaderStageFlags stageFlags,
2635 uint32_t offset,
2636 uint32_t size,
2637 const void* pValues)
2638 {
2639 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2640 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2641 cmd_buffer->push_constant_stages |= stageFlags;
2642 }
2643
2644 VkResult radv_EndCommandBuffer(
2645 VkCommandBuffer commandBuffer)
2646 {
2647 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2648
2649 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2650 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2651 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2652 si_emit_cache_flush(cmd_buffer);
2653 }
2654
2655 /* Make sure CP DMA is idle at the end of IBs because the kernel
2656 * doesn't wait for it.
2657 */
2658 si_cp_dma_wait_for_idle(cmd_buffer);
2659
2660 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2661
2662 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2663 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2664
2665 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2666
2667 return cmd_buffer->record_result;
2668 }
2669
2670 static void
2671 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2672 {
2673 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2674
2675 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2676 return;
2677
2678 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2679
2680 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2681 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2682
2683 cmd_buffer->compute_scratch_size_needed =
2684 MAX2(cmd_buffer->compute_scratch_size_needed,
2685 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2686
2687 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2688 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2689
2690 if (unlikely(cmd_buffer->device->trace_bo))
2691 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2692 }
2693
2694 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2695 VkPipelineBindPoint bind_point)
2696 {
2697 struct radv_descriptor_state *descriptors_state =
2698 radv_get_descriptors_state(cmd_buffer, bind_point);
2699
2700 descriptors_state->dirty |= descriptors_state->valid;
2701 }
2702
2703 void radv_CmdBindPipeline(
2704 VkCommandBuffer commandBuffer,
2705 VkPipelineBindPoint pipelineBindPoint,
2706 VkPipeline _pipeline)
2707 {
2708 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2709 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2710
2711 switch (pipelineBindPoint) {
2712 case VK_PIPELINE_BIND_POINT_COMPUTE:
2713 if (cmd_buffer->state.compute_pipeline == pipeline)
2714 return;
2715 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2716
2717 cmd_buffer->state.compute_pipeline = pipeline;
2718 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2719 break;
2720 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2721 if (cmd_buffer->state.pipeline == pipeline)
2722 return;
2723 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2724
2725 cmd_buffer->state.pipeline = pipeline;
2726 if (!pipeline)
2727 break;
2728
2729 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2730 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2731
2732 /* the new vertex shader might not have the same user regs */
2733 cmd_buffer->state.last_first_instance = -1;
2734 cmd_buffer->state.last_vertex_offset = -1;
2735
2736 /* Prefetch all pipeline shaders at first draw time. */
2737 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2738
2739 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2740
2741 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2742 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2743 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2744 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2745
2746 if (radv_pipeline_has_tess(pipeline))
2747 cmd_buffer->tess_rings_needed = true;
2748 break;
2749 default:
2750 assert(!"invalid bind point");
2751 break;
2752 }
2753 }
2754
2755 void radv_CmdSetViewport(
2756 VkCommandBuffer commandBuffer,
2757 uint32_t firstViewport,
2758 uint32_t viewportCount,
2759 const VkViewport* pViewports)
2760 {
2761 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2762 struct radv_cmd_state *state = &cmd_buffer->state;
2763 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2764
2765 assert(firstViewport < MAX_VIEWPORTS);
2766 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2767
2768 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2769 viewportCount * sizeof(*pViewports));
2770
2771 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2772 }
2773
2774 void radv_CmdSetScissor(
2775 VkCommandBuffer commandBuffer,
2776 uint32_t firstScissor,
2777 uint32_t scissorCount,
2778 const VkRect2D* pScissors)
2779 {
2780 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2781 struct radv_cmd_state *state = &cmd_buffer->state;
2782 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2783
2784 assert(firstScissor < MAX_SCISSORS);
2785 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2786
2787 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2788 scissorCount * sizeof(*pScissors));
2789
2790 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2791 }
2792
2793 void radv_CmdSetLineWidth(
2794 VkCommandBuffer commandBuffer,
2795 float lineWidth)
2796 {
2797 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2798 cmd_buffer->state.dynamic.line_width = lineWidth;
2799 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2800 }
2801
2802 void radv_CmdSetDepthBias(
2803 VkCommandBuffer commandBuffer,
2804 float depthBiasConstantFactor,
2805 float depthBiasClamp,
2806 float depthBiasSlopeFactor)
2807 {
2808 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2809
2810 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2811 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2812 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2813
2814 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2815 }
2816
2817 void radv_CmdSetBlendConstants(
2818 VkCommandBuffer commandBuffer,
2819 const float blendConstants[4])
2820 {
2821 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2822
2823 memcpy(cmd_buffer->state.dynamic.blend_constants,
2824 blendConstants, sizeof(float) * 4);
2825
2826 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2827 }
2828
2829 void radv_CmdSetDepthBounds(
2830 VkCommandBuffer commandBuffer,
2831 float minDepthBounds,
2832 float maxDepthBounds)
2833 {
2834 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2835
2836 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2837 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2838
2839 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2840 }
2841
2842 void radv_CmdSetStencilCompareMask(
2843 VkCommandBuffer commandBuffer,
2844 VkStencilFaceFlags faceMask,
2845 uint32_t compareMask)
2846 {
2847 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2848
2849 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2850 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2851 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2852 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2853
2854 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2855 }
2856
2857 void radv_CmdSetStencilWriteMask(
2858 VkCommandBuffer commandBuffer,
2859 VkStencilFaceFlags faceMask,
2860 uint32_t writeMask)
2861 {
2862 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2863
2864 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2865 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2866 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2867 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2868
2869 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2870 }
2871
2872 void radv_CmdSetStencilReference(
2873 VkCommandBuffer commandBuffer,
2874 VkStencilFaceFlags faceMask,
2875 uint32_t reference)
2876 {
2877 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2878
2879 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2880 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2881 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2882 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2883
2884 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2885 }
2886
2887 void radv_CmdSetDiscardRectangleEXT(
2888 VkCommandBuffer commandBuffer,
2889 uint32_t firstDiscardRectangle,
2890 uint32_t discardRectangleCount,
2891 const VkRect2D* pDiscardRectangles)
2892 {
2893 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2894 struct radv_cmd_state *state = &cmd_buffer->state;
2895 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2896
2897 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2898 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2899
2900 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2901 pDiscardRectangles, discardRectangleCount);
2902
2903 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2904 }
2905
2906 void radv_CmdExecuteCommands(
2907 VkCommandBuffer commandBuffer,
2908 uint32_t commandBufferCount,
2909 const VkCommandBuffer* pCmdBuffers)
2910 {
2911 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2912
2913 assert(commandBufferCount > 0);
2914
2915 /* Emit pending flushes on primary prior to executing secondary */
2916 si_emit_cache_flush(primary);
2917
2918 for (uint32_t i = 0; i < commandBufferCount; i++) {
2919 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2920
2921 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2922 secondary->scratch_size_needed);
2923 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2924 secondary->compute_scratch_size_needed);
2925
2926 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2927 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2928 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2929 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2930 if (secondary->tess_rings_needed)
2931 primary->tess_rings_needed = true;
2932 if (secondary->sample_positions_needed)
2933 primary->sample_positions_needed = true;
2934
2935 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2936
2937
2938 /* When the secondary command buffer is compute only we don't
2939 * need to re-emit the current graphics pipeline.
2940 */
2941 if (secondary->state.emitted_pipeline) {
2942 primary->state.emitted_pipeline =
2943 secondary->state.emitted_pipeline;
2944 }
2945
2946 /* When the secondary command buffer is graphics only we don't
2947 * need to re-emit the current compute pipeline.
2948 */
2949 if (secondary->state.emitted_compute_pipeline) {
2950 primary->state.emitted_compute_pipeline =
2951 secondary->state.emitted_compute_pipeline;
2952 }
2953
2954 /* Only re-emit the draw packets when needed. */
2955 if (secondary->state.last_primitive_reset_en != -1) {
2956 primary->state.last_primitive_reset_en =
2957 secondary->state.last_primitive_reset_en;
2958 }
2959
2960 if (secondary->state.last_primitive_reset_index) {
2961 primary->state.last_primitive_reset_index =
2962 secondary->state.last_primitive_reset_index;
2963 }
2964
2965 if (secondary->state.last_ia_multi_vgt_param) {
2966 primary->state.last_ia_multi_vgt_param =
2967 secondary->state.last_ia_multi_vgt_param;
2968 }
2969
2970 primary->state.last_first_instance = secondary->state.last_first_instance;
2971 primary->state.last_num_instances = secondary->state.last_num_instances;
2972 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2973
2974 if (secondary->state.last_index_type != -1) {
2975 primary->state.last_index_type =
2976 secondary->state.last_index_type;
2977 }
2978 }
2979
2980 /* After executing commands from secondary buffers we have to dirty
2981 * some states.
2982 */
2983 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2984 RADV_CMD_DIRTY_INDEX_BUFFER |
2985 RADV_CMD_DIRTY_DYNAMIC_ALL;
2986 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2987 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2988 }
2989
2990 VkResult radv_CreateCommandPool(
2991 VkDevice _device,
2992 const VkCommandPoolCreateInfo* pCreateInfo,
2993 const VkAllocationCallbacks* pAllocator,
2994 VkCommandPool* pCmdPool)
2995 {
2996 RADV_FROM_HANDLE(radv_device, device, _device);
2997 struct radv_cmd_pool *pool;
2998
2999 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3000 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3001 if (pool == NULL)
3002 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3003
3004 if (pAllocator)
3005 pool->alloc = *pAllocator;
3006 else
3007 pool->alloc = device->alloc;
3008
3009 list_inithead(&pool->cmd_buffers);
3010 list_inithead(&pool->free_cmd_buffers);
3011
3012 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3013
3014 *pCmdPool = radv_cmd_pool_to_handle(pool);
3015
3016 return VK_SUCCESS;
3017
3018 }
3019
3020 void radv_DestroyCommandPool(
3021 VkDevice _device,
3022 VkCommandPool commandPool,
3023 const VkAllocationCallbacks* pAllocator)
3024 {
3025 RADV_FROM_HANDLE(radv_device, device, _device);
3026 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3027
3028 if (!pool)
3029 return;
3030
3031 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3032 &pool->cmd_buffers, pool_link) {
3033 radv_cmd_buffer_destroy(cmd_buffer);
3034 }
3035
3036 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3037 &pool->free_cmd_buffers, pool_link) {
3038 radv_cmd_buffer_destroy(cmd_buffer);
3039 }
3040
3041 vk_free2(&device->alloc, pAllocator, pool);
3042 }
3043
3044 VkResult radv_ResetCommandPool(
3045 VkDevice device,
3046 VkCommandPool commandPool,
3047 VkCommandPoolResetFlags flags)
3048 {
3049 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3050 VkResult result;
3051
3052 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3053 &pool->cmd_buffers, pool_link) {
3054 result = radv_reset_cmd_buffer(cmd_buffer);
3055 if (result != VK_SUCCESS)
3056 return result;
3057 }
3058
3059 return VK_SUCCESS;
3060 }
3061
3062 void radv_TrimCommandPool(
3063 VkDevice device,
3064 VkCommandPool commandPool,
3065 VkCommandPoolTrimFlagsKHR flags)
3066 {
3067 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3068
3069 if (!pool)
3070 return;
3071
3072 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3073 &pool->free_cmd_buffers, pool_link) {
3074 radv_cmd_buffer_destroy(cmd_buffer);
3075 }
3076 }
3077
3078 void radv_CmdBeginRenderPass(
3079 VkCommandBuffer commandBuffer,
3080 const VkRenderPassBeginInfo* pRenderPassBegin,
3081 VkSubpassContents contents)
3082 {
3083 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3084 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3085 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3086
3087 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3088 cmd_buffer->cs, 2048);
3089 MAYBE_UNUSED VkResult result;
3090
3091 cmd_buffer->state.framebuffer = framebuffer;
3092 cmd_buffer->state.pass = pass;
3093 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3094
3095 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3096 if (result != VK_SUCCESS)
3097 return;
3098
3099 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3100 assert(cmd_buffer->cs->cdw <= cdw_max);
3101
3102 radv_cmd_buffer_clear_subpass(cmd_buffer);
3103 }
3104
3105 void radv_CmdBeginRenderPass2KHR(
3106 VkCommandBuffer commandBuffer,
3107 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3108 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3109 {
3110 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3111 pSubpassBeginInfo->contents);
3112 }
3113
3114 void radv_CmdNextSubpass(
3115 VkCommandBuffer commandBuffer,
3116 VkSubpassContents contents)
3117 {
3118 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3119
3120 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3121
3122 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3123 2048);
3124
3125 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3126 radv_cmd_buffer_clear_subpass(cmd_buffer);
3127 }
3128
3129 void radv_CmdNextSubpass2KHR(
3130 VkCommandBuffer commandBuffer,
3131 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3132 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3133 {
3134 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3135 }
3136
3137 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3138 {
3139 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3140 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3141 if (!radv_get_shader(pipeline, stage))
3142 continue;
3143
3144 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3145 if (loc->sgpr_idx == -1)
3146 continue;
3147 uint32_t base_reg = pipeline->user_data_0[stage];
3148 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3149
3150 }
3151 if (pipeline->gs_copy_shader) {
3152 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3153 if (loc->sgpr_idx != -1) {
3154 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3155 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3156 }
3157 }
3158 }
3159
3160 static void
3161 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3162 uint32_t vertex_count)
3163 {
3164 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3165 radeon_emit(cmd_buffer->cs, vertex_count);
3166 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3167 S_0287F0_USE_OPAQUE(0));
3168 }
3169
3170 static void
3171 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3172 uint64_t index_va,
3173 uint32_t index_count)
3174 {
3175 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3176 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3177 radeon_emit(cmd_buffer->cs, index_va);
3178 radeon_emit(cmd_buffer->cs, index_va >> 32);
3179 radeon_emit(cmd_buffer->cs, index_count);
3180 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3181 }
3182
3183 static void
3184 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3185 bool indexed,
3186 uint32_t draw_count,
3187 uint64_t count_va,
3188 uint32_t stride)
3189 {
3190 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3191 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3192 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3193 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3194 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3195 bool predicating = cmd_buffer->state.predicating;
3196 assert(base_reg);
3197
3198 /* just reset draw state for vertex data */
3199 cmd_buffer->state.last_first_instance = -1;
3200 cmd_buffer->state.last_num_instances = -1;
3201 cmd_buffer->state.last_vertex_offset = -1;
3202
3203 if (draw_count == 1 && !count_va && !draw_id_enable) {
3204 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3205 PKT3_DRAW_INDIRECT, 3, predicating));
3206 radeon_emit(cs, 0);
3207 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3208 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3209 radeon_emit(cs, di_src_sel);
3210 } else {
3211 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3212 PKT3_DRAW_INDIRECT_MULTI,
3213 8, predicating));
3214 radeon_emit(cs, 0);
3215 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3216 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3217 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3218 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3219 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3220 radeon_emit(cs, draw_count); /* count */
3221 radeon_emit(cs, count_va); /* count_addr */
3222 radeon_emit(cs, count_va >> 32);
3223 radeon_emit(cs, stride); /* stride */
3224 radeon_emit(cs, di_src_sel);
3225 }
3226 }
3227
3228 struct radv_draw_info {
3229 /**
3230 * Number of vertices.
3231 */
3232 uint32_t count;
3233
3234 /**
3235 * Index of the first vertex.
3236 */
3237 int32_t vertex_offset;
3238
3239 /**
3240 * First instance id.
3241 */
3242 uint32_t first_instance;
3243
3244 /**
3245 * Number of instances.
3246 */
3247 uint32_t instance_count;
3248
3249 /**
3250 * First index (indexed draws only).
3251 */
3252 uint32_t first_index;
3253
3254 /**
3255 * Whether it's an indexed draw.
3256 */
3257 bool indexed;
3258
3259 /**
3260 * Indirect draw parameters resource.
3261 */
3262 struct radv_buffer *indirect;
3263 uint64_t indirect_offset;
3264 uint32_t stride;
3265
3266 /**
3267 * Draw count parameters resource.
3268 */
3269 struct radv_buffer *count_buffer;
3270 uint64_t count_buffer_offset;
3271 };
3272
3273 static void
3274 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3275 const struct radv_draw_info *info)
3276 {
3277 struct radv_cmd_state *state = &cmd_buffer->state;
3278 struct radeon_winsys *ws = cmd_buffer->device->ws;
3279 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3280
3281 if (info->indirect) {
3282 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3283 uint64_t count_va = 0;
3284
3285 va += info->indirect->offset + info->indirect_offset;
3286
3287 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3288
3289 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3290 radeon_emit(cs, 1);
3291 radeon_emit(cs, va);
3292 radeon_emit(cs, va >> 32);
3293
3294 if (info->count_buffer) {
3295 count_va = radv_buffer_get_va(info->count_buffer->bo);
3296 count_va += info->count_buffer->offset +
3297 info->count_buffer_offset;
3298
3299 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3300 }
3301
3302 if (!state->subpass->view_mask) {
3303 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3304 info->indexed,
3305 info->count,
3306 count_va,
3307 info->stride);
3308 } else {
3309 unsigned i;
3310 for_each_bit(i, state->subpass->view_mask) {
3311 radv_emit_view_index(cmd_buffer, i);
3312
3313 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3314 info->indexed,
3315 info->count,
3316 count_va,
3317 info->stride);
3318 }
3319 }
3320 } else {
3321 assert(state->pipeline->graphics.vtx_base_sgpr);
3322
3323 if (info->vertex_offset != state->last_vertex_offset ||
3324 info->first_instance != state->last_first_instance) {
3325 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3326 state->pipeline->graphics.vtx_emit_num);
3327
3328 radeon_emit(cs, info->vertex_offset);
3329 radeon_emit(cs, info->first_instance);
3330 if (state->pipeline->graphics.vtx_emit_num == 3)
3331 radeon_emit(cs, 0);
3332 state->last_first_instance = info->first_instance;
3333 state->last_vertex_offset = info->vertex_offset;
3334 }
3335
3336 if (state->last_num_instances != info->instance_count) {
3337 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3338 radeon_emit(cs, info->instance_count);
3339 state->last_num_instances = info->instance_count;
3340 }
3341
3342 if (info->indexed) {
3343 int index_size = state->index_type ? 4 : 2;
3344 uint64_t index_va;
3345
3346 index_va = state->index_va;
3347 index_va += info->first_index * index_size;
3348
3349 if (!state->subpass->view_mask) {
3350 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3351 index_va,
3352 info->count);
3353 } else {
3354 unsigned i;
3355 for_each_bit(i, state->subpass->view_mask) {
3356 radv_emit_view_index(cmd_buffer, i);
3357
3358 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3359 index_va,
3360 info->count);
3361 }
3362 }
3363 } else {
3364 if (!state->subpass->view_mask) {
3365 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3366 } else {
3367 unsigned i;
3368 for_each_bit(i, state->subpass->view_mask) {
3369 radv_emit_view_index(cmd_buffer, i);
3370
3371 radv_cs_emit_draw_packet(cmd_buffer,
3372 info->count);
3373 }
3374 }
3375 }
3376 }
3377 }
3378
3379 /*
3380 * Vega and raven have a bug which triggers if there are multiple context
3381 * register contexts active at the same time with different scissor values.
3382 *
3383 * There are two possible workarounds:
3384 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3385 * there is only ever 1 active set of scissor values at the same time.
3386 *
3387 * 2) Whenever the hardware switches contexts we have to set the scissor
3388 * registers again even if it is a noop. That way the new context gets
3389 * the correct scissor values.
3390 *
3391 * This implements option 2. radv_need_late_scissor_emission needs to
3392 * return true on affected HW if radv_emit_all_graphics_states sets
3393 * any context registers.
3394 */
3395 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3396 bool indexed_draw)
3397 {
3398 struct radv_cmd_state *state = &cmd_buffer->state;
3399
3400 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3401 return false;
3402
3403 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3404
3405 /* Index & Vertex buffer don't change context regs, and pipeline is handled later. */
3406 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER | RADV_CMD_DIRTY_VERTEX_BUFFER | RADV_CMD_DIRTY_PIPELINE);
3407
3408 /* Assume all state changes except these two can imply context rolls. */
3409 if (cmd_buffer->state.dirty & used_states)
3410 return true;
3411
3412 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3413 return true;
3414
3415 if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3416 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3417 return true;
3418
3419 return false;
3420 }
3421
3422 static void
3423 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3424 const struct radv_draw_info *info)
3425 {
3426 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3427
3428 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3429 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3430 radv_emit_rbplus_state(cmd_buffer);
3431
3432 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3433 radv_emit_graphics_pipeline(cmd_buffer);
3434
3435 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3436 radv_emit_framebuffer_state(cmd_buffer);
3437
3438 if (info->indexed) {
3439 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3440 radv_emit_index_buffer(cmd_buffer);
3441 } else {
3442 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3443 * so the state must be re-emitted before the next indexed
3444 * draw.
3445 */
3446 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3447 cmd_buffer->state.last_index_type = -1;
3448 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3449 }
3450 }
3451
3452 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3453
3454 radv_emit_draw_registers(cmd_buffer, info->indexed,
3455 info->instance_count > 1, info->indirect,
3456 info->indirect ? 0 : info->count);
3457
3458 if (late_scissor_emission)
3459 radv_emit_scissor(cmd_buffer);
3460 }
3461
3462 static void
3463 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3464 const struct radv_draw_info *info)
3465 {
3466 bool has_prefetch =
3467 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3468 bool pipeline_is_dirty =
3469 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3470 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3471
3472 MAYBE_UNUSED unsigned cdw_max =
3473 radeon_check_space(cmd_buffer->device->ws,
3474 cmd_buffer->cs, 4096);
3475
3476 /* Use optimal packet order based on whether we need to sync the
3477 * pipeline.
3478 */
3479 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3480 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3481 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3482 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3483 /* If we have to wait for idle, set all states first, so that
3484 * all SET packets are processed in parallel with previous draw
3485 * calls. Then upload descriptors, set shader pointers, and
3486 * draw, and prefetch at the end. This ensures that the time
3487 * the CUs are idle is very short. (there are only SET_SH
3488 * packets between the wait and the draw)
3489 */
3490 radv_emit_all_graphics_states(cmd_buffer, info);
3491 si_emit_cache_flush(cmd_buffer);
3492 /* <-- CUs are idle here --> */
3493
3494 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3495
3496 radv_emit_draw_packets(cmd_buffer, info);
3497 /* <-- CUs are busy here --> */
3498
3499 /* Start prefetches after the draw has been started. Both will
3500 * run in parallel, but starting the draw first is more
3501 * important.
3502 */
3503 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3504 radv_emit_prefetch_L2(cmd_buffer,
3505 cmd_buffer->state.pipeline, false);
3506 }
3507 } else {
3508 /* If we don't wait for idle, start prefetches first, then set
3509 * states, and draw at the end.
3510 */
3511 si_emit_cache_flush(cmd_buffer);
3512
3513 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3514 /* Only prefetch the vertex shader and VBO descriptors
3515 * in order to start the draw as soon as possible.
3516 */
3517 radv_emit_prefetch_L2(cmd_buffer,
3518 cmd_buffer->state.pipeline, true);
3519 }
3520
3521 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3522
3523 radv_emit_all_graphics_states(cmd_buffer, info);
3524 radv_emit_draw_packets(cmd_buffer, info);
3525
3526 /* Prefetch the remaining shaders after the draw has been
3527 * started.
3528 */
3529 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3530 radv_emit_prefetch_L2(cmd_buffer,
3531 cmd_buffer->state.pipeline, false);
3532 }
3533 }
3534
3535 assert(cmd_buffer->cs->cdw <= cdw_max);
3536 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3537 }
3538
3539 void radv_CmdDraw(
3540 VkCommandBuffer commandBuffer,
3541 uint32_t vertexCount,
3542 uint32_t instanceCount,
3543 uint32_t firstVertex,
3544 uint32_t firstInstance)
3545 {
3546 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3547 struct radv_draw_info info = {};
3548
3549 info.count = vertexCount;
3550 info.instance_count = instanceCount;
3551 info.first_instance = firstInstance;
3552 info.vertex_offset = firstVertex;
3553
3554 radv_draw(cmd_buffer, &info);
3555 }
3556
3557 void radv_CmdDrawIndexed(
3558 VkCommandBuffer commandBuffer,
3559 uint32_t indexCount,
3560 uint32_t instanceCount,
3561 uint32_t firstIndex,
3562 int32_t vertexOffset,
3563 uint32_t firstInstance)
3564 {
3565 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3566 struct radv_draw_info info = {};
3567
3568 info.indexed = true;
3569 info.count = indexCount;
3570 info.instance_count = instanceCount;
3571 info.first_index = firstIndex;
3572 info.vertex_offset = vertexOffset;
3573 info.first_instance = firstInstance;
3574
3575 radv_draw(cmd_buffer, &info);
3576 }
3577
3578 void radv_CmdDrawIndirect(
3579 VkCommandBuffer commandBuffer,
3580 VkBuffer _buffer,
3581 VkDeviceSize offset,
3582 uint32_t drawCount,
3583 uint32_t stride)
3584 {
3585 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3586 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3587 struct radv_draw_info info = {};
3588
3589 info.count = drawCount;
3590 info.indirect = buffer;
3591 info.indirect_offset = offset;
3592 info.stride = stride;
3593
3594 radv_draw(cmd_buffer, &info);
3595 }
3596
3597 void radv_CmdDrawIndexedIndirect(
3598 VkCommandBuffer commandBuffer,
3599 VkBuffer _buffer,
3600 VkDeviceSize offset,
3601 uint32_t drawCount,
3602 uint32_t stride)
3603 {
3604 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3605 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3606 struct radv_draw_info info = {};
3607
3608 info.indexed = true;
3609 info.count = drawCount;
3610 info.indirect = buffer;
3611 info.indirect_offset = offset;
3612 info.stride = stride;
3613
3614 radv_draw(cmd_buffer, &info);
3615 }
3616
3617 void radv_CmdDrawIndirectCountAMD(
3618 VkCommandBuffer commandBuffer,
3619 VkBuffer _buffer,
3620 VkDeviceSize offset,
3621 VkBuffer _countBuffer,
3622 VkDeviceSize countBufferOffset,
3623 uint32_t maxDrawCount,
3624 uint32_t stride)
3625 {
3626 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3627 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3628 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3629 struct radv_draw_info info = {};
3630
3631 info.count = maxDrawCount;
3632 info.indirect = buffer;
3633 info.indirect_offset = offset;
3634 info.count_buffer = count_buffer;
3635 info.count_buffer_offset = countBufferOffset;
3636 info.stride = stride;
3637
3638 radv_draw(cmd_buffer, &info);
3639 }
3640
3641 void radv_CmdDrawIndexedIndirectCountAMD(
3642 VkCommandBuffer commandBuffer,
3643 VkBuffer _buffer,
3644 VkDeviceSize offset,
3645 VkBuffer _countBuffer,
3646 VkDeviceSize countBufferOffset,
3647 uint32_t maxDrawCount,
3648 uint32_t stride)
3649 {
3650 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3651 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3652 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3653 struct radv_draw_info info = {};
3654
3655 info.indexed = true;
3656 info.count = maxDrawCount;
3657 info.indirect = buffer;
3658 info.indirect_offset = offset;
3659 info.count_buffer = count_buffer;
3660 info.count_buffer_offset = countBufferOffset;
3661 info.stride = stride;
3662
3663 radv_draw(cmd_buffer, &info);
3664 }
3665
3666 void radv_CmdDrawIndirectCountKHR(
3667 VkCommandBuffer commandBuffer,
3668 VkBuffer _buffer,
3669 VkDeviceSize offset,
3670 VkBuffer _countBuffer,
3671 VkDeviceSize countBufferOffset,
3672 uint32_t maxDrawCount,
3673 uint32_t stride)
3674 {
3675 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3676 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3677 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3678 struct radv_draw_info info = {};
3679
3680 info.count = maxDrawCount;
3681 info.indirect = buffer;
3682 info.indirect_offset = offset;
3683 info.count_buffer = count_buffer;
3684 info.count_buffer_offset = countBufferOffset;
3685 info.stride = stride;
3686
3687 radv_draw(cmd_buffer, &info);
3688 }
3689
3690 void radv_CmdDrawIndexedIndirectCountKHR(
3691 VkCommandBuffer commandBuffer,
3692 VkBuffer _buffer,
3693 VkDeviceSize offset,
3694 VkBuffer _countBuffer,
3695 VkDeviceSize countBufferOffset,
3696 uint32_t maxDrawCount,
3697 uint32_t stride)
3698 {
3699 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3700 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3701 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3702 struct radv_draw_info info = {};
3703
3704 info.indexed = true;
3705 info.count = maxDrawCount;
3706 info.indirect = buffer;
3707 info.indirect_offset = offset;
3708 info.count_buffer = count_buffer;
3709 info.count_buffer_offset = countBufferOffset;
3710 info.stride = stride;
3711
3712 radv_draw(cmd_buffer, &info);
3713 }
3714
3715 struct radv_dispatch_info {
3716 /**
3717 * Determine the layout of the grid (in block units) to be used.
3718 */
3719 uint32_t blocks[3];
3720
3721 /**
3722 * A starting offset for the grid. If unaligned is set, the offset
3723 * must still be aligned.
3724 */
3725 uint32_t offsets[3];
3726 /**
3727 * Whether it's an unaligned compute dispatch.
3728 */
3729 bool unaligned;
3730
3731 /**
3732 * Indirect compute parameters resource.
3733 */
3734 struct radv_buffer *indirect;
3735 uint64_t indirect_offset;
3736 };
3737
3738 static void
3739 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3740 const struct radv_dispatch_info *info)
3741 {
3742 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3743 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3744 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3745 struct radeon_winsys *ws = cmd_buffer->device->ws;
3746 bool predicating = cmd_buffer->state.predicating;
3747 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3748 struct radv_userdata_info *loc;
3749
3750 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3751 AC_UD_CS_GRID_SIZE);
3752
3753 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3754
3755 if (info->indirect) {
3756 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3757
3758 va += info->indirect->offset + info->indirect_offset;
3759
3760 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3761
3762 if (loc->sgpr_idx != -1) {
3763 for (unsigned i = 0; i < 3; ++i) {
3764 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3765 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3766 COPY_DATA_DST_SEL(COPY_DATA_REG));
3767 radeon_emit(cs, (va + 4 * i));
3768 radeon_emit(cs, (va + 4 * i) >> 32);
3769 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3770 + loc->sgpr_idx * 4) >> 2) + i);
3771 radeon_emit(cs, 0);
3772 }
3773 }
3774
3775 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3776 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
3777 PKT3_SHADER_TYPE_S(1));
3778 radeon_emit(cs, va);
3779 radeon_emit(cs, va >> 32);
3780 radeon_emit(cs, dispatch_initiator);
3781 } else {
3782 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3783 PKT3_SHADER_TYPE_S(1));
3784 radeon_emit(cs, 1);
3785 radeon_emit(cs, va);
3786 radeon_emit(cs, va >> 32);
3787
3788 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
3789 PKT3_SHADER_TYPE_S(1));
3790 radeon_emit(cs, 0);
3791 radeon_emit(cs, dispatch_initiator);
3792 }
3793 } else {
3794 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3795 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3796
3797 if (info->unaligned) {
3798 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3799 unsigned remainder[3];
3800
3801 /* If aligned, these should be an entire block size,
3802 * not 0.
3803 */
3804 remainder[0] = blocks[0] + cs_block_size[0] -
3805 align_u32_npot(blocks[0], cs_block_size[0]);
3806 remainder[1] = blocks[1] + cs_block_size[1] -
3807 align_u32_npot(blocks[1], cs_block_size[1]);
3808 remainder[2] = blocks[2] + cs_block_size[2] -
3809 align_u32_npot(blocks[2], cs_block_size[2]);
3810
3811 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3812 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3813 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3814
3815 for(unsigned i = 0; i < 3; ++i) {
3816 assert(offsets[i] % cs_block_size[i] == 0);
3817 offsets[i] /= cs_block_size[i];
3818 }
3819
3820 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3821 radeon_emit(cs,
3822 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3823 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3824 radeon_emit(cs,
3825 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3826 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3827 radeon_emit(cs,
3828 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3829 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3830
3831 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3832 }
3833
3834 if (loc->sgpr_idx != -1) {
3835 assert(!loc->indirect);
3836 assert(loc->num_sgprs == 3);
3837
3838 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3839 loc->sgpr_idx * 4, 3);
3840 radeon_emit(cs, blocks[0]);
3841 radeon_emit(cs, blocks[1]);
3842 radeon_emit(cs, blocks[2]);
3843 }
3844
3845 if (offsets[0] || offsets[1] || offsets[2]) {
3846 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3847 radeon_emit(cs, offsets[0]);
3848 radeon_emit(cs, offsets[1]);
3849 radeon_emit(cs, offsets[2]);
3850
3851 /* The blocks in the packet are not counts but end values. */
3852 for (unsigned i = 0; i < 3; ++i)
3853 blocks[i] += offsets[i];
3854 } else {
3855 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3856 }
3857
3858 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
3859 PKT3_SHADER_TYPE_S(1));
3860 radeon_emit(cs, blocks[0]);
3861 radeon_emit(cs, blocks[1]);
3862 radeon_emit(cs, blocks[2]);
3863 radeon_emit(cs, dispatch_initiator);
3864 }
3865
3866 assert(cmd_buffer->cs->cdw <= cdw_max);
3867 }
3868
3869 static void
3870 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3871 {
3872 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3873 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3874 }
3875
3876 static void
3877 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3878 const struct radv_dispatch_info *info)
3879 {
3880 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3881 bool has_prefetch =
3882 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3883 bool pipeline_is_dirty = pipeline &&
3884 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3885
3886 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3887 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3888 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3889 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3890 /* If we have to wait for idle, set all states first, so that
3891 * all SET packets are processed in parallel with previous draw
3892 * calls. Then upload descriptors, set shader pointers, and
3893 * dispatch, and prefetch at the end. This ensures that the
3894 * time the CUs are idle is very short. (there are only SET_SH
3895 * packets between the wait and the draw)
3896 */
3897 radv_emit_compute_pipeline(cmd_buffer);
3898 si_emit_cache_flush(cmd_buffer);
3899 /* <-- CUs are idle here --> */
3900
3901 radv_upload_compute_shader_descriptors(cmd_buffer);
3902
3903 radv_emit_dispatch_packets(cmd_buffer, info);
3904 /* <-- CUs are busy here --> */
3905
3906 /* Start prefetches after the dispatch has been started. Both
3907 * will run in parallel, but starting the dispatch first is
3908 * more important.
3909 */
3910 if (has_prefetch && pipeline_is_dirty) {
3911 radv_emit_shader_prefetch(cmd_buffer,
3912 pipeline->shaders[MESA_SHADER_COMPUTE]);
3913 }
3914 } else {
3915 /* If we don't wait for idle, start prefetches first, then set
3916 * states, and dispatch at the end.
3917 */
3918 si_emit_cache_flush(cmd_buffer);
3919
3920 if (has_prefetch && pipeline_is_dirty) {
3921 radv_emit_shader_prefetch(cmd_buffer,
3922 pipeline->shaders[MESA_SHADER_COMPUTE]);
3923 }
3924
3925 radv_upload_compute_shader_descriptors(cmd_buffer);
3926
3927 radv_emit_compute_pipeline(cmd_buffer);
3928 radv_emit_dispatch_packets(cmd_buffer, info);
3929 }
3930
3931 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3932 }
3933
3934 void radv_CmdDispatchBase(
3935 VkCommandBuffer commandBuffer,
3936 uint32_t base_x,
3937 uint32_t base_y,
3938 uint32_t base_z,
3939 uint32_t x,
3940 uint32_t y,
3941 uint32_t z)
3942 {
3943 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3944 struct radv_dispatch_info info = {};
3945
3946 info.blocks[0] = x;
3947 info.blocks[1] = y;
3948 info.blocks[2] = z;
3949
3950 info.offsets[0] = base_x;
3951 info.offsets[1] = base_y;
3952 info.offsets[2] = base_z;
3953 radv_dispatch(cmd_buffer, &info);
3954 }
3955
3956 void radv_CmdDispatch(
3957 VkCommandBuffer commandBuffer,
3958 uint32_t x,
3959 uint32_t y,
3960 uint32_t z)
3961 {
3962 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3963 }
3964
3965 void radv_CmdDispatchIndirect(
3966 VkCommandBuffer commandBuffer,
3967 VkBuffer _buffer,
3968 VkDeviceSize offset)
3969 {
3970 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3971 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3972 struct radv_dispatch_info info = {};
3973
3974 info.indirect = buffer;
3975 info.indirect_offset = offset;
3976
3977 radv_dispatch(cmd_buffer, &info);
3978 }
3979
3980 void radv_unaligned_dispatch(
3981 struct radv_cmd_buffer *cmd_buffer,
3982 uint32_t x,
3983 uint32_t y,
3984 uint32_t z)
3985 {
3986 struct radv_dispatch_info info = {};
3987
3988 info.blocks[0] = x;
3989 info.blocks[1] = y;
3990 info.blocks[2] = z;
3991 info.unaligned = 1;
3992
3993 radv_dispatch(cmd_buffer, &info);
3994 }
3995
3996 void radv_CmdEndRenderPass(
3997 VkCommandBuffer commandBuffer)
3998 {
3999 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4000
4001 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4002
4003 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4004
4005 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
4006 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
4007 radv_handle_subpass_image_transition(cmd_buffer,
4008 (struct radv_subpass_attachment){i, layout});
4009 }
4010
4011 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4012
4013 cmd_buffer->state.pass = NULL;
4014 cmd_buffer->state.subpass = NULL;
4015 cmd_buffer->state.attachments = NULL;
4016 cmd_buffer->state.framebuffer = NULL;
4017 }
4018
4019 void radv_CmdEndRenderPass2KHR(
4020 VkCommandBuffer commandBuffer,
4021 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4022 {
4023 radv_CmdEndRenderPass(commandBuffer);
4024 }
4025
4026 /*
4027 * For HTILE we have the following interesting clear words:
4028 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4029 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4030 * 0xfffffff0: Clear depth to 1.0
4031 * 0x00000000: Clear depth to 0.0
4032 */
4033 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4034 struct radv_image *image,
4035 const VkImageSubresourceRange *range,
4036 uint32_t clear_word)
4037 {
4038 assert(range->baseMipLevel == 0);
4039 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4040 unsigned layer_count = radv_get_layerCount(image, range);
4041 uint64_t size = image->surface.htile_slice_size * layer_count;
4042 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4043 uint64_t offset = image->offset + image->htile_offset +
4044 image->surface.htile_slice_size * range->baseArrayLayer;
4045 struct radv_cmd_state *state = &cmd_buffer->state;
4046 VkClearDepthStencilValue value = {};
4047
4048 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4049 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4050
4051 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4052 size, clear_word);
4053
4054 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4055
4056 if (vk_format_is_stencil(image->vk_format))
4057 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4058
4059 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4060 }
4061
4062 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4063 struct radv_image *image,
4064 VkImageLayout src_layout,
4065 VkImageLayout dst_layout,
4066 unsigned src_queue_mask,
4067 unsigned dst_queue_mask,
4068 const VkImageSubresourceRange *range,
4069 VkImageAspectFlags pending_clears)
4070 {
4071 if (!radv_image_has_htile(image))
4072 return;
4073
4074 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4075 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4076 /* TODO: merge with the clear if applicable */
4077 radv_initialize_htile(cmd_buffer, image, range, 0);
4078 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4079 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4080 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4081 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4082 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4083 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4084 VkImageSubresourceRange local_range = *range;
4085 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4086 local_range.baseMipLevel = 0;
4087 local_range.levelCount = 1;
4088
4089 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4090 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4091
4092 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4093
4094 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4095 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4096 }
4097 }
4098
4099 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4100 struct radv_image *image, uint32_t value)
4101 {
4102 struct radv_cmd_state *state = &cmd_buffer->state;
4103
4104 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4105 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4106
4107 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4108
4109 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4110 }
4111
4112 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4113 struct radv_image *image, uint32_t value)
4114 {
4115 struct radv_cmd_state *state = &cmd_buffer->state;
4116
4117 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4118 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4119
4120 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4121
4122 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4123 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4124 }
4125
4126 /**
4127 * Initialize DCC/FMASK/CMASK metadata for a color image.
4128 */
4129 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4130 struct radv_image *image,
4131 VkImageLayout src_layout,
4132 VkImageLayout dst_layout,
4133 unsigned src_queue_mask,
4134 unsigned dst_queue_mask)
4135 {
4136 if (radv_image_has_cmask(image)) {
4137 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4138
4139 /* TODO: clarify this. */
4140 if (radv_image_has_fmask(image)) {
4141 value = 0xccccccccu;
4142 }
4143
4144 radv_initialise_cmask(cmd_buffer, image, value);
4145 }
4146
4147 if (radv_image_has_dcc(image)) {
4148 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4149 bool need_decompress_pass = false;
4150
4151 if (radv_layout_dcc_compressed(image, dst_layout,
4152 dst_queue_mask)) {
4153 value = 0x20202020u;
4154 need_decompress_pass = true;
4155 }
4156
4157 radv_initialize_dcc(cmd_buffer, image, value);
4158
4159 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, image,
4160 need_decompress_pass);
4161 }
4162
4163 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4164 uint32_t color_values[2] = {};
4165 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4166 }
4167 }
4168
4169 /**
4170 * Handle color image transitions for DCC/FMASK/CMASK.
4171 */
4172 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4173 struct radv_image *image,
4174 VkImageLayout src_layout,
4175 VkImageLayout dst_layout,
4176 unsigned src_queue_mask,
4177 unsigned dst_queue_mask,
4178 const VkImageSubresourceRange *range)
4179 {
4180 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4181 radv_init_color_image_metadata(cmd_buffer, image,
4182 src_layout, dst_layout,
4183 src_queue_mask, dst_queue_mask);
4184 return;
4185 }
4186
4187 if (radv_image_has_dcc(image)) {
4188 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4189 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4190 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4191 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4192 radv_decompress_dcc(cmd_buffer, image, range);
4193 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4194 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4195 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4196 }
4197 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4198 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4199 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4200 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4201 }
4202 }
4203 }
4204
4205 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4206 struct radv_image *image,
4207 VkImageLayout src_layout,
4208 VkImageLayout dst_layout,
4209 uint32_t src_family,
4210 uint32_t dst_family,
4211 const VkImageSubresourceRange *range,
4212 VkImageAspectFlags pending_clears)
4213 {
4214 if (image->exclusive && src_family != dst_family) {
4215 /* This is an acquire or a release operation and there will be
4216 * a corresponding release/acquire. Do the transition in the
4217 * most flexible queue. */
4218
4219 assert(src_family == cmd_buffer->queue_family_index ||
4220 dst_family == cmd_buffer->queue_family_index);
4221
4222 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4223 return;
4224
4225 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4226 (src_family == RADV_QUEUE_GENERAL ||
4227 dst_family == RADV_QUEUE_GENERAL))
4228 return;
4229 }
4230
4231 unsigned src_queue_mask =
4232 radv_image_queue_family_mask(image, src_family,
4233 cmd_buffer->queue_family_index);
4234 unsigned dst_queue_mask =
4235 radv_image_queue_family_mask(image, dst_family,
4236 cmd_buffer->queue_family_index);
4237
4238 if (vk_format_is_depth(image->vk_format)) {
4239 radv_handle_depth_image_transition(cmd_buffer, image,
4240 src_layout, dst_layout,
4241 src_queue_mask, dst_queue_mask,
4242 range, pending_clears);
4243 } else {
4244 radv_handle_color_image_transition(cmd_buffer, image,
4245 src_layout, dst_layout,
4246 src_queue_mask, dst_queue_mask,
4247 range);
4248 }
4249 }
4250
4251 struct radv_barrier_info {
4252 uint32_t eventCount;
4253 const VkEvent *pEvents;
4254 VkPipelineStageFlags srcStageMask;
4255 };
4256
4257 static void
4258 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4259 uint32_t memoryBarrierCount,
4260 const VkMemoryBarrier *pMemoryBarriers,
4261 uint32_t bufferMemoryBarrierCount,
4262 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4263 uint32_t imageMemoryBarrierCount,
4264 const VkImageMemoryBarrier *pImageMemoryBarriers,
4265 const struct radv_barrier_info *info)
4266 {
4267 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4268 enum radv_cmd_flush_bits src_flush_bits = 0;
4269 enum radv_cmd_flush_bits dst_flush_bits = 0;
4270
4271 for (unsigned i = 0; i < info->eventCount; ++i) {
4272 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4273 uint64_t va = radv_buffer_get_va(event->bo);
4274
4275 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4276
4277 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4278
4279 si_emit_wait_fence(cs, va, 1, 0xffffffff);
4280 assert(cmd_buffer->cs->cdw <= cdw_max);
4281 }
4282
4283 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4284 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4285 NULL);
4286 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4287 NULL);
4288 }
4289
4290 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4291 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4292 NULL);
4293 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4294 NULL);
4295 }
4296
4297 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4298 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4299
4300 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4301 image);
4302 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4303 image);
4304 }
4305
4306 radv_stage_flush(cmd_buffer, info->srcStageMask);
4307 cmd_buffer->state.flush_bits |= src_flush_bits;
4308
4309 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4310 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4311 radv_handle_image_transition(cmd_buffer, image,
4312 pImageMemoryBarriers[i].oldLayout,
4313 pImageMemoryBarriers[i].newLayout,
4314 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4315 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4316 &pImageMemoryBarriers[i].subresourceRange,
4317 0);
4318 }
4319
4320 /* Make sure CP DMA is idle because the driver might have performed a
4321 * DMA operation for copying or filling buffers/images.
4322 */
4323 si_cp_dma_wait_for_idle(cmd_buffer);
4324
4325 cmd_buffer->state.flush_bits |= dst_flush_bits;
4326 }
4327
4328 void radv_CmdPipelineBarrier(
4329 VkCommandBuffer commandBuffer,
4330 VkPipelineStageFlags srcStageMask,
4331 VkPipelineStageFlags destStageMask,
4332 VkBool32 byRegion,
4333 uint32_t memoryBarrierCount,
4334 const VkMemoryBarrier* pMemoryBarriers,
4335 uint32_t bufferMemoryBarrierCount,
4336 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4337 uint32_t imageMemoryBarrierCount,
4338 const VkImageMemoryBarrier* pImageMemoryBarriers)
4339 {
4340 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4341 struct radv_barrier_info info;
4342
4343 info.eventCount = 0;
4344 info.pEvents = NULL;
4345 info.srcStageMask = srcStageMask;
4346
4347 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4348 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4349 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4350 }
4351
4352
4353 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4354 struct radv_event *event,
4355 VkPipelineStageFlags stageMask,
4356 unsigned value)
4357 {
4358 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4359 uint64_t va = radv_buffer_get_va(event->bo);
4360
4361 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4362
4363 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4364
4365 /* Flags that only require a top-of-pipe event. */
4366 VkPipelineStageFlags top_of_pipe_flags =
4367 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4368
4369 /* Flags that only require a post-index-fetch event. */
4370 VkPipelineStageFlags post_index_fetch_flags =
4371 top_of_pipe_flags |
4372 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4373 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4374
4375 /* Make sure CP DMA is idle because the driver might have performed a
4376 * DMA operation for copying or filling buffers/images.
4377 */
4378 si_cp_dma_wait_for_idle(cmd_buffer);
4379
4380 /* TODO: Emit EOS events for syncing PS/CS stages. */
4381
4382 if (!(stageMask & ~top_of_pipe_flags)) {
4383 /* Just need to sync the PFP engine. */
4384 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4385 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4386 S_370_WR_CONFIRM(1) |
4387 S_370_ENGINE_SEL(V_370_PFP));
4388 radeon_emit(cs, va);
4389 radeon_emit(cs, va >> 32);
4390 radeon_emit(cs, value);
4391 } else if (!(stageMask & ~post_index_fetch_flags)) {
4392 /* Sync ME because PFP reads index and indirect buffers. */
4393 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4394 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4395 S_370_WR_CONFIRM(1) |
4396 S_370_ENGINE_SEL(V_370_ME));
4397 radeon_emit(cs, va);
4398 radeon_emit(cs, va >> 32);
4399 radeon_emit(cs, value);
4400 } else {
4401 /* Otherwise, sync all prior GPU work using an EOP event. */
4402 si_cs_emit_write_event_eop(cs,
4403 cmd_buffer->device->physical_device->rad_info.chip_class,
4404 radv_cmd_buffer_uses_mec(cmd_buffer),
4405 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4406 EOP_DATA_SEL_VALUE_32BIT, va, 2, value,
4407 cmd_buffer->gfx9_eop_bug_va);
4408 }
4409
4410 assert(cmd_buffer->cs->cdw <= cdw_max);
4411 }
4412
4413 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4414 VkEvent _event,
4415 VkPipelineStageFlags stageMask)
4416 {
4417 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4418 RADV_FROM_HANDLE(radv_event, event, _event);
4419
4420 write_event(cmd_buffer, event, stageMask, 1);
4421 }
4422
4423 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4424 VkEvent _event,
4425 VkPipelineStageFlags stageMask)
4426 {
4427 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4428 RADV_FROM_HANDLE(radv_event, event, _event);
4429
4430 write_event(cmd_buffer, event, stageMask, 0);
4431 }
4432
4433 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4434 uint32_t eventCount,
4435 const VkEvent* pEvents,
4436 VkPipelineStageFlags srcStageMask,
4437 VkPipelineStageFlags dstStageMask,
4438 uint32_t memoryBarrierCount,
4439 const VkMemoryBarrier* pMemoryBarriers,
4440 uint32_t bufferMemoryBarrierCount,
4441 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4442 uint32_t imageMemoryBarrierCount,
4443 const VkImageMemoryBarrier* pImageMemoryBarriers)
4444 {
4445 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4446 struct radv_barrier_info info;
4447
4448 info.eventCount = eventCount;
4449 info.pEvents = pEvents;
4450 info.srcStageMask = 0;
4451
4452 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4453 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4454 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4455 }
4456
4457
4458 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4459 uint32_t deviceMask)
4460 {
4461 /* No-op */
4462 }
4463
4464 /* VK_EXT_conditional_rendering */
4465 void radv_CmdBeginConditionalRenderingEXT(
4466 VkCommandBuffer commandBuffer,
4467 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4468 {
4469 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4470 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4471 bool draw_visible = true;
4472 uint64_t va;
4473
4474 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4475
4476 /* By default, if the 32-bit value at offset in buffer memory is zero,
4477 * then the rendering commands are discarded, otherwise they are
4478 * executed as normal. If the inverted flag is set, all commands are
4479 * discarded if the value is non zero.
4480 */
4481 if (pConditionalRenderingBegin->flags &
4482 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4483 draw_visible = false;
4484 }
4485
4486 /* Enable predication for this command buffer. */
4487 si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4488 cmd_buffer->state.predicating = true;
4489
4490 /* Store conditional rendering user info. */
4491 cmd_buffer->state.predication_type = draw_visible;
4492 cmd_buffer->state.predication_va = va;
4493 }
4494
4495 void radv_CmdEndConditionalRenderingEXT(
4496 VkCommandBuffer commandBuffer)
4497 {
4498 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4499
4500 /* Disable predication for this command buffer. */
4501 si_emit_set_predication_state(cmd_buffer, false, 0);
4502 cmd_buffer->state.predicating = false;
4503
4504 /* Reset conditional rendering user info. */
4505 cmd_buffer->state.predication_type = -1;
4506 cmd_buffer->state.predication_va = 0;
4507 }