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radv: move assert down in radv_bind_descriptor_set
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "gfx9d.h"
33 #include "vk_format.h"
34 #include "radv_meta.h"
35
36 #include "ac_debug.h"
37
38 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
39 struct radv_image *image,
40 VkImageLayout src_layout,
41 VkImageLayout dst_layout,
42 uint32_t src_family,
43 uint32_t dst_family,
44 const VkImageSubresourceRange *range,
45 VkImageAspectFlags pending_clears);
46
47 const struct radv_dynamic_state default_dynamic_state = {
48 .viewport = {
49 .count = 0,
50 },
51 .scissor = {
52 .count = 0,
53 },
54 .line_width = 1.0f,
55 .depth_bias = {
56 .bias = 0.0f,
57 .clamp = 0.0f,
58 .slope = 0.0f,
59 },
60 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
61 .depth_bounds = {
62 .min = 0.0f,
63 .max = 1.0f,
64 },
65 .stencil_compare_mask = {
66 .front = ~0u,
67 .back = ~0u,
68 },
69 .stencil_write_mask = {
70 .front = ~0u,
71 .back = ~0u,
72 },
73 .stencil_reference = {
74 .front = 0u,
75 .back = 0u,
76 },
77 };
78
79 void
80 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
81 const struct radv_dynamic_state *src,
82 uint32_t copy_mask)
83 {
84 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
85 dest->viewport.count = src->viewport.count;
86 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
87 src->viewport.count);
88 }
89
90 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
91 dest->scissor.count = src->scissor.count;
92 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
93 src->scissor.count);
94 }
95
96 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
97 dest->line_width = src->line_width;
98
99 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
100 dest->depth_bias = src->depth_bias;
101
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
103 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
106 dest->depth_bounds = src->depth_bounds;
107
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
109 dest->stencil_compare_mask = src->stencil_compare_mask;
110
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
112 dest->stencil_write_mask = src->stencil_write_mask;
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
115 dest->stencil_reference = src->stencil_reference;
116 }
117
118 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
119 {
120 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
121 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
122 }
123
124 enum ring_type radv_queue_family_to_ring(int f) {
125 switch (f) {
126 case RADV_QUEUE_GENERAL:
127 return RING_GFX;
128 case RADV_QUEUE_COMPUTE:
129 return RING_COMPUTE;
130 case RADV_QUEUE_TRANSFER:
131 return RING_DMA;
132 default:
133 unreachable("Unknown queue family");
134 }
135 }
136
137 static VkResult radv_create_cmd_buffer(
138 struct radv_device * device,
139 struct radv_cmd_pool * pool,
140 VkCommandBufferLevel level,
141 VkCommandBuffer* pCommandBuffer)
142 {
143 struct radv_cmd_buffer *cmd_buffer;
144 VkResult result;
145 unsigned ring;
146 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
147 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
148 if (cmd_buffer == NULL)
149 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
150
151 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
152 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
153 cmd_buffer->device = device;
154 cmd_buffer->pool = pool;
155 cmd_buffer->level = level;
156
157 if (pool) {
158 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
159 cmd_buffer->queue_family_index = pool->queue_family_index;
160
161 } else {
162 /* Init the pool_link so we can safefly call list_del when we destroy
163 * the command buffer
164 */
165 list_inithead(&cmd_buffer->pool_link);
166 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
167 }
168
169 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
170
171 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
172 if (!cmd_buffer->cs) {
173 result = VK_ERROR_OUT_OF_HOST_MEMORY;
174 goto fail;
175 }
176
177 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
178
179 cmd_buffer->upload.offset = 0;
180 cmd_buffer->upload.size = 0;
181 list_inithead(&cmd_buffer->upload.list);
182
183 return VK_SUCCESS;
184
185 fail:
186 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
187
188 return result;
189 }
190
191 static void
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
193 {
194 list_del(&cmd_buffer->pool_link);
195
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
197 &cmd_buffer->upload.list, list) {
198 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
199 list_del(&up->list);
200 free(up);
201 }
202
203 if (cmd_buffer->upload.upload_bo)
204 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
205 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
206 free(cmd_buffer->push_descriptors.set.mapped_ptr);
207 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
208 }
209
210 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
211 {
212
213 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
214
215 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
216 &cmd_buffer->upload.list, list) {
217 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
218 list_del(&up->list);
219 free(up);
220 }
221
222 cmd_buffer->scratch_size_needed = 0;
223 cmd_buffer->compute_scratch_size_needed = 0;
224 cmd_buffer->esgs_ring_size_needed = 0;
225 cmd_buffer->gsvs_ring_size_needed = 0;
226 cmd_buffer->tess_rings_needed = false;
227 cmd_buffer->sample_positions_needed = false;
228
229 if (cmd_buffer->upload.upload_bo)
230 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
231 cmd_buffer->upload.upload_bo, 8);
232 cmd_buffer->upload.offset = 0;
233
234 cmd_buffer->record_fail = false;
235
236 cmd_buffer->ring_offsets_idx = -1;
237
238 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
239 void *fence_ptr;
240 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
241 &cmd_buffer->gfx9_fence_offset,
242 &fence_ptr);
243 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
244 }
245 }
246
247 static bool
248 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
249 uint64_t min_needed)
250 {
251 uint64_t new_size;
252 struct radeon_winsys_bo *bo;
253 struct radv_cmd_buffer_upload *upload;
254 struct radv_device *device = cmd_buffer->device;
255
256 new_size = MAX2(min_needed, 16 * 1024);
257 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
258
259 bo = device->ws->buffer_create(device->ws,
260 new_size, 4096,
261 RADEON_DOMAIN_GTT,
262 RADEON_FLAG_CPU_ACCESS);
263
264 if (!bo) {
265 cmd_buffer->record_fail = true;
266 return false;
267 }
268
269 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
270 if (cmd_buffer->upload.upload_bo) {
271 upload = malloc(sizeof(*upload));
272
273 if (!upload) {
274 cmd_buffer->record_fail = true;
275 device->ws->buffer_destroy(bo);
276 return false;
277 }
278
279 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
280 list_add(&upload->list, &cmd_buffer->upload.list);
281 }
282
283 cmd_buffer->upload.upload_bo = bo;
284 cmd_buffer->upload.size = new_size;
285 cmd_buffer->upload.offset = 0;
286 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
287
288 if (!cmd_buffer->upload.map) {
289 cmd_buffer->record_fail = true;
290 return false;
291 }
292
293 return true;
294 }
295
296 bool
297 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
298 unsigned size,
299 unsigned alignment,
300 unsigned *out_offset,
301 void **ptr)
302 {
303 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
304 if (offset + size > cmd_buffer->upload.size) {
305 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
306 return false;
307 offset = 0;
308 }
309
310 *out_offset = offset;
311 *ptr = cmd_buffer->upload.map + offset;
312
313 cmd_buffer->upload.offset = offset + size;
314 return true;
315 }
316
317 bool
318 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
319 unsigned size, unsigned alignment,
320 const void *data, unsigned *out_offset)
321 {
322 uint8_t *ptr;
323
324 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
325 out_offset, (void **)&ptr))
326 return false;
327
328 if (ptr)
329 memcpy(ptr, data, size);
330
331 return true;
332 }
333
334 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
335 {
336 struct radv_device *device = cmd_buffer->device;
337 struct radeon_winsys_cs *cs = cmd_buffer->cs;
338 uint64_t va;
339
340 if (!device->trace_bo)
341 return;
342
343 va = device->ws->buffer_get_va(device->trace_bo);
344
345 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
346
347 ++cmd_buffer->state.trace_id;
348 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
349 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
350 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
351 S_370_WR_CONFIRM(1) |
352 S_370_ENGINE_SEL(V_370_ME));
353 radeon_emit(cs, va);
354 radeon_emit(cs, va >> 32);
355 radeon_emit(cs, cmd_buffer->state.trace_id);
356 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
357 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
358 }
359
360 static void
361 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
362 struct radv_pipeline *pipeline)
363 {
364 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
365 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
366 8);
367 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
368 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
369
370 if (cmd_buffer->device->physical_device->has_rbplus) {
371 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
372 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
373 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
374 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
375 }
376 }
377
378 static void
379 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
380 struct radv_pipeline *pipeline)
381 {
382 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
383 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
384 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
385
386 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
387 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
388 }
389
390 /* 12.4 fixed-point */
391 static unsigned radv_pack_float_12p4(float x)
392 {
393 return x <= 0 ? 0 :
394 x >= 4096 ? 0xffff : x * 16;
395 }
396
397 uint32_t
398 radv_shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
399 {
400 switch (stage) {
401 case MESA_SHADER_FRAGMENT:
402 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
403 case MESA_SHADER_VERTEX:
404 if (has_tess)
405 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
406 else
407 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
408 case MESA_SHADER_GEOMETRY:
409 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
410 case MESA_SHADER_COMPUTE:
411 return R_00B900_COMPUTE_USER_DATA_0;
412 case MESA_SHADER_TESS_CTRL:
413 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
414 case MESA_SHADER_TESS_EVAL:
415 if (has_gs)
416 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
417 else
418 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
419 default:
420 unreachable("unknown shader");
421 }
422 }
423
424 struct ac_userdata_info *
425 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
426 gl_shader_stage stage,
427 int idx)
428 {
429 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
430 }
431
432 static void
433 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
434 struct radv_pipeline *pipeline,
435 gl_shader_stage stage,
436 int idx, uint64_t va)
437 {
438 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
439 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
440 if (loc->sgpr_idx == -1)
441 return;
442 assert(loc->num_sgprs == 2);
443 assert(!loc->indirect);
444 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
445 radeon_emit(cmd_buffer->cs, va);
446 radeon_emit(cmd_buffer->cs, va >> 32);
447 }
448
449 static void
450 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
451 struct radv_pipeline *pipeline)
452 {
453 int num_samples = pipeline->graphics.ms.num_samples;
454 struct radv_multisample_state *ms = &pipeline->graphics.ms;
455 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
456
457 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
458 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
459 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
460
461 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
462 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
463
464 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
465 return;
466
467 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
468 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
469 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
470
471 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
472
473 /* GFX9: Flush DFSM when the AA mode changes. */
474 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
475 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
476 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
477 }
478 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
479 uint32_t offset;
480 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
481 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
482 if (loc->sgpr_idx == -1)
483 return;
484 assert(loc->num_sgprs == 1);
485 assert(!loc->indirect);
486 switch (num_samples) {
487 default:
488 offset = 0;
489 break;
490 case 2:
491 offset = 1;
492 break;
493 case 4:
494 offset = 3;
495 break;
496 case 8:
497 offset = 7;
498 break;
499 case 16:
500 offset = 15;
501 break;
502 }
503
504 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
505 cmd_buffer->sample_positions_needed = true;
506 }
507 }
508
509 static void
510 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
511 struct radv_pipeline *pipeline)
512 {
513 struct radv_raster_state *raster = &pipeline->graphics.raster;
514
515 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
516 raster->pa_cl_clip_cntl);
517
518 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
519 raster->spi_interp_control);
520
521 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
522 unsigned tmp = (unsigned)(1.0 * 8.0);
523 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
524 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
525 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
526
527 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
528 raster->pa_su_vtx_cntl);
529
530 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
531 raster->pa_su_sc_mode_cntl);
532 }
533
534 static inline void
535 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
536 unsigned size)
537 {
538 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
539 si_cp_dma_prefetch(cmd_buffer, va, size);
540 }
541
542 static void
543 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
544 struct radv_pipeline *pipeline,
545 struct radv_shader_variant *shader,
546 struct ac_vs_output_info *outinfo)
547 {
548 struct radeon_winsys *ws = cmd_buffer->device->ws;
549 uint64_t va = ws->buffer_get_va(shader->bo);
550 unsigned export_count;
551
552 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
553 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
554
555 export_count = MAX2(1, outinfo->param_exports);
556 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
557 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
558
559 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
560 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
561 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
562 V_02870C_SPI_SHADER_4COMP :
563 V_02870C_SPI_SHADER_NONE) |
564 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
565 V_02870C_SPI_SHADER_4COMP :
566 V_02870C_SPI_SHADER_NONE) |
567 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
568 V_02870C_SPI_SHADER_4COMP :
569 V_02870C_SPI_SHADER_NONE));
570
571
572 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
573 radeon_emit(cmd_buffer->cs, va >> 8);
574 radeon_emit(cmd_buffer->cs, va >> 40);
575 radeon_emit(cmd_buffer->cs, shader->rsrc1);
576 radeon_emit(cmd_buffer->cs, shader->rsrc2);
577
578 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
579 S_028818_VTX_W0_FMT(1) |
580 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
581 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
582 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
583
584
585 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
586 pipeline->graphics.pa_cl_vs_out_cntl);
587
588 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
589 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
590 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
591 }
592
593 static void
594 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
595 struct radv_shader_variant *shader,
596 struct ac_es_output_info *outinfo)
597 {
598 struct radeon_winsys *ws = cmd_buffer->device->ws;
599 uint64_t va = ws->buffer_get_va(shader->bo);
600
601 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
602 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
603
604 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
605 outinfo->esgs_itemsize / 4);
606 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
607 radeon_emit(cmd_buffer->cs, va >> 8);
608 radeon_emit(cmd_buffer->cs, va >> 40);
609 radeon_emit(cmd_buffer->cs, shader->rsrc1);
610 radeon_emit(cmd_buffer->cs, shader->rsrc2);
611 }
612
613 static void
614 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
615 struct radv_shader_variant *shader)
616 {
617 struct radeon_winsys *ws = cmd_buffer->device->ws;
618 uint64_t va = ws->buffer_get_va(shader->bo);
619 uint32_t rsrc2 = shader->rsrc2;
620
621 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
622 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
623
624 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
625 radeon_emit(cmd_buffer->cs, va >> 8);
626 radeon_emit(cmd_buffer->cs, va >> 40);
627
628 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
629 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
630 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
631 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
632
633 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
634 radeon_emit(cmd_buffer->cs, shader->rsrc1);
635 radeon_emit(cmd_buffer->cs, rsrc2);
636 }
637
638 static void
639 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
640 struct radv_shader_variant *shader)
641 {
642 struct radeon_winsys *ws = cmd_buffer->device->ws;
643 uint64_t va = ws->buffer_get_va(shader->bo);
644
645 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
646 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
647
648 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
649 radeon_emit(cmd_buffer->cs, va >> 8);
650 radeon_emit(cmd_buffer->cs, va >> 40);
651 radeon_emit(cmd_buffer->cs, shader->rsrc1);
652 radeon_emit(cmd_buffer->cs, shader->rsrc2);
653 }
654
655 static void
656 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
657 struct radv_pipeline *pipeline)
658 {
659 struct radv_shader_variant *vs;
660
661 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
662
663 vs = pipeline->shaders[MESA_SHADER_VERTEX];
664
665 if (vs->info.vs.as_ls)
666 radv_emit_hw_ls(cmd_buffer, vs);
667 else if (vs->info.vs.as_es)
668 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
669 else
670 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
671
672 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
673 }
674
675
676 static void
677 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
678 struct radv_pipeline *pipeline)
679 {
680 if (!radv_pipeline_has_tess(pipeline))
681 return;
682
683 struct radv_shader_variant *tes, *tcs;
684
685 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
686 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
687
688 if (tes->info.tes.as_es)
689 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
690 else
691 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
692
693 radv_emit_hw_hs(cmd_buffer, tcs);
694
695 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
696 pipeline->graphics.tess.tf_param);
697
698 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
699 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
700 pipeline->graphics.tess.ls_hs_config);
701 else
702 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
703 pipeline->graphics.tess.ls_hs_config);
704
705 struct ac_userdata_info *loc;
706
707 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
708 if (loc->sgpr_idx != -1) {
709 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
710 assert(loc->num_sgprs == 4);
711 assert(!loc->indirect);
712 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
713 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
714 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
715 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
716 pipeline->graphics.tess.num_tcs_input_cp << 26);
717 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
718 }
719
720 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
721 if (loc->sgpr_idx != -1) {
722 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
723 assert(loc->num_sgprs == 1);
724 assert(!loc->indirect);
725
726 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
727 pipeline->graphics.tess.offchip_layout);
728 }
729
730 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
731 if (loc->sgpr_idx != -1) {
732 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
733 assert(loc->num_sgprs == 1);
734 assert(!loc->indirect);
735
736 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
737 pipeline->graphics.tess.tcs_in_layout);
738 }
739 }
740
741 static void
742 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
743 struct radv_pipeline *pipeline)
744 {
745 struct radeon_winsys *ws = cmd_buffer->device->ws;
746 struct radv_shader_variant *gs;
747 uint64_t va;
748
749 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
750
751 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
752 if (!gs)
753 return;
754
755 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
756
757 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
758 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
759 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
760 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
761
762 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
763
764 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
765
766 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
767 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
768 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
769 radeon_emit(cmd_buffer->cs, 0);
770 radeon_emit(cmd_buffer->cs, 0);
771 radeon_emit(cmd_buffer->cs, 0);
772
773 uint32_t gs_num_invocations = gs->info.gs.invocations;
774 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
775 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
776 S_028B90_ENABLE(gs_num_invocations > 0));
777
778 va = ws->buffer_get_va(gs->bo);
779 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
780 radv_emit_prefetch(cmd_buffer, va, gs->code_size);
781
782 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
783 radeon_emit(cmd_buffer->cs, va >> 8);
784 radeon_emit(cmd_buffer->cs, va >> 40);
785 radeon_emit(cmd_buffer->cs, gs->rsrc1);
786 radeon_emit(cmd_buffer->cs, gs->rsrc2);
787
788 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
789
790 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
791 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
792 if (loc->sgpr_idx != -1) {
793 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
794 uint32_t num_entries = 64;
795 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
796
797 if (is_vi)
798 num_entries *= stride;
799
800 stride = S_008F04_STRIDE(stride);
801 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
802 radeon_emit(cmd_buffer->cs, stride);
803 radeon_emit(cmd_buffer->cs, num_entries);
804 }
805 }
806
807 static void
808 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
809 struct radv_pipeline *pipeline)
810 {
811 struct radeon_winsys *ws = cmd_buffer->device->ws;
812 struct radv_shader_variant *ps;
813 uint64_t va;
814 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
815 struct radv_blend_state *blend = &pipeline->graphics.blend;
816 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
817
818 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
819
820 va = ws->buffer_get_va(ps->bo);
821 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
822 radv_emit_prefetch(cmd_buffer, va, ps->code_size);
823
824 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
825 radeon_emit(cmd_buffer->cs, va >> 8);
826 radeon_emit(cmd_buffer->cs, va >> 40);
827 radeon_emit(cmd_buffer->cs, ps->rsrc1);
828 radeon_emit(cmd_buffer->cs, ps->rsrc2);
829
830 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
831 pipeline->graphics.db_shader_control);
832
833 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
834 ps->config.spi_ps_input_ena);
835
836 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
837 ps->config.spi_ps_input_addr);
838
839 if (ps->info.fs.force_persample)
840 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
841
842 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
843 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
844
845 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
846
847 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
848 pipeline->graphics.shader_z_format);
849
850 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
851
852 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
853 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
854
855 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
856 /* optimise this? */
857 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
858 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
859 }
860
861 if (pipeline->graphics.ps_input_cntl_num) {
862 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
863 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
864 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
865 }
866 }
867 }
868
869 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
870 struct radv_pipeline *pipeline)
871 {
872 uint32_t vtx_reuse_depth = 30;
873 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
874 return;
875
876 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
877 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
878 vtx_reuse_depth = 14;
879 }
880 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
881 vtx_reuse_depth);
882 }
883
884 static void
885 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
886 struct radv_pipeline *pipeline)
887 {
888 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
889 return;
890
891 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
892 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
893 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
894 radv_update_multisample_state(cmd_buffer, pipeline);
895 radv_emit_vertex_shader(cmd_buffer, pipeline);
896 radv_emit_tess_shaders(cmd_buffer, pipeline);
897 radv_emit_geometry_shader(cmd_buffer, pipeline);
898 radv_emit_fragment_shader(cmd_buffer, pipeline);
899 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
900
901 cmd_buffer->scratch_size_needed =
902 MAX2(cmd_buffer->scratch_size_needed,
903 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
904
905 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
906 S_0286E8_WAVES(pipeline->max_waves) |
907 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
908
909 if (!cmd_buffer->state.emitted_pipeline ||
910 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
911 pipeline->graphics.can_use_guardband)
912 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
913
914 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
915
916 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
917 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
918 } else {
919 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
920 }
921 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
922
923 cmd_buffer->state.emitted_pipeline = pipeline;
924 }
925
926 static void
927 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
928 {
929 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
930 cmd_buffer->state.dynamic.viewport.viewports);
931 }
932
933 static void
934 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
935 {
936 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
937 si_write_scissors(cmd_buffer->cs, 0, count,
938 cmd_buffer->state.dynamic.scissor.scissors,
939 cmd_buffer->state.dynamic.viewport.viewports,
940 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
941 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
942 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
943 }
944
945 static void
946 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
947 int index,
948 struct radv_color_buffer_info *cb)
949 {
950 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
951
952 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
953 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
954 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
955 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
956 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
957 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
958 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
959 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
960 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
961 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
962 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
963 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
964 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
965
966 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
967 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
968 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
969
970 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
971 cb->gfx9_epitch);
972 } else {
973 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
974 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
975 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
976 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
977 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
978 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
979 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
980 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
981 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
982 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
983 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
984 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
985
986 if (is_vi) { /* DCC BASE */
987 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
988 }
989 }
990 }
991
992 static void
993 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
994 struct radv_ds_buffer_info *ds,
995 struct radv_image *image,
996 VkImageLayout layout)
997 {
998 uint32_t db_z_info = ds->db_z_info;
999 uint32_t db_stencil_info = ds->db_stencil_info;
1000
1001 if (!radv_layout_has_htile(image, layout,
1002 radv_image_queue_family_mask(image,
1003 cmd_buffer->queue_family_index,
1004 cmd_buffer->queue_family_index))) {
1005 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1006 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1007 }
1008
1009 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1010
1011 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1012 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1013 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1014 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1015 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1016
1017 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1018 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1019 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1020 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1021 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1022 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1023 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1024 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1025 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1026 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1027 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1028
1029 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1030 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1031 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1032 } else {
1033 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1034
1035 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1036 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1037 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1038 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1039 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1040 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1041 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1042 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1043 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1044 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1045
1046 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1047 }
1048
1049 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1050 ds->pa_su_poly_offset_db_fmt_cntl);
1051 }
1052
1053 void
1054 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1055 struct radv_image *image,
1056 VkClearDepthStencilValue ds_clear_value,
1057 VkImageAspectFlags aspects)
1058 {
1059 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1060 va += image->offset + image->clear_value_offset;
1061 unsigned reg_offset = 0, reg_count = 0;
1062
1063 if (!image->surface.htile_size || !aspects)
1064 return;
1065
1066 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1067 ++reg_count;
1068 } else {
1069 ++reg_offset;
1070 va += 4;
1071 }
1072 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1073 ++reg_count;
1074
1075 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1076
1077 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1078 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1079 S_370_WR_CONFIRM(1) |
1080 S_370_ENGINE_SEL(V_370_PFP));
1081 radeon_emit(cmd_buffer->cs, va);
1082 radeon_emit(cmd_buffer->cs, va >> 32);
1083 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1084 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1085 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1086 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1087
1088 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1089 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1090 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1091 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1092 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1093 }
1094
1095 static void
1096 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1097 struct radv_image *image)
1098 {
1099 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1100 va += image->offset + image->clear_value_offset;
1101
1102 if (!image->surface.htile_size)
1103 return;
1104
1105 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1106
1107 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1108 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1109 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1110 COPY_DATA_COUNT_SEL);
1111 radeon_emit(cmd_buffer->cs, va);
1112 radeon_emit(cmd_buffer->cs, va >> 32);
1113 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1114 radeon_emit(cmd_buffer->cs, 0);
1115
1116 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1117 radeon_emit(cmd_buffer->cs, 0);
1118 }
1119
1120 void
1121 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1122 struct radv_image *image,
1123 int idx,
1124 uint32_t color_values[2])
1125 {
1126 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1127 va += image->offset + image->clear_value_offset;
1128
1129 if (!image->cmask.size && !image->surface.dcc_size)
1130 return;
1131
1132 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1133
1134 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1135 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1136 S_370_WR_CONFIRM(1) |
1137 S_370_ENGINE_SEL(V_370_PFP));
1138 radeon_emit(cmd_buffer->cs, va);
1139 radeon_emit(cmd_buffer->cs, va >> 32);
1140 radeon_emit(cmd_buffer->cs, color_values[0]);
1141 radeon_emit(cmd_buffer->cs, color_values[1]);
1142
1143 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1144 radeon_emit(cmd_buffer->cs, color_values[0]);
1145 radeon_emit(cmd_buffer->cs, color_values[1]);
1146 }
1147
1148 static void
1149 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1150 struct radv_image *image,
1151 int idx)
1152 {
1153 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1154 va += image->offset + image->clear_value_offset;
1155
1156 if (!image->cmask.size && !image->surface.dcc_size)
1157 return;
1158
1159 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1160 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1161
1162 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1163 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1164 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1165 COPY_DATA_COUNT_SEL);
1166 radeon_emit(cmd_buffer->cs, va);
1167 radeon_emit(cmd_buffer->cs, va >> 32);
1168 radeon_emit(cmd_buffer->cs, reg >> 2);
1169 radeon_emit(cmd_buffer->cs, 0);
1170
1171 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1172 radeon_emit(cmd_buffer->cs, 0);
1173 }
1174
1175 void
1176 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1177 {
1178 int i;
1179 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1180 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1181
1182 for (i = 0; i < subpass->color_count; ++i) {
1183 int idx = subpass->color_attachments[i].attachment;
1184 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1185
1186 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1187
1188 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1189 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1190
1191 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1192 }
1193
1194 for (i = subpass->color_count; i < 8; i++)
1195 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1196 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1197
1198 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1199 int idx = subpass->depth_stencil_attachment.attachment;
1200 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1201 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1202 struct radv_image *image = att->attachment->image;
1203 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1204 uint32_t queue_mask = radv_image_queue_family_mask(image,
1205 cmd_buffer->queue_family_index,
1206 cmd_buffer->queue_family_index);
1207 /* We currently don't support writing decompressed HTILE */
1208 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1209 radv_layout_is_htile_compressed(image, layout, queue_mask));
1210
1211 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1212
1213 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1214 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1215 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1216 }
1217 radv_load_depth_clear_regs(cmd_buffer, image);
1218 } else {
1219 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1220 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1221 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1222 }
1223 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1224 S_028208_BR_X(framebuffer->width) |
1225 S_028208_BR_Y(framebuffer->height));
1226
1227 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1228 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1229 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1230 }
1231 }
1232
1233 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1234 {
1235 uint32_t db_count_control;
1236
1237 if(!cmd_buffer->state.active_occlusion_queries) {
1238 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1239 db_count_control = 0;
1240 } else {
1241 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1242 }
1243 } else {
1244 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1245 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1246 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1247 S_028004_ZPASS_ENABLE(1) |
1248 S_028004_SLICE_EVEN_ENABLE(1) |
1249 S_028004_SLICE_ODD_ENABLE(1);
1250 } else {
1251 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1252 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1253 }
1254 }
1255
1256 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1257 }
1258
1259 static void
1260 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1261 {
1262 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1263
1264 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1265 return;
1266
1267 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1268 radv_emit_viewport(cmd_buffer);
1269
1270 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1271 radv_emit_scissor(cmd_buffer);
1272
1273 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1274 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1275 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1276 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1277 }
1278
1279 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1280 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1281 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1282 }
1283
1284 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1285 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1286 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1287 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1288 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1289 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1290 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1291 S_028430_STENCILOPVAL(1));
1292 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1293 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1294 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1295 S_028434_STENCILOPVAL_BF(1));
1296 }
1297
1298 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1299 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1300 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1301 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1302 }
1303
1304 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1305 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1306 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1307 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1308 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1309
1310 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1311 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1312 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1313 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1314 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1315 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1316 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1317 }
1318 }
1319
1320 cmd_buffer->state.dirty = 0;
1321 }
1322
1323 static void
1324 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1325 struct radv_pipeline *pipeline,
1326 int idx,
1327 uint64_t va,
1328 gl_shader_stage stage)
1329 {
1330 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1331 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1332
1333 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1334 return;
1335
1336 assert(!desc_set_loc->indirect);
1337 assert(desc_set_loc->num_sgprs == 2);
1338 radeon_set_sh_reg_seq(cmd_buffer->cs,
1339 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1340 radeon_emit(cmd_buffer->cs, va);
1341 radeon_emit(cmd_buffer->cs, va >> 32);
1342 }
1343
1344 static void
1345 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1346 VkShaderStageFlags stages,
1347 struct radv_descriptor_set *set,
1348 unsigned idx)
1349 {
1350 if (cmd_buffer->state.pipeline) {
1351 radv_foreach_stage(stage, stages) {
1352 if (cmd_buffer->state.pipeline->shaders[stage])
1353 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1354 idx, set->va,
1355 stage);
1356 }
1357 }
1358
1359 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1360 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1361 idx, set->va,
1362 MESA_SHADER_COMPUTE);
1363 }
1364
1365 static void
1366 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1367 {
1368 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1369 uint32_t *ptr = NULL;
1370 unsigned bo_offset;
1371
1372 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set->size, 32,
1373 &bo_offset,
1374 (void**) &ptr))
1375 return;
1376
1377 set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1378 set->va += bo_offset;
1379
1380 memcpy(ptr, set->mapped_ptr, set->size);
1381 }
1382
1383 static void
1384 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1385 {
1386 uint32_t size = MAX_SETS * 2 * 4;
1387 uint32_t offset;
1388 void *ptr;
1389
1390 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1391 256, &offset, &ptr))
1392 return;
1393
1394 for (unsigned i = 0; i < MAX_SETS; i++) {
1395 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1396 uint64_t set_va = 0;
1397 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1398 if (set)
1399 set_va = set->va;
1400 uptr[0] = set_va & 0xffffffff;
1401 uptr[1] = set_va >> 32;
1402 }
1403
1404 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1405 va += offset;
1406
1407 if (cmd_buffer->state.pipeline) {
1408 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1409 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1410 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1411
1412 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1413 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1414 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1415
1416 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1417 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1418 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1419
1420 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1421 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1422 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1423
1424 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1425 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1426 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1427 }
1428
1429 if (cmd_buffer->state.compute_pipeline)
1430 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1431 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1432 }
1433
1434 static void
1435 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1436 VkShaderStageFlags stages)
1437 {
1438 unsigned i;
1439
1440 if (!cmd_buffer->state.descriptors_dirty)
1441 return;
1442
1443 if (cmd_buffer->state.push_descriptors_dirty)
1444 radv_flush_push_descriptors(cmd_buffer);
1445
1446 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1447 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1448 radv_flush_indirect_descriptor_sets(cmd_buffer);
1449 }
1450
1451 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1452 cmd_buffer->cs,
1453 MAX_SETS * MESA_SHADER_STAGES * 4);
1454
1455 for (i = 0; i < MAX_SETS; i++) {
1456 if (!(cmd_buffer->state.descriptors_dirty & (1u << i)))
1457 continue;
1458 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1459 if (!set)
1460 continue;
1461
1462 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1463 }
1464 cmd_buffer->state.descriptors_dirty = 0;
1465 cmd_buffer->state.push_descriptors_dirty = false;
1466 assert(cmd_buffer->cs->cdw <= cdw_max);
1467 }
1468
1469 static void
1470 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1471 struct radv_pipeline *pipeline,
1472 VkShaderStageFlags stages)
1473 {
1474 struct radv_pipeline_layout *layout = pipeline->layout;
1475 unsigned offset;
1476 void *ptr;
1477 uint64_t va;
1478
1479 stages &= cmd_buffer->push_constant_stages;
1480 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1481 return;
1482
1483 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1484 16 * layout->dynamic_offset_count,
1485 256, &offset, &ptr))
1486 return;
1487
1488 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1489 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1490 16 * layout->dynamic_offset_count);
1491
1492 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1493 va += offset;
1494
1495 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1496 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1497
1498 radv_foreach_stage(stage, stages) {
1499 if (pipeline->shaders[stage]) {
1500 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1501 AC_UD_PUSH_CONSTANTS, va);
1502 }
1503 }
1504
1505 cmd_buffer->push_constant_stages &= ~stages;
1506 assert(cmd_buffer->cs->cdw <= cdw_max);
1507 }
1508
1509 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1510 bool indexed_draw)
1511 {
1512 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1513
1514 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1515 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1516 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1517 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1518 primitive_reset_en);
1519 } else {
1520 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1521 primitive_reset_en);
1522 }
1523 }
1524
1525 if (primitive_reset_en) {
1526 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1527
1528 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1529 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1530 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1531 primitive_reset_index);
1532 }
1533 }
1534 }
1535
1536 static void
1537 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
1538 {
1539 struct radv_device *device = cmd_buffer->device;
1540
1541 if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline || cmd_buffer->state.vb_dirty) &&
1542 cmd_buffer->state.pipeline->num_vertex_attribs &&
1543 cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) {
1544 unsigned vb_offset;
1545 void *vb_ptr;
1546 uint32_t i = 0;
1547 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1548 uint64_t va;
1549
1550 /* allocate some descriptor state for vertex buffers */
1551 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1552 &vb_offset, &vb_ptr);
1553
1554 for (i = 0; i < num_attribs; i++) {
1555 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1556 uint32_t offset;
1557 int vb = cmd_buffer->state.pipeline->va_binding[i];
1558 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1559 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1560
1561 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1562 va = device->ws->buffer_get_va(buffer->bo);
1563
1564 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1565 va += offset + buffer->offset;
1566 desc[0] = va;
1567 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1568 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1569 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1570 else
1571 desc[2] = buffer->size - offset;
1572 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1573 }
1574
1575 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1576 va += vb_offset;
1577
1578 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1579 AC_UD_VS_VERTEX_BUFFERS, va);
1580 }
1581 cmd_buffer->state.vb_dirty = 0;
1582 }
1583
1584 static void
1585 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1586 bool indexed_draw, bool instanced_draw,
1587 bool indirect_draw,
1588 uint32_t draw_vertex_count)
1589 {
1590 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1591 uint32_t ia_multi_vgt_param;
1592
1593 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1594 cmd_buffer->cs, 4096);
1595
1596 radv_cmd_buffer_update_vertex_descriptors(cmd_buffer);
1597
1598 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1599 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1600
1601 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1602 radv_emit_framebuffer_state(cmd_buffer);
1603
1604 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1605 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1606 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1607 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
1608 else if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1609 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1610 else
1611 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1612 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1613 }
1614
1615 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1616
1617 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1618
1619 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1620 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1621 VK_SHADER_STAGE_ALL_GRAPHICS);
1622
1623 assert(cmd_buffer->cs->cdw <= cdw_max);
1624
1625 si_emit_cache_flush(cmd_buffer);
1626 }
1627
1628 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1629 VkPipelineStageFlags src_stage_mask)
1630 {
1631 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1632 VK_PIPELINE_STAGE_TRANSFER_BIT |
1633 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1634 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1635 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1636 }
1637
1638 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1639 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1640 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1641 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1642 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1643 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1644 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1645 VK_PIPELINE_STAGE_TRANSFER_BIT |
1646 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1647 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1648 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1649 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1650 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1651 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1652 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1653 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1654 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1655 }
1656 }
1657
1658 static enum radv_cmd_flush_bits
1659 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1660 VkAccessFlags src_flags)
1661 {
1662 enum radv_cmd_flush_bits flush_bits = 0;
1663 uint32_t b;
1664 for_each_bit(b, src_flags) {
1665 switch ((VkAccessFlagBits)(1 << b)) {
1666 case VK_ACCESS_SHADER_WRITE_BIT:
1667 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1668 break;
1669 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1670 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1671 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1672 break;
1673 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1674 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1675 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1676 break;
1677 case VK_ACCESS_TRANSFER_WRITE_BIT:
1678 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1679 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1680 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1681 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1682 RADV_CMD_FLAG_INV_GLOBAL_L2;
1683 break;
1684 default:
1685 break;
1686 }
1687 }
1688 return flush_bits;
1689 }
1690
1691 static enum radv_cmd_flush_bits
1692 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1693 VkAccessFlags dst_flags,
1694 struct radv_image *image)
1695 {
1696 enum radv_cmd_flush_bits flush_bits = 0;
1697 uint32_t b;
1698 for_each_bit(b, dst_flags) {
1699 switch ((VkAccessFlagBits)(1 << b)) {
1700 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1701 case VK_ACCESS_INDEX_READ_BIT:
1702 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1703 break;
1704 case VK_ACCESS_UNIFORM_READ_BIT:
1705 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1706 break;
1707 case VK_ACCESS_SHADER_READ_BIT:
1708 case VK_ACCESS_TRANSFER_READ_BIT:
1709 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1710 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1711 RADV_CMD_FLAG_INV_GLOBAL_L2;
1712 break;
1713 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1714 /* TODO: change to image && when the image gets passed
1715 * through from the subpass. */
1716 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1717 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1718 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1719 break;
1720 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1721 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1722 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1723 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1724 break;
1725 default:
1726 break;
1727 }
1728 }
1729 return flush_bits;
1730 }
1731
1732 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1733 {
1734 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1735 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1736 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1737 NULL);
1738 }
1739
1740 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1741 VkAttachmentReference att)
1742 {
1743 unsigned idx = att.attachment;
1744 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1745 VkImageSubresourceRange range;
1746 range.aspectMask = 0;
1747 range.baseMipLevel = view->base_mip;
1748 range.levelCount = 1;
1749 range.baseArrayLayer = view->base_layer;
1750 range.layerCount = cmd_buffer->state.framebuffer->layers;
1751
1752 radv_handle_image_transition(cmd_buffer,
1753 view->image,
1754 cmd_buffer->state.attachments[idx].current_layout,
1755 att.layout, 0, 0, &range,
1756 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1757
1758 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1759
1760
1761 }
1762
1763 void
1764 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1765 const struct radv_subpass *subpass, bool transitions)
1766 {
1767 if (transitions) {
1768 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1769
1770 for (unsigned i = 0; i < subpass->color_count; ++i) {
1771 radv_handle_subpass_image_transition(cmd_buffer,
1772 subpass->color_attachments[i]);
1773 }
1774
1775 for (unsigned i = 0; i < subpass->input_count; ++i) {
1776 radv_handle_subpass_image_transition(cmd_buffer,
1777 subpass->input_attachments[i]);
1778 }
1779
1780 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1781 radv_handle_subpass_image_transition(cmd_buffer,
1782 subpass->depth_stencil_attachment);
1783 }
1784 }
1785
1786 cmd_buffer->state.subpass = subpass;
1787
1788 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1789 }
1790
1791 static void
1792 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1793 struct radv_render_pass *pass,
1794 const VkRenderPassBeginInfo *info)
1795 {
1796 struct radv_cmd_state *state = &cmd_buffer->state;
1797
1798 if (pass->attachment_count == 0) {
1799 state->attachments = NULL;
1800 return;
1801 }
1802
1803 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1804 pass->attachment_count *
1805 sizeof(state->attachments[0]),
1806 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1807 if (state->attachments == NULL) {
1808 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1809 abort();
1810 }
1811
1812 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1813 struct radv_render_pass_attachment *att = &pass->attachments[i];
1814 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1815 VkImageAspectFlags clear_aspects = 0;
1816
1817 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1818 /* color attachment */
1819 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1820 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1821 }
1822 } else {
1823 /* depthstencil attachment */
1824 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1825 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1826 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1827 }
1828 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1829 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1830 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1831 }
1832 }
1833
1834 state->attachments[i].pending_clear_aspects = clear_aspects;
1835 if (clear_aspects && info) {
1836 assert(info->clearValueCount > i);
1837 state->attachments[i].clear_value = info->pClearValues[i];
1838 }
1839
1840 state->attachments[i].current_layout = att->initial_layout;
1841 }
1842 }
1843
1844 VkResult radv_AllocateCommandBuffers(
1845 VkDevice _device,
1846 const VkCommandBufferAllocateInfo *pAllocateInfo,
1847 VkCommandBuffer *pCommandBuffers)
1848 {
1849 RADV_FROM_HANDLE(radv_device, device, _device);
1850 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1851
1852 VkResult result = VK_SUCCESS;
1853 uint32_t i;
1854
1855 memset(pCommandBuffers, 0,
1856 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1857
1858 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1859
1860 if (!list_empty(&pool->free_cmd_buffers)) {
1861 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1862
1863 list_del(&cmd_buffer->pool_link);
1864 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1865
1866 radv_reset_cmd_buffer(cmd_buffer);
1867 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1868 cmd_buffer->level = pAllocateInfo->level;
1869
1870 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1871 result = VK_SUCCESS;
1872 } else {
1873 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1874 &pCommandBuffers[i]);
1875 }
1876 if (result != VK_SUCCESS)
1877 break;
1878 }
1879
1880 if (result != VK_SUCCESS)
1881 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1882 i, pCommandBuffers);
1883
1884 return result;
1885 }
1886
1887 void radv_FreeCommandBuffers(
1888 VkDevice device,
1889 VkCommandPool commandPool,
1890 uint32_t commandBufferCount,
1891 const VkCommandBuffer *pCommandBuffers)
1892 {
1893 for (uint32_t i = 0; i < commandBufferCount; i++) {
1894 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1895
1896 if (cmd_buffer) {
1897 if (cmd_buffer->pool) {
1898 list_del(&cmd_buffer->pool_link);
1899 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1900 } else
1901 radv_cmd_buffer_destroy(cmd_buffer);
1902
1903 }
1904 }
1905 }
1906
1907 VkResult radv_ResetCommandBuffer(
1908 VkCommandBuffer commandBuffer,
1909 VkCommandBufferResetFlags flags)
1910 {
1911 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1912 radv_reset_cmd_buffer(cmd_buffer);
1913 return VK_SUCCESS;
1914 }
1915
1916 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1917 {
1918 struct radv_device *device = cmd_buffer->device;
1919 if (device->gfx_init) {
1920 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1921 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1922 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1923 radeon_emit(cmd_buffer->cs, va);
1924 radeon_emit(cmd_buffer->cs, va >> 32);
1925 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1926 } else
1927 si_init_config(cmd_buffer);
1928 }
1929
1930 VkResult radv_BeginCommandBuffer(
1931 VkCommandBuffer commandBuffer,
1932 const VkCommandBufferBeginInfo *pBeginInfo)
1933 {
1934 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1935 radv_reset_cmd_buffer(cmd_buffer);
1936
1937 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1938 cmd_buffer->state.last_primitive_reset_en = -1;
1939
1940 /* setup initial configuration into command buffer */
1941 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1942 switch (cmd_buffer->queue_family_index) {
1943 case RADV_QUEUE_GENERAL:
1944 emit_gfx_buffer_state(cmd_buffer);
1945 radv_set_db_count_control(cmd_buffer);
1946 break;
1947 case RADV_QUEUE_COMPUTE:
1948 si_init_compute(cmd_buffer);
1949 break;
1950 case RADV_QUEUE_TRANSFER:
1951 default:
1952 break;
1953 }
1954 }
1955
1956 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1957 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1958 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1959
1960 struct radv_subpass *subpass =
1961 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1962
1963 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1964 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1965 }
1966
1967 radv_cmd_buffer_trace_emit(cmd_buffer);
1968 return VK_SUCCESS;
1969 }
1970
1971 void radv_CmdBindVertexBuffers(
1972 VkCommandBuffer commandBuffer,
1973 uint32_t firstBinding,
1974 uint32_t bindingCount,
1975 const VkBuffer* pBuffers,
1976 const VkDeviceSize* pOffsets)
1977 {
1978 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1979 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1980
1981 /* We have to defer setting up vertex buffer since we need the buffer
1982 * stride from the pipeline. */
1983
1984 assert(firstBinding + bindingCount < MAX_VBS);
1985 for (uint32_t i = 0; i < bindingCount; i++) {
1986 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1987 vb[firstBinding + i].offset = pOffsets[i];
1988 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1989 }
1990 }
1991
1992 void radv_CmdBindIndexBuffer(
1993 VkCommandBuffer commandBuffer,
1994 VkBuffer buffer,
1995 VkDeviceSize offset,
1996 VkIndexType indexType)
1997 {
1998 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1999 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2000
2001 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2002 cmd_buffer->state.index_va = cmd_buffer->device->ws->buffer_get_va(index_buffer->bo);
2003 cmd_buffer->state.index_va += index_buffer->offset + offset;
2004
2005 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2006 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2007 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2008 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, index_buffer->bo, 8);
2009 }
2010
2011
2012 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2013 struct radv_descriptor_set *set,
2014 unsigned idx)
2015 {
2016 struct radeon_winsys *ws = cmd_buffer->device->ws;
2017
2018 cmd_buffer->state.descriptors[idx] = set;
2019 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2020 if (!set)
2021 return;
2022
2023 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2024
2025 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2026 if (set->descriptors[j])
2027 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2028
2029 if(set->bo)
2030 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2031 }
2032
2033 void radv_CmdBindDescriptorSets(
2034 VkCommandBuffer commandBuffer,
2035 VkPipelineBindPoint pipelineBindPoint,
2036 VkPipelineLayout _layout,
2037 uint32_t firstSet,
2038 uint32_t descriptorSetCount,
2039 const VkDescriptorSet* pDescriptorSets,
2040 uint32_t dynamicOffsetCount,
2041 const uint32_t* pDynamicOffsets)
2042 {
2043 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2044 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2045 unsigned dyn_idx = 0;
2046
2047 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2048 unsigned idx = i + firstSet;
2049 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2050 radv_bind_descriptor_set(cmd_buffer, set, idx);
2051
2052 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2053 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2054 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2055 assert(dyn_idx < dynamicOffsetCount);
2056
2057 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2058 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2059 dst[0] = va;
2060 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2061 dst[2] = range->size;
2062 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2063 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2064 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2065 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2066 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2067 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2068 cmd_buffer->push_constant_stages |=
2069 set->layout->dynamic_shader_stages;
2070 }
2071 }
2072 }
2073
2074 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2075 struct radv_descriptor_set *set,
2076 struct radv_descriptor_set_layout *layout)
2077 {
2078 set->size = layout->size;
2079 set->layout = layout;
2080
2081 if (cmd_buffer->push_descriptors.capacity < set->size) {
2082 size_t new_size = MAX2(set->size, 1024);
2083 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2084 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2085
2086 free(set->mapped_ptr);
2087 set->mapped_ptr = malloc(new_size);
2088
2089 if (!set->mapped_ptr) {
2090 cmd_buffer->push_descriptors.capacity = 0;
2091 cmd_buffer->record_fail = true;
2092 return false;
2093 }
2094
2095 cmd_buffer->push_descriptors.capacity = new_size;
2096 }
2097
2098 return true;
2099 }
2100
2101 void radv_meta_push_descriptor_set(
2102 struct radv_cmd_buffer* cmd_buffer,
2103 VkPipelineBindPoint pipelineBindPoint,
2104 VkPipelineLayout _layout,
2105 uint32_t set,
2106 uint32_t descriptorWriteCount,
2107 const VkWriteDescriptorSet* pDescriptorWrites)
2108 {
2109 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2110 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2111 unsigned bo_offset;
2112
2113 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2114
2115 push_set->size = layout->set[set].layout->size;
2116 push_set->layout = layout->set[set].layout;
2117
2118 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2119 &bo_offset,
2120 (void**) &push_set->mapped_ptr))
2121 return;
2122
2123 push_set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
2124 push_set->va += bo_offset;
2125
2126 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2127 radv_descriptor_set_to_handle(push_set),
2128 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2129
2130 cmd_buffer->state.descriptors[set] = push_set;
2131 cmd_buffer->state.descriptors_dirty |= (1u << set);
2132 }
2133
2134 void radv_CmdPushDescriptorSetKHR(
2135 VkCommandBuffer commandBuffer,
2136 VkPipelineBindPoint pipelineBindPoint,
2137 VkPipelineLayout _layout,
2138 uint32_t set,
2139 uint32_t descriptorWriteCount,
2140 const VkWriteDescriptorSet* pDescriptorWrites)
2141 {
2142 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2143 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2144 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2145
2146 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2147
2148 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2149 return;
2150
2151 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2152 radv_descriptor_set_to_handle(push_set),
2153 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2154
2155 cmd_buffer->state.descriptors[set] = push_set;
2156 cmd_buffer->state.descriptors_dirty |= (1u << set);
2157 cmd_buffer->state.push_descriptors_dirty = true;
2158 }
2159
2160 void radv_CmdPushDescriptorSetWithTemplateKHR(
2161 VkCommandBuffer commandBuffer,
2162 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2163 VkPipelineLayout _layout,
2164 uint32_t set,
2165 const void* pData)
2166 {
2167 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2168 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2169 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2170
2171 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2172
2173 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2174 return;
2175
2176 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2177 descriptorUpdateTemplate, pData);
2178
2179 cmd_buffer->state.descriptors[set] = push_set;
2180 cmd_buffer->state.descriptors_dirty |= (1u << set);
2181 cmd_buffer->state.push_descriptors_dirty = true;
2182 }
2183
2184 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2185 VkPipelineLayout layout,
2186 VkShaderStageFlags stageFlags,
2187 uint32_t offset,
2188 uint32_t size,
2189 const void* pValues)
2190 {
2191 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2192 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2193 cmd_buffer->push_constant_stages |= stageFlags;
2194 }
2195
2196 VkResult radv_EndCommandBuffer(
2197 VkCommandBuffer commandBuffer)
2198 {
2199 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2200
2201 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
2202 si_emit_cache_flush(cmd_buffer);
2203
2204 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
2205 cmd_buffer->record_fail)
2206 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2207 return VK_SUCCESS;
2208 }
2209
2210 static void
2211 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2212 {
2213 struct radeon_winsys *ws = cmd_buffer->device->ws;
2214 struct radv_shader_variant *compute_shader;
2215 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2216 uint64_t va;
2217
2218 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2219 return;
2220
2221 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2222
2223 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2224 va = ws->buffer_get_va(compute_shader->bo);
2225
2226 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2227 radv_emit_prefetch(cmd_buffer, va, compute_shader->code_size);
2228
2229 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2230 cmd_buffer->cs, 16);
2231
2232 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2233 radeon_emit(cmd_buffer->cs, va >> 8);
2234 radeon_emit(cmd_buffer->cs, va >> 40);
2235
2236 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2237 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2238 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2239
2240
2241 cmd_buffer->compute_scratch_size_needed =
2242 MAX2(cmd_buffer->compute_scratch_size_needed,
2243 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2244
2245 /* change these once we have scratch support */
2246 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2247 S_00B860_WAVES(pipeline->max_waves) |
2248 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2249
2250 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2251 radeon_emit(cmd_buffer->cs,
2252 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2253 radeon_emit(cmd_buffer->cs,
2254 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2255 radeon_emit(cmd_buffer->cs,
2256 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2257
2258 assert(cmd_buffer->cs->cdw <= cdw_max);
2259 }
2260
2261 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2262 {
2263 for (unsigned i = 0; i < MAX_SETS; i++) {
2264 if (cmd_buffer->state.descriptors[i])
2265 cmd_buffer->state.descriptors_dirty |= (1u << i);
2266 }
2267 }
2268
2269 void radv_CmdBindPipeline(
2270 VkCommandBuffer commandBuffer,
2271 VkPipelineBindPoint pipelineBindPoint,
2272 VkPipeline _pipeline)
2273 {
2274 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2275 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2276
2277 radv_mark_descriptor_sets_dirty(cmd_buffer);
2278
2279 switch (pipelineBindPoint) {
2280 case VK_PIPELINE_BIND_POINT_COMPUTE:
2281 cmd_buffer->state.compute_pipeline = pipeline;
2282 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2283 break;
2284 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2285 cmd_buffer->state.pipeline = pipeline;
2286 if (!pipeline)
2287 break;
2288
2289 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2290 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2291
2292 /* Apply the dynamic state from the pipeline */
2293 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2294 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2295 &pipeline->dynamic_state,
2296 pipeline->dynamic_state_mask);
2297
2298 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2299 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2300 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2301 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2302
2303 if (radv_pipeline_has_tess(pipeline))
2304 cmd_buffer->tess_rings_needed = true;
2305
2306 if (radv_pipeline_has_gs(pipeline)) {
2307 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2308 AC_UD_SCRATCH_RING_OFFSETS);
2309 if (cmd_buffer->ring_offsets_idx == -1)
2310 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2311 else if (loc->sgpr_idx != -1)
2312 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2313 }
2314 break;
2315 default:
2316 assert(!"invalid bind point");
2317 break;
2318 }
2319 }
2320
2321 void radv_CmdSetViewport(
2322 VkCommandBuffer commandBuffer,
2323 uint32_t firstViewport,
2324 uint32_t viewportCount,
2325 const VkViewport* pViewports)
2326 {
2327 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2328
2329 const uint32_t total_count = firstViewport + viewportCount;
2330 if (cmd_buffer->state.dynamic.viewport.count < total_count)
2331 cmd_buffer->state.dynamic.viewport.count = total_count;
2332
2333 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2334 pViewports, viewportCount * sizeof(*pViewports));
2335
2336 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2337 }
2338
2339 void radv_CmdSetScissor(
2340 VkCommandBuffer commandBuffer,
2341 uint32_t firstScissor,
2342 uint32_t scissorCount,
2343 const VkRect2D* pScissors)
2344 {
2345 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2346
2347 const uint32_t total_count = firstScissor + scissorCount;
2348 if (cmd_buffer->state.dynamic.scissor.count < total_count)
2349 cmd_buffer->state.dynamic.scissor.count = total_count;
2350
2351 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2352 pScissors, scissorCount * sizeof(*pScissors));
2353 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2354 }
2355
2356 void radv_CmdSetLineWidth(
2357 VkCommandBuffer commandBuffer,
2358 float lineWidth)
2359 {
2360 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2361 cmd_buffer->state.dynamic.line_width = lineWidth;
2362 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2363 }
2364
2365 void radv_CmdSetDepthBias(
2366 VkCommandBuffer commandBuffer,
2367 float depthBiasConstantFactor,
2368 float depthBiasClamp,
2369 float depthBiasSlopeFactor)
2370 {
2371 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2372
2373 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2374 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2375 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2376
2377 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2378 }
2379
2380 void radv_CmdSetBlendConstants(
2381 VkCommandBuffer commandBuffer,
2382 const float blendConstants[4])
2383 {
2384 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2385
2386 memcpy(cmd_buffer->state.dynamic.blend_constants,
2387 blendConstants, sizeof(float) * 4);
2388
2389 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2390 }
2391
2392 void radv_CmdSetDepthBounds(
2393 VkCommandBuffer commandBuffer,
2394 float minDepthBounds,
2395 float maxDepthBounds)
2396 {
2397 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2398
2399 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2400 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2401
2402 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2403 }
2404
2405 void radv_CmdSetStencilCompareMask(
2406 VkCommandBuffer commandBuffer,
2407 VkStencilFaceFlags faceMask,
2408 uint32_t compareMask)
2409 {
2410 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2411
2412 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2413 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2414 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2415 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2416
2417 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2418 }
2419
2420 void radv_CmdSetStencilWriteMask(
2421 VkCommandBuffer commandBuffer,
2422 VkStencilFaceFlags faceMask,
2423 uint32_t writeMask)
2424 {
2425 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2426
2427 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2428 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2429 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2430 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2431
2432 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2433 }
2434
2435 void radv_CmdSetStencilReference(
2436 VkCommandBuffer commandBuffer,
2437 VkStencilFaceFlags faceMask,
2438 uint32_t reference)
2439 {
2440 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2441
2442 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2443 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2444 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2445 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2446
2447 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2448 }
2449
2450 void radv_CmdExecuteCommands(
2451 VkCommandBuffer commandBuffer,
2452 uint32_t commandBufferCount,
2453 const VkCommandBuffer* pCmdBuffers)
2454 {
2455 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2456
2457 /* Emit pending flushes on primary prior to executing secondary */
2458 si_emit_cache_flush(primary);
2459
2460 for (uint32_t i = 0; i < commandBufferCount; i++) {
2461 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2462
2463 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2464 secondary->scratch_size_needed);
2465 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2466 secondary->compute_scratch_size_needed);
2467
2468 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2469 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2470 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2471 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2472 if (secondary->tess_rings_needed)
2473 primary->tess_rings_needed = true;
2474 if (secondary->sample_positions_needed)
2475 primary->sample_positions_needed = true;
2476
2477 if (secondary->ring_offsets_idx != -1) {
2478 if (primary->ring_offsets_idx == -1)
2479 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2480 else
2481 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2482 }
2483 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2484 }
2485
2486 /* if we execute secondary we need to re-emit out pipelines */
2487 if (commandBufferCount) {
2488 primary->state.emitted_pipeline = NULL;
2489 primary->state.emitted_compute_pipeline = NULL;
2490 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2491 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2492 primary->state.last_primitive_reset_en = -1;
2493 primary->state.last_primitive_reset_index = 0;
2494 radv_mark_descriptor_sets_dirty(primary);
2495 }
2496 }
2497
2498 VkResult radv_CreateCommandPool(
2499 VkDevice _device,
2500 const VkCommandPoolCreateInfo* pCreateInfo,
2501 const VkAllocationCallbacks* pAllocator,
2502 VkCommandPool* pCmdPool)
2503 {
2504 RADV_FROM_HANDLE(radv_device, device, _device);
2505 struct radv_cmd_pool *pool;
2506
2507 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2508 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2509 if (pool == NULL)
2510 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2511
2512 if (pAllocator)
2513 pool->alloc = *pAllocator;
2514 else
2515 pool->alloc = device->alloc;
2516
2517 list_inithead(&pool->cmd_buffers);
2518 list_inithead(&pool->free_cmd_buffers);
2519
2520 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2521
2522 *pCmdPool = radv_cmd_pool_to_handle(pool);
2523
2524 return VK_SUCCESS;
2525
2526 }
2527
2528 void radv_DestroyCommandPool(
2529 VkDevice _device,
2530 VkCommandPool commandPool,
2531 const VkAllocationCallbacks* pAllocator)
2532 {
2533 RADV_FROM_HANDLE(radv_device, device, _device);
2534 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2535
2536 if (!pool)
2537 return;
2538
2539 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2540 &pool->cmd_buffers, pool_link) {
2541 radv_cmd_buffer_destroy(cmd_buffer);
2542 }
2543
2544 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2545 &pool->free_cmd_buffers, pool_link) {
2546 radv_cmd_buffer_destroy(cmd_buffer);
2547 }
2548
2549 vk_free2(&device->alloc, pAllocator, pool);
2550 }
2551
2552 VkResult radv_ResetCommandPool(
2553 VkDevice device,
2554 VkCommandPool commandPool,
2555 VkCommandPoolResetFlags flags)
2556 {
2557 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2558
2559 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2560 &pool->cmd_buffers, pool_link) {
2561 radv_reset_cmd_buffer(cmd_buffer);
2562 }
2563
2564 return VK_SUCCESS;
2565 }
2566
2567 void radv_TrimCommandPoolKHR(
2568 VkDevice device,
2569 VkCommandPool commandPool,
2570 VkCommandPoolTrimFlagsKHR flags)
2571 {
2572 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2573
2574 if (!pool)
2575 return;
2576
2577 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2578 &pool->free_cmd_buffers, pool_link) {
2579 radv_cmd_buffer_destroy(cmd_buffer);
2580 }
2581 }
2582
2583 void radv_CmdBeginRenderPass(
2584 VkCommandBuffer commandBuffer,
2585 const VkRenderPassBeginInfo* pRenderPassBegin,
2586 VkSubpassContents contents)
2587 {
2588 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2589 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2590 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2591
2592 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2593 cmd_buffer->cs, 2048);
2594
2595 cmd_buffer->state.framebuffer = framebuffer;
2596 cmd_buffer->state.pass = pass;
2597 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2598 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2599
2600 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2601 assert(cmd_buffer->cs->cdw <= cdw_max);
2602
2603 radv_cmd_buffer_clear_subpass(cmd_buffer);
2604 }
2605
2606 void radv_CmdNextSubpass(
2607 VkCommandBuffer commandBuffer,
2608 VkSubpassContents contents)
2609 {
2610 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2611
2612 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2613
2614 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2615 2048);
2616
2617 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2618 radv_cmd_buffer_clear_subpass(cmd_buffer);
2619 }
2620
2621 void radv_CmdDraw(
2622 VkCommandBuffer commandBuffer,
2623 uint32_t vertexCount,
2624 uint32_t instanceCount,
2625 uint32_t firstVertex,
2626 uint32_t firstInstance)
2627 {
2628 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2629
2630 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2631
2632 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2633
2634 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2635 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2636 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2637 radeon_emit(cmd_buffer->cs, firstVertex);
2638 radeon_emit(cmd_buffer->cs, firstInstance);
2639 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2640 radeon_emit(cmd_buffer->cs, 0);
2641
2642 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2643 radeon_emit(cmd_buffer->cs, instanceCount);
2644
2645 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
2646 radeon_emit(cmd_buffer->cs, vertexCount);
2647 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2648 S_0287F0_USE_OPAQUE(0));
2649
2650 assert(cmd_buffer->cs->cdw <= cdw_max);
2651
2652 radv_cmd_buffer_trace_emit(cmd_buffer);
2653 }
2654
2655 void radv_CmdDrawIndexed(
2656 VkCommandBuffer commandBuffer,
2657 uint32_t indexCount,
2658 uint32_t instanceCount,
2659 uint32_t firstIndex,
2660 int32_t vertexOffset,
2661 uint32_t firstInstance)
2662 {
2663 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2664 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2665 uint64_t index_va;
2666
2667 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2668
2669 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2670
2671 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2672 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_03090C_VGT_INDEX_TYPE,
2673 2, cmd_buffer->state.index_type);
2674 } else {
2675 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2676 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2677 }
2678
2679 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2680 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2681 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2682 radeon_emit(cmd_buffer->cs, vertexOffset);
2683 radeon_emit(cmd_buffer->cs, firstInstance);
2684 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2685 radeon_emit(cmd_buffer->cs, 0);
2686
2687 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2688 radeon_emit(cmd_buffer->cs, instanceCount);
2689
2690 index_va = cmd_buffer->state.index_va;
2691 index_va += firstIndex * index_size;
2692 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2693 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2694 radeon_emit(cmd_buffer->cs, index_va);
2695 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2696 radeon_emit(cmd_buffer->cs, indexCount);
2697 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2698
2699 assert(cmd_buffer->cs->cdw <= cdw_max);
2700 radv_cmd_buffer_trace_emit(cmd_buffer);
2701 }
2702
2703 static void
2704 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2705 VkBuffer _buffer,
2706 VkDeviceSize offset,
2707 VkBuffer _count_buffer,
2708 VkDeviceSize count_offset,
2709 uint32_t draw_count,
2710 uint32_t stride,
2711 bool indexed)
2712 {
2713 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2714 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2715 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2716 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2717 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2718 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2719 indirect_va += offset + buffer->offset;
2720 uint64_t count_va = 0;
2721
2722 if (count_buffer) {
2723 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2724 count_va += count_offset + count_buffer->offset;
2725 }
2726
2727 if (!draw_count)
2728 return;
2729
2730 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2731 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2732 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2733 assert(base_reg);
2734
2735 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2736 radeon_emit(cs, 1);
2737 radeon_emit(cs, indirect_va);
2738 radeon_emit(cs, indirect_va >> 32);
2739
2740 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2741 PKT3_DRAW_INDIRECT_MULTI,
2742 8, false));
2743 radeon_emit(cs, 0);
2744 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2745 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2746 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2747 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2748 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2749 radeon_emit(cs, draw_count); /* count */
2750 radeon_emit(cs, count_va); /* count_addr */
2751 radeon_emit(cs, count_va >> 32);
2752 radeon_emit(cs, stride); /* stride */
2753 radeon_emit(cs, di_src_sel);
2754 radv_cmd_buffer_trace_emit(cmd_buffer);
2755 }
2756
2757 static void
2758 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2759 VkBuffer buffer,
2760 VkDeviceSize offset,
2761 VkBuffer countBuffer,
2762 VkDeviceSize countBufferOffset,
2763 uint32_t maxDrawCount,
2764 uint32_t stride)
2765 {
2766 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2767 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
2768
2769 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2770 cmd_buffer->cs, 14);
2771
2772 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2773 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2774
2775 assert(cmd_buffer->cs->cdw <= cdw_max);
2776 }
2777
2778 static void
2779 radv_cmd_draw_indexed_indirect_count(
2780 VkCommandBuffer commandBuffer,
2781 VkBuffer buffer,
2782 VkDeviceSize offset,
2783 VkBuffer countBuffer,
2784 VkDeviceSize countBufferOffset,
2785 uint32_t maxDrawCount,
2786 uint32_t stride)
2787 {
2788 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2789 uint64_t index_va;
2790 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
2791
2792 index_va = cmd_buffer->state.index_va;
2793
2794 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2795
2796 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2797 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2798
2799 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2800 radeon_emit(cmd_buffer->cs, index_va);
2801 radeon_emit(cmd_buffer->cs, index_va >> 32);
2802
2803 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2804 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2805
2806 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2807 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2808
2809 assert(cmd_buffer->cs->cdw <= cdw_max);
2810 }
2811
2812 void radv_CmdDrawIndirect(
2813 VkCommandBuffer commandBuffer,
2814 VkBuffer buffer,
2815 VkDeviceSize offset,
2816 uint32_t drawCount,
2817 uint32_t stride)
2818 {
2819 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2820 VK_NULL_HANDLE, 0, drawCount, stride);
2821 }
2822
2823 void radv_CmdDrawIndexedIndirect(
2824 VkCommandBuffer commandBuffer,
2825 VkBuffer buffer,
2826 VkDeviceSize offset,
2827 uint32_t drawCount,
2828 uint32_t stride)
2829 {
2830 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2831 VK_NULL_HANDLE, 0, drawCount, stride);
2832 }
2833
2834 void radv_CmdDrawIndirectCountAMD(
2835 VkCommandBuffer commandBuffer,
2836 VkBuffer buffer,
2837 VkDeviceSize offset,
2838 VkBuffer countBuffer,
2839 VkDeviceSize countBufferOffset,
2840 uint32_t maxDrawCount,
2841 uint32_t stride)
2842 {
2843 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2844 countBuffer, countBufferOffset,
2845 maxDrawCount, stride);
2846 }
2847
2848 void radv_CmdDrawIndexedIndirectCountAMD(
2849 VkCommandBuffer commandBuffer,
2850 VkBuffer buffer,
2851 VkDeviceSize offset,
2852 VkBuffer countBuffer,
2853 VkDeviceSize countBufferOffset,
2854 uint32_t maxDrawCount,
2855 uint32_t stride)
2856 {
2857 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2858 countBuffer, countBufferOffset,
2859 maxDrawCount, stride);
2860 }
2861
2862 static void
2863 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2864 {
2865 radv_emit_compute_pipeline(cmd_buffer);
2866 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
2867 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2868 VK_SHADER_STAGE_COMPUTE_BIT);
2869 si_emit_cache_flush(cmd_buffer);
2870 }
2871
2872 void radv_CmdDispatch(
2873 VkCommandBuffer commandBuffer,
2874 uint32_t x,
2875 uint32_t y,
2876 uint32_t z)
2877 {
2878 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2879
2880 radv_flush_compute_state(cmd_buffer);
2881
2882 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2883
2884 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2885 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2886 if (loc->sgpr_idx != -1) {
2887 assert(!loc->indirect);
2888 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2889 assert(loc->num_sgprs == grid_used);
2890 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
2891 radeon_emit(cmd_buffer->cs, x);
2892 if (grid_used > 1)
2893 radeon_emit(cmd_buffer->cs, y);
2894 if (grid_used > 2)
2895 radeon_emit(cmd_buffer->cs, z);
2896 }
2897
2898 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2899 PKT3_SHADER_TYPE_S(1));
2900 radeon_emit(cmd_buffer->cs, x);
2901 radeon_emit(cmd_buffer->cs, y);
2902 radeon_emit(cmd_buffer->cs, z);
2903 radeon_emit(cmd_buffer->cs, 1);
2904
2905 assert(cmd_buffer->cs->cdw <= cdw_max);
2906 radv_cmd_buffer_trace_emit(cmd_buffer);
2907 }
2908
2909 void radv_CmdDispatchIndirect(
2910 VkCommandBuffer commandBuffer,
2911 VkBuffer _buffer,
2912 VkDeviceSize offset)
2913 {
2914 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2915 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2916 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2917 va += buffer->offset + offset;
2918
2919 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2920
2921 radv_flush_compute_state(cmd_buffer);
2922
2923 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2924 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2925 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2926 if (loc->sgpr_idx != -1) {
2927 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2928 for (unsigned i = 0; i < grid_used; ++i) {
2929 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2930 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2931 COPY_DATA_DST_SEL(COPY_DATA_REG));
2932 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2933 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2934 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2935 radeon_emit(cmd_buffer->cs, 0);
2936 }
2937 }
2938
2939 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2940 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2941 PKT3_SHADER_TYPE_S(1));
2942 radeon_emit(cmd_buffer->cs, va);
2943 radeon_emit(cmd_buffer->cs, va >> 32);
2944 radeon_emit(cmd_buffer->cs, 1);
2945 } else {
2946 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2947 PKT3_SHADER_TYPE_S(1));
2948 radeon_emit(cmd_buffer->cs, 1);
2949 radeon_emit(cmd_buffer->cs, va);
2950 radeon_emit(cmd_buffer->cs, va >> 32);
2951
2952 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2953 PKT3_SHADER_TYPE_S(1));
2954 radeon_emit(cmd_buffer->cs, 0);
2955 radeon_emit(cmd_buffer->cs, 1);
2956 }
2957
2958 assert(cmd_buffer->cs->cdw <= cdw_max);
2959 radv_cmd_buffer_trace_emit(cmd_buffer);
2960 }
2961
2962 void radv_unaligned_dispatch(
2963 struct radv_cmd_buffer *cmd_buffer,
2964 uint32_t x,
2965 uint32_t y,
2966 uint32_t z)
2967 {
2968 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2969 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2970 uint32_t blocks[3], remainder[3];
2971
2972 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2973 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2974 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2975
2976 /* If aligned, these should be an entire block size, not 0 */
2977 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2978 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2979 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2980
2981 radv_flush_compute_state(cmd_buffer);
2982
2983 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2984
2985 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2986 radeon_emit(cmd_buffer->cs,
2987 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2988 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2989 radeon_emit(cmd_buffer->cs,
2990 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2991 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2992 radeon_emit(cmd_buffer->cs,
2993 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2994 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2995
2996 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2997 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2998 if (loc->sgpr_idx != -1) {
2999 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
3000 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
3001 radeon_emit(cmd_buffer->cs, blocks[0]);
3002 if (grid_used > 1)
3003 radeon_emit(cmd_buffer->cs, blocks[1]);
3004 if (grid_used > 2)
3005 radeon_emit(cmd_buffer->cs, blocks[2]);
3006 }
3007 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3008 PKT3_SHADER_TYPE_S(1));
3009 radeon_emit(cmd_buffer->cs, blocks[0]);
3010 radeon_emit(cmd_buffer->cs, blocks[1]);
3011 radeon_emit(cmd_buffer->cs, blocks[2]);
3012 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
3013 S_00B800_PARTIAL_TG_EN(1));
3014
3015 assert(cmd_buffer->cs->cdw <= cdw_max);
3016 radv_cmd_buffer_trace_emit(cmd_buffer);
3017 }
3018
3019 void radv_CmdEndRenderPass(
3020 VkCommandBuffer commandBuffer)
3021 {
3022 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3023
3024 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3025
3026 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3027
3028 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3029 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3030 radv_handle_subpass_image_transition(cmd_buffer,
3031 (VkAttachmentReference){i, layout});
3032 }
3033
3034 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3035
3036 cmd_buffer->state.pass = NULL;
3037 cmd_buffer->state.subpass = NULL;
3038 cmd_buffer->state.attachments = NULL;
3039 cmd_buffer->state.framebuffer = NULL;
3040 }
3041
3042 /*
3043 * For HTILE we have the following interesting clear words:
3044 * 0x0000030f: Uncompressed.
3045 * 0xfffffff0: Clear depth to 1.0
3046 * 0x00000000: Clear depth to 0.0
3047 */
3048 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3049 struct radv_image *image,
3050 const VkImageSubresourceRange *range,
3051 uint32_t clear_word)
3052 {
3053 assert(range->baseMipLevel == 0);
3054 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3055 unsigned layer_count = radv_get_layerCount(image, range);
3056 uint64_t size = image->surface.htile_slice_size * layer_count;
3057 uint64_t offset = image->offset + image->htile_offset +
3058 image->surface.htile_slice_size * range->baseArrayLayer;
3059
3060 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3061 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3062
3063 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
3064
3065 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3066 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3067 RADV_CMD_FLAG_INV_VMEM_L1 |
3068 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3069 }
3070
3071 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3072 struct radv_image *image,
3073 VkImageLayout src_layout,
3074 VkImageLayout dst_layout,
3075 unsigned src_queue_mask,
3076 unsigned dst_queue_mask,
3077 const VkImageSubresourceRange *range,
3078 VkImageAspectFlags pending_clears)
3079 {
3080 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3081 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3082 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3083 cmd_buffer->state.render_area.extent.width == image->info.width &&
3084 cmd_buffer->state.render_area.extent.height == image->info.height) {
3085 /* The clear will initialize htile. */
3086 return;
3087 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3088 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3089 /* TODO: merge with the clear if applicable */
3090 radv_initialize_htile(cmd_buffer, image, range, 0);
3091 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3092 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3093 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3094 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3095 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3096 VkImageSubresourceRange local_range = *range;
3097 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3098 local_range.baseMipLevel = 0;
3099 local_range.levelCount = 1;
3100
3101 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3102 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3103
3104 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3105
3106 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3107 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3108 }
3109 }
3110
3111 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3112 struct radv_image *image, uint32_t value)
3113 {
3114 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3115 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3116
3117 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3118 image->cmask.size, value);
3119
3120 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3121 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3122 RADV_CMD_FLAG_INV_VMEM_L1 |
3123 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3124 }
3125
3126 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3127 struct radv_image *image,
3128 VkImageLayout src_layout,
3129 VkImageLayout dst_layout,
3130 unsigned src_queue_mask,
3131 unsigned dst_queue_mask,
3132 const VkImageSubresourceRange *range,
3133 VkImageAspectFlags pending_clears)
3134 {
3135 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3136 if (image->fmask.size)
3137 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3138 else
3139 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3140 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3141 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3142 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3143 }
3144 }
3145
3146 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3147 struct radv_image *image, uint32_t value)
3148 {
3149
3150 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3151 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3152
3153 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3154 image->surface.dcc_size, value);
3155
3156 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3157 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3158 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3159 RADV_CMD_FLAG_INV_VMEM_L1 |
3160 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3161 }
3162
3163 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3164 struct radv_image *image,
3165 VkImageLayout src_layout,
3166 VkImageLayout dst_layout,
3167 unsigned src_queue_mask,
3168 unsigned dst_queue_mask,
3169 const VkImageSubresourceRange *range,
3170 VkImageAspectFlags pending_clears)
3171 {
3172 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3173 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3174 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3175 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3176 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3177 }
3178 }
3179
3180 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3181 struct radv_image *image,
3182 VkImageLayout src_layout,
3183 VkImageLayout dst_layout,
3184 uint32_t src_family,
3185 uint32_t dst_family,
3186 const VkImageSubresourceRange *range,
3187 VkImageAspectFlags pending_clears)
3188 {
3189 if (image->exclusive && src_family != dst_family) {
3190 /* This is an acquire or a release operation and there will be
3191 * a corresponding release/acquire. Do the transition in the
3192 * most flexible queue. */
3193
3194 assert(src_family == cmd_buffer->queue_family_index ||
3195 dst_family == cmd_buffer->queue_family_index);
3196
3197 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3198 return;
3199
3200 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3201 (src_family == RADV_QUEUE_GENERAL ||
3202 dst_family == RADV_QUEUE_GENERAL))
3203 return;
3204 }
3205
3206 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3207 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3208
3209 if (image->surface.htile_size)
3210 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3211 dst_layout, src_queue_mask,
3212 dst_queue_mask, range,
3213 pending_clears);
3214
3215 if (image->cmask.size)
3216 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3217 dst_layout, src_queue_mask,
3218 dst_queue_mask, range,
3219 pending_clears);
3220
3221 if (image->surface.dcc_size)
3222 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3223 dst_layout, src_queue_mask,
3224 dst_queue_mask, range,
3225 pending_clears);
3226 }
3227
3228 void radv_CmdPipelineBarrier(
3229 VkCommandBuffer commandBuffer,
3230 VkPipelineStageFlags srcStageMask,
3231 VkPipelineStageFlags destStageMask,
3232 VkBool32 byRegion,
3233 uint32_t memoryBarrierCount,
3234 const VkMemoryBarrier* pMemoryBarriers,
3235 uint32_t bufferMemoryBarrierCount,
3236 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3237 uint32_t imageMemoryBarrierCount,
3238 const VkImageMemoryBarrier* pImageMemoryBarriers)
3239 {
3240 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3241 enum radv_cmd_flush_bits src_flush_bits = 0;
3242 enum radv_cmd_flush_bits dst_flush_bits = 0;
3243
3244 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3245 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3246 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3247 NULL);
3248 }
3249
3250 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3251 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3252 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3253 NULL);
3254 }
3255
3256 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3257 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3258 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3259 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3260 image);
3261 }
3262
3263 radv_stage_flush(cmd_buffer, srcStageMask);
3264 cmd_buffer->state.flush_bits |= src_flush_bits;
3265
3266 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3267 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3268 radv_handle_image_transition(cmd_buffer, image,
3269 pImageMemoryBarriers[i].oldLayout,
3270 pImageMemoryBarriers[i].newLayout,
3271 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3272 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3273 &pImageMemoryBarriers[i].subresourceRange,
3274 0);
3275 }
3276
3277 cmd_buffer->state.flush_bits |= dst_flush_bits;
3278 }
3279
3280
3281 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3282 struct radv_event *event,
3283 VkPipelineStageFlags stageMask,
3284 unsigned value)
3285 {
3286 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3287 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3288
3289 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3290
3291 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3292
3293 /* TODO: this is overkill. Probably should figure something out from
3294 * the stage mask. */
3295
3296 si_cs_emit_write_event_eop(cs,
3297 cmd_buffer->device->physical_device->rad_info.chip_class,
3298 false,
3299 EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
3300 1, va, 2, value);
3301
3302 assert(cmd_buffer->cs->cdw <= cdw_max);
3303 }
3304
3305 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3306 VkEvent _event,
3307 VkPipelineStageFlags stageMask)
3308 {
3309 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3310 RADV_FROM_HANDLE(radv_event, event, _event);
3311
3312 write_event(cmd_buffer, event, stageMask, 1);
3313 }
3314
3315 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3316 VkEvent _event,
3317 VkPipelineStageFlags stageMask)
3318 {
3319 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3320 RADV_FROM_HANDLE(radv_event, event, _event);
3321
3322 write_event(cmd_buffer, event, stageMask, 0);
3323 }
3324
3325 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3326 uint32_t eventCount,
3327 const VkEvent* pEvents,
3328 VkPipelineStageFlags srcStageMask,
3329 VkPipelineStageFlags dstStageMask,
3330 uint32_t memoryBarrierCount,
3331 const VkMemoryBarrier* pMemoryBarriers,
3332 uint32_t bufferMemoryBarrierCount,
3333 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3334 uint32_t imageMemoryBarrierCount,
3335 const VkImageMemoryBarrier* pImageMemoryBarriers)
3336 {
3337 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3338 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3339
3340 for (unsigned i = 0; i < eventCount; ++i) {
3341 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3342 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3343
3344 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3345
3346 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3347
3348 si_emit_wait_fence(cs, va, 1, 0xffffffff);
3349 assert(cmd_buffer->cs->cdw <= cdw_max);
3350 }
3351
3352
3353 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3354 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3355
3356 radv_handle_image_transition(cmd_buffer, image,
3357 pImageMemoryBarriers[i].oldLayout,
3358 pImageMemoryBarriers[i].newLayout,
3359 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3360 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3361 &pImageMemoryBarriers[i].subresourceRange,
3362 0);
3363 }
3364
3365 /* TODO: figure out how to do memory barriers without waiting */
3366 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3367 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3368 RADV_CMD_FLAG_INV_VMEM_L1 |
3369 RADV_CMD_FLAG_INV_SMEM_L1;
3370 }