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bed899d686e3da083ed215c77185a7de48a3eecc
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range);
61
62 const struct radv_dynamic_state default_dynamic_state = {
63 .viewport = {
64 .count = 0,
65 },
66 .scissor = {
67 .count = 0,
68 },
69 .line_width = 1.0f,
70 .depth_bias = {
71 .bias = 0.0f,
72 .clamp = 0.0f,
73 .slope = 0.0f,
74 },
75 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
76 .depth_bounds = {
77 .min = 0.0f,
78 .max = 1.0f,
79 },
80 .stencil_compare_mask = {
81 .front = ~0u,
82 .back = ~0u,
83 },
84 .stencil_write_mask = {
85 .front = ~0u,
86 .back = ~0u,
87 },
88 .stencil_reference = {
89 .front = 0u,
90 .back = 0u,
91 },
92 };
93
94 static void
95 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
96 const struct radv_dynamic_state *src)
97 {
98 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
99 uint32_t copy_mask = src->mask;
100 uint32_t dest_mask = 0;
101
102 /* Make sure to copy the number of viewports/scissors because they can
103 * only be specified at pipeline creation time.
104 */
105 dest->viewport.count = src->viewport.count;
106 dest->scissor.count = src->scissor.count;
107 dest->discard_rectangle.count = src->discard_rectangle.count;
108
109 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
110 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
111 src->viewport.count * sizeof(VkViewport))) {
112 typed_memcpy(dest->viewport.viewports,
113 src->viewport.viewports,
114 src->viewport.count);
115 dest_mask |= RADV_DYNAMIC_VIEWPORT;
116 }
117 }
118
119 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
120 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
121 src->scissor.count * sizeof(VkRect2D))) {
122 typed_memcpy(dest->scissor.scissors,
123 src->scissor.scissors, src->scissor.count);
124 dest_mask |= RADV_DYNAMIC_SCISSOR;
125 }
126 }
127
128 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
129 if (dest->line_width != src->line_width) {
130 dest->line_width = src->line_width;
131 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
132 }
133 }
134
135 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
136 if (memcmp(&dest->depth_bias, &src->depth_bias,
137 sizeof(src->depth_bias))) {
138 dest->depth_bias = src->depth_bias;
139 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
144 if (memcmp(&dest->blend_constants, &src->blend_constants,
145 sizeof(src->blend_constants))) {
146 typed_memcpy(dest->blend_constants,
147 src->blend_constants, 4);
148 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
149 }
150 }
151
152 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
153 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
154 sizeof(src->depth_bounds))) {
155 dest->depth_bounds = src->depth_bounds;
156 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
161 if (memcmp(&dest->stencil_compare_mask,
162 &src->stencil_compare_mask,
163 sizeof(src->stencil_compare_mask))) {
164 dest->stencil_compare_mask = src->stencil_compare_mask;
165 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
166 }
167 }
168
169 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
170 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
171 sizeof(src->stencil_write_mask))) {
172 dest->stencil_write_mask = src->stencil_write_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
178 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
179 sizeof(src->stencil_reference))) {
180 dest->stencil_reference = src->stencil_reference;
181 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
186 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
187 src->discard_rectangle.count * sizeof(VkRect2D))) {
188 typed_memcpy(dest->discard_rectangle.rectangles,
189 src->discard_rectangle.rectangles,
190 src->discard_rectangle.count);
191 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
192 }
193 }
194
195 cmd_buffer->state.dirty |= dest_mask;
196 }
197
198 static void
199 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
200 struct radv_pipeline *pipeline)
201 {
202 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
203 struct radv_shader_info *info;
204
205 if (!pipeline->streamout_shader)
206 return;
207
208 info = &pipeline->streamout_shader->info.info;
209 for (int i = 0; i < MAX_SO_BUFFERS; i++)
210 so->stride_in_dw[i] = info->so.strides[i];
211
212 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
213 }
214
215 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
216 {
217 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
218 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
219 }
220
221 enum ring_type radv_queue_family_to_ring(int f) {
222 switch (f) {
223 case RADV_QUEUE_GENERAL:
224 return RING_GFX;
225 case RADV_QUEUE_COMPUTE:
226 return RING_COMPUTE;
227 case RADV_QUEUE_TRANSFER:
228 return RING_DMA;
229 default:
230 unreachable("Unknown queue family");
231 }
232 }
233
234 static VkResult radv_create_cmd_buffer(
235 struct radv_device * device,
236 struct radv_cmd_pool * pool,
237 VkCommandBufferLevel level,
238 VkCommandBuffer* pCommandBuffer)
239 {
240 struct radv_cmd_buffer *cmd_buffer;
241 unsigned ring;
242 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
243 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
244 if (cmd_buffer == NULL)
245 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
246
247 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
248 cmd_buffer->device = device;
249 cmd_buffer->pool = pool;
250 cmd_buffer->level = level;
251
252 if (pool) {
253 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
254 cmd_buffer->queue_family_index = pool->queue_family_index;
255
256 } else {
257 /* Init the pool_link so we can safely call list_del when we destroy
258 * the command buffer
259 */
260 list_inithead(&cmd_buffer->pool_link);
261 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
262 }
263
264 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
265
266 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
267 if (!cmd_buffer->cs) {
268 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
269 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
270 }
271
272 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
273
274 list_inithead(&cmd_buffer->upload.list);
275
276 return VK_SUCCESS;
277 }
278
279 static void
280 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
281 {
282 list_del(&cmd_buffer->pool_link);
283
284 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
285 &cmd_buffer->upload.list, list) {
286 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
287 list_del(&up->list);
288 free(up);
289 }
290
291 if (cmd_buffer->upload.upload_bo)
292 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
293 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
294
295 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
296 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
297
298 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
299 }
300
301 static VkResult
302 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
303 {
304
305 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
306
307 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
308 &cmd_buffer->upload.list, list) {
309 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
310 list_del(&up->list);
311 free(up);
312 }
313
314 cmd_buffer->push_constant_stages = 0;
315 cmd_buffer->scratch_size_needed = 0;
316 cmd_buffer->compute_scratch_size_needed = 0;
317 cmd_buffer->esgs_ring_size_needed = 0;
318 cmd_buffer->gsvs_ring_size_needed = 0;
319 cmd_buffer->tess_rings_needed = false;
320 cmd_buffer->sample_positions_needed = false;
321
322 if (cmd_buffer->upload.upload_bo)
323 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
324 cmd_buffer->upload.upload_bo);
325 cmd_buffer->upload.offset = 0;
326
327 cmd_buffer->record_result = VK_SUCCESS;
328
329 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
330 cmd_buffer->descriptors[i].dirty = 0;
331 cmd_buffer->descriptors[i].valid = 0;
332 cmd_buffer->descriptors[i].push_dirty = false;
333 }
334
335 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
336 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
337 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
338 unsigned fence_offset, eop_bug_offset;
339 void *fence_ptr;
340
341 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
342 &fence_ptr);
343
344 cmd_buffer->gfx9_fence_va =
345 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
346 cmd_buffer->gfx9_fence_va += fence_offset;
347
348 /* Allocate a buffer for the EOP bug on GFX9. */
349 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
350 &eop_bug_offset, &fence_ptr);
351 cmd_buffer->gfx9_eop_bug_va =
352 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
353 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
354 }
355
356 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
357
358 return cmd_buffer->record_result;
359 }
360
361 static bool
362 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
363 uint64_t min_needed)
364 {
365 uint64_t new_size;
366 struct radeon_winsys_bo *bo;
367 struct radv_cmd_buffer_upload *upload;
368 struct radv_device *device = cmd_buffer->device;
369
370 new_size = MAX2(min_needed, 16 * 1024);
371 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
372
373 bo = device->ws->buffer_create(device->ws,
374 new_size, 4096,
375 RADEON_DOMAIN_GTT,
376 RADEON_FLAG_CPU_ACCESS|
377 RADEON_FLAG_NO_INTERPROCESS_SHARING |
378 RADEON_FLAG_32BIT,
379 RADV_BO_PRIORITY_UPLOAD_BUFFER);
380
381 if (!bo) {
382 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
383 return false;
384 }
385
386 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
387 if (cmd_buffer->upload.upload_bo) {
388 upload = malloc(sizeof(*upload));
389
390 if (!upload) {
391 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
392 device->ws->buffer_destroy(bo);
393 return false;
394 }
395
396 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
397 list_add(&upload->list, &cmd_buffer->upload.list);
398 }
399
400 cmd_buffer->upload.upload_bo = bo;
401 cmd_buffer->upload.size = new_size;
402 cmd_buffer->upload.offset = 0;
403 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
404
405 if (!cmd_buffer->upload.map) {
406 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
407 return false;
408 }
409
410 return true;
411 }
412
413 bool
414 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
415 unsigned size,
416 unsigned alignment,
417 unsigned *out_offset,
418 void **ptr)
419 {
420 assert(util_is_power_of_two_nonzero(alignment));
421
422 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
423 if (offset + size > cmd_buffer->upload.size) {
424 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
425 return false;
426 offset = 0;
427 }
428
429 *out_offset = offset;
430 *ptr = cmd_buffer->upload.map + offset;
431
432 cmd_buffer->upload.offset = offset + size;
433 return true;
434 }
435
436 bool
437 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
438 unsigned size, unsigned alignment,
439 const void *data, unsigned *out_offset)
440 {
441 uint8_t *ptr;
442
443 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
444 out_offset, (void **)&ptr))
445 return false;
446
447 if (ptr)
448 memcpy(ptr, data, size);
449
450 return true;
451 }
452
453 static void
454 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
455 unsigned count, const uint32_t *data)
456 {
457 struct radeon_cmdbuf *cs = cmd_buffer->cs;
458
459 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
460
461 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
462 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
463 S_370_WR_CONFIRM(1) |
464 S_370_ENGINE_SEL(V_370_ME));
465 radeon_emit(cs, va);
466 radeon_emit(cs, va >> 32);
467 radeon_emit_array(cs, data, count);
468 }
469
470 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
471 {
472 struct radv_device *device = cmd_buffer->device;
473 struct radeon_cmdbuf *cs = cmd_buffer->cs;
474 uint64_t va;
475
476 va = radv_buffer_get_va(device->trace_bo);
477 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
478 va += 4;
479
480 ++cmd_buffer->state.trace_id;
481 radv_emit_write_data_packet(cmd_buffer, va, 1,
482 &cmd_buffer->state.trace_id);
483
484 radeon_check_space(cmd_buffer->device->ws, cs, 2);
485
486 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
487 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
488 }
489
490 static void
491 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
492 enum radv_cmd_flush_bits flags)
493 {
494 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
495 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
496 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
497
498 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
499
500 /* Force wait for graphics or compute engines to be idle. */
501 si_cs_emit_cache_flush(cmd_buffer->cs,
502 cmd_buffer->device->physical_device->rad_info.chip_class,
503 &cmd_buffer->gfx9_fence_idx,
504 cmd_buffer->gfx9_fence_va,
505 radv_cmd_buffer_uses_mec(cmd_buffer),
506 flags, cmd_buffer->gfx9_eop_bug_va);
507 }
508
509 if (unlikely(cmd_buffer->device->trace_bo))
510 radv_cmd_buffer_trace_emit(cmd_buffer);
511 }
512
513 static void
514 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
515 struct radv_pipeline *pipeline, enum ring_type ring)
516 {
517 struct radv_device *device = cmd_buffer->device;
518 uint32_t data[2];
519 uint64_t va;
520
521 va = radv_buffer_get_va(device->trace_bo);
522
523 switch (ring) {
524 case RING_GFX:
525 va += 8;
526 break;
527 case RING_COMPUTE:
528 va += 16;
529 break;
530 default:
531 assert(!"invalid ring type");
532 }
533
534 data[0] = (uintptr_t)pipeline;
535 data[1] = (uintptr_t)pipeline >> 32;
536
537 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
538 }
539
540 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
541 VkPipelineBindPoint bind_point,
542 struct radv_descriptor_set *set,
543 unsigned idx)
544 {
545 struct radv_descriptor_state *descriptors_state =
546 radv_get_descriptors_state(cmd_buffer, bind_point);
547
548 descriptors_state->sets[idx] = set;
549
550 descriptors_state->valid |= (1u << idx); /* active descriptors */
551 descriptors_state->dirty |= (1u << idx);
552 }
553
554 static void
555 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
556 VkPipelineBindPoint bind_point)
557 {
558 struct radv_descriptor_state *descriptors_state =
559 radv_get_descriptors_state(cmd_buffer, bind_point);
560 struct radv_device *device = cmd_buffer->device;
561 uint32_t data[MAX_SETS * 2] = {};
562 uint64_t va;
563 unsigned i;
564 va = radv_buffer_get_va(device->trace_bo) + 24;
565
566 for_each_bit(i, descriptors_state->valid) {
567 struct radv_descriptor_set *set = descriptors_state->sets[i];
568 data[i * 2] = (uintptr_t)set;
569 data[i * 2 + 1] = (uintptr_t)set >> 32;
570 }
571
572 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
573 }
574
575 struct radv_userdata_info *
576 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
577 gl_shader_stage stage,
578 int idx)
579 {
580 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
581 return &shader->info.user_sgprs_locs.shader_data[idx];
582 }
583
584 static void
585 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
586 struct radv_pipeline *pipeline,
587 gl_shader_stage stage,
588 int idx, uint64_t va)
589 {
590 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
591 uint32_t base_reg = pipeline->user_data_0[stage];
592 if (loc->sgpr_idx == -1)
593 return;
594
595 assert(loc->num_sgprs == 1);
596
597 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
598 base_reg + loc->sgpr_idx * 4, va, false);
599 }
600
601 static void
602 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
603 struct radv_pipeline *pipeline,
604 struct radv_descriptor_state *descriptors_state,
605 gl_shader_stage stage)
606 {
607 struct radv_device *device = cmd_buffer->device;
608 struct radeon_cmdbuf *cs = cmd_buffer->cs;
609 uint32_t sh_base = pipeline->user_data_0[stage];
610 struct radv_userdata_locations *locs =
611 &pipeline->shaders[stage]->info.user_sgprs_locs;
612 unsigned mask = locs->descriptor_sets_enabled;
613
614 mask &= descriptors_state->dirty & descriptors_state->valid;
615
616 while (mask) {
617 int start, count;
618
619 u_bit_scan_consecutive_range(&mask, &start, &count);
620
621 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
622 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
623
624 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
625 for (int i = 0; i < count; i++) {
626 struct radv_descriptor_set *set =
627 descriptors_state->sets[start + i];
628
629 radv_emit_shader_pointer_body(device, cs, set->va, true);
630 }
631 }
632 }
633
634 static void
635 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
636 struct radv_pipeline *pipeline,
637 gl_shader_stage stage,
638 int idx, int count, uint32_t *values)
639 {
640 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
641 uint32_t base_reg = pipeline->user_data_0[stage];
642 if (loc->sgpr_idx == -1)
643 return;
644
645 assert(loc->num_sgprs == count);
646
647 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
648 radeon_emit_array(cmd_buffer->cs, values, count);
649 }
650
651 static void
652 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
653 struct radv_pipeline *pipeline)
654 {
655 int num_samples = pipeline->graphics.ms.num_samples;
656 struct radv_multisample_state *ms = &pipeline->graphics.ms;
657 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
658
659 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
660 cmd_buffer->sample_positions_needed = true;
661
662 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
663 return;
664
665 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
666 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
667 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
668
669 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
670
671 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
672
673 /* GFX9: Flush DFSM when the AA mode changes. */
674 if (cmd_buffer->device->dfsm_allowed) {
675 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
676 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
677 }
678
679 cmd_buffer->state.context_roll_without_scissor_emitted = true;
680 }
681
682 static void
683 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
684 struct radv_shader_variant *shader)
685 {
686 uint64_t va;
687
688 if (!shader)
689 return;
690
691 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
692
693 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
694 }
695
696 static void
697 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
698 struct radv_pipeline *pipeline,
699 bool vertex_stage_only)
700 {
701 struct radv_cmd_state *state = &cmd_buffer->state;
702 uint32_t mask = state->prefetch_L2_mask;
703
704 if (vertex_stage_only) {
705 /* Fast prefetch path for starting draws as soon as possible.
706 */
707 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
708 RADV_PREFETCH_VBO_DESCRIPTORS);
709 }
710
711 if (mask & RADV_PREFETCH_VS)
712 radv_emit_shader_prefetch(cmd_buffer,
713 pipeline->shaders[MESA_SHADER_VERTEX]);
714
715 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
716 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
717
718 if (mask & RADV_PREFETCH_TCS)
719 radv_emit_shader_prefetch(cmd_buffer,
720 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
721
722 if (mask & RADV_PREFETCH_TES)
723 radv_emit_shader_prefetch(cmd_buffer,
724 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
725
726 if (mask & RADV_PREFETCH_GS) {
727 radv_emit_shader_prefetch(cmd_buffer,
728 pipeline->shaders[MESA_SHADER_GEOMETRY]);
729 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
730 }
731
732 if (mask & RADV_PREFETCH_PS)
733 radv_emit_shader_prefetch(cmd_buffer,
734 pipeline->shaders[MESA_SHADER_FRAGMENT]);
735
736 state->prefetch_L2_mask &= ~mask;
737 }
738
739 static void
740 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
741 {
742 if (!cmd_buffer->device->physical_device->rbplus_allowed)
743 return;
744
745 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
746 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
747 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
748
749 unsigned sx_ps_downconvert = 0;
750 unsigned sx_blend_opt_epsilon = 0;
751 unsigned sx_blend_opt_control = 0;
752
753 for (unsigned i = 0; i < subpass->color_count; ++i) {
754 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
755 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
756 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
757 continue;
758 }
759
760 int idx = subpass->color_attachments[i].attachment;
761 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
762
763 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
764 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
765 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
766 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
767
768 bool has_alpha, has_rgb;
769
770 /* Set if RGB and A are present. */
771 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
772
773 if (format == V_028C70_COLOR_8 ||
774 format == V_028C70_COLOR_16 ||
775 format == V_028C70_COLOR_32)
776 has_rgb = !has_alpha;
777 else
778 has_rgb = true;
779
780 /* Check the colormask and export format. */
781 if (!(colormask & 0x7))
782 has_rgb = false;
783 if (!(colormask & 0x8))
784 has_alpha = false;
785
786 if (spi_format == V_028714_SPI_SHADER_ZERO) {
787 has_rgb = false;
788 has_alpha = false;
789 }
790
791 /* Disable value checking for disabled channels. */
792 if (!has_rgb)
793 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
794 if (!has_alpha)
795 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
796
797 /* Enable down-conversion for 32bpp and smaller formats. */
798 switch (format) {
799 case V_028C70_COLOR_8:
800 case V_028C70_COLOR_8_8:
801 case V_028C70_COLOR_8_8_8_8:
802 /* For 1 and 2-channel formats, use the superset thereof. */
803 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
804 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
805 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
806 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
807 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
808 }
809 break;
810
811 case V_028C70_COLOR_5_6_5:
812 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
813 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
814 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
815 }
816 break;
817
818 case V_028C70_COLOR_1_5_5_5:
819 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
820 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
821 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
822 }
823 break;
824
825 case V_028C70_COLOR_4_4_4_4:
826 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
827 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
828 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
829 }
830 break;
831
832 case V_028C70_COLOR_32:
833 if (swap == V_028C70_SWAP_STD &&
834 spi_format == V_028714_SPI_SHADER_32_R)
835 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
836 else if (swap == V_028C70_SWAP_ALT_REV &&
837 spi_format == V_028714_SPI_SHADER_32_AR)
838 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
839 break;
840
841 case V_028C70_COLOR_16:
842 case V_028C70_COLOR_16_16:
843 /* For 1-channel formats, use the superset thereof. */
844 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
845 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
846 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
847 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
848 if (swap == V_028C70_SWAP_STD ||
849 swap == V_028C70_SWAP_STD_REV)
850 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
851 else
852 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
853 }
854 break;
855
856 case V_028C70_COLOR_10_11_11:
857 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
858 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
859 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
860 }
861 break;
862
863 case V_028C70_COLOR_2_10_10_10:
864 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
865 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
866 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
867 }
868 break;
869 }
870 }
871
872 for (unsigned i = subpass->color_count; i < 8; ++i) {
873 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
874 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
875 }
876 /* TODO: avoid redundantly setting context registers */
877 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
878 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
879 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
880 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
881
882 cmd_buffer->state.context_roll_without_scissor_emitted = true;
883 }
884
885 static void
886 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
887 {
888 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
889
890 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
891 return;
892
893 radv_update_multisample_state(cmd_buffer, pipeline);
894
895 cmd_buffer->scratch_size_needed =
896 MAX2(cmd_buffer->scratch_size_needed,
897 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
898
899 if (!cmd_buffer->state.emitted_pipeline ||
900 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
901 pipeline->graphics.can_use_guardband)
902 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
903
904 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
905
906 if (!cmd_buffer->state.emitted_pipeline ||
907 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
908 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
909 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
910 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
911 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
912 cmd_buffer->state.context_roll_without_scissor_emitted = true;
913 }
914
915 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
916 if (!pipeline->shaders[i])
917 continue;
918
919 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
920 pipeline->shaders[i]->bo);
921 }
922
923 if (radv_pipeline_has_gs(pipeline))
924 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
925 pipeline->gs_copy_shader->bo);
926
927 if (unlikely(cmd_buffer->device->trace_bo))
928 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
929
930 cmd_buffer->state.emitted_pipeline = pipeline;
931
932 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
933 }
934
935 static void
936 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
937 {
938 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
939 cmd_buffer->state.dynamic.viewport.viewports);
940 }
941
942 static void
943 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
944 {
945 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
946
947 si_write_scissors(cmd_buffer->cs, 0, count,
948 cmd_buffer->state.dynamic.scissor.scissors,
949 cmd_buffer->state.dynamic.viewport.viewports,
950 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
951
952 cmd_buffer->state.context_roll_without_scissor_emitted = false;
953 }
954
955 static void
956 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
957 {
958 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
959 return;
960
961 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
962 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
963 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
964 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
965 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
966 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
967 S_028214_BR_Y(rect.offset.y + rect.extent.height));
968 }
969 }
970
971 static void
972 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
973 {
974 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
975
976 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
977 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
978 }
979
980 static void
981 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
982 {
983 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
984
985 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
986 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
987 }
988
989 static void
990 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
991 {
992 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
993
994 radeon_set_context_reg_seq(cmd_buffer->cs,
995 R_028430_DB_STENCILREFMASK, 2);
996 radeon_emit(cmd_buffer->cs,
997 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
998 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
999 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1000 S_028430_STENCILOPVAL(1));
1001 radeon_emit(cmd_buffer->cs,
1002 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1003 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1004 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1005 S_028434_STENCILOPVAL_BF(1));
1006 }
1007
1008 static void
1009 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1010 {
1011 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1012
1013 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1014 fui(d->depth_bounds.min));
1015 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1016 fui(d->depth_bounds.max));
1017 }
1018
1019 static void
1020 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1021 {
1022 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1023 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1024 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1025
1026
1027 radeon_set_context_reg_seq(cmd_buffer->cs,
1028 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1029 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1030 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1031 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1032 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1033 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1034 }
1035
1036 static void
1037 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1038 int index,
1039 struct radv_attachment_info *att,
1040 struct radv_image *image,
1041 VkImageLayout layout)
1042 {
1043 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1044 struct radv_color_buffer_info *cb = &att->cb;
1045 uint32_t cb_color_info = cb->cb_color_info;
1046
1047 if (!radv_layout_dcc_compressed(image, layout,
1048 radv_image_queue_family_mask(image,
1049 cmd_buffer->queue_family_index,
1050 cmd_buffer->queue_family_index))) {
1051 cb_color_info &= C_028C70_DCC_ENABLE;
1052 }
1053
1054 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1055 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1056 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1057 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1058 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1059 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1060 radeon_emit(cmd_buffer->cs, cb_color_info);
1061 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1062 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1063 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1064 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1065 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1066 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1067
1068 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1069 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1070 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1071
1072 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1073 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1074 } else {
1075 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1076 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1077 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1078 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1079 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1080 radeon_emit(cmd_buffer->cs, cb_color_info);
1081 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1082 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1083 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1084 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1085 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1086 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1087
1088 if (is_vi) { /* DCC BASE */
1089 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1090 }
1091 }
1092
1093 if (radv_image_has_dcc(image)) {
1094 /* Drawing with DCC enabled also compresses colorbuffers. */
1095 radv_update_dcc_metadata(cmd_buffer, image, true);
1096 }
1097 }
1098
1099 static void
1100 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1101 struct radv_ds_buffer_info *ds,
1102 struct radv_image *image, VkImageLayout layout,
1103 bool requires_cond_exec)
1104 {
1105 uint32_t db_z_info = ds->db_z_info;
1106 uint32_t db_z_info_reg;
1107
1108 if (!radv_image_is_tc_compat_htile(image))
1109 return;
1110
1111 if (!radv_layout_has_htile(image, layout,
1112 radv_image_queue_family_mask(image,
1113 cmd_buffer->queue_family_index,
1114 cmd_buffer->queue_family_index))) {
1115 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1116 }
1117
1118 db_z_info &= C_028040_ZRANGE_PRECISION;
1119
1120 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1121 db_z_info_reg = R_028038_DB_Z_INFO;
1122 } else {
1123 db_z_info_reg = R_028040_DB_Z_INFO;
1124 }
1125
1126 /* When we don't know the last fast clear value we need to emit a
1127 * conditional packet that will eventually skip the following
1128 * SET_CONTEXT_REG packet.
1129 */
1130 if (requires_cond_exec) {
1131 uint64_t va = radv_buffer_get_va(image->bo);
1132 va += image->offset + image->tc_compat_zrange_offset;
1133
1134 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1135 radeon_emit(cmd_buffer->cs, va);
1136 radeon_emit(cmd_buffer->cs, va >> 32);
1137 radeon_emit(cmd_buffer->cs, 0);
1138 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1139 }
1140
1141 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1142 }
1143
1144 static void
1145 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1146 struct radv_ds_buffer_info *ds,
1147 struct radv_image *image,
1148 VkImageLayout layout)
1149 {
1150 uint32_t db_z_info = ds->db_z_info;
1151 uint32_t db_stencil_info = ds->db_stencil_info;
1152
1153 if (!radv_layout_has_htile(image, layout,
1154 radv_image_queue_family_mask(image,
1155 cmd_buffer->queue_family_index,
1156 cmd_buffer->queue_family_index))) {
1157 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1158 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1159 }
1160
1161 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1162 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1163
1164
1165 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1166 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1167 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1168 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1169 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1170
1171 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1172 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1173 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1174 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1175 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1176 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1177 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1178 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1179 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1180 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1181 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1182
1183 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1184 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1185 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1186 } else {
1187 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1188
1189 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1190 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1191 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1192 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1193 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1194 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1195 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1196 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1197 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1198 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1199
1200 }
1201
1202 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1203 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1204
1205 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1206 ds->pa_su_poly_offset_db_fmt_cntl);
1207 }
1208
1209 /**
1210 * Update the fast clear depth/stencil values if the image is bound as a
1211 * depth/stencil buffer.
1212 */
1213 static void
1214 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1215 struct radv_image *image,
1216 VkClearDepthStencilValue ds_clear_value,
1217 VkImageAspectFlags aspects)
1218 {
1219 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1220 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1221 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1222 struct radv_attachment_info *att;
1223 uint32_t att_idx;
1224
1225 if (!framebuffer || !subpass)
1226 return;
1227
1228 if (!subpass->depth_stencil_attachment)
1229 return;
1230
1231 att_idx = subpass->depth_stencil_attachment->attachment;
1232 att = &framebuffer->attachments[att_idx];
1233 if (att->attachment->image != image)
1234 return;
1235
1236 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1237 radeon_emit(cs, ds_clear_value.stencil);
1238 radeon_emit(cs, fui(ds_clear_value.depth));
1239
1240 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1241 * only needed when clearing Z to 0.0.
1242 */
1243 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1244 ds_clear_value.depth == 0.0) {
1245 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1246
1247 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1248 layout, false);
1249 }
1250
1251 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1252 }
1253
1254 /**
1255 * Set the clear depth/stencil values to the image's metadata.
1256 */
1257 static void
1258 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1259 struct radv_image *image,
1260 VkClearDepthStencilValue ds_clear_value,
1261 VkImageAspectFlags aspects)
1262 {
1263 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1264 uint64_t va = radv_buffer_get_va(image->bo);
1265 unsigned reg_offset = 0, reg_count = 0;
1266
1267 va += image->offset + image->clear_value_offset;
1268
1269 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1270 ++reg_count;
1271 } else {
1272 ++reg_offset;
1273 va += 4;
1274 }
1275 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1276 ++reg_count;
1277
1278 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
1279 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1280 S_370_WR_CONFIRM(1) |
1281 S_370_ENGINE_SEL(V_370_PFP));
1282 radeon_emit(cs, va);
1283 radeon_emit(cs, va >> 32);
1284 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1285 radeon_emit(cs, ds_clear_value.stencil);
1286 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1287 radeon_emit(cs, fui(ds_clear_value.depth));
1288 }
1289
1290 /**
1291 * Update the TC-compat metadata value for this image.
1292 */
1293 static void
1294 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1295 struct radv_image *image,
1296 uint32_t value)
1297 {
1298 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1299 uint64_t va = radv_buffer_get_va(image->bo);
1300 va += image->offset + image->tc_compat_zrange_offset;
1301
1302 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1303 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1304 S_370_WR_CONFIRM(1) |
1305 S_370_ENGINE_SEL(V_370_PFP));
1306 radeon_emit(cs, va);
1307 radeon_emit(cs, va >> 32);
1308 radeon_emit(cs, value);
1309 }
1310
1311 static void
1312 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1313 struct radv_image *image,
1314 VkClearDepthStencilValue ds_clear_value)
1315 {
1316 uint64_t va = radv_buffer_get_va(image->bo);
1317 va += image->offset + image->tc_compat_zrange_offset;
1318 uint32_t cond_val;
1319
1320 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1321 * depth clear value is 0.0f.
1322 */
1323 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1324
1325 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1326 }
1327
1328 /**
1329 * Update the clear depth/stencil values for this image.
1330 */
1331 void
1332 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1333 struct radv_image *image,
1334 VkClearDepthStencilValue ds_clear_value,
1335 VkImageAspectFlags aspects)
1336 {
1337 assert(radv_image_has_htile(image));
1338
1339 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1340
1341 if (radv_image_is_tc_compat_htile(image) &&
1342 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1343 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1344 ds_clear_value);
1345 }
1346
1347 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1348 aspects);
1349 }
1350
1351 /**
1352 * Load the clear depth/stencil values from the image's metadata.
1353 */
1354 static void
1355 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1356 struct radv_image *image)
1357 {
1358 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1359 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1360 uint64_t va = radv_buffer_get_va(image->bo);
1361 unsigned reg_offset = 0, reg_count = 0;
1362
1363 va += image->offset + image->clear_value_offset;
1364
1365 if (!radv_image_has_htile(image))
1366 return;
1367
1368 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1369 ++reg_count;
1370 } else {
1371 ++reg_offset;
1372 va += 4;
1373 }
1374 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1375 ++reg_count;
1376
1377 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1378
1379 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1380 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1381 radeon_emit(cs, va);
1382 radeon_emit(cs, va >> 32);
1383 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1384 radeon_emit(cs, reg_count);
1385 } else {
1386 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1387 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1388 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1389 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1390 radeon_emit(cs, va);
1391 radeon_emit(cs, va >> 32);
1392 radeon_emit(cs, reg >> 2);
1393 radeon_emit(cs, 0);
1394
1395 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1396 radeon_emit(cs, 0);
1397 }
1398 }
1399
1400 /*
1401 * With DCC some colors don't require CMASK elimination before being
1402 * used as a texture. This sets a predicate value to determine if the
1403 * cmask eliminate is required.
1404 */
1405 void
1406 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1407 struct radv_image *image, bool value)
1408 {
1409 uint64_t pred_val = value;
1410 uint64_t va = radv_buffer_get_va(image->bo);
1411 va += image->offset + image->fce_pred_offset;
1412
1413 assert(radv_image_has_dcc(image));
1414
1415 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1416 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1417 S_370_WR_CONFIRM(1) |
1418 S_370_ENGINE_SEL(V_370_PFP));
1419 radeon_emit(cmd_buffer->cs, va);
1420 radeon_emit(cmd_buffer->cs, va >> 32);
1421 radeon_emit(cmd_buffer->cs, pred_val);
1422 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1423 }
1424
1425 /**
1426 * Update the DCC predicate to reflect the compression state.
1427 */
1428 void
1429 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1430 struct radv_image *image, bool value)
1431 {
1432 uint64_t pred_val = value;
1433 uint64_t va = radv_buffer_get_va(image->bo);
1434 va += image->offset + image->dcc_pred_offset;
1435
1436 assert(radv_image_has_dcc(image));
1437
1438 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1439 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1440 S_370_WR_CONFIRM(1) |
1441 S_370_ENGINE_SEL(V_370_PFP));
1442 radeon_emit(cmd_buffer->cs, va);
1443 radeon_emit(cmd_buffer->cs, va >> 32);
1444 radeon_emit(cmd_buffer->cs, pred_val);
1445 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1446 }
1447
1448 /**
1449 * Update the fast clear color values if the image is bound as a color buffer.
1450 */
1451 static void
1452 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1453 struct radv_image *image,
1454 int cb_idx,
1455 uint32_t color_values[2])
1456 {
1457 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1458 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1459 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1460 struct radv_attachment_info *att;
1461 uint32_t att_idx;
1462
1463 if (!framebuffer || !subpass)
1464 return;
1465
1466 att_idx = subpass->color_attachments[cb_idx].attachment;
1467 if (att_idx == VK_ATTACHMENT_UNUSED)
1468 return;
1469
1470 att = &framebuffer->attachments[att_idx];
1471 if (att->attachment->image != image)
1472 return;
1473
1474 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1475 radeon_emit(cs, color_values[0]);
1476 radeon_emit(cs, color_values[1]);
1477
1478 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1479 }
1480
1481 /**
1482 * Set the clear color values to the image's metadata.
1483 */
1484 static void
1485 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1486 struct radv_image *image,
1487 uint32_t color_values[2])
1488 {
1489 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1490 uint64_t va = radv_buffer_get_va(image->bo);
1491
1492 va += image->offset + image->clear_value_offset;
1493
1494 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1495
1496 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, cmd_buffer->state.predicating));
1497 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1498 S_370_WR_CONFIRM(1) |
1499 S_370_ENGINE_SEL(V_370_PFP));
1500 radeon_emit(cs, va);
1501 radeon_emit(cs, va >> 32);
1502 radeon_emit(cs, color_values[0]);
1503 radeon_emit(cs, color_values[1]);
1504 }
1505
1506 /**
1507 * Update the clear color values for this image.
1508 */
1509 void
1510 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1511 struct radv_image *image,
1512 int cb_idx,
1513 uint32_t color_values[2])
1514 {
1515 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1516
1517 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1518
1519 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1520 color_values);
1521 }
1522
1523 /**
1524 * Load the clear color values from the image's metadata.
1525 */
1526 static void
1527 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1528 struct radv_image *image,
1529 int cb_idx)
1530 {
1531 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1532 uint64_t va = radv_buffer_get_va(image->bo);
1533
1534 va += image->offset + image->clear_value_offset;
1535
1536 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1537 return;
1538
1539 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1540
1541 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1542 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1543 radeon_emit(cs, va);
1544 radeon_emit(cs, va >> 32);
1545 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1546 radeon_emit(cs, 2);
1547 } else {
1548 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1549 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1550 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1551 COPY_DATA_COUNT_SEL);
1552 radeon_emit(cs, va);
1553 radeon_emit(cs, va >> 32);
1554 radeon_emit(cs, reg >> 2);
1555 radeon_emit(cs, 0);
1556
1557 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1558 radeon_emit(cs, 0);
1559 }
1560 }
1561
1562 static void
1563 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1564 {
1565 int i;
1566 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1567 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1568 unsigned num_bpp64_colorbufs = 0;
1569
1570 /* this may happen for inherited secondary recording */
1571 if (!framebuffer)
1572 return;
1573
1574 for (i = 0; i < 8; ++i) {
1575 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1576 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1577 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1578 continue;
1579 }
1580
1581 int idx = subpass->color_attachments[i].attachment;
1582 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1583 struct radv_image *image = att->attachment->image;
1584 VkImageLayout layout = subpass->color_attachments[i].layout;
1585
1586 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1587
1588 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1589 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1590
1591 radv_load_color_clear_metadata(cmd_buffer, image, i);
1592
1593 if (image->surface.bpe >= 8)
1594 num_bpp64_colorbufs++;
1595 }
1596
1597 if (subpass->depth_stencil_attachment) {
1598 int idx = subpass->depth_stencil_attachment->attachment;
1599 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1600 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1601 struct radv_image *image = att->attachment->image;
1602 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1603 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1604 cmd_buffer->queue_family_index,
1605 cmd_buffer->queue_family_index);
1606 /* We currently don't support writing decompressed HTILE */
1607 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1608 radv_layout_is_htile_compressed(image, layout, queue_mask));
1609
1610 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1611
1612 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1613 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1614 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1615 }
1616 radv_load_ds_clear_metadata(cmd_buffer, image);
1617 } else {
1618 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1619 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1620 else
1621 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1622
1623 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1624 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1625 }
1626 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1627 S_028208_BR_X(framebuffer->width) |
1628 S_028208_BR_Y(framebuffer->height));
1629
1630 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1631 uint8_t watermark = 4; /* Default value for VI. */
1632
1633 /* For optimal DCC performance. */
1634 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1635 if (num_bpp64_colorbufs >= 5) {
1636 watermark = 8;
1637 } else {
1638 watermark = 6;
1639 }
1640 }
1641
1642 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1643 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1644 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1645 }
1646
1647 if (cmd_buffer->device->dfsm_allowed) {
1648 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1649 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1650 }
1651
1652 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1653 }
1654
1655 static void
1656 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1657 {
1658 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1659 struct radv_cmd_state *state = &cmd_buffer->state;
1660
1661 if (state->index_type != state->last_index_type) {
1662 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1663 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1664 2, state->index_type);
1665 } else {
1666 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1667 radeon_emit(cs, state->index_type);
1668 }
1669
1670 state->last_index_type = state->index_type;
1671 }
1672
1673 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1674 radeon_emit(cs, state->index_va);
1675 radeon_emit(cs, state->index_va >> 32);
1676
1677 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1678 radeon_emit(cs, state->max_index_count);
1679
1680 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1681 }
1682
1683 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1684 {
1685 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1686 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1687 uint32_t pa_sc_mode_cntl_1 =
1688 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1689 uint32_t db_count_control;
1690
1691 if(!cmd_buffer->state.active_occlusion_queries) {
1692 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1693 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1694 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1695 has_perfect_queries) {
1696 /* Re-enable out-of-order rasterization if the
1697 * bound pipeline supports it and if it's has
1698 * been disabled before starting any perfect
1699 * occlusion queries.
1700 */
1701 radeon_set_context_reg(cmd_buffer->cs,
1702 R_028A4C_PA_SC_MODE_CNTL_1,
1703 pa_sc_mode_cntl_1);
1704 }
1705 }
1706 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1707 } else {
1708 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1709 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1710
1711 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1712 db_count_control =
1713 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1714 S_028004_SAMPLE_RATE(sample_rate) |
1715 S_028004_ZPASS_ENABLE(1) |
1716 S_028004_SLICE_EVEN_ENABLE(1) |
1717 S_028004_SLICE_ODD_ENABLE(1);
1718
1719 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1720 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1721 has_perfect_queries) {
1722 /* If the bound pipeline has enabled
1723 * out-of-order rasterization, we should
1724 * disable it before starting any perfect
1725 * occlusion queries.
1726 */
1727 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1728
1729 radeon_set_context_reg(cmd_buffer->cs,
1730 R_028A4C_PA_SC_MODE_CNTL_1,
1731 pa_sc_mode_cntl_1);
1732 }
1733 } else {
1734 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1735 S_028004_SAMPLE_RATE(sample_rate);
1736 }
1737 }
1738
1739 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1740
1741 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1742 }
1743
1744 static void
1745 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1746 {
1747 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1748
1749 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1750 radv_emit_viewport(cmd_buffer);
1751
1752 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1753 !cmd_buffer->device->physical_device->has_scissor_bug)
1754 radv_emit_scissor(cmd_buffer);
1755
1756 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1757 radv_emit_line_width(cmd_buffer);
1758
1759 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1760 radv_emit_blend_constants(cmd_buffer);
1761
1762 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1763 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1764 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1765 radv_emit_stencil(cmd_buffer);
1766
1767 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1768 radv_emit_depth_bounds(cmd_buffer);
1769
1770 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1771 radv_emit_depth_bias(cmd_buffer);
1772
1773 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1774 radv_emit_discard_rectangle(cmd_buffer);
1775
1776 cmd_buffer->state.dirty &= ~states;
1777 }
1778
1779 static void
1780 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1781 VkPipelineBindPoint bind_point)
1782 {
1783 struct radv_descriptor_state *descriptors_state =
1784 radv_get_descriptors_state(cmd_buffer, bind_point);
1785 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1786 unsigned bo_offset;
1787
1788 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1789 set->mapped_ptr,
1790 &bo_offset))
1791 return;
1792
1793 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1794 set->va += bo_offset;
1795 }
1796
1797 static void
1798 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1799 VkPipelineBindPoint bind_point)
1800 {
1801 struct radv_descriptor_state *descriptors_state =
1802 radv_get_descriptors_state(cmd_buffer, bind_point);
1803 uint32_t size = MAX_SETS * 4;
1804 uint32_t offset;
1805 void *ptr;
1806
1807 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1808 256, &offset, &ptr))
1809 return;
1810
1811 for (unsigned i = 0; i < MAX_SETS; i++) {
1812 uint32_t *uptr = ((uint32_t *)ptr) + i;
1813 uint64_t set_va = 0;
1814 struct radv_descriptor_set *set = descriptors_state->sets[i];
1815 if (descriptors_state->valid & (1u << i))
1816 set_va = set->va;
1817 uptr[0] = set_va & 0xffffffff;
1818 }
1819
1820 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1821 va += offset;
1822
1823 if (cmd_buffer->state.pipeline) {
1824 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1825 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1826 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1827
1828 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1829 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1830 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1831
1832 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1833 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1834 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1835
1836 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1837 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1838 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1839
1840 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1841 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1842 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1843 }
1844
1845 if (cmd_buffer->state.compute_pipeline)
1846 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1847 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1848 }
1849
1850 static void
1851 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1852 VkShaderStageFlags stages)
1853 {
1854 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1855 VK_PIPELINE_BIND_POINT_COMPUTE :
1856 VK_PIPELINE_BIND_POINT_GRAPHICS;
1857 struct radv_descriptor_state *descriptors_state =
1858 radv_get_descriptors_state(cmd_buffer, bind_point);
1859 struct radv_cmd_state *state = &cmd_buffer->state;
1860 bool flush_indirect_descriptors;
1861
1862 if (!descriptors_state->dirty)
1863 return;
1864
1865 if (descriptors_state->push_dirty)
1866 radv_flush_push_descriptors(cmd_buffer, bind_point);
1867
1868 flush_indirect_descriptors =
1869 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1870 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1871 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1872 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1873
1874 if (flush_indirect_descriptors)
1875 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1876
1877 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1878 cmd_buffer->cs,
1879 MAX_SETS * MESA_SHADER_STAGES * 4);
1880
1881 if (cmd_buffer->state.pipeline) {
1882 radv_foreach_stage(stage, stages) {
1883 if (!cmd_buffer->state.pipeline->shaders[stage])
1884 continue;
1885
1886 radv_emit_descriptor_pointers(cmd_buffer,
1887 cmd_buffer->state.pipeline,
1888 descriptors_state, stage);
1889 }
1890 }
1891
1892 if (cmd_buffer->state.compute_pipeline &&
1893 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1894 radv_emit_descriptor_pointers(cmd_buffer,
1895 cmd_buffer->state.compute_pipeline,
1896 descriptors_state,
1897 MESA_SHADER_COMPUTE);
1898 }
1899
1900 descriptors_state->dirty = 0;
1901 descriptors_state->push_dirty = false;
1902
1903 assert(cmd_buffer->cs->cdw <= cdw_max);
1904
1905 if (unlikely(cmd_buffer->device->trace_bo))
1906 radv_save_descriptors(cmd_buffer, bind_point);
1907 }
1908
1909 static void
1910 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1911 VkShaderStageFlags stages)
1912 {
1913 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1914 ? cmd_buffer->state.compute_pipeline
1915 : cmd_buffer->state.pipeline;
1916 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1917 VK_PIPELINE_BIND_POINT_COMPUTE :
1918 VK_PIPELINE_BIND_POINT_GRAPHICS;
1919 struct radv_descriptor_state *descriptors_state =
1920 radv_get_descriptors_state(cmd_buffer, bind_point);
1921 struct radv_pipeline_layout *layout = pipeline->layout;
1922 struct radv_shader_variant *shader, *prev_shader;
1923 bool need_push_constants = false;
1924 unsigned offset;
1925 void *ptr;
1926 uint64_t va;
1927
1928 stages &= cmd_buffer->push_constant_stages;
1929 if (!stages ||
1930 (!layout->push_constant_size && !layout->dynamic_offset_count))
1931 return;
1932
1933 radv_foreach_stage(stage, stages) {
1934 if (!pipeline->shaders[stage])
1935 continue;
1936
1937 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
1938 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
1939
1940 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
1941 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
1942
1943 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
1944 AC_UD_INLINE_PUSH_CONSTANTS,
1945 count,
1946 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
1947 }
1948
1949 if (need_push_constants) {
1950 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1951 16 * layout->dynamic_offset_count,
1952 256, &offset, &ptr))
1953 return;
1954
1955 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1956 memcpy((char*)ptr + layout->push_constant_size,
1957 descriptors_state->dynamic_buffers,
1958 16 * layout->dynamic_offset_count);
1959
1960 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1961 va += offset;
1962
1963 MAYBE_UNUSED unsigned cdw_max =
1964 radeon_check_space(cmd_buffer->device->ws,
1965 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1966
1967 prev_shader = NULL;
1968 radv_foreach_stage(stage, stages) {
1969 shader = radv_get_shader(pipeline, stage);
1970
1971 /* Avoid redundantly emitting the address for merged stages. */
1972 if (shader && shader != prev_shader) {
1973 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1974 AC_UD_PUSH_CONSTANTS, va);
1975
1976 prev_shader = shader;
1977 }
1978 }
1979 assert(cmd_buffer->cs->cdw <= cdw_max);
1980 }
1981
1982 cmd_buffer->push_constant_stages &= ~stages;
1983 }
1984
1985 static void
1986 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1987 bool pipeline_is_dirty)
1988 {
1989 if ((pipeline_is_dirty ||
1990 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1991 cmd_buffer->state.pipeline->num_vertex_bindings &&
1992 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1993 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1994 unsigned vb_offset;
1995 void *vb_ptr;
1996 uint32_t i = 0;
1997 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
1998 uint64_t va;
1999
2000 /* allocate some descriptor state for vertex buffers */
2001 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2002 &vb_offset, &vb_ptr))
2003 return;
2004
2005 for (i = 0; i < count; i++) {
2006 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2007 uint32_t offset;
2008 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2009 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2010
2011 if (!buffer)
2012 continue;
2013
2014 va = radv_buffer_get_va(buffer->bo);
2015
2016 offset = cmd_buffer->vertex_bindings[i].offset;
2017 va += offset + buffer->offset;
2018 desc[0] = va;
2019 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2020 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
2021 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2022 else
2023 desc[2] = buffer->size - offset;
2024 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2025 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2026 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2027 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2028 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2029 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2030 }
2031
2032 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2033 va += vb_offset;
2034
2035 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2036 AC_UD_VS_VERTEX_BUFFERS, va);
2037
2038 cmd_buffer->state.vb_va = va;
2039 cmd_buffer->state.vb_size = count * 16;
2040 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2041 }
2042 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2043 }
2044
2045 static void
2046 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2047 {
2048 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2049 struct radv_userdata_info *loc;
2050 uint32_t base_reg;
2051
2052 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2053 if (!radv_get_shader(pipeline, stage))
2054 continue;
2055
2056 loc = radv_lookup_user_sgpr(pipeline, stage,
2057 AC_UD_STREAMOUT_BUFFERS);
2058 if (loc->sgpr_idx == -1)
2059 continue;
2060
2061 base_reg = pipeline->user_data_0[stage];
2062
2063 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2064 base_reg + loc->sgpr_idx * 4, va, false);
2065 }
2066
2067 if (pipeline->gs_copy_shader) {
2068 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2069 if (loc->sgpr_idx != -1) {
2070 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2071
2072 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2073 base_reg + loc->sgpr_idx * 4, va, false);
2074 }
2075 }
2076 }
2077
2078 static void
2079 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2080 {
2081 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2082 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2083 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2084 unsigned so_offset;
2085 void *so_ptr;
2086 uint64_t va;
2087
2088 /* Allocate some descriptor state for streamout buffers. */
2089 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2090 MAX_SO_BUFFERS * 16, 256,
2091 &so_offset, &so_ptr))
2092 return;
2093
2094 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2095 struct radv_buffer *buffer = sb[i].buffer;
2096 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2097
2098 if (!(so->enabled_mask & (1 << i)))
2099 continue;
2100
2101 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2102
2103 va += sb[i].offset;
2104
2105 /* Set the descriptor.
2106 *
2107 * On VI, the format must be non-INVALID, otherwise
2108 * the buffer will be considered not bound and store
2109 * instructions will be no-ops.
2110 */
2111 desc[0] = va;
2112 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2113 desc[2] = 0xffffffff;
2114 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2115 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2116 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2117 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2118 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2119 }
2120
2121 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2122 va += so_offset;
2123
2124 radv_emit_streamout_buffers(cmd_buffer, va);
2125 }
2126
2127 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2128 }
2129
2130 static void
2131 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2132 {
2133 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2134 radv_flush_streamout_descriptors(cmd_buffer);
2135 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2136 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2137 }
2138
2139 struct radv_draw_info {
2140 /**
2141 * Number of vertices.
2142 */
2143 uint32_t count;
2144
2145 /**
2146 * Index of the first vertex.
2147 */
2148 int32_t vertex_offset;
2149
2150 /**
2151 * First instance id.
2152 */
2153 uint32_t first_instance;
2154
2155 /**
2156 * Number of instances.
2157 */
2158 uint32_t instance_count;
2159
2160 /**
2161 * First index (indexed draws only).
2162 */
2163 uint32_t first_index;
2164
2165 /**
2166 * Whether it's an indexed draw.
2167 */
2168 bool indexed;
2169
2170 /**
2171 * Indirect draw parameters resource.
2172 */
2173 struct radv_buffer *indirect;
2174 uint64_t indirect_offset;
2175 uint32_t stride;
2176
2177 /**
2178 * Draw count parameters resource.
2179 */
2180 struct radv_buffer *count_buffer;
2181 uint64_t count_buffer_offset;
2182
2183 /**
2184 * Stream output parameters resource.
2185 */
2186 struct radv_buffer *strmout_buffer;
2187 uint64_t strmout_buffer_offset;
2188 };
2189
2190 static void
2191 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2192 const struct radv_draw_info *draw_info)
2193 {
2194 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2195 struct radv_cmd_state *state = &cmd_buffer->state;
2196 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2197 uint32_t ia_multi_vgt_param;
2198 int32_t primitive_reset_en;
2199
2200 /* Draw state. */
2201 ia_multi_vgt_param =
2202 si_get_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2203 draw_info->indirect,
2204 draw_info->indirect ? 0 : draw_info->count);
2205
2206 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2207 if (info->chip_class >= GFX9) {
2208 radeon_set_uconfig_reg_idx(cs,
2209 R_030960_IA_MULTI_VGT_PARAM,
2210 4, ia_multi_vgt_param);
2211 } else if (info->chip_class >= CIK) {
2212 radeon_set_context_reg_idx(cs,
2213 R_028AA8_IA_MULTI_VGT_PARAM,
2214 1, ia_multi_vgt_param);
2215 } else {
2216 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2217 ia_multi_vgt_param);
2218 }
2219 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2220 }
2221
2222 /* Primitive restart. */
2223 primitive_reset_en =
2224 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2225
2226 if (primitive_reset_en != state->last_primitive_reset_en) {
2227 state->last_primitive_reset_en = primitive_reset_en;
2228 if (info->chip_class >= GFX9) {
2229 radeon_set_uconfig_reg(cs,
2230 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2231 primitive_reset_en);
2232 } else {
2233 radeon_set_context_reg(cs,
2234 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2235 primitive_reset_en);
2236 }
2237 }
2238
2239 if (primitive_reset_en) {
2240 uint32_t primitive_reset_index =
2241 state->index_type ? 0xffffffffu : 0xffffu;
2242
2243 if (primitive_reset_index != state->last_primitive_reset_index) {
2244 radeon_set_context_reg(cs,
2245 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2246 primitive_reset_index);
2247 state->last_primitive_reset_index = primitive_reset_index;
2248 }
2249 }
2250
2251 if (draw_info->strmout_buffer) {
2252 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2253
2254 va += draw_info->strmout_buffer->offset +
2255 draw_info->strmout_buffer_offset;
2256
2257 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2258 draw_info->stride);
2259
2260 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2261 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2262 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2263 COPY_DATA_WR_CONFIRM);
2264 radeon_emit(cs, va);
2265 radeon_emit(cs, va >> 32);
2266 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2267 radeon_emit(cs, 0); /* unused */
2268
2269 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2270 }
2271 }
2272
2273 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2274 VkPipelineStageFlags src_stage_mask)
2275 {
2276 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2277 VK_PIPELINE_STAGE_TRANSFER_BIT |
2278 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2279 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2280 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2281 }
2282
2283 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2284 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2285 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2286 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2287 VK_PIPELINE_STAGE_TRANSFER_BIT |
2288 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2289 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2290 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2291 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2292 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2293 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2294 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2295 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2296 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2297 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2298 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2299 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2300 }
2301 }
2302
2303 static enum radv_cmd_flush_bits
2304 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2305 VkAccessFlags src_flags,
2306 struct radv_image *image)
2307 {
2308 bool flush_CB_meta = true, flush_DB_meta = true;
2309 enum radv_cmd_flush_bits flush_bits = 0;
2310 uint32_t b;
2311
2312 if (image) {
2313 if (!radv_image_has_CB_metadata(image))
2314 flush_CB_meta = false;
2315 if (!radv_image_has_htile(image))
2316 flush_DB_meta = false;
2317 }
2318
2319 for_each_bit(b, src_flags) {
2320 switch ((VkAccessFlagBits)(1 << b)) {
2321 case VK_ACCESS_SHADER_WRITE_BIT:
2322 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2323 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2324 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2325 break;
2326 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2327 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2328 if (flush_CB_meta)
2329 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2330 break;
2331 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2332 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2333 if (flush_DB_meta)
2334 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2335 break;
2336 case VK_ACCESS_TRANSFER_WRITE_BIT:
2337 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2338 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2339 RADV_CMD_FLAG_INV_GLOBAL_L2;
2340
2341 if (flush_CB_meta)
2342 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2343 if (flush_DB_meta)
2344 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2345 break;
2346 default:
2347 break;
2348 }
2349 }
2350 return flush_bits;
2351 }
2352
2353 static enum radv_cmd_flush_bits
2354 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2355 VkAccessFlags dst_flags,
2356 struct radv_image *image)
2357 {
2358 bool flush_CB_meta = true, flush_DB_meta = true;
2359 enum radv_cmd_flush_bits flush_bits = 0;
2360 bool flush_CB = true, flush_DB = true;
2361 bool image_is_coherent = false;
2362 uint32_t b;
2363
2364 if (image) {
2365 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2366 flush_CB = false;
2367 flush_DB = false;
2368 }
2369
2370 if (!radv_image_has_CB_metadata(image))
2371 flush_CB_meta = false;
2372 if (!radv_image_has_htile(image))
2373 flush_DB_meta = false;
2374
2375 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2376 if (image->info.samples == 1 &&
2377 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2378 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2379 !vk_format_is_stencil(image->vk_format)) {
2380 /* Single-sample color and single-sample depth
2381 * (not stencil) are coherent with shaders on
2382 * GFX9.
2383 */
2384 image_is_coherent = true;
2385 }
2386 }
2387 }
2388
2389 for_each_bit(b, dst_flags) {
2390 switch ((VkAccessFlagBits)(1 << b)) {
2391 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2392 case VK_ACCESS_INDEX_READ_BIT:
2393 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2394 break;
2395 case VK_ACCESS_UNIFORM_READ_BIT:
2396 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2397 break;
2398 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2399 case VK_ACCESS_TRANSFER_READ_BIT:
2400 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2401 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2402 RADV_CMD_FLAG_INV_GLOBAL_L2;
2403 break;
2404 case VK_ACCESS_SHADER_READ_BIT:
2405 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2406
2407 if (!image_is_coherent)
2408 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2409 break;
2410 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2411 if (flush_CB)
2412 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2413 if (flush_CB_meta)
2414 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2415 break;
2416 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2417 if (flush_DB)
2418 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2419 if (flush_DB_meta)
2420 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2421 break;
2422 default:
2423 break;
2424 }
2425 }
2426 return flush_bits;
2427 }
2428
2429 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2430 const struct radv_subpass_barrier *barrier)
2431 {
2432 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2433 NULL);
2434 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2435 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2436 NULL);
2437 }
2438
2439 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2440 struct radv_subpass_attachment att)
2441 {
2442 unsigned idx = att.attachment;
2443 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2444 VkImageSubresourceRange range;
2445 range.aspectMask = 0;
2446 range.baseMipLevel = view->base_mip;
2447 range.levelCount = 1;
2448 range.baseArrayLayer = view->base_layer;
2449 range.layerCount = cmd_buffer->state.framebuffer->layers;
2450
2451 if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
2452 /* If the current subpass uses multiview, the driver might have
2453 * performed a fast color/depth clear to the whole image
2454 * (including all layers). To make sure the driver will
2455 * decompress the image correctly (if needed), we have to
2456 * account for the "real" number of layers. If the view mask is
2457 * sparse, this will decompress more layers than needed.
2458 */
2459 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2460 }
2461
2462 radv_handle_image_transition(cmd_buffer,
2463 view->image,
2464 cmd_buffer->state.attachments[idx].current_layout,
2465 att.layout, 0, 0, &range);
2466
2467 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2468
2469
2470 }
2471
2472 void
2473 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2474 const struct radv_subpass *subpass)
2475 {
2476 cmd_buffer->state.subpass = subpass;
2477
2478 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2479 }
2480
2481 static VkResult
2482 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2483 struct radv_render_pass *pass,
2484 const VkRenderPassBeginInfo *info)
2485 {
2486 struct radv_cmd_state *state = &cmd_buffer->state;
2487
2488 if (pass->attachment_count == 0) {
2489 state->attachments = NULL;
2490 return VK_SUCCESS;
2491 }
2492
2493 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2494 pass->attachment_count *
2495 sizeof(state->attachments[0]),
2496 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2497 if (state->attachments == NULL) {
2498 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2499 return cmd_buffer->record_result;
2500 }
2501
2502 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2503 struct radv_render_pass_attachment *att = &pass->attachments[i];
2504 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2505 VkImageAspectFlags clear_aspects = 0;
2506
2507 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2508 /* color attachment */
2509 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2510 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2511 }
2512 } else {
2513 /* depthstencil attachment */
2514 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2515 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2516 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2517 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2518 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2519 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2520 }
2521 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2522 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2523 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2524 }
2525 }
2526
2527 state->attachments[i].pending_clear_aspects = clear_aspects;
2528 state->attachments[i].cleared_views = 0;
2529 if (clear_aspects && info) {
2530 assert(info->clearValueCount > i);
2531 state->attachments[i].clear_value = info->pClearValues[i];
2532 }
2533
2534 state->attachments[i].current_layout = att->initial_layout;
2535 }
2536
2537 return VK_SUCCESS;
2538 }
2539
2540 VkResult radv_AllocateCommandBuffers(
2541 VkDevice _device,
2542 const VkCommandBufferAllocateInfo *pAllocateInfo,
2543 VkCommandBuffer *pCommandBuffers)
2544 {
2545 RADV_FROM_HANDLE(radv_device, device, _device);
2546 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2547
2548 VkResult result = VK_SUCCESS;
2549 uint32_t i;
2550
2551 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2552
2553 if (!list_empty(&pool->free_cmd_buffers)) {
2554 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2555
2556 list_del(&cmd_buffer->pool_link);
2557 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2558
2559 result = radv_reset_cmd_buffer(cmd_buffer);
2560 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2561 cmd_buffer->level = pAllocateInfo->level;
2562
2563 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2564 } else {
2565 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2566 &pCommandBuffers[i]);
2567 }
2568 if (result != VK_SUCCESS)
2569 break;
2570 }
2571
2572 if (result != VK_SUCCESS) {
2573 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2574 i, pCommandBuffers);
2575
2576 /* From the Vulkan 1.0.66 spec:
2577 *
2578 * "vkAllocateCommandBuffers can be used to create multiple
2579 * command buffers. If the creation of any of those command
2580 * buffers fails, the implementation must destroy all
2581 * successfully created command buffer objects from this
2582 * command, set all entries of the pCommandBuffers array to
2583 * NULL and return the error."
2584 */
2585 memset(pCommandBuffers, 0,
2586 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2587 }
2588
2589 return result;
2590 }
2591
2592 void radv_FreeCommandBuffers(
2593 VkDevice device,
2594 VkCommandPool commandPool,
2595 uint32_t commandBufferCount,
2596 const VkCommandBuffer *pCommandBuffers)
2597 {
2598 for (uint32_t i = 0; i < commandBufferCount; i++) {
2599 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2600
2601 if (cmd_buffer) {
2602 if (cmd_buffer->pool) {
2603 list_del(&cmd_buffer->pool_link);
2604 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2605 } else
2606 radv_cmd_buffer_destroy(cmd_buffer);
2607
2608 }
2609 }
2610 }
2611
2612 VkResult radv_ResetCommandBuffer(
2613 VkCommandBuffer commandBuffer,
2614 VkCommandBufferResetFlags flags)
2615 {
2616 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2617 return radv_reset_cmd_buffer(cmd_buffer);
2618 }
2619
2620 VkResult radv_BeginCommandBuffer(
2621 VkCommandBuffer commandBuffer,
2622 const VkCommandBufferBeginInfo *pBeginInfo)
2623 {
2624 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2625 VkResult result = VK_SUCCESS;
2626
2627 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2628 /* If the command buffer has already been resetted with
2629 * vkResetCommandBuffer, no need to do it again.
2630 */
2631 result = radv_reset_cmd_buffer(cmd_buffer);
2632 if (result != VK_SUCCESS)
2633 return result;
2634 }
2635
2636 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2637 cmd_buffer->state.last_primitive_reset_en = -1;
2638 cmd_buffer->state.last_index_type = -1;
2639 cmd_buffer->state.last_num_instances = -1;
2640 cmd_buffer->state.last_vertex_offset = -1;
2641 cmd_buffer->state.last_first_instance = -1;
2642 cmd_buffer->state.predication_type = -1;
2643 cmd_buffer->usage_flags = pBeginInfo->flags;
2644
2645 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2646 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2647 assert(pBeginInfo->pInheritanceInfo);
2648 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2649 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2650
2651 struct radv_subpass *subpass =
2652 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2653
2654 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2655 if (result != VK_SUCCESS)
2656 return result;
2657
2658 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
2659 }
2660
2661 if (unlikely(cmd_buffer->device->trace_bo)) {
2662 struct radv_device *device = cmd_buffer->device;
2663
2664 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2665 device->trace_bo);
2666
2667 radv_cmd_buffer_trace_emit(cmd_buffer);
2668 }
2669
2670 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2671
2672 return result;
2673 }
2674
2675 void radv_CmdBindVertexBuffers(
2676 VkCommandBuffer commandBuffer,
2677 uint32_t firstBinding,
2678 uint32_t bindingCount,
2679 const VkBuffer* pBuffers,
2680 const VkDeviceSize* pOffsets)
2681 {
2682 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2683 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2684 bool changed = false;
2685
2686 /* We have to defer setting up vertex buffer since we need the buffer
2687 * stride from the pipeline. */
2688
2689 assert(firstBinding + bindingCount <= MAX_VBS);
2690 for (uint32_t i = 0; i < bindingCount; i++) {
2691 uint32_t idx = firstBinding + i;
2692
2693 if (!changed &&
2694 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2695 vb[idx].offset != pOffsets[i])) {
2696 changed = true;
2697 }
2698
2699 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2700 vb[idx].offset = pOffsets[i];
2701
2702 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2703 vb[idx].buffer->bo);
2704 }
2705
2706 if (!changed) {
2707 /* No state changes. */
2708 return;
2709 }
2710
2711 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2712 }
2713
2714 void radv_CmdBindIndexBuffer(
2715 VkCommandBuffer commandBuffer,
2716 VkBuffer buffer,
2717 VkDeviceSize offset,
2718 VkIndexType indexType)
2719 {
2720 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2721 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2722
2723 if (cmd_buffer->state.index_buffer == index_buffer &&
2724 cmd_buffer->state.index_offset == offset &&
2725 cmd_buffer->state.index_type == indexType) {
2726 /* No state changes. */
2727 return;
2728 }
2729
2730 cmd_buffer->state.index_buffer = index_buffer;
2731 cmd_buffer->state.index_offset = offset;
2732 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2733 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2734 cmd_buffer->state.index_va += index_buffer->offset + offset;
2735
2736 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2737 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2738 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2739 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2740 }
2741
2742
2743 static void
2744 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2745 VkPipelineBindPoint bind_point,
2746 struct radv_descriptor_set *set, unsigned idx)
2747 {
2748 struct radeon_winsys *ws = cmd_buffer->device->ws;
2749
2750 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2751
2752 assert(set);
2753 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2754
2755 if (!cmd_buffer->device->use_global_bo_list) {
2756 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2757 if (set->descriptors[j])
2758 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2759 }
2760
2761 if(set->bo)
2762 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2763 }
2764
2765 void radv_CmdBindDescriptorSets(
2766 VkCommandBuffer commandBuffer,
2767 VkPipelineBindPoint pipelineBindPoint,
2768 VkPipelineLayout _layout,
2769 uint32_t firstSet,
2770 uint32_t descriptorSetCount,
2771 const VkDescriptorSet* pDescriptorSets,
2772 uint32_t dynamicOffsetCount,
2773 const uint32_t* pDynamicOffsets)
2774 {
2775 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2776 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2777 unsigned dyn_idx = 0;
2778
2779 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2780 struct radv_descriptor_state *descriptors_state =
2781 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2782
2783 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2784 unsigned idx = i + firstSet;
2785 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2786 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2787
2788 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2789 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2790 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2791 assert(dyn_idx < dynamicOffsetCount);
2792
2793 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2794 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2795 dst[0] = va;
2796 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2797 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2798 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2799 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2800 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2801 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2802 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2803 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2804 cmd_buffer->push_constant_stages |=
2805 set->layout->dynamic_shader_stages;
2806 }
2807 }
2808 }
2809
2810 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2811 struct radv_descriptor_set *set,
2812 struct radv_descriptor_set_layout *layout,
2813 VkPipelineBindPoint bind_point)
2814 {
2815 struct radv_descriptor_state *descriptors_state =
2816 radv_get_descriptors_state(cmd_buffer, bind_point);
2817 set->size = layout->size;
2818 set->layout = layout;
2819
2820 if (descriptors_state->push_set.capacity < set->size) {
2821 size_t new_size = MAX2(set->size, 1024);
2822 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2823 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2824
2825 free(set->mapped_ptr);
2826 set->mapped_ptr = malloc(new_size);
2827
2828 if (!set->mapped_ptr) {
2829 descriptors_state->push_set.capacity = 0;
2830 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2831 return false;
2832 }
2833
2834 descriptors_state->push_set.capacity = new_size;
2835 }
2836
2837 return true;
2838 }
2839
2840 void radv_meta_push_descriptor_set(
2841 struct radv_cmd_buffer* cmd_buffer,
2842 VkPipelineBindPoint pipelineBindPoint,
2843 VkPipelineLayout _layout,
2844 uint32_t set,
2845 uint32_t descriptorWriteCount,
2846 const VkWriteDescriptorSet* pDescriptorWrites)
2847 {
2848 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2849 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2850 unsigned bo_offset;
2851
2852 assert(set == 0);
2853 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2854
2855 push_set->size = layout->set[set].layout->size;
2856 push_set->layout = layout->set[set].layout;
2857
2858 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2859 &bo_offset,
2860 (void**) &push_set->mapped_ptr))
2861 return;
2862
2863 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2864 push_set->va += bo_offset;
2865
2866 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2867 radv_descriptor_set_to_handle(push_set),
2868 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2869
2870 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2871 }
2872
2873 void radv_CmdPushDescriptorSetKHR(
2874 VkCommandBuffer commandBuffer,
2875 VkPipelineBindPoint pipelineBindPoint,
2876 VkPipelineLayout _layout,
2877 uint32_t set,
2878 uint32_t descriptorWriteCount,
2879 const VkWriteDescriptorSet* pDescriptorWrites)
2880 {
2881 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2882 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2883 struct radv_descriptor_state *descriptors_state =
2884 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2885 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2886
2887 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2888
2889 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2890 layout->set[set].layout,
2891 pipelineBindPoint))
2892 return;
2893
2894 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2895 radv_descriptor_set_to_handle(push_set),
2896 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2897
2898 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2899 descriptors_state->push_dirty = true;
2900 }
2901
2902 void radv_CmdPushDescriptorSetWithTemplateKHR(
2903 VkCommandBuffer commandBuffer,
2904 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2905 VkPipelineLayout _layout,
2906 uint32_t set,
2907 const void* pData)
2908 {
2909 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2910 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2911 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2912 struct radv_descriptor_state *descriptors_state =
2913 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2914 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2915
2916 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2917
2918 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2919 layout->set[set].layout,
2920 templ->bind_point))
2921 return;
2922
2923 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2924 descriptorUpdateTemplate, pData);
2925
2926 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2927 descriptors_state->push_dirty = true;
2928 }
2929
2930 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2931 VkPipelineLayout layout,
2932 VkShaderStageFlags stageFlags,
2933 uint32_t offset,
2934 uint32_t size,
2935 const void* pValues)
2936 {
2937 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2938 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2939 cmd_buffer->push_constant_stages |= stageFlags;
2940 }
2941
2942 VkResult radv_EndCommandBuffer(
2943 VkCommandBuffer commandBuffer)
2944 {
2945 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2946
2947 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2948 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2949 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2950 si_emit_cache_flush(cmd_buffer);
2951 }
2952
2953 /* Make sure CP DMA is idle at the end of IBs because the kernel
2954 * doesn't wait for it.
2955 */
2956 si_cp_dma_wait_for_idle(cmd_buffer);
2957
2958 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2959
2960 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2961 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2962
2963 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2964
2965 return cmd_buffer->record_result;
2966 }
2967
2968 static void
2969 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2970 {
2971 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2972
2973 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2974 return;
2975
2976 assert(!pipeline->ctx_cs.cdw);
2977
2978 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2979
2980 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2981 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2982
2983 cmd_buffer->compute_scratch_size_needed =
2984 MAX2(cmd_buffer->compute_scratch_size_needed,
2985 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2986
2987 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2988 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2989
2990 if (unlikely(cmd_buffer->device->trace_bo))
2991 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2992 }
2993
2994 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2995 VkPipelineBindPoint bind_point)
2996 {
2997 struct radv_descriptor_state *descriptors_state =
2998 radv_get_descriptors_state(cmd_buffer, bind_point);
2999
3000 descriptors_state->dirty |= descriptors_state->valid;
3001 }
3002
3003 void radv_CmdBindPipeline(
3004 VkCommandBuffer commandBuffer,
3005 VkPipelineBindPoint pipelineBindPoint,
3006 VkPipeline _pipeline)
3007 {
3008 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3009 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3010
3011 switch (pipelineBindPoint) {
3012 case VK_PIPELINE_BIND_POINT_COMPUTE:
3013 if (cmd_buffer->state.compute_pipeline == pipeline)
3014 return;
3015 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3016
3017 cmd_buffer->state.compute_pipeline = pipeline;
3018 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3019 break;
3020 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3021 if (cmd_buffer->state.pipeline == pipeline)
3022 return;
3023 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3024
3025 cmd_buffer->state.pipeline = pipeline;
3026 if (!pipeline)
3027 break;
3028
3029 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3030 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3031
3032 /* the new vertex shader might not have the same user regs */
3033 cmd_buffer->state.last_first_instance = -1;
3034 cmd_buffer->state.last_vertex_offset = -1;
3035
3036 /* Prefetch all pipeline shaders at first draw time. */
3037 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3038
3039 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3040 radv_bind_streamout_state(cmd_buffer, pipeline);
3041
3042 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3043 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3044 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3045 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3046
3047 if (radv_pipeline_has_tess(pipeline))
3048 cmd_buffer->tess_rings_needed = true;
3049 break;
3050 default:
3051 assert(!"invalid bind point");
3052 break;
3053 }
3054 }
3055
3056 void radv_CmdSetViewport(
3057 VkCommandBuffer commandBuffer,
3058 uint32_t firstViewport,
3059 uint32_t viewportCount,
3060 const VkViewport* pViewports)
3061 {
3062 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3063 struct radv_cmd_state *state = &cmd_buffer->state;
3064 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3065
3066 assert(firstViewport < MAX_VIEWPORTS);
3067 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3068
3069 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3070 pViewports, viewportCount * sizeof(*pViewports))) {
3071 return;
3072 }
3073
3074 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3075 viewportCount * sizeof(*pViewports));
3076
3077 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3078 }
3079
3080 void radv_CmdSetScissor(
3081 VkCommandBuffer commandBuffer,
3082 uint32_t firstScissor,
3083 uint32_t scissorCount,
3084 const VkRect2D* pScissors)
3085 {
3086 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3087 struct radv_cmd_state *state = &cmd_buffer->state;
3088 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3089
3090 assert(firstScissor < MAX_SCISSORS);
3091 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3092
3093 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3094 scissorCount * sizeof(*pScissors))) {
3095 return;
3096 }
3097
3098 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3099 scissorCount * sizeof(*pScissors));
3100
3101 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3102 }
3103
3104 void radv_CmdSetLineWidth(
3105 VkCommandBuffer commandBuffer,
3106 float lineWidth)
3107 {
3108 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3109
3110 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3111 return;
3112
3113 cmd_buffer->state.dynamic.line_width = lineWidth;
3114 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3115 }
3116
3117 void radv_CmdSetDepthBias(
3118 VkCommandBuffer commandBuffer,
3119 float depthBiasConstantFactor,
3120 float depthBiasClamp,
3121 float depthBiasSlopeFactor)
3122 {
3123 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3124 struct radv_cmd_state *state = &cmd_buffer->state;
3125
3126 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3127 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3128 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3129 return;
3130 }
3131
3132 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3133 state->dynamic.depth_bias.clamp = depthBiasClamp;
3134 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3135
3136 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3137 }
3138
3139 void radv_CmdSetBlendConstants(
3140 VkCommandBuffer commandBuffer,
3141 const float blendConstants[4])
3142 {
3143 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3144 struct radv_cmd_state *state = &cmd_buffer->state;
3145
3146 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3147 return;
3148
3149 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3150
3151 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3152 }
3153
3154 void radv_CmdSetDepthBounds(
3155 VkCommandBuffer commandBuffer,
3156 float minDepthBounds,
3157 float maxDepthBounds)
3158 {
3159 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3160 struct radv_cmd_state *state = &cmd_buffer->state;
3161
3162 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3163 state->dynamic.depth_bounds.max == maxDepthBounds) {
3164 return;
3165 }
3166
3167 state->dynamic.depth_bounds.min = minDepthBounds;
3168 state->dynamic.depth_bounds.max = maxDepthBounds;
3169
3170 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3171 }
3172
3173 void radv_CmdSetStencilCompareMask(
3174 VkCommandBuffer commandBuffer,
3175 VkStencilFaceFlags faceMask,
3176 uint32_t compareMask)
3177 {
3178 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3179 struct radv_cmd_state *state = &cmd_buffer->state;
3180 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3181 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3182
3183 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3184 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3185 return;
3186 }
3187
3188 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3189 state->dynamic.stencil_compare_mask.front = compareMask;
3190 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3191 state->dynamic.stencil_compare_mask.back = compareMask;
3192
3193 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3194 }
3195
3196 void radv_CmdSetStencilWriteMask(
3197 VkCommandBuffer commandBuffer,
3198 VkStencilFaceFlags faceMask,
3199 uint32_t writeMask)
3200 {
3201 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3202 struct radv_cmd_state *state = &cmd_buffer->state;
3203 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3204 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3205
3206 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3207 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3208 return;
3209 }
3210
3211 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3212 state->dynamic.stencil_write_mask.front = writeMask;
3213 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3214 state->dynamic.stencil_write_mask.back = writeMask;
3215
3216 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3217 }
3218
3219 void radv_CmdSetStencilReference(
3220 VkCommandBuffer commandBuffer,
3221 VkStencilFaceFlags faceMask,
3222 uint32_t reference)
3223 {
3224 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3225 struct radv_cmd_state *state = &cmd_buffer->state;
3226 bool front_same = state->dynamic.stencil_reference.front == reference;
3227 bool back_same = state->dynamic.stencil_reference.back == reference;
3228
3229 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3230 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3231 return;
3232 }
3233
3234 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3235 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3236 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3237 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3238
3239 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3240 }
3241
3242 void radv_CmdSetDiscardRectangleEXT(
3243 VkCommandBuffer commandBuffer,
3244 uint32_t firstDiscardRectangle,
3245 uint32_t discardRectangleCount,
3246 const VkRect2D* pDiscardRectangles)
3247 {
3248 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3249 struct radv_cmd_state *state = &cmd_buffer->state;
3250 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3251
3252 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3253 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3254
3255 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3256 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3257 return;
3258 }
3259
3260 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3261 pDiscardRectangles, discardRectangleCount);
3262
3263 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3264 }
3265
3266 void radv_CmdExecuteCommands(
3267 VkCommandBuffer commandBuffer,
3268 uint32_t commandBufferCount,
3269 const VkCommandBuffer* pCmdBuffers)
3270 {
3271 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3272
3273 assert(commandBufferCount > 0);
3274
3275 /* Emit pending flushes on primary prior to executing secondary */
3276 si_emit_cache_flush(primary);
3277
3278 for (uint32_t i = 0; i < commandBufferCount; i++) {
3279 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3280
3281 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3282 secondary->scratch_size_needed);
3283 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3284 secondary->compute_scratch_size_needed);
3285
3286 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3287 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3288 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3289 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3290 if (secondary->tess_rings_needed)
3291 primary->tess_rings_needed = true;
3292 if (secondary->sample_positions_needed)
3293 primary->sample_positions_needed = true;
3294
3295 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3296
3297
3298 /* When the secondary command buffer is compute only we don't
3299 * need to re-emit the current graphics pipeline.
3300 */
3301 if (secondary->state.emitted_pipeline) {
3302 primary->state.emitted_pipeline =
3303 secondary->state.emitted_pipeline;
3304 }
3305
3306 /* When the secondary command buffer is graphics only we don't
3307 * need to re-emit the current compute pipeline.
3308 */
3309 if (secondary->state.emitted_compute_pipeline) {
3310 primary->state.emitted_compute_pipeline =
3311 secondary->state.emitted_compute_pipeline;
3312 }
3313
3314 /* Only re-emit the draw packets when needed. */
3315 if (secondary->state.last_primitive_reset_en != -1) {
3316 primary->state.last_primitive_reset_en =
3317 secondary->state.last_primitive_reset_en;
3318 }
3319
3320 if (secondary->state.last_primitive_reset_index) {
3321 primary->state.last_primitive_reset_index =
3322 secondary->state.last_primitive_reset_index;
3323 }
3324
3325 if (secondary->state.last_ia_multi_vgt_param) {
3326 primary->state.last_ia_multi_vgt_param =
3327 secondary->state.last_ia_multi_vgt_param;
3328 }
3329
3330 primary->state.last_first_instance = secondary->state.last_first_instance;
3331 primary->state.last_num_instances = secondary->state.last_num_instances;
3332 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3333
3334 if (secondary->state.last_index_type != -1) {
3335 primary->state.last_index_type =
3336 secondary->state.last_index_type;
3337 }
3338 }
3339
3340 /* After executing commands from secondary buffers we have to dirty
3341 * some states.
3342 */
3343 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3344 RADV_CMD_DIRTY_INDEX_BUFFER |
3345 RADV_CMD_DIRTY_DYNAMIC_ALL;
3346 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3347 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3348 }
3349
3350 VkResult radv_CreateCommandPool(
3351 VkDevice _device,
3352 const VkCommandPoolCreateInfo* pCreateInfo,
3353 const VkAllocationCallbacks* pAllocator,
3354 VkCommandPool* pCmdPool)
3355 {
3356 RADV_FROM_HANDLE(radv_device, device, _device);
3357 struct radv_cmd_pool *pool;
3358
3359 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3360 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3361 if (pool == NULL)
3362 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3363
3364 if (pAllocator)
3365 pool->alloc = *pAllocator;
3366 else
3367 pool->alloc = device->alloc;
3368
3369 list_inithead(&pool->cmd_buffers);
3370 list_inithead(&pool->free_cmd_buffers);
3371
3372 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3373
3374 *pCmdPool = radv_cmd_pool_to_handle(pool);
3375
3376 return VK_SUCCESS;
3377
3378 }
3379
3380 void radv_DestroyCommandPool(
3381 VkDevice _device,
3382 VkCommandPool commandPool,
3383 const VkAllocationCallbacks* pAllocator)
3384 {
3385 RADV_FROM_HANDLE(radv_device, device, _device);
3386 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3387
3388 if (!pool)
3389 return;
3390
3391 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3392 &pool->cmd_buffers, pool_link) {
3393 radv_cmd_buffer_destroy(cmd_buffer);
3394 }
3395
3396 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3397 &pool->free_cmd_buffers, pool_link) {
3398 radv_cmd_buffer_destroy(cmd_buffer);
3399 }
3400
3401 vk_free2(&device->alloc, pAllocator, pool);
3402 }
3403
3404 VkResult radv_ResetCommandPool(
3405 VkDevice device,
3406 VkCommandPool commandPool,
3407 VkCommandPoolResetFlags flags)
3408 {
3409 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3410 VkResult result;
3411
3412 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3413 &pool->cmd_buffers, pool_link) {
3414 result = radv_reset_cmd_buffer(cmd_buffer);
3415 if (result != VK_SUCCESS)
3416 return result;
3417 }
3418
3419 return VK_SUCCESS;
3420 }
3421
3422 void radv_TrimCommandPool(
3423 VkDevice device,
3424 VkCommandPool commandPool,
3425 VkCommandPoolTrimFlags flags)
3426 {
3427 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3428
3429 if (!pool)
3430 return;
3431
3432 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3433 &pool->free_cmd_buffers, pool_link) {
3434 radv_cmd_buffer_destroy(cmd_buffer);
3435 }
3436 }
3437
3438 static uint32_t
3439 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3440 {
3441 struct radv_cmd_state *state = &cmd_buffer->state;
3442 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3443
3444 /* The id of this subpass shouldn't exceed the number of subpasses in
3445 * this render pass minus 1.
3446 */
3447 assert(subpass_id < state->pass->subpass_count);
3448 return subpass_id;
3449 }
3450
3451 static void
3452 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
3453 uint32_t subpass_id)
3454 {
3455 struct radv_cmd_state *state = &cmd_buffer->state;
3456 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
3457
3458 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3459 cmd_buffer->cs, 4096);
3460
3461 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
3462
3463 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3464 const uint32_t a = subpass->attachments[i].attachment;
3465 if (a == VK_ATTACHMENT_UNUSED)
3466 continue;
3467
3468 radv_handle_subpass_image_transition(cmd_buffer,
3469 subpass->attachments[i]);
3470 }
3471
3472 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3473 radv_cmd_buffer_clear_subpass(cmd_buffer);
3474
3475 assert(cmd_buffer->cs->cdw <= cdw_max);
3476 }
3477
3478 static void
3479 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
3480 {
3481 struct radv_cmd_state *state = &cmd_buffer->state;
3482 const struct radv_subpass *subpass = state->subpass;
3483 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3484
3485 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3486
3487 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3488 const uint32_t a = subpass->attachments[i].attachment;
3489 if (a == VK_ATTACHMENT_UNUSED)
3490 continue;
3491
3492 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
3493 continue;
3494
3495 VkImageLayout layout = state->pass->attachments[a].final_layout;
3496 radv_handle_subpass_image_transition(cmd_buffer,
3497 (struct radv_subpass_attachment){a, layout});
3498 }
3499 }
3500
3501 void radv_CmdBeginRenderPass(
3502 VkCommandBuffer commandBuffer,
3503 const VkRenderPassBeginInfo* pRenderPassBegin,
3504 VkSubpassContents contents)
3505 {
3506 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3507 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3508 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3509 VkResult result;
3510
3511 cmd_buffer->state.framebuffer = framebuffer;
3512 cmd_buffer->state.pass = pass;
3513 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3514
3515 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3516 if (result != VK_SUCCESS)
3517 return;
3518
3519 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
3520 }
3521
3522 void radv_CmdBeginRenderPass2KHR(
3523 VkCommandBuffer commandBuffer,
3524 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3525 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3526 {
3527 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3528 pSubpassBeginInfo->contents);
3529 }
3530
3531 void radv_CmdNextSubpass(
3532 VkCommandBuffer commandBuffer,
3533 VkSubpassContents contents)
3534 {
3535 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3536
3537 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
3538 radv_cmd_buffer_end_subpass(cmd_buffer);
3539 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
3540 }
3541
3542 void radv_CmdNextSubpass2KHR(
3543 VkCommandBuffer commandBuffer,
3544 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3545 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3546 {
3547 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3548 }
3549
3550 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3551 {
3552 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3553 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3554 if (!radv_get_shader(pipeline, stage))
3555 continue;
3556
3557 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3558 if (loc->sgpr_idx == -1)
3559 continue;
3560 uint32_t base_reg = pipeline->user_data_0[stage];
3561 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3562
3563 }
3564 if (pipeline->gs_copy_shader) {
3565 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3566 if (loc->sgpr_idx != -1) {
3567 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3568 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3569 }
3570 }
3571 }
3572
3573 static void
3574 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3575 uint32_t vertex_count,
3576 bool use_opaque)
3577 {
3578 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3579 radeon_emit(cmd_buffer->cs, vertex_count);
3580 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3581 S_0287F0_USE_OPAQUE(use_opaque));
3582 }
3583
3584 static void
3585 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3586 uint64_t index_va,
3587 uint32_t index_count)
3588 {
3589 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3590 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3591 radeon_emit(cmd_buffer->cs, index_va);
3592 radeon_emit(cmd_buffer->cs, index_va >> 32);
3593 radeon_emit(cmd_buffer->cs, index_count);
3594 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3595 }
3596
3597 static void
3598 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3599 bool indexed,
3600 uint32_t draw_count,
3601 uint64_t count_va,
3602 uint32_t stride)
3603 {
3604 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3605 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3606 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3607 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3608 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3609 bool predicating = cmd_buffer->state.predicating;
3610 assert(base_reg);
3611
3612 /* just reset draw state for vertex data */
3613 cmd_buffer->state.last_first_instance = -1;
3614 cmd_buffer->state.last_num_instances = -1;
3615 cmd_buffer->state.last_vertex_offset = -1;
3616
3617 if (draw_count == 1 && !count_va && !draw_id_enable) {
3618 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3619 PKT3_DRAW_INDIRECT, 3, predicating));
3620 radeon_emit(cs, 0);
3621 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3622 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3623 radeon_emit(cs, di_src_sel);
3624 } else {
3625 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3626 PKT3_DRAW_INDIRECT_MULTI,
3627 8, predicating));
3628 radeon_emit(cs, 0);
3629 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3630 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3631 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3632 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3633 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3634 radeon_emit(cs, draw_count); /* count */
3635 radeon_emit(cs, count_va); /* count_addr */
3636 radeon_emit(cs, count_va >> 32);
3637 radeon_emit(cs, stride); /* stride */
3638 radeon_emit(cs, di_src_sel);
3639 }
3640 }
3641
3642 static void
3643 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3644 const struct radv_draw_info *info)
3645 {
3646 struct radv_cmd_state *state = &cmd_buffer->state;
3647 struct radeon_winsys *ws = cmd_buffer->device->ws;
3648 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3649
3650 if (info->indirect) {
3651 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3652 uint64_t count_va = 0;
3653
3654 va += info->indirect->offset + info->indirect_offset;
3655
3656 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3657
3658 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3659 radeon_emit(cs, 1);
3660 radeon_emit(cs, va);
3661 radeon_emit(cs, va >> 32);
3662
3663 if (info->count_buffer) {
3664 count_va = radv_buffer_get_va(info->count_buffer->bo);
3665 count_va += info->count_buffer->offset +
3666 info->count_buffer_offset;
3667
3668 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3669 }
3670
3671 if (!state->subpass->view_mask) {
3672 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3673 info->indexed,
3674 info->count,
3675 count_va,
3676 info->stride);
3677 } else {
3678 unsigned i;
3679 for_each_bit(i, state->subpass->view_mask) {
3680 radv_emit_view_index(cmd_buffer, i);
3681
3682 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3683 info->indexed,
3684 info->count,
3685 count_va,
3686 info->stride);
3687 }
3688 }
3689 } else {
3690 assert(state->pipeline->graphics.vtx_base_sgpr);
3691
3692 if (info->vertex_offset != state->last_vertex_offset ||
3693 info->first_instance != state->last_first_instance) {
3694 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3695 state->pipeline->graphics.vtx_emit_num);
3696
3697 radeon_emit(cs, info->vertex_offset);
3698 radeon_emit(cs, info->first_instance);
3699 if (state->pipeline->graphics.vtx_emit_num == 3)
3700 radeon_emit(cs, 0);
3701 state->last_first_instance = info->first_instance;
3702 state->last_vertex_offset = info->vertex_offset;
3703 }
3704
3705 if (state->last_num_instances != info->instance_count) {
3706 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3707 radeon_emit(cs, info->instance_count);
3708 state->last_num_instances = info->instance_count;
3709 }
3710
3711 if (info->indexed) {
3712 int index_size = state->index_type ? 4 : 2;
3713 uint64_t index_va;
3714
3715 index_va = state->index_va;
3716 index_va += info->first_index * index_size;
3717
3718 if (!state->subpass->view_mask) {
3719 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3720 index_va,
3721 info->count);
3722 } else {
3723 unsigned i;
3724 for_each_bit(i, state->subpass->view_mask) {
3725 radv_emit_view_index(cmd_buffer, i);
3726
3727 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3728 index_va,
3729 info->count);
3730 }
3731 }
3732 } else {
3733 if (!state->subpass->view_mask) {
3734 radv_cs_emit_draw_packet(cmd_buffer,
3735 info->count,
3736 !!info->strmout_buffer);
3737 } else {
3738 unsigned i;
3739 for_each_bit(i, state->subpass->view_mask) {
3740 radv_emit_view_index(cmd_buffer, i);
3741
3742 radv_cs_emit_draw_packet(cmd_buffer,
3743 info->count,
3744 !!info->strmout_buffer);
3745 }
3746 }
3747 }
3748 }
3749 }
3750
3751 /*
3752 * Vega and raven have a bug which triggers if there are multiple context
3753 * register contexts active at the same time with different scissor values.
3754 *
3755 * There are two possible workarounds:
3756 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3757 * there is only ever 1 active set of scissor values at the same time.
3758 *
3759 * 2) Whenever the hardware switches contexts we have to set the scissor
3760 * registers again even if it is a noop. That way the new context gets
3761 * the correct scissor values.
3762 *
3763 * This implements option 2. radv_need_late_scissor_emission needs to
3764 * return true on affected HW if radv_emit_all_graphics_states sets
3765 * any context registers.
3766 */
3767 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3768 const struct radv_draw_info *info)
3769 {
3770 struct radv_cmd_state *state = &cmd_buffer->state;
3771
3772 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3773 return false;
3774
3775 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
3776 return true;
3777
3778 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3779
3780 /* Index, vertex and streamout buffers don't change context regs, and
3781 * pipeline is already handled.
3782 */
3783 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3784 RADV_CMD_DIRTY_VERTEX_BUFFER |
3785 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
3786 RADV_CMD_DIRTY_PIPELINE);
3787
3788 if (cmd_buffer->state.dirty & used_states)
3789 return true;
3790
3791 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
3792 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3793 return true;
3794
3795 return false;
3796 }
3797
3798 static void
3799 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3800 const struct radv_draw_info *info)
3801 {
3802 bool late_scissor_emission;
3803
3804 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3805 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3806 radv_emit_rbplus_state(cmd_buffer);
3807
3808 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3809 radv_emit_graphics_pipeline(cmd_buffer);
3810
3811 /* This should be before the cmd_buffer->state.dirty is cleared
3812 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
3813 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
3814 late_scissor_emission =
3815 radv_need_late_scissor_emission(cmd_buffer, info);
3816
3817 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3818 radv_emit_framebuffer_state(cmd_buffer);
3819
3820 if (info->indexed) {
3821 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3822 radv_emit_index_buffer(cmd_buffer);
3823 } else {
3824 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3825 * so the state must be re-emitted before the next indexed
3826 * draw.
3827 */
3828 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3829 cmd_buffer->state.last_index_type = -1;
3830 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3831 }
3832 }
3833
3834 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3835
3836 radv_emit_draw_registers(cmd_buffer, info);
3837
3838 if (late_scissor_emission)
3839 radv_emit_scissor(cmd_buffer);
3840 }
3841
3842 static void
3843 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3844 const struct radv_draw_info *info)
3845 {
3846 struct radeon_info *rad_info =
3847 &cmd_buffer->device->physical_device->rad_info;
3848 bool has_prefetch =
3849 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3850 bool pipeline_is_dirty =
3851 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3852 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3853
3854 MAYBE_UNUSED unsigned cdw_max =
3855 radeon_check_space(cmd_buffer->device->ws,
3856 cmd_buffer->cs, 4096);
3857
3858 if (likely(!info->indirect)) {
3859 /* SI-CI treat instance_count==0 as instance_count==1. There is
3860 * no workaround for indirect draws, but we can at least skip
3861 * direct draws.
3862 */
3863 if (unlikely(!info->instance_count))
3864 return;
3865
3866 /* Handle count == 0. */
3867 if (unlikely(!info->count && !info->strmout_buffer))
3868 return;
3869 }
3870
3871 /* Use optimal packet order based on whether we need to sync the
3872 * pipeline.
3873 */
3874 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3875 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3876 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3877 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3878 /* If we have to wait for idle, set all states first, so that
3879 * all SET packets are processed in parallel with previous draw
3880 * calls. Then upload descriptors, set shader pointers, and
3881 * draw, and prefetch at the end. This ensures that the time
3882 * the CUs are idle is very short. (there are only SET_SH
3883 * packets between the wait and the draw)
3884 */
3885 radv_emit_all_graphics_states(cmd_buffer, info);
3886 si_emit_cache_flush(cmd_buffer);
3887 /* <-- CUs are idle here --> */
3888
3889 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3890
3891 radv_emit_draw_packets(cmd_buffer, info);
3892 /* <-- CUs are busy here --> */
3893
3894 /* Start prefetches after the draw has been started. Both will
3895 * run in parallel, but starting the draw first is more
3896 * important.
3897 */
3898 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3899 radv_emit_prefetch_L2(cmd_buffer,
3900 cmd_buffer->state.pipeline, false);
3901 }
3902 } else {
3903 /* If we don't wait for idle, start prefetches first, then set
3904 * states, and draw at the end.
3905 */
3906 si_emit_cache_flush(cmd_buffer);
3907
3908 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3909 /* Only prefetch the vertex shader and VBO descriptors
3910 * in order to start the draw as soon as possible.
3911 */
3912 radv_emit_prefetch_L2(cmd_buffer,
3913 cmd_buffer->state.pipeline, true);
3914 }
3915
3916 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3917
3918 radv_emit_all_graphics_states(cmd_buffer, info);
3919 radv_emit_draw_packets(cmd_buffer, info);
3920
3921 /* Prefetch the remaining shaders after the draw has been
3922 * started.
3923 */
3924 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3925 radv_emit_prefetch_L2(cmd_buffer,
3926 cmd_buffer->state.pipeline, false);
3927 }
3928 }
3929
3930 /* Workaround for a VGT hang when streamout is enabled.
3931 * It must be done after drawing.
3932 */
3933 if (cmd_buffer->state.streamout.streamout_enabled &&
3934 (rad_info->family == CHIP_HAWAII ||
3935 rad_info->family == CHIP_TONGA ||
3936 rad_info->family == CHIP_FIJI)) {
3937 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
3938 }
3939
3940 assert(cmd_buffer->cs->cdw <= cdw_max);
3941 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3942 }
3943
3944 void radv_CmdDraw(
3945 VkCommandBuffer commandBuffer,
3946 uint32_t vertexCount,
3947 uint32_t instanceCount,
3948 uint32_t firstVertex,
3949 uint32_t firstInstance)
3950 {
3951 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3952 struct radv_draw_info info = {};
3953
3954 info.count = vertexCount;
3955 info.instance_count = instanceCount;
3956 info.first_instance = firstInstance;
3957 info.vertex_offset = firstVertex;
3958
3959 radv_draw(cmd_buffer, &info);
3960 }
3961
3962 void radv_CmdDrawIndexed(
3963 VkCommandBuffer commandBuffer,
3964 uint32_t indexCount,
3965 uint32_t instanceCount,
3966 uint32_t firstIndex,
3967 int32_t vertexOffset,
3968 uint32_t firstInstance)
3969 {
3970 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3971 struct radv_draw_info info = {};
3972
3973 info.indexed = true;
3974 info.count = indexCount;
3975 info.instance_count = instanceCount;
3976 info.first_index = firstIndex;
3977 info.vertex_offset = vertexOffset;
3978 info.first_instance = firstInstance;
3979
3980 radv_draw(cmd_buffer, &info);
3981 }
3982
3983 void radv_CmdDrawIndirect(
3984 VkCommandBuffer commandBuffer,
3985 VkBuffer _buffer,
3986 VkDeviceSize offset,
3987 uint32_t drawCount,
3988 uint32_t stride)
3989 {
3990 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3991 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3992 struct radv_draw_info info = {};
3993
3994 info.count = drawCount;
3995 info.indirect = buffer;
3996 info.indirect_offset = offset;
3997 info.stride = stride;
3998
3999 radv_draw(cmd_buffer, &info);
4000 }
4001
4002 void radv_CmdDrawIndexedIndirect(
4003 VkCommandBuffer commandBuffer,
4004 VkBuffer _buffer,
4005 VkDeviceSize offset,
4006 uint32_t drawCount,
4007 uint32_t stride)
4008 {
4009 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4010 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4011 struct radv_draw_info info = {};
4012
4013 info.indexed = true;
4014 info.count = drawCount;
4015 info.indirect = buffer;
4016 info.indirect_offset = offset;
4017 info.stride = stride;
4018
4019 radv_draw(cmd_buffer, &info);
4020 }
4021
4022 void radv_CmdDrawIndirectCountAMD(
4023 VkCommandBuffer commandBuffer,
4024 VkBuffer _buffer,
4025 VkDeviceSize offset,
4026 VkBuffer _countBuffer,
4027 VkDeviceSize countBufferOffset,
4028 uint32_t maxDrawCount,
4029 uint32_t stride)
4030 {
4031 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4032 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4033 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4034 struct radv_draw_info info = {};
4035
4036 info.count = maxDrawCount;
4037 info.indirect = buffer;
4038 info.indirect_offset = offset;
4039 info.count_buffer = count_buffer;
4040 info.count_buffer_offset = countBufferOffset;
4041 info.stride = stride;
4042
4043 radv_draw(cmd_buffer, &info);
4044 }
4045
4046 void radv_CmdDrawIndexedIndirectCountAMD(
4047 VkCommandBuffer commandBuffer,
4048 VkBuffer _buffer,
4049 VkDeviceSize offset,
4050 VkBuffer _countBuffer,
4051 VkDeviceSize countBufferOffset,
4052 uint32_t maxDrawCount,
4053 uint32_t stride)
4054 {
4055 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4056 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4057 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4058 struct radv_draw_info info = {};
4059
4060 info.indexed = true;
4061 info.count = maxDrawCount;
4062 info.indirect = buffer;
4063 info.indirect_offset = offset;
4064 info.count_buffer = count_buffer;
4065 info.count_buffer_offset = countBufferOffset;
4066 info.stride = stride;
4067
4068 radv_draw(cmd_buffer, &info);
4069 }
4070
4071 void radv_CmdDrawIndirectCountKHR(
4072 VkCommandBuffer commandBuffer,
4073 VkBuffer _buffer,
4074 VkDeviceSize offset,
4075 VkBuffer _countBuffer,
4076 VkDeviceSize countBufferOffset,
4077 uint32_t maxDrawCount,
4078 uint32_t stride)
4079 {
4080 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4081 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4082 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4083 struct radv_draw_info info = {};
4084
4085 info.count = maxDrawCount;
4086 info.indirect = buffer;
4087 info.indirect_offset = offset;
4088 info.count_buffer = count_buffer;
4089 info.count_buffer_offset = countBufferOffset;
4090 info.stride = stride;
4091
4092 radv_draw(cmd_buffer, &info);
4093 }
4094
4095 void radv_CmdDrawIndexedIndirectCountKHR(
4096 VkCommandBuffer commandBuffer,
4097 VkBuffer _buffer,
4098 VkDeviceSize offset,
4099 VkBuffer _countBuffer,
4100 VkDeviceSize countBufferOffset,
4101 uint32_t maxDrawCount,
4102 uint32_t stride)
4103 {
4104 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4105 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4106 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4107 struct radv_draw_info info = {};
4108
4109 info.indexed = true;
4110 info.count = maxDrawCount;
4111 info.indirect = buffer;
4112 info.indirect_offset = offset;
4113 info.count_buffer = count_buffer;
4114 info.count_buffer_offset = countBufferOffset;
4115 info.stride = stride;
4116
4117 radv_draw(cmd_buffer, &info);
4118 }
4119
4120 struct radv_dispatch_info {
4121 /**
4122 * Determine the layout of the grid (in block units) to be used.
4123 */
4124 uint32_t blocks[3];
4125
4126 /**
4127 * A starting offset for the grid. If unaligned is set, the offset
4128 * must still be aligned.
4129 */
4130 uint32_t offsets[3];
4131 /**
4132 * Whether it's an unaligned compute dispatch.
4133 */
4134 bool unaligned;
4135
4136 /**
4137 * Indirect compute parameters resource.
4138 */
4139 struct radv_buffer *indirect;
4140 uint64_t indirect_offset;
4141 };
4142
4143 static void
4144 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4145 const struct radv_dispatch_info *info)
4146 {
4147 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4148 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4149 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4150 struct radeon_winsys *ws = cmd_buffer->device->ws;
4151 bool predicating = cmd_buffer->state.predicating;
4152 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4153 struct radv_userdata_info *loc;
4154
4155 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4156 AC_UD_CS_GRID_SIZE);
4157
4158 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4159
4160 if (info->indirect) {
4161 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4162
4163 va += info->indirect->offset + info->indirect_offset;
4164
4165 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4166
4167 if (loc->sgpr_idx != -1) {
4168 for (unsigned i = 0; i < 3; ++i) {
4169 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4170 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4171 COPY_DATA_DST_SEL(COPY_DATA_REG));
4172 radeon_emit(cs, (va + 4 * i));
4173 radeon_emit(cs, (va + 4 * i) >> 32);
4174 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4175 + loc->sgpr_idx * 4) >> 2) + i);
4176 radeon_emit(cs, 0);
4177 }
4178 }
4179
4180 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4181 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4182 PKT3_SHADER_TYPE_S(1));
4183 radeon_emit(cs, va);
4184 radeon_emit(cs, va >> 32);
4185 radeon_emit(cs, dispatch_initiator);
4186 } else {
4187 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4188 PKT3_SHADER_TYPE_S(1));
4189 radeon_emit(cs, 1);
4190 radeon_emit(cs, va);
4191 radeon_emit(cs, va >> 32);
4192
4193 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4194 PKT3_SHADER_TYPE_S(1));
4195 radeon_emit(cs, 0);
4196 radeon_emit(cs, dispatch_initiator);
4197 }
4198 } else {
4199 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4200 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4201
4202 if (info->unaligned) {
4203 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4204 unsigned remainder[3];
4205
4206 /* If aligned, these should be an entire block size,
4207 * not 0.
4208 */
4209 remainder[0] = blocks[0] + cs_block_size[0] -
4210 align_u32_npot(blocks[0], cs_block_size[0]);
4211 remainder[1] = blocks[1] + cs_block_size[1] -
4212 align_u32_npot(blocks[1], cs_block_size[1]);
4213 remainder[2] = blocks[2] + cs_block_size[2] -
4214 align_u32_npot(blocks[2], cs_block_size[2]);
4215
4216 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4217 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4218 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4219
4220 for(unsigned i = 0; i < 3; ++i) {
4221 assert(offsets[i] % cs_block_size[i] == 0);
4222 offsets[i] /= cs_block_size[i];
4223 }
4224
4225 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4226 radeon_emit(cs,
4227 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4228 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4229 radeon_emit(cs,
4230 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4231 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4232 radeon_emit(cs,
4233 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4234 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4235
4236 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4237 }
4238
4239 if (loc->sgpr_idx != -1) {
4240 assert(loc->num_sgprs == 3);
4241
4242 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4243 loc->sgpr_idx * 4, 3);
4244 radeon_emit(cs, blocks[0]);
4245 radeon_emit(cs, blocks[1]);
4246 radeon_emit(cs, blocks[2]);
4247 }
4248
4249 if (offsets[0] || offsets[1] || offsets[2]) {
4250 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4251 radeon_emit(cs, offsets[0]);
4252 radeon_emit(cs, offsets[1]);
4253 radeon_emit(cs, offsets[2]);
4254
4255 /* The blocks in the packet are not counts but end values. */
4256 for (unsigned i = 0; i < 3; ++i)
4257 blocks[i] += offsets[i];
4258 } else {
4259 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4260 }
4261
4262 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4263 PKT3_SHADER_TYPE_S(1));
4264 radeon_emit(cs, blocks[0]);
4265 radeon_emit(cs, blocks[1]);
4266 radeon_emit(cs, blocks[2]);
4267 radeon_emit(cs, dispatch_initiator);
4268 }
4269
4270 assert(cmd_buffer->cs->cdw <= cdw_max);
4271 }
4272
4273 static void
4274 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4275 {
4276 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4277 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4278 }
4279
4280 static void
4281 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4282 const struct radv_dispatch_info *info)
4283 {
4284 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4285 bool has_prefetch =
4286 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
4287 bool pipeline_is_dirty = pipeline &&
4288 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4289
4290 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4291 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4292 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4293 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4294 /* If we have to wait for idle, set all states first, so that
4295 * all SET packets are processed in parallel with previous draw
4296 * calls. Then upload descriptors, set shader pointers, and
4297 * dispatch, and prefetch at the end. This ensures that the
4298 * time the CUs are idle is very short. (there are only SET_SH
4299 * packets between the wait and the draw)
4300 */
4301 radv_emit_compute_pipeline(cmd_buffer);
4302 si_emit_cache_flush(cmd_buffer);
4303 /* <-- CUs are idle here --> */
4304
4305 radv_upload_compute_shader_descriptors(cmd_buffer);
4306
4307 radv_emit_dispatch_packets(cmd_buffer, info);
4308 /* <-- CUs are busy here --> */
4309
4310 /* Start prefetches after the dispatch has been started. Both
4311 * will run in parallel, but starting the dispatch first is
4312 * more important.
4313 */
4314 if (has_prefetch && pipeline_is_dirty) {
4315 radv_emit_shader_prefetch(cmd_buffer,
4316 pipeline->shaders[MESA_SHADER_COMPUTE]);
4317 }
4318 } else {
4319 /* If we don't wait for idle, start prefetches first, then set
4320 * states, and dispatch at the end.
4321 */
4322 si_emit_cache_flush(cmd_buffer);
4323
4324 if (has_prefetch && pipeline_is_dirty) {
4325 radv_emit_shader_prefetch(cmd_buffer,
4326 pipeline->shaders[MESA_SHADER_COMPUTE]);
4327 }
4328
4329 radv_upload_compute_shader_descriptors(cmd_buffer);
4330
4331 radv_emit_compute_pipeline(cmd_buffer);
4332 radv_emit_dispatch_packets(cmd_buffer, info);
4333 }
4334
4335 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4336 }
4337
4338 void radv_CmdDispatchBase(
4339 VkCommandBuffer commandBuffer,
4340 uint32_t base_x,
4341 uint32_t base_y,
4342 uint32_t base_z,
4343 uint32_t x,
4344 uint32_t y,
4345 uint32_t z)
4346 {
4347 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4348 struct radv_dispatch_info info = {};
4349
4350 info.blocks[0] = x;
4351 info.blocks[1] = y;
4352 info.blocks[2] = z;
4353
4354 info.offsets[0] = base_x;
4355 info.offsets[1] = base_y;
4356 info.offsets[2] = base_z;
4357 radv_dispatch(cmd_buffer, &info);
4358 }
4359
4360 void radv_CmdDispatch(
4361 VkCommandBuffer commandBuffer,
4362 uint32_t x,
4363 uint32_t y,
4364 uint32_t z)
4365 {
4366 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4367 }
4368
4369 void radv_CmdDispatchIndirect(
4370 VkCommandBuffer commandBuffer,
4371 VkBuffer _buffer,
4372 VkDeviceSize offset)
4373 {
4374 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4375 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4376 struct radv_dispatch_info info = {};
4377
4378 info.indirect = buffer;
4379 info.indirect_offset = offset;
4380
4381 radv_dispatch(cmd_buffer, &info);
4382 }
4383
4384 void radv_unaligned_dispatch(
4385 struct radv_cmd_buffer *cmd_buffer,
4386 uint32_t x,
4387 uint32_t y,
4388 uint32_t z)
4389 {
4390 struct radv_dispatch_info info = {};
4391
4392 info.blocks[0] = x;
4393 info.blocks[1] = y;
4394 info.blocks[2] = z;
4395 info.unaligned = 1;
4396
4397 radv_dispatch(cmd_buffer, &info);
4398 }
4399
4400 void radv_CmdEndRenderPass(
4401 VkCommandBuffer commandBuffer)
4402 {
4403 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4404
4405 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4406
4407 radv_cmd_buffer_end_subpass(cmd_buffer);
4408
4409 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4410
4411 cmd_buffer->state.pass = NULL;
4412 cmd_buffer->state.subpass = NULL;
4413 cmd_buffer->state.attachments = NULL;
4414 cmd_buffer->state.framebuffer = NULL;
4415 }
4416
4417 void radv_CmdEndRenderPass2KHR(
4418 VkCommandBuffer commandBuffer,
4419 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4420 {
4421 radv_CmdEndRenderPass(commandBuffer);
4422 }
4423
4424 /*
4425 * For HTILE we have the following interesting clear words:
4426 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4427 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4428 * 0xfffffff0: Clear depth to 1.0
4429 * 0x00000000: Clear depth to 0.0
4430 */
4431 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4432 struct radv_image *image,
4433 const VkImageSubresourceRange *range,
4434 uint32_t clear_word)
4435 {
4436 assert(range->baseMipLevel == 0);
4437 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4438 unsigned layer_count = radv_get_layerCount(image, range);
4439 uint64_t size = image->surface.htile_slice_size * layer_count;
4440 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4441 uint64_t offset = image->offset + image->htile_offset +
4442 image->surface.htile_slice_size * range->baseArrayLayer;
4443 struct radv_cmd_state *state = &cmd_buffer->state;
4444 VkClearDepthStencilValue value = {};
4445
4446 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4447 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4448
4449 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4450 size, clear_word);
4451
4452 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4453
4454 if (vk_format_is_stencil(image->vk_format))
4455 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4456
4457 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4458
4459 if (radv_image_is_tc_compat_htile(image)) {
4460 /* Initialize the TC-compat metada value to 0 because by
4461 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4462 * need have to conditionally update its value when performing
4463 * a fast depth clear.
4464 */
4465 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4466 }
4467 }
4468
4469 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4470 struct radv_image *image,
4471 VkImageLayout src_layout,
4472 VkImageLayout dst_layout,
4473 unsigned src_queue_mask,
4474 unsigned dst_queue_mask,
4475 const VkImageSubresourceRange *range)
4476 {
4477 if (!radv_image_has_htile(image))
4478 return;
4479
4480 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4481 /* TODO: merge with the clear if applicable */
4482 radv_initialize_htile(cmd_buffer, image, range, 0);
4483 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4484 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4485 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4486 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4487 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4488 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4489 VkImageSubresourceRange local_range = *range;
4490 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4491 local_range.baseMipLevel = 0;
4492 local_range.levelCount = 1;
4493
4494 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4495 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4496
4497 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4498
4499 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4500 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4501 }
4502 }
4503
4504 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4505 struct radv_image *image, uint32_t value)
4506 {
4507 struct radv_cmd_state *state = &cmd_buffer->state;
4508
4509 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4510 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4511
4512 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4513
4514 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4515 }
4516
4517 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4518 struct radv_image *image)
4519 {
4520 struct radv_cmd_state *state = &cmd_buffer->state;
4521 static const uint32_t fmask_clear_values[4] = {
4522 0x00000000,
4523 0x02020202,
4524 0xE4E4E4E4,
4525 0x76543210
4526 };
4527 uint32_t log2_samples = util_logbase2(image->info.samples);
4528 uint32_t value = fmask_clear_values[log2_samples];
4529
4530 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4531 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4532
4533 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
4534
4535 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4536 }
4537
4538 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4539 struct radv_image *image, uint32_t value)
4540 {
4541 struct radv_cmd_state *state = &cmd_buffer->state;
4542
4543 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4544 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4545
4546 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4547
4548 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4549 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4550 }
4551
4552 /**
4553 * Initialize DCC/FMASK/CMASK metadata for a color image.
4554 */
4555 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4556 struct radv_image *image,
4557 VkImageLayout src_layout,
4558 VkImageLayout dst_layout,
4559 unsigned src_queue_mask,
4560 unsigned dst_queue_mask)
4561 {
4562 if (radv_image_has_cmask(image)) {
4563 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4564
4565 /* TODO: clarify this. */
4566 if (radv_image_has_fmask(image)) {
4567 value = 0xccccccccu;
4568 }
4569
4570 radv_initialise_cmask(cmd_buffer, image, value);
4571 }
4572
4573 if (radv_image_has_fmask(image)) {
4574 radv_initialize_fmask(cmd_buffer, image);
4575 }
4576
4577 if (radv_image_has_dcc(image)) {
4578 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4579 bool need_decompress_pass = false;
4580
4581 if (radv_layout_dcc_compressed(image, dst_layout,
4582 dst_queue_mask)) {
4583 value = 0x20202020u;
4584 need_decompress_pass = true;
4585 }
4586
4587 radv_initialize_dcc(cmd_buffer, image, value);
4588
4589 radv_update_fce_metadata(cmd_buffer, image,
4590 need_decompress_pass);
4591 }
4592
4593 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4594 uint32_t color_values[2] = {};
4595 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4596 }
4597 }
4598
4599 /**
4600 * Handle color image transitions for DCC/FMASK/CMASK.
4601 */
4602 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4603 struct radv_image *image,
4604 VkImageLayout src_layout,
4605 VkImageLayout dst_layout,
4606 unsigned src_queue_mask,
4607 unsigned dst_queue_mask,
4608 const VkImageSubresourceRange *range)
4609 {
4610 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4611 radv_init_color_image_metadata(cmd_buffer, image,
4612 src_layout, dst_layout,
4613 src_queue_mask, dst_queue_mask);
4614 return;
4615 }
4616
4617 if (radv_image_has_dcc(image)) {
4618 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4619 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4620 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4621 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4622 radv_decompress_dcc(cmd_buffer, image, range);
4623 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4624 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4625 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4626 }
4627 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4628 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4629 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4630 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4631 }
4632
4633 if (radv_image_has_fmask(image)) {
4634 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
4635 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
4636 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
4637 }
4638 }
4639 }
4640 }
4641
4642 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4643 struct radv_image *image,
4644 VkImageLayout src_layout,
4645 VkImageLayout dst_layout,
4646 uint32_t src_family,
4647 uint32_t dst_family,
4648 const VkImageSubresourceRange *range)
4649 {
4650 if (image->exclusive && src_family != dst_family) {
4651 /* This is an acquire or a release operation and there will be
4652 * a corresponding release/acquire. Do the transition in the
4653 * most flexible queue. */
4654
4655 assert(src_family == cmd_buffer->queue_family_index ||
4656 dst_family == cmd_buffer->queue_family_index);
4657
4658 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4659 return;
4660
4661 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4662 (src_family == RADV_QUEUE_GENERAL ||
4663 dst_family == RADV_QUEUE_GENERAL))
4664 return;
4665 }
4666
4667 if (src_layout == dst_layout)
4668 return;
4669
4670 unsigned src_queue_mask =
4671 radv_image_queue_family_mask(image, src_family,
4672 cmd_buffer->queue_family_index);
4673 unsigned dst_queue_mask =
4674 radv_image_queue_family_mask(image, dst_family,
4675 cmd_buffer->queue_family_index);
4676
4677 if (vk_format_is_depth(image->vk_format)) {
4678 radv_handle_depth_image_transition(cmd_buffer, image,
4679 src_layout, dst_layout,
4680 src_queue_mask, dst_queue_mask,
4681 range);
4682 } else {
4683 radv_handle_color_image_transition(cmd_buffer, image,
4684 src_layout, dst_layout,
4685 src_queue_mask, dst_queue_mask,
4686 range);
4687 }
4688 }
4689
4690 struct radv_barrier_info {
4691 uint32_t eventCount;
4692 const VkEvent *pEvents;
4693 VkPipelineStageFlags srcStageMask;
4694 VkPipelineStageFlags dstStageMask;
4695 };
4696
4697 static void
4698 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4699 uint32_t memoryBarrierCount,
4700 const VkMemoryBarrier *pMemoryBarriers,
4701 uint32_t bufferMemoryBarrierCount,
4702 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4703 uint32_t imageMemoryBarrierCount,
4704 const VkImageMemoryBarrier *pImageMemoryBarriers,
4705 const struct radv_barrier_info *info)
4706 {
4707 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4708 enum radv_cmd_flush_bits src_flush_bits = 0;
4709 enum radv_cmd_flush_bits dst_flush_bits = 0;
4710
4711 for (unsigned i = 0; i < info->eventCount; ++i) {
4712 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4713 uint64_t va = radv_buffer_get_va(event->bo);
4714
4715 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4716
4717 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4718
4719 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
4720 assert(cmd_buffer->cs->cdw <= cdw_max);
4721 }
4722
4723 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4724 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4725 NULL);
4726 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4727 NULL);
4728 }
4729
4730 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4731 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4732 NULL);
4733 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4734 NULL);
4735 }
4736
4737 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4738 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4739
4740 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4741 image);
4742 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4743 image);
4744 }
4745
4746 /* The Vulkan spec 1.1.98 says:
4747 *
4748 * "An execution dependency with only
4749 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
4750 * will only prevent that stage from executing in subsequently
4751 * submitted commands. As this stage does not perform any actual
4752 * execution, this is not observable - in effect, it does not delay
4753 * processing of subsequent commands. Similarly an execution dependency
4754 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
4755 * will effectively not wait for any prior commands to complete."
4756 */
4757 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
4758 radv_stage_flush(cmd_buffer, info->srcStageMask);
4759 cmd_buffer->state.flush_bits |= src_flush_bits;
4760
4761 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4762 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4763 radv_handle_image_transition(cmd_buffer, image,
4764 pImageMemoryBarriers[i].oldLayout,
4765 pImageMemoryBarriers[i].newLayout,
4766 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4767 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4768 &pImageMemoryBarriers[i].subresourceRange);
4769 }
4770
4771 /* Make sure CP DMA is idle because the driver might have performed a
4772 * DMA operation for copying or filling buffers/images.
4773 */
4774 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4775 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4776 si_cp_dma_wait_for_idle(cmd_buffer);
4777
4778 cmd_buffer->state.flush_bits |= dst_flush_bits;
4779 }
4780
4781 void radv_CmdPipelineBarrier(
4782 VkCommandBuffer commandBuffer,
4783 VkPipelineStageFlags srcStageMask,
4784 VkPipelineStageFlags destStageMask,
4785 VkBool32 byRegion,
4786 uint32_t memoryBarrierCount,
4787 const VkMemoryBarrier* pMemoryBarriers,
4788 uint32_t bufferMemoryBarrierCount,
4789 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4790 uint32_t imageMemoryBarrierCount,
4791 const VkImageMemoryBarrier* pImageMemoryBarriers)
4792 {
4793 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4794 struct radv_barrier_info info;
4795
4796 info.eventCount = 0;
4797 info.pEvents = NULL;
4798 info.srcStageMask = srcStageMask;
4799 info.dstStageMask = destStageMask;
4800
4801 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4802 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4803 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4804 }
4805
4806
4807 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4808 struct radv_event *event,
4809 VkPipelineStageFlags stageMask,
4810 unsigned value)
4811 {
4812 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4813 uint64_t va = radv_buffer_get_va(event->bo);
4814
4815 si_emit_cache_flush(cmd_buffer);
4816
4817 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4818
4819 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4820
4821 /* Flags that only require a top-of-pipe event. */
4822 VkPipelineStageFlags top_of_pipe_flags =
4823 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4824
4825 /* Flags that only require a post-index-fetch event. */
4826 VkPipelineStageFlags post_index_fetch_flags =
4827 top_of_pipe_flags |
4828 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4829 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4830
4831 /* Make sure CP DMA is idle because the driver might have performed a
4832 * DMA operation for copying or filling buffers/images.
4833 */
4834 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4835 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4836 si_cp_dma_wait_for_idle(cmd_buffer);
4837
4838 /* TODO: Emit EOS events for syncing PS/CS stages. */
4839
4840 if (!(stageMask & ~top_of_pipe_flags)) {
4841 /* Just need to sync the PFP engine. */
4842 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4843 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4844 S_370_WR_CONFIRM(1) |
4845 S_370_ENGINE_SEL(V_370_PFP));
4846 radeon_emit(cs, va);
4847 radeon_emit(cs, va >> 32);
4848 radeon_emit(cs, value);
4849 } else if (!(stageMask & ~post_index_fetch_flags)) {
4850 /* Sync ME because PFP reads index and indirect buffers. */
4851 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4852 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4853 S_370_WR_CONFIRM(1) |
4854 S_370_ENGINE_SEL(V_370_ME));
4855 radeon_emit(cs, va);
4856 radeon_emit(cs, va >> 32);
4857 radeon_emit(cs, value);
4858 } else {
4859 /* Otherwise, sync all prior GPU work using an EOP event. */
4860 si_cs_emit_write_event_eop(cs,
4861 cmd_buffer->device->physical_device->rad_info.chip_class,
4862 radv_cmd_buffer_uses_mec(cmd_buffer),
4863 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4864 EOP_DATA_SEL_VALUE_32BIT, va, value,
4865 cmd_buffer->gfx9_eop_bug_va);
4866 }
4867
4868 assert(cmd_buffer->cs->cdw <= cdw_max);
4869 }
4870
4871 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4872 VkEvent _event,
4873 VkPipelineStageFlags stageMask)
4874 {
4875 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4876 RADV_FROM_HANDLE(radv_event, event, _event);
4877
4878 write_event(cmd_buffer, event, stageMask, 1);
4879 }
4880
4881 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4882 VkEvent _event,
4883 VkPipelineStageFlags stageMask)
4884 {
4885 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4886 RADV_FROM_HANDLE(radv_event, event, _event);
4887
4888 write_event(cmd_buffer, event, stageMask, 0);
4889 }
4890
4891 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4892 uint32_t eventCount,
4893 const VkEvent* pEvents,
4894 VkPipelineStageFlags srcStageMask,
4895 VkPipelineStageFlags dstStageMask,
4896 uint32_t memoryBarrierCount,
4897 const VkMemoryBarrier* pMemoryBarriers,
4898 uint32_t bufferMemoryBarrierCount,
4899 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4900 uint32_t imageMemoryBarrierCount,
4901 const VkImageMemoryBarrier* pImageMemoryBarriers)
4902 {
4903 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4904 struct radv_barrier_info info;
4905
4906 info.eventCount = eventCount;
4907 info.pEvents = pEvents;
4908 info.srcStageMask = 0;
4909
4910 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4911 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4912 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4913 }
4914
4915
4916 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4917 uint32_t deviceMask)
4918 {
4919 /* No-op */
4920 }
4921
4922 /* VK_EXT_conditional_rendering */
4923 void radv_CmdBeginConditionalRenderingEXT(
4924 VkCommandBuffer commandBuffer,
4925 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4926 {
4927 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4928 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4929 bool draw_visible = true;
4930 uint64_t va;
4931
4932 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4933
4934 /* By default, if the 32-bit value at offset in buffer memory is zero,
4935 * then the rendering commands are discarded, otherwise they are
4936 * executed as normal. If the inverted flag is set, all commands are
4937 * discarded if the value is non zero.
4938 */
4939 if (pConditionalRenderingBegin->flags &
4940 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4941 draw_visible = false;
4942 }
4943
4944 si_emit_cache_flush(cmd_buffer);
4945
4946 /* Enable predication for this command buffer. */
4947 si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4948 cmd_buffer->state.predicating = true;
4949
4950 /* Store conditional rendering user info. */
4951 cmd_buffer->state.predication_type = draw_visible;
4952 cmd_buffer->state.predication_va = va;
4953 }
4954
4955 void radv_CmdEndConditionalRenderingEXT(
4956 VkCommandBuffer commandBuffer)
4957 {
4958 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4959
4960 /* Disable predication for this command buffer. */
4961 si_emit_set_predication_state(cmd_buffer, false, 0);
4962 cmd_buffer->state.predicating = false;
4963
4964 /* Reset conditional rendering user info. */
4965 cmd_buffer->state.predication_type = -1;
4966 cmd_buffer->state.predication_va = 0;
4967 }
4968
4969 /* VK_EXT_transform_feedback */
4970 void radv_CmdBindTransformFeedbackBuffersEXT(
4971 VkCommandBuffer commandBuffer,
4972 uint32_t firstBinding,
4973 uint32_t bindingCount,
4974 const VkBuffer* pBuffers,
4975 const VkDeviceSize* pOffsets,
4976 const VkDeviceSize* pSizes)
4977 {
4978 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4979 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4980 uint8_t enabled_mask = 0;
4981
4982 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
4983 for (uint32_t i = 0; i < bindingCount; i++) {
4984 uint32_t idx = firstBinding + i;
4985
4986 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
4987 sb[idx].offset = pOffsets[i];
4988 sb[idx].size = pSizes[i];
4989
4990 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4991 sb[idx].buffer->bo);
4992
4993 enabled_mask |= 1 << idx;
4994 }
4995
4996 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
4997
4998 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
4999 }
5000
5001 static void
5002 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5003 {
5004 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5005 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5006
5007 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5008 radeon_emit(cs,
5009 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5010 S_028B94_RAST_STREAM(0) |
5011 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5012 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5013 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5014 radeon_emit(cs, so->hw_enabled_mask &
5015 so->enabled_stream_buffers_mask);
5016
5017 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5018 }
5019
5020 static void
5021 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5022 {
5023 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5024 bool old_streamout_enabled = so->streamout_enabled;
5025 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5026
5027 so->streamout_enabled = enable;
5028
5029 so->hw_enabled_mask = so->enabled_mask |
5030 (so->enabled_mask << 4) |
5031 (so->enabled_mask << 8) |
5032 (so->enabled_mask << 12);
5033
5034 if ((old_streamout_enabled != so->streamout_enabled) ||
5035 (old_hw_enabled_mask != so->hw_enabled_mask))
5036 radv_emit_streamout_enable(cmd_buffer);
5037 }
5038
5039 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5040 {
5041 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5042 unsigned reg_strmout_cntl;
5043
5044 /* The register is at different places on different ASICs. */
5045 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
5046 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5047 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5048 } else {
5049 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5050 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5051 }
5052
5053 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5054 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5055
5056 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5057 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5058 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5059 radeon_emit(cs, 0);
5060 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5061 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5062 radeon_emit(cs, 4); /* poll interval */
5063 }
5064
5065 void radv_CmdBeginTransformFeedbackEXT(
5066 VkCommandBuffer commandBuffer,
5067 uint32_t firstCounterBuffer,
5068 uint32_t counterBufferCount,
5069 const VkBuffer* pCounterBuffers,
5070 const VkDeviceSize* pCounterBufferOffsets)
5071 {
5072 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5073 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5074 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5075 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5076 uint32_t i;
5077
5078 radv_flush_vgt_streamout(cmd_buffer);
5079
5080 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5081 for_each_bit(i, so->enabled_mask) {
5082 int32_t counter_buffer_idx = i - firstCounterBuffer;
5083 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5084 counter_buffer_idx = -1;
5085
5086 /* SI binds streamout buffers as shader resources.
5087 * VGT only counts primitives and tells the shader through
5088 * SGPRs what to do.
5089 */
5090 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5091 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5092 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5093
5094 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5095
5096 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5097 /* The array of counter buffers is optional. */
5098 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5099 uint64_t va = radv_buffer_get_va(buffer->bo);
5100
5101 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5102
5103 /* Append */
5104 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5105 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5106 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5107 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5108 radeon_emit(cs, 0); /* unused */
5109 radeon_emit(cs, 0); /* unused */
5110 radeon_emit(cs, va); /* src address lo */
5111 radeon_emit(cs, va >> 32); /* src address hi */
5112
5113 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5114 } else {
5115 /* Start from the beginning. */
5116 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5117 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5118 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5119 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5120 radeon_emit(cs, 0); /* unused */
5121 radeon_emit(cs, 0); /* unused */
5122 radeon_emit(cs, 0); /* unused */
5123 radeon_emit(cs, 0); /* unused */
5124 }
5125 }
5126
5127 radv_set_streamout_enable(cmd_buffer, true);
5128 }
5129
5130 void radv_CmdEndTransformFeedbackEXT(
5131 VkCommandBuffer commandBuffer,
5132 uint32_t firstCounterBuffer,
5133 uint32_t counterBufferCount,
5134 const VkBuffer* pCounterBuffers,
5135 const VkDeviceSize* pCounterBufferOffsets)
5136 {
5137 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5138 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5139 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5140 uint32_t i;
5141
5142 radv_flush_vgt_streamout(cmd_buffer);
5143
5144 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5145 for_each_bit(i, so->enabled_mask) {
5146 int32_t counter_buffer_idx = i - firstCounterBuffer;
5147 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5148 counter_buffer_idx = -1;
5149
5150 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5151 /* The array of counters buffer is optional. */
5152 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5153 uint64_t va = radv_buffer_get_va(buffer->bo);
5154
5155 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5156
5157 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5158 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5159 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5160 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5161 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5162 radeon_emit(cs, va); /* dst address lo */
5163 radeon_emit(cs, va >> 32); /* dst address hi */
5164 radeon_emit(cs, 0); /* unused */
5165 radeon_emit(cs, 0); /* unused */
5166
5167 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5168 }
5169
5170 /* Deactivate transform feedback by zeroing the buffer size.
5171 * The counters (primitives generated, primitives emitted) may
5172 * be enabled even if there is not buffer bound. This ensures
5173 * that the primitives-emitted query won't increment.
5174 */
5175 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5176
5177 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5178 }
5179
5180 radv_set_streamout_enable(cmd_buffer, false);
5181 }
5182
5183 void radv_CmdDrawIndirectByteCountEXT(
5184 VkCommandBuffer commandBuffer,
5185 uint32_t instanceCount,
5186 uint32_t firstInstance,
5187 VkBuffer _counterBuffer,
5188 VkDeviceSize counterBufferOffset,
5189 uint32_t counterOffset,
5190 uint32_t vertexStride)
5191 {
5192 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5193 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5194 struct radv_draw_info info = {};
5195
5196 info.instance_count = instanceCount;
5197 info.first_instance = firstInstance;
5198 info.strmout_buffer = counterBuffer;
5199 info.strmout_buffer_offset = counterBufferOffset;
5200 info.stride = vertexStride;
5201
5202 radv_draw(cmd_buffer, &info);
5203 }