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[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 };
96
97 static void
98 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
99 const struct radv_dynamic_state *src)
100 {
101 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
102 uint32_t copy_mask = src->mask;
103 uint32_t dest_mask = 0;
104
105 /* Make sure to copy the number of viewports/scissors because they can
106 * only be specified at pipeline creation time.
107 */
108 dest->viewport.count = src->viewport.count;
109 dest->scissor.count = src->scissor.count;
110 dest->discard_rectangle.count = src->discard_rectangle.count;
111 dest->sample_location.count = src->sample_location.count;
112
113 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
114 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
115 src->viewport.count * sizeof(VkViewport))) {
116 typed_memcpy(dest->viewport.viewports,
117 src->viewport.viewports,
118 src->viewport.count);
119 dest_mask |= RADV_DYNAMIC_VIEWPORT;
120 }
121 }
122
123 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
124 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
125 src->scissor.count * sizeof(VkRect2D))) {
126 typed_memcpy(dest->scissor.scissors,
127 src->scissor.scissors, src->scissor.count);
128 dest_mask |= RADV_DYNAMIC_SCISSOR;
129 }
130 }
131
132 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
133 if (dest->line_width != src->line_width) {
134 dest->line_width = src->line_width;
135 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
136 }
137 }
138
139 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
140 if (memcmp(&dest->depth_bias, &src->depth_bias,
141 sizeof(src->depth_bias))) {
142 dest->depth_bias = src->depth_bias;
143 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
144 }
145 }
146
147 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
148 if (memcmp(&dest->blend_constants, &src->blend_constants,
149 sizeof(src->blend_constants))) {
150 typed_memcpy(dest->blend_constants,
151 src->blend_constants, 4);
152 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
153 }
154 }
155
156 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
157 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
158 sizeof(src->depth_bounds))) {
159 dest->depth_bounds = src->depth_bounds;
160 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
161 }
162 }
163
164 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
165 if (memcmp(&dest->stencil_compare_mask,
166 &src->stencil_compare_mask,
167 sizeof(src->stencil_compare_mask))) {
168 dest->stencil_compare_mask = src->stencil_compare_mask;
169 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
170 }
171 }
172
173 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
174 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
175 sizeof(src->stencil_write_mask))) {
176 dest->stencil_write_mask = src->stencil_write_mask;
177 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
178 }
179 }
180
181 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
182 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
183 sizeof(src->stencil_reference))) {
184 dest->stencil_reference = src->stencil_reference;
185 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
186 }
187 }
188
189 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
190 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
191 src->discard_rectangle.count * sizeof(VkRect2D))) {
192 typed_memcpy(dest->discard_rectangle.rectangles,
193 src->discard_rectangle.rectangles,
194 src->discard_rectangle.count);
195 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
196 }
197 }
198
199 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
200 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
201 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
202 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
203 memcmp(&dest->sample_location.locations,
204 &src->sample_location.locations,
205 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
206 dest->sample_location.per_pixel = src->sample_location.per_pixel;
207 dest->sample_location.grid_size = src->sample_location.grid_size;
208 typed_memcpy(dest->sample_location.locations,
209 src->sample_location.locations,
210 src->sample_location.count);
211 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
212 }
213 }
214
215 cmd_buffer->state.dirty |= dest_mask;
216 }
217
218 static void
219 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
220 struct radv_pipeline *pipeline)
221 {
222 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
223 struct radv_shader_info *info;
224
225 if (!pipeline->streamout_shader ||
226 cmd_buffer->device->physical_device->use_ngg_streamout)
227 return;
228
229 info = &pipeline->streamout_shader->info;
230 for (int i = 0; i < MAX_SO_BUFFERS; i++)
231 so->stride_in_dw[i] = info->so.strides[i];
232
233 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
234 }
235
236 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
237 {
238 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
239 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
240 }
241
242 enum ring_type radv_queue_family_to_ring(int f) {
243 switch (f) {
244 case RADV_QUEUE_GENERAL:
245 return RING_GFX;
246 case RADV_QUEUE_COMPUTE:
247 return RING_COMPUTE;
248 case RADV_QUEUE_TRANSFER:
249 return RING_DMA;
250 default:
251 unreachable("Unknown queue family");
252 }
253 }
254
255 static VkResult radv_create_cmd_buffer(
256 struct radv_device * device,
257 struct radv_cmd_pool * pool,
258 VkCommandBufferLevel level,
259 VkCommandBuffer* pCommandBuffer)
260 {
261 struct radv_cmd_buffer *cmd_buffer;
262 unsigned ring;
263 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
264 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
265 if (cmd_buffer == NULL)
266 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
267
268 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
269 cmd_buffer->device = device;
270 cmd_buffer->pool = pool;
271 cmd_buffer->level = level;
272
273 if (pool) {
274 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
275 cmd_buffer->queue_family_index = pool->queue_family_index;
276
277 } else {
278 /* Init the pool_link so we can safely call list_del when we destroy
279 * the command buffer
280 */
281 list_inithead(&cmd_buffer->pool_link);
282 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
283 }
284
285 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
286
287 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
288 if (!cmd_buffer->cs) {
289 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
290 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
291 }
292
293 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
294
295 list_inithead(&cmd_buffer->upload.list);
296
297 return VK_SUCCESS;
298 }
299
300 static void
301 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
302 {
303 list_del(&cmd_buffer->pool_link);
304
305 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
306 &cmd_buffer->upload.list, list) {
307 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
308 list_del(&up->list);
309 free(up);
310 }
311
312 if (cmd_buffer->upload.upload_bo)
313 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
314 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
315
316 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
317 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
318
319 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
320 }
321
322 static VkResult
323 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
324 {
325 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
326
327 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
328 &cmd_buffer->upload.list, list) {
329 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
330 list_del(&up->list);
331 free(up);
332 }
333
334 cmd_buffer->push_constant_stages = 0;
335 cmd_buffer->scratch_size_per_wave_needed = 0;
336 cmd_buffer->scratch_waves_wanted = 0;
337 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
338 cmd_buffer->compute_scratch_waves_wanted = 0;
339 cmd_buffer->esgs_ring_size_needed = 0;
340 cmd_buffer->gsvs_ring_size_needed = 0;
341 cmd_buffer->tess_rings_needed = false;
342 cmd_buffer->gds_needed = false;
343 cmd_buffer->gds_oa_needed = false;
344 cmd_buffer->sample_positions_needed = false;
345
346 if (cmd_buffer->upload.upload_bo)
347 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
348 cmd_buffer->upload.upload_bo);
349 cmd_buffer->upload.offset = 0;
350
351 cmd_buffer->record_result = VK_SUCCESS;
352
353 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
354
355 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
356 cmd_buffer->descriptors[i].dirty = 0;
357 cmd_buffer->descriptors[i].valid = 0;
358 cmd_buffer->descriptors[i].push_dirty = false;
359 }
360
361 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
362 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
363 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
364 unsigned fence_offset, eop_bug_offset;
365 void *fence_ptr;
366
367 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
368 &fence_ptr);
369
370 cmd_buffer->gfx9_fence_va =
371 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
372 cmd_buffer->gfx9_fence_va += fence_offset;
373
374 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
375 /* Allocate a buffer for the EOP bug on GFX9. */
376 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
377 &eop_bug_offset, &fence_ptr);
378 cmd_buffer->gfx9_eop_bug_va =
379 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
380 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
381 }
382 }
383
384 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
385
386 return cmd_buffer->record_result;
387 }
388
389 static bool
390 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
391 uint64_t min_needed)
392 {
393 uint64_t new_size;
394 struct radeon_winsys_bo *bo;
395 struct radv_cmd_buffer_upload *upload;
396 struct radv_device *device = cmd_buffer->device;
397
398 new_size = MAX2(min_needed, 16 * 1024);
399 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
400
401 bo = device->ws->buffer_create(device->ws,
402 new_size, 4096,
403 RADEON_DOMAIN_GTT,
404 RADEON_FLAG_CPU_ACCESS|
405 RADEON_FLAG_NO_INTERPROCESS_SHARING |
406 RADEON_FLAG_32BIT,
407 RADV_BO_PRIORITY_UPLOAD_BUFFER);
408
409 if (!bo) {
410 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
411 return false;
412 }
413
414 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
415 if (cmd_buffer->upload.upload_bo) {
416 upload = malloc(sizeof(*upload));
417
418 if (!upload) {
419 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
420 device->ws->buffer_destroy(bo);
421 return false;
422 }
423
424 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
425 list_add(&upload->list, &cmd_buffer->upload.list);
426 }
427
428 cmd_buffer->upload.upload_bo = bo;
429 cmd_buffer->upload.size = new_size;
430 cmd_buffer->upload.offset = 0;
431 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
432
433 if (!cmd_buffer->upload.map) {
434 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
435 return false;
436 }
437
438 return true;
439 }
440
441 bool
442 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
443 unsigned size,
444 unsigned alignment,
445 unsigned *out_offset,
446 void **ptr)
447 {
448 assert(util_is_power_of_two_nonzero(alignment));
449
450 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
451 if (offset + size > cmd_buffer->upload.size) {
452 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
453 return false;
454 offset = 0;
455 }
456
457 *out_offset = offset;
458 *ptr = cmd_buffer->upload.map + offset;
459
460 cmd_buffer->upload.offset = offset + size;
461 return true;
462 }
463
464 bool
465 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
466 unsigned size, unsigned alignment,
467 const void *data, unsigned *out_offset)
468 {
469 uint8_t *ptr;
470
471 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
472 out_offset, (void **)&ptr))
473 return false;
474
475 if (ptr)
476 memcpy(ptr, data, size);
477
478 return true;
479 }
480
481 static void
482 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
483 unsigned count, const uint32_t *data)
484 {
485 struct radeon_cmdbuf *cs = cmd_buffer->cs;
486
487 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
488
489 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
490 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
491 S_370_WR_CONFIRM(1) |
492 S_370_ENGINE_SEL(V_370_ME));
493 radeon_emit(cs, va);
494 radeon_emit(cs, va >> 32);
495 radeon_emit_array(cs, data, count);
496 }
497
498 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
499 {
500 struct radv_device *device = cmd_buffer->device;
501 struct radeon_cmdbuf *cs = cmd_buffer->cs;
502 uint64_t va;
503
504 va = radv_buffer_get_va(device->trace_bo);
505 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
506 va += 4;
507
508 ++cmd_buffer->state.trace_id;
509 radv_emit_write_data_packet(cmd_buffer, va, 1,
510 &cmd_buffer->state.trace_id);
511
512 radeon_check_space(cmd_buffer->device->ws, cs, 2);
513
514 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
515 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
516 }
517
518 static void
519 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
520 enum radv_cmd_flush_bits flags)
521 {
522 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
523 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
524 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
525
526 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
527
528 /* Force wait for graphics or compute engines to be idle. */
529 si_cs_emit_cache_flush(cmd_buffer->cs,
530 cmd_buffer->device->physical_device->rad_info.chip_class,
531 &cmd_buffer->gfx9_fence_idx,
532 cmd_buffer->gfx9_fence_va,
533 radv_cmd_buffer_uses_mec(cmd_buffer),
534 flags, cmd_buffer->gfx9_eop_bug_va);
535 }
536
537 if (unlikely(cmd_buffer->device->trace_bo))
538 radv_cmd_buffer_trace_emit(cmd_buffer);
539 }
540
541 static void
542 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
543 struct radv_pipeline *pipeline, enum ring_type ring)
544 {
545 struct radv_device *device = cmd_buffer->device;
546 uint32_t data[2];
547 uint64_t va;
548
549 va = radv_buffer_get_va(device->trace_bo);
550
551 switch (ring) {
552 case RING_GFX:
553 va += 8;
554 break;
555 case RING_COMPUTE:
556 va += 16;
557 break;
558 default:
559 assert(!"invalid ring type");
560 }
561
562 uint64_t pipeline_address = (uintptr_t)pipeline;
563 data[0] = pipeline_address;
564 data[1] = pipeline_address >> 32;
565
566 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
567 }
568
569 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
570 VkPipelineBindPoint bind_point,
571 struct radv_descriptor_set *set,
572 unsigned idx)
573 {
574 struct radv_descriptor_state *descriptors_state =
575 radv_get_descriptors_state(cmd_buffer, bind_point);
576
577 descriptors_state->sets[idx] = set;
578
579 descriptors_state->valid |= (1u << idx); /* active descriptors */
580 descriptors_state->dirty |= (1u << idx);
581 }
582
583 static void
584 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
585 VkPipelineBindPoint bind_point)
586 {
587 struct radv_descriptor_state *descriptors_state =
588 radv_get_descriptors_state(cmd_buffer, bind_point);
589 struct radv_device *device = cmd_buffer->device;
590 uint32_t data[MAX_SETS * 2] = {};
591 uint64_t va;
592 unsigned i;
593 va = radv_buffer_get_va(device->trace_bo) + 24;
594
595 for_each_bit(i, descriptors_state->valid) {
596 struct radv_descriptor_set *set = descriptors_state->sets[i];
597 data[i * 2] = (uint64_t)(uintptr_t)set;
598 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
599 }
600
601 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
602 }
603
604 struct radv_userdata_info *
605 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
606 gl_shader_stage stage,
607 int idx)
608 {
609 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
610 return &shader->info.user_sgprs_locs.shader_data[idx];
611 }
612
613 static void
614 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
615 struct radv_pipeline *pipeline,
616 gl_shader_stage stage,
617 int idx, uint64_t va)
618 {
619 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
620 uint32_t base_reg = pipeline->user_data_0[stage];
621 if (loc->sgpr_idx == -1)
622 return;
623
624 assert(loc->num_sgprs == 1);
625
626 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
627 base_reg + loc->sgpr_idx * 4, va, false);
628 }
629
630 static void
631 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
632 struct radv_pipeline *pipeline,
633 struct radv_descriptor_state *descriptors_state,
634 gl_shader_stage stage)
635 {
636 struct radv_device *device = cmd_buffer->device;
637 struct radeon_cmdbuf *cs = cmd_buffer->cs;
638 uint32_t sh_base = pipeline->user_data_0[stage];
639 struct radv_userdata_locations *locs =
640 &pipeline->shaders[stage]->info.user_sgprs_locs;
641 unsigned mask = locs->descriptor_sets_enabled;
642
643 mask &= descriptors_state->dirty & descriptors_state->valid;
644
645 while (mask) {
646 int start, count;
647
648 u_bit_scan_consecutive_range(&mask, &start, &count);
649
650 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
651 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
652
653 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
654 for (int i = 0; i < count; i++) {
655 struct radv_descriptor_set *set =
656 descriptors_state->sets[start + i];
657
658 radv_emit_shader_pointer_body(device, cs, set->va, true);
659 }
660 }
661 }
662
663 /**
664 * Convert the user sample locations to hardware sample locations (the values
665 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
666 */
667 static void
668 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
669 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
670 {
671 uint32_t x_offset = x % state->grid_size.width;
672 uint32_t y_offset = y % state->grid_size.height;
673 uint32_t num_samples = (uint32_t)state->per_pixel;
674 VkSampleLocationEXT *user_locs;
675 uint32_t pixel_offset;
676
677 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
678
679 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
680 user_locs = &state->locations[pixel_offset];
681
682 for (uint32_t i = 0; i < num_samples; i++) {
683 float shifted_pos_x = user_locs[i].x - 0.5;
684 float shifted_pos_y = user_locs[i].y - 0.5;
685
686 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
687 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
688
689 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
690 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
691 }
692 }
693
694 /**
695 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
696 * locations.
697 */
698 static void
699 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
700 uint32_t *sample_locs_pixel)
701 {
702 for (uint32_t i = 0; i < num_samples; i++) {
703 uint32_t sample_reg_idx = i / 4;
704 uint32_t sample_loc_idx = i % 4;
705 int32_t pos_x = sample_locs[i].x;
706 int32_t pos_y = sample_locs[i].y;
707
708 uint32_t shift_x = 8 * sample_loc_idx;
709 uint32_t shift_y = shift_x + 4;
710
711 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
712 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
713 }
714 }
715
716 /**
717 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
718 * sample locations.
719 */
720 static uint64_t
721 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
722 VkOffset2D *sample_locs,
723 uint32_t num_samples)
724 {
725 uint32_t centroid_priorities[num_samples];
726 uint32_t sample_mask = num_samples - 1;
727 uint32_t distances[num_samples];
728 uint64_t centroid_priority = 0;
729
730 /* Compute the distances from center for each sample. */
731 for (int i = 0; i < num_samples; i++) {
732 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
733 (sample_locs[i].y * sample_locs[i].y);
734 }
735
736 /* Compute the centroid priorities by looking at the distances array. */
737 for (int i = 0; i < num_samples; i++) {
738 uint32_t min_idx = 0;
739
740 for (int j = 1; j < num_samples; j++) {
741 if (distances[j] < distances[min_idx])
742 min_idx = j;
743 }
744
745 centroid_priorities[i] = min_idx;
746 distances[min_idx] = 0xffffffff;
747 }
748
749 /* Compute the final centroid priority. */
750 for (int i = 0; i < 8; i++) {
751 centroid_priority |=
752 centroid_priorities[i & sample_mask] << (i * 4);
753 }
754
755 return centroid_priority << 32 | centroid_priority;
756 }
757
758 /**
759 * Emit the sample locations that are specified with VK_EXT_sample_locations.
760 */
761 static void
762 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
763 {
764 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
765 struct radv_multisample_state *ms = &pipeline->graphics.ms;
766 struct radv_sample_locations_state *sample_location =
767 &cmd_buffer->state.dynamic.sample_location;
768 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
769 struct radeon_cmdbuf *cs = cmd_buffer->cs;
770 uint32_t sample_locs_pixel[4][2] = {};
771 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
772 uint32_t max_sample_dist = 0;
773 uint64_t centroid_priority;
774
775 if (!cmd_buffer->state.dynamic.sample_location.count)
776 return;
777
778 /* Convert the user sample locations to hardware sample locations. */
779 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
780 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
781 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
782 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
783
784 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
785 for (uint32_t i = 0; i < 4; i++) {
786 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
787 sample_locs_pixel[i]);
788 }
789
790 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
791 centroid_priority =
792 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
793 num_samples);
794
795 /* Compute the maximum sample distance from the specified locations. */
796 for (uint32_t i = 0; i < num_samples; i++) {
797 VkOffset2D offset = sample_locs[0][i];
798 max_sample_dist = MAX2(max_sample_dist,
799 MAX2(abs(offset.x), abs(offset.y)));
800 }
801
802 /* Emit the specified user sample locations. */
803 switch (num_samples) {
804 case 2:
805 case 4:
806 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
807 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
808 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
809 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
810 break;
811 case 8:
812 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
813 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
814 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
815 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
816 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
817 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
818 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
819 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
820 break;
821 default:
822 unreachable("invalid number of samples");
823 }
824
825 /* Emit the maximum sample distance and the centroid priority. */
826 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
827
828 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
829 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
830
831 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
832 radeon_emit(cs, pa_sc_aa_config);
833
834 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
835 radeon_emit(cs, centroid_priority);
836 radeon_emit(cs, centroid_priority >> 32);
837
838 /* GFX9: Flush DFSM when the AA mode changes. */
839 if (cmd_buffer->device->dfsm_allowed) {
840 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
841 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
842 }
843
844 cmd_buffer->state.context_roll_without_scissor_emitted = true;
845 }
846
847 static void
848 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
849 struct radv_pipeline *pipeline,
850 gl_shader_stage stage,
851 int idx, int count, uint32_t *values)
852 {
853 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
854 uint32_t base_reg = pipeline->user_data_0[stage];
855 if (loc->sgpr_idx == -1)
856 return;
857
858 assert(loc->num_sgprs == count);
859
860 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
861 radeon_emit_array(cmd_buffer->cs, values, count);
862 }
863
864 static void
865 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
866 struct radv_pipeline *pipeline)
867 {
868 int num_samples = pipeline->graphics.ms.num_samples;
869 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
870
871 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
872 cmd_buffer->sample_positions_needed = true;
873
874 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
875 return;
876
877 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
878
879 cmd_buffer->state.context_roll_without_scissor_emitted = true;
880 }
881
882 static void
883 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
884 struct radv_pipeline *pipeline)
885 {
886 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
887
888
889 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
890 return;
891
892 if (old_pipeline &&
893 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
894 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
895 return;
896
897 bool binning_flush = false;
898 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
899 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
900 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
901 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
902 binning_flush = !old_pipeline ||
903 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
904 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
905 }
906
907 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
908 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
909 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
910
911 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
912 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
913 pipeline->graphics.binning.db_dfsm_control);
914 } else {
915 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
916 pipeline->graphics.binning.db_dfsm_control);
917 }
918
919 cmd_buffer->state.context_roll_without_scissor_emitted = true;
920 }
921
922
923 static void
924 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
925 struct radv_shader_variant *shader)
926 {
927 uint64_t va;
928
929 if (!shader)
930 return;
931
932 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
933
934 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
935 }
936
937 static void
938 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
939 struct radv_pipeline *pipeline,
940 bool vertex_stage_only)
941 {
942 struct radv_cmd_state *state = &cmd_buffer->state;
943 uint32_t mask = state->prefetch_L2_mask;
944
945 if (vertex_stage_only) {
946 /* Fast prefetch path for starting draws as soon as possible.
947 */
948 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
949 RADV_PREFETCH_VBO_DESCRIPTORS);
950 }
951
952 if (mask & RADV_PREFETCH_VS)
953 radv_emit_shader_prefetch(cmd_buffer,
954 pipeline->shaders[MESA_SHADER_VERTEX]);
955
956 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
957 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
958
959 if (mask & RADV_PREFETCH_TCS)
960 radv_emit_shader_prefetch(cmd_buffer,
961 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
962
963 if (mask & RADV_PREFETCH_TES)
964 radv_emit_shader_prefetch(cmd_buffer,
965 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
966
967 if (mask & RADV_PREFETCH_GS) {
968 radv_emit_shader_prefetch(cmd_buffer,
969 pipeline->shaders[MESA_SHADER_GEOMETRY]);
970 if (radv_pipeline_has_gs_copy_shader(pipeline))
971 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
972 }
973
974 if (mask & RADV_PREFETCH_PS)
975 radv_emit_shader_prefetch(cmd_buffer,
976 pipeline->shaders[MESA_SHADER_FRAGMENT]);
977
978 state->prefetch_L2_mask &= ~mask;
979 }
980
981 static void
982 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
983 {
984 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
985 return;
986
987 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
988 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
989
990 unsigned sx_ps_downconvert = 0;
991 unsigned sx_blend_opt_epsilon = 0;
992 unsigned sx_blend_opt_control = 0;
993
994 if (!cmd_buffer->state.attachments || !subpass)
995 return;
996
997 for (unsigned i = 0; i < subpass->color_count; ++i) {
998 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
999 /* We don't set the DISABLE bits, because the HW can't have holes,
1000 * so the SPI color format is set to 32-bit 1-component. */
1001 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1002 continue;
1003 }
1004
1005 int idx = subpass->color_attachments[i].attachment;
1006 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1007
1008 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1009 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1010 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1011 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1012
1013 bool has_alpha, has_rgb;
1014
1015 /* Set if RGB and A are present. */
1016 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1017
1018 if (format == V_028C70_COLOR_8 ||
1019 format == V_028C70_COLOR_16 ||
1020 format == V_028C70_COLOR_32)
1021 has_rgb = !has_alpha;
1022 else
1023 has_rgb = true;
1024
1025 /* Check the colormask and export format. */
1026 if (!(colormask & 0x7))
1027 has_rgb = false;
1028 if (!(colormask & 0x8))
1029 has_alpha = false;
1030
1031 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1032 has_rgb = false;
1033 has_alpha = false;
1034 }
1035
1036 /* Disable value checking for disabled channels. */
1037 if (!has_rgb)
1038 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1039 if (!has_alpha)
1040 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1041
1042 /* Enable down-conversion for 32bpp and smaller formats. */
1043 switch (format) {
1044 case V_028C70_COLOR_8:
1045 case V_028C70_COLOR_8_8:
1046 case V_028C70_COLOR_8_8_8_8:
1047 /* For 1 and 2-channel formats, use the superset thereof. */
1048 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1049 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1050 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1051 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1052 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1053 }
1054 break;
1055
1056 case V_028C70_COLOR_5_6_5:
1057 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1058 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1059 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1060 }
1061 break;
1062
1063 case V_028C70_COLOR_1_5_5_5:
1064 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1065 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1066 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1067 }
1068 break;
1069
1070 case V_028C70_COLOR_4_4_4_4:
1071 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1072 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1073 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1074 }
1075 break;
1076
1077 case V_028C70_COLOR_32:
1078 if (swap == V_028C70_SWAP_STD &&
1079 spi_format == V_028714_SPI_SHADER_32_R)
1080 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1081 else if (swap == V_028C70_SWAP_ALT_REV &&
1082 spi_format == V_028714_SPI_SHADER_32_AR)
1083 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1084 break;
1085
1086 case V_028C70_COLOR_16:
1087 case V_028C70_COLOR_16_16:
1088 /* For 1-channel formats, use the superset thereof. */
1089 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1090 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1091 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1092 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1093 if (swap == V_028C70_SWAP_STD ||
1094 swap == V_028C70_SWAP_STD_REV)
1095 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1096 else
1097 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1098 }
1099 break;
1100
1101 case V_028C70_COLOR_10_11_11:
1102 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1103 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1104 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1105 }
1106 break;
1107
1108 case V_028C70_COLOR_2_10_10_10:
1109 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1110 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1111 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1112 }
1113 break;
1114 }
1115 }
1116
1117 /* Do not set the DISABLE bits for the unused attachments, as that
1118 * breaks dual source blending in SkQP and does not seem to improve
1119 * performance. */
1120
1121 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1122 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1123 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1124 return;
1125
1126 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1127 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1128 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1129 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1130
1131 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1132
1133 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1134 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1135 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1136 }
1137
1138 static void
1139 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1140 {
1141 if (!cmd_buffer->device->pbb_allowed)
1142 return;
1143
1144 struct radv_binning_settings settings =
1145 radv_get_binning_settings(cmd_buffer->device->physical_device);
1146 bool break_for_new_ps =
1147 (!cmd_buffer->state.emitted_pipeline ||
1148 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1149 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1150 (settings.context_states_per_bin > 1 ||
1151 settings.persistent_states_per_bin > 1);
1152 bool break_for_new_cb_target_mask =
1153 (!cmd_buffer->state.emitted_pipeline ||
1154 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1155 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1156 settings.context_states_per_bin > 1;
1157
1158 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1159 return;
1160
1161 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1162 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1163 }
1164
1165 static void
1166 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1167 {
1168 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1169
1170 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1171 return;
1172
1173 radv_update_multisample_state(cmd_buffer, pipeline);
1174 radv_update_binning_state(cmd_buffer, pipeline);
1175
1176 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1177 pipeline->scratch_bytes_per_wave);
1178 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1179 pipeline->max_waves);
1180
1181 if (!cmd_buffer->state.emitted_pipeline ||
1182 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1183 pipeline->graphics.can_use_guardband)
1184 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1185
1186 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1187
1188 if (!cmd_buffer->state.emitted_pipeline ||
1189 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1190 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1191 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1192 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1193 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1194 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1195 }
1196
1197 radv_emit_batch_break_on_new_ps(cmd_buffer);
1198
1199 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1200 if (!pipeline->shaders[i])
1201 continue;
1202
1203 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1204 pipeline->shaders[i]->bo);
1205 }
1206
1207 if (radv_pipeline_has_gs_copy_shader(pipeline))
1208 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1209 pipeline->gs_copy_shader->bo);
1210
1211 if (unlikely(cmd_buffer->device->trace_bo))
1212 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1213
1214 cmd_buffer->state.emitted_pipeline = pipeline;
1215
1216 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1217 }
1218
1219 static void
1220 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1221 {
1222 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1223 cmd_buffer->state.dynamic.viewport.viewports);
1224 }
1225
1226 static void
1227 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1228 {
1229 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1230
1231 si_write_scissors(cmd_buffer->cs, 0, count,
1232 cmd_buffer->state.dynamic.scissor.scissors,
1233 cmd_buffer->state.dynamic.viewport.viewports,
1234 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1235
1236 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1237 }
1238
1239 static void
1240 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1241 {
1242 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1243 return;
1244
1245 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1246 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1247 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1248 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1249 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1250 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1251 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1252 }
1253 }
1254
1255 static void
1256 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1257 {
1258 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1259
1260 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1261 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1262 }
1263
1264 static void
1265 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1266 {
1267 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1268
1269 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1270 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1271 }
1272
1273 static void
1274 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1275 {
1276 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1277
1278 radeon_set_context_reg_seq(cmd_buffer->cs,
1279 R_028430_DB_STENCILREFMASK, 2);
1280 radeon_emit(cmd_buffer->cs,
1281 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1282 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1283 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1284 S_028430_STENCILOPVAL(1));
1285 radeon_emit(cmd_buffer->cs,
1286 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1287 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1288 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1289 S_028434_STENCILOPVAL_BF(1));
1290 }
1291
1292 static void
1293 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1294 {
1295 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1296
1297 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1298 fui(d->depth_bounds.min));
1299 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1300 fui(d->depth_bounds.max));
1301 }
1302
1303 static void
1304 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1305 {
1306 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1307 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1308 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1309
1310
1311 radeon_set_context_reg_seq(cmd_buffer->cs,
1312 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1313 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1314 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1315 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1316 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1317 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1318 }
1319
1320 static void
1321 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1322 int index,
1323 struct radv_color_buffer_info *cb,
1324 struct radv_image_view *iview,
1325 VkImageLayout layout,
1326 bool in_render_loop)
1327 {
1328 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1329 uint32_t cb_color_info = cb->cb_color_info;
1330 struct radv_image *image = iview->image;
1331
1332 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1333 radv_image_queue_family_mask(image,
1334 cmd_buffer->queue_family_index,
1335 cmd_buffer->queue_family_index))) {
1336 cb_color_info &= C_028C70_DCC_ENABLE;
1337 }
1338
1339 if (radv_image_is_tc_compat_cmask(image) &&
1340 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1341 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1342 /* If this bit is set, the FMASK decompression operation
1343 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1344 */
1345 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1346 }
1347
1348 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1349 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1350 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1351 radeon_emit(cmd_buffer->cs, 0);
1352 radeon_emit(cmd_buffer->cs, 0);
1353 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1354 radeon_emit(cmd_buffer->cs, cb_color_info);
1355 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1356 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1357 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1358 radeon_emit(cmd_buffer->cs, 0);
1359 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1360 radeon_emit(cmd_buffer->cs, 0);
1361
1362 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1363 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1364
1365 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1366 cb->cb_color_base >> 32);
1367 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1368 cb->cb_color_cmask >> 32);
1369 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1370 cb->cb_color_fmask >> 32);
1371 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1372 cb->cb_dcc_base >> 32);
1373 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1374 cb->cb_color_attrib2);
1375 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1376 cb->cb_color_attrib3);
1377 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1378 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1379 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1380 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1381 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1382 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1383 radeon_emit(cmd_buffer->cs, cb_color_info);
1384 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1385 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1386 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1387 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1388 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1389 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1390
1391 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1392 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1393 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1394
1395 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1396 cb->cb_mrt_epitch);
1397 } else {
1398 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1399 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1400 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1401 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1402 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1403 radeon_emit(cmd_buffer->cs, cb_color_info);
1404 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1405 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1406 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1407 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1408 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1409 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1410
1411 if (is_vi) { /* DCC BASE */
1412 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1413 }
1414 }
1415
1416 if (radv_dcc_enabled(image, iview->base_mip)) {
1417 /* Drawing with DCC enabled also compresses colorbuffers. */
1418 VkImageSubresourceRange range = {
1419 .aspectMask = iview->aspect_mask,
1420 .baseMipLevel = iview->base_mip,
1421 .levelCount = iview->level_count,
1422 .baseArrayLayer = iview->base_layer,
1423 .layerCount = iview->layer_count,
1424 };
1425
1426 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1427 }
1428 }
1429
1430 static void
1431 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1432 struct radv_ds_buffer_info *ds,
1433 const struct radv_image_view *iview,
1434 VkImageLayout layout,
1435 bool in_render_loop, bool requires_cond_exec)
1436 {
1437 const struct radv_image *image = iview->image;
1438 uint32_t db_z_info = ds->db_z_info;
1439 uint32_t db_z_info_reg;
1440
1441 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1442 !radv_image_is_tc_compat_htile(image))
1443 return;
1444
1445 if (!radv_layout_has_htile(image, layout, in_render_loop,
1446 radv_image_queue_family_mask(image,
1447 cmd_buffer->queue_family_index,
1448 cmd_buffer->queue_family_index))) {
1449 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1450 }
1451
1452 db_z_info &= C_028040_ZRANGE_PRECISION;
1453
1454 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1455 db_z_info_reg = R_028038_DB_Z_INFO;
1456 } else {
1457 db_z_info_reg = R_028040_DB_Z_INFO;
1458 }
1459
1460 /* When we don't know the last fast clear value we need to emit a
1461 * conditional packet that will eventually skip the following
1462 * SET_CONTEXT_REG packet.
1463 */
1464 if (requires_cond_exec) {
1465 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1466
1467 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1468 radeon_emit(cmd_buffer->cs, va);
1469 radeon_emit(cmd_buffer->cs, va >> 32);
1470 radeon_emit(cmd_buffer->cs, 0);
1471 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1472 }
1473
1474 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1475 }
1476
1477 static void
1478 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1479 struct radv_ds_buffer_info *ds,
1480 struct radv_image_view *iview,
1481 VkImageLayout layout,
1482 bool in_render_loop)
1483 {
1484 const struct radv_image *image = iview->image;
1485 uint32_t db_z_info = ds->db_z_info;
1486 uint32_t db_stencil_info = ds->db_stencil_info;
1487
1488 if (!radv_layout_has_htile(image, layout, in_render_loop,
1489 radv_image_queue_family_mask(image,
1490 cmd_buffer->queue_family_index,
1491 cmd_buffer->queue_family_index))) {
1492 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1493 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1494 }
1495
1496 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1497 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1498
1499 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1500 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1501 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1502
1503 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1504 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1505 radeon_emit(cmd_buffer->cs, db_z_info);
1506 radeon_emit(cmd_buffer->cs, db_stencil_info);
1507 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1508 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1509 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1510 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1511
1512 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1513 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1514 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1515 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1516 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1517 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1518 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1519 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1520 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1521 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1522 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1523
1524 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1525 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1526 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1527 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1528 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1529 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1530 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1531 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1532 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1533 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1534 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1535
1536 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1537 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1538 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1539 } else {
1540 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1541
1542 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1543 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1544 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1545 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1546 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1547 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1548 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1549 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1550 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1551 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1552
1553 }
1554
1555 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1556 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1557 in_render_loop, true);
1558
1559 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1560 ds->pa_su_poly_offset_db_fmt_cntl);
1561 }
1562
1563 /**
1564 * Update the fast clear depth/stencil values if the image is bound as a
1565 * depth/stencil buffer.
1566 */
1567 static void
1568 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1569 const struct radv_image_view *iview,
1570 VkClearDepthStencilValue ds_clear_value,
1571 VkImageAspectFlags aspects)
1572 {
1573 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1574 const struct radv_image *image = iview->image;
1575 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1576 uint32_t att_idx;
1577
1578 if (!cmd_buffer->state.attachments || !subpass)
1579 return;
1580
1581 if (!subpass->depth_stencil_attachment)
1582 return;
1583
1584 att_idx = subpass->depth_stencil_attachment->attachment;
1585 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1586 return;
1587
1588 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1589 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1590 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1591 radeon_emit(cs, ds_clear_value.stencil);
1592 radeon_emit(cs, fui(ds_clear_value.depth));
1593 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1594 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1595 radeon_emit(cs, fui(ds_clear_value.depth));
1596 } else {
1597 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1598 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1599 radeon_emit(cs, ds_clear_value.stencil);
1600 }
1601
1602 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1603 * only needed when clearing Z to 0.0.
1604 */
1605 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1606 ds_clear_value.depth == 0.0) {
1607 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1608 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1609
1610 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1611 iview, layout, in_render_loop, false);
1612 }
1613
1614 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1615 }
1616
1617 /**
1618 * Set the clear depth/stencil values to the image's metadata.
1619 */
1620 static void
1621 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1622 struct radv_image *image,
1623 const VkImageSubresourceRange *range,
1624 VkClearDepthStencilValue ds_clear_value,
1625 VkImageAspectFlags aspects)
1626 {
1627 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1628 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1629 uint32_t level_count = radv_get_levelCount(image, range);
1630
1631 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1632 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1633 /* Use the fastest way when both aspects are used. */
1634 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1635 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1636 S_370_WR_CONFIRM(1) |
1637 S_370_ENGINE_SEL(V_370_PFP));
1638 radeon_emit(cs, va);
1639 radeon_emit(cs, va >> 32);
1640
1641 for (uint32_t l = 0; l < level_count; l++) {
1642 radeon_emit(cs, ds_clear_value.stencil);
1643 radeon_emit(cs, fui(ds_clear_value.depth));
1644 }
1645 } else {
1646 /* Otherwise we need one WRITE_DATA packet per level. */
1647 for (uint32_t l = 0; l < level_count; l++) {
1648 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1649 unsigned value;
1650
1651 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1652 value = fui(ds_clear_value.depth);
1653 va += 4;
1654 } else {
1655 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1656 value = ds_clear_value.stencil;
1657 }
1658
1659 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1660 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1661 S_370_WR_CONFIRM(1) |
1662 S_370_ENGINE_SEL(V_370_PFP));
1663 radeon_emit(cs, va);
1664 radeon_emit(cs, va >> 32);
1665 radeon_emit(cs, value);
1666 }
1667 }
1668 }
1669
1670 /**
1671 * Update the TC-compat metadata value for this image.
1672 */
1673 static void
1674 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1675 struct radv_image *image,
1676 const VkImageSubresourceRange *range,
1677 uint32_t value)
1678 {
1679 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1680
1681 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1682 return;
1683
1684 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1685 uint32_t level_count = radv_get_levelCount(image, range);
1686
1687 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1688 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1689 S_370_WR_CONFIRM(1) |
1690 S_370_ENGINE_SEL(V_370_PFP));
1691 radeon_emit(cs, va);
1692 radeon_emit(cs, va >> 32);
1693
1694 for (uint32_t l = 0; l < level_count; l++)
1695 radeon_emit(cs, value);
1696 }
1697
1698 static void
1699 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1700 const struct radv_image_view *iview,
1701 VkClearDepthStencilValue ds_clear_value)
1702 {
1703 VkImageSubresourceRange range = {
1704 .aspectMask = iview->aspect_mask,
1705 .baseMipLevel = iview->base_mip,
1706 .levelCount = iview->level_count,
1707 .baseArrayLayer = iview->base_layer,
1708 .layerCount = iview->layer_count,
1709 };
1710 uint32_t cond_val;
1711
1712 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1713 * depth clear value is 0.0f.
1714 */
1715 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1716
1717 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1718 cond_val);
1719 }
1720
1721 /**
1722 * Update the clear depth/stencil values for this image.
1723 */
1724 void
1725 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1726 const struct radv_image_view *iview,
1727 VkClearDepthStencilValue ds_clear_value,
1728 VkImageAspectFlags aspects)
1729 {
1730 VkImageSubresourceRange range = {
1731 .aspectMask = iview->aspect_mask,
1732 .baseMipLevel = iview->base_mip,
1733 .levelCount = iview->level_count,
1734 .baseArrayLayer = iview->base_layer,
1735 .layerCount = iview->layer_count,
1736 };
1737 struct radv_image *image = iview->image;
1738
1739 assert(radv_image_has_htile(image));
1740
1741 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1742 ds_clear_value, aspects);
1743
1744 if (radv_image_is_tc_compat_htile(image) &&
1745 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1746 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1747 ds_clear_value);
1748 }
1749
1750 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1751 aspects);
1752 }
1753
1754 /**
1755 * Load the clear depth/stencil values from the image's metadata.
1756 */
1757 static void
1758 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1759 const struct radv_image_view *iview)
1760 {
1761 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1762 const struct radv_image *image = iview->image;
1763 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1764 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1765 unsigned reg_offset = 0, reg_count = 0;
1766
1767 if (!radv_image_has_htile(image))
1768 return;
1769
1770 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1771 ++reg_count;
1772 } else {
1773 ++reg_offset;
1774 va += 4;
1775 }
1776 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1777 ++reg_count;
1778
1779 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1780
1781 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1782 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1783 radeon_emit(cs, va);
1784 radeon_emit(cs, va >> 32);
1785 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1786 radeon_emit(cs, reg_count);
1787 } else {
1788 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1789 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1790 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1791 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1792 radeon_emit(cs, va);
1793 radeon_emit(cs, va >> 32);
1794 radeon_emit(cs, reg >> 2);
1795 radeon_emit(cs, 0);
1796
1797 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1798 radeon_emit(cs, 0);
1799 }
1800 }
1801
1802 /*
1803 * With DCC some colors don't require CMASK elimination before being
1804 * used as a texture. This sets a predicate value to determine if the
1805 * cmask eliminate is required.
1806 */
1807 void
1808 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1809 struct radv_image *image,
1810 const VkImageSubresourceRange *range, bool value)
1811 {
1812 uint64_t pred_val = value;
1813 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1814 uint32_t level_count = radv_get_levelCount(image, range);
1815 uint32_t count = 2 * level_count;
1816
1817 assert(radv_dcc_enabled(image, range->baseMipLevel));
1818
1819 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1820 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1821 S_370_WR_CONFIRM(1) |
1822 S_370_ENGINE_SEL(V_370_PFP));
1823 radeon_emit(cmd_buffer->cs, va);
1824 radeon_emit(cmd_buffer->cs, va >> 32);
1825
1826 for (uint32_t l = 0; l < level_count; l++) {
1827 radeon_emit(cmd_buffer->cs, pred_val);
1828 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1829 }
1830 }
1831
1832 /**
1833 * Update the DCC predicate to reflect the compression state.
1834 */
1835 void
1836 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1837 struct radv_image *image,
1838 const VkImageSubresourceRange *range, bool value)
1839 {
1840 uint64_t pred_val = value;
1841 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1842 uint32_t level_count = radv_get_levelCount(image, range);
1843 uint32_t count = 2 * level_count;
1844
1845 assert(radv_dcc_enabled(image, range->baseMipLevel));
1846
1847 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1848 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1849 S_370_WR_CONFIRM(1) |
1850 S_370_ENGINE_SEL(V_370_PFP));
1851 radeon_emit(cmd_buffer->cs, va);
1852 radeon_emit(cmd_buffer->cs, va >> 32);
1853
1854 for (uint32_t l = 0; l < level_count; l++) {
1855 radeon_emit(cmd_buffer->cs, pred_val);
1856 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1857 }
1858 }
1859
1860 /**
1861 * Update the fast clear color values if the image is bound as a color buffer.
1862 */
1863 static void
1864 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1865 struct radv_image *image,
1866 int cb_idx,
1867 uint32_t color_values[2])
1868 {
1869 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1870 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1871 uint32_t att_idx;
1872
1873 if (!cmd_buffer->state.attachments || !subpass)
1874 return;
1875
1876 att_idx = subpass->color_attachments[cb_idx].attachment;
1877 if (att_idx == VK_ATTACHMENT_UNUSED)
1878 return;
1879
1880 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1881 return;
1882
1883 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1884 radeon_emit(cs, color_values[0]);
1885 radeon_emit(cs, color_values[1]);
1886
1887 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1888 }
1889
1890 /**
1891 * Set the clear color values to the image's metadata.
1892 */
1893 static void
1894 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1895 struct radv_image *image,
1896 const VkImageSubresourceRange *range,
1897 uint32_t color_values[2])
1898 {
1899 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1900 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1901 uint32_t level_count = radv_get_levelCount(image, range);
1902 uint32_t count = 2 * level_count;
1903
1904 assert(radv_image_has_cmask(image) ||
1905 radv_dcc_enabled(image, range->baseMipLevel));
1906
1907 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1908 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1909 S_370_WR_CONFIRM(1) |
1910 S_370_ENGINE_SEL(V_370_PFP));
1911 radeon_emit(cs, va);
1912 radeon_emit(cs, va >> 32);
1913
1914 for (uint32_t l = 0; l < level_count; l++) {
1915 radeon_emit(cs, color_values[0]);
1916 radeon_emit(cs, color_values[1]);
1917 }
1918 }
1919
1920 /**
1921 * Update the clear color values for this image.
1922 */
1923 void
1924 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1925 const struct radv_image_view *iview,
1926 int cb_idx,
1927 uint32_t color_values[2])
1928 {
1929 struct radv_image *image = iview->image;
1930 VkImageSubresourceRange range = {
1931 .aspectMask = iview->aspect_mask,
1932 .baseMipLevel = iview->base_mip,
1933 .levelCount = iview->level_count,
1934 .baseArrayLayer = iview->base_layer,
1935 .layerCount = iview->layer_count,
1936 };
1937
1938 assert(radv_image_has_cmask(image) ||
1939 radv_dcc_enabled(image, iview->base_mip));
1940
1941 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1942
1943 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1944 color_values);
1945 }
1946
1947 /**
1948 * Load the clear color values from the image's metadata.
1949 */
1950 static void
1951 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1952 struct radv_image_view *iview,
1953 int cb_idx)
1954 {
1955 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1956 struct radv_image *image = iview->image;
1957 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1958
1959 if (!radv_image_has_cmask(image) &&
1960 !radv_dcc_enabled(image, iview->base_mip))
1961 return;
1962
1963 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1964
1965 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1966 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1967 radeon_emit(cs, va);
1968 radeon_emit(cs, va >> 32);
1969 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1970 radeon_emit(cs, 2);
1971 } else {
1972 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1973 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1974 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1975 COPY_DATA_COUNT_SEL);
1976 radeon_emit(cs, va);
1977 radeon_emit(cs, va >> 32);
1978 radeon_emit(cs, reg >> 2);
1979 radeon_emit(cs, 0);
1980
1981 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1982 radeon_emit(cs, 0);
1983 }
1984 }
1985
1986 static void
1987 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1988 {
1989 int i;
1990 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1991 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1992
1993 /* this may happen for inherited secondary recording */
1994 if (!framebuffer)
1995 return;
1996
1997 for (i = 0; i < 8; ++i) {
1998 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1999 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2000 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2001 continue;
2002 }
2003
2004 int idx = subpass->color_attachments[i].attachment;
2005 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2006 VkImageLayout layout = subpass->color_attachments[i].layout;
2007 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2008
2009 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2010
2011 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2012 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2013 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2014
2015 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2016 }
2017
2018 if (subpass->depth_stencil_attachment) {
2019 int idx = subpass->depth_stencil_attachment->attachment;
2020 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2021 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2022 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2023 struct radv_image *image = iview->image;
2024 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2025 ASSERTED uint32_t queue_mask = radv_image_queue_family_mask(image,
2026 cmd_buffer->queue_family_index,
2027 cmd_buffer->queue_family_index);
2028 /* We currently don't support writing decompressed HTILE */
2029 assert(radv_layout_has_htile(image, layout, in_render_loop, queue_mask) ==
2030 radv_layout_is_htile_compressed(image, layout, in_render_loop, queue_mask));
2031
2032 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2033
2034 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2035 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2036 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2037 }
2038 radv_load_ds_clear_metadata(cmd_buffer, iview);
2039 } else {
2040 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2041 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2042 else
2043 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2044
2045 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2046 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2047 }
2048 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2049 S_028208_BR_X(framebuffer->width) |
2050 S_028208_BR_Y(framebuffer->height));
2051
2052 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2053 bool disable_constant_encode =
2054 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2055 enum chip_class chip_class =
2056 cmd_buffer->device->physical_device->rad_info.chip_class;
2057 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2058
2059 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2060 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2061 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2062 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2063 }
2064
2065 if (cmd_buffer->device->dfsm_allowed) {
2066 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2067 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2068 }
2069
2070 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2071 }
2072
2073 static void
2074 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
2075 {
2076 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2077 struct radv_cmd_state *state = &cmd_buffer->state;
2078
2079 if (state->index_type != state->last_index_type) {
2080 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2081 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2082 cs, R_03090C_VGT_INDEX_TYPE,
2083 2, state->index_type);
2084 } else {
2085 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2086 radeon_emit(cs, state->index_type);
2087 }
2088
2089 state->last_index_type = state->index_type;
2090 }
2091
2092 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2093 * the index_va and max_index_count already. */
2094 if (!indirect)
2095 return;
2096
2097 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2098 radeon_emit(cs, state->index_va);
2099 radeon_emit(cs, state->index_va >> 32);
2100
2101 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2102 radeon_emit(cs, state->max_index_count);
2103
2104 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2105 }
2106
2107 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2108 {
2109 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2110 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2111 uint32_t pa_sc_mode_cntl_1 =
2112 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2113 uint32_t db_count_control;
2114
2115 if(!cmd_buffer->state.active_occlusion_queries) {
2116 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2117 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2118 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2119 has_perfect_queries) {
2120 /* Re-enable out-of-order rasterization if the
2121 * bound pipeline supports it and if it's has
2122 * been disabled before starting any perfect
2123 * occlusion queries.
2124 */
2125 radeon_set_context_reg(cmd_buffer->cs,
2126 R_028A4C_PA_SC_MODE_CNTL_1,
2127 pa_sc_mode_cntl_1);
2128 }
2129 }
2130 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2131 } else {
2132 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2133 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2134 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2135
2136 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2137 db_count_control =
2138 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2139 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2140 S_028004_SAMPLE_RATE(sample_rate) |
2141 S_028004_ZPASS_ENABLE(1) |
2142 S_028004_SLICE_EVEN_ENABLE(1) |
2143 S_028004_SLICE_ODD_ENABLE(1);
2144
2145 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2146 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2147 has_perfect_queries) {
2148 /* If the bound pipeline has enabled
2149 * out-of-order rasterization, we should
2150 * disable it before starting any perfect
2151 * occlusion queries.
2152 */
2153 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2154
2155 radeon_set_context_reg(cmd_buffer->cs,
2156 R_028A4C_PA_SC_MODE_CNTL_1,
2157 pa_sc_mode_cntl_1);
2158 }
2159 } else {
2160 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2161 S_028004_SAMPLE_RATE(sample_rate);
2162 }
2163 }
2164
2165 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2166
2167 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2168 }
2169
2170 static void
2171 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2172 {
2173 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2174
2175 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2176 radv_emit_viewport(cmd_buffer);
2177
2178 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2179 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2180 radv_emit_scissor(cmd_buffer);
2181
2182 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2183 radv_emit_line_width(cmd_buffer);
2184
2185 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2186 radv_emit_blend_constants(cmd_buffer);
2187
2188 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2189 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2190 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2191 radv_emit_stencil(cmd_buffer);
2192
2193 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2194 radv_emit_depth_bounds(cmd_buffer);
2195
2196 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2197 radv_emit_depth_bias(cmd_buffer);
2198
2199 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2200 radv_emit_discard_rectangle(cmd_buffer);
2201
2202 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2203 radv_emit_sample_locations(cmd_buffer);
2204
2205 cmd_buffer->state.dirty &= ~states;
2206 }
2207
2208 static void
2209 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2210 VkPipelineBindPoint bind_point)
2211 {
2212 struct radv_descriptor_state *descriptors_state =
2213 radv_get_descriptors_state(cmd_buffer, bind_point);
2214 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2215 unsigned bo_offset;
2216
2217 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2218 set->mapped_ptr,
2219 &bo_offset))
2220 return;
2221
2222 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2223 set->va += bo_offset;
2224 }
2225
2226 static void
2227 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2228 VkPipelineBindPoint bind_point)
2229 {
2230 struct radv_descriptor_state *descriptors_state =
2231 radv_get_descriptors_state(cmd_buffer, bind_point);
2232 uint32_t size = MAX_SETS * 4;
2233 uint32_t offset;
2234 void *ptr;
2235
2236 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2237 256, &offset, &ptr))
2238 return;
2239
2240 for (unsigned i = 0; i < MAX_SETS; i++) {
2241 uint32_t *uptr = ((uint32_t *)ptr) + i;
2242 uint64_t set_va = 0;
2243 struct radv_descriptor_set *set = descriptors_state->sets[i];
2244 if (descriptors_state->valid & (1u << i))
2245 set_va = set->va;
2246 uptr[0] = set_va & 0xffffffff;
2247 }
2248
2249 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2250 va += offset;
2251
2252 if (cmd_buffer->state.pipeline) {
2253 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2254 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2255 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2256
2257 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2258 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2259 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2260
2261 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2262 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2263 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2264
2265 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2266 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2267 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2268
2269 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2270 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2271 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2272 }
2273
2274 if (cmd_buffer->state.compute_pipeline)
2275 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2276 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2277 }
2278
2279 static void
2280 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2281 VkShaderStageFlags stages)
2282 {
2283 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2284 VK_PIPELINE_BIND_POINT_COMPUTE :
2285 VK_PIPELINE_BIND_POINT_GRAPHICS;
2286 struct radv_descriptor_state *descriptors_state =
2287 radv_get_descriptors_state(cmd_buffer, bind_point);
2288 struct radv_cmd_state *state = &cmd_buffer->state;
2289 bool flush_indirect_descriptors;
2290
2291 if (!descriptors_state->dirty)
2292 return;
2293
2294 if (descriptors_state->push_dirty)
2295 radv_flush_push_descriptors(cmd_buffer, bind_point);
2296
2297 flush_indirect_descriptors =
2298 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2299 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2300 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2301 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2302
2303 if (flush_indirect_descriptors)
2304 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2305
2306 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2307 cmd_buffer->cs,
2308 MAX_SETS * MESA_SHADER_STAGES * 4);
2309
2310 if (cmd_buffer->state.pipeline) {
2311 radv_foreach_stage(stage, stages) {
2312 if (!cmd_buffer->state.pipeline->shaders[stage])
2313 continue;
2314
2315 radv_emit_descriptor_pointers(cmd_buffer,
2316 cmd_buffer->state.pipeline,
2317 descriptors_state, stage);
2318 }
2319 }
2320
2321 if (cmd_buffer->state.compute_pipeline &&
2322 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2323 radv_emit_descriptor_pointers(cmd_buffer,
2324 cmd_buffer->state.compute_pipeline,
2325 descriptors_state,
2326 MESA_SHADER_COMPUTE);
2327 }
2328
2329 descriptors_state->dirty = 0;
2330 descriptors_state->push_dirty = false;
2331
2332 assert(cmd_buffer->cs->cdw <= cdw_max);
2333
2334 if (unlikely(cmd_buffer->device->trace_bo))
2335 radv_save_descriptors(cmd_buffer, bind_point);
2336 }
2337
2338 static void
2339 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2340 VkShaderStageFlags stages)
2341 {
2342 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2343 ? cmd_buffer->state.compute_pipeline
2344 : cmd_buffer->state.pipeline;
2345 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2346 VK_PIPELINE_BIND_POINT_COMPUTE :
2347 VK_PIPELINE_BIND_POINT_GRAPHICS;
2348 struct radv_descriptor_state *descriptors_state =
2349 radv_get_descriptors_state(cmd_buffer, bind_point);
2350 struct radv_pipeline_layout *layout = pipeline->layout;
2351 struct radv_shader_variant *shader, *prev_shader;
2352 bool need_push_constants = false;
2353 unsigned offset;
2354 void *ptr;
2355 uint64_t va;
2356
2357 stages &= cmd_buffer->push_constant_stages;
2358 if (!stages ||
2359 (!layout->push_constant_size && !layout->dynamic_offset_count))
2360 return;
2361
2362 radv_foreach_stage(stage, stages) {
2363 shader = radv_get_shader(pipeline, stage);
2364 if (!shader)
2365 continue;
2366
2367 need_push_constants |= shader->info.loads_push_constants;
2368 need_push_constants |= shader->info.loads_dynamic_offsets;
2369
2370 uint8_t base = shader->info.base_inline_push_consts;
2371 uint8_t count = shader->info.num_inline_push_consts;
2372
2373 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2374 AC_UD_INLINE_PUSH_CONSTANTS,
2375 count,
2376 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2377 }
2378
2379 if (need_push_constants) {
2380 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2381 16 * layout->dynamic_offset_count,
2382 256, &offset, &ptr))
2383 return;
2384
2385 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2386 memcpy((char*)ptr + layout->push_constant_size,
2387 descriptors_state->dynamic_buffers,
2388 16 * layout->dynamic_offset_count);
2389
2390 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2391 va += offset;
2392
2393 ASSERTED unsigned cdw_max =
2394 radeon_check_space(cmd_buffer->device->ws,
2395 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2396
2397 prev_shader = NULL;
2398 radv_foreach_stage(stage, stages) {
2399 shader = radv_get_shader(pipeline, stage);
2400
2401 /* Avoid redundantly emitting the address for merged stages. */
2402 if (shader && shader != prev_shader) {
2403 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2404 AC_UD_PUSH_CONSTANTS, va);
2405
2406 prev_shader = shader;
2407 }
2408 }
2409 assert(cmd_buffer->cs->cdw <= cdw_max);
2410 }
2411
2412 cmd_buffer->push_constant_stages &= ~stages;
2413 }
2414
2415 static void
2416 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2417 bool pipeline_is_dirty)
2418 {
2419 if ((pipeline_is_dirty ||
2420 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2421 cmd_buffer->state.pipeline->num_vertex_bindings &&
2422 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2423 unsigned vb_offset;
2424 void *vb_ptr;
2425 uint32_t i = 0;
2426 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2427 uint64_t va;
2428
2429 /* allocate some descriptor state for vertex buffers */
2430 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2431 &vb_offset, &vb_ptr))
2432 return;
2433
2434 for (i = 0; i < count; i++) {
2435 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2436 uint32_t offset;
2437 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2438 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2439 unsigned num_records;
2440
2441 if (!buffer)
2442 continue;
2443
2444 va = radv_buffer_get_va(buffer->bo);
2445
2446 offset = cmd_buffer->vertex_bindings[i].offset;
2447 va += offset + buffer->offset;
2448
2449 num_records = buffer->size - offset;
2450 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2451 num_records /= stride;
2452
2453 desc[0] = va;
2454 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2455 desc[2] = num_records;
2456 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2457 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2458 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2459 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2460
2461 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2462 /* OOB_SELECT chooses the out-of-bounds check:
2463 * - 1: index >= NUM_RECORDS (Structured)
2464 * - 3: offset >= NUM_RECORDS (Raw)
2465 */
2466 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2467
2468 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2469 S_008F0C_OOB_SELECT(oob_select) |
2470 S_008F0C_RESOURCE_LEVEL(1);
2471 } else {
2472 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2473 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2474 }
2475 }
2476
2477 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2478 va += vb_offset;
2479
2480 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2481 AC_UD_VS_VERTEX_BUFFERS, va);
2482
2483 cmd_buffer->state.vb_va = va;
2484 cmd_buffer->state.vb_size = count * 16;
2485 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2486 }
2487 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2488 }
2489
2490 static void
2491 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2492 {
2493 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2494 struct radv_userdata_info *loc;
2495 uint32_t base_reg;
2496
2497 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2498 if (!radv_get_shader(pipeline, stage))
2499 continue;
2500
2501 loc = radv_lookup_user_sgpr(pipeline, stage,
2502 AC_UD_STREAMOUT_BUFFERS);
2503 if (loc->sgpr_idx == -1)
2504 continue;
2505
2506 base_reg = pipeline->user_data_0[stage];
2507
2508 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2509 base_reg + loc->sgpr_idx * 4, va, false);
2510 }
2511
2512 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2513 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2514 if (loc->sgpr_idx != -1) {
2515 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2516
2517 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2518 base_reg + loc->sgpr_idx * 4, va, false);
2519 }
2520 }
2521 }
2522
2523 static void
2524 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2525 {
2526 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2527 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2528 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2529 unsigned so_offset;
2530 void *so_ptr;
2531 uint64_t va;
2532
2533 /* Allocate some descriptor state for streamout buffers. */
2534 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2535 MAX_SO_BUFFERS * 16, 256,
2536 &so_offset, &so_ptr))
2537 return;
2538
2539 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2540 struct radv_buffer *buffer = sb[i].buffer;
2541 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2542
2543 if (!(so->enabled_mask & (1 << i)))
2544 continue;
2545
2546 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2547
2548 va += sb[i].offset;
2549
2550 /* Set the descriptor.
2551 *
2552 * On GFX8, the format must be non-INVALID, otherwise
2553 * the buffer will be considered not bound and store
2554 * instructions will be no-ops.
2555 */
2556 uint32_t size = 0xffffffff;
2557
2558 /* Compute the correct buffer size for NGG streamout
2559 * because it's used to determine the max emit per
2560 * buffer.
2561 */
2562 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2563 size = buffer->size - sb[i].offset;
2564
2565 desc[0] = va;
2566 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2567 desc[2] = size;
2568 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2569 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2570 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2571 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2572
2573 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2574 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2575 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2576 S_008F0C_RESOURCE_LEVEL(1);
2577 } else {
2578 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2579 }
2580 }
2581
2582 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2583 va += so_offset;
2584
2585 radv_emit_streamout_buffers(cmd_buffer, va);
2586 }
2587
2588 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2589 }
2590
2591 static void
2592 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2593 {
2594 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2595 struct radv_userdata_info *loc;
2596 uint32_t ngg_gs_state = 0;
2597 uint32_t base_reg;
2598
2599 if (!radv_pipeline_has_gs(pipeline) ||
2600 !radv_pipeline_has_ngg(pipeline))
2601 return;
2602
2603 /* By default NGG GS queries are disabled but they are enabled if the
2604 * command buffer has active GDS queries or if it's a secondary command
2605 * buffer that inherits the number of generated primitives.
2606 */
2607 if (cmd_buffer->state.active_pipeline_gds_queries ||
2608 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2609 ngg_gs_state = 1;
2610
2611 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2612 AC_UD_NGG_GS_STATE);
2613 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2614 assert(loc->sgpr_idx != -1);
2615
2616 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2617 ngg_gs_state);
2618 }
2619
2620 static void
2621 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2622 {
2623 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2624 radv_flush_streamout_descriptors(cmd_buffer);
2625 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2626 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2627 radv_flush_ngg_gs_state(cmd_buffer);
2628 }
2629
2630 struct radv_draw_info {
2631 /**
2632 * Number of vertices.
2633 */
2634 uint32_t count;
2635
2636 /**
2637 * Index of the first vertex.
2638 */
2639 int32_t vertex_offset;
2640
2641 /**
2642 * First instance id.
2643 */
2644 uint32_t first_instance;
2645
2646 /**
2647 * Number of instances.
2648 */
2649 uint32_t instance_count;
2650
2651 /**
2652 * First index (indexed draws only).
2653 */
2654 uint32_t first_index;
2655
2656 /**
2657 * Whether it's an indexed draw.
2658 */
2659 bool indexed;
2660
2661 /**
2662 * Indirect draw parameters resource.
2663 */
2664 struct radv_buffer *indirect;
2665 uint64_t indirect_offset;
2666 uint32_t stride;
2667
2668 /**
2669 * Draw count parameters resource.
2670 */
2671 struct radv_buffer *count_buffer;
2672 uint64_t count_buffer_offset;
2673
2674 /**
2675 * Stream output parameters resource.
2676 */
2677 struct radv_buffer *strmout_buffer;
2678 uint64_t strmout_buffer_offset;
2679 };
2680
2681 static uint32_t
2682 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2683 {
2684 switch (cmd_buffer->state.index_type) {
2685 case V_028A7C_VGT_INDEX_8:
2686 return 0xffu;
2687 case V_028A7C_VGT_INDEX_16:
2688 return 0xffffu;
2689 case V_028A7C_VGT_INDEX_32:
2690 return 0xffffffffu;
2691 default:
2692 unreachable("invalid index type");
2693 }
2694 }
2695
2696 static void
2697 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2698 bool instanced_draw, bool indirect_draw,
2699 bool count_from_stream_output,
2700 uint32_t draw_vertex_count)
2701 {
2702 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2703 struct radv_cmd_state *state = &cmd_buffer->state;
2704 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2705 unsigned ia_multi_vgt_param;
2706
2707 ia_multi_vgt_param =
2708 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2709 indirect_draw,
2710 count_from_stream_output,
2711 draw_vertex_count);
2712
2713 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2714 if (info->chip_class == GFX9) {
2715 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2716 cs,
2717 R_030960_IA_MULTI_VGT_PARAM,
2718 4, ia_multi_vgt_param);
2719 } else if (info->chip_class >= GFX7) {
2720 radeon_set_context_reg_idx(cs,
2721 R_028AA8_IA_MULTI_VGT_PARAM,
2722 1, ia_multi_vgt_param);
2723 } else {
2724 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2725 ia_multi_vgt_param);
2726 }
2727 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2728 }
2729 }
2730
2731 static void
2732 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2733 const struct radv_draw_info *draw_info)
2734 {
2735 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2736 struct radv_cmd_state *state = &cmd_buffer->state;
2737 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2738 int32_t primitive_reset_en;
2739
2740 /* Draw state. */
2741 if (info->chip_class < GFX10) {
2742 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2743 draw_info->indirect,
2744 !!draw_info->strmout_buffer,
2745 draw_info->indirect ? 0 : draw_info->count);
2746 }
2747
2748 /* Primitive restart. */
2749 primitive_reset_en =
2750 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2751
2752 if (primitive_reset_en != state->last_primitive_reset_en) {
2753 state->last_primitive_reset_en = primitive_reset_en;
2754 if (info->chip_class >= GFX9) {
2755 radeon_set_uconfig_reg(cs,
2756 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2757 primitive_reset_en);
2758 } else {
2759 radeon_set_context_reg(cs,
2760 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2761 primitive_reset_en);
2762 }
2763 }
2764
2765 if (primitive_reset_en) {
2766 uint32_t primitive_reset_index =
2767 radv_get_primitive_reset_index(cmd_buffer);
2768
2769 if (primitive_reset_index != state->last_primitive_reset_index) {
2770 radeon_set_context_reg(cs,
2771 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2772 primitive_reset_index);
2773 state->last_primitive_reset_index = primitive_reset_index;
2774 }
2775 }
2776
2777 if (draw_info->strmout_buffer) {
2778 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2779
2780 va += draw_info->strmout_buffer->offset +
2781 draw_info->strmout_buffer_offset;
2782
2783 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2784 draw_info->stride);
2785
2786 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2787 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2788 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2789 COPY_DATA_WR_CONFIRM);
2790 radeon_emit(cs, va);
2791 radeon_emit(cs, va >> 32);
2792 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2793 radeon_emit(cs, 0); /* unused */
2794
2795 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2796 }
2797 }
2798
2799 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2800 VkPipelineStageFlags src_stage_mask)
2801 {
2802 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2803 VK_PIPELINE_STAGE_TRANSFER_BIT |
2804 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2805 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2806 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2807 }
2808
2809 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2810 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2811 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2812 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2813 VK_PIPELINE_STAGE_TRANSFER_BIT |
2814 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2815 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2816 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2817 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2818 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2819 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2820 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2821 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2822 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2823 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2824 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2825 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2826 }
2827 }
2828
2829 static enum radv_cmd_flush_bits
2830 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2831 VkAccessFlags src_flags,
2832 struct radv_image *image)
2833 {
2834 bool flush_CB_meta = true, flush_DB_meta = true;
2835 enum radv_cmd_flush_bits flush_bits = 0;
2836 uint32_t b;
2837
2838 if (image) {
2839 if (!radv_image_has_CB_metadata(image))
2840 flush_CB_meta = false;
2841 if (!radv_image_has_htile(image))
2842 flush_DB_meta = false;
2843 }
2844
2845 for_each_bit(b, src_flags) {
2846 switch ((VkAccessFlagBits)(1 << b)) {
2847 case VK_ACCESS_SHADER_WRITE_BIT:
2848 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2849 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2850 flush_bits |= RADV_CMD_FLAG_WB_L2;
2851 break;
2852 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2853 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2854 if (flush_CB_meta)
2855 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2856 break;
2857 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2858 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2859 if (flush_DB_meta)
2860 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2861 break;
2862 case VK_ACCESS_TRANSFER_WRITE_BIT:
2863 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2864 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2865 RADV_CMD_FLAG_INV_L2;
2866
2867 if (flush_CB_meta)
2868 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2869 if (flush_DB_meta)
2870 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2871 break;
2872 default:
2873 break;
2874 }
2875 }
2876 return flush_bits;
2877 }
2878
2879 static enum radv_cmd_flush_bits
2880 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2881 VkAccessFlags dst_flags,
2882 struct radv_image *image)
2883 {
2884 bool flush_CB_meta = true, flush_DB_meta = true;
2885 enum radv_cmd_flush_bits flush_bits = 0;
2886 bool flush_CB = true, flush_DB = true;
2887 bool image_is_coherent = false;
2888 uint32_t b;
2889
2890 if (image) {
2891 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2892 flush_CB = false;
2893 flush_DB = false;
2894 }
2895
2896 if (!radv_image_has_CB_metadata(image))
2897 flush_CB_meta = false;
2898 if (!radv_image_has_htile(image))
2899 flush_DB_meta = false;
2900
2901 /* TODO: implement shader coherent for GFX10 */
2902
2903 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2904 if (image->info.samples == 1 &&
2905 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2906 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2907 !vk_format_is_stencil(image->vk_format)) {
2908 /* Single-sample color and single-sample depth
2909 * (not stencil) are coherent with shaders on
2910 * GFX9.
2911 */
2912 image_is_coherent = true;
2913 }
2914 }
2915 }
2916
2917 for_each_bit(b, dst_flags) {
2918 switch ((VkAccessFlagBits)(1 << b)) {
2919 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2920 case VK_ACCESS_INDEX_READ_BIT:
2921 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2922 break;
2923 case VK_ACCESS_UNIFORM_READ_BIT:
2924 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2925 break;
2926 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2927 case VK_ACCESS_TRANSFER_READ_BIT:
2928 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2929 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2930 RADV_CMD_FLAG_INV_L2;
2931 break;
2932 case VK_ACCESS_SHADER_READ_BIT:
2933 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2934 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2935 * invalidate the scalar cache. */
2936 if (cmd_buffer->device->physical_device->use_aco &&
2937 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8)
2938 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
2939
2940 if (!image_is_coherent)
2941 flush_bits |= RADV_CMD_FLAG_INV_L2;
2942 break;
2943 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2944 if (flush_CB)
2945 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2946 if (flush_CB_meta)
2947 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2948 break;
2949 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2950 if (flush_DB)
2951 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2952 if (flush_DB_meta)
2953 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2954 break;
2955 default:
2956 break;
2957 }
2958 }
2959 return flush_bits;
2960 }
2961
2962 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2963 const struct radv_subpass_barrier *barrier)
2964 {
2965 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2966 NULL);
2967 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2968 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2969 NULL);
2970 }
2971
2972 uint32_t
2973 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2974 {
2975 struct radv_cmd_state *state = &cmd_buffer->state;
2976 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2977
2978 /* The id of this subpass shouldn't exceed the number of subpasses in
2979 * this render pass minus 1.
2980 */
2981 assert(subpass_id < state->pass->subpass_count);
2982 return subpass_id;
2983 }
2984
2985 static struct radv_sample_locations_state *
2986 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2987 uint32_t att_idx,
2988 bool begin_subpass)
2989 {
2990 struct radv_cmd_state *state = &cmd_buffer->state;
2991 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2992 struct radv_image_view *view = state->attachments[att_idx].iview;
2993
2994 if (view->image->info.samples == 1)
2995 return NULL;
2996
2997 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2998 /* Return the initial sample locations if this is the initial
2999 * layout transition of the given subpass attachemnt.
3000 */
3001 if (state->attachments[att_idx].sample_location.count > 0)
3002 return &state->attachments[att_idx].sample_location;
3003 } else {
3004 /* Otherwise return the subpass sample locations if defined. */
3005 if (state->subpass_sample_locs) {
3006 /* Because the driver sets the current subpass before
3007 * initial layout transitions, we should use the sample
3008 * locations from the previous subpass to avoid an
3009 * off-by-one problem. Otherwise, use the sample
3010 * locations for the current subpass for final layout
3011 * transitions.
3012 */
3013 if (begin_subpass)
3014 subpass_id--;
3015
3016 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
3017 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
3018 return &state->subpass_sample_locs[i].sample_location;
3019 }
3020 }
3021 }
3022
3023 return NULL;
3024 }
3025
3026 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
3027 struct radv_subpass_attachment att,
3028 bool begin_subpass)
3029 {
3030 unsigned idx = att.attachment;
3031 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
3032 struct radv_sample_locations_state *sample_locs;
3033 VkImageSubresourceRange range;
3034 range.aspectMask = view->aspect_mask;
3035 range.baseMipLevel = view->base_mip;
3036 range.levelCount = 1;
3037 range.baseArrayLayer = view->base_layer;
3038 range.layerCount = cmd_buffer->state.framebuffer->layers;
3039
3040 if (cmd_buffer->state.subpass->view_mask) {
3041 /* If the current subpass uses multiview, the driver might have
3042 * performed a fast color/depth clear to the whole image
3043 * (including all layers). To make sure the driver will
3044 * decompress the image correctly (if needed), we have to
3045 * account for the "real" number of layers. If the view mask is
3046 * sparse, this will decompress more layers than needed.
3047 */
3048 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3049 }
3050
3051 /* Get the subpass sample locations for the given attachment, if NULL
3052 * is returned the driver will use the default HW locations.
3053 */
3054 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3055 begin_subpass);
3056
3057 /* Determine if the subpass uses separate depth/stencil layouts. */
3058 bool uses_separate_depth_stencil_layouts = false;
3059 if ((cmd_buffer->state.attachments[idx].current_layout !=
3060 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3061 (att.layout != att.stencil_layout)) {
3062 uses_separate_depth_stencil_layouts = true;
3063 }
3064
3065 /* For separate layouts, perform depth and stencil transitions
3066 * separately.
3067 */
3068 if (uses_separate_depth_stencil_layouts &&
3069 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3070 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3071 /* Depth-only transitions. */
3072 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3073 radv_handle_image_transition(cmd_buffer,
3074 view->image,
3075 cmd_buffer->state.attachments[idx].current_layout,
3076 cmd_buffer->state.attachments[idx].current_in_render_loop,
3077 att.layout, att.in_render_loop,
3078 0, 0, &range, sample_locs);
3079
3080 /* Stencil-only transitions. */
3081 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3082 radv_handle_image_transition(cmd_buffer,
3083 view->image,
3084 cmd_buffer->state.attachments[idx].current_stencil_layout,
3085 cmd_buffer->state.attachments[idx].current_in_render_loop,
3086 att.stencil_layout, att.in_render_loop,
3087 0, 0, &range, sample_locs);
3088 } else {
3089 radv_handle_image_transition(cmd_buffer,
3090 view->image,
3091 cmd_buffer->state.attachments[idx].current_layout,
3092 cmd_buffer->state.attachments[idx].current_in_render_loop,
3093 att.layout, att.in_render_loop,
3094 0, 0, &range, sample_locs);
3095 }
3096
3097 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3098 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3099 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3100
3101
3102 }
3103
3104 void
3105 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3106 const struct radv_subpass *subpass)
3107 {
3108 cmd_buffer->state.subpass = subpass;
3109
3110 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3111 }
3112
3113 static VkResult
3114 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3115 struct radv_render_pass *pass,
3116 const VkRenderPassBeginInfo *info)
3117 {
3118 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3119 vk_find_struct_const(info->pNext,
3120 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3121 struct radv_cmd_state *state = &cmd_buffer->state;
3122
3123 if (!sample_locs) {
3124 state->subpass_sample_locs = NULL;
3125 return VK_SUCCESS;
3126 }
3127
3128 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3129 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3130 &sample_locs->pAttachmentInitialSampleLocations[i];
3131 uint32_t att_idx = att_sample_locs->attachmentIndex;
3132 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3133
3134 assert(vk_format_is_depth_or_stencil(image->vk_format));
3135
3136 /* From the Vulkan spec 1.1.108:
3137 *
3138 * "If the image referenced by the framebuffer attachment at
3139 * index attachmentIndex was not created with
3140 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3141 * then the values specified in sampleLocationsInfo are
3142 * ignored."
3143 */
3144 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3145 continue;
3146
3147 const VkSampleLocationsInfoEXT *sample_locs_info =
3148 &att_sample_locs->sampleLocationsInfo;
3149
3150 state->attachments[att_idx].sample_location.per_pixel =
3151 sample_locs_info->sampleLocationsPerPixel;
3152 state->attachments[att_idx].sample_location.grid_size =
3153 sample_locs_info->sampleLocationGridSize;
3154 state->attachments[att_idx].sample_location.count =
3155 sample_locs_info->sampleLocationsCount;
3156 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3157 sample_locs_info->pSampleLocations,
3158 sample_locs_info->sampleLocationsCount);
3159 }
3160
3161 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3162 sample_locs->postSubpassSampleLocationsCount *
3163 sizeof(state->subpass_sample_locs[0]),
3164 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3165 if (state->subpass_sample_locs == NULL) {
3166 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3167 return cmd_buffer->record_result;
3168 }
3169
3170 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3171
3172 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3173 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3174 &sample_locs->pPostSubpassSampleLocations[i];
3175 const VkSampleLocationsInfoEXT *sample_locs_info =
3176 &subpass_sample_locs_info->sampleLocationsInfo;
3177
3178 state->subpass_sample_locs[i].subpass_idx =
3179 subpass_sample_locs_info->subpassIndex;
3180 state->subpass_sample_locs[i].sample_location.per_pixel =
3181 sample_locs_info->sampleLocationsPerPixel;
3182 state->subpass_sample_locs[i].sample_location.grid_size =
3183 sample_locs_info->sampleLocationGridSize;
3184 state->subpass_sample_locs[i].sample_location.count =
3185 sample_locs_info->sampleLocationsCount;
3186 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3187 sample_locs_info->pSampleLocations,
3188 sample_locs_info->sampleLocationsCount);
3189 }
3190
3191 return VK_SUCCESS;
3192 }
3193
3194 static VkResult
3195 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3196 struct radv_render_pass *pass,
3197 const VkRenderPassBeginInfo *info)
3198 {
3199 struct radv_cmd_state *state = &cmd_buffer->state;
3200 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3201
3202 if (info) {
3203 attachment_info = vk_find_struct_const(info->pNext,
3204 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3205 }
3206
3207
3208 if (pass->attachment_count == 0) {
3209 state->attachments = NULL;
3210 return VK_SUCCESS;
3211 }
3212
3213 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3214 pass->attachment_count *
3215 sizeof(state->attachments[0]),
3216 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3217 if (state->attachments == NULL) {
3218 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3219 return cmd_buffer->record_result;
3220 }
3221
3222 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3223 struct radv_render_pass_attachment *att = &pass->attachments[i];
3224 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3225 VkImageAspectFlags clear_aspects = 0;
3226
3227 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3228 /* color attachment */
3229 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3230 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3231 }
3232 } else {
3233 /* depthstencil attachment */
3234 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3235 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3236 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3237 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3238 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3239 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3240 }
3241 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3242 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3243 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3244 }
3245 }
3246
3247 state->attachments[i].pending_clear_aspects = clear_aspects;
3248 state->attachments[i].cleared_views = 0;
3249 if (clear_aspects && info) {
3250 assert(info->clearValueCount > i);
3251 state->attachments[i].clear_value = info->pClearValues[i];
3252 }
3253
3254 state->attachments[i].current_layout = att->initial_layout;
3255 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3256 state->attachments[i].sample_location.count = 0;
3257
3258 struct radv_image_view *iview;
3259 if (attachment_info && attachment_info->attachmentCount > i) {
3260 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3261 } else {
3262 iview = state->framebuffer->attachments[i];
3263 }
3264
3265 state->attachments[i].iview = iview;
3266 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3267 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3268 } else {
3269 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3270 }
3271 }
3272
3273 return VK_SUCCESS;
3274 }
3275
3276 VkResult radv_AllocateCommandBuffers(
3277 VkDevice _device,
3278 const VkCommandBufferAllocateInfo *pAllocateInfo,
3279 VkCommandBuffer *pCommandBuffers)
3280 {
3281 RADV_FROM_HANDLE(radv_device, device, _device);
3282 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3283
3284 VkResult result = VK_SUCCESS;
3285 uint32_t i;
3286
3287 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3288
3289 if (!list_is_empty(&pool->free_cmd_buffers)) {
3290 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3291
3292 list_del(&cmd_buffer->pool_link);
3293 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3294
3295 result = radv_reset_cmd_buffer(cmd_buffer);
3296 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3297 cmd_buffer->level = pAllocateInfo->level;
3298
3299 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3300 } else {
3301 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3302 &pCommandBuffers[i]);
3303 }
3304 if (result != VK_SUCCESS)
3305 break;
3306 }
3307
3308 if (result != VK_SUCCESS) {
3309 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3310 i, pCommandBuffers);
3311
3312 /* From the Vulkan 1.0.66 spec:
3313 *
3314 * "vkAllocateCommandBuffers can be used to create multiple
3315 * command buffers. If the creation of any of those command
3316 * buffers fails, the implementation must destroy all
3317 * successfully created command buffer objects from this
3318 * command, set all entries of the pCommandBuffers array to
3319 * NULL and return the error."
3320 */
3321 memset(pCommandBuffers, 0,
3322 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3323 }
3324
3325 return result;
3326 }
3327
3328 void radv_FreeCommandBuffers(
3329 VkDevice device,
3330 VkCommandPool commandPool,
3331 uint32_t commandBufferCount,
3332 const VkCommandBuffer *pCommandBuffers)
3333 {
3334 for (uint32_t i = 0; i < commandBufferCount; i++) {
3335 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3336
3337 if (cmd_buffer) {
3338 if (cmd_buffer->pool) {
3339 list_del(&cmd_buffer->pool_link);
3340 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3341 } else
3342 radv_cmd_buffer_destroy(cmd_buffer);
3343
3344 }
3345 }
3346 }
3347
3348 VkResult radv_ResetCommandBuffer(
3349 VkCommandBuffer commandBuffer,
3350 VkCommandBufferResetFlags flags)
3351 {
3352 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3353 return radv_reset_cmd_buffer(cmd_buffer);
3354 }
3355
3356 VkResult radv_BeginCommandBuffer(
3357 VkCommandBuffer commandBuffer,
3358 const VkCommandBufferBeginInfo *pBeginInfo)
3359 {
3360 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3361 VkResult result = VK_SUCCESS;
3362
3363 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3364 /* If the command buffer has already been resetted with
3365 * vkResetCommandBuffer, no need to do it again.
3366 */
3367 result = radv_reset_cmd_buffer(cmd_buffer);
3368 if (result != VK_SUCCESS)
3369 return result;
3370 }
3371
3372 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3373 cmd_buffer->state.last_primitive_reset_en = -1;
3374 cmd_buffer->state.last_index_type = -1;
3375 cmd_buffer->state.last_num_instances = -1;
3376 cmd_buffer->state.last_vertex_offset = -1;
3377 cmd_buffer->state.last_first_instance = -1;
3378 cmd_buffer->state.predication_type = -1;
3379 cmd_buffer->state.last_sx_ps_downconvert = -1;
3380 cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
3381 cmd_buffer->state.last_sx_blend_opt_control = -1;
3382 cmd_buffer->usage_flags = pBeginInfo->flags;
3383
3384 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3385 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3386 assert(pBeginInfo->pInheritanceInfo);
3387 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3388 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3389
3390 struct radv_subpass *subpass =
3391 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3392
3393 if (cmd_buffer->state.framebuffer) {
3394 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3395 if (result != VK_SUCCESS)
3396 return result;
3397 }
3398
3399 cmd_buffer->state.inherited_pipeline_statistics =
3400 pBeginInfo->pInheritanceInfo->pipelineStatistics;
3401
3402 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3403 }
3404
3405 if (unlikely(cmd_buffer->device->trace_bo)) {
3406 struct radv_device *device = cmd_buffer->device;
3407
3408 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3409 device->trace_bo);
3410
3411 radv_cmd_buffer_trace_emit(cmd_buffer);
3412 }
3413
3414 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3415
3416 return result;
3417 }
3418
3419 void radv_CmdBindVertexBuffers(
3420 VkCommandBuffer commandBuffer,
3421 uint32_t firstBinding,
3422 uint32_t bindingCount,
3423 const VkBuffer* pBuffers,
3424 const VkDeviceSize* pOffsets)
3425 {
3426 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3427 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3428 bool changed = false;
3429
3430 /* We have to defer setting up vertex buffer since we need the buffer
3431 * stride from the pipeline. */
3432
3433 assert(firstBinding + bindingCount <= MAX_VBS);
3434 for (uint32_t i = 0; i < bindingCount; i++) {
3435 uint32_t idx = firstBinding + i;
3436
3437 if (!changed &&
3438 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3439 vb[idx].offset != pOffsets[i])) {
3440 changed = true;
3441 }
3442
3443 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3444 vb[idx].offset = pOffsets[i];
3445
3446 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3447 vb[idx].buffer->bo);
3448 }
3449
3450 if (!changed) {
3451 /* No state changes. */
3452 return;
3453 }
3454
3455 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3456 }
3457
3458 static uint32_t
3459 vk_to_index_type(VkIndexType type)
3460 {
3461 switch (type) {
3462 case VK_INDEX_TYPE_UINT8_EXT:
3463 return V_028A7C_VGT_INDEX_8;
3464 case VK_INDEX_TYPE_UINT16:
3465 return V_028A7C_VGT_INDEX_16;
3466 case VK_INDEX_TYPE_UINT32:
3467 return V_028A7C_VGT_INDEX_32;
3468 default:
3469 unreachable("invalid index type");
3470 }
3471 }
3472
3473 static uint32_t
3474 radv_get_vgt_index_size(uint32_t type)
3475 {
3476 switch (type) {
3477 case V_028A7C_VGT_INDEX_8:
3478 return 1;
3479 case V_028A7C_VGT_INDEX_16:
3480 return 2;
3481 case V_028A7C_VGT_INDEX_32:
3482 return 4;
3483 default:
3484 unreachable("invalid index type");
3485 }
3486 }
3487
3488 void radv_CmdBindIndexBuffer(
3489 VkCommandBuffer commandBuffer,
3490 VkBuffer buffer,
3491 VkDeviceSize offset,
3492 VkIndexType indexType)
3493 {
3494 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3495 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3496
3497 if (cmd_buffer->state.index_buffer == index_buffer &&
3498 cmd_buffer->state.index_offset == offset &&
3499 cmd_buffer->state.index_type == indexType) {
3500 /* No state changes. */
3501 return;
3502 }
3503
3504 cmd_buffer->state.index_buffer = index_buffer;
3505 cmd_buffer->state.index_offset = offset;
3506 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3507 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3508 cmd_buffer->state.index_va += index_buffer->offset + offset;
3509
3510 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3511 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3512 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3513 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3514 }
3515
3516
3517 static void
3518 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3519 VkPipelineBindPoint bind_point,
3520 struct radv_descriptor_set *set, unsigned idx)
3521 {
3522 struct radeon_winsys *ws = cmd_buffer->device->ws;
3523
3524 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3525
3526 assert(set);
3527 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3528
3529 if (!cmd_buffer->device->use_global_bo_list) {
3530 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3531 if (set->descriptors[j])
3532 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3533 }
3534
3535 if(set->bo)
3536 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3537 }
3538
3539 void radv_CmdBindDescriptorSets(
3540 VkCommandBuffer commandBuffer,
3541 VkPipelineBindPoint pipelineBindPoint,
3542 VkPipelineLayout _layout,
3543 uint32_t firstSet,
3544 uint32_t descriptorSetCount,
3545 const VkDescriptorSet* pDescriptorSets,
3546 uint32_t dynamicOffsetCount,
3547 const uint32_t* pDynamicOffsets)
3548 {
3549 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3550 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3551 unsigned dyn_idx = 0;
3552
3553 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3554 struct radv_descriptor_state *descriptors_state =
3555 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3556
3557 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3558 unsigned idx = i + firstSet;
3559 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3560
3561 /* If the set is already bound we only need to update the
3562 * (potentially changed) dynamic offsets. */
3563 if (descriptors_state->sets[idx] != set ||
3564 !(descriptors_state->valid & (1u << idx))) {
3565 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3566 }
3567
3568 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3569 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3570 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3571 assert(dyn_idx < dynamicOffsetCount);
3572
3573 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3574 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3575 dst[0] = va;
3576 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3577 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3578 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3579 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3580 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3581 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3582
3583 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3584 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3585 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3586 S_008F0C_RESOURCE_LEVEL(1);
3587 } else {
3588 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3589 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3590 }
3591
3592 cmd_buffer->push_constant_stages |=
3593 set->layout->dynamic_shader_stages;
3594 }
3595 }
3596 }
3597
3598 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3599 struct radv_descriptor_set *set,
3600 struct radv_descriptor_set_layout *layout,
3601 VkPipelineBindPoint bind_point)
3602 {
3603 struct radv_descriptor_state *descriptors_state =
3604 radv_get_descriptors_state(cmd_buffer, bind_point);
3605 set->size = layout->size;
3606 set->layout = layout;
3607
3608 if (descriptors_state->push_set.capacity < set->size) {
3609 size_t new_size = MAX2(set->size, 1024);
3610 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3611 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3612
3613 free(set->mapped_ptr);
3614 set->mapped_ptr = malloc(new_size);
3615
3616 if (!set->mapped_ptr) {
3617 descriptors_state->push_set.capacity = 0;
3618 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3619 return false;
3620 }
3621
3622 descriptors_state->push_set.capacity = new_size;
3623 }
3624
3625 return true;
3626 }
3627
3628 void radv_meta_push_descriptor_set(
3629 struct radv_cmd_buffer* cmd_buffer,
3630 VkPipelineBindPoint pipelineBindPoint,
3631 VkPipelineLayout _layout,
3632 uint32_t set,
3633 uint32_t descriptorWriteCount,
3634 const VkWriteDescriptorSet* pDescriptorWrites)
3635 {
3636 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3637 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3638 unsigned bo_offset;
3639
3640 assert(set == 0);
3641 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3642
3643 push_set->size = layout->set[set].layout->size;
3644 push_set->layout = layout->set[set].layout;
3645
3646 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3647 &bo_offset,
3648 (void**) &push_set->mapped_ptr))
3649 return;
3650
3651 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3652 push_set->va += bo_offset;
3653
3654 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3655 radv_descriptor_set_to_handle(push_set),
3656 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3657
3658 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3659 }
3660
3661 void radv_CmdPushDescriptorSetKHR(
3662 VkCommandBuffer commandBuffer,
3663 VkPipelineBindPoint pipelineBindPoint,
3664 VkPipelineLayout _layout,
3665 uint32_t set,
3666 uint32_t descriptorWriteCount,
3667 const VkWriteDescriptorSet* pDescriptorWrites)
3668 {
3669 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3670 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3671 struct radv_descriptor_state *descriptors_state =
3672 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3673 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3674
3675 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3676
3677 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3678 layout->set[set].layout,
3679 pipelineBindPoint))
3680 return;
3681
3682 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3683 * because it is invalid, according to Vulkan spec.
3684 */
3685 for (int i = 0; i < descriptorWriteCount; i++) {
3686 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3687 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3688 }
3689
3690 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3691 radv_descriptor_set_to_handle(push_set),
3692 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3693
3694 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3695 descriptors_state->push_dirty = true;
3696 }
3697
3698 void radv_CmdPushDescriptorSetWithTemplateKHR(
3699 VkCommandBuffer commandBuffer,
3700 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3701 VkPipelineLayout _layout,
3702 uint32_t set,
3703 const void* pData)
3704 {
3705 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3706 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3707 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3708 struct radv_descriptor_state *descriptors_state =
3709 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3710 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3711
3712 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3713
3714 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3715 layout->set[set].layout,
3716 templ->bind_point))
3717 return;
3718
3719 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3720 descriptorUpdateTemplate, pData);
3721
3722 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3723 descriptors_state->push_dirty = true;
3724 }
3725
3726 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3727 VkPipelineLayout layout,
3728 VkShaderStageFlags stageFlags,
3729 uint32_t offset,
3730 uint32_t size,
3731 const void* pValues)
3732 {
3733 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3734 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3735 cmd_buffer->push_constant_stages |= stageFlags;
3736 }
3737
3738 VkResult radv_EndCommandBuffer(
3739 VkCommandBuffer commandBuffer)
3740 {
3741 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3742
3743 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3744 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3745 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3746
3747 /* Make sure to sync all pending active queries at the end of
3748 * command buffer.
3749 */
3750 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3751
3752 /* Since NGG streamout uses GDS, we need to make GDS idle when
3753 * we leave the IB, otherwise another process might overwrite
3754 * it while our shaders are busy.
3755 */
3756 if (cmd_buffer->gds_needed)
3757 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3758
3759 si_emit_cache_flush(cmd_buffer);
3760 }
3761
3762 /* Make sure CP DMA is idle at the end of IBs because the kernel
3763 * doesn't wait for it.
3764 */
3765 si_cp_dma_wait_for_idle(cmd_buffer);
3766
3767 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3768 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3769
3770 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3771 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3772
3773 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3774
3775 return cmd_buffer->record_result;
3776 }
3777
3778 static void
3779 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3780 {
3781 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3782
3783 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3784 return;
3785
3786 assert(!pipeline->ctx_cs.cdw);
3787
3788 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3789
3790 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3791 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3792
3793 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
3794 pipeline->scratch_bytes_per_wave);
3795 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
3796 pipeline->max_waves);
3797
3798 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3799 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3800
3801 if (unlikely(cmd_buffer->device->trace_bo))
3802 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3803 }
3804
3805 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3806 VkPipelineBindPoint bind_point)
3807 {
3808 struct radv_descriptor_state *descriptors_state =
3809 radv_get_descriptors_state(cmd_buffer, bind_point);
3810
3811 descriptors_state->dirty |= descriptors_state->valid;
3812 }
3813
3814 void radv_CmdBindPipeline(
3815 VkCommandBuffer commandBuffer,
3816 VkPipelineBindPoint pipelineBindPoint,
3817 VkPipeline _pipeline)
3818 {
3819 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3820 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3821
3822 switch (pipelineBindPoint) {
3823 case VK_PIPELINE_BIND_POINT_COMPUTE:
3824 if (cmd_buffer->state.compute_pipeline == pipeline)
3825 return;
3826 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3827
3828 cmd_buffer->state.compute_pipeline = pipeline;
3829 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3830 break;
3831 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3832 if (cmd_buffer->state.pipeline == pipeline)
3833 return;
3834 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3835
3836 cmd_buffer->state.pipeline = pipeline;
3837 if (!pipeline)
3838 break;
3839
3840 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3841 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3842
3843 /* the new vertex shader might not have the same user regs */
3844 cmd_buffer->state.last_first_instance = -1;
3845 cmd_buffer->state.last_vertex_offset = -1;
3846
3847 /* Prefetch all pipeline shaders at first draw time. */
3848 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3849
3850 if ((cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3851 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3852 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3853 cmd_buffer->state.emitted_pipeline &&
3854 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3855 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3856 /* Transitioning from NGG to legacy GS requires
3857 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3858 * at the beginning of IBs when legacy GS ring pointers
3859 * are set.
3860 */
3861 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3862 }
3863
3864 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3865 radv_bind_streamout_state(cmd_buffer, pipeline);
3866
3867 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3868 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3869 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3870 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3871
3872 if (radv_pipeline_has_tess(pipeline))
3873 cmd_buffer->tess_rings_needed = true;
3874 break;
3875 default:
3876 assert(!"invalid bind point");
3877 break;
3878 }
3879 }
3880
3881 void radv_CmdSetViewport(
3882 VkCommandBuffer commandBuffer,
3883 uint32_t firstViewport,
3884 uint32_t viewportCount,
3885 const VkViewport* pViewports)
3886 {
3887 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3888 struct radv_cmd_state *state = &cmd_buffer->state;
3889 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
3890
3891 assert(firstViewport < MAX_VIEWPORTS);
3892 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3893
3894 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3895 pViewports, viewportCount * sizeof(*pViewports))) {
3896 return;
3897 }
3898
3899 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3900 viewportCount * sizeof(*pViewports));
3901
3902 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3903 }
3904
3905 void radv_CmdSetScissor(
3906 VkCommandBuffer commandBuffer,
3907 uint32_t firstScissor,
3908 uint32_t scissorCount,
3909 const VkRect2D* pScissors)
3910 {
3911 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3912 struct radv_cmd_state *state = &cmd_buffer->state;
3913 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
3914
3915 assert(firstScissor < MAX_SCISSORS);
3916 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3917
3918 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3919 scissorCount * sizeof(*pScissors))) {
3920 return;
3921 }
3922
3923 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3924 scissorCount * sizeof(*pScissors));
3925
3926 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3927 }
3928
3929 void radv_CmdSetLineWidth(
3930 VkCommandBuffer commandBuffer,
3931 float lineWidth)
3932 {
3933 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3934
3935 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3936 return;
3937
3938 cmd_buffer->state.dynamic.line_width = lineWidth;
3939 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3940 }
3941
3942 void radv_CmdSetDepthBias(
3943 VkCommandBuffer commandBuffer,
3944 float depthBiasConstantFactor,
3945 float depthBiasClamp,
3946 float depthBiasSlopeFactor)
3947 {
3948 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3949 struct radv_cmd_state *state = &cmd_buffer->state;
3950
3951 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3952 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3953 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3954 return;
3955 }
3956
3957 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3958 state->dynamic.depth_bias.clamp = depthBiasClamp;
3959 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3960
3961 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3962 }
3963
3964 void radv_CmdSetBlendConstants(
3965 VkCommandBuffer commandBuffer,
3966 const float blendConstants[4])
3967 {
3968 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3969 struct radv_cmd_state *state = &cmd_buffer->state;
3970
3971 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3972 return;
3973
3974 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3975
3976 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3977 }
3978
3979 void radv_CmdSetDepthBounds(
3980 VkCommandBuffer commandBuffer,
3981 float minDepthBounds,
3982 float maxDepthBounds)
3983 {
3984 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3985 struct radv_cmd_state *state = &cmd_buffer->state;
3986
3987 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3988 state->dynamic.depth_bounds.max == maxDepthBounds) {
3989 return;
3990 }
3991
3992 state->dynamic.depth_bounds.min = minDepthBounds;
3993 state->dynamic.depth_bounds.max = maxDepthBounds;
3994
3995 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3996 }
3997
3998 void radv_CmdSetStencilCompareMask(
3999 VkCommandBuffer commandBuffer,
4000 VkStencilFaceFlags faceMask,
4001 uint32_t compareMask)
4002 {
4003 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4004 struct radv_cmd_state *state = &cmd_buffer->state;
4005 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
4006 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
4007
4008 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4009 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4010 return;
4011 }
4012
4013 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4014 state->dynamic.stencil_compare_mask.front = compareMask;
4015 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4016 state->dynamic.stencil_compare_mask.back = compareMask;
4017
4018 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
4019 }
4020
4021 void radv_CmdSetStencilWriteMask(
4022 VkCommandBuffer commandBuffer,
4023 VkStencilFaceFlags faceMask,
4024 uint32_t writeMask)
4025 {
4026 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4027 struct radv_cmd_state *state = &cmd_buffer->state;
4028 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
4029 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
4030
4031 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4032 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4033 return;
4034 }
4035
4036 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4037 state->dynamic.stencil_write_mask.front = writeMask;
4038 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4039 state->dynamic.stencil_write_mask.back = writeMask;
4040
4041 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
4042 }
4043
4044 void radv_CmdSetStencilReference(
4045 VkCommandBuffer commandBuffer,
4046 VkStencilFaceFlags faceMask,
4047 uint32_t reference)
4048 {
4049 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4050 struct radv_cmd_state *state = &cmd_buffer->state;
4051 bool front_same = state->dynamic.stencil_reference.front == reference;
4052 bool back_same = state->dynamic.stencil_reference.back == reference;
4053
4054 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4055 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4056 return;
4057 }
4058
4059 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4060 cmd_buffer->state.dynamic.stencil_reference.front = reference;
4061 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4062 cmd_buffer->state.dynamic.stencil_reference.back = reference;
4063
4064 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
4065 }
4066
4067 void radv_CmdSetDiscardRectangleEXT(
4068 VkCommandBuffer commandBuffer,
4069 uint32_t firstDiscardRectangle,
4070 uint32_t discardRectangleCount,
4071 const VkRect2D* pDiscardRectangles)
4072 {
4073 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4074 struct radv_cmd_state *state = &cmd_buffer->state;
4075 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
4076
4077 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
4078 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
4079
4080 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
4081 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
4082 return;
4083 }
4084
4085 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
4086 pDiscardRectangles, discardRectangleCount);
4087
4088 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
4089 }
4090
4091 void radv_CmdSetSampleLocationsEXT(
4092 VkCommandBuffer commandBuffer,
4093 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
4094 {
4095 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4096 struct radv_cmd_state *state = &cmd_buffer->state;
4097
4098 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
4099
4100 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
4101 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
4102 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
4103 typed_memcpy(&state->dynamic.sample_location.locations[0],
4104 pSampleLocationsInfo->pSampleLocations,
4105 pSampleLocationsInfo->sampleLocationsCount);
4106
4107 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
4108 }
4109
4110 void radv_CmdExecuteCommands(
4111 VkCommandBuffer commandBuffer,
4112 uint32_t commandBufferCount,
4113 const VkCommandBuffer* pCmdBuffers)
4114 {
4115 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4116
4117 assert(commandBufferCount > 0);
4118
4119 /* Emit pending flushes on primary prior to executing secondary */
4120 si_emit_cache_flush(primary);
4121
4122 for (uint32_t i = 0; i < commandBufferCount; i++) {
4123 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4124
4125 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4126 secondary->scratch_size_per_wave_needed);
4127 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4128 secondary->scratch_waves_wanted);
4129 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4130 secondary->compute_scratch_size_per_wave_needed);
4131 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4132 secondary->compute_scratch_waves_wanted);
4133
4134 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4135 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4136 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4137 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4138 if (secondary->tess_rings_needed)
4139 primary->tess_rings_needed = true;
4140 if (secondary->sample_positions_needed)
4141 primary->sample_positions_needed = true;
4142 if (secondary->gds_needed)
4143 primary->gds_needed = true;
4144
4145 if (!secondary->state.framebuffer &&
4146 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4147 /* Emit the framebuffer state from primary if secondary
4148 * has been recorded without a framebuffer, otherwise
4149 * fast color/depth clears can't work.
4150 */
4151 radv_emit_framebuffer_state(primary);
4152 }
4153
4154 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4155
4156
4157 /* When the secondary command buffer is compute only we don't
4158 * need to re-emit the current graphics pipeline.
4159 */
4160 if (secondary->state.emitted_pipeline) {
4161 primary->state.emitted_pipeline =
4162 secondary->state.emitted_pipeline;
4163 }
4164
4165 /* When the secondary command buffer is graphics only we don't
4166 * need to re-emit the current compute pipeline.
4167 */
4168 if (secondary->state.emitted_compute_pipeline) {
4169 primary->state.emitted_compute_pipeline =
4170 secondary->state.emitted_compute_pipeline;
4171 }
4172
4173 /* Only re-emit the draw packets when needed. */
4174 if (secondary->state.last_primitive_reset_en != -1) {
4175 primary->state.last_primitive_reset_en =
4176 secondary->state.last_primitive_reset_en;
4177 }
4178
4179 if (secondary->state.last_primitive_reset_index) {
4180 primary->state.last_primitive_reset_index =
4181 secondary->state.last_primitive_reset_index;
4182 }
4183
4184 if (secondary->state.last_ia_multi_vgt_param) {
4185 primary->state.last_ia_multi_vgt_param =
4186 secondary->state.last_ia_multi_vgt_param;
4187 }
4188
4189 primary->state.last_first_instance = secondary->state.last_first_instance;
4190 primary->state.last_num_instances = secondary->state.last_num_instances;
4191 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4192 primary->state.last_sx_ps_downconvert = secondary->state.last_sx_ps_downconvert;
4193 primary->state.last_sx_blend_opt_epsilon = secondary->state.last_sx_blend_opt_epsilon;
4194 primary->state.last_sx_blend_opt_control = secondary->state.last_sx_blend_opt_control;
4195
4196 if (secondary->state.last_index_type != -1) {
4197 primary->state.last_index_type =
4198 secondary->state.last_index_type;
4199 }
4200 }
4201
4202 /* After executing commands from secondary buffers we have to dirty
4203 * some states.
4204 */
4205 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4206 RADV_CMD_DIRTY_INDEX_BUFFER |
4207 RADV_CMD_DIRTY_DYNAMIC_ALL;
4208 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4209 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4210 }
4211
4212 VkResult radv_CreateCommandPool(
4213 VkDevice _device,
4214 const VkCommandPoolCreateInfo* pCreateInfo,
4215 const VkAllocationCallbacks* pAllocator,
4216 VkCommandPool* pCmdPool)
4217 {
4218 RADV_FROM_HANDLE(radv_device, device, _device);
4219 struct radv_cmd_pool *pool;
4220
4221 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
4222 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4223 if (pool == NULL)
4224 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4225
4226 if (pAllocator)
4227 pool->alloc = *pAllocator;
4228 else
4229 pool->alloc = device->alloc;
4230
4231 list_inithead(&pool->cmd_buffers);
4232 list_inithead(&pool->free_cmd_buffers);
4233
4234 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4235
4236 *pCmdPool = radv_cmd_pool_to_handle(pool);
4237
4238 return VK_SUCCESS;
4239
4240 }
4241
4242 void radv_DestroyCommandPool(
4243 VkDevice _device,
4244 VkCommandPool commandPool,
4245 const VkAllocationCallbacks* pAllocator)
4246 {
4247 RADV_FROM_HANDLE(radv_device, device, _device);
4248 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4249
4250 if (!pool)
4251 return;
4252
4253 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4254 &pool->cmd_buffers, pool_link) {
4255 radv_cmd_buffer_destroy(cmd_buffer);
4256 }
4257
4258 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4259 &pool->free_cmd_buffers, pool_link) {
4260 radv_cmd_buffer_destroy(cmd_buffer);
4261 }
4262
4263 vk_free2(&device->alloc, pAllocator, pool);
4264 }
4265
4266 VkResult radv_ResetCommandPool(
4267 VkDevice device,
4268 VkCommandPool commandPool,
4269 VkCommandPoolResetFlags flags)
4270 {
4271 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4272 VkResult result;
4273
4274 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4275 &pool->cmd_buffers, pool_link) {
4276 result = radv_reset_cmd_buffer(cmd_buffer);
4277 if (result != VK_SUCCESS)
4278 return result;
4279 }
4280
4281 return VK_SUCCESS;
4282 }
4283
4284 void radv_TrimCommandPool(
4285 VkDevice device,
4286 VkCommandPool commandPool,
4287 VkCommandPoolTrimFlags flags)
4288 {
4289 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4290
4291 if (!pool)
4292 return;
4293
4294 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4295 &pool->free_cmd_buffers, pool_link) {
4296 radv_cmd_buffer_destroy(cmd_buffer);
4297 }
4298 }
4299
4300 static void
4301 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4302 uint32_t subpass_id)
4303 {
4304 struct radv_cmd_state *state = &cmd_buffer->state;
4305 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4306
4307 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4308 cmd_buffer->cs, 4096);
4309
4310 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4311
4312 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4313
4314 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4315 const uint32_t a = subpass->attachments[i].attachment;
4316 if (a == VK_ATTACHMENT_UNUSED)
4317 continue;
4318
4319 radv_handle_subpass_image_transition(cmd_buffer,
4320 subpass->attachments[i],
4321 true);
4322 }
4323
4324 radv_cmd_buffer_clear_subpass(cmd_buffer);
4325
4326 assert(cmd_buffer->cs->cdw <= cdw_max);
4327 }
4328
4329 static void
4330 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4331 {
4332 struct radv_cmd_state *state = &cmd_buffer->state;
4333 const struct radv_subpass *subpass = state->subpass;
4334 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4335
4336 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4337
4338 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4339 const uint32_t a = subpass->attachments[i].attachment;
4340 if (a == VK_ATTACHMENT_UNUSED)
4341 continue;
4342
4343 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4344 continue;
4345
4346 VkImageLayout layout = state->pass->attachments[a].final_layout;
4347 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
4348 struct radv_subpass_attachment att = { a, layout, stencil_layout };
4349 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4350 }
4351 }
4352
4353 void radv_CmdBeginRenderPass(
4354 VkCommandBuffer commandBuffer,
4355 const VkRenderPassBeginInfo* pRenderPassBegin,
4356 VkSubpassContents contents)
4357 {
4358 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4359 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4360 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4361 VkResult result;
4362
4363 cmd_buffer->state.framebuffer = framebuffer;
4364 cmd_buffer->state.pass = pass;
4365 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4366
4367 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4368 if (result != VK_SUCCESS)
4369 return;
4370
4371 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4372 if (result != VK_SUCCESS)
4373 return;
4374
4375 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4376 }
4377
4378 void radv_CmdBeginRenderPass2(
4379 VkCommandBuffer commandBuffer,
4380 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4381 const VkSubpassBeginInfo* pSubpassBeginInfo)
4382 {
4383 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4384 pSubpassBeginInfo->contents);
4385 }
4386
4387 void radv_CmdNextSubpass(
4388 VkCommandBuffer commandBuffer,
4389 VkSubpassContents contents)
4390 {
4391 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4392
4393 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4394 radv_cmd_buffer_end_subpass(cmd_buffer);
4395 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4396 }
4397
4398 void radv_CmdNextSubpass2(
4399 VkCommandBuffer commandBuffer,
4400 const VkSubpassBeginInfo* pSubpassBeginInfo,
4401 const VkSubpassEndInfo* pSubpassEndInfo)
4402 {
4403 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4404 }
4405
4406 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4407 {
4408 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4409 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4410 if (!radv_get_shader(pipeline, stage))
4411 continue;
4412
4413 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4414 if (loc->sgpr_idx == -1)
4415 continue;
4416 uint32_t base_reg = pipeline->user_data_0[stage];
4417 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4418
4419 }
4420 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4421 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4422 if (loc->sgpr_idx != -1) {
4423 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4424 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4425 }
4426 }
4427 }
4428
4429 static void
4430 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4431 uint32_t vertex_count,
4432 bool use_opaque)
4433 {
4434 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4435 radeon_emit(cmd_buffer->cs, vertex_count);
4436 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4437 S_0287F0_USE_OPAQUE(use_opaque));
4438 }
4439
4440 static void
4441 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4442 uint64_t index_va,
4443 uint32_t index_count)
4444 {
4445 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4446 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4447 radeon_emit(cmd_buffer->cs, index_va);
4448 radeon_emit(cmd_buffer->cs, index_va >> 32);
4449 radeon_emit(cmd_buffer->cs, index_count);
4450 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4451 }
4452
4453 static void
4454 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4455 bool indexed,
4456 uint32_t draw_count,
4457 uint64_t count_va,
4458 uint32_t stride)
4459 {
4460 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4461 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4462 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4463 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4464 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4465 bool predicating = cmd_buffer->state.predicating;
4466 assert(base_reg);
4467
4468 /* just reset draw state for vertex data */
4469 cmd_buffer->state.last_first_instance = -1;
4470 cmd_buffer->state.last_num_instances = -1;
4471 cmd_buffer->state.last_vertex_offset = -1;
4472
4473 if (draw_count == 1 && !count_va && !draw_id_enable) {
4474 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4475 PKT3_DRAW_INDIRECT, 3, predicating));
4476 radeon_emit(cs, 0);
4477 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4478 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4479 radeon_emit(cs, di_src_sel);
4480 } else {
4481 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4482 PKT3_DRAW_INDIRECT_MULTI,
4483 8, predicating));
4484 radeon_emit(cs, 0);
4485 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4486 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4487 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4488 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4489 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4490 radeon_emit(cs, draw_count); /* count */
4491 radeon_emit(cs, count_va); /* count_addr */
4492 radeon_emit(cs, count_va >> 32);
4493 radeon_emit(cs, stride); /* stride */
4494 radeon_emit(cs, di_src_sel);
4495 }
4496 }
4497
4498 static void
4499 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4500 const struct radv_draw_info *info)
4501 {
4502 struct radv_cmd_state *state = &cmd_buffer->state;
4503 struct radeon_winsys *ws = cmd_buffer->device->ws;
4504 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4505
4506 if (info->indirect) {
4507 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4508 uint64_t count_va = 0;
4509
4510 va += info->indirect->offset + info->indirect_offset;
4511
4512 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4513
4514 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4515 radeon_emit(cs, 1);
4516 radeon_emit(cs, va);
4517 radeon_emit(cs, va >> 32);
4518
4519 if (info->count_buffer) {
4520 count_va = radv_buffer_get_va(info->count_buffer->bo);
4521 count_va += info->count_buffer->offset +
4522 info->count_buffer_offset;
4523
4524 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4525 }
4526
4527 if (!state->subpass->view_mask) {
4528 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4529 info->indexed,
4530 info->count,
4531 count_va,
4532 info->stride);
4533 } else {
4534 unsigned i;
4535 for_each_bit(i, state->subpass->view_mask) {
4536 radv_emit_view_index(cmd_buffer, i);
4537
4538 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4539 info->indexed,
4540 info->count,
4541 count_va,
4542 info->stride);
4543 }
4544 }
4545 } else {
4546 assert(state->pipeline->graphics.vtx_base_sgpr);
4547
4548 if (info->vertex_offset != state->last_vertex_offset ||
4549 info->first_instance != state->last_first_instance) {
4550 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4551 state->pipeline->graphics.vtx_emit_num);
4552
4553 radeon_emit(cs, info->vertex_offset);
4554 radeon_emit(cs, info->first_instance);
4555 if (state->pipeline->graphics.vtx_emit_num == 3)
4556 radeon_emit(cs, 0);
4557 state->last_first_instance = info->first_instance;
4558 state->last_vertex_offset = info->vertex_offset;
4559 }
4560
4561 if (state->last_num_instances != info->instance_count) {
4562 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4563 radeon_emit(cs, info->instance_count);
4564 state->last_num_instances = info->instance_count;
4565 }
4566
4567 if (info->indexed) {
4568 int index_size = radv_get_vgt_index_size(state->index_type);
4569 uint64_t index_va;
4570
4571 /* Skip draw calls with 0-sized index buffers. They
4572 * cause a hang on some chips, like Navi10-14.
4573 */
4574 if (!cmd_buffer->state.max_index_count)
4575 return;
4576
4577 index_va = state->index_va;
4578 index_va += info->first_index * index_size;
4579
4580 if (!state->subpass->view_mask) {
4581 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4582 index_va,
4583 info->count);
4584 } else {
4585 unsigned i;
4586 for_each_bit(i, state->subpass->view_mask) {
4587 radv_emit_view_index(cmd_buffer, i);
4588
4589 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4590 index_va,
4591 info->count);
4592 }
4593 }
4594 } else {
4595 if (!state->subpass->view_mask) {
4596 radv_cs_emit_draw_packet(cmd_buffer,
4597 info->count,
4598 !!info->strmout_buffer);
4599 } else {
4600 unsigned i;
4601 for_each_bit(i, state->subpass->view_mask) {
4602 radv_emit_view_index(cmd_buffer, i);
4603
4604 radv_cs_emit_draw_packet(cmd_buffer,
4605 info->count,
4606 !!info->strmout_buffer);
4607 }
4608 }
4609 }
4610 }
4611 }
4612
4613 /*
4614 * Vega and raven have a bug which triggers if there are multiple context
4615 * register contexts active at the same time with different scissor values.
4616 *
4617 * There are two possible workarounds:
4618 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4619 * there is only ever 1 active set of scissor values at the same time.
4620 *
4621 * 2) Whenever the hardware switches contexts we have to set the scissor
4622 * registers again even if it is a noop. That way the new context gets
4623 * the correct scissor values.
4624 *
4625 * This implements option 2. radv_need_late_scissor_emission needs to
4626 * return true on affected HW if radv_emit_all_graphics_states sets
4627 * any context registers.
4628 */
4629 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4630 const struct radv_draw_info *info)
4631 {
4632 struct radv_cmd_state *state = &cmd_buffer->state;
4633
4634 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
4635 return false;
4636
4637 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4638 return true;
4639
4640 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4641
4642 /* Index, vertex and streamout buffers don't change context regs, and
4643 * pipeline is already handled.
4644 */
4645 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4646 RADV_CMD_DIRTY_VERTEX_BUFFER |
4647 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4648 RADV_CMD_DIRTY_PIPELINE);
4649
4650 if (cmd_buffer->state.dirty & used_states)
4651 return true;
4652
4653 uint32_t primitive_reset_index =
4654 radv_get_primitive_reset_index(cmd_buffer);
4655
4656 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4657 primitive_reset_index != state->last_primitive_reset_index)
4658 return true;
4659
4660 return false;
4661 }
4662
4663 static void
4664 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4665 const struct radv_draw_info *info)
4666 {
4667 bool late_scissor_emission;
4668
4669 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4670 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4671 radv_emit_rbplus_state(cmd_buffer);
4672
4673 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4674 radv_emit_graphics_pipeline(cmd_buffer);
4675
4676 /* This should be before the cmd_buffer->state.dirty is cleared
4677 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4678 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4679 late_scissor_emission =
4680 radv_need_late_scissor_emission(cmd_buffer, info);
4681
4682 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4683 radv_emit_framebuffer_state(cmd_buffer);
4684
4685 if (info->indexed) {
4686 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4687 radv_emit_index_buffer(cmd_buffer, info->indirect);
4688 } else {
4689 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4690 * so the state must be re-emitted before the next indexed
4691 * draw.
4692 */
4693 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4694 cmd_buffer->state.last_index_type = -1;
4695 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4696 }
4697 }
4698
4699 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4700
4701 radv_emit_draw_registers(cmd_buffer, info);
4702
4703 if (late_scissor_emission)
4704 radv_emit_scissor(cmd_buffer);
4705 }
4706
4707 static void
4708 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4709 const struct radv_draw_info *info)
4710 {
4711 struct radeon_info *rad_info =
4712 &cmd_buffer->device->physical_device->rad_info;
4713 bool has_prefetch =
4714 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4715 bool pipeline_is_dirty =
4716 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4717 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4718
4719 ASSERTED unsigned cdw_max =
4720 radeon_check_space(cmd_buffer->device->ws,
4721 cmd_buffer->cs, 4096);
4722
4723 if (likely(!info->indirect)) {
4724 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4725 * no workaround for indirect draws, but we can at least skip
4726 * direct draws.
4727 */
4728 if (unlikely(!info->instance_count))
4729 return;
4730
4731 /* Handle count == 0. */
4732 if (unlikely(!info->count && !info->strmout_buffer))
4733 return;
4734 }
4735
4736 /* Use optimal packet order based on whether we need to sync the
4737 * pipeline.
4738 */
4739 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4740 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4741 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4742 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4743 /* If we have to wait for idle, set all states first, so that
4744 * all SET packets are processed in parallel with previous draw
4745 * calls. Then upload descriptors, set shader pointers, and
4746 * draw, and prefetch at the end. This ensures that the time
4747 * the CUs are idle is very short. (there are only SET_SH
4748 * packets between the wait and the draw)
4749 */
4750 radv_emit_all_graphics_states(cmd_buffer, info);
4751 si_emit_cache_flush(cmd_buffer);
4752 /* <-- CUs are idle here --> */
4753
4754 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4755
4756 radv_emit_draw_packets(cmd_buffer, info);
4757 /* <-- CUs are busy here --> */
4758
4759 /* Start prefetches after the draw has been started. Both will
4760 * run in parallel, but starting the draw first is more
4761 * important.
4762 */
4763 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4764 radv_emit_prefetch_L2(cmd_buffer,
4765 cmd_buffer->state.pipeline, false);
4766 }
4767 } else {
4768 /* If we don't wait for idle, start prefetches first, then set
4769 * states, and draw at the end.
4770 */
4771 si_emit_cache_flush(cmd_buffer);
4772
4773 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4774 /* Only prefetch the vertex shader and VBO descriptors
4775 * in order to start the draw as soon as possible.
4776 */
4777 radv_emit_prefetch_L2(cmd_buffer,
4778 cmd_buffer->state.pipeline, true);
4779 }
4780
4781 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4782
4783 radv_emit_all_graphics_states(cmd_buffer, info);
4784 radv_emit_draw_packets(cmd_buffer, info);
4785
4786 /* Prefetch the remaining shaders after the draw has been
4787 * started.
4788 */
4789 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4790 radv_emit_prefetch_L2(cmd_buffer,
4791 cmd_buffer->state.pipeline, false);
4792 }
4793 }
4794
4795 /* Workaround for a VGT hang when streamout is enabled.
4796 * It must be done after drawing.
4797 */
4798 if (cmd_buffer->state.streamout.streamout_enabled &&
4799 (rad_info->family == CHIP_HAWAII ||
4800 rad_info->family == CHIP_TONGA ||
4801 rad_info->family == CHIP_FIJI)) {
4802 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4803 }
4804
4805 assert(cmd_buffer->cs->cdw <= cdw_max);
4806 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4807 }
4808
4809 void radv_CmdDraw(
4810 VkCommandBuffer commandBuffer,
4811 uint32_t vertexCount,
4812 uint32_t instanceCount,
4813 uint32_t firstVertex,
4814 uint32_t firstInstance)
4815 {
4816 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4817 struct radv_draw_info info = {};
4818
4819 info.count = vertexCount;
4820 info.instance_count = instanceCount;
4821 info.first_instance = firstInstance;
4822 info.vertex_offset = firstVertex;
4823
4824 radv_draw(cmd_buffer, &info);
4825 }
4826
4827 void radv_CmdDrawIndexed(
4828 VkCommandBuffer commandBuffer,
4829 uint32_t indexCount,
4830 uint32_t instanceCount,
4831 uint32_t firstIndex,
4832 int32_t vertexOffset,
4833 uint32_t firstInstance)
4834 {
4835 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4836 struct radv_draw_info info = {};
4837
4838 info.indexed = true;
4839 info.count = indexCount;
4840 info.instance_count = instanceCount;
4841 info.first_index = firstIndex;
4842 info.vertex_offset = vertexOffset;
4843 info.first_instance = firstInstance;
4844
4845 radv_draw(cmd_buffer, &info);
4846 }
4847
4848 void radv_CmdDrawIndirect(
4849 VkCommandBuffer commandBuffer,
4850 VkBuffer _buffer,
4851 VkDeviceSize offset,
4852 uint32_t drawCount,
4853 uint32_t stride)
4854 {
4855 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4856 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4857 struct radv_draw_info info = {};
4858
4859 info.count = drawCount;
4860 info.indirect = buffer;
4861 info.indirect_offset = offset;
4862 info.stride = stride;
4863
4864 radv_draw(cmd_buffer, &info);
4865 }
4866
4867 void radv_CmdDrawIndexedIndirect(
4868 VkCommandBuffer commandBuffer,
4869 VkBuffer _buffer,
4870 VkDeviceSize offset,
4871 uint32_t drawCount,
4872 uint32_t stride)
4873 {
4874 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4875 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4876 struct radv_draw_info info = {};
4877
4878 info.indexed = true;
4879 info.count = drawCount;
4880 info.indirect = buffer;
4881 info.indirect_offset = offset;
4882 info.stride = stride;
4883
4884 radv_draw(cmd_buffer, &info);
4885 }
4886
4887 void radv_CmdDrawIndirectCount(
4888 VkCommandBuffer commandBuffer,
4889 VkBuffer _buffer,
4890 VkDeviceSize offset,
4891 VkBuffer _countBuffer,
4892 VkDeviceSize countBufferOffset,
4893 uint32_t maxDrawCount,
4894 uint32_t stride)
4895 {
4896 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4897 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4898 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4899 struct radv_draw_info info = {};
4900
4901 info.count = maxDrawCount;
4902 info.indirect = buffer;
4903 info.indirect_offset = offset;
4904 info.count_buffer = count_buffer;
4905 info.count_buffer_offset = countBufferOffset;
4906 info.stride = stride;
4907
4908 radv_draw(cmd_buffer, &info);
4909 }
4910
4911 void radv_CmdDrawIndexedIndirectCount(
4912 VkCommandBuffer commandBuffer,
4913 VkBuffer _buffer,
4914 VkDeviceSize offset,
4915 VkBuffer _countBuffer,
4916 VkDeviceSize countBufferOffset,
4917 uint32_t maxDrawCount,
4918 uint32_t stride)
4919 {
4920 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4921 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4922 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4923 struct radv_draw_info info = {};
4924
4925 info.indexed = true;
4926 info.count = maxDrawCount;
4927 info.indirect = buffer;
4928 info.indirect_offset = offset;
4929 info.count_buffer = count_buffer;
4930 info.count_buffer_offset = countBufferOffset;
4931 info.stride = stride;
4932
4933 radv_draw(cmd_buffer, &info);
4934 }
4935
4936 struct radv_dispatch_info {
4937 /**
4938 * Determine the layout of the grid (in block units) to be used.
4939 */
4940 uint32_t blocks[3];
4941
4942 /**
4943 * A starting offset for the grid. If unaligned is set, the offset
4944 * must still be aligned.
4945 */
4946 uint32_t offsets[3];
4947 /**
4948 * Whether it's an unaligned compute dispatch.
4949 */
4950 bool unaligned;
4951
4952 /**
4953 * Indirect compute parameters resource.
4954 */
4955 struct radv_buffer *indirect;
4956 uint64_t indirect_offset;
4957 };
4958
4959 static void
4960 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4961 const struct radv_dispatch_info *info)
4962 {
4963 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4964 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4965 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4966 struct radeon_winsys *ws = cmd_buffer->device->ws;
4967 bool predicating = cmd_buffer->state.predicating;
4968 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4969 struct radv_userdata_info *loc;
4970
4971 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4972 AC_UD_CS_GRID_SIZE);
4973
4974 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4975
4976 if (compute_shader->info.wave_size == 32) {
4977 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
4978 dispatch_initiator |= S_00B800_CS_W32_EN(1);
4979 }
4980
4981 if (info->indirect) {
4982 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4983
4984 va += info->indirect->offset + info->indirect_offset;
4985
4986 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4987
4988 if (loc->sgpr_idx != -1) {
4989 for (unsigned i = 0; i < 3; ++i) {
4990 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4991 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4992 COPY_DATA_DST_SEL(COPY_DATA_REG));
4993 radeon_emit(cs, (va + 4 * i));
4994 radeon_emit(cs, (va + 4 * i) >> 32);
4995 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4996 + loc->sgpr_idx * 4) >> 2) + i);
4997 radeon_emit(cs, 0);
4998 }
4999 }
5000
5001 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
5002 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
5003 PKT3_SHADER_TYPE_S(1));
5004 radeon_emit(cs, va);
5005 radeon_emit(cs, va >> 32);
5006 radeon_emit(cs, dispatch_initiator);
5007 } else {
5008 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
5009 PKT3_SHADER_TYPE_S(1));
5010 radeon_emit(cs, 1);
5011 radeon_emit(cs, va);
5012 radeon_emit(cs, va >> 32);
5013
5014 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
5015 PKT3_SHADER_TYPE_S(1));
5016 radeon_emit(cs, 0);
5017 radeon_emit(cs, dispatch_initiator);
5018 }
5019 } else {
5020 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
5021 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
5022
5023 if (info->unaligned) {
5024 unsigned *cs_block_size = compute_shader->info.cs.block_size;
5025 unsigned remainder[3];
5026
5027 /* If aligned, these should be an entire block size,
5028 * not 0.
5029 */
5030 remainder[0] = blocks[0] + cs_block_size[0] -
5031 align_u32_npot(blocks[0], cs_block_size[0]);
5032 remainder[1] = blocks[1] + cs_block_size[1] -
5033 align_u32_npot(blocks[1], cs_block_size[1]);
5034 remainder[2] = blocks[2] + cs_block_size[2] -
5035 align_u32_npot(blocks[2], cs_block_size[2]);
5036
5037 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
5038 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
5039 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
5040
5041 for(unsigned i = 0; i < 3; ++i) {
5042 assert(offsets[i] % cs_block_size[i] == 0);
5043 offsets[i] /= cs_block_size[i];
5044 }
5045
5046 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5047 radeon_emit(cs,
5048 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
5049 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
5050 radeon_emit(cs,
5051 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
5052 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
5053 radeon_emit(cs,
5054 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
5055 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
5056
5057 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
5058 }
5059
5060 if (loc->sgpr_idx != -1) {
5061 assert(loc->num_sgprs == 3);
5062
5063 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
5064 loc->sgpr_idx * 4, 3);
5065 radeon_emit(cs, blocks[0]);
5066 radeon_emit(cs, blocks[1]);
5067 radeon_emit(cs, blocks[2]);
5068 }
5069
5070 if (offsets[0] || offsets[1] || offsets[2]) {
5071 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
5072 radeon_emit(cs, offsets[0]);
5073 radeon_emit(cs, offsets[1]);
5074 radeon_emit(cs, offsets[2]);
5075
5076 /* The blocks in the packet are not counts but end values. */
5077 for (unsigned i = 0; i < 3; ++i)
5078 blocks[i] += offsets[i];
5079 } else {
5080 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
5081 }
5082
5083 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
5084 PKT3_SHADER_TYPE_S(1));
5085 radeon_emit(cs, blocks[0]);
5086 radeon_emit(cs, blocks[1]);
5087 radeon_emit(cs, blocks[2]);
5088 radeon_emit(cs, dispatch_initiator);
5089 }
5090
5091 assert(cmd_buffer->cs->cdw <= cdw_max);
5092 }
5093
5094 static void
5095 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
5096 {
5097 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5098 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5099 }
5100
5101 static void
5102 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
5103 const struct radv_dispatch_info *info)
5104 {
5105 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5106 bool has_prefetch =
5107 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5108 bool pipeline_is_dirty = pipeline &&
5109 pipeline != cmd_buffer->state.emitted_compute_pipeline;
5110
5111 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5112 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5113 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5114 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5115 /* If we have to wait for idle, set all states first, so that
5116 * all SET packets are processed in parallel with previous draw
5117 * calls. Then upload descriptors, set shader pointers, and
5118 * dispatch, and prefetch at the end. This ensures that the
5119 * time the CUs are idle is very short. (there are only SET_SH
5120 * packets between the wait and the draw)
5121 */
5122 radv_emit_compute_pipeline(cmd_buffer);
5123 si_emit_cache_flush(cmd_buffer);
5124 /* <-- CUs are idle here --> */
5125
5126 radv_upload_compute_shader_descriptors(cmd_buffer);
5127
5128 radv_emit_dispatch_packets(cmd_buffer, info);
5129 /* <-- CUs are busy here --> */
5130
5131 /* Start prefetches after the dispatch has been started. Both
5132 * will run in parallel, but starting the dispatch first is
5133 * more important.
5134 */
5135 if (has_prefetch && pipeline_is_dirty) {
5136 radv_emit_shader_prefetch(cmd_buffer,
5137 pipeline->shaders[MESA_SHADER_COMPUTE]);
5138 }
5139 } else {
5140 /* If we don't wait for idle, start prefetches first, then set
5141 * states, and dispatch at the end.
5142 */
5143 si_emit_cache_flush(cmd_buffer);
5144
5145 if (has_prefetch && pipeline_is_dirty) {
5146 radv_emit_shader_prefetch(cmd_buffer,
5147 pipeline->shaders[MESA_SHADER_COMPUTE]);
5148 }
5149
5150 radv_upload_compute_shader_descriptors(cmd_buffer);
5151
5152 radv_emit_compute_pipeline(cmd_buffer);
5153 radv_emit_dispatch_packets(cmd_buffer, info);
5154 }
5155
5156 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5157 }
5158
5159 void radv_CmdDispatchBase(
5160 VkCommandBuffer commandBuffer,
5161 uint32_t base_x,
5162 uint32_t base_y,
5163 uint32_t base_z,
5164 uint32_t x,
5165 uint32_t y,
5166 uint32_t z)
5167 {
5168 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5169 struct radv_dispatch_info info = {};
5170
5171 info.blocks[0] = x;
5172 info.blocks[1] = y;
5173 info.blocks[2] = z;
5174
5175 info.offsets[0] = base_x;
5176 info.offsets[1] = base_y;
5177 info.offsets[2] = base_z;
5178 radv_dispatch(cmd_buffer, &info);
5179 }
5180
5181 void radv_CmdDispatch(
5182 VkCommandBuffer commandBuffer,
5183 uint32_t x,
5184 uint32_t y,
5185 uint32_t z)
5186 {
5187 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5188 }
5189
5190 void radv_CmdDispatchIndirect(
5191 VkCommandBuffer commandBuffer,
5192 VkBuffer _buffer,
5193 VkDeviceSize offset)
5194 {
5195 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5196 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5197 struct radv_dispatch_info info = {};
5198
5199 info.indirect = buffer;
5200 info.indirect_offset = offset;
5201
5202 radv_dispatch(cmd_buffer, &info);
5203 }
5204
5205 void radv_unaligned_dispatch(
5206 struct radv_cmd_buffer *cmd_buffer,
5207 uint32_t x,
5208 uint32_t y,
5209 uint32_t z)
5210 {
5211 struct radv_dispatch_info info = {};
5212
5213 info.blocks[0] = x;
5214 info.blocks[1] = y;
5215 info.blocks[2] = z;
5216 info.unaligned = 1;
5217
5218 radv_dispatch(cmd_buffer, &info);
5219 }
5220
5221 void radv_CmdEndRenderPass(
5222 VkCommandBuffer commandBuffer)
5223 {
5224 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5225
5226 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5227
5228 radv_cmd_buffer_end_subpass(cmd_buffer);
5229
5230 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5231 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5232
5233 cmd_buffer->state.pass = NULL;
5234 cmd_buffer->state.subpass = NULL;
5235 cmd_buffer->state.attachments = NULL;
5236 cmd_buffer->state.framebuffer = NULL;
5237 cmd_buffer->state.subpass_sample_locs = NULL;
5238 }
5239
5240 void radv_CmdEndRenderPass2(
5241 VkCommandBuffer commandBuffer,
5242 const VkSubpassEndInfo* pSubpassEndInfo)
5243 {
5244 radv_CmdEndRenderPass(commandBuffer);
5245 }
5246
5247 /*
5248 * For HTILE we have the following interesting clear words:
5249 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5250 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5251 * 0xfffffff0: Clear depth to 1.0
5252 * 0x00000000: Clear depth to 0.0
5253 */
5254 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5255 struct radv_image *image,
5256 const VkImageSubresourceRange *range)
5257 {
5258 assert(range->baseMipLevel == 0);
5259 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5260 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5261 struct radv_cmd_state *state = &cmd_buffer->state;
5262 uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5263 VkClearDepthStencilValue value = {};
5264
5265 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5266 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5267
5268 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
5269
5270 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5271
5272 if (vk_format_is_stencil(image->vk_format))
5273 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5274
5275 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5276
5277 if (radv_image_is_tc_compat_htile(image)) {
5278 /* Initialize the TC-compat metada value to 0 because by
5279 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5280 * need have to conditionally update its value when performing
5281 * a fast depth clear.
5282 */
5283 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5284 }
5285 }
5286
5287 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5288 struct radv_image *image,
5289 VkImageLayout src_layout,
5290 bool src_render_loop,
5291 VkImageLayout dst_layout,
5292 bool dst_render_loop,
5293 unsigned src_queue_mask,
5294 unsigned dst_queue_mask,
5295 const VkImageSubresourceRange *range,
5296 struct radv_sample_locations_state *sample_locs)
5297 {
5298 if (!radv_image_has_htile(image))
5299 return;
5300
5301 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5302 radv_initialize_htile(cmd_buffer, image, range);
5303 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5304 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5305 radv_initialize_htile(cmd_buffer, image, range);
5306 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5307 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5308 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5309 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5310
5311 radv_decompress_depth_image_inplace(cmd_buffer, image, range,
5312 sample_locs);
5313
5314 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5315 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5316 }
5317 }
5318
5319 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5320 struct radv_image *image,
5321 const VkImageSubresourceRange *range,
5322 uint32_t value)
5323 {
5324 struct radv_cmd_state *state = &cmd_buffer->state;
5325
5326 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5327 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5328
5329 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5330
5331 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5332 }
5333
5334 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5335 struct radv_image *image,
5336 const VkImageSubresourceRange *range)
5337 {
5338 struct radv_cmd_state *state = &cmd_buffer->state;
5339 static const uint32_t fmask_clear_values[4] = {
5340 0x00000000,
5341 0x02020202,
5342 0xE4E4E4E4,
5343 0x76543210
5344 };
5345 uint32_t log2_samples = util_logbase2(image->info.samples);
5346 uint32_t value = fmask_clear_values[log2_samples];
5347
5348 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5349 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5350
5351 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5352
5353 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5354 }
5355
5356 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5357 struct radv_image *image,
5358 const VkImageSubresourceRange *range, uint32_t value)
5359 {
5360 struct radv_cmd_state *state = &cmd_buffer->state;
5361 unsigned size = 0;
5362
5363 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5364 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5365
5366 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5367
5368 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5369 /* When DCC is enabled with mipmaps, some levels might not
5370 * support fast clears and we have to initialize them as "fully
5371 * expanded".
5372 */
5373 /* Compute the size of all fast clearable DCC levels. */
5374 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5375 struct legacy_surf_level *surf_level =
5376 &image->planes[0].surface.u.legacy.level[i];
5377 unsigned dcc_fast_clear_size =
5378 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5379
5380 if (!dcc_fast_clear_size)
5381 break;
5382
5383 size = surf_level->dcc_offset + dcc_fast_clear_size;
5384 }
5385
5386 /* Initialize the mipmap levels without DCC. */
5387 if (size != image->planes[0].surface.dcc_size) {
5388 state->flush_bits |=
5389 radv_fill_buffer(cmd_buffer, image->bo,
5390 image->offset + image->dcc_offset + size,
5391 image->planes[0].surface.dcc_size - size,
5392 0xffffffff);
5393 }
5394 }
5395
5396 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5397 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5398 }
5399
5400 /**
5401 * Initialize DCC/FMASK/CMASK metadata for a color image.
5402 */
5403 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5404 struct radv_image *image,
5405 VkImageLayout src_layout,
5406 bool src_render_loop,
5407 VkImageLayout dst_layout,
5408 bool dst_render_loop,
5409 unsigned src_queue_mask,
5410 unsigned dst_queue_mask,
5411 const VkImageSubresourceRange *range)
5412 {
5413 if (radv_image_has_cmask(image)) {
5414 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5415
5416 /* TODO: clarify this. */
5417 if (radv_image_has_fmask(image)) {
5418 value = 0xccccccccu;
5419 }
5420
5421 radv_initialise_cmask(cmd_buffer, image, range, value);
5422 }
5423
5424 if (radv_image_has_fmask(image)) {
5425 radv_initialize_fmask(cmd_buffer, image, range);
5426 }
5427
5428 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5429 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5430 bool need_decompress_pass = false;
5431
5432 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5433 dst_render_loop,
5434 dst_queue_mask)) {
5435 value = 0x20202020u;
5436 need_decompress_pass = true;
5437 }
5438
5439 radv_initialize_dcc(cmd_buffer, image, range, value);
5440
5441 radv_update_fce_metadata(cmd_buffer, image, range,
5442 need_decompress_pass);
5443 }
5444
5445 if (radv_image_has_cmask(image) ||
5446 radv_dcc_enabled(image, range->baseMipLevel)) {
5447 uint32_t color_values[2] = {};
5448 radv_set_color_clear_metadata(cmd_buffer, image, range,
5449 color_values);
5450 }
5451 }
5452
5453 /**
5454 * Handle color image transitions for DCC/FMASK/CMASK.
5455 */
5456 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5457 struct radv_image *image,
5458 VkImageLayout src_layout,
5459 bool src_render_loop,
5460 VkImageLayout dst_layout,
5461 bool dst_render_loop,
5462 unsigned src_queue_mask,
5463 unsigned dst_queue_mask,
5464 const VkImageSubresourceRange *range)
5465 {
5466 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5467 radv_init_color_image_metadata(cmd_buffer, image,
5468 src_layout, src_render_loop,
5469 dst_layout, dst_render_loop,
5470 src_queue_mask, dst_queue_mask,
5471 range);
5472 return;
5473 }
5474
5475 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5476 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5477 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5478 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5479 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5480 radv_decompress_dcc(cmd_buffer, image, range);
5481 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5482 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5483 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5484 }
5485 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5486 bool fce_eliminate = false, fmask_expand = false;
5487
5488 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5489 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5490 fce_eliminate = true;
5491 }
5492
5493 if (radv_image_has_fmask(image)) {
5494 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5495 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5496 /* A FMASK decompress is required before doing
5497 * a MSAA decompress using FMASK.
5498 */
5499 fmask_expand = true;
5500 }
5501 }
5502
5503 if (fce_eliminate || fmask_expand)
5504 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5505
5506 if (fmask_expand)
5507 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5508 }
5509 }
5510
5511 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5512 struct radv_image *image,
5513 VkImageLayout src_layout,
5514 bool src_render_loop,
5515 VkImageLayout dst_layout,
5516 bool dst_render_loop,
5517 uint32_t src_family,
5518 uint32_t dst_family,
5519 const VkImageSubresourceRange *range,
5520 struct radv_sample_locations_state *sample_locs)
5521 {
5522 if (image->exclusive && src_family != dst_family) {
5523 /* This is an acquire or a release operation and there will be
5524 * a corresponding release/acquire. Do the transition in the
5525 * most flexible queue. */
5526
5527 assert(src_family == cmd_buffer->queue_family_index ||
5528 dst_family == cmd_buffer->queue_family_index);
5529
5530 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5531 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5532 return;
5533
5534 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5535 return;
5536
5537 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5538 (src_family == RADV_QUEUE_GENERAL ||
5539 dst_family == RADV_QUEUE_GENERAL))
5540 return;
5541 }
5542
5543 if (src_layout == dst_layout)
5544 return;
5545
5546 unsigned src_queue_mask =
5547 radv_image_queue_family_mask(image, src_family,
5548 cmd_buffer->queue_family_index);
5549 unsigned dst_queue_mask =
5550 radv_image_queue_family_mask(image, dst_family,
5551 cmd_buffer->queue_family_index);
5552
5553 if (vk_format_is_depth(image->vk_format)) {
5554 radv_handle_depth_image_transition(cmd_buffer, image,
5555 src_layout, src_render_loop,
5556 dst_layout, dst_render_loop,
5557 src_queue_mask, dst_queue_mask,
5558 range, sample_locs);
5559 } else {
5560 radv_handle_color_image_transition(cmd_buffer, image,
5561 src_layout, src_render_loop,
5562 dst_layout, dst_render_loop,
5563 src_queue_mask, dst_queue_mask,
5564 range);
5565 }
5566 }
5567
5568 struct radv_barrier_info {
5569 uint32_t eventCount;
5570 const VkEvent *pEvents;
5571 VkPipelineStageFlags srcStageMask;
5572 VkPipelineStageFlags dstStageMask;
5573 };
5574
5575 static void
5576 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5577 uint32_t memoryBarrierCount,
5578 const VkMemoryBarrier *pMemoryBarriers,
5579 uint32_t bufferMemoryBarrierCount,
5580 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5581 uint32_t imageMemoryBarrierCount,
5582 const VkImageMemoryBarrier *pImageMemoryBarriers,
5583 const struct radv_barrier_info *info)
5584 {
5585 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5586 enum radv_cmd_flush_bits src_flush_bits = 0;
5587 enum radv_cmd_flush_bits dst_flush_bits = 0;
5588
5589 for (unsigned i = 0; i < info->eventCount; ++i) {
5590 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5591 uint64_t va = radv_buffer_get_va(event->bo);
5592
5593 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5594
5595 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5596
5597 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5598 assert(cmd_buffer->cs->cdw <= cdw_max);
5599 }
5600
5601 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5602 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5603 NULL);
5604 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5605 NULL);
5606 }
5607
5608 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5609 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5610 NULL);
5611 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5612 NULL);
5613 }
5614
5615 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5616 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5617
5618 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5619 image);
5620 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5621 image);
5622 }
5623
5624 /* The Vulkan spec 1.1.98 says:
5625 *
5626 * "An execution dependency with only
5627 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5628 * will only prevent that stage from executing in subsequently
5629 * submitted commands. As this stage does not perform any actual
5630 * execution, this is not observable - in effect, it does not delay
5631 * processing of subsequent commands. Similarly an execution dependency
5632 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5633 * will effectively not wait for any prior commands to complete."
5634 */
5635 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5636 radv_stage_flush(cmd_buffer, info->srcStageMask);
5637 cmd_buffer->state.flush_bits |= src_flush_bits;
5638
5639 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5640 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5641
5642 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5643 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5644 SAMPLE_LOCATIONS_INFO_EXT);
5645 struct radv_sample_locations_state sample_locations = {};
5646
5647 if (sample_locs_info) {
5648 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5649 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5650 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5651 sample_locations.count = sample_locs_info->sampleLocationsCount;
5652 typed_memcpy(&sample_locations.locations[0],
5653 sample_locs_info->pSampleLocations,
5654 sample_locs_info->sampleLocationsCount);
5655 }
5656
5657 radv_handle_image_transition(cmd_buffer, image,
5658 pImageMemoryBarriers[i].oldLayout,
5659 false, /* Outside of a renderpass we are never in a renderloop */
5660 pImageMemoryBarriers[i].newLayout,
5661 false, /* Outside of a renderpass we are never in a renderloop */
5662 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5663 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5664 &pImageMemoryBarriers[i].subresourceRange,
5665 sample_locs_info ? &sample_locations : NULL);
5666 }
5667
5668 /* Make sure CP DMA is idle because the driver might have performed a
5669 * DMA operation for copying or filling buffers/images.
5670 */
5671 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5672 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5673 si_cp_dma_wait_for_idle(cmd_buffer);
5674
5675 cmd_buffer->state.flush_bits |= dst_flush_bits;
5676 }
5677
5678 void radv_CmdPipelineBarrier(
5679 VkCommandBuffer commandBuffer,
5680 VkPipelineStageFlags srcStageMask,
5681 VkPipelineStageFlags destStageMask,
5682 VkBool32 byRegion,
5683 uint32_t memoryBarrierCount,
5684 const VkMemoryBarrier* pMemoryBarriers,
5685 uint32_t bufferMemoryBarrierCount,
5686 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5687 uint32_t imageMemoryBarrierCount,
5688 const VkImageMemoryBarrier* pImageMemoryBarriers)
5689 {
5690 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5691 struct radv_barrier_info info;
5692
5693 info.eventCount = 0;
5694 info.pEvents = NULL;
5695 info.srcStageMask = srcStageMask;
5696 info.dstStageMask = destStageMask;
5697
5698 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5699 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5700 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5701 }
5702
5703
5704 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5705 struct radv_event *event,
5706 VkPipelineStageFlags stageMask,
5707 unsigned value)
5708 {
5709 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5710 uint64_t va = radv_buffer_get_va(event->bo);
5711
5712 si_emit_cache_flush(cmd_buffer);
5713
5714 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5715
5716 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5717
5718 /* Flags that only require a top-of-pipe event. */
5719 VkPipelineStageFlags top_of_pipe_flags =
5720 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5721
5722 /* Flags that only require a post-index-fetch event. */
5723 VkPipelineStageFlags post_index_fetch_flags =
5724 top_of_pipe_flags |
5725 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5726 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5727
5728 /* Make sure CP DMA is idle because the driver might have performed a
5729 * DMA operation for copying or filling buffers/images.
5730 */
5731 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5732 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5733 si_cp_dma_wait_for_idle(cmd_buffer);
5734
5735 /* TODO: Emit EOS events for syncing PS/CS stages. */
5736
5737 if (!(stageMask & ~top_of_pipe_flags)) {
5738 /* Just need to sync the PFP engine. */
5739 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5740 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5741 S_370_WR_CONFIRM(1) |
5742 S_370_ENGINE_SEL(V_370_PFP));
5743 radeon_emit(cs, va);
5744 radeon_emit(cs, va >> 32);
5745 radeon_emit(cs, value);
5746 } else if (!(stageMask & ~post_index_fetch_flags)) {
5747 /* Sync ME because PFP reads index and indirect buffers. */
5748 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5749 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5750 S_370_WR_CONFIRM(1) |
5751 S_370_ENGINE_SEL(V_370_ME));
5752 radeon_emit(cs, va);
5753 radeon_emit(cs, va >> 32);
5754 radeon_emit(cs, value);
5755 } else {
5756 /* Otherwise, sync all prior GPU work using an EOP event. */
5757 si_cs_emit_write_event_eop(cs,
5758 cmd_buffer->device->physical_device->rad_info.chip_class,
5759 radv_cmd_buffer_uses_mec(cmd_buffer),
5760 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5761 EOP_DST_SEL_MEM,
5762 EOP_DATA_SEL_VALUE_32BIT, va, value,
5763 cmd_buffer->gfx9_eop_bug_va);
5764 }
5765
5766 assert(cmd_buffer->cs->cdw <= cdw_max);
5767 }
5768
5769 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5770 VkEvent _event,
5771 VkPipelineStageFlags stageMask)
5772 {
5773 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5774 RADV_FROM_HANDLE(radv_event, event, _event);
5775
5776 write_event(cmd_buffer, event, stageMask, 1);
5777 }
5778
5779 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5780 VkEvent _event,
5781 VkPipelineStageFlags stageMask)
5782 {
5783 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5784 RADV_FROM_HANDLE(radv_event, event, _event);
5785
5786 write_event(cmd_buffer, event, stageMask, 0);
5787 }
5788
5789 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5790 uint32_t eventCount,
5791 const VkEvent* pEvents,
5792 VkPipelineStageFlags srcStageMask,
5793 VkPipelineStageFlags dstStageMask,
5794 uint32_t memoryBarrierCount,
5795 const VkMemoryBarrier* pMemoryBarriers,
5796 uint32_t bufferMemoryBarrierCount,
5797 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5798 uint32_t imageMemoryBarrierCount,
5799 const VkImageMemoryBarrier* pImageMemoryBarriers)
5800 {
5801 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5802 struct radv_barrier_info info;
5803
5804 info.eventCount = eventCount;
5805 info.pEvents = pEvents;
5806 info.srcStageMask = 0;
5807
5808 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5809 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5810 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5811 }
5812
5813
5814 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5815 uint32_t deviceMask)
5816 {
5817 /* No-op */
5818 }
5819
5820 /* VK_EXT_conditional_rendering */
5821 void radv_CmdBeginConditionalRenderingEXT(
5822 VkCommandBuffer commandBuffer,
5823 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5824 {
5825 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5826 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5827 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5828 bool draw_visible = true;
5829 uint64_t pred_value = 0;
5830 uint64_t va, new_va;
5831 unsigned pred_offset;
5832
5833 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5834
5835 /* By default, if the 32-bit value at offset in buffer memory is zero,
5836 * then the rendering commands are discarded, otherwise they are
5837 * executed as normal. If the inverted flag is set, all commands are
5838 * discarded if the value is non zero.
5839 */
5840 if (pConditionalRenderingBegin->flags &
5841 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5842 draw_visible = false;
5843 }
5844
5845 si_emit_cache_flush(cmd_buffer);
5846
5847 /* From the Vulkan spec 1.1.107:
5848 *
5849 * "If the 32-bit value at offset in buffer memory is zero, then the
5850 * rendering commands are discarded, otherwise they are executed as
5851 * normal. If the value of the predicate in buffer memory changes while
5852 * conditional rendering is active, the rendering commands may be
5853 * discarded in an implementation-dependent way. Some implementations
5854 * may latch the value of the predicate upon beginning conditional
5855 * rendering while others may read it before every rendering command."
5856 *
5857 * But, the AMD hardware treats the predicate as a 64-bit value which
5858 * means we need a workaround in the driver. Luckily, it's not required
5859 * to support if the value changes when predication is active.
5860 *
5861 * The workaround is as follows:
5862 * 1) allocate a 64-value in the upload BO and initialize it to 0
5863 * 2) copy the 32-bit predicate value to the upload BO
5864 * 3) use the new allocated VA address for predication
5865 *
5866 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5867 * in ME (+ sync PFP) instead of PFP.
5868 */
5869 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5870
5871 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5872
5873 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5874 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5875 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5876 COPY_DATA_WR_CONFIRM);
5877 radeon_emit(cs, va);
5878 radeon_emit(cs, va >> 32);
5879 radeon_emit(cs, new_va);
5880 radeon_emit(cs, new_va >> 32);
5881
5882 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5883 radeon_emit(cs, 0);
5884
5885 /* Enable predication for this command buffer. */
5886 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5887 cmd_buffer->state.predicating = true;
5888
5889 /* Store conditional rendering user info. */
5890 cmd_buffer->state.predication_type = draw_visible;
5891 cmd_buffer->state.predication_va = new_va;
5892 }
5893
5894 void radv_CmdEndConditionalRenderingEXT(
5895 VkCommandBuffer commandBuffer)
5896 {
5897 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5898
5899 /* Disable predication for this command buffer. */
5900 si_emit_set_predication_state(cmd_buffer, false, 0);
5901 cmd_buffer->state.predicating = false;
5902
5903 /* Reset conditional rendering user info. */
5904 cmd_buffer->state.predication_type = -1;
5905 cmd_buffer->state.predication_va = 0;
5906 }
5907
5908 /* VK_EXT_transform_feedback */
5909 void radv_CmdBindTransformFeedbackBuffersEXT(
5910 VkCommandBuffer commandBuffer,
5911 uint32_t firstBinding,
5912 uint32_t bindingCount,
5913 const VkBuffer* pBuffers,
5914 const VkDeviceSize* pOffsets,
5915 const VkDeviceSize* pSizes)
5916 {
5917 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5918 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5919 uint8_t enabled_mask = 0;
5920
5921 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5922 for (uint32_t i = 0; i < bindingCount; i++) {
5923 uint32_t idx = firstBinding + i;
5924
5925 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5926 sb[idx].offset = pOffsets[i];
5927 sb[idx].size = pSizes[i];
5928
5929 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5930 sb[idx].buffer->bo);
5931
5932 enabled_mask |= 1 << idx;
5933 }
5934
5935 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5936
5937 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5938 }
5939
5940 static void
5941 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5942 {
5943 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5944 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5945
5946 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5947 radeon_emit(cs,
5948 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5949 S_028B94_RAST_STREAM(0) |
5950 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5951 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5952 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5953 radeon_emit(cs, so->hw_enabled_mask &
5954 so->enabled_stream_buffers_mask);
5955
5956 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5957 }
5958
5959 static void
5960 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5961 {
5962 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5963 bool old_streamout_enabled = so->streamout_enabled;
5964 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5965
5966 so->streamout_enabled = enable;
5967
5968 so->hw_enabled_mask = so->enabled_mask |
5969 (so->enabled_mask << 4) |
5970 (so->enabled_mask << 8) |
5971 (so->enabled_mask << 12);
5972
5973 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
5974 ((old_streamout_enabled != so->streamout_enabled) ||
5975 (old_hw_enabled_mask != so->hw_enabled_mask)))
5976 radv_emit_streamout_enable(cmd_buffer);
5977
5978 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
5979 cmd_buffer->gds_needed = true;
5980 cmd_buffer->gds_oa_needed = true;
5981 }
5982 }
5983
5984 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5985 {
5986 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5987 unsigned reg_strmout_cntl;
5988
5989 /* The register is at different places on different ASICs. */
5990 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5991 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5992 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5993 } else {
5994 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5995 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5996 }
5997
5998 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5999 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
6000
6001 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
6002 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
6003 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
6004 radeon_emit(cs, 0);
6005 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6006 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6007 radeon_emit(cs, 4); /* poll interval */
6008 }
6009
6010 static void
6011 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6012 uint32_t firstCounterBuffer,
6013 uint32_t counterBufferCount,
6014 const VkBuffer *pCounterBuffers,
6015 const VkDeviceSize *pCounterBufferOffsets)
6016
6017 {
6018 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6019 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6020 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6021 uint32_t i;
6022
6023 radv_flush_vgt_streamout(cmd_buffer);
6024
6025 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6026 for_each_bit(i, so->enabled_mask) {
6027 int32_t counter_buffer_idx = i - firstCounterBuffer;
6028 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6029 counter_buffer_idx = -1;
6030
6031 /* AMD GCN binds streamout buffers as shader resources.
6032 * VGT only counts primitives and tells the shader through
6033 * SGPRs what to do.
6034 */
6035 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
6036 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
6037 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
6038
6039 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6040
6041 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6042 /* The array of counter buffers is optional. */
6043 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6044 uint64_t va = radv_buffer_get_va(buffer->bo);
6045
6046 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6047
6048 /* Append */
6049 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6050 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6051 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6052 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
6053 radeon_emit(cs, 0); /* unused */
6054 radeon_emit(cs, 0); /* unused */
6055 radeon_emit(cs, va); /* src address lo */
6056 radeon_emit(cs, va >> 32); /* src address hi */
6057
6058 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6059 } else {
6060 /* Start from the beginning. */
6061 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6062 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6063 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6064 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
6065 radeon_emit(cs, 0); /* unused */
6066 radeon_emit(cs, 0); /* unused */
6067 radeon_emit(cs, 0); /* unused */
6068 radeon_emit(cs, 0); /* unused */
6069 }
6070 }
6071
6072 radv_set_streamout_enable(cmd_buffer, true);
6073 }
6074
6075 static void
6076 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6077 uint32_t firstCounterBuffer,
6078 uint32_t counterBufferCount,
6079 const VkBuffer *pCounterBuffers,
6080 const VkDeviceSize *pCounterBufferOffsets)
6081 {
6082 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6083 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
6084 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6085 uint32_t i;
6086
6087 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6088 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6089
6090 /* Sync because the next streamout operation will overwrite GDS and we
6091 * have to make sure it's idle.
6092 * TODO: Improve by tracking if there is a streamout operation in
6093 * flight.
6094 */
6095 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
6096 si_emit_cache_flush(cmd_buffer);
6097
6098 for_each_bit(i, so->enabled_mask) {
6099 int32_t counter_buffer_idx = i - firstCounterBuffer;
6100 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6101 counter_buffer_idx = -1;
6102
6103 bool append = counter_buffer_idx >= 0 &&
6104 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
6105 uint64_t va = 0;
6106
6107 if (append) {
6108 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6109
6110 va += radv_buffer_get_va(buffer->bo);
6111 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6112
6113 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6114 }
6115
6116 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6117 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6118 S_411_DST_SEL(V_411_GDS) |
6119 S_411_CP_SYNC(i == last_target));
6120 radeon_emit(cs, va);
6121 radeon_emit(cs, va >> 32);
6122 radeon_emit(cs, 4 * i); /* destination in GDS */
6123 radeon_emit(cs, 0);
6124 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6125 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6126 }
6127
6128 radv_set_streamout_enable(cmd_buffer, true);
6129 }
6130
6131 void radv_CmdBeginTransformFeedbackEXT(
6132 VkCommandBuffer commandBuffer,
6133 uint32_t firstCounterBuffer,
6134 uint32_t counterBufferCount,
6135 const VkBuffer* pCounterBuffers,
6136 const VkDeviceSize* pCounterBufferOffsets)
6137 {
6138 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6139
6140 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6141 gfx10_emit_streamout_begin(cmd_buffer,
6142 firstCounterBuffer, counterBufferCount,
6143 pCounterBuffers, pCounterBufferOffsets);
6144 } else {
6145 radv_emit_streamout_begin(cmd_buffer,
6146 firstCounterBuffer, counterBufferCount,
6147 pCounterBuffers, pCounterBufferOffsets);
6148 }
6149 }
6150
6151 static void
6152 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6153 uint32_t firstCounterBuffer,
6154 uint32_t counterBufferCount,
6155 const VkBuffer *pCounterBuffers,
6156 const VkDeviceSize *pCounterBufferOffsets)
6157 {
6158 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6159 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6160 uint32_t i;
6161
6162 radv_flush_vgt_streamout(cmd_buffer);
6163
6164 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6165 for_each_bit(i, so->enabled_mask) {
6166 int32_t counter_buffer_idx = i - firstCounterBuffer;
6167 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6168 counter_buffer_idx = -1;
6169
6170 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6171 /* The array of counters buffer is optional. */
6172 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6173 uint64_t va = radv_buffer_get_va(buffer->bo);
6174
6175 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6176
6177 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6178 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6179 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6180 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6181 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6182 radeon_emit(cs, va); /* dst address lo */
6183 radeon_emit(cs, va >> 32); /* dst address hi */
6184 radeon_emit(cs, 0); /* unused */
6185 radeon_emit(cs, 0); /* unused */
6186
6187 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6188 }
6189
6190 /* Deactivate transform feedback by zeroing the buffer size.
6191 * The counters (primitives generated, primitives emitted) may
6192 * be enabled even if there is not buffer bound. This ensures
6193 * that the primitives-emitted query won't increment.
6194 */
6195 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6196
6197 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6198 }
6199
6200 radv_set_streamout_enable(cmd_buffer, false);
6201 }
6202
6203 static void
6204 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6205 uint32_t firstCounterBuffer,
6206 uint32_t counterBufferCount,
6207 const VkBuffer *pCounterBuffers,
6208 const VkDeviceSize *pCounterBufferOffsets)
6209 {
6210 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6211 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6212 uint32_t i;
6213
6214 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6215 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6216
6217 for_each_bit(i, so->enabled_mask) {
6218 int32_t counter_buffer_idx = i - firstCounterBuffer;
6219 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6220 counter_buffer_idx = -1;
6221
6222 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6223 /* The array of counters buffer is optional. */
6224 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6225 uint64_t va = radv_buffer_get_va(buffer->bo);
6226
6227 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6228
6229 si_cs_emit_write_event_eop(cs,
6230 cmd_buffer->device->physical_device->rad_info.chip_class,
6231 radv_cmd_buffer_uses_mec(cmd_buffer),
6232 V_028A90_PS_DONE, 0,
6233 EOP_DST_SEL_TC_L2,
6234 EOP_DATA_SEL_GDS,
6235 va, EOP_DATA_GDS(i, 1), 0);
6236
6237 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6238 }
6239 }
6240
6241 radv_set_streamout_enable(cmd_buffer, false);
6242 }
6243
6244 void radv_CmdEndTransformFeedbackEXT(
6245 VkCommandBuffer commandBuffer,
6246 uint32_t firstCounterBuffer,
6247 uint32_t counterBufferCount,
6248 const VkBuffer* pCounterBuffers,
6249 const VkDeviceSize* pCounterBufferOffsets)
6250 {
6251 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6252
6253 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6254 gfx10_emit_streamout_end(cmd_buffer,
6255 firstCounterBuffer, counterBufferCount,
6256 pCounterBuffers, pCounterBufferOffsets);
6257 } else {
6258 radv_emit_streamout_end(cmd_buffer,
6259 firstCounterBuffer, counterBufferCount,
6260 pCounterBuffers, pCounterBufferOffsets);
6261 }
6262 }
6263
6264 void radv_CmdDrawIndirectByteCountEXT(
6265 VkCommandBuffer commandBuffer,
6266 uint32_t instanceCount,
6267 uint32_t firstInstance,
6268 VkBuffer _counterBuffer,
6269 VkDeviceSize counterBufferOffset,
6270 uint32_t counterOffset,
6271 uint32_t vertexStride)
6272 {
6273 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6274 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6275 struct radv_draw_info info = {};
6276
6277 info.instance_count = instanceCount;
6278 info.first_instance = firstInstance;
6279 info.strmout_buffer = counterBuffer;
6280 info.strmout_buffer_offset = counterBufferOffset;
6281 info.stride = vertexStride;
6282
6283 radv_draw(cmd_buffer, &info);
6284 }
6285
6286 /* VK_AMD_buffer_marker */
6287 void radv_CmdWriteBufferMarkerAMD(
6288 VkCommandBuffer commandBuffer,
6289 VkPipelineStageFlagBits pipelineStage,
6290 VkBuffer dstBuffer,
6291 VkDeviceSize dstOffset,
6292 uint32_t marker)
6293 {
6294 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6295 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6296 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6297 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6298
6299 si_emit_cache_flush(cmd_buffer);
6300
6301 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6302
6303 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6304 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6305 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6306 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6307 COPY_DATA_WR_CONFIRM);
6308 radeon_emit(cs, marker);
6309 radeon_emit(cs, 0);
6310 radeon_emit(cs, va);
6311 radeon_emit(cs, va >> 32);
6312 } else {
6313 si_cs_emit_write_event_eop(cs,
6314 cmd_buffer->device->physical_device->rad_info.chip_class,
6315 radv_cmd_buffer_uses_mec(cmd_buffer),
6316 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6317 EOP_DST_SEL_MEM,
6318 EOP_DATA_SEL_VALUE_32BIT,
6319 va, marker,
6320 cmd_buffer->gfx9_eop_bug_va);
6321 }
6322
6323 assert(cmd_buffer->cs->cdw <= cdw_max);
6324 }