2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
33 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
41 RADV_PREFETCH_VBO_DESCRIPTORS
= (1 << 0),
42 RADV_PREFETCH_VS
= (1 << 1),
43 RADV_PREFETCH_TCS
= (1 << 2),
44 RADV_PREFETCH_TES
= (1 << 3),
45 RADV_PREFETCH_GS
= (1 << 4),
46 RADV_PREFETCH_PS
= (1 << 5),
47 RADV_PREFETCH_SHADERS
= (RADV_PREFETCH_VS
|
54 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
55 struct radv_image
*image
,
56 VkImageLayout src_layout
,
58 VkImageLayout dst_layout
,
62 const VkImageSubresourceRange
*range
,
63 struct radv_sample_locations_state
*sample_locs
);
65 const struct radv_dynamic_state default_dynamic_state
= {
78 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
83 .stencil_compare_mask
= {
87 .stencil_write_mask
= {
91 .stencil_reference
= {
102 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
103 const struct radv_dynamic_state
*src
)
105 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
106 uint32_t copy_mask
= src
->mask
;
107 uint32_t dest_mask
= 0;
109 /* Make sure to copy the number of viewports/scissors because they can
110 * only be specified at pipeline creation time.
112 dest
->viewport
.count
= src
->viewport
.count
;
113 dest
->scissor
.count
= src
->scissor
.count
;
114 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
115 dest
->sample_location
.count
= src
->sample_location
.count
;
117 if (copy_mask
& RADV_DYNAMIC_VIEWPORT
) {
118 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
119 src
->viewport
.count
* sizeof(VkViewport
))) {
120 typed_memcpy(dest
->viewport
.viewports
,
121 src
->viewport
.viewports
,
122 src
->viewport
.count
);
123 dest_mask
|= RADV_DYNAMIC_VIEWPORT
;
127 if (copy_mask
& RADV_DYNAMIC_SCISSOR
) {
128 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
129 src
->scissor
.count
* sizeof(VkRect2D
))) {
130 typed_memcpy(dest
->scissor
.scissors
,
131 src
->scissor
.scissors
, src
->scissor
.count
);
132 dest_mask
|= RADV_DYNAMIC_SCISSOR
;
136 if (copy_mask
& RADV_DYNAMIC_LINE_WIDTH
) {
137 if (dest
->line_width
!= src
->line_width
) {
138 dest
->line_width
= src
->line_width
;
139 dest_mask
|= RADV_DYNAMIC_LINE_WIDTH
;
143 if (copy_mask
& RADV_DYNAMIC_DEPTH_BIAS
) {
144 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
145 sizeof(src
->depth_bias
))) {
146 dest
->depth_bias
= src
->depth_bias
;
147 dest_mask
|= RADV_DYNAMIC_DEPTH_BIAS
;
151 if (copy_mask
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
152 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
153 sizeof(src
->blend_constants
))) {
154 typed_memcpy(dest
->blend_constants
,
155 src
->blend_constants
, 4);
156 dest_mask
|= RADV_DYNAMIC_BLEND_CONSTANTS
;
160 if (copy_mask
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
161 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
162 sizeof(src
->depth_bounds
))) {
163 dest
->depth_bounds
= src
->depth_bounds
;
164 dest_mask
|= RADV_DYNAMIC_DEPTH_BOUNDS
;
168 if (copy_mask
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
169 if (memcmp(&dest
->stencil_compare_mask
,
170 &src
->stencil_compare_mask
,
171 sizeof(src
->stencil_compare_mask
))) {
172 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
173 dest_mask
|= RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
177 if (copy_mask
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
178 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
179 sizeof(src
->stencil_write_mask
))) {
180 dest
->stencil_write_mask
= src
->stencil_write_mask
;
181 dest_mask
|= RADV_DYNAMIC_STENCIL_WRITE_MASK
;
185 if (copy_mask
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
186 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
187 sizeof(src
->stencil_reference
))) {
188 dest
->stencil_reference
= src
->stencil_reference
;
189 dest_mask
|= RADV_DYNAMIC_STENCIL_REFERENCE
;
193 if (copy_mask
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
194 if (memcmp(&dest
->discard_rectangle
.rectangles
, &src
->discard_rectangle
.rectangles
,
195 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
196 typed_memcpy(dest
->discard_rectangle
.rectangles
,
197 src
->discard_rectangle
.rectangles
,
198 src
->discard_rectangle
.count
);
199 dest_mask
|= RADV_DYNAMIC_DISCARD_RECTANGLE
;
203 if (copy_mask
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
204 if (dest
->sample_location
.per_pixel
!= src
->sample_location
.per_pixel
||
205 dest
->sample_location
.grid_size
.width
!= src
->sample_location
.grid_size
.width
||
206 dest
->sample_location
.grid_size
.height
!= src
->sample_location
.grid_size
.height
||
207 memcmp(&dest
->sample_location
.locations
,
208 &src
->sample_location
.locations
,
209 src
->sample_location
.count
* sizeof(VkSampleLocationEXT
))) {
210 dest
->sample_location
.per_pixel
= src
->sample_location
.per_pixel
;
211 dest
->sample_location
.grid_size
= src
->sample_location
.grid_size
;
212 typed_memcpy(dest
->sample_location
.locations
,
213 src
->sample_location
.locations
,
214 src
->sample_location
.count
);
215 dest_mask
|= RADV_DYNAMIC_SAMPLE_LOCATIONS
;
219 if (copy_mask
& RADV_DYNAMIC_LINE_STIPPLE
) {
220 if (memcmp(&dest
->line_stipple
, &src
->line_stipple
,
221 sizeof(src
->line_stipple
))) {
222 dest
->line_stipple
= src
->line_stipple
;
223 dest_mask
|= RADV_DYNAMIC_LINE_STIPPLE
;
227 cmd_buffer
->state
.dirty
|= dest_mask
;
231 radv_bind_streamout_state(struct radv_cmd_buffer
*cmd_buffer
,
232 struct radv_pipeline
*pipeline
)
234 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
235 struct radv_shader_info
*info
;
237 if (!pipeline
->streamout_shader
||
238 cmd_buffer
->device
->physical_device
->use_ngg_streamout
)
241 info
= &pipeline
->streamout_shader
->info
;
242 for (int i
= 0; i
< MAX_SO_BUFFERS
; i
++)
243 so
->stride_in_dw
[i
] = info
->so
.strides
[i
];
245 so
->enabled_stream_buffers_mask
= info
->so
.enabled_stream_buffers_mask
;
248 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
250 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
251 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
254 enum ring_type
radv_queue_family_to_ring(int f
) {
256 case RADV_QUEUE_GENERAL
:
258 case RADV_QUEUE_COMPUTE
:
260 case RADV_QUEUE_TRANSFER
:
263 unreachable("Unknown queue family");
267 static VkResult
radv_create_cmd_buffer(
268 struct radv_device
* device
,
269 struct radv_cmd_pool
* pool
,
270 VkCommandBufferLevel level
,
271 VkCommandBuffer
* pCommandBuffer
)
273 struct radv_cmd_buffer
*cmd_buffer
;
275 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
276 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
277 if (cmd_buffer
== NULL
)
278 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
280 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
281 cmd_buffer
->device
= device
;
282 cmd_buffer
->pool
= pool
;
283 cmd_buffer
->level
= level
;
286 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
287 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
290 /* Init the pool_link so we can safely call list_del when we destroy
293 list_inithead(&cmd_buffer
->pool_link
);
294 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
297 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
299 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
300 if (!cmd_buffer
->cs
) {
301 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
302 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
305 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
307 list_inithead(&cmd_buffer
->upload
.list
);
313 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
315 list_del(&cmd_buffer
->pool_link
);
317 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
318 &cmd_buffer
->upload
.list
, list
) {
319 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
324 if (cmd_buffer
->upload
.upload_bo
)
325 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
326 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
328 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
329 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
331 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
335 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
337 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
339 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
340 &cmd_buffer
->upload
.list
, list
) {
341 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
346 cmd_buffer
->push_constant_stages
= 0;
347 cmd_buffer
->scratch_size_per_wave_needed
= 0;
348 cmd_buffer
->scratch_waves_wanted
= 0;
349 cmd_buffer
->compute_scratch_size_per_wave_needed
= 0;
350 cmd_buffer
->compute_scratch_waves_wanted
= 0;
351 cmd_buffer
->esgs_ring_size_needed
= 0;
352 cmd_buffer
->gsvs_ring_size_needed
= 0;
353 cmd_buffer
->tess_rings_needed
= false;
354 cmd_buffer
->gds_needed
= false;
355 cmd_buffer
->gds_oa_needed
= false;
356 cmd_buffer
->sample_positions_needed
= false;
358 if (cmd_buffer
->upload
.upload_bo
)
359 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
360 cmd_buffer
->upload
.upload_bo
);
361 cmd_buffer
->upload
.offset
= 0;
363 cmd_buffer
->record_result
= VK_SUCCESS
;
365 memset(cmd_buffer
->vertex_bindings
, 0, sizeof(cmd_buffer
->vertex_bindings
));
367 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
368 cmd_buffer
->descriptors
[i
].dirty
= 0;
369 cmd_buffer
->descriptors
[i
].valid
= 0;
370 cmd_buffer
->descriptors
[i
].push_dirty
= false;
373 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
374 cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
) {
375 unsigned num_db
= cmd_buffer
->device
->physical_device
->rad_info
.num_render_backends
;
376 unsigned fence_offset
, eop_bug_offset
;
379 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 8, &fence_offset
,
382 cmd_buffer
->gfx9_fence_va
=
383 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
384 cmd_buffer
->gfx9_fence_va
+= fence_offset
;
386 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
387 /* Allocate a buffer for the EOP bug on GFX9. */
388 radv_cmd_buffer_upload_alloc(cmd_buffer
, 16 * num_db
, 8,
389 &eop_bug_offset
, &fence_ptr
);
390 cmd_buffer
->gfx9_eop_bug_va
=
391 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
392 cmd_buffer
->gfx9_eop_bug_va
+= eop_bug_offset
;
396 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_INITIAL
;
398 return cmd_buffer
->record_result
;
402 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
406 struct radeon_winsys_bo
*bo
;
407 struct radv_cmd_buffer_upload
*upload
;
408 struct radv_device
*device
= cmd_buffer
->device
;
410 new_size
= MAX2(min_needed
, 16 * 1024);
411 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
413 bo
= device
->ws
->buffer_create(device
->ws
,
416 RADEON_FLAG_CPU_ACCESS
|
417 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
419 RADV_BO_PRIORITY_UPLOAD_BUFFER
);
422 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
426 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, bo
);
427 if (cmd_buffer
->upload
.upload_bo
) {
428 upload
= malloc(sizeof(*upload
));
431 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
432 device
->ws
->buffer_destroy(bo
);
436 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
437 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
440 cmd_buffer
->upload
.upload_bo
= bo
;
441 cmd_buffer
->upload
.size
= new_size
;
442 cmd_buffer
->upload
.offset
= 0;
443 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
445 if (!cmd_buffer
->upload
.map
) {
446 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
454 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
457 unsigned *out_offset
,
460 assert(util_is_power_of_two_nonzero(alignment
));
462 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
463 if (offset
+ size
> cmd_buffer
->upload
.size
) {
464 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
469 *out_offset
= offset
;
470 *ptr
= cmd_buffer
->upload
.map
+ offset
;
472 cmd_buffer
->upload
.offset
= offset
+ size
;
477 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
478 unsigned size
, unsigned alignment
,
479 const void *data
, unsigned *out_offset
)
483 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
484 out_offset
, (void **)&ptr
))
488 memcpy(ptr
, data
, size
);
494 radv_emit_write_data_packet(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
495 unsigned count
, const uint32_t *data
)
497 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
499 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4 + count
);
501 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
502 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
503 S_370_WR_CONFIRM(1) |
504 S_370_ENGINE_SEL(V_370_ME
));
506 radeon_emit(cs
, va
>> 32);
507 radeon_emit_array(cs
, data
, count
);
510 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
512 struct radv_device
*device
= cmd_buffer
->device
;
513 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
516 va
= radv_buffer_get_va(device
->trace_bo
);
517 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
520 ++cmd_buffer
->state
.trace_id
;
521 radv_emit_write_data_packet(cmd_buffer
, va
, 1,
522 &cmd_buffer
->state
.trace_id
);
524 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 2);
526 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
527 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
531 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
,
532 enum radv_cmd_flush_bits flags
)
534 if (unlikely(cmd_buffer
->device
->thread_trace_bo
)) {
535 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
536 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER
) | EVENT_INDEX(0));
539 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
540 assert(flags
& (RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
541 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
));
543 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 4);
545 /* Force wait for graphics or compute engines to be idle. */
546 si_cs_emit_cache_flush(cmd_buffer
->cs
,
547 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
548 &cmd_buffer
->gfx9_fence_idx
,
549 cmd_buffer
->gfx9_fence_va
,
550 radv_cmd_buffer_uses_mec(cmd_buffer
),
551 flags
, cmd_buffer
->gfx9_eop_bug_va
);
554 if (unlikely(cmd_buffer
->device
->trace_bo
))
555 radv_cmd_buffer_trace_emit(cmd_buffer
);
559 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
560 struct radv_pipeline
*pipeline
, enum ring_type ring
)
562 struct radv_device
*device
= cmd_buffer
->device
;
566 va
= radv_buffer_get_va(device
->trace_bo
);
576 assert(!"invalid ring type");
579 uint64_t pipeline_address
= (uintptr_t)pipeline
;
580 data
[0] = pipeline_address
;
581 data
[1] = pipeline_address
>> 32;
583 radv_emit_write_data_packet(cmd_buffer
, va
, 2, data
);
586 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
587 VkPipelineBindPoint bind_point
,
588 struct radv_descriptor_set
*set
,
591 struct radv_descriptor_state
*descriptors_state
=
592 radv_get_descriptors_state(cmd_buffer
, bind_point
);
594 descriptors_state
->sets
[idx
] = set
;
596 descriptors_state
->valid
|= (1u << idx
); /* active descriptors */
597 descriptors_state
->dirty
|= (1u << idx
);
601 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
602 VkPipelineBindPoint bind_point
)
604 struct radv_descriptor_state
*descriptors_state
=
605 radv_get_descriptors_state(cmd_buffer
, bind_point
);
606 struct radv_device
*device
= cmd_buffer
->device
;
607 uint32_t data
[MAX_SETS
* 2] = {};
610 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
612 for_each_bit(i
, descriptors_state
->valid
) {
613 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
614 data
[i
* 2] = (uint64_t)(uintptr_t)set
;
615 data
[i
* 2 + 1] = (uint64_t)(uintptr_t)set
>> 32;
618 radv_emit_write_data_packet(cmd_buffer
, va
, MAX_SETS
* 2, data
);
621 struct radv_userdata_info
*
622 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
623 gl_shader_stage stage
,
626 struct radv_shader_variant
*shader
= radv_get_shader(pipeline
, stage
);
627 return &shader
->info
.user_sgprs_locs
.shader_data
[idx
];
631 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
632 struct radv_pipeline
*pipeline
,
633 gl_shader_stage stage
,
634 int idx
, uint64_t va
)
636 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
637 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
638 if (loc
->sgpr_idx
== -1)
641 assert(loc
->num_sgprs
== 1);
643 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
644 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
648 radv_emit_descriptor_pointers(struct radv_cmd_buffer
*cmd_buffer
,
649 struct radv_pipeline
*pipeline
,
650 struct radv_descriptor_state
*descriptors_state
,
651 gl_shader_stage stage
)
653 struct radv_device
*device
= cmd_buffer
->device
;
654 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
655 uint32_t sh_base
= pipeline
->user_data_0
[stage
];
656 struct radv_userdata_locations
*locs
=
657 &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
;
658 unsigned mask
= locs
->descriptor_sets_enabled
;
660 mask
&= descriptors_state
->dirty
& descriptors_state
->valid
;
665 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
667 struct radv_userdata_info
*loc
= &locs
->descriptor_sets
[start
];
668 unsigned sh_offset
= sh_base
+ loc
->sgpr_idx
* 4;
670 radv_emit_shader_pointer_head(cs
, sh_offset
, count
, true);
671 for (int i
= 0; i
< count
; i
++) {
672 struct radv_descriptor_set
*set
=
673 descriptors_state
->sets
[start
+ i
];
675 radv_emit_shader_pointer_body(device
, cs
, set
->va
, true);
681 * Convert the user sample locations to hardware sample locations (the values
682 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
685 radv_convert_user_sample_locs(struct radv_sample_locations_state
*state
,
686 uint32_t x
, uint32_t y
, VkOffset2D
*sample_locs
)
688 uint32_t x_offset
= x
% state
->grid_size
.width
;
689 uint32_t y_offset
= y
% state
->grid_size
.height
;
690 uint32_t num_samples
= (uint32_t)state
->per_pixel
;
691 VkSampleLocationEXT
*user_locs
;
692 uint32_t pixel_offset
;
694 pixel_offset
= (x_offset
+ y_offset
* state
->grid_size
.width
) * num_samples
;
696 assert(pixel_offset
<= MAX_SAMPLE_LOCATIONS
);
697 user_locs
= &state
->locations
[pixel_offset
];
699 for (uint32_t i
= 0; i
< num_samples
; i
++) {
700 float shifted_pos_x
= user_locs
[i
].x
- 0.5;
701 float shifted_pos_y
= user_locs
[i
].y
- 0.5;
703 int32_t scaled_pos_x
= floorf(shifted_pos_x
* 16);
704 int32_t scaled_pos_y
= floorf(shifted_pos_y
* 16);
706 sample_locs
[i
].x
= CLAMP(scaled_pos_x
, -8, 7);
707 sample_locs
[i
].y
= CLAMP(scaled_pos_y
, -8, 7);
712 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
716 radv_compute_sample_locs_pixel(uint32_t num_samples
, VkOffset2D
*sample_locs
,
717 uint32_t *sample_locs_pixel
)
719 for (uint32_t i
= 0; i
< num_samples
; i
++) {
720 uint32_t sample_reg_idx
= i
/ 4;
721 uint32_t sample_loc_idx
= i
% 4;
722 int32_t pos_x
= sample_locs
[i
].x
;
723 int32_t pos_y
= sample_locs
[i
].y
;
725 uint32_t shift_x
= 8 * sample_loc_idx
;
726 uint32_t shift_y
= shift_x
+ 4;
728 sample_locs_pixel
[sample_reg_idx
] |= (pos_x
& 0xf) << shift_x
;
729 sample_locs_pixel
[sample_reg_idx
] |= (pos_y
& 0xf) << shift_y
;
734 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
738 radv_compute_centroid_priority(struct radv_cmd_buffer
*cmd_buffer
,
739 VkOffset2D
*sample_locs
,
740 uint32_t num_samples
)
742 uint32_t centroid_priorities
[num_samples
];
743 uint32_t sample_mask
= num_samples
- 1;
744 uint32_t distances
[num_samples
];
745 uint64_t centroid_priority
= 0;
747 /* Compute the distances from center for each sample. */
748 for (int i
= 0; i
< num_samples
; i
++) {
749 distances
[i
] = (sample_locs
[i
].x
* sample_locs
[i
].x
) +
750 (sample_locs
[i
].y
* sample_locs
[i
].y
);
753 /* Compute the centroid priorities by looking at the distances array. */
754 for (int i
= 0; i
< num_samples
; i
++) {
755 uint32_t min_idx
= 0;
757 for (int j
= 1; j
< num_samples
; j
++) {
758 if (distances
[j
] < distances
[min_idx
])
762 centroid_priorities
[i
] = min_idx
;
763 distances
[min_idx
] = 0xffffffff;
766 /* Compute the final centroid priority. */
767 for (int i
= 0; i
< 8; i
++) {
769 centroid_priorities
[i
& sample_mask
] << (i
* 4);
772 return centroid_priority
<< 32 | centroid_priority
;
776 * Emit the sample locations that are specified with VK_EXT_sample_locations.
779 radv_emit_sample_locations(struct radv_cmd_buffer
*cmd_buffer
)
781 struct radv_sample_locations_state
*sample_location
=
782 &cmd_buffer
->state
.dynamic
.sample_location
;
783 uint32_t num_samples
= (uint32_t)sample_location
->per_pixel
;
784 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
785 uint32_t sample_locs_pixel
[4][2] = {};
786 VkOffset2D sample_locs
[4][8]; /* 8 is the max. sample count supported */
787 uint32_t max_sample_dist
= 0;
788 uint64_t centroid_priority
;
790 if (!cmd_buffer
->state
.dynamic
.sample_location
.count
)
793 /* Convert the user sample locations to hardware sample locations. */
794 radv_convert_user_sample_locs(sample_location
, 0, 0, sample_locs
[0]);
795 radv_convert_user_sample_locs(sample_location
, 1, 0, sample_locs
[1]);
796 radv_convert_user_sample_locs(sample_location
, 0, 1, sample_locs
[2]);
797 radv_convert_user_sample_locs(sample_location
, 1, 1, sample_locs
[3]);
799 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
800 for (uint32_t i
= 0; i
< 4; i
++) {
801 radv_compute_sample_locs_pixel(num_samples
, sample_locs
[i
],
802 sample_locs_pixel
[i
]);
805 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
807 radv_compute_centroid_priority(cmd_buffer
, sample_locs
[0],
810 /* Compute the maximum sample distance from the specified locations. */
811 for (unsigned i
= 0; i
< 4; ++i
) {
812 for (uint32_t j
= 0; j
< num_samples
; j
++) {
813 VkOffset2D offset
= sample_locs
[i
][j
];
814 max_sample_dist
= MAX2(max_sample_dist
,
815 MAX2(abs(offset
.x
), abs(offset
.y
)));
819 /* Emit the specified user sample locations. */
820 switch (num_samples
) {
823 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
824 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
825 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
826 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
829 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
830 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
831 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
832 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
833 radeon_set_context_reg(cs
, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
, sample_locs_pixel
[0][1]);
834 radeon_set_context_reg(cs
, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
, sample_locs_pixel
[1][1]);
835 radeon_set_context_reg(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
, sample_locs_pixel
[2][1]);
836 radeon_set_context_reg(cs
, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
, sample_locs_pixel
[3][1]);
839 unreachable("invalid number of samples");
842 /* Emit the maximum sample distance and the centroid priority. */
843 radeon_set_context_reg_rmw(cs
, R_028BE0_PA_SC_AA_CONFIG
,
844 S_028BE0_MAX_SAMPLE_DIST(max_sample_dist
),
845 ~C_028BE0_MAX_SAMPLE_DIST
);
847 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
848 radeon_emit(cs
, centroid_priority
);
849 radeon_emit(cs
, centroid_priority
>> 32);
851 /* GFX9: Flush DFSM when the AA mode changes. */
852 if (cmd_buffer
->device
->dfsm_allowed
) {
853 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
854 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
857 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
861 radv_emit_inline_push_consts(struct radv_cmd_buffer
*cmd_buffer
,
862 struct radv_pipeline
*pipeline
,
863 gl_shader_stage stage
,
864 int idx
, int count
, uint32_t *values
)
866 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
867 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
868 if (loc
->sgpr_idx
== -1)
871 assert(loc
->num_sgprs
== count
);
873 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, count
);
874 radeon_emit_array(cmd_buffer
->cs
, values
, count
);
878 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
879 struct radv_pipeline
*pipeline
)
881 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
882 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
884 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.needs_sample_positions
)
885 cmd_buffer
->sample_positions_needed
= true;
887 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
890 radv_emit_default_sample_locations(cmd_buffer
->cs
, num_samples
);
892 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
896 radv_update_binning_state(struct radv_cmd_buffer
*cmd_buffer
,
897 struct radv_pipeline
*pipeline
)
899 const struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
902 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
906 old_pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
== pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
&&
907 old_pipeline
->graphics
.binning
.db_dfsm_control
== pipeline
->graphics
.binning
.db_dfsm_control
)
910 bool binning_flush
= false;
911 if (cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_VEGA12
||
912 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_VEGA20
||
913 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_RAVEN2
||
914 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
915 binning_flush
= !old_pipeline
||
916 G_028C44_BINNING_MODE(old_pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
) !=
917 G_028C44_BINNING_MODE(pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
);
920 radeon_set_context_reg(cmd_buffer
->cs
, R_028C44_PA_SC_BINNER_CNTL_0
,
921 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
|
922 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush
));
924 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
925 radeon_set_context_reg(cmd_buffer
->cs
, R_028038_DB_DFSM_CONTROL
,
926 pipeline
->graphics
.binning
.db_dfsm_control
);
928 radeon_set_context_reg(cmd_buffer
->cs
, R_028060_DB_DFSM_CONTROL
,
929 pipeline
->graphics
.binning
.db_dfsm_control
);
932 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
937 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
938 struct radv_shader_variant
*shader
)
945 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
947 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
951 radv_emit_prefetch_L2(struct radv_cmd_buffer
*cmd_buffer
,
952 struct radv_pipeline
*pipeline
,
953 bool vertex_stage_only
)
955 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
956 uint32_t mask
= state
->prefetch_L2_mask
;
958 if (vertex_stage_only
) {
959 /* Fast prefetch path for starting draws as soon as possible.
961 mask
= state
->prefetch_L2_mask
& (RADV_PREFETCH_VS
|
962 RADV_PREFETCH_VBO_DESCRIPTORS
);
965 if (mask
& RADV_PREFETCH_VS
)
966 radv_emit_shader_prefetch(cmd_buffer
,
967 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
969 if (mask
& RADV_PREFETCH_VBO_DESCRIPTORS
)
970 si_cp_dma_prefetch(cmd_buffer
, state
->vb_va
, state
->vb_size
);
972 if (mask
& RADV_PREFETCH_TCS
)
973 radv_emit_shader_prefetch(cmd_buffer
,
974 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
976 if (mask
& RADV_PREFETCH_TES
)
977 radv_emit_shader_prefetch(cmd_buffer
,
978 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
980 if (mask
& RADV_PREFETCH_GS
) {
981 radv_emit_shader_prefetch(cmd_buffer
,
982 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
983 if (radv_pipeline_has_gs_copy_shader(pipeline
))
984 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
987 if (mask
& RADV_PREFETCH_PS
)
988 radv_emit_shader_prefetch(cmd_buffer
,
989 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
991 state
->prefetch_L2_mask
&= ~mask
;
995 radv_emit_rbplus_state(struct radv_cmd_buffer
*cmd_buffer
)
997 if (!cmd_buffer
->device
->physical_device
->rad_info
.rbplus_allowed
)
1000 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1001 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1003 unsigned sx_ps_downconvert
= 0;
1004 unsigned sx_blend_opt_epsilon
= 0;
1005 unsigned sx_blend_opt_control
= 0;
1007 if (!cmd_buffer
->state
.attachments
|| !subpass
)
1010 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1011 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1012 /* We don't set the DISABLE bits, because the HW can't have holes,
1013 * so the SPI color format is set to 32-bit 1-component. */
1014 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
1018 int idx
= subpass
->color_attachments
[i
].attachment
;
1019 struct radv_color_buffer_info
*cb
= &cmd_buffer
->state
.attachments
[idx
].cb
;
1021 unsigned format
= G_028C70_FORMAT(cb
->cb_color_info
);
1022 unsigned swap
= G_028C70_COMP_SWAP(cb
->cb_color_info
);
1023 uint32_t spi_format
= (pipeline
->graphics
.col_format
>> (i
* 4)) & 0xf;
1024 uint32_t colormask
= (pipeline
->graphics
.cb_target_mask
>> (i
* 4)) & 0xf;
1026 bool has_alpha
, has_rgb
;
1028 /* Set if RGB and A are present. */
1029 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(cb
->cb_color_attrib
);
1031 if (format
== V_028C70_COLOR_8
||
1032 format
== V_028C70_COLOR_16
||
1033 format
== V_028C70_COLOR_32
)
1034 has_rgb
= !has_alpha
;
1038 /* Check the colormask and export format. */
1039 if (!(colormask
& 0x7))
1041 if (!(colormask
& 0x8))
1044 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
1049 /* Disable value checking for disabled channels. */
1051 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1053 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1055 /* Enable down-conversion for 32bpp and smaller formats. */
1057 case V_028C70_COLOR_8
:
1058 case V_028C70_COLOR_8_8
:
1059 case V_028C70_COLOR_8_8_8_8
:
1060 /* For 1 and 2-channel formats, use the superset thereof. */
1061 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
1062 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1063 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1064 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
1065 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
1069 case V_028C70_COLOR_5_6_5
:
1070 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1071 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
1072 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
1076 case V_028C70_COLOR_1_5_5_5
:
1077 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1078 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
1079 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
1083 case V_028C70_COLOR_4_4_4_4
:
1084 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1085 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
1086 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
1090 case V_028C70_COLOR_32
:
1091 if (swap
== V_028C70_SWAP_STD
&&
1092 spi_format
== V_028714_SPI_SHADER_32_R
)
1093 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
1094 else if (swap
== V_028C70_SWAP_ALT_REV
&&
1095 spi_format
== V_028714_SPI_SHADER_32_AR
)
1096 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
1099 case V_028C70_COLOR_16
:
1100 case V_028C70_COLOR_16_16
:
1101 /* For 1-channel formats, use the superset thereof. */
1102 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
1103 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
1104 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1105 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1106 if (swap
== V_028C70_SWAP_STD
||
1107 swap
== V_028C70_SWAP_STD_REV
)
1108 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
1110 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
1114 case V_028C70_COLOR_10_11_11
:
1115 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1116 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
1117 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
1121 case V_028C70_COLOR_2_10_10_10
:
1122 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1123 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
1124 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
1130 /* Do not set the DISABLE bits for the unused attachments, as that
1131 * breaks dual source blending in SkQP and does not seem to improve
1134 if (sx_ps_downconvert
== cmd_buffer
->state
.last_sx_ps_downconvert
&&
1135 sx_blend_opt_epsilon
== cmd_buffer
->state
.last_sx_blend_opt_epsilon
&&
1136 sx_blend_opt_control
== cmd_buffer
->state
.last_sx_blend_opt_control
)
1139 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
1140 radeon_emit(cmd_buffer
->cs
, sx_ps_downconvert
);
1141 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_epsilon
);
1142 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_control
);
1144 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1146 cmd_buffer
->state
.last_sx_ps_downconvert
= sx_ps_downconvert
;
1147 cmd_buffer
->state
.last_sx_blend_opt_epsilon
= sx_blend_opt_epsilon
;
1148 cmd_buffer
->state
.last_sx_blend_opt_control
= sx_blend_opt_control
;
1152 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer
*cmd_buffer
)
1154 if (!cmd_buffer
->device
->pbb_allowed
)
1157 struct radv_binning_settings settings
=
1158 radv_get_binning_settings(cmd_buffer
->device
->physical_device
);
1159 bool break_for_new_ps
=
1160 (!cmd_buffer
->state
.emitted_pipeline
||
1161 cmd_buffer
->state
.emitted_pipeline
->shaders
[MESA_SHADER_FRAGMENT
] !=
1162 cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) &&
1163 (settings
.context_states_per_bin
> 1 ||
1164 settings
.persistent_states_per_bin
> 1);
1165 bool break_for_new_cb_target_mask
=
1166 (!cmd_buffer
->state
.emitted_pipeline
||
1167 cmd_buffer
->state
.emitted_pipeline
->graphics
.cb_target_mask
!=
1168 cmd_buffer
->state
.pipeline
->graphics
.cb_target_mask
) &&
1169 settings
.context_states_per_bin
> 1;
1171 if (!break_for_new_ps
&& !break_for_new_cb_target_mask
)
1174 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1175 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1179 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
1181 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1183 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
1186 radv_update_multisample_state(cmd_buffer
, pipeline
);
1187 radv_update_binning_state(cmd_buffer
, pipeline
);
1189 cmd_buffer
->scratch_size_per_wave_needed
= MAX2(cmd_buffer
->scratch_size_per_wave_needed
,
1190 pipeline
->scratch_bytes_per_wave
);
1191 cmd_buffer
->scratch_waves_wanted
= MAX2(cmd_buffer
->scratch_waves_wanted
,
1192 pipeline
->max_waves
);
1194 if (!cmd_buffer
->state
.emitted_pipeline
||
1195 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
1196 pipeline
->graphics
.can_use_guardband
)
1197 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
1199 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
1201 if (!cmd_buffer
->state
.emitted_pipeline
||
1202 cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.cdw
!= pipeline
->ctx_cs
.cdw
||
1203 cmd_buffer
->state
.emitted_pipeline
->ctx_cs_hash
!= pipeline
->ctx_cs_hash
||
1204 memcmp(cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.buf
,
1205 pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
* 4)) {
1206 radeon_emit_array(cmd_buffer
->cs
, pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
);
1207 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1210 radv_emit_batch_break_on_new_ps(cmd_buffer
);
1212 for (unsigned i
= 0; i
< MESA_SHADER_COMPUTE
; i
++) {
1213 if (!pipeline
->shaders
[i
])
1216 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1217 pipeline
->shaders
[i
]->bo
);
1220 if (radv_pipeline_has_gs_copy_shader(pipeline
))
1221 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1222 pipeline
->gs_copy_shader
->bo
);
1224 if (unlikely(cmd_buffer
->device
->trace_bo
))
1225 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
1227 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
1229 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
1233 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
1235 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
1236 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
1240 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
1242 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
1244 si_write_scissors(cmd_buffer
->cs
, 0, count
,
1245 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
1246 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
1247 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
1249 cmd_buffer
->state
.context_roll_without_scissor_emitted
= false;
1253 radv_emit_discard_rectangle(struct radv_cmd_buffer
*cmd_buffer
)
1255 if (!cmd_buffer
->state
.dynamic
.discard_rectangle
.count
)
1258 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028210_PA_SC_CLIPRECT_0_TL
,
1259 cmd_buffer
->state
.dynamic
.discard_rectangle
.count
* 2);
1260 for (unsigned i
= 0; i
< cmd_buffer
->state
.dynamic
.discard_rectangle
.count
; ++i
) {
1261 VkRect2D rect
= cmd_buffer
->state
.dynamic
.discard_rectangle
.rectangles
[i
];
1262 radeon_emit(cmd_buffer
->cs
, S_028210_TL_X(rect
.offset
.x
) | S_028210_TL_Y(rect
.offset
.y
));
1263 radeon_emit(cmd_buffer
->cs
, S_028214_BR_X(rect
.offset
.x
+ rect
.extent
.width
) |
1264 S_028214_BR_Y(rect
.offset
.y
+ rect
.extent
.height
));
1269 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
1271 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1273 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1274 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
1278 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
1280 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1282 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1283 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
1287 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
1289 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1291 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1292 R_028430_DB_STENCILREFMASK
, 2);
1293 radeon_emit(cmd_buffer
->cs
,
1294 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1295 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1296 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1297 S_028430_STENCILOPVAL(1));
1298 radeon_emit(cmd_buffer
->cs
,
1299 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1300 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1301 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1302 S_028434_STENCILOPVAL_BF(1));
1306 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
1308 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1310 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
1311 fui(d
->depth_bounds
.min
));
1312 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
1313 fui(d
->depth_bounds
.max
));
1317 radv_emit_depth_bias(struct radv_cmd_buffer
*cmd_buffer
)
1319 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1320 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1321 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1324 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1325 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1326 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1327 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1328 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1329 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1330 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1334 radv_emit_line_stipple(struct radv_cmd_buffer
*cmd_buffer
)
1336 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1337 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1338 uint32_t auto_reset_cntl
= 1;
1340 if (pipeline
->graphics
.topology
== VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
)
1341 auto_reset_cntl
= 2;
1343 radeon_set_context_reg(cmd_buffer
->cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1344 S_028A0C_LINE_PATTERN(d
->line_stipple
.pattern
) |
1345 S_028A0C_REPEAT_COUNT(d
->line_stipple
.factor
- 1) |
1346 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl
));
1350 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1352 struct radv_color_buffer_info
*cb
,
1353 struct radv_image_view
*iview
,
1354 VkImageLayout layout
,
1355 bool in_render_loop
)
1357 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
;
1358 uint32_t cb_color_info
= cb
->cb_color_info
;
1359 struct radv_image
*image
= iview
->image
;
1361 if (!radv_layout_dcc_compressed(cmd_buffer
->device
, image
, layout
, in_render_loop
,
1362 radv_image_queue_family_mask(image
,
1363 cmd_buffer
->queue_family_index
,
1364 cmd_buffer
->queue_family_index
))) {
1365 cb_color_info
&= C_028C70_DCC_ENABLE
;
1368 if (radv_image_is_tc_compat_cmask(image
) &&
1369 (radv_is_fmask_decompress_pipeline(cmd_buffer
) ||
1370 radv_is_dcc_decompress_pipeline(cmd_buffer
))) {
1371 /* If this bit is set, the FMASK decompression operation
1372 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1374 cb_color_info
&= C_028C70_FMASK_COMPRESS_1FRAG_ONLY
;
1377 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1378 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1379 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1380 radeon_emit(cmd_buffer
->cs
, 0);
1381 radeon_emit(cmd_buffer
->cs
, 0);
1382 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1383 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1384 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1385 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1386 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1387 radeon_emit(cmd_buffer
->cs
, 0);
1388 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1389 radeon_emit(cmd_buffer
->cs
, 0);
1391 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 1);
1392 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1394 radeon_set_context_reg(cmd_buffer
->cs
, R_028E40_CB_COLOR0_BASE_EXT
+ index
* 4,
1395 cb
->cb_color_base
>> 32);
1396 radeon_set_context_reg(cmd_buffer
->cs
, R_028E60_CB_COLOR0_CMASK_BASE_EXT
+ index
* 4,
1397 cb
->cb_color_cmask
>> 32);
1398 radeon_set_context_reg(cmd_buffer
->cs
, R_028E80_CB_COLOR0_FMASK_BASE_EXT
+ index
* 4,
1399 cb
->cb_color_fmask
>> 32);
1400 radeon_set_context_reg(cmd_buffer
->cs
, R_028EA0_CB_COLOR0_DCC_BASE_EXT
+ index
* 4,
1401 cb
->cb_dcc_base
>> 32);
1402 radeon_set_context_reg(cmd_buffer
->cs
, R_028EC0_CB_COLOR0_ATTRIB2
+ index
* 4,
1403 cb
->cb_color_attrib2
);
1404 radeon_set_context_reg(cmd_buffer
->cs
, R_028EE0_CB_COLOR0_ATTRIB3
+ index
* 4,
1405 cb
->cb_color_attrib3
);
1406 } else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1407 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1408 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1409 radeon_emit(cmd_buffer
->cs
, S_028C64_BASE_256B(cb
->cb_color_base
>> 32));
1410 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1411 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1412 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1413 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1414 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1415 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1416 radeon_emit(cmd_buffer
->cs
, S_028C80_BASE_256B(cb
->cb_color_cmask
>> 32));
1417 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1418 radeon_emit(cmd_buffer
->cs
, S_028C88_BASE_256B(cb
->cb_color_fmask
>> 32));
1420 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1421 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1422 radeon_emit(cmd_buffer
->cs
, S_028C98_BASE_256B(cb
->cb_dcc_base
>> 32));
1424 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1427 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1428 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1429 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1430 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1431 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1432 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1433 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1434 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1435 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1436 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1437 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1438 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1440 if (is_vi
) { /* DCC BASE */
1441 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1445 if (radv_dcc_enabled(image
, iview
->base_mip
)) {
1446 /* Drawing with DCC enabled also compresses colorbuffers. */
1447 VkImageSubresourceRange range
= {
1448 .aspectMask
= iview
->aspect_mask
,
1449 .baseMipLevel
= iview
->base_mip
,
1450 .levelCount
= iview
->level_count
,
1451 .baseArrayLayer
= iview
->base_layer
,
1452 .layerCount
= iview
->layer_count
,
1455 radv_update_dcc_metadata(cmd_buffer
, image
, &range
, true);
1460 radv_update_zrange_precision(struct radv_cmd_buffer
*cmd_buffer
,
1461 struct radv_ds_buffer_info
*ds
,
1462 const struct radv_image_view
*iview
,
1463 VkImageLayout layout
,
1464 bool in_render_loop
, bool requires_cond_exec
)
1466 const struct radv_image
*image
= iview
->image
;
1467 uint32_t db_z_info
= ds
->db_z_info
;
1468 uint32_t db_z_info_reg
;
1470 if (!cmd_buffer
->device
->physical_device
->rad_info
.has_tc_compat_zrange_bug
||
1471 !radv_image_is_tc_compat_htile(image
))
1474 if (!radv_layout_is_htile_compressed(image
, layout
, in_render_loop
,
1475 radv_image_queue_family_mask(image
,
1476 cmd_buffer
->queue_family_index
,
1477 cmd_buffer
->queue_family_index
))) {
1478 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1481 db_z_info
&= C_028040_ZRANGE_PRECISION
;
1483 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1484 db_z_info_reg
= R_028038_DB_Z_INFO
;
1486 db_z_info_reg
= R_028040_DB_Z_INFO
;
1489 /* When we don't know the last fast clear value we need to emit a
1490 * conditional packet that will eventually skip the following
1491 * SET_CONTEXT_REG packet.
1493 if (requires_cond_exec
) {
1494 uint64_t va
= radv_get_tc_compat_zrange_va(image
, iview
->base_mip
);
1496 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COND_EXEC
, 3, 0));
1497 radeon_emit(cmd_buffer
->cs
, va
);
1498 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1499 radeon_emit(cmd_buffer
->cs
, 0);
1500 radeon_emit(cmd_buffer
->cs
, 3); /* SET_CONTEXT_REG size */
1503 radeon_set_context_reg(cmd_buffer
->cs
, db_z_info_reg
, db_z_info
);
1507 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1508 struct radv_ds_buffer_info
*ds
,
1509 struct radv_image_view
*iview
,
1510 VkImageLayout layout
,
1511 bool in_render_loop
)
1513 const struct radv_image
*image
= iview
->image
;
1514 uint32_t db_z_info
= ds
->db_z_info
;
1515 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1517 if (!radv_layout_is_htile_compressed(image
, layout
, in_render_loop
,
1518 radv_image_queue_family_mask(image
,
1519 cmd_buffer
->queue_family_index
,
1520 cmd_buffer
->queue_family_index
))) {
1521 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1522 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1525 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1526 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1528 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1529 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1530 radeon_set_context_reg(cmd_buffer
->cs
, R_02801C_DB_DEPTH_SIZE_XY
, ds
->db_depth_size
);
1532 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 7);
1533 radeon_emit(cmd_buffer
->cs
, S_02803C_RESOURCE_LEVEL(1));
1534 radeon_emit(cmd_buffer
->cs
, db_z_info
);
1535 radeon_emit(cmd_buffer
->cs
, db_stencil_info
);
1536 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
);
1537 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
);
1538 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
);
1539 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
);
1541 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_READ_BASE_HI
, 5);
1542 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32);
1543 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32);
1544 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32);
1545 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32);
1546 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
>> 32);
1547 } else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1548 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1549 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1550 radeon_emit(cmd_buffer
->cs
, S_028018_BASE_HI(ds
->db_htile_data_base
>> 32));
1551 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1553 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1554 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1555 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1556 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1557 radeon_emit(cmd_buffer
->cs
, S_028044_BASE_HI(ds
->db_z_read_base
>> 32)); /* DB_Z_READ_BASE_HI */
1558 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1559 radeon_emit(cmd_buffer
->cs
, S_02804C_BASE_HI(ds
->db_stencil_read_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
1560 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1561 radeon_emit(cmd_buffer
->cs
, S_028054_BASE_HI(ds
->db_z_write_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
1562 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1563 radeon_emit(cmd_buffer
->cs
, S_02805C_BASE_HI(ds
->db_stencil_write_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1565 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1566 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1567 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1569 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1571 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1572 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1573 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1574 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1575 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1576 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1577 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1578 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1579 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1580 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1584 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1585 radv_update_zrange_precision(cmd_buffer
, ds
, iview
, layout
,
1586 in_render_loop
, true);
1588 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1589 ds
->pa_su_poly_offset_db_fmt_cntl
);
1593 * Update the fast clear depth/stencil values if the image is bound as a
1594 * depth/stencil buffer.
1597 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer
*cmd_buffer
,
1598 const struct radv_image_view
*iview
,
1599 VkClearDepthStencilValue ds_clear_value
,
1600 VkImageAspectFlags aspects
)
1602 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1603 const struct radv_image
*image
= iview
->image
;
1604 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1607 if (!cmd_buffer
->state
.attachments
|| !subpass
)
1610 if (!subpass
->depth_stencil_attachment
)
1613 att_idx
= subpass
->depth_stencil_attachment
->attachment
;
1614 if (cmd_buffer
->state
.attachments
[att_idx
].iview
->image
!= image
)
1617 if (aspects
== (VK_IMAGE_ASPECT_DEPTH_BIT
|
1618 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
1619 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
1620 radeon_emit(cs
, ds_clear_value
.stencil
);
1621 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1622 } else if (aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1623 radeon_set_context_reg_seq(cs
, R_02802C_DB_DEPTH_CLEAR
, 1);
1624 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1626 assert(aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1627 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 1);
1628 radeon_emit(cs
, ds_clear_value
.stencil
);
1631 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1632 * only needed when clearing Z to 0.0.
1634 if ((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1635 ds_clear_value
.depth
== 0.0) {
1636 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1637 bool in_render_loop
= subpass
->depth_stencil_attachment
->in_render_loop
;
1639 radv_update_zrange_precision(cmd_buffer
, &cmd_buffer
->state
.attachments
[att_idx
].ds
,
1640 iview
, layout
, in_render_loop
, false);
1643 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1647 * Set the clear depth/stencil values to the image's metadata.
1650 radv_set_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1651 struct radv_image
*image
,
1652 const VkImageSubresourceRange
*range
,
1653 VkClearDepthStencilValue ds_clear_value
,
1654 VkImageAspectFlags aspects
)
1656 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1657 uint64_t va
= radv_get_ds_clear_value_va(image
, range
->baseMipLevel
);
1658 uint32_t level_count
= radv_get_levelCount(image
, range
);
1660 if (aspects
== (VK_IMAGE_ASPECT_DEPTH_BIT
|
1661 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
1662 /* Use the fastest way when both aspects are used. */
1663 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + 2 * level_count
, cmd_buffer
->state
.predicating
));
1664 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1665 S_370_WR_CONFIRM(1) |
1666 S_370_ENGINE_SEL(V_370_PFP
));
1667 radeon_emit(cs
, va
);
1668 radeon_emit(cs
, va
>> 32);
1670 for (uint32_t l
= 0; l
< level_count
; l
++) {
1671 radeon_emit(cs
, ds_clear_value
.stencil
);
1672 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1675 /* Otherwise we need one WRITE_DATA packet per level. */
1676 for (uint32_t l
= 0; l
< level_count
; l
++) {
1677 uint64_t va
= radv_get_ds_clear_value_va(image
, range
->baseMipLevel
+ l
);
1680 if (aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1681 value
= fui(ds_clear_value
.depth
);
1684 assert(aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1685 value
= ds_clear_value
.stencil
;
1688 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, cmd_buffer
->state
.predicating
));
1689 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1690 S_370_WR_CONFIRM(1) |
1691 S_370_ENGINE_SEL(V_370_PFP
));
1692 radeon_emit(cs
, va
);
1693 radeon_emit(cs
, va
>> 32);
1694 radeon_emit(cs
, value
);
1700 * Update the TC-compat metadata value for this image.
1703 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1704 struct radv_image
*image
,
1705 const VkImageSubresourceRange
*range
,
1708 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1710 if (!cmd_buffer
->device
->physical_device
->rad_info
.has_tc_compat_zrange_bug
)
1713 uint64_t va
= radv_get_tc_compat_zrange_va(image
, range
->baseMipLevel
);
1714 uint32_t level_count
= radv_get_levelCount(image
, range
);
1716 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + level_count
, cmd_buffer
->state
.predicating
));
1717 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1718 S_370_WR_CONFIRM(1) |
1719 S_370_ENGINE_SEL(V_370_PFP
));
1720 radeon_emit(cs
, va
);
1721 radeon_emit(cs
, va
>> 32);
1723 for (uint32_t l
= 0; l
< level_count
; l
++)
1724 radeon_emit(cs
, value
);
1728 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1729 const struct radv_image_view
*iview
,
1730 VkClearDepthStencilValue ds_clear_value
)
1732 VkImageSubresourceRange range
= {
1733 .aspectMask
= iview
->aspect_mask
,
1734 .baseMipLevel
= iview
->base_mip
,
1735 .levelCount
= iview
->level_count
,
1736 .baseArrayLayer
= iview
->base_layer
,
1737 .layerCount
= iview
->layer_count
,
1741 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1742 * depth clear value is 0.0f.
1744 cond_val
= ds_clear_value
.depth
== 0.0f
? UINT_MAX
: 0;
1746 radv_set_tc_compat_zrange_metadata(cmd_buffer
, iview
->image
, &range
,
1751 * Update the clear depth/stencil values for this image.
1754 radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1755 const struct radv_image_view
*iview
,
1756 VkClearDepthStencilValue ds_clear_value
,
1757 VkImageAspectFlags aspects
)
1759 VkImageSubresourceRange range
= {
1760 .aspectMask
= iview
->aspect_mask
,
1761 .baseMipLevel
= iview
->base_mip
,
1762 .levelCount
= iview
->level_count
,
1763 .baseArrayLayer
= iview
->base_layer
,
1764 .layerCount
= iview
->layer_count
,
1766 struct radv_image
*image
= iview
->image
;
1768 assert(radv_image_has_htile(image
));
1770 radv_set_ds_clear_metadata(cmd_buffer
, iview
->image
, &range
,
1771 ds_clear_value
, aspects
);
1773 if (radv_image_is_tc_compat_htile(image
) &&
1774 (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
1775 radv_update_tc_compat_zrange_metadata(cmd_buffer
, iview
,
1779 radv_update_bound_fast_clear_ds(cmd_buffer
, iview
, ds_clear_value
,
1784 * Load the clear depth/stencil values from the image's metadata.
1787 radv_load_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1788 const struct radv_image_view
*iview
)
1790 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1791 const struct radv_image
*image
= iview
->image
;
1792 VkImageAspectFlags aspects
= vk_format_aspects(image
->vk_format
);
1793 uint64_t va
= radv_get_ds_clear_value_va(image
, iview
->base_mip
);
1794 unsigned reg_offset
= 0, reg_count
= 0;
1796 if (!radv_image_has_htile(image
))
1799 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1805 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1808 uint32_t reg
= R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
;
1810 if (cmd_buffer
->device
->physical_device
->rad_info
.has_load_ctx_reg_pkt
) {
1811 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, 0));
1812 radeon_emit(cs
, va
);
1813 radeon_emit(cs
, va
>> 32);
1814 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1815 radeon_emit(cs
, reg_count
);
1817 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1818 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1819 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1820 (reg_count
== 2 ? COPY_DATA_COUNT_SEL
: 0));
1821 radeon_emit(cs
, va
);
1822 radeon_emit(cs
, va
>> 32);
1823 radeon_emit(cs
, reg
>> 2);
1826 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1832 * With DCC some colors don't require CMASK elimination before being
1833 * used as a texture. This sets a predicate value to determine if the
1834 * cmask eliminate is required.
1837 radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1838 struct radv_image
*image
,
1839 const VkImageSubresourceRange
*range
, bool value
)
1841 uint64_t pred_val
= value
;
1842 uint64_t va
= radv_image_get_fce_pred_va(image
, range
->baseMipLevel
);
1843 uint32_t level_count
= radv_get_levelCount(image
, range
);
1844 uint32_t count
= 2 * level_count
;
1846 assert(radv_dcc_enabled(image
, range
->baseMipLevel
));
1848 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
1849 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1850 S_370_WR_CONFIRM(1) |
1851 S_370_ENGINE_SEL(V_370_PFP
));
1852 radeon_emit(cmd_buffer
->cs
, va
);
1853 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1855 for (uint32_t l
= 0; l
< level_count
; l
++) {
1856 radeon_emit(cmd_buffer
->cs
, pred_val
);
1857 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1862 * Update the DCC predicate to reflect the compression state.
1865 radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1866 struct radv_image
*image
,
1867 const VkImageSubresourceRange
*range
, bool value
)
1869 uint64_t pred_val
= value
;
1870 uint64_t va
= radv_image_get_dcc_pred_va(image
, range
->baseMipLevel
);
1871 uint32_t level_count
= radv_get_levelCount(image
, range
);
1872 uint32_t count
= 2 * level_count
;
1874 assert(radv_dcc_enabled(image
, range
->baseMipLevel
));
1876 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
1877 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1878 S_370_WR_CONFIRM(1) |
1879 S_370_ENGINE_SEL(V_370_PFP
));
1880 radeon_emit(cmd_buffer
->cs
, va
);
1881 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1883 for (uint32_t l
= 0; l
< level_count
; l
++) {
1884 radeon_emit(cmd_buffer
->cs
, pred_val
);
1885 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1890 * Update the fast clear color values if the image is bound as a color buffer.
1893 radv_update_bound_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1894 struct radv_image
*image
,
1896 uint32_t color_values
[2])
1898 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1899 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1902 if (!cmd_buffer
->state
.attachments
|| !subpass
)
1905 att_idx
= subpass
->color_attachments
[cb_idx
].attachment
;
1906 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1909 if (cmd_buffer
->state
.attachments
[att_idx
].iview
->image
!= image
)
1912 radeon_set_context_reg_seq(cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c, 2);
1913 radeon_emit(cs
, color_values
[0]);
1914 radeon_emit(cs
, color_values
[1]);
1916 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1920 * Set the clear color values to the image's metadata.
1923 radv_set_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1924 struct radv_image
*image
,
1925 const VkImageSubresourceRange
*range
,
1926 uint32_t color_values
[2])
1928 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1929 uint64_t va
= radv_image_get_fast_clear_va(image
, range
->baseMipLevel
);
1930 uint32_t level_count
= radv_get_levelCount(image
, range
);
1931 uint32_t count
= 2 * level_count
;
1933 assert(radv_image_has_cmask(image
) ||
1934 radv_dcc_enabled(image
, range
->baseMipLevel
));
1936 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, cmd_buffer
->state
.predicating
));
1937 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1938 S_370_WR_CONFIRM(1) |
1939 S_370_ENGINE_SEL(V_370_PFP
));
1940 radeon_emit(cs
, va
);
1941 radeon_emit(cs
, va
>> 32);
1943 for (uint32_t l
= 0; l
< level_count
; l
++) {
1944 radeon_emit(cs
, color_values
[0]);
1945 radeon_emit(cs
, color_values
[1]);
1950 * Update the clear color values for this image.
1953 radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1954 const struct radv_image_view
*iview
,
1956 uint32_t color_values
[2])
1958 struct radv_image
*image
= iview
->image
;
1959 VkImageSubresourceRange range
= {
1960 .aspectMask
= iview
->aspect_mask
,
1961 .baseMipLevel
= iview
->base_mip
,
1962 .levelCount
= iview
->level_count
,
1963 .baseArrayLayer
= iview
->base_layer
,
1964 .layerCount
= iview
->layer_count
,
1967 assert(radv_image_has_cmask(image
) ||
1968 radv_dcc_enabled(image
, iview
->base_mip
));
1970 radv_set_color_clear_metadata(cmd_buffer
, image
, &range
, color_values
);
1972 radv_update_bound_fast_clear_color(cmd_buffer
, image
, cb_idx
,
1977 * Load the clear color values from the image's metadata.
1980 radv_load_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1981 struct radv_image_view
*iview
,
1984 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1985 struct radv_image
*image
= iview
->image
;
1986 uint64_t va
= radv_image_get_fast_clear_va(image
, iview
->base_mip
);
1988 if (!radv_image_has_cmask(image
) &&
1989 !radv_dcc_enabled(image
, iview
->base_mip
))
1992 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c;
1994 if (cmd_buffer
->device
->physical_device
->rad_info
.has_load_ctx_reg_pkt
) {
1995 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, cmd_buffer
->state
.predicating
));
1996 radeon_emit(cs
, va
);
1997 radeon_emit(cs
, va
>> 32);
1998 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
2001 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
2002 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
2003 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
2004 COPY_DATA_COUNT_SEL
);
2005 radeon_emit(cs
, va
);
2006 radeon_emit(cs
, va
>> 32);
2007 radeon_emit(cs
, reg
>> 2);
2010 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
2016 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
2019 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
2020 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2022 /* this may happen for inherited secondary recording */
2026 for (i
= 0; i
< 8; ++i
) {
2027 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
2028 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2029 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2033 int idx
= subpass
->color_attachments
[i
].attachment
;
2034 struct radv_image_view
*iview
= cmd_buffer
->state
.attachments
[idx
].iview
;
2035 VkImageLayout layout
= subpass
->color_attachments
[i
].layout
;
2036 bool in_render_loop
= subpass
->color_attachments
[i
].in_render_loop
;
2038 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, iview
->bo
);
2040 assert(iview
->aspect_mask
& (VK_IMAGE_ASPECT_COLOR_BIT
| VK_IMAGE_ASPECT_PLANE_0_BIT
|
2041 VK_IMAGE_ASPECT_PLANE_1_BIT
| VK_IMAGE_ASPECT_PLANE_2_BIT
));
2042 radv_emit_fb_color_state(cmd_buffer
, i
, &cmd_buffer
->state
.attachments
[idx
].cb
, iview
, layout
, in_render_loop
);
2044 radv_load_color_clear_metadata(cmd_buffer
, iview
, i
);
2047 if (subpass
->depth_stencil_attachment
) {
2048 int idx
= subpass
->depth_stencil_attachment
->attachment
;
2049 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
2050 bool in_render_loop
= subpass
->depth_stencil_attachment
->in_render_loop
;
2051 struct radv_image_view
*iview
= cmd_buffer
->state
.attachments
[idx
].iview
;
2052 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, cmd_buffer
->state
.attachments
[idx
].iview
->bo
);
2054 radv_emit_fb_ds_state(cmd_buffer
, &cmd_buffer
->state
.attachments
[idx
].ds
, iview
, layout
, in_render_loop
);
2056 if (cmd_buffer
->state
.attachments
[idx
].ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
2057 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2058 cmd_buffer
->state
.offset_scale
= cmd_buffer
->state
.attachments
[idx
].ds
.offset_scale
;
2060 radv_load_ds_clear_metadata(cmd_buffer
, iview
);
2062 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
)
2063 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
2065 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
2067 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
2068 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
2070 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
2071 S_028208_BR_X(framebuffer
->width
) |
2072 S_028208_BR_Y(framebuffer
->height
));
2074 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
) {
2075 bool disable_constant_encode
=
2076 cmd_buffer
->device
->physical_device
->rad_info
.has_dcc_constant_encode
;
2077 enum chip_class chip_class
=
2078 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
;
2079 uint8_t watermark
= chip_class
>= GFX10
? 6 : 4;
2081 radeon_set_context_reg(cmd_buffer
->cs
, R_028424_CB_DCC_CONTROL
,
2082 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class
<= GFX9
) |
2083 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
2084 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode
));
2087 if (cmd_buffer
->device
->dfsm_allowed
) {
2088 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2089 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
2092 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
2096 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
, bool indirect
)
2098 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2099 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2101 if (state
->index_type
!= state
->last_index_type
) {
2102 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2103 radeon_set_uconfig_reg_idx(cmd_buffer
->device
->physical_device
,
2104 cs
, R_03090C_VGT_INDEX_TYPE
,
2105 2, state
->index_type
);
2107 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2108 radeon_emit(cs
, state
->index_type
);
2111 state
->last_index_type
= state
->index_type
;
2114 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2115 * the index_va and max_index_count already. */
2119 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
2120 radeon_emit(cs
, state
->index_va
);
2121 radeon_emit(cs
, state
->index_va
>> 32);
2123 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
2124 radeon_emit(cs
, state
->max_index_count
);
2126 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
2129 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
2131 bool has_perfect_queries
= cmd_buffer
->state
.perfect_occlusion_queries_enabled
;
2132 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2133 uint32_t pa_sc_mode_cntl_1
=
2134 pipeline
? pipeline
->graphics
.ms
.pa_sc_mode_cntl_1
: 0;
2135 uint32_t db_count_control
;
2137 if(!cmd_buffer
->state
.active_occlusion_queries
) {
2138 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2139 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
2140 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
2141 has_perfect_queries
) {
2142 /* Re-enable out-of-order rasterization if the
2143 * bound pipeline supports it and if it's has
2144 * been disabled before starting any perfect
2145 * occlusion queries.
2147 radeon_set_context_reg(cmd_buffer
->cs
,
2148 R_028A4C_PA_SC_MODE_CNTL_1
,
2152 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
2154 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2155 uint32_t sample_rate
= subpass
? util_logbase2(subpass
->max_sample_count
) : 0;
2156 bool gfx10_perfect
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& has_perfect_queries
;
2158 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2160 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries
) |
2161 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect
) |
2162 S_028004_SAMPLE_RATE(sample_rate
) |
2163 S_028004_ZPASS_ENABLE(1) |
2164 S_028004_SLICE_EVEN_ENABLE(1) |
2165 S_028004_SLICE_ODD_ENABLE(1);
2167 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
2168 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
2169 has_perfect_queries
) {
2170 /* If the bound pipeline has enabled
2171 * out-of-order rasterization, we should
2172 * disable it before starting any perfect
2173 * occlusion queries.
2175 pa_sc_mode_cntl_1
&= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE
;
2177 radeon_set_context_reg(cmd_buffer
->cs
,
2178 R_028A4C_PA_SC_MODE_CNTL_1
,
2182 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
2183 S_028004_SAMPLE_RATE(sample_rate
);
2187 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
2189 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
2193 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
2195 uint32_t states
= cmd_buffer
->state
.dirty
& cmd_buffer
->state
.emitted_pipeline
->graphics
.needed_dynamic_state
;
2197 if (states
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
2198 radv_emit_viewport(cmd_buffer
);
2200 if (states
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
2201 !cmd_buffer
->device
->physical_device
->rad_info
.has_gfx9_scissor_bug
)
2202 radv_emit_scissor(cmd_buffer
);
2204 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
2205 radv_emit_line_width(cmd_buffer
);
2207 if (states
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
2208 radv_emit_blend_constants(cmd_buffer
);
2210 if (states
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
2211 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
2212 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
2213 radv_emit_stencil(cmd_buffer
);
2215 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
2216 radv_emit_depth_bounds(cmd_buffer
);
2218 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)
2219 radv_emit_depth_bias(cmd_buffer
);
2221 if (states
& RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
)
2222 radv_emit_discard_rectangle(cmd_buffer
);
2224 if (states
& RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
)
2225 radv_emit_sample_locations(cmd_buffer
);
2227 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
)
2228 radv_emit_line_stipple(cmd_buffer
);
2230 cmd_buffer
->state
.dirty
&= ~states
;
2234 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2235 VkPipelineBindPoint bind_point
)
2237 struct radv_descriptor_state
*descriptors_state
=
2238 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2239 struct radv_descriptor_set
*set
= &descriptors_state
->push_set
.set
;
2242 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
2247 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2248 set
->va
+= bo_offset
;
2252 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
,
2253 VkPipelineBindPoint bind_point
)
2255 struct radv_descriptor_state
*descriptors_state
=
2256 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2257 uint32_t size
= MAX_SETS
* 4;
2261 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
2262 256, &offset
, &ptr
))
2265 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
2266 uint32_t *uptr
= ((uint32_t *)ptr
) + i
;
2267 uint64_t set_va
= 0;
2268 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
2269 if (descriptors_state
->valid
& (1u << i
))
2271 uptr
[0] = set_va
& 0xffffffff;
2274 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2277 if (cmd_buffer
->state
.pipeline
) {
2278 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
2279 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2280 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2282 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
2283 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
2284 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2286 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
2287 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2288 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2290 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2291 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
2292 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2294 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2295 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
2296 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2299 if (cmd_buffer
->state
.compute_pipeline
)
2300 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
2301 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2305 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2306 VkShaderStageFlags stages
)
2308 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2309 VK_PIPELINE_BIND_POINT_COMPUTE
:
2310 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2311 struct radv_descriptor_state
*descriptors_state
=
2312 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2313 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2314 bool flush_indirect_descriptors
;
2316 if (!descriptors_state
->dirty
)
2319 if (descriptors_state
->push_dirty
)
2320 radv_flush_push_descriptors(cmd_buffer
, bind_point
);
2322 flush_indirect_descriptors
=
2323 (bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
&&
2324 state
->pipeline
&& state
->pipeline
->need_indirect_descriptor_sets
) ||
2325 (bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
&&
2326 state
->compute_pipeline
&& state
->compute_pipeline
->need_indirect_descriptor_sets
);
2328 if (flush_indirect_descriptors
)
2329 radv_flush_indirect_descriptor_sets(cmd_buffer
, bind_point
);
2331 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2333 MAX_SETS
* MESA_SHADER_STAGES
* 4);
2335 if (cmd_buffer
->state
.pipeline
) {
2336 radv_foreach_stage(stage
, stages
) {
2337 if (!cmd_buffer
->state
.pipeline
->shaders
[stage
])
2340 radv_emit_descriptor_pointers(cmd_buffer
,
2341 cmd_buffer
->state
.pipeline
,
2342 descriptors_state
, stage
);
2346 if (cmd_buffer
->state
.compute_pipeline
&&
2347 (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)) {
2348 radv_emit_descriptor_pointers(cmd_buffer
,
2349 cmd_buffer
->state
.compute_pipeline
,
2351 MESA_SHADER_COMPUTE
);
2354 descriptors_state
->dirty
= 0;
2355 descriptors_state
->push_dirty
= false;
2357 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2359 if (unlikely(cmd_buffer
->device
->trace_bo
))
2360 radv_save_descriptors(cmd_buffer
, bind_point
);
2364 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
2365 VkShaderStageFlags stages
)
2367 struct radv_pipeline
*pipeline
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
2368 ? cmd_buffer
->state
.compute_pipeline
2369 : cmd_buffer
->state
.pipeline
;
2370 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2371 VK_PIPELINE_BIND_POINT_COMPUTE
:
2372 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2373 struct radv_descriptor_state
*descriptors_state
=
2374 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2375 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
2376 struct radv_shader_variant
*shader
, *prev_shader
;
2377 bool need_push_constants
= false;
2382 stages
&= cmd_buffer
->push_constant_stages
;
2384 (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
2387 radv_foreach_stage(stage
, stages
) {
2388 shader
= radv_get_shader(pipeline
, stage
);
2392 need_push_constants
|= shader
->info
.loads_push_constants
;
2393 need_push_constants
|= shader
->info
.loads_dynamic_offsets
;
2395 uint8_t base
= shader
->info
.base_inline_push_consts
;
2396 uint8_t count
= shader
->info
.num_inline_push_consts
;
2398 radv_emit_inline_push_consts(cmd_buffer
, pipeline
, stage
,
2399 AC_UD_INLINE_PUSH_CONSTANTS
,
2401 (uint32_t *)&cmd_buffer
->push_constants
[base
* 4]);
2404 if (need_push_constants
) {
2405 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
2406 16 * layout
->dynamic_offset_count
,
2407 256, &offset
, &ptr
))
2410 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
2411 memcpy((char*)ptr
+ layout
->push_constant_size
,
2412 descriptors_state
->dynamic_buffers
,
2413 16 * layout
->dynamic_offset_count
);
2415 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2418 ASSERTED
unsigned cdw_max
=
2419 radeon_check_space(cmd_buffer
->device
->ws
,
2420 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
2423 radv_foreach_stage(stage
, stages
) {
2424 shader
= radv_get_shader(pipeline
, stage
);
2426 /* Avoid redundantly emitting the address for merged stages. */
2427 if (shader
&& shader
!= prev_shader
) {
2428 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
2429 AC_UD_PUSH_CONSTANTS
, va
);
2431 prev_shader
= shader
;
2434 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2437 cmd_buffer
->push_constant_stages
&= ~stages
;
2441 radv_flush_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2442 bool pipeline_is_dirty
)
2444 if ((pipeline_is_dirty
||
2445 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_VERTEX_BUFFER
)) &&
2446 cmd_buffer
->state
.pipeline
->num_vertex_bindings
&&
2447 radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.has_vertex_buffers
) {
2451 uint32_t count
= cmd_buffer
->state
.pipeline
->num_vertex_bindings
;
2454 /* allocate some descriptor state for vertex buffers */
2455 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
2456 &vb_offset
, &vb_ptr
))
2459 for (i
= 0; i
< count
; i
++) {
2460 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
2462 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[i
].buffer
;
2463 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[i
];
2464 unsigned num_records
;
2469 va
= radv_buffer_get_va(buffer
->bo
);
2471 offset
= cmd_buffer
->vertex_bindings
[i
].offset
;
2472 va
+= offset
+ buffer
->offset
;
2474 num_records
= buffer
->size
- offset
;
2475 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
!= GFX8
&& stride
)
2476 num_records
/= stride
;
2479 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
2480 desc
[2] = num_records
;
2481 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2482 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2483 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2484 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2486 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2487 /* OOB_SELECT chooses the out-of-bounds check:
2488 * - 1: index >= NUM_RECORDS (Structured)
2489 * - 3: offset >= NUM_RECORDS (Raw)
2491 int oob_select
= stride
? V_008F0C_OOB_SELECT_STRUCTURED
: V_008F0C_OOB_SELECT_RAW
;
2493 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT
) |
2494 S_008F0C_OOB_SELECT(oob_select
) |
2495 S_008F0C_RESOURCE_LEVEL(1);
2497 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT
) |
2498 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2502 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2505 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2506 AC_UD_VS_VERTEX_BUFFERS
, va
);
2508 cmd_buffer
->state
.vb_va
= va
;
2509 cmd_buffer
->state
.vb_size
= count
* 16;
2510 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_VBO_DESCRIPTORS
;
2512 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_VERTEX_BUFFER
;
2516 radv_emit_streamout_buffers(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
)
2518 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2519 struct radv_userdata_info
*loc
;
2522 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
2523 if (!radv_get_shader(pipeline
, stage
))
2526 loc
= radv_lookup_user_sgpr(pipeline
, stage
,
2527 AC_UD_STREAMOUT_BUFFERS
);
2528 if (loc
->sgpr_idx
== -1)
2531 base_reg
= pipeline
->user_data_0
[stage
];
2533 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2534 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2537 if (radv_pipeline_has_gs_copy_shader(pipeline
)) {
2538 loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_STREAMOUT_BUFFERS
];
2539 if (loc
->sgpr_idx
!= -1) {
2540 base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2542 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2543 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2549 radv_flush_streamout_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
2551 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_STREAMOUT_BUFFER
) {
2552 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
2553 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
2558 /* Allocate some descriptor state for streamout buffers. */
2559 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
,
2560 MAX_SO_BUFFERS
* 16, 256,
2561 &so_offset
, &so_ptr
))
2564 for (uint32_t i
= 0; i
< MAX_SO_BUFFERS
; i
++) {
2565 struct radv_buffer
*buffer
= sb
[i
].buffer
;
2566 uint32_t *desc
= &((uint32_t *)so_ptr
)[i
* 4];
2568 if (!(so
->enabled_mask
& (1 << i
)))
2571 va
= radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
2575 /* Set the descriptor.
2577 * On GFX8, the format must be non-INVALID, otherwise
2578 * the buffer will be considered not bound and store
2579 * instructions will be no-ops.
2581 uint32_t size
= 0xffffffff;
2583 /* Compute the correct buffer size for NGG streamout
2584 * because it's used to determine the max emit per
2587 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
)
2588 size
= buffer
->size
- sb
[i
].offset
;
2591 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2593 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2594 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2595 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2596 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2598 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2599 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2600 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
2601 S_008F0C_RESOURCE_LEVEL(1);
2603 desc
[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2607 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2610 radv_emit_streamout_buffers(cmd_buffer
, va
);
2613 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
2617 radv_flush_ngg_gs_state(struct radv_cmd_buffer
*cmd_buffer
)
2619 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2620 struct radv_userdata_info
*loc
;
2621 uint32_t ngg_gs_state
= 0;
2624 if (!radv_pipeline_has_gs(pipeline
) ||
2625 !radv_pipeline_has_ngg(pipeline
))
2628 /* By default NGG GS queries are disabled but they are enabled if the
2629 * command buffer has active GDS queries or if it's a secondary command
2630 * buffer that inherits the number of generated primitives.
2632 if (cmd_buffer
->state
.active_pipeline_gds_queries
||
2633 (cmd_buffer
->state
.inherited_pipeline_statistics
& VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT
))
2636 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_GEOMETRY
,
2637 AC_UD_NGG_GS_STATE
);
2638 base_reg
= pipeline
->user_data_0
[MESA_SHADER_GEOMETRY
];
2639 assert(loc
->sgpr_idx
!= -1);
2641 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
2646 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
2648 radv_flush_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
);
2649 radv_flush_streamout_descriptors(cmd_buffer
);
2650 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2651 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2652 radv_flush_ngg_gs_state(cmd_buffer
);
2655 struct radv_draw_info
{
2657 * Number of vertices.
2662 * Index of the first vertex.
2664 int32_t vertex_offset
;
2667 * First instance id.
2669 uint32_t first_instance
;
2672 * Number of instances.
2674 uint32_t instance_count
;
2677 * First index (indexed draws only).
2679 uint32_t first_index
;
2682 * Whether it's an indexed draw.
2687 * Indirect draw parameters resource.
2689 struct radv_buffer
*indirect
;
2690 uint64_t indirect_offset
;
2694 * Draw count parameters resource.
2696 struct radv_buffer
*count_buffer
;
2697 uint64_t count_buffer_offset
;
2700 * Stream output parameters resource.
2702 struct radv_buffer
*strmout_buffer
;
2703 uint64_t strmout_buffer_offset
;
2707 radv_get_primitive_reset_index(struct radv_cmd_buffer
*cmd_buffer
)
2709 switch (cmd_buffer
->state
.index_type
) {
2710 case V_028A7C_VGT_INDEX_8
:
2712 case V_028A7C_VGT_INDEX_16
:
2714 case V_028A7C_VGT_INDEX_32
:
2717 unreachable("invalid index type");
2722 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
2723 bool instanced_draw
, bool indirect_draw
,
2724 bool count_from_stream_output
,
2725 uint32_t draw_vertex_count
)
2727 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2728 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2729 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2730 unsigned ia_multi_vgt_param
;
2732 ia_multi_vgt_param
=
2733 si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
,
2735 count_from_stream_output
,
2738 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
2739 if (info
->chip_class
== GFX9
) {
2740 radeon_set_uconfig_reg_idx(cmd_buffer
->device
->physical_device
,
2742 R_030960_IA_MULTI_VGT_PARAM
,
2743 4, ia_multi_vgt_param
);
2744 } else if (info
->chip_class
>= GFX7
) {
2745 radeon_set_context_reg_idx(cs
,
2746 R_028AA8_IA_MULTI_VGT_PARAM
,
2747 1, ia_multi_vgt_param
);
2749 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
2750 ia_multi_vgt_param
);
2752 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
2757 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
,
2758 const struct radv_draw_info
*draw_info
)
2760 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2761 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2762 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2763 int32_t primitive_reset_en
;
2766 if (info
->chip_class
< GFX10
) {
2767 si_emit_ia_multi_vgt_param(cmd_buffer
, draw_info
->instance_count
> 1,
2768 draw_info
->indirect
,
2769 !!draw_info
->strmout_buffer
,
2770 draw_info
->indirect
? 0 : draw_info
->count
);
2773 /* Primitive restart. */
2774 primitive_reset_en
=
2775 draw_info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
;
2777 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
2778 state
->last_primitive_reset_en
= primitive_reset_en
;
2779 if (info
->chip_class
>= GFX9
) {
2780 radeon_set_uconfig_reg(cs
,
2781 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
2782 primitive_reset_en
);
2784 radeon_set_context_reg(cs
,
2785 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
2786 primitive_reset_en
);
2790 if (primitive_reset_en
) {
2791 uint32_t primitive_reset_index
=
2792 radv_get_primitive_reset_index(cmd_buffer
);
2794 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
2795 radeon_set_context_reg(cs
,
2796 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
2797 primitive_reset_index
);
2798 state
->last_primitive_reset_index
= primitive_reset_index
;
2802 if (draw_info
->strmout_buffer
) {
2803 uint64_t va
= radv_buffer_get_va(draw_info
->strmout_buffer
->bo
);
2805 va
+= draw_info
->strmout_buffer
->offset
+
2806 draw_info
->strmout_buffer_offset
;
2808 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
2811 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
2812 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
2813 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
2814 COPY_DATA_WR_CONFIRM
);
2815 radeon_emit(cs
, va
);
2816 radeon_emit(cs
, va
>> 32);
2817 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
2818 radeon_emit(cs
, 0); /* unused */
2820 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, draw_info
->strmout_buffer
->bo
);
2824 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
2825 VkPipelineStageFlags src_stage_mask
)
2827 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
2828 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2829 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2830 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2831 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
2834 if (src_stage_mask
& (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
2835 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
2836 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
2837 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
2838 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2839 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2840 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
2841 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2842 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
2843 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
2844 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
2845 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
|
2846 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
2847 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
2848 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
2849 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT
)) {
2850 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
2854 static enum radv_cmd_flush_bits
2855 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2856 VkAccessFlags src_flags
,
2857 struct radv_image
*image
)
2859 bool flush_CB_meta
= true, flush_DB_meta
= true;
2860 enum radv_cmd_flush_bits flush_bits
= 0;
2864 if (!radv_image_has_CB_metadata(image
))
2865 flush_CB_meta
= false;
2866 if (!radv_image_has_htile(image
))
2867 flush_DB_meta
= false;
2870 for_each_bit(b
, src_flags
) {
2871 switch ((VkAccessFlagBits
)(1 << b
)) {
2872 case VK_ACCESS_SHADER_WRITE_BIT
:
2873 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
:
2874 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2875 flush_bits
|= RADV_CMD_FLAG_WB_L2
;
2877 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2878 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2880 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2882 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2883 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2885 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2887 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2888 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2889 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2890 RADV_CMD_FLAG_INV_L2
;
2893 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2895 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2904 static enum radv_cmd_flush_bits
2905 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2906 VkAccessFlags dst_flags
,
2907 struct radv_image
*image
)
2909 bool flush_CB_meta
= true, flush_DB_meta
= true;
2910 enum radv_cmd_flush_bits flush_bits
= 0;
2911 bool flush_CB
= true, flush_DB
= true;
2912 bool image_is_coherent
= false;
2916 if (!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)) {
2921 if (!radv_image_has_CB_metadata(image
))
2922 flush_CB_meta
= false;
2923 if (!radv_image_has_htile(image
))
2924 flush_DB_meta
= false;
2926 /* TODO: implement shader coherent for GFX10 */
2928 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
2929 if (image
->info
.samples
== 1 &&
2930 (image
->usage
& (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
2931 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) &&
2932 !vk_format_is_stencil(image
->vk_format
)) {
2933 /* Single-sample color and single-sample depth
2934 * (not stencil) are coherent with shaders on
2937 image_is_coherent
= true;
2942 for_each_bit(b
, dst_flags
) {
2943 switch ((VkAccessFlagBits
)(1 << b
)) {
2944 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2945 case VK_ACCESS_INDEX_READ_BIT
:
2946 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2948 case VK_ACCESS_UNIFORM_READ_BIT
:
2949 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
| RADV_CMD_FLAG_INV_SCACHE
;
2951 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2952 case VK_ACCESS_TRANSFER_READ_BIT
:
2953 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2954 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
|
2955 RADV_CMD_FLAG_INV_L2
;
2957 case VK_ACCESS_SHADER_READ_BIT
:
2958 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
;
2959 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2960 * invalidate the scalar cache. */
2961 if (cmd_buffer
->device
->physical_device
->use_aco
&&
2962 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
)
2963 flush_bits
|= RADV_CMD_FLAG_INV_SCACHE
;
2965 if (!image_is_coherent
)
2966 flush_bits
|= RADV_CMD_FLAG_INV_L2
;
2968 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
2970 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2972 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2974 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
2976 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2978 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2987 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2988 const struct radv_subpass_barrier
*barrier
)
2990 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
,
2992 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
2993 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
2998 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
)
3000 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3001 uint32_t subpass_id
= state
->subpass
- state
->pass
->subpasses
;
3003 /* The id of this subpass shouldn't exceed the number of subpasses in
3004 * this render pass minus 1.
3006 assert(subpass_id
< state
->pass
->subpass_count
);
3010 static struct radv_sample_locations_state
*
3011 radv_get_attachment_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
3015 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3016 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
3017 struct radv_image_view
*view
= state
->attachments
[att_idx
].iview
;
3019 if (view
->image
->info
.samples
== 1)
3022 if (state
->pass
->attachments
[att_idx
].first_subpass_idx
== subpass_id
) {
3023 /* Return the initial sample locations if this is the initial
3024 * layout transition of the given subpass attachemnt.
3026 if (state
->attachments
[att_idx
].sample_location
.count
> 0)
3027 return &state
->attachments
[att_idx
].sample_location
;
3029 /* Otherwise return the subpass sample locations if defined. */
3030 if (state
->subpass_sample_locs
) {
3031 /* Because the driver sets the current subpass before
3032 * initial layout transitions, we should use the sample
3033 * locations from the previous subpass to avoid an
3034 * off-by-one problem. Otherwise, use the sample
3035 * locations for the current subpass for final layout
3041 for (uint32_t i
= 0; i
< state
->num_subpass_sample_locs
; i
++) {
3042 if (state
->subpass_sample_locs
[i
].subpass_idx
== subpass_id
)
3043 return &state
->subpass_sample_locs
[i
].sample_location
;
3051 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3052 struct radv_subpass_attachment att
,
3055 unsigned idx
= att
.attachment
;
3056 struct radv_image_view
*view
= cmd_buffer
->state
.attachments
[idx
].iview
;
3057 struct radv_sample_locations_state
*sample_locs
;
3058 VkImageSubresourceRange range
;
3059 range
.aspectMask
= view
->aspect_mask
;
3060 range
.baseMipLevel
= view
->base_mip
;
3061 range
.levelCount
= 1;
3062 range
.baseArrayLayer
= view
->base_layer
;
3063 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
3065 if (cmd_buffer
->state
.subpass
->view_mask
) {
3066 /* If the current subpass uses multiview, the driver might have
3067 * performed a fast color/depth clear to the whole image
3068 * (including all layers). To make sure the driver will
3069 * decompress the image correctly (if needed), we have to
3070 * account for the "real" number of layers. If the view mask is
3071 * sparse, this will decompress more layers than needed.
3073 range
.layerCount
= util_last_bit(cmd_buffer
->state
.subpass
->view_mask
);
3076 /* Get the subpass sample locations for the given attachment, if NULL
3077 * is returned the driver will use the default HW locations.
3079 sample_locs
= radv_get_attachment_sample_locations(cmd_buffer
, idx
,
3082 /* Determine if the subpass uses separate depth/stencil layouts. */
3083 bool uses_separate_depth_stencil_layouts
= false;
3084 if ((cmd_buffer
->state
.attachments
[idx
].current_layout
!=
3085 cmd_buffer
->state
.attachments
[idx
].current_stencil_layout
) ||
3086 (att
.layout
!= att
.stencil_layout
)) {
3087 uses_separate_depth_stencil_layouts
= true;
3090 /* For separate layouts, perform depth and stencil transitions
3093 if (uses_separate_depth_stencil_layouts
&&
3094 (range
.aspectMask
== (VK_IMAGE_ASPECT_DEPTH_BIT
|
3095 VK_IMAGE_ASPECT_STENCIL_BIT
))) {
3096 /* Depth-only transitions. */
3097 range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
3098 radv_handle_image_transition(cmd_buffer
,
3100 cmd_buffer
->state
.attachments
[idx
].current_layout
,
3101 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
,
3102 att
.layout
, att
.in_render_loop
,
3103 0, 0, &range
, sample_locs
);
3105 /* Stencil-only transitions. */
3106 range
.aspectMask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
3107 radv_handle_image_transition(cmd_buffer
,
3109 cmd_buffer
->state
.attachments
[idx
].current_stencil_layout
,
3110 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
,
3111 att
.stencil_layout
, att
.in_render_loop
,
3112 0, 0, &range
, sample_locs
);
3114 radv_handle_image_transition(cmd_buffer
,
3116 cmd_buffer
->state
.attachments
[idx
].current_layout
,
3117 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
,
3118 att
.layout
, att
.in_render_loop
,
3119 0, 0, &range
, sample_locs
);
3122 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
3123 cmd_buffer
->state
.attachments
[idx
].current_stencil_layout
= att
.stencil_layout
;
3124 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
= att
.in_render_loop
;
3130 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
3131 const struct radv_subpass
*subpass
)
3133 cmd_buffer
->state
.subpass
= subpass
;
3135 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
3139 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
3140 struct radv_render_pass
*pass
,
3141 const VkRenderPassBeginInfo
*info
)
3143 const struct VkRenderPassSampleLocationsBeginInfoEXT
*sample_locs
=
3144 vk_find_struct_const(info
->pNext
,
3145 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT
);
3146 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3149 state
->subpass_sample_locs
= NULL
;
3153 for (uint32_t i
= 0; i
< sample_locs
->attachmentInitialSampleLocationsCount
; i
++) {
3154 const VkAttachmentSampleLocationsEXT
*att_sample_locs
=
3155 &sample_locs
->pAttachmentInitialSampleLocations
[i
];
3156 uint32_t att_idx
= att_sample_locs
->attachmentIndex
;
3157 struct radv_image
*image
= cmd_buffer
->state
.attachments
[att_idx
].iview
->image
;
3159 assert(vk_format_is_depth_or_stencil(image
->vk_format
));
3161 /* From the Vulkan spec 1.1.108:
3163 * "If the image referenced by the framebuffer attachment at
3164 * index attachmentIndex was not created with
3165 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3166 * then the values specified in sampleLocationsInfo are
3169 if (!(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
))
3172 const VkSampleLocationsInfoEXT
*sample_locs_info
=
3173 &att_sample_locs
->sampleLocationsInfo
;
3175 state
->attachments
[att_idx
].sample_location
.per_pixel
=
3176 sample_locs_info
->sampleLocationsPerPixel
;
3177 state
->attachments
[att_idx
].sample_location
.grid_size
=
3178 sample_locs_info
->sampleLocationGridSize
;
3179 state
->attachments
[att_idx
].sample_location
.count
=
3180 sample_locs_info
->sampleLocationsCount
;
3181 typed_memcpy(&state
->attachments
[att_idx
].sample_location
.locations
[0],
3182 sample_locs_info
->pSampleLocations
,
3183 sample_locs_info
->sampleLocationsCount
);
3186 state
->subpass_sample_locs
= vk_alloc(&cmd_buffer
->pool
->alloc
,
3187 sample_locs
->postSubpassSampleLocationsCount
*
3188 sizeof(state
->subpass_sample_locs
[0]),
3189 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3190 if (state
->subpass_sample_locs
== NULL
) {
3191 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3192 return cmd_buffer
->record_result
;
3195 state
->num_subpass_sample_locs
= sample_locs
->postSubpassSampleLocationsCount
;
3197 for (uint32_t i
= 0; i
< sample_locs
->postSubpassSampleLocationsCount
; i
++) {
3198 const VkSubpassSampleLocationsEXT
*subpass_sample_locs_info
=
3199 &sample_locs
->pPostSubpassSampleLocations
[i
];
3200 const VkSampleLocationsInfoEXT
*sample_locs_info
=
3201 &subpass_sample_locs_info
->sampleLocationsInfo
;
3203 state
->subpass_sample_locs
[i
].subpass_idx
=
3204 subpass_sample_locs_info
->subpassIndex
;
3205 state
->subpass_sample_locs
[i
].sample_location
.per_pixel
=
3206 sample_locs_info
->sampleLocationsPerPixel
;
3207 state
->subpass_sample_locs
[i
].sample_location
.grid_size
=
3208 sample_locs_info
->sampleLocationGridSize
;
3209 state
->subpass_sample_locs
[i
].sample_location
.count
=
3210 sample_locs_info
->sampleLocationsCount
;
3211 typed_memcpy(&state
->subpass_sample_locs
[i
].sample_location
.locations
[0],
3212 sample_locs_info
->pSampleLocations
,
3213 sample_locs_info
->sampleLocationsCount
);
3220 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
3221 struct radv_render_pass
*pass
,
3222 const VkRenderPassBeginInfo
*info
)
3224 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3225 const struct VkRenderPassAttachmentBeginInfo
*attachment_info
= NULL
;
3228 attachment_info
= vk_find_struct_const(info
->pNext
,
3229 RENDER_PASS_ATTACHMENT_BEGIN_INFO
);
3233 if (pass
->attachment_count
== 0) {
3234 state
->attachments
= NULL
;
3238 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
3239 pass
->attachment_count
*
3240 sizeof(state
->attachments
[0]),
3241 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3242 if (state
->attachments
== NULL
) {
3243 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3244 return cmd_buffer
->record_result
;
3247 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
3248 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
3249 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
3250 VkImageAspectFlags clear_aspects
= 0;
3252 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
3253 /* color attachment */
3254 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3255 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
3258 /* depthstencil attachment */
3259 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
3260 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3261 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
3262 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
3263 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
3264 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
3266 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
3267 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3268 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
3272 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
3273 state
->attachments
[i
].cleared_views
= 0;
3274 if (clear_aspects
&& info
) {
3275 assert(info
->clearValueCount
> i
);
3276 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
3279 state
->attachments
[i
].current_layout
= att
->initial_layout
;
3280 state
->attachments
[i
].current_stencil_layout
= att
->stencil_initial_layout
;
3281 state
->attachments
[i
].sample_location
.count
= 0;
3283 struct radv_image_view
*iview
;
3284 if (attachment_info
&& attachment_info
->attachmentCount
> i
) {
3285 iview
= radv_image_view_from_handle(attachment_info
->pAttachments
[i
]);
3287 iview
= state
->framebuffer
->attachments
[i
];
3290 state
->attachments
[i
].iview
= iview
;
3291 if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3292 radv_initialise_ds_surface(cmd_buffer
->device
, &state
->attachments
[i
].ds
, iview
);
3294 radv_initialise_color_surface(cmd_buffer
->device
, &state
->attachments
[i
].cb
, iview
);
3301 VkResult
radv_AllocateCommandBuffers(
3303 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
3304 VkCommandBuffer
*pCommandBuffers
)
3306 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3307 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
3309 VkResult result
= VK_SUCCESS
;
3312 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
3314 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
3315 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
3317 list_del(&cmd_buffer
->pool_link
);
3318 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
3320 result
= radv_reset_cmd_buffer(cmd_buffer
);
3321 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
3322 cmd_buffer
->level
= pAllocateInfo
->level
;
3324 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
3326 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
3327 &pCommandBuffers
[i
]);
3329 if (result
!= VK_SUCCESS
)
3333 if (result
!= VK_SUCCESS
) {
3334 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
3335 i
, pCommandBuffers
);
3337 /* From the Vulkan 1.0.66 spec:
3339 * "vkAllocateCommandBuffers can be used to create multiple
3340 * command buffers. If the creation of any of those command
3341 * buffers fails, the implementation must destroy all
3342 * successfully created command buffer objects from this
3343 * command, set all entries of the pCommandBuffers array to
3344 * NULL and return the error."
3346 memset(pCommandBuffers
, 0,
3347 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
3353 void radv_FreeCommandBuffers(
3355 VkCommandPool commandPool
,
3356 uint32_t commandBufferCount
,
3357 const VkCommandBuffer
*pCommandBuffers
)
3359 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3360 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
3363 if (cmd_buffer
->pool
) {
3364 list_del(&cmd_buffer
->pool_link
);
3365 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
3367 radv_cmd_buffer_destroy(cmd_buffer
);
3373 VkResult
radv_ResetCommandBuffer(
3374 VkCommandBuffer commandBuffer
,
3375 VkCommandBufferResetFlags flags
)
3377 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3378 return radv_reset_cmd_buffer(cmd_buffer
);
3381 VkResult
radv_BeginCommandBuffer(
3382 VkCommandBuffer commandBuffer
,
3383 const VkCommandBufferBeginInfo
*pBeginInfo
)
3385 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3386 VkResult result
= VK_SUCCESS
;
3388 if (cmd_buffer
->status
!= RADV_CMD_BUFFER_STATUS_INITIAL
) {
3389 /* If the command buffer has already been resetted with
3390 * vkResetCommandBuffer, no need to do it again.
3392 result
= radv_reset_cmd_buffer(cmd_buffer
);
3393 if (result
!= VK_SUCCESS
)
3397 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
3398 cmd_buffer
->state
.last_primitive_reset_en
= -1;
3399 cmd_buffer
->state
.last_index_type
= -1;
3400 cmd_buffer
->state
.last_num_instances
= -1;
3401 cmd_buffer
->state
.last_vertex_offset
= -1;
3402 cmd_buffer
->state
.last_first_instance
= -1;
3403 cmd_buffer
->state
.predication_type
= -1;
3404 cmd_buffer
->state
.last_sx_ps_downconvert
= -1;
3405 cmd_buffer
->state
.last_sx_blend_opt_epsilon
= -1;
3406 cmd_buffer
->state
.last_sx_blend_opt_control
= -1;
3407 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
3409 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
3410 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
3411 assert(pBeginInfo
->pInheritanceInfo
);
3412 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
3413 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
3415 struct radv_subpass
*subpass
=
3416 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
3418 if (cmd_buffer
->state
.framebuffer
) {
3419 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
3420 if (result
!= VK_SUCCESS
)
3424 cmd_buffer
->state
.inherited_pipeline_statistics
=
3425 pBeginInfo
->pInheritanceInfo
->pipelineStatistics
;
3427 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
3430 if (unlikely(cmd_buffer
->device
->trace_bo
))
3431 radv_cmd_buffer_trace_emit(cmd_buffer
);
3433 radv_describe_begin_cmd_buffer(cmd_buffer
);
3435 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_RECORDING
;
3440 void radv_CmdBindVertexBuffers(
3441 VkCommandBuffer commandBuffer
,
3442 uint32_t firstBinding
,
3443 uint32_t bindingCount
,
3444 const VkBuffer
* pBuffers
,
3445 const VkDeviceSize
* pOffsets
)
3447 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3448 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
3449 bool changed
= false;
3451 /* We have to defer setting up vertex buffer since we need the buffer
3452 * stride from the pipeline. */
3454 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
3455 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
3456 uint32_t idx
= firstBinding
+ i
;
3459 (vb
[idx
].buffer
!= radv_buffer_from_handle(pBuffers
[i
]) ||
3460 vb
[idx
].offset
!= pOffsets
[i
])) {
3464 vb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
3465 vb
[idx
].offset
= pOffsets
[i
];
3467 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3468 vb
[idx
].buffer
->bo
);
3472 /* No state changes. */
3476 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_VERTEX_BUFFER
;
3480 vk_to_index_type(VkIndexType type
)
3483 case VK_INDEX_TYPE_UINT8_EXT
:
3484 return V_028A7C_VGT_INDEX_8
;
3485 case VK_INDEX_TYPE_UINT16
:
3486 return V_028A7C_VGT_INDEX_16
;
3487 case VK_INDEX_TYPE_UINT32
:
3488 return V_028A7C_VGT_INDEX_32
;
3490 unreachable("invalid index type");
3495 radv_get_vgt_index_size(uint32_t type
)
3498 case V_028A7C_VGT_INDEX_8
:
3500 case V_028A7C_VGT_INDEX_16
:
3502 case V_028A7C_VGT_INDEX_32
:
3505 unreachable("invalid index type");
3509 void radv_CmdBindIndexBuffer(
3510 VkCommandBuffer commandBuffer
,
3512 VkDeviceSize offset
,
3513 VkIndexType indexType
)
3515 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3516 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
3518 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
3519 cmd_buffer
->state
.index_offset
== offset
&&
3520 cmd_buffer
->state
.index_type
== indexType
) {
3521 /* No state changes. */
3525 cmd_buffer
->state
.index_buffer
= index_buffer
;
3526 cmd_buffer
->state
.index_offset
= offset
;
3527 cmd_buffer
->state
.index_type
= vk_to_index_type(indexType
);
3528 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
3529 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
3531 int index_size
= radv_get_vgt_index_size(vk_to_index_type(indexType
));
3532 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) / index_size
;
3533 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3534 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, index_buffer
->bo
);
3539 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3540 VkPipelineBindPoint bind_point
,
3541 struct radv_descriptor_set
*set
, unsigned idx
)
3543 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3545 radv_set_descriptor_set(cmd_buffer
, bind_point
, set
, idx
);
3548 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
3550 if (!cmd_buffer
->device
->use_global_bo_list
) {
3551 for (unsigned j
= 0; j
< set
->buffer_count
; ++j
)
3552 if (set
->descriptors
[j
])
3553 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->descriptors
[j
]);
3557 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->bo
);
3560 void radv_CmdBindDescriptorSets(
3561 VkCommandBuffer commandBuffer
,
3562 VkPipelineBindPoint pipelineBindPoint
,
3563 VkPipelineLayout _layout
,
3565 uint32_t descriptorSetCount
,
3566 const VkDescriptorSet
* pDescriptorSets
,
3567 uint32_t dynamicOffsetCount
,
3568 const uint32_t* pDynamicOffsets
)
3570 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3571 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3572 unsigned dyn_idx
= 0;
3574 const bool no_dynamic_bounds
= cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
3575 struct radv_descriptor_state
*descriptors_state
=
3576 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3578 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
3579 unsigned idx
= i
+ firstSet
;
3580 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
3582 /* If the set is already bound we only need to update the
3583 * (potentially changed) dynamic offsets. */
3584 if (descriptors_state
->sets
[idx
] != set
||
3585 !(descriptors_state
->valid
& (1u << idx
))) {
3586 radv_bind_descriptor_set(cmd_buffer
, pipelineBindPoint
, set
, idx
);
3589 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
3590 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
3591 uint32_t *dst
= descriptors_state
->dynamic_buffers
+ idx
* 4;
3592 assert(dyn_idx
< dynamicOffsetCount
);
3594 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
3595 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
3597 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
3598 dst
[2] = no_dynamic_bounds
? 0xffffffffu
: range
->size
;
3599 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3600 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3601 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3602 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3604 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3605 dst
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3606 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3607 S_008F0C_RESOURCE_LEVEL(1);
3609 dst
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3610 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3613 cmd_buffer
->push_constant_stages
|=
3614 set
->layout
->dynamic_shader_stages
;
3619 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3620 struct radv_descriptor_set
*set
,
3621 struct radv_descriptor_set_layout
*layout
,
3622 VkPipelineBindPoint bind_point
)
3624 struct radv_descriptor_state
*descriptors_state
=
3625 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3626 set
->size
= layout
->size
;
3627 set
->layout
= layout
;
3629 if (descriptors_state
->push_set
.capacity
< set
->size
) {
3630 size_t new_size
= MAX2(set
->size
, 1024);
3631 new_size
= MAX2(new_size
, 2 * descriptors_state
->push_set
.capacity
);
3632 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
3634 free(set
->mapped_ptr
);
3635 set
->mapped_ptr
= malloc(new_size
);
3637 if (!set
->mapped_ptr
) {
3638 descriptors_state
->push_set
.capacity
= 0;
3639 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3643 descriptors_state
->push_set
.capacity
= new_size
;
3649 void radv_meta_push_descriptor_set(
3650 struct radv_cmd_buffer
* cmd_buffer
,
3651 VkPipelineBindPoint pipelineBindPoint
,
3652 VkPipelineLayout _layout
,
3654 uint32_t descriptorWriteCount
,
3655 const VkWriteDescriptorSet
* pDescriptorWrites
)
3657 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3658 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
3662 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3664 push_set
->size
= layout
->set
[set
].layout
->size
;
3665 push_set
->layout
= layout
->set
[set
].layout
;
3667 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
3669 (void**) &push_set
->mapped_ptr
))
3672 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
3673 push_set
->va
+= bo_offset
;
3675 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3676 radv_descriptor_set_to_handle(push_set
),
3677 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3679 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3682 void radv_CmdPushDescriptorSetKHR(
3683 VkCommandBuffer commandBuffer
,
3684 VkPipelineBindPoint pipelineBindPoint
,
3685 VkPipelineLayout _layout
,
3687 uint32_t descriptorWriteCount
,
3688 const VkWriteDescriptorSet
* pDescriptorWrites
)
3690 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3691 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3692 struct radv_descriptor_state
*descriptors_state
=
3693 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3694 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3696 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3698 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3699 layout
->set
[set
].layout
,
3703 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3704 * because it is invalid, according to Vulkan spec.
3706 for (int i
= 0; i
< descriptorWriteCount
; i
++) {
3707 ASSERTED
const VkWriteDescriptorSet
*writeset
= &pDescriptorWrites
[i
];
3708 assert(writeset
->descriptorType
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
);
3711 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3712 radv_descriptor_set_to_handle(push_set
),
3713 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3715 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3716 descriptors_state
->push_dirty
= true;
3719 void radv_CmdPushDescriptorSetWithTemplateKHR(
3720 VkCommandBuffer commandBuffer
,
3721 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
3722 VkPipelineLayout _layout
,
3726 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3727 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3728 RADV_FROM_HANDLE(radv_descriptor_update_template
, templ
, descriptorUpdateTemplate
);
3729 struct radv_descriptor_state
*descriptors_state
=
3730 radv_get_descriptors_state(cmd_buffer
, templ
->bind_point
);
3731 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3733 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3735 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3736 layout
->set
[set
].layout
,
3740 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
3741 descriptorUpdateTemplate
, pData
);
3743 radv_set_descriptor_set(cmd_buffer
, templ
->bind_point
, push_set
, set
);
3744 descriptors_state
->push_dirty
= true;
3747 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
3748 VkPipelineLayout layout
,
3749 VkShaderStageFlags stageFlags
,
3752 const void* pValues
)
3754 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3755 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
3756 cmd_buffer
->push_constant_stages
|= stageFlags
;
3759 VkResult
radv_EndCommandBuffer(
3760 VkCommandBuffer commandBuffer
)
3762 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3764 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
3765 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX6
)
3766 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WB_L2
;
3768 /* Make sure to sync all pending active queries at the end of
3771 cmd_buffer
->state
.flush_bits
|= cmd_buffer
->active_query_flush_bits
;
3773 /* Since NGG streamout uses GDS, we need to make GDS idle when
3774 * we leave the IB, otherwise another process might overwrite
3775 * it while our shaders are busy.
3777 if (cmd_buffer
->gds_needed
)
3778 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
3780 si_emit_cache_flush(cmd_buffer
);
3783 /* Make sure CP DMA is idle at the end of IBs because the kernel
3784 * doesn't wait for it.
3786 si_cp_dma_wait_for_idle(cmd_buffer
);
3788 radv_describe_end_cmd_buffer(cmd_buffer
);
3790 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3791 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
3793 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
3794 return vk_error(cmd_buffer
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3796 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_EXECUTABLE
;
3798 return cmd_buffer
->record_result
;
3802 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
3804 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3806 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
3809 assert(!pipeline
->ctx_cs
.cdw
);
3811 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
3813 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, pipeline
->cs
.cdw
);
3814 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
3816 cmd_buffer
->compute_scratch_size_per_wave_needed
= MAX2(cmd_buffer
->compute_scratch_size_per_wave_needed
,
3817 pipeline
->scratch_bytes_per_wave
);
3818 cmd_buffer
->compute_scratch_waves_wanted
= MAX2(cmd_buffer
->compute_scratch_waves_wanted
,
3819 pipeline
->max_waves
);
3821 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3822 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->bo
);
3824 if (unlikely(cmd_buffer
->device
->trace_bo
))
3825 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
3828 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
,
3829 VkPipelineBindPoint bind_point
)
3831 struct radv_descriptor_state
*descriptors_state
=
3832 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3834 descriptors_state
->dirty
|= descriptors_state
->valid
;
3837 void radv_CmdBindPipeline(
3838 VkCommandBuffer commandBuffer
,
3839 VkPipelineBindPoint pipelineBindPoint
,
3840 VkPipeline _pipeline
)
3842 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3843 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
3845 switch (pipelineBindPoint
) {
3846 case VK_PIPELINE_BIND_POINT_COMPUTE
:
3847 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
3849 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3851 cmd_buffer
->state
.compute_pipeline
= pipeline
;
3852 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3854 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
3855 if (cmd_buffer
->state
.pipeline
== pipeline
)
3857 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3859 cmd_buffer
->state
.pipeline
= pipeline
;
3863 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
3864 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
3866 /* the new vertex shader might not have the same user regs */
3867 cmd_buffer
->state
.last_first_instance
= -1;
3868 cmd_buffer
->state
.last_vertex_offset
= -1;
3870 /* Prefetch all pipeline shaders at first draw time. */
3871 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_SHADERS
;
3873 if ((cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_NAVI10
||
3874 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_NAVI12
||
3875 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_NAVI14
) &&
3876 cmd_buffer
->state
.emitted_pipeline
&&
3877 radv_pipeline_has_ngg(cmd_buffer
->state
.emitted_pipeline
) &&
3878 !radv_pipeline_has_ngg(cmd_buffer
->state
.pipeline
)) {
3879 /* Transitioning from NGG to legacy GS requires
3880 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3881 * at the beginning of IBs when legacy GS ring pointers
3884 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_FLUSH
;
3887 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
3888 radv_bind_streamout_state(cmd_buffer
, pipeline
);
3890 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
3891 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
3892 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
3893 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
3895 if (radv_pipeline_has_tess(pipeline
))
3896 cmd_buffer
->tess_rings_needed
= true;
3899 assert(!"invalid bind point");
3904 void radv_CmdSetViewport(
3905 VkCommandBuffer commandBuffer
,
3906 uint32_t firstViewport
,
3907 uint32_t viewportCount
,
3908 const VkViewport
* pViewports
)
3910 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3911 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3912 ASSERTED
const uint32_t total_count
= firstViewport
+ viewportCount
;
3914 assert(firstViewport
< MAX_VIEWPORTS
);
3915 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
3917 if (!memcmp(state
->dynamic
.viewport
.viewports
+ firstViewport
,
3918 pViewports
, viewportCount
* sizeof(*pViewports
))) {
3922 memcpy(state
->dynamic
.viewport
.viewports
+ firstViewport
, pViewports
,
3923 viewportCount
* sizeof(*pViewports
));
3925 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
3928 void radv_CmdSetScissor(
3929 VkCommandBuffer commandBuffer
,
3930 uint32_t firstScissor
,
3931 uint32_t scissorCount
,
3932 const VkRect2D
* pScissors
)
3934 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3935 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3936 ASSERTED
const uint32_t total_count
= firstScissor
+ scissorCount
;
3938 assert(firstScissor
< MAX_SCISSORS
);
3939 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
3941 if (!memcmp(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3942 scissorCount
* sizeof(*pScissors
))) {
3946 memcpy(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3947 scissorCount
* sizeof(*pScissors
));
3949 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
3952 void radv_CmdSetLineWidth(
3953 VkCommandBuffer commandBuffer
,
3956 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3958 if (cmd_buffer
->state
.dynamic
.line_width
== lineWidth
)
3961 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
3962 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
3965 void radv_CmdSetDepthBias(
3966 VkCommandBuffer commandBuffer
,
3967 float depthBiasConstantFactor
,
3968 float depthBiasClamp
,
3969 float depthBiasSlopeFactor
)
3971 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3972 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3974 if (state
->dynamic
.depth_bias
.bias
== depthBiasConstantFactor
&&
3975 state
->dynamic
.depth_bias
.clamp
== depthBiasClamp
&&
3976 state
->dynamic
.depth_bias
.slope
== depthBiasSlopeFactor
) {
3980 state
->dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
3981 state
->dynamic
.depth_bias
.clamp
= depthBiasClamp
;
3982 state
->dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
3984 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
3987 void radv_CmdSetBlendConstants(
3988 VkCommandBuffer commandBuffer
,
3989 const float blendConstants
[4])
3991 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3992 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3994 if (!memcmp(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4))
3997 memcpy(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4);
3999 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
4002 void radv_CmdSetDepthBounds(
4003 VkCommandBuffer commandBuffer
,
4004 float minDepthBounds
,
4005 float maxDepthBounds
)
4007 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4008 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4010 if (state
->dynamic
.depth_bounds
.min
== minDepthBounds
&&
4011 state
->dynamic
.depth_bounds
.max
== maxDepthBounds
) {
4015 state
->dynamic
.depth_bounds
.min
= minDepthBounds
;
4016 state
->dynamic
.depth_bounds
.max
= maxDepthBounds
;
4018 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
4021 void radv_CmdSetStencilCompareMask(
4022 VkCommandBuffer commandBuffer
,
4023 VkStencilFaceFlags faceMask
,
4024 uint32_t compareMask
)
4026 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4027 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4028 bool front_same
= state
->dynamic
.stencil_compare_mask
.front
== compareMask
;
4029 bool back_same
= state
->dynamic
.stencil_compare_mask
.back
== compareMask
;
4031 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
4032 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
4036 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
4037 state
->dynamic
.stencil_compare_mask
.front
= compareMask
;
4038 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
4039 state
->dynamic
.stencil_compare_mask
.back
= compareMask
;
4041 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
4044 void radv_CmdSetStencilWriteMask(
4045 VkCommandBuffer commandBuffer
,
4046 VkStencilFaceFlags faceMask
,
4049 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4050 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4051 bool front_same
= state
->dynamic
.stencil_write_mask
.front
== writeMask
;
4052 bool back_same
= state
->dynamic
.stencil_write_mask
.back
== writeMask
;
4054 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
4055 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
4059 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
4060 state
->dynamic
.stencil_write_mask
.front
= writeMask
;
4061 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
4062 state
->dynamic
.stencil_write_mask
.back
= writeMask
;
4064 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
4067 void radv_CmdSetStencilReference(
4068 VkCommandBuffer commandBuffer
,
4069 VkStencilFaceFlags faceMask
,
4072 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4073 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4074 bool front_same
= state
->dynamic
.stencil_reference
.front
== reference
;
4075 bool back_same
= state
->dynamic
.stencil_reference
.back
== reference
;
4077 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
4078 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
4082 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
4083 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
4084 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
4085 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
4087 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
4090 void radv_CmdSetDiscardRectangleEXT(
4091 VkCommandBuffer commandBuffer
,
4092 uint32_t firstDiscardRectangle
,
4093 uint32_t discardRectangleCount
,
4094 const VkRect2D
* pDiscardRectangles
)
4096 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4097 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4098 ASSERTED
const uint32_t total_count
= firstDiscardRectangle
+ discardRectangleCount
;
4100 assert(firstDiscardRectangle
< MAX_DISCARD_RECTANGLES
);
4101 assert(total_count
>= 1 && total_count
<= MAX_DISCARD_RECTANGLES
);
4103 if (!memcmp(state
->dynamic
.discard_rectangle
.rectangles
+ firstDiscardRectangle
,
4104 pDiscardRectangles
, discardRectangleCount
* sizeof(*pDiscardRectangles
))) {
4108 typed_memcpy(&state
->dynamic
.discard_rectangle
.rectangles
[firstDiscardRectangle
],
4109 pDiscardRectangles
, discardRectangleCount
);
4111 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
;
4114 void radv_CmdSetSampleLocationsEXT(
4115 VkCommandBuffer commandBuffer
,
4116 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
4118 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4119 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4121 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
4123 state
->dynamic
.sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
4124 state
->dynamic
.sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
4125 state
->dynamic
.sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
4126 typed_memcpy(&state
->dynamic
.sample_location
.locations
[0],
4127 pSampleLocationsInfo
->pSampleLocations
,
4128 pSampleLocationsInfo
->sampleLocationsCount
);
4130 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
;
4133 void radv_CmdSetLineStippleEXT(
4134 VkCommandBuffer commandBuffer
,
4135 uint32_t lineStippleFactor
,
4136 uint16_t lineStipplePattern
)
4138 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4139 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4141 state
->dynamic
.line_stipple
.factor
= lineStippleFactor
;
4142 state
->dynamic
.line_stipple
.pattern
= lineStipplePattern
;
4144 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
4147 void radv_CmdExecuteCommands(
4148 VkCommandBuffer commandBuffer
,
4149 uint32_t commandBufferCount
,
4150 const VkCommandBuffer
* pCmdBuffers
)
4152 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
4154 assert(commandBufferCount
> 0);
4156 /* Emit pending flushes on primary prior to executing secondary */
4157 si_emit_cache_flush(primary
);
4159 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
4160 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
4162 primary
->scratch_size_per_wave_needed
= MAX2(primary
->scratch_size_per_wave_needed
,
4163 secondary
->scratch_size_per_wave_needed
);
4164 primary
->scratch_waves_wanted
= MAX2(primary
->scratch_waves_wanted
,
4165 secondary
->scratch_waves_wanted
);
4166 primary
->compute_scratch_size_per_wave_needed
= MAX2(primary
->compute_scratch_size_per_wave_needed
,
4167 secondary
->compute_scratch_size_per_wave_needed
);
4168 primary
->compute_scratch_waves_wanted
= MAX2(primary
->compute_scratch_waves_wanted
,
4169 secondary
->compute_scratch_waves_wanted
);
4171 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
4172 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
4173 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
4174 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
4175 if (secondary
->tess_rings_needed
)
4176 primary
->tess_rings_needed
= true;
4177 if (secondary
->sample_positions_needed
)
4178 primary
->sample_positions_needed
= true;
4179 if (secondary
->gds_needed
)
4180 primary
->gds_needed
= true;
4182 if (!secondary
->state
.framebuffer
&&
4183 (primary
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)) {
4184 /* Emit the framebuffer state from primary if secondary
4185 * has been recorded without a framebuffer, otherwise
4186 * fast color/depth clears can't work.
4188 radv_emit_framebuffer_state(primary
);
4191 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
4194 /* When the secondary command buffer is compute only we don't
4195 * need to re-emit the current graphics pipeline.
4197 if (secondary
->state
.emitted_pipeline
) {
4198 primary
->state
.emitted_pipeline
=
4199 secondary
->state
.emitted_pipeline
;
4202 /* When the secondary command buffer is graphics only we don't
4203 * need to re-emit the current compute pipeline.
4205 if (secondary
->state
.emitted_compute_pipeline
) {
4206 primary
->state
.emitted_compute_pipeline
=
4207 secondary
->state
.emitted_compute_pipeline
;
4210 /* Only re-emit the draw packets when needed. */
4211 if (secondary
->state
.last_primitive_reset_en
!= -1) {
4212 primary
->state
.last_primitive_reset_en
=
4213 secondary
->state
.last_primitive_reset_en
;
4216 if (secondary
->state
.last_primitive_reset_index
) {
4217 primary
->state
.last_primitive_reset_index
=
4218 secondary
->state
.last_primitive_reset_index
;
4221 if (secondary
->state
.last_ia_multi_vgt_param
) {
4222 primary
->state
.last_ia_multi_vgt_param
=
4223 secondary
->state
.last_ia_multi_vgt_param
;
4226 primary
->state
.last_first_instance
= secondary
->state
.last_first_instance
;
4227 primary
->state
.last_num_instances
= secondary
->state
.last_num_instances
;
4228 primary
->state
.last_vertex_offset
= secondary
->state
.last_vertex_offset
;
4229 primary
->state
.last_sx_ps_downconvert
= secondary
->state
.last_sx_ps_downconvert
;
4230 primary
->state
.last_sx_blend_opt_epsilon
= secondary
->state
.last_sx_blend_opt_epsilon
;
4231 primary
->state
.last_sx_blend_opt_control
= secondary
->state
.last_sx_blend_opt_control
;
4233 if (secondary
->state
.last_index_type
!= -1) {
4234 primary
->state
.last_index_type
=
4235 secondary
->state
.last_index_type
;
4239 /* After executing commands from secondary buffers we have to dirty
4242 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
4243 RADV_CMD_DIRTY_INDEX_BUFFER
|
4244 RADV_CMD_DIRTY_DYNAMIC_ALL
;
4245 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_GRAPHICS
);
4246 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_COMPUTE
);
4249 VkResult
radv_CreateCommandPool(
4251 const VkCommandPoolCreateInfo
* pCreateInfo
,
4252 const VkAllocationCallbacks
* pAllocator
,
4253 VkCommandPool
* pCmdPool
)
4255 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4256 struct radv_cmd_pool
*pool
;
4258 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
4259 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4261 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4264 pool
->alloc
= *pAllocator
;
4266 pool
->alloc
= device
->alloc
;
4268 list_inithead(&pool
->cmd_buffers
);
4269 list_inithead(&pool
->free_cmd_buffers
);
4271 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
4273 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
4279 void radv_DestroyCommandPool(
4281 VkCommandPool commandPool
,
4282 const VkAllocationCallbacks
* pAllocator
)
4284 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4285 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4290 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4291 &pool
->cmd_buffers
, pool_link
) {
4292 radv_cmd_buffer_destroy(cmd_buffer
);
4295 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4296 &pool
->free_cmd_buffers
, pool_link
) {
4297 radv_cmd_buffer_destroy(cmd_buffer
);
4300 vk_free2(&device
->alloc
, pAllocator
, pool
);
4303 VkResult
radv_ResetCommandPool(
4305 VkCommandPool commandPool
,
4306 VkCommandPoolResetFlags flags
)
4308 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4311 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
4312 &pool
->cmd_buffers
, pool_link
) {
4313 result
= radv_reset_cmd_buffer(cmd_buffer
);
4314 if (result
!= VK_SUCCESS
)
4321 void radv_TrimCommandPool(
4323 VkCommandPool commandPool
,
4324 VkCommandPoolTrimFlags flags
)
4326 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4331 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4332 &pool
->free_cmd_buffers
, pool_link
) {
4333 radv_cmd_buffer_destroy(cmd_buffer
);
4338 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer
*cmd_buffer
,
4339 uint32_t subpass_id
)
4341 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4342 struct radv_subpass
*subpass
= &state
->pass
->subpasses
[subpass_id
];
4344 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
4345 cmd_buffer
->cs
, 4096);
4347 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
4349 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
4351 radv_describe_barrier_start(cmd_buffer
, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC
);
4353 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4354 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4355 if (a
== VK_ATTACHMENT_UNUSED
)
4358 radv_handle_subpass_image_transition(cmd_buffer
,
4359 subpass
->attachments
[i
],
4363 radv_describe_barrier_end(cmd_buffer
);
4365 radv_cmd_buffer_clear_subpass(cmd_buffer
);
4367 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4371 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer
*cmd_buffer
)
4373 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4374 const struct radv_subpass
*subpass
= state
->subpass
;
4375 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
4377 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
4379 radv_describe_barrier_start(cmd_buffer
, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC
);
4381 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4382 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4383 if (a
== VK_ATTACHMENT_UNUSED
)
4386 if (state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4389 VkImageLayout layout
= state
->pass
->attachments
[a
].final_layout
;
4390 VkImageLayout stencil_layout
= state
->pass
->attachments
[a
].stencil_final_layout
;
4391 struct radv_subpass_attachment att
= { a
, layout
, stencil_layout
};
4392 radv_handle_subpass_image_transition(cmd_buffer
, att
, false);
4395 radv_describe_barrier_end(cmd_buffer
);
4399 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer
*cmd_buffer
,
4400 const VkRenderPassBeginInfo
*pRenderPassBegin
)
4402 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4403 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4406 cmd_buffer
->state
.framebuffer
= framebuffer
;
4407 cmd_buffer
->state
.pass
= pass
;
4408 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4410 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
4411 if (result
!= VK_SUCCESS
)
4414 result
= radv_cmd_state_setup_sample_locations(cmd_buffer
, pass
, pRenderPassBegin
);
4415 if (result
!= VK_SUCCESS
)
4419 void radv_CmdBeginRenderPass(
4420 VkCommandBuffer commandBuffer
,
4421 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4422 VkSubpassContents contents
)
4424 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4426 radv_cmd_buffer_begin_render_pass(cmd_buffer
, pRenderPassBegin
);
4428 radv_cmd_buffer_begin_subpass(cmd_buffer
, 0);
4431 void radv_CmdBeginRenderPass2(
4432 VkCommandBuffer commandBuffer
,
4433 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4434 const VkSubpassBeginInfo
* pSubpassBeginInfo
)
4436 radv_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
4437 pSubpassBeginInfo
->contents
);
4440 void radv_CmdNextSubpass(
4441 VkCommandBuffer commandBuffer
,
4442 VkSubpassContents contents
)
4444 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4446 uint32_t prev_subpass
= radv_get_subpass_id(cmd_buffer
);
4447 radv_cmd_buffer_end_subpass(cmd_buffer
);
4448 radv_cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4451 void radv_CmdNextSubpass2(
4452 VkCommandBuffer commandBuffer
,
4453 const VkSubpassBeginInfo
* pSubpassBeginInfo
,
4454 const VkSubpassEndInfo
* pSubpassEndInfo
)
4456 radv_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
4459 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
4461 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
4462 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
4463 if (!radv_get_shader(pipeline
, stage
))
4466 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
4467 if (loc
->sgpr_idx
== -1)
4469 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
4470 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
4473 if (radv_pipeline_has_gs_copy_shader(pipeline
)) {
4474 struct radv_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
4475 if (loc
->sgpr_idx
!= -1) {
4476 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
4477 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
4483 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
4484 uint32_t vertex_count
,
4487 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
4488 radeon_emit(cmd_buffer
->cs
, vertex_count
);
4489 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
4490 S_0287F0_USE_OPAQUE(use_opaque
));
4494 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
4496 uint32_t index_count
)
4498 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, cmd_buffer
->state
.predicating
));
4499 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
4500 radeon_emit(cmd_buffer
->cs
, index_va
);
4501 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
4502 radeon_emit(cmd_buffer
->cs
, index_count
);
4503 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
4507 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
4509 uint32_t draw_count
,
4513 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4514 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
4515 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
4516 bool draw_id_enable
= radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
;
4517 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
4518 bool predicating
= cmd_buffer
->state
.predicating
;
4521 /* just reset draw state for vertex data */
4522 cmd_buffer
->state
.last_first_instance
= -1;
4523 cmd_buffer
->state
.last_num_instances
= -1;
4524 cmd_buffer
->state
.last_vertex_offset
= -1;
4526 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
4527 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
4528 PKT3_DRAW_INDIRECT
, 3, predicating
));
4530 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
4531 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
4532 radeon_emit(cs
, di_src_sel
);
4534 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
4535 PKT3_DRAW_INDIRECT_MULTI
,
4538 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
4539 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
4540 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
4541 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
4542 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
4543 radeon_emit(cs
, draw_count
); /* count */
4544 radeon_emit(cs
, count_va
); /* count_addr */
4545 radeon_emit(cs
, count_va
>> 32);
4546 radeon_emit(cs
, stride
); /* stride */
4547 radeon_emit(cs
, di_src_sel
);
4552 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
4553 const struct radv_draw_info
*info
)
4555 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4556 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
4557 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4559 if (info
->indirect
) {
4560 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
4561 uint64_t count_va
= 0;
4563 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
4565 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
4567 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
4569 radeon_emit(cs
, va
);
4570 radeon_emit(cs
, va
>> 32);
4572 if (info
->count_buffer
) {
4573 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
4574 count_va
+= info
->count_buffer
->offset
+
4575 info
->count_buffer_offset
;
4577 radv_cs_add_buffer(ws
, cs
, info
->count_buffer
->bo
);
4580 if (!state
->subpass
->view_mask
) {
4581 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
4588 for_each_bit(i
, state
->subpass
->view_mask
) {
4589 radv_emit_view_index(cmd_buffer
, i
);
4591 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
4599 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
4601 if (info
->vertex_offset
!= state
->last_vertex_offset
||
4602 info
->first_instance
!= state
->last_first_instance
) {
4603 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
4604 state
->pipeline
->graphics
.vtx_emit_num
);
4606 radeon_emit(cs
, info
->vertex_offset
);
4607 radeon_emit(cs
, info
->first_instance
);
4608 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
4610 state
->last_first_instance
= info
->first_instance
;
4611 state
->last_vertex_offset
= info
->vertex_offset
;
4614 if (state
->last_num_instances
!= info
->instance_count
) {
4615 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, false));
4616 radeon_emit(cs
, info
->instance_count
);
4617 state
->last_num_instances
= info
->instance_count
;
4620 if (info
->indexed
) {
4621 int index_size
= radv_get_vgt_index_size(state
->index_type
);
4624 /* Skip draw calls with 0-sized index buffers. They
4625 * cause a hang on some chips, like Navi10-14.
4627 if (!cmd_buffer
->state
.max_index_count
)
4630 index_va
= state
->index_va
;
4631 index_va
+= info
->first_index
* index_size
;
4633 if (!state
->subpass
->view_mask
) {
4634 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
4639 for_each_bit(i
, state
->subpass
->view_mask
) {
4640 radv_emit_view_index(cmd_buffer
, i
);
4642 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
4648 if (!state
->subpass
->view_mask
) {
4649 radv_cs_emit_draw_packet(cmd_buffer
,
4651 !!info
->strmout_buffer
);
4654 for_each_bit(i
, state
->subpass
->view_mask
) {
4655 radv_emit_view_index(cmd_buffer
, i
);
4657 radv_cs_emit_draw_packet(cmd_buffer
,
4659 !!info
->strmout_buffer
);
4667 * Vega and raven have a bug which triggers if there are multiple context
4668 * register contexts active at the same time with different scissor values.
4670 * There are two possible workarounds:
4671 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4672 * there is only ever 1 active set of scissor values at the same time.
4674 * 2) Whenever the hardware switches contexts we have to set the scissor
4675 * registers again even if it is a noop. That way the new context gets
4676 * the correct scissor values.
4678 * This implements option 2. radv_need_late_scissor_emission needs to
4679 * return true on affected HW if radv_emit_all_graphics_states sets
4680 * any context registers.
4682 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer
*cmd_buffer
,
4683 const struct radv_draw_info
*info
)
4685 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4687 if (!cmd_buffer
->device
->physical_device
->rad_info
.has_gfx9_scissor_bug
)
4690 if (cmd_buffer
->state
.context_roll_without_scissor_emitted
|| info
->strmout_buffer
)
4693 uint32_t used_states
= cmd_buffer
->state
.pipeline
->graphics
.needed_dynamic_state
| ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
4695 /* Index, vertex and streamout buffers don't change context regs, and
4696 * pipeline is already handled.
4698 used_states
&= ~(RADV_CMD_DIRTY_INDEX_BUFFER
|
4699 RADV_CMD_DIRTY_VERTEX_BUFFER
|
4700 RADV_CMD_DIRTY_STREAMOUT_BUFFER
|
4701 RADV_CMD_DIRTY_PIPELINE
);
4703 if (cmd_buffer
->state
.dirty
& used_states
)
4706 uint32_t primitive_reset_index
=
4707 radv_get_primitive_reset_index(cmd_buffer
);
4709 if (info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
&&
4710 primitive_reset_index
!= state
->last_primitive_reset_index
)
4717 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
4718 const struct radv_draw_info
*info
)
4720 bool late_scissor_emission
;
4722 if ((cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
) ||
4723 cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
4724 radv_emit_rbplus_state(cmd_buffer
);
4726 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
4727 radv_emit_graphics_pipeline(cmd_buffer
);
4729 /* This should be before the cmd_buffer->state.dirty is cleared
4730 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4731 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4732 late_scissor_emission
=
4733 radv_need_late_scissor_emission(cmd_buffer
, info
);
4735 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
4736 radv_emit_framebuffer_state(cmd_buffer
);
4738 if (info
->indexed
) {
4739 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
4740 radv_emit_index_buffer(cmd_buffer
, info
->indirect
);
4742 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4743 * so the state must be re-emitted before the next indexed
4746 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4747 cmd_buffer
->state
.last_index_type
= -1;
4748 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
4752 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
4754 radv_emit_draw_registers(cmd_buffer
, info
);
4756 if (late_scissor_emission
)
4757 radv_emit_scissor(cmd_buffer
);
4761 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
4762 const struct radv_draw_info
*info
)
4764 struct radeon_info
*rad_info
=
4765 &cmd_buffer
->device
->physical_device
->rad_info
;
4767 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
4768 bool pipeline_is_dirty
=
4769 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
4770 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
4772 ASSERTED
unsigned cdw_max
=
4773 radeon_check_space(cmd_buffer
->device
->ws
,
4774 cmd_buffer
->cs
, 4096);
4776 if (likely(!info
->indirect
)) {
4777 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4778 * no workaround for indirect draws, but we can at least skip
4781 if (unlikely(!info
->instance_count
))
4784 /* Handle count == 0. */
4785 if (unlikely(!info
->count
&& !info
->strmout_buffer
))
4789 radv_describe_draw(cmd_buffer
);
4791 /* Use optimal packet order based on whether we need to sync the
4794 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4795 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4796 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4797 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4798 /* If we have to wait for idle, set all states first, so that
4799 * all SET packets are processed in parallel with previous draw
4800 * calls. Then upload descriptors, set shader pointers, and
4801 * draw, and prefetch at the end. This ensures that the time
4802 * the CUs are idle is very short. (there are only SET_SH
4803 * packets between the wait and the draw)
4805 radv_emit_all_graphics_states(cmd_buffer
, info
);
4806 si_emit_cache_flush(cmd_buffer
);
4807 /* <-- CUs are idle here --> */
4809 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4811 radv_emit_draw_packets(cmd_buffer
, info
);
4812 /* <-- CUs are busy here --> */
4814 /* Start prefetches after the draw has been started. Both will
4815 * run in parallel, but starting the draw first is more
4818 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4819 radv_emit_prefetch_L2(cmd_buffer
,
4820 cmd_buffer
->state
.pipeline
, false);
4823 /* If we don't wait for idle, start prefetches first, then set
4824 * states, and draw at the end.
4826 si_emit_cache_flush(cmd_buffer
);
4828 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4829 /* Only prefetch the vertex shader and VBO descriptors
4830 * in order to start the draw as soon as possible.
4832 radv_emit_prefetch_L2(cmd_buffer
,
4833 cmd_buffer
->state
.pipeline
, true);
4836 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4838 radv_emit_all_graphics_states(cmd_buffer
, info
);
4839 radv_emit_draw_packets(cmd_buffer
, info
);
4841 /* Prefetch the remaining shaders after the draw has been
4844 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4845 radv_emit_prefetch_L2(cmd_buffer
,
4846 cmd_buffer
->state
.pipeline
, false);
4850 /* Workaround for a VGT hang when streamout is enabled.
4851 * It must be done after drawing.
4853 if (cmd_buffer
->state
.streamout
.streamout_enabled
&&
4854 (rad_info
->family
== CHIP_HAWAII
||
4855 rad_info
->family
== CHIP_TONGA
||
4856 rad_info
->family
== CHIP_FIJI
)) {
4857 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
;
4860 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4861 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_PS_PARTIAL_FLUSH
);
4865 VkCommandBuffer commandBuffer
,
4866 uint32_t vertexCount
,
4867 uint32_t instanceCount
,
4868 uint32_t firstVertex
,
4869 uint32_t firstInstance
)
4871 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4872 struct radv_draw_info info
= {};
4874 info
.count
= vertexCount
;
4875 info
.instance_count
= instanceCount
;
4876 info
.first_instance
= firstInstance
;
4877 info
.vertex_offset
= firstVertex
;
4879 radv_draw(cmd_buffer
, &info
);
4882 void radv_CmdDrawIndexed(
4883 VkCommandBuffer commandBuffer
,
4884 uint32_t indexCount
,
4885 uint32_t instanceCount
,
4886 uint32_t firstIndex
,
4887 int32_t vertexOffset
,
4888 uint32_t firstInstance
)
4890 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4891 struct radv_draw_info info
= {};
4893 info
.indexed
= true;
4894 info
.count
= indexCount
;
4895 info
.instance_count
= instanceCount
;
4896 info
.first_index
= firstIndex
;
4897 info
.vertex_offset
= vertexOffset
;
4898 info
.first_instance
= firstInstance
;
4900 radv_draw(cmd_buffer
, &info
);
4903 void radv_CmdDrawIndirect(
4904 VkCommandBuffer commandBuffer
,
4906 VkDeviceSize offset
,
4910 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4911 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4912 struct radv_draw_info info
= {};
4914 info
.count
= drawCount
;
4915 info
.indirect
= buffer
;
4916 info
.indirect_offset
= offset
;
4917 info
.stride
= stride
;
4919 radv_draw(cmd_buffer
, &info
);
4922 void radv_CmdDrawIndexedIndirect(
4923 VkCommandBuffer commandBuffer
,
4925 VkDeviceSize offset
,
4929 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4930 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4931 struct radv_draw_info info
= {};
4933 info
.indexed
= true;
4934 info
.count
= drawCount
;
4935 info
.indirect
= buffer
;
4936 info
.indirect_offset
= offset
;
4937 info
.stride
= stride
;
4939 radv_draw(cmd_buffer
, &info
);
4942 void radv_CmdDrawIndirectCount(
4943 VkCommandBuffer commandBuffer
,
4945 VkDeviceSize offset
,
4946 VkBuffer _countBuffer
,
4947 VkDeviceSize countBufferOffset
,
4948 uint32_t maxDrawCount
,
4951 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4952 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4953 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4954 struct radv_draw_info info
= {};
4956 info
.count
= maxDrawCount
;
4957 info
.indirect
= buffer
;
4958 info
.indirect_offset
= offset
;
4959 info
.count_buffer
= count_buffer
;
4960 info
.count_buffer_offset
= countBufferOffset
;
4961 info
.stride
= stride
;
4963 radv_draw(cmd_buffer
, &info
);
4966 void radv_CmdDrawIndexedIndirectCount(
4967 VkCommandBuffer commandBuffer
,
4969 VkDeviceSize offset
,
4970 VkBuffer _countBuffer
,
4971 VkDeviceSize countBufferOffset
,
4972 uint32_t maxDrawCount
,
4975 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4976 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4977 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4978 struct radv_draw_info info
= {};
4980 info
.indexed
= true;
4981 info
.count
= maxDrawCount
;
4982 info
.indirect
= buffer
;
4983 info
.indirect_offset
= offset
;
4984 info
.count_buffer
= count_buffer
;
4985 info
.count_buffer_offset
= countBufferOffset
;
4986 info
.stride
= stride
;
4988 radv_draw(cmd_buffer
, &info
);
4991 struct radv_dispatch_info
{
4993 * Determine the layout of the grid (in block units) to be used.
4998 * A starting offset for the grid. If unaligned is set, the offset
4999 * must still be aligned.
5001 uint32_t offsets
[3];
5003 * Whether it's an unaligned compute dispatch.
5008 * Indirect compute parameters resource.
5010 struct radv_buffer
*indirect
;
5011 uint64_t indirect_offset
;
5015 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
5016 const struct radv_dispatch_info
*info
)
5018 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
5019 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5020 unsigned dispatch_initiator
= cmd_buffer
->device
->dispatch_initiator
;
5021 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
5022 bool predicating
= cmd_buffer
->state
.predicating
;
5023 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5024 struct radv_userdata_info
*loc
;
5026 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
5027 AC_UD_CS_GRID_SIZE
);
5029 ASSERTED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
5031 if (compute_shader
->info
.wave_size
== 32) {
5032 assert(cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
5033 dispatch_initiator
|= S_00B800_CS_W32_EN(1);
5036 if (info
->indirect
) {
5037 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
5039 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
5041 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
5043 if (loc
->sgpr_idx
!= -1) {
5044 for (unsigned i
= 0; i
< 3; ++i
) {
5045 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
5046 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
5047 COPY_DATA_DST_SEL(COPY_DATA_REG
));
5048 radeon_emit(cs
, (va
+ 4 * i
));
5049 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
5050 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
5051 + loc
->sgpr_idx
* 4) >> 2) + i
);
5056 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
5057 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, predicating
) |
5058 PKT3_SHADER_TYPE_S(1));
5059 radeon_emit(cs
, va
);
5060 radeon_emit(cs
, va
>> 32);
5061 radeon_emit(cs
, dispatch_initiator
);
5063 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
5064 PKT3_SHADER_TYPE_S(1));
5066 radeon_emit(cs
, va
);
5067 radeon_emit(cs
, va
>> 32);
5069 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, predicating
) |
5070 PKT3_SHADER_TYPE_S(1));
5072 radeon_emit(cs
, dispatch_initiator
);
5075 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
5076 unsigned offsets
[3] = { info
->offsets
[0], info
->offsets
[1], info
->offsets
[2] };
5078 if (info
->unaligned
) {
5079 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
5080 unsigned remainder
[3];
5082 /* If aligned, these should be an entire block size,
5085 remainder
[0] = blocks
[0] + cs_block_size
[0] -
5086 align_u32_npot(blocks
[0], cs_block_size
[0]);
5087 remainder
[1] = blocks
[1] + cs_block_size
[1] -
5088 align_u32_npot(blocks
[1], cs_block_size
[1]);
5089 remainder
[2] = blocks
[2] + cs_block_size
[2] -
5090 align_u32_npot(blocks
[2], cs_block_size
[2]);
5092 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
5093 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
5094 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
5096 for(unsigned i
= 0; i
< 3; ++i
) {
5097 assert(offsets
[i
] % cs_block_size
[i
] == 0);
5098 offsets
[i
] /= cs_block_size
[i
];
5101 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5103 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
5104 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
5106 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
5107 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
5109 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
5110 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
5112 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
5115 if (loc
->sgpr_idx
!= -1) {
5116 assert(loc
->num_sgprs
== 3);
5118 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
5119 loc
->sgpr_idx
* 4, 3);
5120 radeon_emit(cs
, blocks
[0]);
5121 radeon_emit(cs
, blocks
[1]);
5122 radeon_emit(cs
, blocks
[2]);
5125 if (offsets
[0] || offsets
[1] || offsets
[2]) {
5126 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
5127 radeon_emit(cs
, offsets
[0]);
5128 radeon_emit(cs
, offsets
[1]);
5129 radeon_emit(cs
, offsets
[2]);
5131 /* The blocks in the packet are not counts but end values. */
5132 for (unsigned i
= 0; i
< 3; ++i
)
5133 blocks
[i
] += offsets
[i
];
5135 dispatch_initiator
|= S_00B800_FORCE_START_AT_000(1);
5138 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, predicating
) |
5139 PKT3_SHADER_TYPE_S(1));
5140 radeon_emit(cs
, blocks
[0]);
5141 radeon_emit(cs
, blocks
[1]);
5142 radeon_emit(cs
, blocks
[2]);
5143 radeon_emit(cs
, dispatch_initiator
);
5146 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5150 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
5152 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
5153 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
5157 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
5158 const struct radv_dispatch_info
*info
)
5160 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
5162 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
5163 bool pipeline_is_dirty
= pipeline
&&
5164 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
5166 radv_describe_dispatch(cmd_buffer
, 8, 8, 8);
5168 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5169 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5170 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
5171 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
5172 /* If we have to wait for idle, set all states first, so that
5173 * all SET packets are processed in parallel with previous draw
5174 * calls. Then upload descriptors, set shader pointers, and
5175 * dispatch, and prefetch at the end. This ensures that the
5176 * time the CUs are idle is very short. (there are only SET_SH
5177 * packets between the wait and the draw)
5179 radv_emit_compute_pipeline(cmd_buffer
);
5180 si_emit_cache_flush(cmd_buffer
);
5181 /* <-- CUs are idle here --> */
5183 radv_upload_compute_shader_descriptors(cmd_buffer
);
5185 radv_emit_dispatch_packets(cmd_buffer
, info
);
5186 /* <-- CUs are busy here --> */
5188 /* Start prefetches after the dispatch has been started. Both
5189 * will run in parallel, but starting the dispatch first is
5192 if (has_prefetch
&& pipeline_is_dirty
) {
5193 radv_emit_shader_prefetch(cmd_buffer
,
5194 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
5197 /* If we don't wait for idle, start prefetches first, then set
5198 * states, and dispatch at the end.
5200 si_emit_cache_flush(cmd_buffer
);
5202 if (has_prefetch
&& pipeline_is_dirty
) {
5203 radv_emit_shader_prefetch(cmd_buffer
,
5204 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
5207 radv_upload_compute_shader_descriptors(cmd_buffer
);
5209 radv_emit_compute_pipeline(cmd_buffer
);
5210 radv_emit_dispatch_packets(cmd_buffer
, info
);
5213 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_CS_PARTIAL_FLUSH
);
5216 void radv_CmdDispatchBase(
5217 VkCommandBuffer commandBuffer
,
5225 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5226 struct radv_dispatch_info info
= {};
5232 info
.offsets
[0] = base_x
;
5233 info
.offsets
[1] = base_y
;
5234 info
.offsets
[2] = base_z
;
5235 radv_dispatch(cmd_buffer
, &info
);
5238 void radv_CmdDispatch(
5239 VkCommandBuffer commandBuffer
,
5244 radv_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
5247 void radv_CmdDispatchIndirect(
5248 VkCommandBuffer commandBuffer
,
5250 VkDeviceSize offset
)
5252 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5253 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5254 struct radv_dispatch_info info
= {};
5256 info
.indirect
= buffer
;
5257 info
.indirect_offset
= offset
;
5259 radv_dispatch(cmd_buffer
, &info
);
5262 void radv_unaligned_dispatch(
5263 struct radv_cmd_buffer
*cmd_buffer
,
5268 struct radv_dispatch_info info
= {};
5275 radv_dispatch(cmd_buffer
, &info
);
5279 radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer
*cmd_buffer
)
5281 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
5282 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
5284 cmd_buffer
->state
.pass
= NULL
;
5285 cmd_buffer
->state
.subpass
= NULL
;
5286 cmd_buffer
->state
.attachments
= NULL
;
5287 cmd_buffer
->state
.framebuffer
= NULL
;
5288 cmd_buffer
->state
.subpass_sample_locs
= NULL
;
5291 void radv_CmdEndRenderPass(
5292 VkCommandBuffer commandBuffer
)
5294 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5296 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
5298 radv_cmd_buffer_end_subpass(cmd_buffer
);
5300 radv_cmd_buffer_end_render_pass(cmd_buffer
);
5303 void radv_CmdEndRenderPass2(
5304 VkCommandBuffer commandBuffer
,
5305 const VkSubpassEndInfo
* pSubpassEndInfo
)
5307 radv_CmdEndRenderPass(commandBuffer
);
5311 * For HTILE we have the following interesting clear words:
5312 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5313 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5314 * 0xfffffff0: Clear depth to 1.0
5315 * 0x00000000: Clear depth to 0.0
5317 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
5318 struct radv_image
*image
,
5319 const VkImageSubresourceRange
*range
)
5321 assert(range
->baseMipLevel
== 0);
5322 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
5323 VkImageAspectFlags aspects
= VK_IMAGE_ASPECT_DEPTH_BIT
;
5324 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5325 uint32_t htile_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
5326 VkClearDepthStencilValue value
= {};
5327 struct radv_barrier_data barrier
= {};
5329 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5330 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5332 barrier
.layout_transitions
.init_mask_ram
= 1;
5333 radv_describe_layout_transition(cmd_buffer
, &barrier
);
5335 state
->flush_bits
|= radv_clear_htile(cmd_buffer
, image
, range
, htile_value
);
5337 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5339 if (vk_format_is_stencil(image
->vk_format
))
5340 aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
5342 radv_set_ds_clear_metadata(cmd_buffer
, image
, range
, value
, aspects
);
5344 if (radv_image_is_tc_compat_htile(image
)) {
5345 /* Initialize the TC-compat metada value to 0 because by
5346 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5347 * need have to conditionally update its value when performing
5348 * a fast depth clear.
5350 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, range
, 0);
5354 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5355 struct radv_image
*image
,
5356 VkImageLayout src_layout
,
5357 bool src_render_loop
,
5358 VkImageLayout dst_layout
,
5359 bool dst_render_loop
,
5360 unsigned src_queue_mask
,
5361 unsigned dst_queue_mask
,
5362 const VkImageSubresourceRange
*range
,
5363 struct radv_sample_locations_state
*sample_locs
)
5365 if (!radv_image_has_htile(image
))
5368 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
5369 radv_initialize_htile(cmd_buffer
, image
, range
);
5370 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5371 radv_layout_is_htile_compressed(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5372 radv_initialize_htile(cmd_buffer
, image
, range
);
5373 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5374 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5375 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5376 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5378 radv_decompress_depth_stencil(cmd_buffer
, image
, range
,
5381 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5382 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5386 static void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
5387 struct radv_image
*image
,
5388 const VkImageSubresourceRange
*range
,
5391 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5392 struct radv_barrier_data barrier
= {};
5394 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5395 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5397 barrier
.layout_transitions
.init_mask_ram
= 1;
5398 radv_describe_layout_transition(cmd_buffer
, &barrier
);
5400 state
->flush_bits
|= radv_clear_cmask(cmd_buffer
, image
, range
, value
);
5402 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5405 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
5406 struct radv_image
*image
,
5407 const VkImageSubresourceRange
*range
)
5409 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5410 static const uint32_t fmask_clear_values
[4] = {
5416 uint32_t log2_samples
= util_logbase2(image
->info
.samples
);
5417 uint32_t value
= fmask_clear_values
[log2_samples
];
5418 struct radv_barrier_data barrier
= {};
5420 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5421 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5423 barrier
.layout_transitions
.init_mask_ram
= 1;
5424 radv_describe_layout_transition(cmd_buffer
, &barrier
);
5426 state
->flush_bits
|= radv_clear_fmask(cmd_buffer
, image
, range
, value
);
5428 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5431 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
5432 struct radv_image
*image
,
5433 const VkImageSubresourceRange
*range
, uint32_t value
)
5435 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5436 struct radv_barrier_data barrier
= {};
5439 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5440 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5442 barrier
.layout_transitions
.init_mask_ram
= 1;
5443 radv_describe_layout_transition(cmd_buffer
, &barrier
);
5445 state
->flush_bits
|= radv_clear_dcc(cmd_buffer
, image
, range
, value
);
5447 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX8
) {
5448 /* When DCC is enabled with mipmaps, some levels might not
5449 * support fast clears and we have to initialize them as "fully
5452 /* Compute the size of all fast clearable DCC levels. */
5453 for (unsigned i
= 0; i
< image
->planes
[0].surface
.num_dcc_levels
; i
++) {
5454 struct legacy_surf_level
*surf_level
=
5455 &image
->planes
[0].surface
.u
.legacy
.level
[i
];
5456 unsigned dcc_fast_clear_size
=
5457 surf_level
->dcc_slice_fast_clear_size
* image
->info
.array_size
;
5459 if (!dcc_fast_clear_size
)
5462 size
= surf_level
->dcc_offset
+ dcc_fast_clear_size
;
5465 /* Initialize the mipmap levels without DCC. */
5466 if (size
!= image
->planes
[0].surface
.dcc_size
) {
5467 state
->flush_bits
|=
5468 radv_fill_buffer(cmd_buffer
, image
->bo
,
5469 image
->offset
+ image
->dcc_offset
+ size
,
5470 image
->planes
[0].surface
.dcc_size
- size
,
5475 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5476 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5480 * Initialize DCC/FMASK/CMASK metadata for a color image.
5482 static void radv_init_color_image_metadata(struct radv_cmd_buffer
*cmd_buffer
,
5483 struct radv_image
*image
,
5484 VkImageLayout src_layout
,
5485 bool src_render_loop
,
5486 VkImageLayout dst_layout
,
5487 bool dst_render_loop
,
5488 unsigned src_queue_mask
,
5489 unsigned dst_queue_mask
,
5490 const VkImageSubresourceRange
*range
)
5492 if (radv_image_has_cmask(image
)) {
5493 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
5495 /* TODO: clarify this. */
5496 if (radv_image_has_fmask(image
)) {
5497 value
= 0xccccccccu
;
5500 radv_initialise_cmask(cmd_buffer
, image
, range
, value
);
5503 if (radv_image_has_fmask(image
)) {
5504 radv_initialize_fmask(cmd_buffer
, image
, range
);
5507 if (radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5508 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
5509 bool need_decompress_pass
= false;
5511 if (radv_layout_dcc_compressed(cmd_buffer
->device
, image
, dst_layout
,
5514 value
= 0x20202020u
;
5515 need_decompress_pass
= true;
5518 radv_initialize_dcc(cmd_buffer
, image
, range
, value
);
5520 radv_update_fce_metadata(cmd_buffer
, image
, range
,
5521 need_decompress_pass
);
5524 if (radv_image_has_cmask(image
) ||
5525 radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5526 uint32_t color_values
[2] = {};
5527 radv_set_color_clear_metadata(cmd_buffer
, image
, range
,
5533 * Handle color image transitions for DCC/FMASK/CMASK.
5535 static void radv_handle_color_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5536 struct radv_image
*image
,
5537 VkImageLayout src_layout
,
5538 bool src_render_loop
,
5539 VkImageLayout dst_layout
,
5540 bool dst_render_loop
,
5541 unsigned src_queue_mask
,
5542 unsigned dst_queue_mask
,
5543 const VkImageSubresourceRange
*range
)
5545 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
5546 radv_init_color_image_metadata(cmd_buffer
, image
,
5547 src_layout
, src_render_loop
,
5548 dst_layout
, dst_render_loop
,
5549 src_queue_mask
, dst_queue_mask
,
5554 if (radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5555 if (src_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
5556 radv_initialize_dcc(cmd_buffer
, image
, range
, 0xffffffffu
);
5557 } else if (radv_layout_dcc_compressed(cmd_buffer
->device
, image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5558 !radv_layout_dcc_compressed(cmd_buffer
->device
, image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5559 radv_decompress_dcc(cmd_buffer
, image
, range
);
5560 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5561 !radv_layout_can_fast_clear(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5562 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
5564 } else if (radv_image_has_cmask(image
) || radv_image_has_fmask(image
)) {
5565 bool fce_eliminate
= false, fmask_expand
= false;
5567 if (radv_layout_can_fast_clear(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5568 !radv_layout_can_fast_clear(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5569 fce_eliminate
= true;
5572 if (radv_image_has_fmask(image
)) {
5573 if (src_layout
!= VK_IMAGE_LAYOUT_GENERAL
&&
5574 dst_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
5575 /* A FMASK decompress is required before doing
5576 * a MSAA decompress using FMASK.
5578 fmask_expand
= true;
5582 if (fce_eliminate
|| fmask_expand
)
5583 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
5586 struct radv_barrier_data barrier
= {};
5587 barrier
.layout_transitions
.fmask_color_expand
= 1;
5588 radv_describe_layout_transition(cmd_buffer
, &barrier
);
5590 radv_expand_fmask_image_inplace(cmd_buffer
, image
, range
);
5595 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5596 struct radv_image
*image
,
5597 VkImageLayout src_layout
,
5598 bool src_render_loop
,
5599 VkImageLayout dst_layout
,
5600 bool dst_render_loop
,
5601 uint32_t src_family
,
5602 uint32_t dst_family
,
5603 const VkImageSubresourceRange
*range
,
5604 struct radv_sample_locations_state
*sample_locs
)
5606 if (image
->exclusive
&& src_family
!= dst_family
) {
5607 /* This is an acquire or a release operation and there will be
5608 * a corresponding release/acquire. Do the transition in the
5609 * most flexible queue. */
5611 assert(src_family
== cmd_buffer
->queue_family_index
||
5612 dst_family
== cmd_buffer
->queue_family_index
);
5614 if (src_family
== VK_QUEUE_FAMILY_EXTERNAL
||
5615 src_family
== VK_QUEUE_FAMILY_FOREIGN_EXT
)
5618 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
5621 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
5622 (src_family
== RADV_QUEUE_GENERAL
||
5623 dst_family
== RADV_QUEUE_GENERAL
))
5627 if (src_layout
== dst_layout
)
5630 unsigned src_queue_mask
=
5631 radv_image_queue_family_mask(image
, src_family
,
5632 cmd_buffer
->queue_family_index
);
5633 unsigned dst_queue_mask
=
5634 radv_image_queue_family_mask(image
, dst_family
,
5635 cmd_buffer
->queue_family_index
);
5637 if (vk_format_is_depth(image
->vk_format
)) {
5638 radv_handle_depth_image_transition(cmd_buffer
, image
,
5639 src_layout
, src_render_loop
,
5640 dst_layout
, dst_render_loop
,
5641 src_queue_mask
, dst_queue_mask
,
5642 range
, sample_locs
);
5644 radv_handle_color_image_transition(cmd_buffer
, image
,
5645 src_layout
, src_render_loop
,
5646 dst_layout
, dst_render_loop
,
5647 src_queue_mask
, dst_queue_mask
,
5652 struct radv_barrier_info
{
5653 enum rgp_barrier_reason reason
;
5654 uint32_t eventCount
;
5655 const VkEvent
*pEvents
;
5656 VkPipelineStageFlags srcStageMask
;
5657 VkPipelineStageFlags dstStageMask
;
5661 radv_barrier(struct radv_cmd_buffer
*cmd_buffer
,
5662 uint32_t memoryBarrierCount
,
5663 const VkMemoryBarrier
*pMemoryBarriers
,
5664 uint32_t bufferMemoryBarrierCount
,
5665 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
5666 uint32_t imageMemoryBarrierCount
,
5667 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
5668 const struct radv_barrier_info
*info
)
5670 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5671 enum radv_cmd_flush_bits src_flush_bits
= 0;
5672 enum radv_cmd_flush_bits dst_flush_bits
= 0;
5674 radv_describe_barrier_start(cmd_buffer
, info
->reason
);
5676 for (unsigned i
= 0; i
< info
->eventCount
; ++i
) {
5677 RADV_FROM_HANDLE(radv_event
, event
, info
->pEvents
[i
]);
5678 uint64_t va
= radv_buffer_get_va(event
->bo
);
5680 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
5682 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
5684 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, va
, 1, 0xffffffff);
5685 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5688 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
5689 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
,
5691 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
5695 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
5696 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
,
5698 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
5702 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
5703 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
5705 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
,
5707 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
5711 /* The Vulkan spec 1.1.98 says:
5713 * "An execution dependency with only
5714 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5715 * will only prevent that stage from executing in subsequently
5716 * submitted commands. As this stage does not perform any actual
5717 * execution, this is not observable - in effect, it does not delay
5718 * processing of subsequent commands. Similarly an execution dependency
5719 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5720 * will effectively not wait for any prior commands to complete."
5722 if (info
->dstStageMask
!= VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
)
5723 radv_stage_flush(cmd_buffer
, info
->srcStageMask
);
5724 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
5726 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
5727 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
5729 const struct VkSampleLocationsInfoEXT
*sample_locs_info
=
5730 vk_find_struct_const(pImageMemoryBarriers
[i
].pNext
,
5731 SAMPLE_LOCATIONS_INFO_EXT
);
5732 struct radv_sample_locations_state sample_locations
= {};
5734 if (sample_locs_info
) {
5735 assert(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
);
5736 sample_locations
.per_pixel
= sample_locs_info
->sampleLocationsPerPixel
;
5737 sample_locations
.grid_size
= sample_locs_info
->sampleLocationGridSize
;
5738 sample_locations
.count
= sample_locs_info
->sampleLocationsCount
;
5739 typed_memcpy(&sample_locations
.locations
[0],
5740 sample_locs_info
->pSampleLocations
,
5741 sample_locs_info
->sampleLocationsCount
);
5744 radv_handle_image_transition(cmd_buffer
, image
,
5745 pImageMemoryBarriers
[i
].oldLayout
,
5746 false, /* Outside of a renderpass we are never in a renderloop */
5747 pImageMemoryBarriers
[i
].newLayout
,
5748 false, /* Outside of a renderpass we are never in a renderloop */
5749 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
5750 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
5751 &pImageMemoryBarriers
[i
].subresourceRange
,
5752 sample_locs_info
? &sample_locations
: NULL
);
5755 /* Make sure CP DMA is idle because the driver might have performed a
5756 * DMA operation for copying or filling buffers/images.
5758 if (info
->srcStageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
5759 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
5760 si_cp_dma_wait_for_idle(cmd_buffer
);
5762 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
5764 radv_describe_barrier_end(cmd_buffer
);
5767 void radv_CmdPipelineBarrier(
5768 VkCommandBuffer commandBuffer
,
5769 VkPipelineStageFlags srcStageMask
,
5770 VkPipelineStageFlags destStageMask
,
5772 uint32_t memoryBarrierCount
,
5773 const VkMemoryBarrier
* pMemoryBarriers
,
5774 uint32_t bufferMemoryBarrierCount
,
5775 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5776 uint32_t imageMemoryBarrierCount
,
5777 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5779 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5780 struct radv_barrier_info info
;
5782 info
.reason
= RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER
;
5783 info
.eventCount
= 0;
5784 info
.pEvents
= NULL
;
5785 info
.srcStageMask
= srcStageMask
;
5786 info
.dstStageMask
= destStageMask
;
5788 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
5789 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5790 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5794 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
5795 struct radv_event
*event
,
5796 VkPipelineStageFlags stageMask
,
5799 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5800 uint64_t va
= radv_buffer_get_va(event
->bo
);
5802 si_emit_cache_flush(cmd_buffer
);
5804 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
5806 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 21);
5808 /* Flags that only require a top-of-pipe event. */
5809 VkPipelineStageFlags top_of_pipe_flags
=
5810 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
;
5812 /* Flags that only require a post-index-fetch event. */
5813 VkPipelineStageFlags post_index_fetch_flags
=
5815 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
5816 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
;
5818 /* Make sure CP DMA is idle because the driver might have performed a
5819 * DMA operation for copying or filling buffers/images.
5821 if (stageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
5822 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
5823 si_cp_dma_wait_for_idle(cmd_buffer
);
5825 /* TODO: Emit EOS events for syncing PS/CS stages. */
5827 if (!(stageMask
& ~top_of_pipe_flags
)) {
5828 /* Just need to sync the PFP engine. */
5829 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5830 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5831 S_370_WR_CONFIRM(1) |
5832 S_370_ENGINE_SEL(V_370_PFP
));
5833 radeon_emit(cs
, va
);
5834 radeon_emit(cs
, va
>> 32);
5835 radeon_emit(cs
, value
);
5836 } else if (!(stageMask
& ~post_index_fetch_flags
)) {
5837 /* Sync ME because PFP reads index and indirect buffers. */
5838 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5839 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5840 S_370_WR_CONFIRM(1) |
5841 S_370_ENGINE_SEL(V_370_ME
));
5842 radeon_emit(cs
, va
);
5843 radeon_emit(cs
, va
>> 32);
5844 radeon_emit(cs
, value
);
5846 /* Otherwise, sync all prior GPU work using an EOP event. */
5847 si_cs_emit_write_event_eop(cs
,
5848 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
5849 radv_cmd_buffer_uses_mec(cmd_buffer
),
5850 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
5852 EOP_DATA_SEL_VALUE_32BIT
, va
, value
,
5853 cmd_buffer
->gfx9_eop_bug_va
);
5856 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5859 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
5861 VkPipelineStageFlags stageMask
)
5863 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5864 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5866 write_event(cmd_buffer
, event
, stageMask
, 1);
5869 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
5871 VkPipelineStageFlags stageMask
)
5873 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5874 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5876 write_event(cmd_buffer
, event
, stageMask
, 0);
5879 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
5880 uint32_t eventCount
,
5881 const VkEvent
* pEvents
,
5882 VkPipelineStageFlags srcStageMask
,
5883 VkPipelineStageFlags dstStageMask
,
5884 uint32_t memoryBarrierCount
,
5885 const VkMemoryBarrier
* pMemoryBarriers
,
5886 uint32_t bufferMemoryBarrierCount
,
5887 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5888 uint32_t imageMemoryBarrierCount
,
5889 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5891 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5892 struct radv_barrier_info info
;
5894 info
.reason
= RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS
;
5895 info
.eventCount
= eventCount
;
5896 info
.pEvents
= pEvents
;
5897 info
.srcStageMask
= 0;
5899 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
5900 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5901 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5905 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer
,
5906 uint32_t deviceMask
)
5911 /* VK_EXT_conditional_rendering */
5912 void radv_CmdBeginConditionalRenderingEXT(
5913 VkCommandBuffer commandBuffer
,
5914 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5916 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5917 RADV_FROM_HANDLE(radv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5918 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5919 bool draw_visible
= true;
5920 uint64_t pred_value
= 0;
5921 uint64_t va
, new_va
;
5922 unsigned pred_offset
;
5924 va
= radv_buffer_get_va(buffer
->bo
) + pConditionalRenderingBegin
->offset
;
5926 /* By default, if the 32-bit value at offset in buffer memory is zero,
5927 * then the rendering commands are discarded, otherwise they are
5928 * executed as normal. If the inverted flag is set, all commands are
5929 * discarded if the value is non zero.
5931 if (pConditionalRenderingBegin
->flags
&
5932 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
) {
5933 draw_visible
= false;
5936 si_emit_cache_flush(cmd_buffer
);
5938 /* From the Vulkan spec 1.1.107:
5940 * "If the 32-bit value at offset in buffer memory is zero, then the
5941 * rendering commands are discarded, otherwise they are executed as
5942 * normal. If the value of the predicate in buffer memory changes while
5943 * conditional rendering is active, the rendering commands may be
5944 * discarded in an implementation-dependent way. Some implementations
5945 * may latch the value of the predicate upon beginning conditional
5946 * rendering while others may read it before every rendering command."
5948 * But, the AMD hardware treats the predicate as a 64-bit value which
5949 * means we need a workaround in the driver. Luckily, it's not required
5950 * to support if the value changes when predication is active.
5952 * The workaround is as follows:
5953 * 1) allocate a 64-value in the upload BO and initialize it to 0
5954 * 2) copy the 32-bit predicate value to the upload BO
5955 * 3) use the new allocated VA address for predication
5957 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5958 * in ME (+ sync PFP) instead of PFP.
5960 radv_cmd_buffer_upload_data(cmd_buffer
, 8, 16, &pred_value
, &pred_offset
);
5962 new_va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
) + pred_offset
;
5964 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
5965 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
5966 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
5967 COPY_DATA_WR_CONFIRM
);
5968 radeon_emit(cs
, va
);
5969 radeon_emit(cs
, va
>> 32);
5970 radeon_emit(cs
, new_va
);
5971 radeon_emit(cs
, new_va
>> 32);
5973 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
5976 /* Enable predication for this command buffer. */
5977 si_emit_set_predication_state(cmd_buffer
, draw_visible
, new_va
);
5978 cmd_buffer
->state
.predicating
= true;
5980 /* Store conditional rendering user info. */
5981 cmd_buffer
->state
.predication_type
= draw_visible
;
5982 cmd_buffer
->state
.predication_va
= new_va
;
5985 void radv_CmdEndConditionalRenderingEXT(
5986 VkCommandBuffer commandBuffer
)
5988 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5990 /* Disable predication for this command buffer. */
5991 si_emit_set_predication_state(cmd_buffer
, false, 0);
5992 cmd_buffer
->state
.predicating
= false;
5994 /* Reset conditional rendering user info. */
5995 cmd_buffer
->state
.predication_type
= -1;
5996 cmd_buffer
->state
.predication_va
= 0;
5999 /* VK_EXT_transform_feedback */
6000 void radv_CmdBindTransformFeedbackBuffersEXT(
6001 VkCommandBuffer commandBuffer
,
6002 uint32_t firstBinding
,
6003 uint32_t bindingCount
,
6004 const VkBuffer
* pBuffers
,
6005 const VkDeviceSize
* pOffsets
,
6006 const VkDeviceSize
* pSizes
)
6008 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6009 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
6010 uint8_t enabled_mask
= 0;
6012 assert(firstBinding
+ bindingCount
<= MAX_SO_BUFFERS
);
6013 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
6014 uint32_t idx
= firstBinding
+ i
;
6016 sb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
6017 sb
[idx
].offset
= pOffsets
[i
];
6019 if (!pSizes
|| pSizes
[i
] == VK_WHOLE_SIZE
) {
6020 sb
[idx
].size
= sb
[idx
].buffer
->size
- sb
[idx
].offset
;
6022 sb
[idx
].size
= pSizes
[i
];
6025 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
6026 sb
[idx
].buffer
->bo
);
6028 enabled_mask
|= 1 << idx
;
6031 cmd_buffer
->state
.streamout
.enabled_mask
|= enabled_mask
;
6033 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
6037 radv_emit_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
)
6039 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6040 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6042 radeon_set_context_reg_seq(cs
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
6044 S_028B94_STREAMOUT_0_EN(so
->streamout_enabled
) |
6045 S_028B94_RAST_STREAM(0) |
6046 S_028B94_STREAMOUT_1_EN(so
->streamout_enabled
) |
6047 S_028B94_STREAMOUT_2_EN(so
->streamout_enabled
) |
6048 S_028B94_STREAMOUT_3_EN(so
->streamout_enabled
));
6049 radeon_emit(cs
, so
->hw_enabled_mask
&
6050 so
->enabled_stream_buffers_mask
);
6052 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
6056 radv_set_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
, bool enable
)
6058 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6059 bool old_streamout_enabled
= so
->streamout_enabled
;
6060 uint32_t old_hw_enabled_mask
= so
->hw_enabled_mask
;
6062 so
->streamout_enabled
= enable
;
6064 so
->hw_enabled_mask
= so
->enabled_mask
|
6065 (so
->enabled_mask
<< 4) |
6066 (so
->enabled_mask
<< 8) |
6067 (so
->enabled_mask
<< 12);
6069 if (!cmd_buffer
->device
->physical_device
->use_ngg_streamout
&&
6070 ((old_streamout_enabled
!= so
->streamout_enabled
) ||
6071 (old_hw_enabled_mask
!= so
->hw_enabled_mask
)))
6072 radv_emit_streamout_enable(cmd_buffer
);
6074 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
) {
6075 cmd_buffer
->gds_needed
= true;
6076 cmd_buffer
->gds_oa_needed
= true;
6080 static void radv_flush_vgt_streamout(struct radv_cmd_buffer
*cmd_buffer
)
6082 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6083 unsigned reg_strmout_cntl
;
6085 /* The register is at different places on different ASICs. */
6086 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
6087 reg_strmout_cntl
= R_0300FC_CP_STRMOUT_CNTL
;
6088 radeon_set_uconfig_reg(cs
, reg_strmout_cntl
, 0);
6090 reg_strmout_cntl
= R_0084FC_CP_STRMOUT_CNTL
;
6091 radeon_set_config_reg(cs
, reg_strmout_cntl
, 0);
6094 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
6095 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH
) | EVENT_INDEX(0));
6097 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
6098 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
); /* wait until the register is equal to the reference value */
6099 radeon_emit(cs
, reg_strmout_cntl
>> 2); /* register */
6101 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6102 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6103 radeon_emit(cs
, 4); /* poll interval */
6107 radv_emit_streamout_begin(struct radv_cmd_buffer
*cmd_buffer
,
6108 uint32_t firstCounterBuffer
,
6109 uint32_t counterBufferCount
,
6110 const VkBuffer
*pCounterBuffers
,
6111 const VkDeviceSize
*pCounterBufferOffsets
)
6114 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
6115 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6116 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6119 radv_flush_vgt_streamout(cmd_buffer
);
6121 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6122 for_each_bit(i
, so
->enabled_mask
) {
6123 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6124 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6125 counter_buffer_idx
= -1;
6127 /* AMD GCN binds streamout buffers as shader resources.
6128 * VGT only counts primitives and tells the shader through
6131 radeon_set_context_reg_seq(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 2);
6132 radeon_emit(cs
, sb
[i
].size
>> 2); /* BUFFER_SIZE (in DW) */
6133 radeon_emit(cs
, so
->stride_in_dw
[i
]); /* VTX_STRIDE (in DW) */
6135 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
6137 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
6138 /* The array of counter buffers is optional. */
6139 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6140 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
6142 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6145 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
6146 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
6147 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6148 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM
)); /* control */
6149 radeon_emit(cs
, 0); /* unused */
6150 radeon_emit(cs
, 0); /* unused */
6151 radeon_emit(cs
, va
); /* src address lo */
6152 radeon_emit(cs
, va
>> 32); /* src address hi */
6154 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6156 /* Start from the beginning. */
6157 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
6158 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
6159 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6160 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET
)); /* control */
6161 radeon_emit(cs
, 0); /* unused */
6162 radeon_emit(cs
, 0); /* unused */
6163 radeon_emit(cs
, 0); /* unused */
6164 radeon_emit(cs
, 0); /* unused */
6168 radv_set_streamout_enable(cmd_buffer
, true);
6172 gfx10_emit_streamout_begin(struct radv_cmd_buffer
*cmd_buffer
,
6173 uint32_t firstCounterBuffer
,
6174 uint32_t counterBufferCount
,
6175 const VkBuffer
*pCounterBuffers
,
6176 const VkDeviceSize
*pCounterBufferOffsets
)
6178 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6179 unsigned last_target
= util_last_bit(so
->enabled_mask
) - 1;
6180 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6183 assert(cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
6184 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6186 /* Sync because the next streamout operation will overwrite GDS and we
6187 * have to make sure it's idle.
6188 * TODO: Improve by tracking if there is a streamout operation in
6191 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
6192 si_emit_cache_flush(cmd_buffer
);
6194 for_each_bit(i
, so
->enabled_mask
) {
6195 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6196 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6197 counter_buffer_idx
= -1;
6199 bool append
= counter_buffer_idx
>= 0 &&
6200 pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
];
6204 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6206 va
+= radv_buffer_get_va(buffer
->bo
);
6207 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6209 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6212 radeon_emit(cs
, PKT3(PKT3_DMA_DATA
, 5, 0));
6213 radeon_emit(cs
, S_411_SRC_SEL(append
? V_411_SRC_ADDR_TC_L2
: V_411_DATA
) |
6214 S_411_DST_SEL(V_411_GDS
) |
6215 S_411_CP_SYNC(i
== last_target
));
6216 radeon_emit(cs
, va
);
6217 radeon_emit(cs
, va
>> 32);
6218 radeon_emit(cs
, 4 * i
); /* destination in GDS */
6220 radeon_emit(cs
, S_414_BYTE_COUNT_GFX9(4) |
6221 S_414_DISABLE_WR_CONFIRM_GFX9(i
!= last_target
));
6224 radv_set_streamout_enable(cmd_buffer
, true);
6227 void radv_CmdBeginTransformFeedbackEXT(
6228 VkCommandBuffer commandBuffer
,
6229 uint32_t firstCounterBuffer
,
6230 uint32_t counterBufferCount
,
6231 const VkBuffer
* pCounterBuffers
,
6232 const VkDeviceSize
* pCounterBufferOffsets
)
6234 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6236 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
) {
6237 gfx10_emit_streamout_begin(cmd_buffer
,
6238 firstCounterBuffer
, counterBufferCount
,
6239 pCounterBuffers
, pCounterBufferOffsets
);
6241 radv_emit_streamout_begin(cmd_buffer
,
6242 firstCounterBuffer
, counterBufferCount
,
6243 pCounterBuffers
, pCounterBufferOffsets
);
6248 radv_emit_streamout_end(struct radv_cmd_buffer
*cmd_buffer
,
6249 uint32_t firstCounterBuffer
,
6250 uint32_t counterBufferCount
,
6251 const VkBuffer
*pCounterBuffers
,
6252 const VkDeviceSize
*pCounterBufferOffsets
)
6254 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6255 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6258 radv_flush_vgt_streamout(cmd_buffer
);
6260 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6261 for_each_bit(i
, so
->enabled_mask
) {
6262 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6263 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6264 counter_buffer_idx
= -1;
6266 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
6267 /* The array of counters buffer is optional. */
6268 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6269 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
6271 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6273 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
6274 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
6275 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6276 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE
) |
6277 STRMOUT_STORE_BUFFER_FILLED_SIZE
); /* control */
6278 radeon_emit(cs
, va
); /* dst address lo */
6279 radeon_emit(cs
, va
>> 32); /* dst address hi */
6280 radeon_emit(cs
, 0); /* unused */
6281 radeon_emit(cs
, 0); /* unused */
6283 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6286 /* Deactivate transform feedback by zeroing the buffer size.
6287 * The counters (primitives generated, primitives emitted) may
6288 * be enabled even if there is not buffer bound. This ensures
6289 * that the primitives-emitted query won't increment.
6291 radeon_set_context_reg(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 0);
6293 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
6296 radv_set_streamout_enable(cmd_buffer
, false);
6300 gfx10_emit_streamout_end(struct radv_cmd_buffer
*cmd_buffer
,
6301 uint32_t firstCounterBuffer
,
6302 uint32_t counterBufferCount
,
6303 const VkBuffer
*pCounterBuffers
,
6304 const VkDeviceSize
*pCounterBufferOffsets
)
6306 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6307 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6310 assert(cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
6311 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6313 for_each_bit(i
, so
->enabled_mask
) {
6314 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6315 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6316 counter_buffer_idx
= -1;
6318 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
6319 /* The array of counters buffer is optional. */
6320 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6321 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
6323 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6325 si_cs_emit_write_event_eop(cs
,
6326 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
6327 radv_cmd_buffer_uses_mec(cmd_buffer
),
6328 V_028A90_PS_DONE
, 0,
6331 va
, EOP_DATA_GDS(i
, 1), 0);
6333 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6337 radv_set_streamout_enable(cmd_buffer
, false);
6340 void radv_CmdEndTransformFeedbackEXT(
6341 VkCommandBuffer commandBuffer
,
6342 uint32_t firstCounterBuffer
,
6343 uint32_t counterBufferCount
,
6344 const VkBuffer
* pCounterBuffers
,
6345 const VkDeviceSize
* pCounterBufferOffsets
)
6347 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6349 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
) {
6350 gfx10_emit_streamout_end(cmd_buffer
,
6351 firstCounterBuffer
, counterBufferCount
,
6352 pCounterBuffers
, pCounterBufferOffsets
);
6354 radv_emit_streamout_end(cmd_buffer
,
6355 firstCounterBuffer
, counterBufferCount
,
6356 pCounterBuffers
, pCounterBufferOffsets
);
6360 void radv_CmdDrawIndirectByteCountEXT(
6361 VkCommandBuffer commandBuffer
,
6362 uint32_t instanceCount
,
6363 uint32_t firstInstance
,
6364 VkBuffer _counterBuffer
,
6365 VkDeviceSize counterBufferOffset
,
6366 uint32_t counterOffset
,
6367 uint32_t vertexStride
)
6369 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6370 RADV_FROM_HANDLE(radv_buffer
, counterBuffer
, _counterBuffer
);
6371 struct radv_draw_info info
= {};
6373 info
.instance_count
= instanceCount
;
6374 info
.first_instance
= firstInstance
;
6375 info
.strmout_buffer
= counterBuffer
;
6376 info
.strmout_buffer_offset
= counterBufferOffset
;
6377 info
.stride
= vertexStride
;
6379 radv_draw(cmd_buffer
, &info
);
6382 /* VK_AMD_buffer_marker */
6383 void radv_CmdWriteBufferMarkerAMD(
6384 VkCommandBuffer commandBuffer
,
6385 VkPipelineStageFlagBits pipelineStage
,
6387 VkDeviceSize dstOffset
,
6390 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6391 RADV_FROM_HANDLE(radv_buffer
, buffer
, dstBuffer
);
6392 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6393 uint64_t va
= radv_buffer_get_va(buffer
->bo
) + dstOffset
;
6395 si_emit_cache_flush(cmd_buffer
);
6397 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 12);
6399 if (!(pipelineStage
& ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
)) {
6400 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
6401 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_IMM
) |
6402 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
6403 COPY_DATA_WR_CONFIRM
);
6404 radeon_emit(cs
, marker
);
6406 radeon_emit(cs
, va
);
6407 radeon_emit(cs
, va
>> 32);
6409 si_cs_emit_write_event_eop(cs
,
6410 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
6411 radv_cmd_buffer_uses_mec(cmd_buffer
),
6412 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
6414 EOP_DATA_SEL_VALUE_32BIT
,
6416 cmd_buffer
->gfx9_eop_bug_va
);
6419 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);