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radv: set WD_SWITCH_ON_EOP=1 when drawing primitives from a stream output buffer
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range);
61
62 const struct radv_dynamic_state default_dynamic_state = {
63 .viewport = {
64 .count = 0,
65 },
66 .scissor = {
67 .count = 0,
68 },
69 .line_width = 1.0f,
70 .depth_bias = {
71 .bias = 0.0f,
72 .clamp = 0.0f,
73 .slope = 0.0f,
74 },
75 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
76 .depth_bounds = {
77 .min = 0.0f,
78 .max = 1.0f,
79 },
80 .stencil_compare_mask = {
81 .front = ~0u,
82 .back = ~0u,
83 },
84 .stencil_write_mask = {
85 .front = ~0u,
86 .back = ~0u,
87 },
88 .stencil_reference = {
89 .front = 0u,
90 .back = 0u,
91 },
92 };
93
94 static void
95 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
96 const struct radv_dynamic_state *src)
97 {
98 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
99 uint32_t copy_mask = src->mask;
100 uint32_t dest_mask = 0;
101
102 /* Make sure to copy the number of viewports/scissors because they can
103 * only be specified at pipeline creation time.
104 */
105 dest->viewport.count = src->viewport.count;
106 dest->scissor.count = src->scissor.count;
107 dest->discard_rectangle.count = src->discard_rectangle.count;
108
109 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
110 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
111 src->viewport.count * sizeof(VkViewport))) {
112 typed_memcpy(dest->viewport.viewports,
113 src->viewport.viewports,
114 src->viewport.count);
115 dest_mask |= RADV_DYNAMIC_VIEWPORT;
116 }
117 }
118
119 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
120 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
121 src->scissor.count * sizeof(VkRect2D))) {
122 typed_memcpy(dest->scissor.scissors,
123 src->scissor.scissors, src->scissor.count);
124 dest_mask |= RADV_DYNAMIC_SCISSOR;
125 }
126 }
127
128 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
129 if (dest->line_width != src->line_width) {
130 dest->line_width = src->line_width;
131 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
132 }
133 }
134
135 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
136 if (memcmp(&dest->depth_bias, &src->depth_bias,
137 sizeof(src->depth_bias))) {
138 dest->depth_bias = src->depth_bias;
139 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
144 if (memcmp(&dest->blend_constants, &src->blend_constants,
145 sizeof(src->blend_constants))) {
146 typed_memcpy(dest->blend_constants,
147 src->blend_constants, 4);
148 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
149 }
150 }
151
152 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
153 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
154 sizeof(src->depth_bounds))) {
155 dest->depth_bounds = src->depth_bounds;
156 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
161 if (memcmp(&dest->stencil_compare_mask,
162 &src->stencil_compare_mask,
163 sizeof(src->stencil_compare_mask))) {
164 dest->stencil_compare_mask = src->stencil_compare_mask;
165 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
166 }
167 }
168
169 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
170 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
171 sizeof(src->stencil_write_mask))) {
172 dest->stencil_write_mask = src->stencil_write_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
178 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
179 sizeof(src->stencil_reference))) {
180 dest->stencil_reference = src->stencil_reference;
181 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
186 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
187 src->discard_rectangle.count * sizeof(VkRect2D))) {
188 typed_memcpy(dest->discard_rectangle.rectangles,
189 src->discard_rectangle.rectangles,
190 src->discard_rectangle.count);
191 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
192 }
193 }
194
195 cmd_buffer->state.dirty |= dest_mask;
196 }
197
198 static void
199 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
200 struct radv_pipeline *pipeline)
201 {
202 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
203 struct radv_shader_info *info;
204
205 if (!pipeline->streamout_shader)
206 return;
207
208 info = &pipeline->streamout_shader->info.info;
209 for (int i = 0; i < MAX_SO_BUFFERS; i++)
210 so->stride_in_dw[i] = info->so.strides[i];
211
212 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
213 }
214
215 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
216 {
217 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
218 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
219 }
220
221 enum ring_type radv_queue_family_to_ring(int f) {
222 switch (f) {
223 case RADV_QUEUE_GENERAL:
224 return RING_GFX;
225 case RADV_QUEUE_COMPUTE:
226 return RING_COMPUTE;
227 case RADV_QUEUE_TRANSFER:
228 return RING_DMA;
229 default:
230 unreachable("Unknown queue family");
231 }
232 }
233
234 static VkResult radv_create_cmd_buffer(
235 struct radv_device * device,
236 struct radv_cmd_pool * pool,
237 VkCommandBufferLevel level,
238 VkCommandBuffer* pCommandBuffer)
239 {
240 struct radv_cmd_buffer *cmd_buffer;
241 unsigned ring;
242 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
243 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
244 if (cmd_buffer == NULL)
245 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
246
247 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
248 cmd_buffer->device = device;
249 cmd_buffer->pool = pool;
250 cmd_buffer->level = level;
251
252 if (pool) {
253 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
254 cmd_buffer->queue_family_index = pool->queue_family_index;
255
256 } else {
257 /* Init the pool_link so we can safely call list_del when we destroy
258 * the command buffer
259 */
260 list_inithead(&cmd_buffer->pool_link);
261 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
262 }
263
264 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
265
266 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
267 if (!cmd_buffer->cs) {
268 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
269 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
270 }
271
272 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
273
274 list_inithead(&cmd_buffer->upload.list);
275
276 return VK_SUCCESS;
277 }
278
279 static void
280 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
281 {
282 list_del(&cmd_buffer->pool_link);
283
284 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
285 &cmd_buffer->upload.list, list) {
286 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
287 list_del(&up->list);
288 free(up);
289 }
290
291 if (cmd_buffer->upload.upload_bo)
292 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
293 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
294
295 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
296 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
297
298 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
299 }
300
301 static VkResult
302 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
303 {
304
305 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
306
307 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
308 &cmd_buffer->upload.list, list) {
309 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
310 list_del(&up->list);
311 free(up);
312 }
313
314 cmd_buffer->push_constant_stages = 0;
315 cmd_buffer->scratch_size_needed = 0;
316 cmd_buffer->compute_scratch_size_needed = 0;
317 cmd_buffer->esgs_ring_size_needed = 0;
318 cmd_buffer->gsvs_ring_size_needed = 0;
319 cmd_buffer->tess_rings_needed = false;
320 cmd_buffer->sample_positions_needed = false;
321
322 if (cmd_buffer->upload.upload_bo)
323 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
324 cmd_buffer->upload.upload_bo);
325 cmd_buffer->upload.offset = 0;
326
327 cmd_buffer->record_result = VK_SUCCESS;
328
329 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
330 cmd_buffer->descriptors[i].dirty = 0;
331 cmd_buffer->descriptors[i].valid = 0;
332 cmd_buffer->descriptors[i].push_dirty = false;
333 }
334
335 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
336 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
337 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
338 unsigned fence_offset, eop_bug_offset;
339 void *fence_ptr;
340
341 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
342 &fence_ptr);
343
344 cmd_buffer->gfx9_fence_va =
345 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
346 cmd_buffer->gfx9_fence_va += fence_offset;
347
348 /* Allocate a buffer for the EOP bug on GFX9. */
349 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
350 &eop_bug_offset, &fence_ptr);
351 cmd_buffer->gfx9_eop_bug_va =
352 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
353 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
354 }
355
356 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
357
358 return cmd_buffer->record_result;
359 }
360
361 static bool
362 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
363 uint64_t min_needed)
364 {
365 uint64_t new_size;
366 struct radeon_winsys_bo *bo;
367 struct radv_cmd_buffer_upload *upload;
368 struct radv_device *device = cmd_buffer->device;
369
370 new_size = MAX2(min_needed, 16 * 1024);
371 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
372
373 bo = device->ws->buffer_create(device->ws,
374 new_size, 4096,
375 RADEON_DOMAIN_GTT,
376 RADEON_FLAG_CPU_ACCESS|
377 RADEON_FLAG_NO_INTERPROCESS_SHARING |
378 RADEON_FLAG_32BIT,
379 RADV_BO_PRIORITY_UPLOAD_BUFFER);
380
381 if (!bo) {
382 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
383 return false;
384 }
385
386 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
387 if (cmd_buffer->upload.upload_bo) {
388 upload = malloc(sizeof(*upload));
389
390 if (!upload) {
391 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
392 device->ws->buffer_destroy(bo);
393 return false;
394 }
395
396 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
397 list_add(&upload->list, &cmd_buffer->upload.list);
398 }
399
400 cmd_buffer->upload.upload_bo = bo;
401 cmd_buffer->upload.size = new_size;
402 cmd_buffer->upload.offset = 0;
403 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
404
405 if (!cmd_buffer->upload.map) {
406 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
407 return false;
408 }
409
410 return true;
411 }
412
413 bool
414 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
415 unsigned size,
416 unsigned alignment,
417 unsigned *out_offset,
418 void **ptr)
419 {
420 assert(util_is_power_of_two_nonzero(alignment));
421
422 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
423 if (offset + size > cmd_buffer->upload.size) {
424 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
425 return false;
426 offset = 0;
427 }
428
429 *out_offset = offset;
430 *ptr = cmd_buffer->upload.map + offset;
431
432 cmd_buffer->upload.offset = offset + size;
433 return true;
434 }
435
436 bool
437 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
438 unsigned size, unsigned alignment,
439 const void *data, unsigned *out_offset)
440 {
441 uint8_t *ptr;
442
443 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
444 out_offset, (void **)&ptr))
445 return false;
446
447 if (ptr)
448 memcpy(ptr, data, size);
449
450 return true;
451 }
452
453 static void
454 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
455 unsigned count, const uint32_t *data)
456 {
457 struct radeon_cmdbuf *cs = cmd_buffer->cs;
458
459 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
460
461 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
462 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
463 S_370_WR_CONFIRM(1) |
464 S_370_ENGINE_SEL(V_370_ME));
465 radeon_emit(cs, va);
466 radeon_emit(cs, va >> 32);
467 radeon_emit_array(cs, data, count);
468 }
469
470 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
471 {
472 struct radv_device *device = cmd_buffer->device;
473 struct radeon_cmdbuf *cs = cmd_buffer->cs;
474 uint64_t va;
475
476 va = radv_buffer_get_va(device->trace_bo);
477 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
478 va += 4;
479
480 ++cmd_buffer->state.trace_id;
481 radv_emit_write_data_packet(cmd_buffer, va, 1,
482 &cmd_buffer->state.trace_id);
483
484 radeon_check_space(cmd_buffer->device->ws, cs, 2);
485
486 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
487 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
488 }
489
490 static void
491 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
492 enum radv_cmd_flush_bits flags)
493 {
494 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
495 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
496 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
497
498 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
499
500 /* Force wait for graphics or compute engines to be idle. */
501 si_cs_emit_cache_flush(cmd_buffer->cs,
502 cmd_buffer->device->physical_device->rad_info.chip_class,
503 &cmd_buffer->gfx9_fence_idx,
504 cmd_buffer->gfx9_fence_va,
505 radv_cmd_buffer_uses_mec(cmd_buffer),
506 flags, cmd_buffer->gfx9_eop_bug_va);
507 }
508
509 if (unlikely(cmd_buffer->device->trace_bo))
510 radv_cmd_buffer_trace_emit(cmd_buffer);
511 }
512
513 static void
514 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
515 struct radv_pipeline *pipeline, enum ring_type ring)
516 {
517 struct radv_device *device = cmd_buffer->device;
518 uint32_t data[2];
519 uint64_t va;
520
521 va = radv_buffer_get_va(device->trace_bo);
522
523 switch (ring) {
524 case RING_GFX:
525 va += 8;
526 break;
527 case RING_COMPUTE:
528 va += 16;
529 break;
530 default:
531 assert(!"invalid ring type");
532 }
533
534 data[0] = (uintptr_t)pipeline;
535 data[1] = (uintptr_t)pipeline >> 32;
536
537 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
538 }
539
540 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
541 VkPipelineBindPoint bind_point,
542 struct radv_descriptor_set *set,
543 unsigned idx)
544 {
545 struct radv_descriptor_state *descriptors_state =
546 radv_get_descriptors_state(cmd_buffer, bind_point);
547
548 descriptors_state->sets[idx] = set;
549
550 descriptors_state->valid |= (1u << idx); /* active descriptors */
551 descriptors_state->dirty |= (1u << idx);
552 }
553
554 static void
555 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
556 VkPipelineBindPoint bind_point)
557 {
558 struct radv_descriptor_state *descriptors_state =
559 radv_get_descriptors_state(cmd_buffer, bind_point);
560 struct radv_device *device = cmd_buffer->device;
561 uint32_t data[MAX_SETS * 2] = {};
562 uint64_t va;
563 unsigned i;
564 va = radv_buffer_get_va(device->trace_bo) + 24;
565
566 for_each_bit(i, descriptors_state->valid) {
567 struct radv_descriptor_set *set = descriptors_state->sets[i];
568 data[i * 2] = (uintptr_t)set;
569 data[i * 2 + 1] = (uintptr_t)set >> 32;
570 }
571
572 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
573 }
574
575 struct radv_userdata_info *
576 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
577 gl_shader_stage stage,
578 int idx)
579 {
580 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
581 return &shader->info.user_sgprs_locs.shader_data[idx];
582 }
583
584 static void
585 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
586 struct radv_pipeline *pipeline,
587 gl_shader_stage stage,
588 int idx, uint64_t va)
589 {
590 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
591 uint32_t base_reg = pipeline->user_data_0[stage];
592 if (loc->sgpr_idx == -1)
593 return;
594
595 assert(loc->num_sgprs == 1);
596
597 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
598 base_reg + loc->sgpr_idx * 4, va, false);
599 }
600
601 static void
602 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
603 struct radv_pipeline *pipeline,
604 struct radv_descriptor_state *descriptors_state,
605 gl_shader_stage stage)
606 {
607 struct radv_device *device = cmd_buffer->device;
608 struct radeon_cmdbuf *cs = cmd_buffer->cs;
609 uint32_t sh_base = pipeline->user_data_0[stage];
610 struct radv_userdata_locations *locs =
611 &pipeline->shaders[stage]->info.user_sgprs_locs;
612 unsigned mask = locs->descriptor_sets_enabled;
613
614 mask &= descriptors_state->dirty & descriptors_state->valid;
615
616 while (mask) {
617 int start, count;
618
619 u_bit_scan_consecutive_range(&mask, &start, &count);
620
621 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
622 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
623
624 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
625 for (int i = 0; i < count; i++) {
626 struct radv_descriptor_set *set =
627 descriptors_state->sets[start + i];
628
629 radv_emit_shader_pointer_body(device, cs, set->va, true);
630 }
631 }
632 }
633
634 static void
635 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
636 struct radv_pipeline *pipeline,
637 gl_shader_stage stage,
638 int idx, int count, uint32_t *values)
639 {
640 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
641 uint32_t base_reg = pipeline->user_data_0[stage];
642 if (loc->sgpr_idx == -1)
643 return;
644
645 assert(loc->num_sgprs == count);
646
647 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
648 radeon_emit_array(cmd_buffer->cs, values, count);
649 }
650
651 static void
652 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
653 struct radv_pipeline *pipeline)
654 {
655 int num_samples = pipeline->graphics.ms.num_samples;
656 struct radv_multisample_state *ms = &pipeline->graphics.ms;
657 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
658
659 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
660 cmd_buffer->sample_positions_needed = true;
661
662 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
663 return;
664
665 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
666 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
667 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
668
669 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
670
671 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
672
673 /* GFX9: Flush DFSM when the AA mode changes. */
674 if (cmd_buffer->device->dfsm_allowed) {
675 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
676 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
677 }
678
679 cmd_buffer->state.context_roll_without_scissor_emitted = true;
680 }
681
682 static void
683 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
684 struct radv_shader_variant *shader)
685 {
686 uint64_t va;
687
688 if (!shader)
689 return;
690
691 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
692
693 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
694 }
695
696 static void
697 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
698 struct radv_pipeline *pipeline,
699 bool vertex_stage_only)
700 {
701 struct radv_cmd_state *state = &cmd_buffer->state;
702 uint32_t mask = state->prefetch_L2_mask;
703
704 if (vertex_stage_only) {
705 /* Fast prefetch path for starting draws as soon as possible.
706 */
707 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
708 RADV_PREFETCH_VBO_DESCRIPTORS);
709 }
710
711 if (mask & RADV_PREFETCH_VS)
712 radv_emit_shader_prefetch(cmd_buffer,
713 pipeline->shaders[MESA_SHADER_VERTEX]);
714
715 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
716 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
717
718 if (mask & RADV_PREFETCH_TCS)
719 radv_emit_shader_prefetch(cmd_buffer,
720 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
721
722 if (mask & RADV_PREFETCH_TES)
723 radv_emit_shader_prefetch(cmd_buffer,
724 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
725
726 if (mask & RADV_PREFETCH_GS) {
727 radv_emit_shader_prefetch(cmd_buffer,
728 pipeline->shaders[MESA_SHADER_GEOMETRY]);
729 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
730 }
731
732 if (mask & RADV_PREFETCH_PS)
733 radv_emit_shader_prefetch(cmd_buffer,
734 pipeline->shaders[MESA_SHADER_FRAGMENT]);
735
736 state->prefetch_L2_mask &= ~mask;
737 }
738
739 static void
740 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
741 {
742 if (!cmd_buffer->device->physical_device->rbplus_allowed)
743 return;
744
745 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
746 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
747 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
748
749 unsigned sx_ps_downconvert = 0;
750 unsigned sx_blend_opt_epsilon = 0;
751 unsigned sx_blend_opt_control = 0;
752
753 for (unsigned i = 0; i < subpass->color_count; ++i) {
754 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
755 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
756 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
757 continue;
758 }
759
760 int idx = subpass->color_attachments[i].attachment;
761 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
762
763 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
764 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
765 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
766 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
767
768 bool has_alpha, has_rgb;
769
770 /* Set if RGB and A are present. */
771 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
772
773 if (format == V_028C70_COLOR_8 ||
774 format == V_028C70_COLOR_16 ||
775 format == V_028C70_COLOR_32)
776 has_rgb = !has_alpha;
777 else
778 has_rgb = true;
779
780 /* Check the colormask and export format. */
781 if (!(colormask & 0x7))
782 has_rgb = false;
783 if (!(colormask & 0x8))
784 has_alpha = false;
785
786 if (spi_format == V_028714_SPI_SHADER_ZERO) {
787 has_rgb = false;
788 has_alpha = false;
789 }
790
791 /* Disable value checking for disabled channels. */
792 if (!has_rgb)
793 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
794 if (!has_alpha)
795 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
796
797 /* Enable down-conversion for 32bpp and smaller formats. */
798 switch (format) {
799 case V_028C70_COLOR_8:
800 case V_028C70_COLOR_8_8:
801 case V_028C70_COLOR_8_8_8_8:
802 /* For 1 and 2-channel formats, use the superset thereof. */
803 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
804 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
805 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
806 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
807 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
808 }
809 break;
810
811 case V_028C70_COLOR_5_6_5:
812 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
813 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
814 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
815 }
816 break;
817
818 case V_028C70_COLOR_1_5_5_5:
819 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
820 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
821 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
822 }
823 break;
824
825 case V_028C70_COLOR_4_4_4_4:
826 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
827 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
828 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
829 }
830 break;
831
832 case V_028C70_COLOR_32:
833 if (swap == V_028C70_SWAP_STD &&
834 spi_format == V_028714_SPI_SHADER_32_R)
835 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
836 else if (swap == V_028C70_SWAP_ALT_REV &&
837 spi_format == V_028714_SPI_SHADER_32_AR)
838 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
839 break;
840
841 case V_028C70_COLOR_16:
842 case V_028C70_COLOR_16_16:
843 /* For 1-channel formats, use the superset thereof. */
844 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
845 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
846 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
847 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
848 if (swap == V_028C70_SWAP_STD ||
849 swap == V_028C70_SWAP_STD_REV)
850 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
851 else
852 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
853 }
854 break;
855
856 case V_028C70_COLOR_10_11_11:
857 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
858 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
859 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
860 }
861 break;
862
863 case V_028C70_COLOR_2_10_10_10:
864 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
865 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
866 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
867 }
868 break;
869 }
870 }
871
872 for (unsigned i = subpass->color_count; i < 8; ++i) {
873 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
874 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
875 }
876 /* TODO: avoid redundantly setting context registers */
877 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
878 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
879 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
880 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
881
882 cmd_buffer->state.context_roll_without_scissor_emitted = true;
883 }
884
885 static void
886 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
887 {
888 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
889
890 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
891 return;
892
893 radv_update_multisample_state(cmd_buffer, pipeline);
894
895 cmd_buffer->scratch_size_needed =
896 MAX2(cmd_buffer->scratch_size_needed,
897 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
898
899 if (!cmd_buffer->state.emitted_pipeline ||
900 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
901 pipeline->graphics.can_use_guardband)
902 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
903
904 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
905
906 if (!cmd_buffer->state.emitted_pipeline ||
907 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
908 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
909 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
910 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
911 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
912 cmd_buffer->state.context_roll_without_scissor_emitted = true;
913 }
914
915 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
916 if (!pipeline->shaders[i])
917 continue;
918
919 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
920 pipeline->shaders[i]->bo);
921 }
922
923 if (radv_pipeline_has_gs(pipeline))
924 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
925 pipeline->gs_copy_shader->bo);
926
927 if (unlikely(cmd_buffer->device->trace_bo))
928 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
929
930 cmd_buffer->state.emitted_pipeline = pipeline;
931
932 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
933 }
934
935 static void
936 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
937 {
938 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
939 cmd_buffer->state.dynamic.viewport.viewports);
940 }
941
942 static void
943 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
944 {
945 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
946
947 si_write_scissors(cmd_buffer->cs, 0, count,
948 cmd_buffer->state.dynamic.scissor.scissors,
949 cmd_buffer->state.dynamic.viewport.viewports,
950 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
951
952 cmd_buffer->state.context_roll_without_scissor_emitted = false;
953 }
954
955 static void
956 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
957 {
958 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
959 return;
960
961 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
962 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
963 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
964 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
965 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
966 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
967 S_028214_BR_Y(rect.offset.y + rect.extent.height));
968 }
969 }
970
971 static void
972 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
973 {
974 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
975
976 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
977 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
978 }
979
980 static void
981 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
982 {
983 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
984
985 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
986 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
987 }
988
989 static void
990 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
991 {
992 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
993
994 radeon_set_context_reg_seq(cmd_buffer->cs,
995 R_028430_DB_STENCILREFMASK, 2);
996 radeon_emit(cmd_buffer->cs,
997 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
998 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
999 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1000 S_028430_STENCILOPVAL(1));
1001 radeon_emit(cmd_buffer->cs,
1002 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1003 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1004 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1005 S_028434_STENCILOPVAL_BF(1));
1006 }
1007
1008 static void
1009 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1010 {
1011 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1012
1013 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1014 fui(d->depth_bounds.min));
1015 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1016 fui(d->depth_bounds.max));
1017 }
1018
1019 static void
1020 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1021 {
1022 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1023 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1024 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1025
1026
1027 radeon_set_context_reg_seq(cmd_buffer->cs,
1028 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1029 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1030 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1031 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1032 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1033 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1034 }
1035
1036 static void
1037 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1038 int index,
1039 struct radv_attachment_info *att,
1040 struct radv_image *image,
1041 VkImageLayout layout)
1042 {
1043 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1044 struct radv_color_buffer_info *cb = &att->cb;
1045 uint32_t cb_color_info = cb->cb_color_info;
1046
1047 if (!radv_layout_dcc_compressed(image, layout,
1048 radv_image_queue_family_mask(image,
1049 cmd_buffer->queue_family_index,
1050 cmd_buffer->queue_family_index))) {
1051 cb_color_info &= C_028C70_DCC_ENABLE;
1052 }
1053
1054 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1055 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1056 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1057 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1058 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1059 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1060 radeon_emit(cmd_buffer->cs, cb_color_info);
1061 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1062 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1063 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1064 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1065 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1066 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1067
1068 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1069 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1070 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1071
1072 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1073 cb->cb_mrt_epitch);
1074 } else {
1075 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1076 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1077 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1078 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1079 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1080 radeon_emit(cmd_buffer->cs, cb_color_info);
1081 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1082 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1083 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1084 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1085 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1086 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1087
1088 if (is_vi) { /* DCC BASE */
1089 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1090 }
1091 }
1092
1093 if (radv_image_has_dcc(image)) {
1094 /* Drawing with DCC enabled also compresses colorbuffers. */
1095 radv_update_dcc_metadata(cmd_buffer, image, true);
1096 }
1097 }
1098
1099 static void
1100 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1101 struct radv_ds_buffer_info *ds,
1102 struct radv_image *image, VkImageLayout layout,
1103 bool requires_cond_exec)
1104 {
1105 uint32_t db_z_info = ds->db_z_info;
1106 uint32_t db_z_info_reg;
1107
1108 if (!radv_image_is_tc_compat_htile(image))
1109 return;
1110
1111 if (!radv_layout_has_htile(image, layout,
1112 radv_image_queue_family_mask(image,
1113 cmd_buffer->queue_family_index,
1114 cmd_buffer->queue_family_index))) {
1115 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1116 }
1117
1118 db_z_info &= C_028040_ZRANGE_PRECISION;
1119
1120 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1121 db_z_info_reg = R_028038_DB_Z_INFO;
1122 } else {
1123 db_z_info_reg = R_028040_DB_Z_INFO;
1124 }
1125
1126 /* When we don't know the last fast clear value we need to emit a
1127 * conditional packet that will eventually skip the following
1128 * SET_CONTEXT_REG packet.
1129 */
1130 if (requires_cond_exec) {
1131 uint64_t va = radv_buffer_get_va(image->bo);
1132 va += image->offset + image->tc_compat_zrange_offset;
1133
1134 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1135 radeon_emit(cmd_buffer->cs, va);
1136 radeon_emit(cmd_buffer->cs, va >> 32);
1137 radeon_emit(cmd_buffer->cs, 0);
1138 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1139 }
1140
1141 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1142 }
1143
1144 static void
1145 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1146 struct radv_ds_buffer_info *ds,
1147 struct radv_image *image,
1148 VkImageLayout layout)
1149 {
1150 uint32_t db_z_info = ds->db_z_info;
1151 uint32_t db_stencil_info = ds->db_stencil_info;
1152
1153 if (!radv_layout_has_htile(image, layout,
1154 radv_image_queue_family_mask(image,
1155 cmd_buffer->queue_family_index,
1156 cmd_buffer->queue_family_index))) {
1157 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1158 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1159 }
1160
1161 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1162 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1163
1164
1165 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1166 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1167 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1168 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1169 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1170
1171 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1172 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1173 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1174 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1175 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1176 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1177 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1178 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1179 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1180 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1181 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1182
1183 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1184 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1185 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1186 } else {
1187 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1188
1189 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1190 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1191 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1192 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1193 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1194 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1195 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1196 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1197 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1198 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1199
1200 }
1201
1202 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1203 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1204
1205 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1206 ds->pa_su_poly_offset_db_fmt_cntl);
1207 }
1208
1209 /**
1210 * Update the fast clear depth/stencil values if the image is bound as a
1211 * depth/stencil buffer.
1212 */
1213 static void
1214 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1215 struct radv_image *image,
1216 VkClearDepthStencilValue ds_clear_value,
1217 VkImageAspectFlags aspects)
1218 {
1219 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1220 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1221 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1222 struct radv_attachment_info *att;
1223 uint32_t att_idx;
1224
1225 if (!framebuffer || !subpass)
1226 return;
1227
1228 if (!subpass->depth_stencil_attachment)
1229 return;
1230
1231 att_idx = subpass->depth_stencil_attachment->attachment;
1232 att = &framebuffer->attachments[att_idx];
1233 if (att->attachment->image != image)
1234 return;
1235
1236 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1237 radeon_emit(cs, ds_clear_value.stencil);
1238 radeon_emit(cs, fui(ds_clear_value.depth));
1239
1240 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1241 * only needed when clearing Z to 0.0.
1242 */
1243 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1244 ds_clear_value.depth == 0.0) {
1245 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1246
1247 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1248 layout, false);
1249 }
1250
1251 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1252 }
1253
1254 /**
1255 * Set the clear depth/stencil values to the image's metadata.
1256 */
1257 static void
1258 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1259 struct radv_image *image,
1260 VkClearDepthStencilValue ds_clear_value,
1261 VkImageAspectFlags aspects)
1262 {
1263 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1264 uint64_t va = radv_buffer_get_va(image->bo);
1265 unsigned reg_offset = 0, reg_count = 0;
1266
1267 va += image->offset + image->clear_value_offset;
1268
1269 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1270 ++reg_count;
1271 } else {
1272 ++reg_offset;
1273 va += 4;
1274 }
1275 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1276 ++reg_count;
1277
1278 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
1279 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1280 S_370_WR_CONFIRM(1) |
1281 S_370_ENGINE_SEL(V_370_PFP));
1282 radeon_emit(cs, va);
1283 radeon_emit(cs, va >> 32);
1284 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1285 radeon_emit(cs, ds_clear_value.stencil);
1286 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1287 radeon_emit(cs, fui(ds_clear_value.depth));
1288 }
1289
1290 /**
1291 * Update the TC-compat metadata value for this image.
1292 */
1293 static void
1294 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1295 struct radv_image *image,
1296 uint32_t value)
1297 {
1298 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1299 uint64_t va = radv_buffer_get_va(image->bo);
1300 va += image->offset + image->tc_compat_zrange_offset;
1301
1302 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1303 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1304 S_370_WR_CONFIRM(1) |
1305 S_370_ENGINE_SEL(V_370_PFP));
1306 radeon_emit(cs, va);
1307 radeon_emit(cs, va >> 32);
1308 radeon_emit(cs, value);
1309 }
1310
1311 static void
1312 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1313 struct radv_image *image,
1314 VkClearDepthStencilValue ds_clear_value)
1315 {
1316 uint64_t va = radv_buffer_get_va(image->bo);
1317 va += image->offset + image->tc_compat_zrange_offset;
1318 uint32_t cond_val;
1319
1320 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1321 * depth clear value is 0.0f.
1322 */
1323 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1324
1325 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1326 }
1327
1328 /**
1329 * Update the clear depth/stencil values for this image.
1330 */
1331 void
1332 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1333 struct radv_image *image,
1334 VkClearDepthStencilValue ds_clear_value,
1335 VkImageAspectFlags aspects)
1336 {
1337 assert(radv_image_has_htile(image));
1338
1339 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1340
1341 if (radv_image_is_tc_compat_htile(image) &&
1342 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1343 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1344 ds_clear_value);
1345 }
1346
1347 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1348 aspects);
1349 }
1350
1351 /**
1352 * Load the clear depth/stencil values from the image's metadata.
1353 */
1354 static void
1355 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1356 struct radv_image *image)
1357 {
1358 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1359 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1360 uint64_t va = radv_buffer_get_va(image->bo);
1361 unsigned reg_offset = 0, reg_count = 0;
1362
1363 va += image->offset + image->clear_value_offset;
1364
1365 if (!radv_image_has_htile(image))
1366 return;
1367
1368 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1369 ++reg_count;
1370 } else {
1371 ++reg_offset;
1372 va += 4;
1373 }
1374 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1375 ++reg_count;
1376
1377 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1378
1379 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1380 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1381 radeon_emit(cs, va);
1382 radeon_emit(cs, va >> 32);
1383 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1384 radeon_emit(cs, reg_count);
1385 } else {
1386 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1387 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1388 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1389 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1390 radeon_emit(cs, va);
1391 radeon_emit(cs, va >> 32);
1392 radeon_emit(cs, reg >> 2);
1393 radeon_emit(cs, 0);
1394
1395 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1396 radeon_emit(cs, 0);
1397 }
1398 }
1399
1400 /*
1401 * With DCC some colors don't require CMASK elimination before being
1402 * used as a texture. This sets a predicate value to determine if the
1403 * cmask eliminate is required.
1404 */
1405 void
1406 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1407 struct radv_image *image, bool value)
1408 {
1409 uint64_t pred_val = value;
1410 uint64_t va = radv_buffer_get_va(image->bo);
1411 va += image->offset + image->fce_pred_offset;
1412
1413 assert(radv_image_has_dcc(image));
1414
1415 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1416 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1417 S_370_WR_CONFIRM(1) |
1418 S_370_ENGINE_SEL(V_370_PFP));
1419 radeon_emit(cmd_buffer->cs, va);
1420 radeon_emit(cmd_buffer->cs, va >> 32);
1421 radeon_emit(cmd_buffer->cs, pred_val);
1422 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1423 }
1424
1425 /**
1426 * Update the DCC predicate to reflect the compression state.
1427 */
1428 void
1429 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1430 struct radv_image *image, bool value)
1431 {
1432 uint64_t pred_val = value;
1433 uint64_t va = radv_buffer_get_va(image->bo);
1434 va += image->offset + image->dcc_pred_offset;
1435
1436 assert(radv_image_has_dcc(image));
1437
1438 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1439 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1440 S_370_WR_CONFIRM(1) |
1441 S_370_ENGINE_SEL(V_370_PFP));
1442 radeon_emit(cmd_buffer->cs, va);
1443 radeon_emit(cmd_buffer->cs, va >> 32);
1444 radeon_emit(cmd_buffer->cs, pred_val);
1445 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1446 }
1447
1448 /**
1449 * Update the fast clear color values if the image is bound as a color buffer.
1450 */
1451 static void
1452 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1453 struct radv_image *image,
1454 int cb_idx,
1455 uint32_t color_values[2])
1456 {
1457 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1458 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1459 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1460 struct radv_attachment_info *att;
1461 uint32_t att_idx;
1462
1463 if (!framebuffer || !subpass)
1464 return;
1465
1466 att_idx = subpass->color_attachments[cb_idx].attachment;
1467 if (att_idx == VK_ATTACHMENT_UNUSED)
1468 return;
1469
1470 att = &framebuffer->attachments[att_idx];
1471 if (att->attachment->image != image)
1472 return;
1473
1474 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1475 radeon_emit(cs, color_values[0]);
1476 radeon_emit(cs, color_values[1]);
1477
1478 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1479 }
1480
1481 /**
1482 * Set the clear color values to the image's metadata.
1483 */
1484 static void
1485 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1486 struct radv_image *image,
1487 uint32_t color_values[2])
1488 {
1489 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1490 uint64_t va = radv_buffer_get_va(image->bo);
1491
1492 va += image->offset + image->clear_value_offset;
1493
1494 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1495
1496 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, cmd_buffer->state.predicating));
1497 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1498 S_370_WR_CONFIRM(1) |
1499 S_370_ENGINE_SEL(V_370_PFP));
1500 radeon_emit(cs, va);
1501 radeon_emit(cs, va >> 32);
1502 radeon_emit(cs, color_values[0]);
1503 radeon_emit(cs, color_values[1]);
1504 }
1505
1506 /**
1507 * Update the clear color values for this image.
1508 */
1509 void
1510 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1511 struct radv_image *image,
1512 int cb_idx,
1513 uint32_t color_values[2])
1514 {
1515 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1516
1517 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1518
1519 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1520 color_values);
1521 }
1522
1523 /**
1524 * Load the clear color values from the image's metadata.
1525 */
1526 static void
1527 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1528 struct radv_image *image,
1529 int cb_idx)
1530 {
1531 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1532 uint64_t va = radv_buffer_get_va(image->bo);
1533
1534 va += image->offset + image->clear_value_offset;
1535
1536 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1537 return;
1538
1539 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1540
1541 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1542 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1543 radeon_emit(cs, va);
1544 radeon_emit(cs, va >> 32);
1545 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1546 radeon_emit(cs, 2);
1547 } else {
1548 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1549 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1550 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1551 COPY_DATA_COUNT_SEL);
1552 radeon_emit(cs, va);
1553 radeon_emit(cs, va >> 32);
1554 radeon_emit(cs, reg >> 2);
1555 radeon_emit(cs, 0);
1556
1557 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1558 radeon_emit(cs, 0);
1559 }
1560 }
1561
1562 static void
1563 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1564 {
1565 int i;
1566 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1567 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1568 unsigned num_bpp64_colorbufs = 0;
1569
1570 /* this may happen for inherited secondary recording */
1571 if (!framebuffer)
1572 return;
1573
1574 for (i = 0; i < 8; ++i) {
1575 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1576 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1577 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1578 continue;
1579 }
1580
1581 int idx = subpass->color_attachments[i].attachment;
1582 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1583 struct radv_image *image = att->attachment->image;
1584 VkImageLayout layout = subpass->color_attachments[i].layout;
1585
1586 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1587
1588 assert(att->attachment->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1589 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1590 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1591
1592 radv_load_color_clear_metadata(cmd_buffer, image, i);
1593
1594 if (image->planes[0].surface.bpe >= 8)
1595 num_bpp64_colorbufs++;
1596 }
1597
1598 if (subpass->depth_stencil_attachment) {
1599 int idx = subpass->depth_stencil_attachment->attachment;
1600 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1601 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1602 struct radv_image *image = att->attachment->image;
1603 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1604 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1605 cmd_buffer->queue_family_index,
1606 cmd_buffer->queue_family_index);
1607 /* We currently don't support writing decompressed HTILE */
1608 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1609 radv_layout_is_htile_compressed(image, layout, queue_mask));
1610
1611 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1612
1613 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1614 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1615 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1616 }
1617 radv_load_ds_clear_metadata(cmd_buffer, image);
1618 } else {
1619 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1620 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1621 else
1622 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1623
1624 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1625 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1626 }
1627 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1628 S_028208_BR_X(framebuffer->width) |
1629 S_028208_BR_Y(framebuffer->height));
1630
1631 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1632 uint8_t watermark = 4; /* Default value for VI. */
1633
1634 /* For optimal DCC performance. */
1635 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1636 if (num_bpp64_colorbufs >= 5) {
1637 watermark = 8;
1638 } else {
1639 watermark = 6;
1640 }
1641 }
1642
1643 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1644 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1645 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1646 }
1647
1648 if (cmd_buffer->device->dfsm_allowed) {
1649 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1650 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1651 }
1652
1653 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1654 }
1655
1656 static void
1657 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1658 {
1659 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1660 struct radv_cmd_state *state = &cmd_buffer->state;
1661
1662 if (state->index_type != state->last_index_type) {
1663 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1664 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1665 2, state->index_type);
1666 } else {
1667 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1668 radeon_emit(cs, state->index_type);
1669 }
1670
1671 state->last_index_type = state->index_type;
1672 }
1673
1674 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1675 radeon_emit(cs, state->index_va);
1676 radeon_emit(cs, state->index_va >> 32);
1677
1678 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1679 radeon_emit(cs, state->max_index_count);
1680
1681 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1682 }
1683
1684 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1685 {
1686 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1687 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1688 uint32_t pa_sc_mode_cntl_1 =
1689 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1690 uint32_t db_count_control;
1691
1692 if(!cmd_buffer->state.active_occlusion_queries) {
1693 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1694 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1695 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1696 has_perfect_queries) {
1697 /* Re-enable out-of-order rasterization if the
1698 * bound pipeline supports it and if it's has
1699 * been disabled before starting any perfect
1700 * occlusion queries.
1701 */
1702 radeon_set_context_reg(cmd_buffer->cs,
1703 R_028A4C_PA_SC_MODE_CNTL_1,
1704 pa_sc_mode_cntl_1);
1705 }
1706 }
1707 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1708 } else {
1709 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1710 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1711
1712 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1713 db_count_control =
1714 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1715 S_028004_SAMPLE_RATE(sample_rate) |
1716 S_028004_ZPASS_ENABLE(1) |
1717 S_028004_SLICE_EVEN_ENABLE(1) |
1718 S_028004_SLICE_ODD_ENABLE(1);
1719
1720 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1721 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1722 has_perfect_queries) {
1723 /* If the bound pipeline has enabled
1724 * out-of-order rasterization, we should
1725 * disable it before starting any perfect
1726 * occlusion queries.
1727 */
1728 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1729
1730 radeon_set_context_reg(cmd_buffer->cs,
1731 R_028A4C_PA_SC_MODE_CNTL_1,
1732 pa_sc_mode_cntl_1);
1733 }
1734 } else {
1735 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1736 S_028004_SAMPLE_RATE(sample_rate);
1737 }
1738 }
1739
1740 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1741
1742 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1743 }
1744
1745 static void
1746 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1747 {
1748 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1749
1750 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1751 radv_emit_viewport(cmd_buffer);
1752
1753 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1754 !cmd_buffer->device->physical_device->has_scissor_bug)
1755 radv_emit_scissor(cmd_buffer);
1756
1757 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1758 radv_emit_line_width(cmd_buffer);
1759
1760 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1761 radv_emit_blend_constants(cmd_buffer);
1762
1763 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1764 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1765 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1766 radv_emit_stencil(cmd_buffer);
1767
1768 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1769 radv_emit_depth_bounds(cmd_buffer);
1770
1771 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1772 radv_emit_depth_bias(cmd_buffer);
1773
1774 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1775 radv_emit_discard_rectangle(cmd_buffer);
1776
1777 cmd_buffer->state.dirty &= ~states;
1778 }
1779
1780 static void
1781 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1782 VkPipelineBindPoint bind_point)
1783 {
1784 struct radv_descriptor_state *descriptors_state =
1785 radv_get_descriptors_state(cmd_buffer, bind_point);
1786 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1787 unsigned bo_offset;
1788
1789 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1790 set->mapped_ptr,
1791 &bo_offset))
1792 return;
1793
1794 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1795 set->va += bo_offset;
1796 }
1797
1798 static void
1799 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1800 VkPipelineBindPoint bind_point)
1801 {
1802 struct radv_descriptor_state *descriptors_state =
1803 radv_get_descriptors_state(cmd_buffer, bind_point);
1804 uint32_t size = MAX_SETS * 4;
1805 uint32_t offset;
1806 void *ptr;
1807
1808 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1809 256, &offset, &ptr))
1810 return;
1811
1812 for (unsigned i = 0; i < MAX_SETS; i++) {
1813 uint32_t *uptr = ((uint32_t *)ptr) + i;
1814 uint64_t set_va = 0;
1815 struct radv_descriptor_set *set = descriptors_state->sets[i];
1816 if (descriptors_state->valid & (1u << i))
1817 set_va = set->va;
1818 uptr[0] = set_va & 0xffffffff;
1819 }
1820
1821 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1822 va += offset;
1823
1824 if (cmd_buffer->state.pipeline) {
1825 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1826 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1827 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1828
1829 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1830 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1831 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1832
1833 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1834 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1835 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1836
1837 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1838 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1839 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1840
1841 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1842 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1843 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1844 }
1845
1846 if (cmd_buffer->state.compute_pipeline)
1847 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1848 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1849 }
1850
1851 static void
1852 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1853 VkShaderStageFlags stages)
1854 {
1855 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1856 VK_PIPELINE_BIND_POINT_COMPUTE :
1857 VK_PIPELINE_BIND_POINT_GRAPHICS;
1858 struct radv_descriptor_state *descriptors_state =
1859 radv_get_descriptors_state(cmd_buffer, bind_point);
1860 struct radv_cmd_state *state = &cmd_buffer->state;
1861 bool flush_indirect_descriptors;
1862
1863 if (!descriptors_state->dirty)
1864 return;
1865
1866 if (descriptors_state->push_dirty)
1867 radv_flush_push_descriptors(cmd_buffer, bind_point);
1868
1869 flush_indirect_descriptors =
1870 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1871 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1872 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1873 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1874
1875 if (flush_indirect_descriptors)
1876 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1877
1878 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1879 cmd_buffer->cs,
1880 MAX_SETS * MESA_SHADER_STAGES * 4);
1881
1882 if (cmd_buffer->state.pipeline) {
1883 radv_foreach_stage(stage, stages) {
1884 if (!cmd_buffer->state.pipeline->shaders[stage])
1885 continue;
1886
1887 radv_emit_descriptor_pointers(cmd_buffer,
1888 cmd_buffer->state.pipeline,
1889 descriptors_state, stage);
1890 }
1891 }
1892
1893 if (cmd_buffer->state.compute_pipeline &&
1894 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1895 radv_emit_descriptor_pointers(cmd_buffer,
1896 cmd_buffer->state.compute_pipeline,
1897 descriptors_state,
1898 MESA_SHADER_COMPUTE);
1899 }
1900
1901 descriptors_state->dirty = 0;
1902 descriptors_state->push_dirty = false;
1903
1904 assert(cmd_buffer->cs->cdw <= cdw_max);
1905
1906 if (unlikely(cmd_buffer->device->trace_bo))
1907 radv_save_descriptors(cmd_buffer, bind_point);
1908 }
1909
1910 static void
1911 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1912 VkShaderStageFlags stages)
1913 {
1914 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1915 ? cmd_buffer->state.compute_pipeline
1916 : cmd_buffer->state.pipeline;
1917 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1918 VK_PIPELINE_BIND_POINT_COMPUTE :
1919 VK_PIPELINE_BIND_POINT_GRAPHICS;
1920 struct radv_descriptor_state *descriptors_state =
1921 radv_get_descriptors_state(cmd_buffer, bind_point);
1922 struct radv_pipeline_layout *layout = pipeline->layout;
1923 struct radv_shader_variant *shader, *prev_shader;
1924 bool need_push_constants = false;
1925 unsigned offset;
1926 void *ptr;
1927 uint64_t va;
1928
1929 stages &= cmd_buffer->push_constant_stages;
1930 if (!stages ||
1931 (!layout->push_constant_size && !layout->dynamic_offset_count))
1932 return;
1933
1934 radv_foreach_stage(stage, stages) {
1935 if (!pipeline->shaders[stage])
1936 continue;
1937
1938 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
1939 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
1940
1941 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
1942 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
1943
1944 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
1945 AC_UD_INLINE_PUSH_CONSTANTS,
1946 count,
1947 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
1948 }
1949
1950 if (need_push_constants) {
1951 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1952 16 * layout->dynamic_offset_count,
1953 256, &offset, &ptr))
1954 return;
1955
1956 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1957 memcpy((char*)ptr + layout->push_constant_size,
1958 descriptors_state->dynamic_buffers,
1959 16 * layout->dynamic_offset_count);
1960
1961 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1962 va += offset;
1963
1964 MAYBE_UNUSED unsigned cdw_max =
1965 radeon_check_space(cmd_buffer->device->ws,
1966 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1967
1968 prev_shader = NULL;
1969 radv_foreach_stage(stage, stages) {
1970 shader = radv_get_shader(pipeline, stage);
1971
1972 /* Avoid redundantly emitting the address for merged stages. */
1973 if (shader && shader != prev_shader) {
1974 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1975 AC_UD_PUSH_CONSTANTS, va);
1976
1977 prev_shader = shader;
1978 }
1979 }
1980 assert(cmd_buffer->cs->cdw <= cdw_max);
1981 }
1982
1983 cmd_buffer->push_constant_stages &= ~stages;
1984 }
1985
1986 static void
1987 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1988 bool pipeline_is_dirty)
1989 {
1990 if ((pipeline_is_dirty ||
1991 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1992 cmd_buffer->state.pipeline->num_vertex_bindings &&
1993 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1994 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1995 unsigned vb_offset;
1996 void *vb_ptr;
1997 uint32_t i = 0;
1998 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
1999 uint64_t va;
2000
2001 /* allocate some descriptor state for vertex buffers */
2002 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2003 &vb_offset, &vb_ptr))
2004 return;
2005
2006 for (i = 0; i < count; i++) {
2007 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2008 uint32_t offset;
2009 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2010 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2011
2012 if (!buffer)
2013 continue;
2014
2015 va = radv_buffer_get_va(buffer->bo);
2016
2017 offset = cmd_buffer->vertex_bindings[i].offset;
2018 va += offset + buffer->offset;
2019 desc[0] = va;
2020 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2021 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
2022 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2023 else
2024 desc[2] = buffer->size - offset;
2025 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2026 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2027 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2028 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2029 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2030 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2031 }
2032
2033 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2034 va += vb_offset;
2035
2036 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2037 AC_UD_VS_VERTEX_BUFFERS, va);
2038
2039 cmd_buffer->state.vb_va = va;
2040 cmd_buffer->state.vb_size = count * 16;
2041 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2042 }
2043 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2044 }
2045
2046 static void
2047 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2048 {
2049 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2050 struct radv_userdata_info *loc;
2051 uint32_t base_reg;
2052
2053 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2054 if (!radv_get_shader(pipeline, stage))
2055 continue;
2056
2057 loc = radv_lookup_user_sgpr(pipeline, stage,
2058 AC_UD_STREAMOUT_BUFFERS);
2059 if (loc->sgpr_idx == -1)
2060 continue;
2061
2062 base_reg = pipeline->user_data_0[stage];
2063
2064 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2065 base_reg + loc->sgpr_idx * 4, va, false);
2066 }
2067
2068 if (pipeline->gs_copy_shader) {
2069 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2070 if (loc->sgpr_idx != -1) {
2071 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2072
2073 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2074 base_reg + loc->sgpr_idx * 4, va, false);
2075 }
2076 }
2077 }
2078
2079 static void
2080 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2081 {
2082 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2083 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2084 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2085 unsigned so_offset;
2086 void *so_ptr;
2087 uint64_t va;
2088
2089 /* Allocate some descriptor state for streamout buffers. */
2090 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2091 MAX_SO_BUFFERS * 16, 256,
2092 &so_offset, &so_ptr))
2093 return;
2094
2095 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2096 struct radv_buffer *buffer = sb[i].buffer;
2097 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2098
2099 if (!(so->enabled_mask & (1 << i)))
2100 continue;
2101
2102 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2103
2104 va += sb[i].offset;
2105
2106 /* Set the descriptor.
2107 *
2108 * On VI, the format must be non-INVALID, otherwise
2109 * the buffer will be considered not bound and store
2110 * instructions will be no-ops.
2111 */
2112 desc[0] = va;
2113 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2114 desc[2] = 0xffffffff;
2115 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2116 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2117 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2118 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2119 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2120 }
2121
2122 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2123 va += so_offset;
2124
2125 radv_emit_streamout_buffers(cmd_buffer, va);
2126 }
2127
2128 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2129 }
2130
2131 static void
2132 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2133 {
2134 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2135 radv_flush_streamout_descriptors(cmd_buffer);
2136 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2137 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2138 }
2139
2140 struct radv_draw_info {
2141 /**
2142 * Number of vertices.
2143 */
2144 uint32_t count;
2145
2146 /**
2147 * Index of the first vertex.
2148 */
2149 int32_t vertex_offset;
2150
2151 /**
2152 * First instance id.
2153 */
2154 uint32_t first_instance;
2155
2156 /**
2157 * Number of instances.
2158 */
2159 uint32_t instance_count;
2160
2161 /**
2162 * First index (indexed draws only).
2163 */
2164 uint32_t first_index;
2165
2166 /**
2167 * Whether it's an indexed draw.
2168 */
2169 bool indexed;
2170
2171 /**
2172 * Indirect draw parameters resource.
2173 */
2174 struct radv_buffer *indirect;
2175 uint64_t indirect_offset;
2176 uint32_t stride;
2177
2178 /**
2179 * Draw count parameters resource.
2180 */
2181 struct radv_buffer *count_buffer;
2182 uint64_t count_buffer_offset;
2183
2184 /**
2185 * Stream output parameters resource.
2186 */
2187 struct radv_buffer *strmout_buffer;
2188 uint64_t strmout_buffer_offset;
2189 };
2190
2191 static void
2192 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2193 const struct radv_draw_info *draw_info)
2194 {
2195 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2196 struct radv_cmd_state *state = &cmd_buffer->state;
2197 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2198 uint32_t ia_multi_vgt_param;
2199 int32_t primitive_reset_en;
2200
2201 /* Draw state. */
2202 ia_multi_vgt_param =
2203 si_get_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2204 draw_info->indirect,
2205 !!draw_info->strmout_buffer,
2206 draw_info->indirect ? 0 : draw_info->count);
2207
2208 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2209 if (info->chip_class >= GFX9) {
2210 radeon_set_uconfig_reg_idx(cs,
2211 R_030960_IA_MULTI_VGT_PARAM,
2212 4, ia_multi_vgt_param);
2213 } else if (info->chip_class >= CIK) {
2214 radeon_set_context_reg_idx(cs,
2215 R_028AA8_IA_MULTI_VGT_PARAM,
2216 1, ia_multi_vgt_param);
2217 } else {
2218 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2219 ia_multi_vgt_param);
2220 }
2221 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2222 }
2223
2224 /* Primitive restart. */
2225 primitive_reset_en =
2226 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2227
2228 if (primitive_reset_en != state->last_primitive_reset_en) {
2229 state->last_primitive_reset_en = primitive_reset_en;
2230 if (info->chip_class >= GFX9) {
2231 radeon_set_uconfig_reg(cs,
2232 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2233 primitive_reset_en);
2234 } else {
2235 radeon_set_context_reg(cs,
2236 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2237 primitive_reset_en);
2238 }
2239 }
2240
2241 if (primitive_reset_en) {
2242 uint32_t primitive_reset_index =
2243 state->index_type ? 0xffffffffu : 0xffffu;
2244
2245 if (primitive_reset_index != state->last_primitive_reset_index) {
2246 radeon_set_context_reg(cs,
2247 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2248 primitive_reset_index);
2249 state->last_primitive_reset_index = primitive_reset_index;
2250 }
2251 }
2252
2253 if (draw_info->strmout_buffer) {
2254 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2255
2256 va += draw_info->strmout_buffer->offset +
2257 draw_info->strmout_buffer_offset;
2258
2259 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2260 draw_info->stride);
2261
2262 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2263 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2264 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2265 COPY_DATA_WR_CONFIRM);
2266 radeon_emit(cs, va);
2267 radeon_emit(cs, va >> 32);
2268 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2269 radeon_emit(cs, 0); /* unused */
2270
2271 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2272 }
2273 }
2274
2275 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2276 VkPipelineStageFlags src_stage_mask)
2277 {
2278 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2279 VK_PIPELINE_STAGE_TRANSFER_BIT |
2280 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2281 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2282 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2283 }
2284
2285 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2286 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2287 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2288 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2289 VK_PIPELINE_STAGE_TRANSFER_BIT |
2290 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2291 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2292 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2293 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2294 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2295 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2296 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2297 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2298 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2299 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2300 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2301 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2302 }
2303 }
2304
2305 static enum radv_cmd_flush_bits
2306 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2307 VkAccessFlags src_flags,
2308 struct radv_image *image)
2309 {
2310 bool flush_CB_meta = true, flush_DB_meta = true;
2311 enum radv_cmd_flush_bits flush_bits = 0;
2312 uint32_t b;
2313
2314 if (image) {
2315 if (!radv_image_has_CB_metadata(image))
2316 flush_CB_meta = false;
2317 if (!radv_image_has_htile(image))
2318 flush_DB_meta = false;
2319 }
2320
2321 for_each_bit(b, src_flags) {
2322 switch ((VkAccessFlagBits)(1 << b)) {
2323 case VK_ACCESS_SHADER_WRITE_BIT:
2324 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2325 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2326 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2327 break;
2328 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2329 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2330 if (flush_CB_meta)
2331 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2332 break;
2333 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2334 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2335 if (flush_DB_meta)
2336 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2337 break;
2338 case VK_ACCESS_TRANSFER_WRITE_BIT:
2339 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2340 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2341 RADV_CMD_FLAG_INV_GLOBAL_L2;
2342
2343 if (flush_CB_meta)
2344 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2345 if (flush_DB_meta)
2346 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2347 break;
2348 default:
2349 break;
2350 }
2351 }
2352 return flush_bits;
2353 }
2354
2355 static enum radv_cmd_flush_bits
2356 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2357 VkAccessFlags dst_flags,
2358 struct radv_image *image)
2359 {
2360 bool flush_CB_meta = true, flush_DB_meta = true;
2361 enum radv_cmd_flush_bits flush_bits = 0;
2362 bool flush_CB = true, flush_DB = true;
2363 bool image_is_coherent = false;
2364 uint32_t b;
2365
2366 if (image) {
2367 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2368 flush_CB = false;
2369 flush_DB = false;
2370 }
2371
2372 if (!radv_image_has_CB_metadata(image))
2373 flush_CB_meta = false;
2374 if (!radv_image_has_htile(image))
2375 flush_DB_meta = false;
2376
2377 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2378 if (image->info.samples == 1 &&
2379 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2380 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2381 !vk_format_is_stencil(image->vk_format)) {
2382 /* Single-sample color and single-sample depth
2383 * (not stencil) are coherent with shaders on
2384 * GFX9.
2385 */
2386 image_is_coherent = true;
2387 }
2388 }
2389 }
2390
2391 for_each_bit(b, dst_flags) {
2392 switch ((VkAccessFlagBits)(1 << b)) {
2393 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2394 case VK_ACCESS_INDEX_READ_BIT:
2395 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2396 break;
2397 case VK_ACCESS_UNIFORM_READ_BIT:
2398 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2399 break;
2400 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2401 case VK_ACCESS_TRANSFER_READ_BIT:
2402 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2403 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2404 RADV_CMD_FLAG_INV_GLOBAL_L2;
2405 break;
2406 case VK_ACCESS_SHADER_READ_BIT:
2407 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2408
2409 if (!image_is_coherent)
2410 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2411 break;
2412 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2413 if (flush_CB)
2414 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2415 if (flush_CB_meta)
2416 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2417 break;
2418 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2419 if (flush_DB)
2420 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2421 if (flush_DB_meta)
2422 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2423 break;
2424 default:
2425 break;
2426 }
2427 }
2428 return flush_bits;
2429 }
2430
2431 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2432 const struct radv_subpass_barrier *barrier)
2433 {
2434 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2435 NULL);
2436 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2437 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2438 NULL);
2439 }
2440
2441 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2442 struct radv_subpass_attachment att)
2443 {
2444 unsigned idx = att.attachment;
2445 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2446 VkImageSubresourceRange range;
2447 range.aspectMask = 0;
2448 range.baseMipLevel = view->base_mip;
2449 range.levelCount = 1;
2450 range.baseArrayLayer = view->base_layer;
2451 range.layerCount = cmd_buffer->state.framebuffer->layers;
2452
2453 if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
2454 /* If the current subpass uses multiview, the driver might have
2455 * performed a fast color/depth clear to the whole image
2456 * (including all layers). To make sure the driver will
2457 * decompress the image correctly (if needed), we have to
2458 * account for the "real" number of layers. If the view mask is
2459 * sparse, this will decompress more layers than needed.
2460 */
2461 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2462 }
2463
2464 radv_handle_image_transition(cmd_buffer,
2465 view->image,
2466 cmd_buffer->state.attachments[idx].current_layout,
2467 att.layout, 0, 0, &range);
2468
2469 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2470
2471
2472 }
2473
2474 void
2475 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2476 const struct radv_subpass *subpass)
2477 {
2478 cmd_buffer->state.subpass = subpass;
2479
2480 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2481 }
2482
2483 static VkResult
2484 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2485 struct radv_render_pass *pass,
2486 const VkRenderPassBeginInfo *info)
2487 {
2488 struct radv_cmd_state *state = &cmd_buffer->state;
2489
2490 if (pass->attachment_count == 0) {
2491 state->attachments = NULL;
2492 return VK_SUCCESS;
2493 }
2494
2495 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2496 pass->attachment_count *
2497 sizeof(state->attachments[0]),
2498 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2499 if (state->attachments == NULL) {
2500 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2501 return cmd_buffer->record_result;
2502 }
2503
2504 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2505 struct radv_render_pass_attachment *att = &pass->attachments[i];
2506 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2507 VkImageAspectFlags clear_aspects = 0;
2508
2509 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2510 /* color attachment */
2511 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2512 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2513 }
2514 } else {
2515 /* depthstencil attachment */
2516 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2517 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2518 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2519 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2520 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2521 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2522 }
2523 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2524 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2525 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2526 }
2527 }
2528
2529 state->attachments[i].pending_clear_aspects = clear_aspects;
2530 state->attachments[i].cleared_views = 0;
2531 if (clear_aspects && info) {
2532 assert(info->clearValueCount > i);
2533 state->attachments[i].clear_value = info->pClearValues[i];
2534 }
2535
2536 state->attachments[i].current_layout = att->initial_layout;
2537 }
2538
2539 return VK_SUCCESS;
2540 }
2541
2542 VkResult radv_AllocateCommandBuffers(
2543 VkDevice _device,
2544 const VkCommandBufferAllocateInfo *pAllocateInfo,
2545 VkCommandBuffer *pCommandBuffers)
2546 {
2547 RADV_FROM_HANDLE(radv_device, device, _device);
2548 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2549
2550 VkResult result = VK_SUCCESS;
2551 uint32_t i;
2552
2553 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2554
2555 if (!list_empty(&pool->free_cmd_buffers)) {
2556 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2557
2558 list_del(&cmd_buffer->pool_link);
2559 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2560
2561 result = radv_reset_cmd_buffer(cmd_buffer);
2562 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2563 cmd_buffer->level = pAllocateInfo->level;
2564
2565 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2566 } else {
2567 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2568 &pCommandBuffers[i]);
2569 }
2570 if (result != VK_SUCCESS)
2571 break;
2572 }
2573
2574 if (result != VK_SUCCESS) {
2575 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2576 i, pCommandBuffers);
2577
2578 /* From the Vulkan 1.0.66 spec:
2579 *
2580 * "vkAllocateCommandBuffers can be used to create multiple
2581 * command buffers. If the creation of any of those command
2582 * buffers fails, the implementation must destroy all
2583 * successfully created command buffer objects from this
2584 * command, set all entries of the pCommandBuffers array to
2585 * NULL and return the error."
2586 */
2587 memset(pCommandBuffers, 0,
2588 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2589 }
2590
2591 return result;
2592 }
2593
2594 void radv_FreeCommandBuffers(
2595 VkDevice device,
2596 VkCommandPool commandPool,
2597 uint32_t commandBufferCount,
2598 const VkCommandBuffer *pCommandBuffers)
2599 {
2600 for (uint32_t i = 0; i < commandBufferCount; i++) {
2601 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2602
2603 if (cmd_buffer) {
2604 if (cmd_buffer->pool) {
2605 list_del(&cmd_buffer->pool_link);
2606 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2607 } else
2608 radv_cmd_buffer_destroy(cmd_buffer);
2609
2610 }
2611 }
2612 }
2613
2614 VkResult radv_ResetCommandBuffer(
2615 VkCommandBuffer commandBuffer,
2616 VkCommandBufferResetFlags flags)
2617 {
2618 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2619 return radv_reset_cmd_buffer(cmd_buffer);
2620 }
2621
2622 VkResult radv_BeginCommandBuffer(
2623 VkCommandBuffer commandBuffer,
2624 const VkCommandBufferBeginInfo *pBeginInfo)
2625 {
2626 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2627 VkResult result = VK_SUCCESS;
2628
2629 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2630 /* If the command buffer has already been resetted with
2631 * vkResetCommandBuffer, no need to do it again.
2632 */
2633 result = radv_reset_cmd_buffer(cmd_buffer);
2634 if (result != VK_SUCCESS)
2635 return result;
2636 }
2637
2638 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2639 cmd_buffer->state.last_primitive_reset_en = -1;
2640 cmd_buffer->state.last_index_type = -1;
2641 cmd_buffer->state.last_num_instances = -1;
2642 cmd_buffer->state.last_vertex_offset = -1;
2643 cmd_buffer->state.last_first_instance = -1;
2644 cmd_buffer->state.predication_type = -1;
2645 cmd_buffer->usage_flags = pBeginInfo->flags;
2646
2647 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2648 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2649 assert(pBeginInfo->pInheritanceInfo);
2650 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2651 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2652
2653 struct radv_subpass *subpass =
2654 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2655
2656 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2657 if (result != VK_SUCCESS)
2658 return result;
2659
2660 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
2661 }
2662
2663 if (unlikely(cmd_buffer->device->trace_bo)) {
2664 struct radv_device *device = cmd_buffer->device;
2665
2666 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2667 device->trace_bo);
2668
2669 radv_cmd_buffer_trace_emit(cmd_buffer);
2670 }
2671
2672 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2673
2674 return result;
2675 }
2676
2677 void radv_CmdBindVertexBuffers(
2678 VkCommandBuffer commandBuffer,
2679 uint32_t firstBinding,
2680 uint32_t bindingCount,
2681 const VkBuffer* pBuffers,
2682 const VkDeviceSize* pOffsets)
2683 {
2684 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2685 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2686 bool changed = false;
2687
2688 /* We have to defer setting up vertex buffer since we need the buffer
2689 * stride from the pipeline. */
2690
2691 assert(firstBinding + bindingCount <= MAX_VBS);
2692 for (uint32_t i = 0; i < bindingCount; i++) {
2693 uint32_t idx = firstBinding + i;
2694
2695 if (!changed &&
2696 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2697 vb[idx].offset != pOffsets[i])) {
2698 changed = true;
2699 }
2700
2701 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2702 vb[idx].offset = pOffsets[i];
2703
2704 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2705 vb[idx].buffer->bo);
2706 }
2707
2708 if (!changed) {
2709 /* No state changes. */
2710 return;
2711 }
2712
2713 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2714 }
2715
2716 void radv_CmdBindIndexBuffer(
2717 VkCommandBuffer commandBuffer,
2718 VkBuffer buffer,
2719 VkDeviceSize offset,
2720 VkIndexType indexType)
2721 {
2722 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2723 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2724
2725 if (cmd_buffer->state.index_buffer == index_buffer &&
2726 cmd_buffer->state.index_offset == offset &&
2727 cmd_buffer->state.index_type == indexType) {
2728 /* No state changes. */
2729 return;
2730 }
2731
2732 cmd_buffer->state.index_buffer = index_buffer;
2733 cmd_buffer->state.index_offset = offset;
2734 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2735 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2736 cmd_buffer->state.index_va += index_buffer->offset + offset;
2737
2738 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2739 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2740 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2741 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2742 }
2743
2744
2745 static void
2746 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2747 VkPipelineBindPoint bind_point,
2748 struct radv_descriptor_set *set, unsigned idx)
2749 {
2750 struct radeon_winsys *ws = cmd_buffer->device->ws;
2751
2752 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2753
2754 assert(set);
2755 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2756
2757 if (!cmd_buffer->device->use_global_bo_list) {
2758 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2759 if (set->descriptors[j])
2760 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2761 }
2762
2763 if(set->bo)
2764 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2765 }
2766
2767 void radv_CmdBindDescriptorSets(
2768 VkCommandBuffer commandBuffer,
2769 VkPipelineBindPoint pipelineBindPoint,
2770 VkPipelineLayout _layout,
2771 uint32_t firstSet,
2772 uint32_t descriptorSetCount,
2773 const VkDescriptorSet* pDescriptorSets,
2774 uint32_t dynamicOffsetCount,
2775 const uint32_t* pDynamicOffsets)
2776 {
2777 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2778 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2779 unsigned dyn_idx = 0;
2780
2781 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2782 struct radv_descriptor_state *descriptors_state =
2783 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2784
2785 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2786 unsigned idx = i + firstSet;
2787 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2788 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2789
2790 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2791 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2792 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2793 assert(dyn_idx < dynamicOffsetCount);
2794
2795 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2796 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2797 dst[0] = va;
2798 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2799 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2800 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2801 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2802 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2803 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2804 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2805 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2806 cmd_buffer->push_constant_stages |=
2807 set->layout->dynamic_shader_stages;
2808 }
2809 }
2810 }
2811
2812 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2813 struct radv_descriptor_set *set,
2814 struct radv_descriptor_set_layout *layout,
2815 VkPipelineBindPoint bind_point)
2816 {
2817 struct radv_descriptor_state *descriptors_state =
2818 radv_get_descriptors_state(cmd_buffer, bind_point);
2819 set->size = layout->size;
2820 set->layout = layout;
2821
2822 if (descriptors_state->push_set.capacity < set->size) {
2823 size_t new_size = MAX2(set->size, 1024);
2824 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2825 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2826
2827 free(set->mapped_ptr);
2828 set->mapped_ptr = malloc(new_size);
2829
2830 if (!set->mapped_ptr) {
2831 descriptors_state->push_set.capacity = 0;
2832 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2833 return false;
2834 }
2835
2836 descriptors_state->push_set.capacity = new_size;
2837 }
2838
2839 return true;
2840 }
2841
2842 void radv_meta_push_descriptor_set(
2843 struct radv_cmd_buffer* cmd_buffer,
2844 VkPipelineBindPoint pipelineBindPoint,
2845 VkPipelineLayout _layout,
2846 uint32_t set,
2847 uint32_t descriptorWriteCount,
2848 const VkWriteDescriptorSet* pDescriptorWrites)
2849 {
2850 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2851 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2852 unsigned bo_offset;
2853
2854 assert(set == 0);
2855 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2856
2857 push_set->size = layout->set[set].layout->size;
2858 push_set->layout = layout->set[set].layout;
2859
2860 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2861 &bo_offset,
2862 (void**) &push_set->mapped_ptr))
2863 return;
2864
2865 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2866 push_set->va += bo_offset;
2867
2868 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2869 radv_descriptor_set_to_handle(push_set),
2870 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2871
2872 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2873 }
2874
2875 void radv_CmdPushDescriptorSetKHR(
2876 VkCommandBuffer commandBuffer,
2877 VkPipelineBindPoint pipelineBindPoint,
2878 VkPipelineLayout _layout,
2879 uint32_t set,
2880 uint32_t descriptorWriteCount,
2881 const VkWriteDescriptorSet* pDescriptorWrites)
2882 {
2883 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2884 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2885 struct radv_descriptor_state *descriptors_state =
2886 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2887 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2888
2889 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2890
2891 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2892 layout->set[set].layout,
2893 pipelineBindPoint))
2894 return;
2895
2896 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2897 radv_descriptor_set_to_handle(push_set),
2898 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2899
2900 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2901 descriptors_state->push_dirty = true;
2902 }
2903
2904 void radv_CmdPushDescriptorSetWithTemplateKHR(
2905 VkCommandBuffer commandBuffer,
2906 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2907 VkPipelineLayout _layout,
2908 uint32_t set,
2909 const void* pData)
2910 {
2911 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2912 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2913 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2914 struct radv_descriptor_state *descriptors_state =
2915 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2916 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2917
2918 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2919
2920 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2921 layout->set[set].layout,
2922 templ->bind_point))
2923 return;
2924
2925 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2926 descriptorUpdateTemplate, pData);
2927
2928 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2929 descriptors_state->push_dirty = true;
2930 }
2931
2932 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2933 VkPipelineLayout layout,
2934 VkShaderStageFlags stageFlags,
2935 uint32_t offset,
2936 uint32_t size,
2937 const void* pValues)
2938 {
2939 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2940 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2941 cmd_buffer->push_constant_stages |= stageFlags;
2942 }
2943
2944 VkResult radv_EndCommandBuffer(
2945 VkCommandBuffer commandBuffer)
2946 {
2947 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2948
2949 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2950 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2951 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2952 si_emit_cache_flush(cmd_buffer);
2953 }
2954
2955 /* Make sure CP DMA is idle at the end of IBs because the kernel
2956 * doesn't wait for it.
2957 */
2958 si_cp_dma_wait_for_idle(cmd_buffer);
2959
2960 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2961
2962 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2963 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2964
2965 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2966
2967 return cmd_buffer->record_result;
2968 }
2969
2970 static void
2971 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2972 {
2973 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2974
2975 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2976 return;
2977
2978 assert(!pipeline->ctx_cs.cdw);
2979
2980 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2981
2982 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2983 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2984
2985 cmd_buffer->compute_scratch_size_needed =
2986 MAX2(cmd_buffer->compute_scratch_size_needed,
2987 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2988
2989 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2990 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2991
2992 if (unlikely(cmd_buffer->device->trace_bo))
2993 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2994 }
2995
2996 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2997 VkPipelineBindPoint bind_point)
2998 {
2999 struct radv_descriptor_state *descriptors_state =
3000 radv_get_descriptors_state(cmd_buffer, bind_point);
3001
3002 descriptors_state->dirty |= descriptors_state->valid;
3003 }
3004
3005 void radv_CmdBindPipeline(
3006 VkCommandBuffer commandBuffer,
3007 VkPipelineBindPoint pipelineBindPoint,
3008 VkPipeline _pipeline)
3009 {
3010 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3011 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3012
3013 switch (pipelineBindPoint) {
3014 case VK_PIPELINE_BIND_POINT_COMPUTE:
3015 if (cmd_buffer->state.compute_pipeline == pipeline)
3016 return;
3017 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3018
3019 cmd_buffer->state.compute_pipeline = pipeline;
3020 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3021 break;
3022 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3023 if (cmd_buffer->state.pipeline == pipeline)
3024 return;
3025 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3026
3027 cmd_buffer->state.pipeline = pipeline;
3028 if (!pipeline)
3029 break;
3030
3031 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3032 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3033
3034 /* the new vertex shader might not have the same user regs */
3035 cmd_buffer->state.last_first_instance = -1;
3036 cmd_buffer->state.last_vertex_offset = -1;
3037
3038 /* Prefetch all pipeline shaders at first draw time. */
3039 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3040
3041 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3042 radv_bind_streamout_state(cmd_buffer, pipeline);
3043
3044 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3045 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3046 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3047 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3048
3049 if (radv_pipeline_has_tess(pipeline))
3050 cmd_buffer->tess_rings_needed = true;
3051 break;
3052 default:
3053 assert(!"invalid bind point");
3054 break;
3055 }
3056 }
3057
3058 void radv_CmdSetViewport(
3059 VkCommandBuffer commandBuffer,
3060 uint32_t firstViewport,
3061 uint32_t viewportCount,
3062 const VkViewport* pViewports)
3063 {
3064 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3065 struct radv_cmd_state *state = &cmd_buffer->state;
3066 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3067
3068 assert(firstViewport < MAX_VIEWPORTS);
3069 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3070
3071 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3072 pViewports, viewportCount * sizeof(*pViewports))) {
3073 return;
3074 }
3075
3076 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3077 viewportCount * sizeof(*pViewports));
3078
3079 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3080 }
3081
3082 void radv_CmdSetScissor(
3083 VkCommandBuffer commandBuffer,
3084 uint32_t firstScissor,
3085 uint32_t scissorCount,
3086 const VkRect2D* pScissors)
3087 {
3088 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3089 struct radv_cmd_state *state = &cmd_buffer->state;
3090 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3091
3092 assert(firstScissor < MAX_SCISSORS);
3093 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3094
3095 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3096 scissorCount * sizeof(*pScissors))) {
3097 return;
3098 }
3099
3100 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3101 scissorCount * sizeof(*pScissors));
3102
3103 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3104 }
3105
3106 void radv_CmdSetLineWidth(
3107 VkCommandBuffer commandBuffer,
3108 float lineWidth)
3109 {
3110 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3111
3112 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3113 return;
3114
3115 cmd_buffer->state.dynamic.line_width = lineWidth;
3116 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3117 }
3118
3119 void radv_CmdSetDepthBias(
3120 VkCommandBuffer commandBuffer,
3121 float depthBiasConstantFactor,
3122 float depthBiasClamp,
3123 float depthBiasSlopeFactor)
3124 {
3125 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3126 struct radv_cmd_state *state = &cmd_buffer->state;
3127
3128 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3129 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3130 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3131 return;
3132 }
3133
3134 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3135 state->dynamic.depth_bias.clamp = depthBiasClamp;
3136 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3137
3138 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3139 }
3140
3141 void radv_CmdSetBlendConstants(
3142 VkCommandBuffer commandBuffer,
3143 const float blendConstants[4])
3144 {
3145 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3146 struct radv_cmd_state *state = &cmd_buffer->state;
3147
3148 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3149 return;
3150
3151 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3152
3153 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3154 }
3155
3156 void radv_CmdSetDepthBounds(
3157 VkCommandBuffer commandBuffer,
3158 float minDepthBounds,
3159 float maxDepthBounds)
3160 {
3161 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3162 struct radv_cmd_state *state = &cmd_buffer->state;
3163
3164 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3165 state->dynamic.depth_bounds.max == maxDepthBounds) {
3166 return;
3167 }
3168
3169 state->dynamic.depth_bounds.min = minDepthBounds;
3170 state->dynamic.depth_bounds.max = maxDepthBounds;
3171
3172 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3173 }
3174
3175 void radv_CmdSetStencilCompareMask(
3176 VkCommandBuffer commandBuffer,
3177 VkStencilFaceFlags faceMask,
3178 uint32_t compareMask)
3179 {
3180 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3181 struct radv_cmd_state *state = &cmd_buffer->state;
3182 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3183 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3184
3185 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3186 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3187 return;
3188 }
3189
3190 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3191 state->dynamic.stencil_compare_mask.front = compareMask;
3192 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3193 state->dynamic.stencil_compare_mask.back = compareMask;
3194
3195 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3196 }
3197
3198 void radv_CmdSetStencilWriteMask(
3199 VkCommandBuffer commandBuffer,
3200 VkStencilFaceFlags faceMask,
3201 uint32_t writeMask)
3202 {
3203 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3204 struct radv_cmd_state *state = &cmd_buffer->state;
3205 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3206 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3207
3208 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3209 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3210 return;
3211 }
3212
3213 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3214 state->dynamic.stencil_write_mask.front = writeMask;
3215 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3216 state->dynamic.stencil_write_mask.back = writeMask;
3217
3218 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3219 }
3220
3221 void radv_CmdSetStencilReference(
3222 VkCommandBuffer commandBuffer,
3223 VkStencilFaceFlags faceMask,
3224 uint32_t reference)
3225 {
3226 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3227 struct radv_cmd_state *state = &cmd_buffer->state;
3228 bool front_same = state->dynamic.stencil_reference.front == reference;
3229 bool back_same = state->dynamic.stencil_reference.back == reference;
3230
3231 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3232 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3233 return;
3234 }
3235
3236 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3237 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3238 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3239 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3240
3241 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3242 }
3243
3244 void radv_CmdSetDiscardRectangleEXT(
3245 VkCommandBuffer commandBuffer,
3246 uint32_t firstDiscardRectangle,
3247 uint32_t discardRectangleCount,
3248 const VkRect2D* pDiscardRectangles)
3249 {
3250 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3251 struct radv_cmd_state *state = &cmd_buffer->state;
3252 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3253
3254 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3255 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3256
3257 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3258 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3259 return;
3260 }
3261
3262 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3263 pDiscardRectangles, discardRectangleCount);
3264
3265 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3266 }
3267
3268 void radv_CmdExecuteCommands(
3269 VkCommandBuffer commandBuffer,
3270 uint32_t commandBufferCount,
3271 const VkCommandBuffer* pCmdBuffers)
3272 {
3273 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3274
3275 assert(commandBufferCount > 0);
3276
3277 /* Emit pending flushes on primary prior to executing secondary */
3278 si_emit_cache_flush(primary);
3279
3280 for (uint32_t i = 0; i < commandBufferCount; i++) {
3281 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3282
3283 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3284 secondary->scratch_size_needed);
3285 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3286 secondary->compute_scratch_size_needed);
3287
3288 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3289 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3290 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3291 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3292 if (secondary->tess_rings_needed)
3293 primary->tess_rings_needed = true;
3294 if (secondary->sample_positions_needed)
3295 primary->sample_positions_needed = true;
3296
3297 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3298
3299
3300 /* When the secondary command buffer is compute only we don't
3301 * need to re-emit the current graphics pipeline.
3302 */
3303 if (secondary->state.emitted_pipeline) {
3304 primary->state.emitted_pipeline =
3305 secondary->state.emitted_pipeline;
3306 }
3307
3308 /* When the secondary command buffer is graphics only we don't
3309 * need to re-emit the current compute pipeline.
3310 */
3311 if (secondary->state.emitted_compute_pipeline) {
3312 primary->state.emitted_compute_pipeline =
3313 secondary->state.emitted_compute_pipeline;
3314 }
3315
3316 /* Only re-emit the draw packets when needed. */
3317 if (secondary->state.last_primitive_reset_en != -1) {
3318 primary->state.last_primitive_reset_en =
3319 secondary->state.last_primitive_reset_en;
3320 }
3321
3322 if (secondary->state.last_primitive_reset_index) {
3323 primary->state.last_primitive_reset_index =
3324 secondary->state.last_primitive_reset_index;
3325 }
3326
3327 if (secondary->state.last_ia_multi_vgt_param) {
3328 primary->state.last_ia_multi_vgt_param =
3329 secondary->state.last_ia_multi_vgt_param;
3330 }
3331
3332 primary->state.last_first_instance = secondary->state.last_first_instance;
3333 primary->state.last_num_instances = secondary->state.last_num_instances;
3334 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3335
3336 if (secondary->state.last_index_type != -1) {
3337 primary->state.last_index_type =
3338 secondary->state.last_index_type;
3339 }
3340 }
3341
3342 /* After executing commands from secondary buffers we have to dirty
3343 * some states.
3344 */
3345 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3346 RADV_CMD_DIRTY_INDEX_BUFFER |
3347 RADV_CMD_DIRTY_DYNAMIC_ALL;
3348 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3349 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3350 }
3351
3352 VkResult radv_CreateCommandPool(
3353 VkDevice _device,
3354 const VkCommandPoolCreateInfo* pCreateInfo,
3355 const VkAllocationCallbacks* pAllocator,
3356 VkCommandPool* pCmdPool)
3357 {
3358 RADV_FROM_HANDLE(radv_device, device, _device);
3359 struct radv_cmd_pool *pool;
3360
3361 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3362 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3363 if (pool == NULL)
3364 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3365
3366 if (pAllocator)
3367 pool->alloc = *pAllocator;
3368 else
3369 pool->alloc = device->alloc;
3370
3371 list_inithead(&pool->cmd_buffers);
3372 list_inithead(&pool->free_cmd_buffers);
3373
3374 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3375
3376 *pCmdPool = radv_cmd_pool_to_handle(pool);
3377
3378 return VK_SUCCESS;
3379
3380 }
3381
3382 void radv_DestroyCommandPool(
3383 VkDevice _device,
3384 VkCommandPool commandPool,
3385 const VkAllocationCallbacks* pAllocator)
3386 {
3387 RADV_FROM_HANDLE(radv_device, device, _device);
3388 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3389
3390 if (!pool)
3391 return;
3392
3393 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3394 &pool->cmd_buffers, pool_link) {
3395 radv_cmd_buffer_destroy(cmd_buffer);
3396 }
3397
3398 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3399 &pool->free_cmd_buffers, pool_link) {
3400 radv_cmd_buffer_destroy(cmd_buffer);
3401 }
3402
3403 vk_free2(&device->alloc, pAllocator, pool);
3404 }
3405
3406 VkResult radv_ResetCommandPool(
3407 VkDevice device,
3408 VkCommandPool commandPool,
3409 VkCommandPoolResetFlags flags)
3410 {
3411 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3412 VkResult result;
3413
3414 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3415 &pool->cmd_buffers, pool_link) {
3416 result = radv_reset_cmd_buffer(cmd_buffer);
3417 if (result != VK_SUCCESS)
3418 return result;
3419 }
3420
3421 return VK_SUCCESS;
3422 }
3423
3424 void radv_TrimCommandPool(
3425 VkDevice device,
3426 VkCommandPool commandPool,
3427 VkCommandPoolTrimFlags flags)
3428 {
3429 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3430
3431 if (!pool)
3432 return;
3433
3434 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3435 &pool->free_cmd_buffers, pool_link) {
3436 radv_cmd_buffer_destroy(cmd_buffer);
3437 }
3438 }
3439
3440 static uint32_t
3441 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3442 {
3443 struct radv_cmd_state *state = &cmd_buffer->state;
3444 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3445
3446 /* The id of this subpass shouldn't exceed the number of subpasses in
3447 * this render pass minus 1.
3448 */
3449 assert(subpass_id < state->pass->subpass_count);
3450 return subpass_id;
3451 }
3452
3453 static void
3454 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
3455 uint32_t subpass_id)
3456 {
3457 struct radv_cmd_state *state = &cmd_buffer->state;
3458 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
3459
3460 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3461 cmd_buffer->cs, 4096);
3462
3463 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
3464
3465 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3466 const uint32_t a = subpass->attachments[i].attachment;
3467 if (a == VK_ATTACHMENT_UNUSED)
3468 continue;
3469
3470 radv_handle_subpass_image_transition(cmd_buffer,
3471 subpass->attachments[i]);
3472 }
3473
3474 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3475 radv_cmd_buffer_clear_subpass(cmd_buffer);
3476
3477 assert(cmd_buffer->cs->cdw <= cdw_max);
3478 }
3479
3480 static void
3481 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
3482 {
3483 struct radv_cmd_state *state = &cmd_buffer->state;
3484 const struct radv_subpass *subpass = state->subpass;
3485 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3486
3487 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3488
3489 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3490 const uint32_t a = subpass->attachments[i].attachment;
3491 if (a == VK_ATTACHMENT_UNUSED)
3492 continue;
3493
3494 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
3495 continue;
3496
3497 VkImageLayout layout = state->pass->attachments[a].final_layout;
3498 radv_handle_subpass_image_transition(cmd_buffer,
3499 (struct radv_subpass_attachment){a, layout});
3500 }
3501 }
3502
3503 void radv_CmdBeginRenderPass(
3504 VkCommandBuffer commandBuffer,
3505 const VkRenderPassBeginInfo* pRenderPassBegin,
3506 VkSubpassContents contents)
3507 {
3508 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3509 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3510 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3511 VkResult result;
3512
3513 cmd_buffer->state.framebuffer = framebuffer;
3514 cmd_buffer->state.pass = pass;
3515 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3516
3517 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3518 if (result != VK_SUCCESS)
3519 return;
3520
3521 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
3522 }
3523
3524 void radv_CmdBeginRenderPass2KHR(
3525 VkCommandBuffer commandBuffer,
3526 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3527 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3528 {
3529 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3530 pSubpassBeginInfo->contents);
3531 }
3532
3533 void radv_CmdNextSubpass(
3534 VkCommandBuffer commandBuffer,
3535 VkSubpassContents contents)
3536 {
3537 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3538
3539 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
3540 radv_cmd_buffer_end_subpass(cmd_buffer);
3541 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
3542 }
3543
3544 void radv_CmdNextSubpass2KHR(
3545 VkCommandBuffer commandBuffer,
3546 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3547 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3548 {
3549 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3550 }
3551
3552 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3553 {
3554 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3555 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3556 if (!radv_get_shader(pipeline, stage))
3557 continue;
3558
3559 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3560 if (loc->sgpr_idx == -1)
3561 continue;
3562 uint32_t base_reg = pipeline->user_data_0[stage];
3563 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3564
3565 }
3566 if (pipeline->gs_copy_shader) {
3567 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3568 if (loc->sgpr_idx != -1) {
3569 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3570 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3571 }
3572 }
3573 }
3574
3575 static void
3576 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3577 uint32_t vertex_count,
3578 bool use_opaque)
3579 {
3580 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3581 radeon_emit(cmd_buffer->cs, vertex_count);
3582 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3583 S_0287F0_USE_OPAQUE(use_opaque));
3584 }
3585
3586 static void
3587 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3588 uint64_t index_va,
3589 uint32_t index_count)
3590 {
3591 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3592 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3593 radeon_emit(cmd_buffer->cs, index_va);
3594 radeon_emit(cmd_buffer->cs, index_va >> 32);
3595 radeon_emit(cmd_buffer->cs, index_count);
3596 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3597 }
3598
3599 static void
3600 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3601 bool indexed,
3602 uint32_t draw_count,
3603 uint64_t count_va,
3604 uint32_t stride)
3605 {
3606 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3607 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3608 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3609 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3610 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3611 bool predicating = cmd_buffer->state.predicating;
3612 assert(base_reg);
3613
3614 /* just reset draw state for vertex data */
3615 cmd_buffer->state.last_first_instance = -1;
3616 cmd_buffer->state.last_num_instances = -1;
3617 cmd_buffer->state.last_vertex_offset = -1;
3618
3619 if (draw_count == 1 && !count_va && !draw_id_enable) {
3620 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3621 PKT3_DRAW_INDIRECT, 3, predicating));
3622 radeon_emit(cs, 0);
3623 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3624 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3625 radeon_emit(cs, di_src_sel);
3626 } else {
3627 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3628 PKT3_DRAW_INDIRECT_MULTI,
3629 8, predicating));
3630 radeon_emit(cs, 0);
3631 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3632 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3633 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3634 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3635 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3636 radeon_emit(cs, draw_count); /* count */
3637 radeon_emit(cs, count_va); /* count_addr */
3638 radeon_emit(cs, count_va >> 32);
3639 radeon_emit(cs, stride); /* stride */
3640 radeon_emit(cs, di_src_sel);
3641 }
3642 }
3643
3644 static void
3645 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3646 const struct radv_draw_info *info)
3647 {
3648 struct radv_cmd_state *state = &cmd_buffer->state;
3649 struct radeon_winsys *ws = cmd_buffer->device->ws;
3650 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3651
3652 if (info->indirect) {
3653 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3654 uint64_t count_va = 0;
3655
3656 va += info->indirect->offset + info->indirect_offset;
3657
3658 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3659
3660 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3661 radeon_emit(cs, 1);
3662 radeon_emit(cs, va);
3663 radeon_emit(cs, va >> 32);
3664
3665 if (info->count_buffer) {
3666 count_va = radv_buffer_get_va(info->count_buffer->bo);
3667 count_va += info->count_buffer->offset +
3668 info->count_buffer_offset;
3669
3670 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3671 }
3672
3673 if (!state->subpass->view_mask) {
3674 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3675 info->indexed,
3676 info->count,
3677 count_va,
3678 info->stride);
3679 } else {
3680 unsigned i;
3681 for_each_bit(i, state->subpass->view_mask) {
3682 radv_emit_view_index(cmd_buffer, i);
3683
3684 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3685 info->indexed,
3686 info->count,
3687 count_va,
3688 info->stride);
3689 }
3690 }
3691 } else {
3692 assert(state->pipeline->graphics.vtx_base_sgpr);
3693
3694 if (info->vertex_offset != state->last_vertex_offset ||
3695 info->first_instance != state->last_first_instance) {
3696 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3697 state->pipeline->graphics.vtx_emit_num);
3698
3699 radeon_emit(cs, info->vertex_offset);
3700 radeon_emit(cs, info->first_instance);
3701 if (state->pipeline->graphics.vtx_emit_num == 3)
3702 radeon_emit(cs, 0);
3703 state->last_first_instance = info->first_instance;
3704 state->last_vertex_offset = info->vertex_offset;
3705 }
3706
3707 if (state->last_num_instances != info->instance_count) {
3708 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3709 radeon_emit(cs, info->instance_count);
3710 state->last_num_instances = info->instance_count;
3711 }
3712
3713 if (info->indexed) {
3714 int index_size = state->index_type ? 4 : 2;
3715 uint64_t index_va;
3716
3717 index_va = state->index_va;
3718 index_va += info->first_index * index_size;
3719
3720 if (!state->subpass->view_mask) {
3721 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3722 index_va,
3723 info->count);
3724 } else {
3725 unsigned i;
3726 for_each_bit(i, state->subpass->view_mask) {
3727 radv_emit_view_index(cmd_buffer, i);
3728
3729 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3730 index_va,
3731 info->count);
3732 }
3733 }
3734 } else {
3735 if (!state->subpass->view_mask) {
3736 radv_cs_emit_draw_packet(cmd_buffer,
3737 info->count,
3738 !!info->strmout_buffer);
3739 } else {
3740 unsigned i;
3741 for_each_bit(i, state->subpass->view_mask) {
3742 radv_emit_view_index(cmd_buffer, i);
3743
3744 radv_cs_emit_draw_packet(cmd_buffer,
3745 info->count,
3746 !!info->strmout_buffer);
3747 }
3748 }
3749 }
3750 }
3751 }
3752
3753 /*
3754 * Vega and raven have a bug which triggers if there are multiple context
3755 * register contexts active at the same time with different scissor values.
3756 *
3757 * There are two possible workarounds:
3758 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3759 * there is only ever 1 active set of scissor values at the same time.
3760 *
3761 * 2) Whenever the hardware switches contexts we have to set the scissor
3762 * registers again even if it is a noop. That way the new context gets
3763 * the correct scissor values.
3764 *
3765 * This implements option 2. radv_need_late_scissor_emission needs to
3766 * return true on affected HW if radv_emit_all_graphics_states sets
3767 * any context registers.
3768 */
3769 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3770 const struct radv_draw_info *info)
3771 {
3772 struct radv_cmd_state *state = &cmd_buffer->state;
3773
3774 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3775 return false;
3776
3777 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
3778 return true;
3779
3780 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3781
3782 /* Index, vertex and streamout buffers don't change context regs, and
3783 * pipeline is already handled.
3784 */
3785 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3786 RADV_CMD_DIRTY_VERTEX_BUFFER |
3787 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
3788 RADV_CMD_DIRTY_PIPELINE);
3789
3790 if (cmd_buffer->state.dirty & used_states)
3791 return true;
3792
3793 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
3794 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3795 return true;
3796
3797 return false;
3798 }
3799
3800 static void
3801 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3802 const struct radv_draw_info *info)
3803 {
3804 bool late_scissor_emission;
3805
3806 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3807 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3808 radv_emit_rbplus_state(cmd_buffer);
3809
3810 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3811 radv_emit_graphics_pipeline(cmd_buffer);
3812
3813 /* This should be before the cmd_buffer->state.dirty is cleared
3814 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
3815 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
3816 late_scissor_emission =
3817 radv_need_late_scissor_emission(cmd_buffer, info);
3818
3819 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3820 radv_emit_framebuffer_state(cmd_buffer);
3821
3822 if (info->indexed) {
3823 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3824 radv_emit_index_buffer(cmd_buffer);
3825 } else {
3826 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3827 * so the state must be re-emitted before the next indexed
3828 * draw.
3829 */
3830 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3831 cmd_buffer->state.last_index_type = -1;
3832 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3833 }
3834 }
3835
3836 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3837
3838 radv_emit_draw_registers(cmd_buffer, info);
3839
3840 if (late_scissor_emission)
3841 radv_emit_scissor(cmd_buffer);
3842 }
3843
3844 static void
3845 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3846 const struct radv_draw_info *info)
3847 {
3848 struct radeon_info *rad_info =
3849 &cmd_buffer->device->physical_device->rad_info;
3850 bool has_prefetch =
3851 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3852 bool pipeline_is_dirty =
3853 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3854 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3855
3856 MAYBE_UNUSED unsigned cdw_max =
3857 radeon_check_space(cmd_buffer->device->ws,
3858 cmd_buffer->cs, 4096);
3859
3860 if (likely(!info->indirect)) {
3861 /* SI-CI treat instance_count==0 as instance_count==1. There is
3862 * no workaround for indirect draws, but we can at least skip
3863 * direct draws.
3864 */
3865 if (unlikely(!info->instance_count))
3866 return;
3867
3868 /* Handle count == 0. */
3869 if (unlikely(!info->count && !info->strmout_buffer))
3870 return;
3871 }
3872
3873 /* Use optimal packet order based on whether we need to sync the
3874 * pipeline.
3875 */
3876 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3877 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3878 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3879 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3880 /* If we have to wait for idle, set all states first, so that
3881 * all SET packets are processed in parallel with previous draw
3882 * calls. Then upload descriptors, set shader pointers, and
3883 * draw, and prefetch at the end. This ensures that the time
3884 * the CUs are idle is very short. (there are only SET_SH
3885 * packets between the wait and the draw)
3886 */
3887 radv_emit_all_graphics_states(cmd_buffer, info);
3888 si_emit_cache_flush(cmd_buffer);
3889 /* <-- CUs are idle here --> */
3890
3891 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3892
3893 radv_emit_draw_packets(cmd_buffer, info);
3894 /* <-- CUs are busy here --> */
3895
3896 /* Start prefetches after the draw has been started. Both will
3897 * run in parallel, but starting the draw first is more
3898 * important.
3899 */
3900 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3901 radv_emit_prefetch_L2(cmd_buffer,
3902 cmd_buffer->state.pipeline, false);
3903 }
3904 } else {
3905 /* If we don't wait for idle, start prefetches first, then set
3906 * states, and draw at the end.
3907 */
3908 si_emit_cache_flush(cmd_buffer);
3909
3910 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3911 /* Only prefetch the vertex shader and VBO descriptors
3912 * in order to start the draw as soon as possible.
3913 */
3914 radv_emit_prefetch_L2(cmd_buffer,
3915 cmd_buffer->state.pipeline, true);
3916 }
3917
3918 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3919
3920 radv_emit_all_graphics_states(cmd_buffer, info);
3921 radv_emit_draw_packets(cmd_buffer, info);
3922
3923 /* Prefetch the remaining shaders after the draw has been
3924 * started.
3925 */
3926 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3927 radv_emit_prefetch_L2(cmd_buffer,
3928 cmd_buffer->state.pipeline, false);
3929 }
3930 }
3931
3932 /* Workaround for a VGT hang when streamout is enabled.
3933 * It must be done after drawing.
3934 */
3935 if (cmd_buffer->state.streamout.streamout_enabled &&
3936 (rad_info->family == CHIP_HAWAII ||
3937 rad_info->family == CHIP_TONGA ||
3938 rad_info->family == CHIP_FIJI)) {
3939 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
3940 }
3941
3942 assert(cmd_buffer->cs->cdw <= cdw_max);
3943 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3944 }
3945
3946 void radv_CmdDraw(
3947 VkCommandBuffer commandBuffer,
3948 uint32_t vertexCount,
3949 uint32_t instanceCount,
3950 uint32_t firstVertex,
3951 uint32_t firstInstance)
3952 {
3953 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3954 struct radv_draw_info info = {};
3955
3956 info.count = vertexCount;
3957 info.instance_count = instanceCount;
3958 info.first_instance = firstInstance;
3959 info.vertex_offset = firstVertex;
3960
3961 radv_draw(cmd_buffer, &info);
3962 }
3963
3964 void radv_CmdDrawIndexed(
3965 VkCommandBuffer commandBuffer,
3966 uint32_t indexCount,
3967 uint32_t instanceCount,
3968 uint32_t firstIndex,
3969 int32_t vertexOffset,
3970 uint32_t firstInstance)
3971 {
3972 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3973 struct radv_draw_info info = {};
3974
3975 info.indexed = true;
3976 info.count = indexCount;
3977 info.instance_count = instanceCount;
3978 info.first_index = firstIndex;
3979 info.vertex_offset = vertexOffset;
3980 info.first_instance = firstInstance;
3981
3982 radv_draw(cmd_buffer, &info);
3983 }
3984
3985 void radv_CmdDrawIndirect(
3986 VkCommandBuffer commandBuffer,
3987 VkBuffer _buffer,
3988 VkDeviceSize offset,
3989 uint32_t drawCount,
3990 uint32_t stride)
3991 {
3992 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3993 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3994 struct radv_draw_info info = {};
3995
3996 info.count = drawCount;
3997 info.indirect = buffer;
3998 info.indirect_offset = offset;
3999 info.stride = stride;
4000
4001 radv_draw(cmd_buffer, &info);
4002 }
4003
4004 void radv_CmdDrawIndexedIndirect(
4005 VkCommandBuffer commandBuffer,
4006 VkBuffer _buffer,
4007 VkDeviceSize offset,
4008 uint32_t drawCount,
4009 uint32_t stride)
4010 {
4011 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4012 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4013 struct radv_draw_info info = {};
4014
4015 info.indexed = true;
4016 info.count = drawCount;
4017 info.indirect = buffer;
4018 info.indirect_offset = offset;
4019 info.stride = stride;
4020
4021 radv_draw(cmd_buffer, &info);
4022 }
4023
4024 void radv_CmdDrawIndirectCountAMD(
4025 VkCommandBuffer commandBuffer,
4026 VkBuffer _buffer,
4027 VkDeviceSize offset,
4028 VkBuffer _countBuffer,
4029 VkDeviceSize countBufferOffset,
4030 uint32_t maxDrawCount,
4031 uint32_t stride)
4032 {
4033 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4034 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4035 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4036 struct radv_draw_info info = {};
4037
4038 info.count = maxDrawCount;
4039 info.indirect = buffer;
4040 info.indirect_offset = offset;
4041 info.count_buffer = count_buffer;
4042 info.count_buffer_offset = countBufferOffset;
4043 info.stride = stride;
4044
4045 radv_draw(cmd_buffer, &info);
4046 }
4047
4048 void radv_CmdDrawIndexedIndirectCountAMD(
4049 VkCommandBuffer commandBuffer,
4050 VkBuffer _buffer,
4051 VkDeviceSize offset,
4052 VkBuffer _countBuffer,
4053 VkDeviceSize countBufferOffset,
4054 uint32_t maxDrawCount,
4055 uint32_t stride)
4056 {
4057 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4058 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4059 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4060 struct radv_draw_info info = {};
4061
4062 info.indexed = true;
4063 info.count = maxDrawCount;
4064 info.indirect = buffer;
4065 info.indirect_offset = offset;
4066 info.count_buffer = count_buffer;
4067 info.count_buffer_offset = countBufferOffset;
4068 info.stride = stride;
4069
4070 radv_draw(cmd_buffer, &info);
4071 }
4072
4073 void radv_CmdDrawIndirectCountKHR(
4074 VkCommandBuffer commandBuffer,
4075 VkBuffer _buffer,
4076 VkDeviceSize offset,
4077 VkBuffer _countBuffer,
4078 VkDeviceSize countBufferOffset,
4079 uint32_t maxDrawCount,
4080 uint32_t stride)
4081 {
4082 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4083 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4084 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4085 struct radv_draw_info info = {};
4086
4087 info.count = maxDrawCount;
4088 info.indirect = buffer;
4089 info.indirect_offset = offset;
4090 info.count_buffer = count_buffer;
4091 info.count_buffer_offset = countBufferOffset;
4092 info.stride = stride;
4093
4094 radv_draw(cmd_buffer, &info);
4095 }
4096
4097 void radv_CmdDrawIndexedIndirectCountKHR(
4098 VkCommandBuffer commandBuffer,
4099 VkBuffer _buffer,
4100 VkDeviceSize offset,
4101 VkBuffer _countBuffer,
4102 VkDeviceSize countBufferOffset,
4103 uint32_t maxDrawCount,
4104 uint32_t stride)
4105 {
4106 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4107 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4108 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4109 struct radv_draw_info info = {};
4110
4111 info.indexed = true;
4112 info.count = maxDrawCount;
4113 info.indirect = buffer;
4114 info.indirect_offset = offset;
4115 info.count_buffer = count_buffer;
4116 info.count_buffer_offset = countBufferOffset;
4117 info.stride = stride;
4118
4119 radv_draw(cmd_buffer, &info);
4120 }
4121
4122 struct radv_dispatch_info {
4123 /**
4124 * Determine the layout of the grid (in block units) to be used.
4125 */
4126 uint32_t blocks[3];
4127
4128 /**
4129 * A starting offset for the grid. If unaligned is set, the offset
4130 * must still be aligned.
4131 */
4132 uint32_t offsets[3];
4133 /**
4134 * Whether it's an unaligned compute dispatch.
4135 */
4136 bool unaligned;
4137
4138 /**
4139 * Indirect compute parameters resource.
4140 */
4141 struct radv_buffer *indirect;
4142 uint64_t indirect_offset;
4143 };
4144
4145 static void
4146 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4147 const struct radv_dispatch_info *info)
4148 {
4149 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4150 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4151 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4152 struct radeon_winsys *ws = cmd_buffer->device->ws;
4153 bool predicating = cmd_buffer->state.predicating;
4154 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4155 struct radv_userdata_info *loc;
4156
4157 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4158 AC_UD_CS_GRID_SIZE);
4159
4160 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4161
4162 if (info->indirect) {
4163 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4164
4165 va += info->indirect->offset + info->indirect_offset;
4166
4167 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4168
4169 if (loc->sgpr_idx != -1) {
4170 for (unsigned i = 0; i < 3; ++i) {
4171 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4172 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4173 COPY_DATA_DST_SEL(COPY_DATA_REG));
4174 radeon_emit(cs, (va + 4 * i));
4175 radeon_emit(cs, (va + 4 * i) >> 32);
4176 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4177 + loc->sgpr_idx * 4) >> 2) + i);
4178 radeon_emit(cs, 0);
4179 }
4180 }
4181
4182 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4183 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4184 PKT3_SHADER_TYPE_S(1));
4185 radeon_emit(cs, va);
4186 radeon_emit(cs, va >> 32);
4187 radeon_emit(cs, dispatch_initiator);
4188 } else {
4189 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4190 PKT3_SHADER_TYPE_S(1));
4191 radeon_emit(cs, 1);
4192 radeon_emit(cs, va);
4193 radeon_emit(cs, va >> 32);
4194
4195 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4196 PKT3_SHADER_TYPE_S(1));
4197 radeon_emit(cs, 0);
4198 radeon_emit(cs, dispatch_initiator);
4199 }
4200 } else {
4201 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4202 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4203
4204 if (info->unaligned) {
4205 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4206 unsigned remainder[3];
4207
4208 /* If aligned, these should be an entire block size,
4209 * not 0.
4210 */
4211 remainder[0] = blocks[0] + cs_block_size[0] -
4212 align_u32_npot(blocks[0], cs_block_size[0]);
4213 remainder[1] = blocks[1] + cs_block_size[1] -
4214 align_u32_npot(blocks[1], cs_block_size[1]);
4215 remainder[2] = blocks[2] + cs_block_size[2] -
4216 align_u32_npot(blocks[2], cs_block_size[2]);
4217
4218 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4219 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4220 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4221
4222 for(unsigned i = 0; i < 3; ++i) {
4223 assert(offsets[i] % cs_block_size[i] == 0);
4224 offsets[i] /= cs_block_size[i];
4225 }
4226
4227 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4228 radeon_emit(cs,
4229 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4230 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4231 radeon_emit(cs,
4232 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4233 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4234 radeon_emit(cs,
4235 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4236 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4237
4238 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4239 }
4240
4241 if (loc->sgpr_idx != -1) {
4242 assert(loc->num_sgprs == 3);
4243
4244 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4245 loc->sgpr_idx * 4, 3);
4246 radeon_emit(cs, blocks[0]);
4247 radeon_emit(cs, blocks[1]);
4248 radeon_emit(cs, blocks[2]);
4249 }
4250
4251 if (offsets[0] || offsets[1] || offsets[2]) {
4252 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4253 radeon_emit(cs, offsets[0]);
4254 radeon_emit(cs, offsets[1]);
4255 radeon_emit(cs, offsets[2]);
4256
4257 /* The blocks in the packet are not counts but end values. */
4258 for (unsigned i = 0; i < 3; ++i)
4259 blocks[i] += offsets[i];
4260 } else {
4261 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4262 }
4263
4264 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4265 PKT3_SHADER_TYPE_S(1));
4266 radeon_emit(cs, blocks[0]);
4267 radeon_emit(cs, blocks[1]);
4268 radeon_emit(cs, blocks[2]);
4269 radeon_emit(cs, dispatch_initiator);
4270 }
4271
4272 assert(cmd_buffer->cs->cdw <= cdw_max);
4273 }
4274
4275 static void
4276 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4277 {
4278 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4279 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4280 }
4281
4282 static void
4283 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4284 const struct radv_dispatch_info *info)
4285 {
4286 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4287 bool has_prefetch =
4288 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
4289 bool pipeline_is_dirty = pipeline &&
4290 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4291
4292 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4293 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4294 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4295 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4296 /* If we have to wait for idle, set all states first, so that
4297 * all SET packets are processed in parallel with previous draw
4298 * calls. Then upload descriptors, set shader pointers, and
4299 * dispatch, and prefetch at the end. This ensures that the
4300 * time the CUs are idle is very short. (there are only SET_SH
4301 * packets between the wait and the draw)
4302 */
4303 radv_emit_compute_pipeline(cmd_buffer);
4304 si_emit_cache_flush(cmd_buffer);
4305 /* <-- CUs are idle here --> */
4306
4307 radv_upload_compute_shader_descriptors(cmd_buffer);
4308
4309 radv_emit_dispatch_packets(cmd_buffer, info);
4310 /* <-- CUs are busy here --> */
4311
4312 /* Start prefetches after the dispatch has been started. Both
4313 * will run in parallel, but starting the dispatch first is
4314 * more important.
4315 */
4316 if (has_prefetch && pipeline_is_dirty) {
4317 radv_emit_shader_prefetch(cmd_buffer,
4318 pipeline->shaders[MESA_SHADER_COMPUTE]);
4319 }
4320 } else {
4321 /* If we don't wait for idle, start prefetches first, then set
4322 * states, and dispatch at the end.
4323 */
4324 si_emit_cache_flush(cmd_buffer);
4325
4326 if (has_prefetch && pipeline_is_dirty) {
4327 radv_emit_shader_prefetch(cmd_buffer,
4328 pipeline->shaders[MESA_SHADER_COMPUTE]);
4329 }
4330
4331 radv_upload_compute_shader_descriptors(cmd_buffer);
4332
4333 radv_emit_compute_pipeline(cmd_buffer);
4334 radv_emit_dispatch_packets(cmd_buffer, info);
4335 }
4336
4337 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4338 }
4339
4340 void radv_CmdDispatchBase(
4341 VkCommandBuffer commandBuffer,
4342 uint32_t base_x,
4343 uint32_t base_y,
4344 uint32_t base_z,
4345 uint32_t x,
4346 uint32_t y,
4347 uint32_t z)
4348 {
4349 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4350 struct radv_dispatch_info info = {};
4351
4352 info.blocks[0] = x;
4353 info.blocks[1] = y;
4354 info.blocks[2] = z;
4355
4356 info.offsets[0] = base_x;
4357 info.offsets[1] = base_y;
4358 info.offsets[2] = base_z;
4359 radv_dispatch(cmd_buffer, &info);
4360 }
4361
4362 void radv_CmdDispatch(
4363 VkCommandBuffer commandBuffer,
4364 uint32_t x,
4365 uint32_t y,
4366 uint32_t z)
4367 {
4368 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4369 }
4370
4371 void radv_CmdDispatchIndirect(
4372 VkCommandBuffer commandBuffer,
4373 VkBuffer _buffer,
4374 VkDeviceSize offset)
4375 {
4376 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4377 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4378 struct radv_dispatch_info info = {};
4379
4380 info.indirect = buffer;
4381 info.indirect_offset = offset;
4382
4383 radv_dispatch(cmd_buffer, &info);
4384 }
4385
4386 void radv_unaligned_dispatch(
4387 struct radv_cmd_buffer *cmd_buffer,
4388 uint32_t x,
4389 uint32_t y,
4390 uint32_t z)
4391 {
4392 struct radv_dispatch_info info = {};
4393
4394 info.blocks[0] = x;
4395 info.blocks[1] = y;
4396 info.blocks[2] = z;
4397 info.unaligned = 1;
4398
4399 radv_dispatch(cmd_buffer, &info);
4400 }
4401
4402 void radv_CmdEndRenderPass(
4403 VkCommandBuffer commandBuffer)
4404 {
4405 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4406
4407 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4408
4409 radv_cmd_buffer_end_subpass(cmd_buffer);
4410
4411 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4412
4413 cmd_buffer->state.pass = NULL;
4414 cmd_buffer->state.subpass = NULL;
4415 cmd_buffer->state.attachments = NULL;
4416 cmd_buffer->state.framebuffer = NULL;
4417 }
4418
4419 void radv_CmdEndRenderPass2KHR(
4420 VkCommandBuffer commandBuffer,
4421 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4422 {
4423 radv_CmdEndRenderPass(commandBuffer);
4424 }
4425
4426 /*
4427 * For HTILE we have the following interesting clear words:
4428 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4429 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4430 * 0xfffffff0: Clear depth to 1.0
4431 * 0x00000000: Clear depth to 0.0
4432 */
4433 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4434 struct radv_image *image,
4435 const VkImageSubresourceRange *range,
4436 uint32_t clear_word)
4437 {
4438 assert(range->baseMipLevel == 0);
4439 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4440 unsigned layer_count = radv_get_layerCount(image, range);
4441 uint64_t size = image->planes[0].surface.htile_slice_size * layer_count;
4442 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4443 uint64_t offset = image->offset + image->htile_offset +
4444 image->planes[0].surface.htile_slice_size * range->baseArrayLayer;
4445 struct radv_cmd_state *state = &cmd_buffer->state;
4446 VkClearDepthStencilValue value = {};
4447
4448 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4449 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4450
4451 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4452 size, clear_word);
4453
4454 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4455
4456 if (vk_format_is_stencil(image->vk_format))
4457 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4458
4459 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4460
4461 if (radv_image_is_tc_compat_htile(image)) {
4462 /* Initialize the TC-compat metada value to 0 because by
4463 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4464 * need have to conditionally update its value when performing
4465 * a fast depth clear.
4466 */
4467 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4468 }
4469 }
4470
4471 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4472 struct radv_image *image,
4473 VkImageLayout src_layout,
4474 VkImageLayout dst_layout,
4475 unsigned src_queue_mask,
4476 unsigned dst_queue_mask,
4477 const VkImageSubresourceRange *range)
4478 {
4479 if (!radv_image_has_htile(image))
4480 return;
4481
4482 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4483 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4484
4485 if (radv_layout_is_htile_compressed(image, dst_layout,
4486 dst_queue_mask)) {
4487 clear_value = 0;
4488 }
4489
4490 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4491 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4492 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4493 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4494 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4495 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4496 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4497 VkImageSubresourceRange local_range = *range;
4498 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4499 local_range.baseMipLevel = 0;
4500 local_range.levelCount = 1;
4501
4502 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4503 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4504
4505 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4506
4507 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4508 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4509 }
4510 }
4511
4512 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4513 struct radv_image *image, uint32_t value)
4514 {
4515 struct radv_cmd_state *state = &cmd_buffer->state;
4516
4517 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4518 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4519
4520 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4521
4522 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4523 }
4524
4525 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4526 struct radv_image *image)
4527 {
4528 struct radv_cmd_state *state = &cmd_buffer->state;
4529 static const uint32_t fmask_clear_values[4] = {
4530 0x00000000,
4531 0x02020202,
4532 0xE4E4E4E4,
4533 0x76543210
4534 };
4535 uint32_t log2_samples = util_logbase2(image->info.samples);
4536 uint32_t value = fmask_clear_values[log2_samples];
4537
4538 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4539 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4540
4541 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
4542
4543 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4544 }
4545
4546 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4547 struct radv_image *image, uint32_t value)
4548 {
4549 struct radv_cmd_state *state = &cmd_buffer->state;
4550
4551 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4552 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4553
4554 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4555
4556 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4557 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4558 }
4559
4560 /**
4561 * Initialize DCC/FMASK/CMASK metadata for a color image.
4562 */
4563 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4564 struct radv_image *image,
4565 VkImageLayout src_layout,
4566 VkImageLayout dst_layout,
4567 unsigned src_queue_mask,
4568 unsigned dst_queue_mask)
4569 {
4570 if (radv_image_has_cmask(image)) {
4571 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4572
4573 /* TODO: clarify this. */
4574 if (radv_image_has_fmask(image)) {
4575 value = 0xccccccccu;
4576 }
4577
4578 radv_initialise_cmask(cmd_buffer, image, value);
4579 }
4580
4581 if (radv_image_has_fmask(image)) {
4582 radv_initialize_fmask(cmd_buffer, image);
4583 }
4584
4585 if (radv_image_has_dcc(image)) {
4586 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4587 bool need_decompress_pass = false;
4588
4589 if (radv_layout_dcc_compressed(image, dst_layout,
4590 dst_queue_mask)) {
4591 value = 0x20202020u;
4592 need_decompress_pass = true;
4593 }
4594
4595 radv_initialize_dcc(cmd_buffer, image, value);
4596
4597 radv_update_fce_metadata(cmd_buffer, image,
4598 need_decompress_pass);
4599 }
4600
4601 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4602 uint32_t color_values[2] = {};
4603 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4604 }
4605 }
4606
4607 /**
4608 * Handle color image transitions for DCC/FMASK/CMASK.
4609 */
4610 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4611 struct radv_image *image,
4612 VkImageLayout src_layout,
4613 VkImageLayout dst_layout,
4614 unsigned src_queue_mask,
4615 unsigned dst_queue_mask,
4616 const VkImageSubresourceRange *range)
4617 {
4618 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4619 radv_init_color_image_metadata(cmd_buffer, image,
4620 src_layout, dst_layout,
4621 src_queue_mask, dst_queue_mask);
4622 return;
4623 }
4624
4625 if (radv_image_has_dcc(image)) {
4626 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4627 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4628 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4629 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4630 radv_decompress_dcc(cmd_buffer, image, range);
4631 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4632 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4633 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4634 }
4635 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4636 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4637 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4638 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4639 }
4640
4641 if (radv_image_has_fmask(image)) {
4642 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
4643 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
4644 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
4645 }
4646 }
4647 }
4648 }
4649
4650 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4651 struct radv_image *image,
4652 VkImageLayout src_layout,
4653 VkImageLayout dst_layout,
4654 uint32_t src_family,
4655 uint32_t dst_family,
4656 const VkImageSubresourceRange *range)
4657 {
4658 if (image->exclusive && src_family != dst_family) {
4659 /* This is an acquire or a release operation and there will be
4660 * a corresponding release/acquire. Do the transition in the
4661 * most flexible queue. */
4662
4663 assert(src_family == cmd_buffer->queue_family_index ||
4664 dst_family == cmd_buffer->queue_family_index);
4665
4666 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4667 return;
4668
4669 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4670 (src_family == RADV_QUEUE_GENERAL ||
4671 dst_family == RADV_QUEUE_GENERAL))
4672 return;
4673 }
4674
4675 if (src_layout == dst_layout)
4676 return;
4677
4678 unsigned src_queue_mask =
4679 radv_image_queue_family_mask(image, src_family,
4680 cmd_buffer->queue_family_index);
4681 unsigned dst_queue_mask =
4682 radv_image_queue_family_mask(image, dst_family,
4683 cmd_buffer->queue_family_index);
4684
4685 if (vk_format_is_depth(image->vk_format)) {
4686 radv_handle_depth_image_transition(cmd_buffer, image,
4687 src_layout, dst_layout,
4688 src_queue_mask, dst_queue_mask,
4689 range);
4690 } else {
4691 radv_handle_color_image_transition(cmd_buffer, image,
4692 src_layout, dst_layout,
4693 src_queue_mask, dst_queue_mask,
4694 range);
4695 }
4696 }
4697
4698 struct radv_barrier_info {
4699 uint32_t eventCount;
4700 const VkEvent *pEvents;
4701 VkPipelineStageFlags srcStageMask;
4702 VkPipelineStageFlags dstStageMask;
4703 };
4704
4705 static void
4706 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4707 uint32_t memoryBarrierCount,
4708 const VkMemoryBarrier *pMemoryBarriers,
4709 uint32_t bufferMemoryBarrierCount,
4710 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4711 uint32_t imageMemoryBarrierCount,
4712 const VkImageMemoryBarrier *pImageMemoryBarriers,
4713 const struct radv_barrier_info *info)
4714 {
4715 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4716 enum radv_cmd_flush_bits src_flush_bits = 0;
4717 enum radv_cmd_flush_bits dst_flush_bits = 0;
4718
4719 for (unsigned i = 0; i < info->eventCount; ++i) {
4720 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4721 uint64_t va = radv_buffer_get_va(event->bo);
4722
4723 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4724
4725 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4726
4727 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
4728 assert(cmd_buffer->cs->cdw <= cdw_max);
4729 }
4730
4731 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4732 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4733 NULL);
4734 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4735 NULL);
4736 }
4737
4738 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4739 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4740 NULL);
4741 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4742 NULL);
4743 }
4744
4745 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4746 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4747
4748 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4749 image);
4750 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4751 image);
4752 }
4753
4754 /* The Vulkan spec 1.1.98 says:
4755 *
4756 * "An execution dependency with only
4757 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
4758 * will only prevent that stage from executing in subsequently
4759 * submitted commands. As this stage does not perform any actual
4760 * execution, this is not observable - in effect, it does not delay
4761 * processing of subsequent commands. Similarly an execution dependency
4762 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
4763 * will effectively not wait for any prior commands to complete."
4764 */
4765 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
4766 radv_stage_flush(cmd_buffer, info->srcStageMask);
4767 cmd_buffer->state.flush_bits |= src_flush_bits;
4768
4769 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4770 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4771 radv_handle_image_transition(cmd_buffer, image,
4772 pImageMemoryBarriers[i].oldLayout,
4773 pImageMemoryBarriers[i].newLayout,
4774 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4775 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4776 &pImageMemoryBarriers[i].subresourceRange);
4777 }
4778
4779 /* Make sure CP DMA is idle because the driver might have performed a
4780 * DMA operation for copying or filling buffers/images.
4781 */
4782 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4783 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4784 si_cp_dma_wait_for_idle(cmd_buffer);
4785
4786 cmd_buffer->state.flush_bits |= dst_flush_bits;
4787 }
4788
4789 void radv_CmdPipelineBarrier(
4790 VkCommandBuffer commandBuffer,
4791 VkPipelineStageFlags srcStageMask,
4792 VkPipelineStageFlags destStageMask,
4793 VkBool32 byRegion,
4794 uint32_t memoryBarrierCount,
4795 const VkMemoryBarrier* pMemoryBarriers,
4796 uint32_t bufferMemoryBarrierCount,
4797 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4798 uint32_t imageMemoryBarrierCount,
4799 const VkImageMemoryBarrier* pImageMemoryBarriers)
4800 {
4801 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4802 struct radv_barrier_info info;
4803
4804 info.eventCount = 0;
4805 info.pEvents = NULL;
4806 info.srcStageMask = srcStageMask;
4807 info.dstStageMask = destStageMask;
4808
4809 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4810 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4811 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4812 }
4813
4814
4815 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4816 struct radv_event *event,
4817 VkPipelineStageFlags stageMask,
4818 unsigned value)
4819 {
4820 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4821 uint64_t va = radv_buffer_get_va(event->bo);
4822
4823 si_emit_cache_flush(cmd_buffer);
4824
4825 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4826
4827 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4828
4829 /* Flags that only require a top-of-pipe event. */
4830 VkPipelineStageFlags top_of_pipe_flags =
4831 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4832
4833 /* Flags that only require a post-index-fetch event. */
4834 VkPipelineStageFlags post_index_fetch_flags =
4835 top_of_pipe_flags |
4836 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4837 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4838
4839 /* Make sure CP DMA is idle because the driver might have performed a
4840 * DMA operation for copying or filling buffers/images.
4841 */
4842 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4843 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4844 si_cp_dma_wait_for_idle(cmd_buffer);
4845
4846 /* TODO: Emit EOS events for syncing PS/CS stages. */
4847
4848 if (!(stageMask & ~top_of_pipe_flags)) {
4849 /* Just need to sync the PFP engine. */
4850 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4851 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4852 S_370_WR_CONFIRM(1) |
4853 S_370_ENGINE_SEL(V_370_PFP));
4854 radeon_emit(cs, va);
4855 radeon_emit(cs, va >> 32);
4856 radeon_emit(cs, value);
4857 } else if (!(stageMask & ~post_index_fetch_flags)) {
4858 /* Sync ME because PFP reads index and indirect buffers. */
4859 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4860 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4861 S_370_WR_CONFIRM(1) |
4862 S_370_ENGINE_SEL(V_370_ME));
4863 radeon_emit(cs, va);
4864 radeon_emit(cs, va >> 32);
4865 radeon_emit(cs, value);
4866 } else {
4867 /* Otherwise, sync all prior GPU work using an EOP event. */
4868 si_cs_emit_write_event_eop(cs,
4869 cmd_buffer->device->physical_device->rad_info.chip_class,
4870 radv_cmd_buffer_uses_mec(cmd_buffer),
4871 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4872 EOP_DATA_SEL_VALUE_32BIT, va, value,
4873 cmd_buffer->gfx9_eop_bug_va);
4874 }
4875
4876 assert(cmd_buffer->cs->cdw <= cdw_max);
4877 }
4878
4879 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4880 VkEvent _event,
4881 VkPipelineStageFlags stageMask)
4882 {
4883 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4884 RADV_FROM_HANDLE(radv_event, event, _event);
4885
4886 write_event(cmd_buffer, event, stageMask, 1);
4887 }
4888
4889 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4890 VkEvent _event,
4891 VkPipelineStageFlags stageMask)
4892 {
4893 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4894 RADV_FROM_HANDLE(radv_event, event, _event);
4895
4896 write_event(cmd_buffer, event, stageMask, 0);
4897 }
4898
4899 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4900 uint32_t eventCount,
4901 const VkEvent* pEvents,
4902 VkPipelineStageFlags srcStageMask,
4903 VkPipelineStageFlags dstStageMask,
4904 uint32_t memoryBarrierCount,
4905 const VkMemoryBarrier* pMemoryBarriers,
4906 uint32_t bufferMemoryBarrierCount,
4907 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4908 uint32_t imageMemoryBarrierCount,
4909 const VkImageMemoryBarrier* pImageMemoryBarriers)
4910 {
4911 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4912 struct radv_barrier_info info;
4913
4914 info.eventCount = eventCount;
4915 info.pEvents = pEvents;
4916 info.srcStageMask = 0;
4917
4918 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4919 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4920 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4921 }
4922
4923
4924 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4925 uint32_t deviceMask)
4926 {
4927 /* No-op */
4928 }
4929
4930 /* VK_EXT_conditional_rendering */
4931 void radv_CmdBeginConditionalRenderingEXT(
4932 VkCommandBuffer commandBuffer,
4933 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4934 {
4935 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4936 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4937 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4938 bool draw_visible = true;
4939 uint64_t pred_value = 0;
4940 uint64_t va, new_va;
4941 unsigned pred_offset;
4942
4943 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4944
4945 /* By default, if the 32-bit value at offset in buffer memory is zero,
4946 * then the rendering commands are discarded, otherwise they are
4947 * executed as normal. If the inverted flag is set, all commands are
4948 * discarded if the value is non zero.
4949 */
4950 if (pConditionalRenderingBegin->flags &
4951 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4952 draw_visible = false;
4953 }
4954
4955 si_emit_cache_flush(cmd_buffer);
4956
4957 /* From the Vulkan spec 1.1.107:
4958 *
4959 * "If the 32-bit value at offset in buffer memory is zero, then the
4960 * rendering commands are discarded, otherwise they are executed as
4961 * normal. If the value of the predicate in buffer memory changes while
4962 * conditional rendering is active, the rendering commands may be
4963 * discarded in an implementation-dependent way. Some implementations
4964 * may latch the value of the predicate upon beginning conditional
4965 * rendering while others may read it before every rendering command."
4966 *
4967 * But, the AMD hardware treats the predicate as a 64-bit value which
4968 * means we need a workaround in the driver. Luckily, it's not required
4969 * to support if the value changes when predication is active.
4970 *
4971 * The workaround is as follows:
4972 * 1) allocate a 64-value in the upload BO and initialize it to 0
4973 * 2) copy the 32-bit predicate value to the upload BO
4974 * 3) use the new allocated VA address for predication
4975 *
4976 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
4977 * in ME (+ sync PFP) instead of PFP.
4978 */
4979 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
4980
4981 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
4982
4983 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4984 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4985 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
4986 COPY_DATA_WR_CONFIRM);
4987 radeon_emit(cs, va);
4988 radeon_emit(cs, va >> 32);
4989 radeon_emit(cs, new_va);
4990 radeon_emit(cs, new_va >> 32);
4991
4992 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
4993 radeon_emit(cs, 0);
4994
4995 /* Enable predication for this command buffer. */
4996 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
4997 cmd_buffer->state.predicating = true;
4998
4999 /* Store conditional rendering user info. */
5000 cmd_buffer->state.predication_type = draw_visible;
5001 cmd_buffer->state.predication_va = new_va;
5002 }
5003
5004 void radv_CmdEndConditionalRenderingEXT(
5005 VkCommandBuffer commandBuffer)
5006 {
5007 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5008
5009 /* Disable predication for this command buffer. */
5010 si_emit_set_predication_state(cmd_buffer, false, 0);
5011 cmd_buffer->state.predicating = false;
5012
5013 /* Reset conditional rendering user info. */
5014 cmd_buffer->state.predication_type = -1;
5015 cmd_buffer->state.predication_va = 0;
5016 }
5017
5018 /* VK_EXT_transform_feedback */
5019 void radv_CmdBindTransformFeedbackBuffersEXT(
5020 VkCommandBuffer commandBuffer,
5021 uint32_t firstBinding,
5022 uint32_t bindingCount,
5023 const VkBuffer* pBuffers,
5024 const VkDeviceSize* pOffsets,
5025 const VkDeviceSize* pSizes)
5026 {
5027 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5028 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5029 uint8_t enabled_mask = 0;
5030
5031 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5032 for (uint32_t i = 0; i < bindingCount; i++) {
5033 uint32_t idx = firstBinding + i;
5034
5035 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5036 sb[idx].offset = pOffsets[i];
5037 sb[idx].size = pSizes[i];
5038
5039 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5040 sb[idx].buffer->bo);
5041
5042 enabled_mask |= 1 << idx;
5043 }
5044
5045 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5046
5047 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5048 }
5049
5050 static void
5051 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5052 {
5053 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5054 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5055
5056 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5057 radeon_emit(cs,
5058 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5059 S_028B94_RAST_STREAM(0) |
5060 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5061 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5062 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5063 radeon_emit(cs, so->hw_enabled_mask &
5064 so->enabled_stream_buffers_mask);
5065
5066 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5067 }
5068
5069 static void
5070 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5071 {
5072 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5073 bool old_streamout_enabled = so->streamout_enabled;
5074 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5075
5076 so->streamout_enabled = enable;
5077
5078 so->hw_enabled_mask = so->enabled_mask |
5079 (so->enabled_mask << 4) |
5080 (so->enabled_mask << 8) |
5081 (so->enabled_mask << 12);
5082
5083 if ((old_streamout_enabled != so->streamout_enabled) ||
5084 (old_hw_enabled_mask != so->hw_enabled_mask))
5085 radv_emit_streamout_enable(cmd_buffer);
5086 }
5087
5088 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5089 {
5090 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5091 unsigned reg_strmout_cntl;
5092
5093 /* The register is at different places on different ASICs. */
5094 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
5095 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5096 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5097 } else {
5098 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5099 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5100 }
5101
5102 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5103 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5104
5105 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5106 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5107 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5108 radeon_emit(cs, 0);
5109 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5110 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5111 radeon_emit(cs, 4); /* poll interval */
5112 }
5113
5114 void radv_CmdBeginTransformFeedbackEXT(
5115 VkCommandBuffer commandBuffer,
5116 uint32_t firstCounterBuffer,
5117 uint32_t counterBufferCount,
5118 const VkBuffer* pCounterBuffers,
5119 const VkDeviceSize* pCounterBufferOffsets)
5120 {
5121 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5122 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5123 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5124 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5125 uint32_t i;
5126
5127 radv_flush_vgt_streamout(cmd_buffer);
5128
5129 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5130 for_each_bit(i, so->enabled_mask) {
5131 int32_t counter_buffer_idx = i - firstCounterBuffer;
5132 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5133 counter_buffer_idx = -1;
5134
5135 /* SI binds streamout buffers as shader resources.
5136 * VGT only counts primitives and tells the shader through
5137 * SGPRs what to do.
5138 */
5139 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5140 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5141 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5142
5143 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5144
5145 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5146 /* The array of counter buffers is optional. */
5147 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5148 uint64_t va = radv_buffer_get_va(buffer->bo);
5149
5150 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5151
5152 /* Append */
5153 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5154 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5155 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5156 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5157 radeon_emit(cs, 0); /* unused */
5158 radeon_emit(cs, 0); /* unused */
5159 radeon_emit(cs, va); /* src address lo */
5160 radeon_emit(cs, va >> 32); /* src address hi */
5161
5162 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5163 } else {
5164 /* Start from the beginning. */
5165 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5166 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5167 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5168 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5169 radeon_emit(cs, 0); /* unused */
5170 radeon_emit(cs, 0); /* unused */
5171 radeon_emit(cs, 0); /* unused */
5172 radeon_emit(cs, 0); /* unused */
5173 }
5174 }
5175
5176 radv_set_streamout_enable(cmd_buffer, true);
5177 }
5178
5179 void radv_CmdEndTransformFeedbackEXT(
5180 VkCommandBuffer commandBuffer,
5181 uint32_t firstCounterBuffer,
5182 uint32_t counterBufferCount,
5183 const VkBuffer* pCounterBuffers,
5184 const VkDeviceSize* pCounterBufferOffsets)
5185 {
5186 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5187 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5188 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5189 uint32_t i;
5190
5191 radv_flush_vgt_streamout(cmd_buffer);
5192
5193 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5194 for_each_bit(i, so->enabled_mask) {
5195 int32_t counter_buffer_idx = i - firstCounterBuffer;
5196 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5197 counter_buffer_idx = -1;
5198
5199 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5200 /* The array of counters buffer is optional. */
5201 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5202 uint64_t va = radv_buffer_get_va(buffer->bo);
5203
5204 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5205
5206 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5207 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5208 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5209 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5210 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5211 radeon_emit(cs, va); /* dst address lo */
5212 radeon_emit(cs, va >> 32); /* dst address hi */
5213 radeon_emit(cs, 0); /* unused */
5214 radeon_emit(cs, 0); /* unused */
5215
5216 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5217 }
5218
5219 /* Deactivate transform feedback by zeroing the buffer size.
5220 * The counters (primitives generated, primitives emitted) may
5221 * be enabled even if there is not buffer bound. This ensures
5222 * that the primitives-emitted query won't increment.
5223 */
5224 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5225
5226 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5227 }
5228
5229 radv_set_streamout_enable(cmd_buffer, false);
5230 }
5231
5232 void radv_CmdDrawIndirectByteCountEXT(
5233 VkCommandBuffer commandBuffer,
5234 uint32_t instanceCount,
5235 uint32_t firstInstance,
5236 VkBuffer _counterBuffer,
5237 VkDeviceSize counterBufferOffset,
5238 uint32_t counterOffset,
5239 uint32_t vertexStride)
5240 {
5241 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5242 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5243 struct radv_draw_info info = {};
5244
5245 info.instance_count = instanceCount;
5246 info.first_instance = firstInstance;
5247 info.strmout_buffer = counterBuffer;
5248 info.strmout_buffer_offset = counterBufferOffset;
5249 info.stride = vertexStride;
5250
5251 radv_draw(cmd_buffer, &info);
5252 }