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radv/gfx10: implement radv_emit_fb_ds_state()
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 struct radv_sample_locations_state *sample_locs);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109 dest->sample_location.count = src->sample_location.count;
110
111 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
112 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
113 src->viewport.count * sizeof(VkViewport))) {
114 typed_memcpy(dest->viewport.viewports,
115 src->viewport.viewports,
116 src->viewport.count);
117 dest_mask |= RADV_DYNAMIC_VIEWPORT;
118 }
119 }
120
121 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
122 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
123 src->scissor.count * sizeof(VkRect2D))) {
124 typed_memcpy(dest->scissor.scissors,
125 src->scissor.scissors, src->scissor.count);
126 dest_mask |= RADV_DYNAMIC_SCISSOR;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
131 if (dest->line_width != src->line_width) {
132 dest->line_width = src->line_width;
133 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
134 }
135 }
136
137 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
138 if (memcmp(&dest->depth_bias, &src->depth_bias,
139 sizeof(src->depth_bias))) {
140 dest->depth_bias = src->depth_bias;
141 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
142 }
143 }
144
145 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
146 if (memcmp(&dest->blend_constants, &src->blend_constants,
147 sizeof(src->blend_constants))) {
148 typed_memcpy(dest->blend_constants,
149 src->blend_constants, 4);
150 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
151 }
152 }
153
154 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
155 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
156 sizeof(src->depth_bounds))) {
157 dest->depth_bounds = src->depth_bounds;
158 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
159 }
160 }
161
162 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
163 if (memcmp(&dest->stencil_compare_mask,
164 &src->stencil_compare_mask,
165 sizeof(src->stencil_compare_mask))) {
166 dest->stencil_compare_mask = src->stencil_compare_mask;
167 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
168 }
169 }
170
171 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
172 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
173 sizeof(src->stencil_write_mask))) {
174 dest->stencil_write_mask = src->stencil_write_mask;
175 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
176 }
177 }
178
179 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
180 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
181 sizeof(src->stencil_reference))) {
182 dest->stencil_reference = src->stencil_reference;
183 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
184 }
185 }
186
187 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
188 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
189 src->discard_rectangle.count * sizeof(VkRect2D))) {
190 typed_memcpy(dest->discard_rectangle.rectangles,
191 src->discard_rectangle.rectangles,
192 src->discard_rectangle.count);
193 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
194 }
195 }
196
197 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
198 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
199 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
200 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
201 memcmp(&dest->sample_location.locations,
202 &src->sample_location.locations,
203 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
204 dest->sample_location.per_pixel = src->sample_location.per_pixel;
205 dest->sample_location.grid_size = src->sample_location.grid_size;
206 typed_memcpy(dest->sample_location.locations,
207 src->sample_location.locations,
208 src->sample_location.count);
209 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
210 }
211 }
212
213 cmd_buffer->state.dirty |= dest_mask;
214 }
215
216 static void
217 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
218 struct radv_pipeline *pipeline)
219 {
220 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
221 struct radv_shader_info *info;
222
223 if (!pipeline->streamout_shader)
224 return;
225
226 info = &pipeline->streamout_shader->info.info;
227 for (int i = 0; i < MAX_SO_BUFFERS; i++)
228 so->stride_in_dw[i] = info->so.strides[i];
229
230 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
231 }
232
233 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
234 {
235 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
236 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
237 }
238
239 enum ring_type radv_queue_family_to_ring(int f) {
240 switch (f) {
241 case RADV_QUEUE_GENERAL:
242 return RING_GFX;
243 case RADV_QUEUE_COMPUTE:
244 return RING_COMPUTE;
245 case RADV_QUEUE_TRANSFER:
246 return RING_DMA;
247 default:
248 unreachable("Unknown queue family");
249 }
250 }
251
252 static VkResult radv_create_cmd_buffer(
253 struct radv_device * device,
254 struct radv_cmd_pool * pool,
255 VkCommandBufferLevel level,
256 VkCommandBuffer* pCommandBuffer)
257 {
258 struct radv_cmd_buffer *cmd_buffer;
259 unsigned ring;
260 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
262 if (cmd_buffer == NULL)
263 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
264
265 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 cmd_buffer->device = device;
267 cmd_buffer->pool = pool;
268 cmd_buffer->level = level;
269
270 if (pool) {
271 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
272 cmd_buffer->queue_family_index = pool->queue_family_index;
273
274 } else {
275 /* Init the pool_link so we can safely call list_del when we destroy
276 * the command buffer
277 */
278 list_inithead(&cmd_buffer->pool_link);
279 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
280 }
281
282 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
283
284 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
285 if (!cmd_buffer->cs) {
286 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
287 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
288 }
289
290 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
291
292 list_inithead(&cmd_buffer->upload.list);
293
294 return VK_SUCCESS;
295 }
296
297 static void
298 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
299 {
300 list_del(&cmd_buffer->pool_link);
301
302 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
303 &cmd_buffer->upload.list, list) {
304 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
305 list_del(&up->list);
306 free(up);
307 }
308
309 if (cmd_buffer->upload.upload_bo)
310 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
311 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
312
313 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
314 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
315
316 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
317 }
318
319 static VkResult
320 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
321 {
322 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
323
324 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
325 &cmd_buffer->upload.list, list) {
326 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
327 list_del(&up->list);
328 free(up);
329 }
330
331 cmd_buffer->push_constant_stages = 0;
332 cmd_buffer->scratch_size_needed = 0;
333 cmd_buffer->compute_scratch_size_needed = 0;
334 cmd_buffer->esgs_ring_size_needed = 0;
335 cmd_buffer->gsvs_ring_size_needed = 0;
336 cmd_buffer->tess_rings_needed = false;
337 cmd_buffer->sample_positions_needed = false;
338
339 if (cmd_buffer->upload.upload_bo)
340 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
341 cmd_buffer->upload.upload_bo);
342 cmd_buffer->upload.offset = 0;
343
344 cmd_buffer->record_result = VK_SUCCESS;
345
346 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
347
348 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
349 cmd_buffer->descriptors[i].dirty = 0;
350 cmd_buffer->descriptors[i].valid = 0;
351 cmd_buffer->descriptors[i].push_dirty = false;
352 }
353
354 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
355 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
356 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
357 unsigned fence_offset, eop_bug_offset;
358 void *fence_ptr;
359
360 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
361 &fence_ptr);
362
363 cmd_buffer->gfx9_fence_va =
364 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
365 cmd_buffer->gfx9_fence_va += fence_offset;
366
367 /* Allocate a buffer for the EOP bug on GFX9. */
368 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
369 &eop_bug_offset, &fence_ptr);
370 cmd_buffer->gfx9_eop_bug_va =
371 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
372 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
373 }
374
375 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
376
377 return cmd_buffer->record_result;
378 }
379
380 static bool
381 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
382 uint64_t min_needed)
383 {
384 uint64_t new_size;
385 struct radeon_winsys_bo *bo;
386 struct radv_cmd_buffer_upload *upload;
387 struct radv_device *device = cmd_buffer->device;
388
389 new_size = MAX2(min_needed, 16 * 1024);
390 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
391
392 bo = device->ws->buffer_create(device->ws,
393 new_size, 4096,
394 RADEON_DOMAIN_GTT,
395 RADEON_FLAG_CPU_ACCESS|
396 RADEON_FLAG_NO_INTERPROCESS_SHARING |
397 RADEON_FLAG_32BIT,
398 RADV_BO_PRIORITY_UPLOAD_BUFFER);
399
400 if (!bo) {
401 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
402 return false;
403 }
404
405 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
406 if (cmd_buffer->upload.upload_bo) {
407 upload = malloc(sizeof(*upload));
408
409 if (!upload) {
410 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
411 device->ws->buffer_destroy(bo);
412 return false;
413 }
414
415 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
416 list_add(&upload->list, &cmd_buffer->upload.list);
417 }
418
419 cmd_buffer->upload.upload_bo = bo;
420 cmd_buffer->upload.size = new_size;
421 cmd_buffer->upload.offset = 0;
422 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
423
424 if (!cmd_buffer->upload.map) {
425 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
426 return false;
427 }
428
429 return true;
430 }
431
432 bool
433 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
434 unsigned size,
435 unsigned alignment,
436 unsigned *out_offset,
437 void **ptr)
438 {
439 assert(util_is_power_of_two_nonzero(alignment));
440
441 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
442 if (offset + size > cmd_buffer->upload.size) {
443 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
444 return false;
445 offset = 0;
446 }
447
448 *out_offset = offset;
449 *ptr = cmd_buffer->upload.map + offset;
450
451 cmd_buffer->upload.offset = offset + size;
452 return true;
453 }
454
455 bool
456 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
457 unsigned size, unsigned alignment,
458 const void *data, unsigned *out_offset)
459 {
460 uint8_t *ptr;
461
462 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
463 out_offset, (void **)&ptr))
464 return false;
465
466 if (ptr)
467 memcpy(ptr, data, size);
468
469 return true;
470 }
471
472 static void
473 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
474 unsigned count, const uint32_t *data)
475 {
476 struct radeon_cmdbuf *cs = cmd_buffer->cs;
477
478 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
479
480 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
481 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
482 S_370_WR_CONFIRM(1) |
483 S_370_ENGINE_SEL(V_370_ME));
484 radeon_emit(cs, va);
485 radeon_emit(cs, va >> 32);
486 radeon_emit_array(cs, data, count);
487 }
488
489 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
490 {
491 struct radv_device *device = cmd_buffer->device;
492 struct radeon_cmdbuf *cs = cmd_buffer->cs;
493 uint64_t va;
494
495 va = radv_buffer_get_va(device->trace_bo);
496 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
497 va += 4;
498
499 ++cmd_buffer->state.trace_id;
500 radv_emit_write_data_packet(cmd_buffer, va, 1,
501 &cmd_buffer->state.trace_id);
502
503 radeon_check_space(cmd_buffer->device->ws, cs, 2);
504
505 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
506 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
507 }
508
509 static void
510 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
511 enum radv_cmd_flush_bits flags)
512 {
513 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
514 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
515 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
516
517 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
518
519 /* Force wait for graphics or compute engines to be idle. */
520 si_cs_emit_cache_flush(cmd_buffer->cs,
521 cmd_buffer->device->physical_device->rad_info.chip_class,
522 &cmd_buffer->gfx9_fence_idx,
523 cmd_buffer->gfx9_fence_va,
524 radv_cmd_buffer_uses_mec(cmd_buffer),
525 flags, cmd_buffer->gfx9_eop_bug_va);
526 }
527
528 if (unlikely(cmd_buffer->device->trace_bo))
529 radv_cmd_buffer_trace_emit(cmd_buffer);
530 }
531
532 static void
533 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
534 struct radv_pipeline *pipeline, enum ring_type ring)
535 {
536 struct radv_device *device = cmd_buffer->device;
537 uint32_t data[2];
538 uint64_t va;
539
540 va = radv_buffer_get_va(device->trace_bo);
541
542 switch (ring) {
543 case RING_GFX:
544 va += 8;
545 break;
546 case RING_COMPUTE:
547 va += 16;
548 break;
549 default:
550 assert(!"invalid ring type");
551 }
552
553 data[0] = (uintptr_t)pipeline;
554 data[1] = (uintptr_t)pipeline >> 32;
555
556 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
557 }
558
559 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
560 VkPipelineBindPoint bind_point,
561 struct radv_descriptor_set *set,
562 unsigned idx)
563 {
564 struct radv_descriptor_state *descriptors_state =
565 radv_get_descriptors_state(cmd_buffer, bind_point);
566
567 descriptors_state->sets[idx] = set;
568
569 descriptors_state->valid |= (1u << idx); /* active descriptors */
570 descriptors_state->dirty |= (1u << idx);
571 }
572
573 static void
574 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
575 VkPipelineBindPoint bind_point)
576 {
577 struct radv_descriptor_state *descriptors_state =
578 radv_get_descriptors_state(cmd_buffer, bind_point);
579 struct radv_device *device = cmd_buffer->device;
580 uint32_t data[MAX_SETS * 2] = {};
581 uint64_t va;
582 unsigned i;
583 va = radv_buffer_get_va(device->trace_bo) + 24;
584
585 for_each_bit(i, descriptors_state->valid) {
586 struct radv_descriptor_set *set = descriptors_state->sets[i];
587 data[i * 2] = (uint64_t)(uintptr_t)set;
588 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
589 }
590
591 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
592 }
593
594 struct radv_userdata_info *
595 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
596 gl_shader_stage stage,
597 int idx)
598 {
599 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
600 return &shader->info.user_sgprs_locs.shader_data[idx];
601 }
602
603 static void
604 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
605 struct radv_pipeline *pipeline,
606 gl_shader_stage stage,
607 int idx, uint64_t va)
608 {
609 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
610 uint32_t base_reg = pipeline->user_data_0[stage];
611 if (loc->sgpr_idx == -1)
612 return;
613
614 assert(loc->num_sgprs == 1);
615
616 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
617 base_reg + loc->sgpr_idx * 4, va, false);
618 }
619
620 static void
621 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
622 struct radv_pipeline *pipeline,
623 struct radv_descriptor_state *descriptors_state,
624 gl_shader_stage stage)
625 {
626 struct radv_device *device = cmd_buffer->device;
627 struct radeon_cmdbuf *cs = cmd_buffer->cs;
628 uint32_t sh_base = pipeline->user_data_0[stage];
629 struct radv_userdata_locations *locs =
630 &pipeline->shaders[stage]->info.user_sgprs_locs;
631 unsigned mask = locs->descriptor_sets_enabled;
632
633 mask &= descriptors_state->dirty & descriptors_state->valid;
634
635 while (mask) {
636 int start, count;
637
638 u_bit_scan_consecutive_range(&mask, &start, &count);
639
640 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
641 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
642
643 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
644 for (int i = 0; i < count; i++) {
645 struct radv_descriptor_set *set =
646 descriptors_state->sets[start + i];
647
648 radv_emit_shader_pointer_body(device, cs, set->va, true);
649 }
650 }
651 }
652
653 /**
654 * Convert the user sample locations to hardware sample locations (the values
655 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
656 */
657 static void
658 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
659 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
660 {
661 uint32_t x_offset = x % state->grid_size.width;
662 uint32_t y_offset = y % state->grid_size.height;
663 uint32_t num_samples = (uint32_t)state->per_pixel;
664 VkSampleLocationEXT *user_locs;
665 uint32_t pixel_offset;
666
667 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
668
669 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
670 user_locs = &state->locations[pixel_offset];
671
672 for (uint32_t i = 0; i < num_samples; i++) {
673 float shifted_pos_x = user_locs[i].x - 0.5;
674 float shifted_pos_y = user_locs[i].y - 0.5;
675
676 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
677 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
678
679 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
680 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
681 }
682 }
683
684 /**
685 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
686 * locations.
687 */
688 static void
689 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
690 uint32_t *sample_locs_pixel)
691 {
692 for (uint32_t i = 0; i < num_samples; i++) {
693 uint32_t sample_reg_idx = i / 4;
694 uint32_t sample_loc_idx = i % 4;
695 int32_t pos_x = sample_locs[i].x;
696 int32_t pos_y = sample_locs[i].y;
697
698 uint32_t shift_x = 8 * sample_loc_idx;
699 uint32_t shift_y = shift_x + 4;
700
701 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
702 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
703 }
704 }
705
706 /**
707 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
708 * sample locations.
709 */
710 static uint64_t
711 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
712 VkOffset2D *sample_locs,
713 uint32_t num_samples)
714 {
715 uint32_t centroid_priorities[num_samples];
716 uint32_t sample_mask = num_samples - 1;
717 uint32_t distances[num_samples];
718 uint64_t centroid_priority = 0;
719
720 /* Compute the distances from center for each sample. */
721 for (int i = 0; i < num_samples; i++) {
722 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
723 (sample_locs[i].y * sample_locs[i].y);
724 }
725
726 /* Compute the centroid priorities by looking at the distances array. */
727 for (int i = 0; i < num_samples; i++) {
728 uint32_t min_idx = 0;
729
730 for (int j = 1; j < num_samples; j++) {
731 if (distances[j] < distances[min_idx])
732 min_idx = j;
733 }
734
735 centroid_priorities[i] = min_idx;
736 distances[min_idx] = 0xffffffff;
737 }
738
739 /* Compute the final centroid priority. */
740 for (int i = 0; i < 8; i++) {
741 centroid_priority |=
742 centroid_priorities[i & sample_mask] << (i * 4);
743 }
744
745 return centroid_priority << 32 | centroid_priority;
746 }
747
748 /**
749 * Emit the sample locations that are specified with VK_EXT_sample_locations.
750 */
751 static void
752 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
753 {
754 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
755 struct radv_multisample_state *ms = &pipeline->graphics.ms;
756 struct radv_sample_locations_state *sample_location =
757 &cmd_buffer->state.dynamic.sample_location;
758 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
759 struct radeon_cmdbuf *cs = cmd_buffer->cs;
760 uint32_t sample_locs_pixel[4][2] = {};
761 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
762 uint32_t max_sample_dist = 0;
763 uint64_t centroid_priority;
764
765 if (!cmd_buffer->state.dynamic.sample_location.count)
766 return;
767
768 /* Convert the user sample locations to hardware sample locations. */
769 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
770 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
771 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
772 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
773
774 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
775 for (uint32_t i = 0; i < 4; i++) {
776 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
777 sample_locs_pixel[i]);
778 }
779
780 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
781 centroid_priority =
782 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
783 num_samples);
784
785 /* Compute the maximum sample distance from the specified locations. */
786 for (uint32_t i = 0; i < num_samples; i++) {
787 VkOffset2D offset = sample_locs[0][i];
788 max_sample_dist = MAX2(max_sample_dist,
789 MAX2(abs(offset.x), abs(offset.y)));
790 }
791
792 /* Emit the specified user sample locations. */
793 switch (num_samples) {
794 case 2:
795 case 4:
796 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
797 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
798 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
799 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
800 break;
801 case 8:
802 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
803 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
804 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
805 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
806 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
807 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
808 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
809 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
810 break;
811 default:
812 unreachable("invalid number of samples");
813 }
814
815 /* Emit the maximum sample distance and the centroid priority. */
816 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
817
818 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
819 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
820
821 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
822 radeon_emit(cs, pa_sc_aa_config);
823
824 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
825 radeon_emit(cs, centroid_priority);
826 radeon_emit(cs, centroid_priority >> 32);
827
828 /* GFX9: Flush DFSM when the AA mode changes. */
829 if (cmd_buffer->device->dfsm_allowed) {
830 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
831 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
832 }
833
834 cmd_buffer->state.context_roll_without_scissor_emitted = true;
835 }
836
837 static void
838 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
839 struct radv_pipeline *pipeline,
840 gl_shader_stage stage,
841 int idx, int count, uint32_t *values)
842 {
843 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
844 uint32_t base_reg = pipeline->user_data_0[stage];
845 if (loc->sgpr_idx == -1)
846 return;
847
848 assert(loc->num_sgprs == count);
849
850 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
851 radeon_emit_array(cmd_buffer->cs, values, count);
852 }
853
854 static void
855 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
856 struct radv_pipeline *pipeline)
857 {
858 int num_samples = pipeline->graphics.ms.num_samples;
859 struct radv_multisample_state *ms = &pipeline->graphics.ms;
860 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
861
862 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
863 cmd_buffer->sample_positions_needed = true;
864
865 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
866 return;
867
868 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
869 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
870 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
871
872 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
873
874 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
875
876 /* GFX9: Flush DFSM when the AA mode changes. */
877 if (cmd_buffer->device->dfsm_allowed) {
878 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
879 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
880 }
881
882 cmd_buffer->state.context_roll_without_scissor_emitted = true;
883 }
884
885 static void
886 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
887 struct radv_shader_variant *shader)
888 {
889 uint64_t va;
890
891 if (!shader)
892 return;
893
894 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
895
896 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
897 }
898
899 static void
900 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
901 struct radv_pipeline *pipeline,
902 bool vertex_stage_only)
903 {
904 struct radv_cmd_state *state = &cmd_buffer->state;
905 uint32_t mask = state->prefetch_L2_mask;
906
907 if (vertex_stage_only) {
908 /* Fast prefetch path for starting draws as soon as possible.
909 */
910 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
911 RADV_PREFETCH_VBO_DESCRIPTORS);
912 }
913
914 if (mask & RADV_PREFETCH_VS)
915 radv_emit_shader_prefetch(cmd_buffer,
916 pipeline->shaders[MESA_SHADER_VERTEX]);
917
918 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
919 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
920
921 if (mask & RADV_PREFETCH_TCS)
922 radv_emit_shader_prefetch(cmd_buffer,
923 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
924
925 if (mask & RADV_PREFETCH_TES)
926 radv_emit_shader_prefetch(cmd_buffer,
927 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
928
929 if (mask & RADV_PREFETCH_GS) {
930 radv_emit_shader_prefetch(cmd_buffer,
931 pipeline->shaders[MESA_SHADER_GEOMETRY]);
932 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
933 }
934
935 if (mask & RADV_PREFETCH_PS)
936 radv_emit_shader_prefetch(cmd_buffer,
937 pipeline->shaders[MESA_SHADER_FRAGMENT]);
938
939 state->prefetch_L2_mask &= ~mask;
940 }
941
942 static void
943 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
944 {
945 if (!cmd_buffer->device->physical_device->rbplus_allowed)
946 return;
947
948 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
949 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
950 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
951
952 unsigned sx_ps_downconvert = 0;
953 unsigned sx_blend_opt_epsilon = 0;
954 unsigned sx_blend_opt_control = 0;
955
956 for (unsigned i = 0; i < subpass->color_count; ++i) {
957 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
958 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
959 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
960 continue;
961 }
962
963 int idx = subpass->color_attachments[i].attachment;
964 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
965
966 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
967 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
968 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
969 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
970
971 bool has_alpha, has_rgb;
972
973 /* Set if RGB and A are present. */
974 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
975
976 if (format == V_028C70_COLOR_8 ||
977 format == V_028C70_COLOR_16 ||
978 format == V_028C70_COLOR_32)
979 has_rgb = !has_alpha;
980 else
981 has_rgb = true;
982
983 /* Check the colormask and export format. */
984 if (!(colormask & 0x7))
985 has_rgb = false;
986 if (!(colormask & 0x8))
987 has_alpha = false;
988
989 if (spi_format == V_028714_SPI_SHADER_ZERO) {
990 has_rgb = false;
991 has_alpha = false;
992 }
993
994 /* Disable value checking for disabled channels. */
995 if (!has_rgb)
996 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
997 if (!has_alpha)
998 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
999
1000 /* Enable down-conversion for 32bpp and smaller formats. */
1001 switch (format) {
1002 case V_028C70_COLOR_8:
1003 case V_028C70_COLOR_8_8:
1004 case V_028C70_COLOR_8_8_8_8:
1005 /* For 1 and 2-channel formats, use the superset thereof. */
1006 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1007 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1008 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1009 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1010 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1011 }
1012 break;
1013
1014 case V_028C70_COLOR_5_6_5:
1015 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1016 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1017 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1018 }
1019 break;
1020
1021 case V_028C70_COLOR_1_5_5_5:
1022 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1023 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1024 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1025 }
1026 break;
1027
1028 case V_028C70_COLOR_4_4_4_4:
1029 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1030 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1031 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1032 }
1033 break;
1034
1035 case V_028C70_COLOR_32:
1036 if (swap == V_028C70_SWAP_STD &&
1037 spi_format == V_028714_SPI_SHADER_32_R)
1038 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1039 else if (swap == V_028C70_SWAP_ALT_REV &&
1040 spi_format == V_028714_SPI_SHADER_32_AR)
1041 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1042 break;
1043
1044 case V_028C70_COLOR_16:
1045 case V_028C70_COLOR_16_16:
1046 /* For 1-channel formats, use the superset thereof. */
1047 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1048 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1049 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1050 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1051 if (swap == V_028C70_SWAP_STD ||
1052 swap == V_028C70_SWAP_STD_REV)
1053 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1054 else
1055 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1056 }
1057 break;
1058
1059 case V_028C70_COLOR_10_11_11:
1060 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1061 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1062 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1063 }
1064 break;
1065
1066 case V_028C70_COLOR_2_10_10_10:
1067 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1068 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1069 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1070 }
1071 break;
1072 }
1073 }
1074
1075 for (unsigned i = subpass->color_count; i < 8; ++i) {
1076 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1077 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1078 }
1079 /* TODO: avoid redundantly setting context registers */
1080 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1081 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1082 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1083 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1084
1085 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1086 }
1087
1088 static void
1089 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1090 {
1091 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1092
1093 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1094 return;
1095
1096 radv_update_multisample_state(cmd_buffer, pipeline);
1097
1098 cmd_buffer->scratch_size_needed =
1099 MAX2(cmd_buffer->scratch_size_needed,
1100 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1101
1102 if (!cmd_buffer->state.emitted_pipeline ||
1103 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1104 pipeline->graphics.can_use_guardband)
1105 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1106
1107 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1108
1109 if (!cmd_buffer->state.emitted_pipeline ||
1110 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1111 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1112 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1113 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1114 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1115 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1116 }
1117
1118 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1119 if (!pipeline->shaders[i])
1120 continue;
1121
1122 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1123 pipeline->shaders[i]->bo);
1124 }
1125
1126 if (radv_pipeline_has_gs(pipeline))
1127 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1128 pipeline->gs_copy_shader->bo);
1129
1130 if (unlikely(cmd_buffer->device->trace_bo))
1131 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1132
1133 cmd_buffer->state.emitted_pipeline = pipeline;
1134
1135 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1136 }
1137
1138 static void
1139 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1140 {
1141 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1142 cmd_buffer->state.dynamic.viewport.viewports);
1143 }
1144
1145 static void
1146 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1147 {
1148 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1149
1150 si_write_scissors(cmd_buffer->cs, 0, count,
1151 cmd_buffer->state.dynamic.scissor.scissors,
1152 cmd_buffer->state.dynamic.viewport.viewports,
1153 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1154
1155 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1156 }
1157
1158 static void
1159 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1160 {
1161 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1162 return;
1163
1164 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1165 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1166 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1167 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1168 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1169 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1170 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1171 }
1172 }
1173
1174 static void
1175 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1176 {
1177 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1178
1179 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1180 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1181 }
1182
1183 static void
1184 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1185 {
1186 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1187
1188 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1189 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1190 }
1191
1192 static void
1193 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1194 {
1195 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1196
1197 radeon_set_context_reg_seq(cmd_buffer->cs,
1198 R_028430_DB_STENCILREFMASK, 2);
1199 radeon_emit(cmd_buffer->cs,
1200 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1201 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1202 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1203 S_028430_STENCILOPVAL(1));
1204 radeon_emit(cmd_buffer->cs,
1205 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1206 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1207 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1208 S_028434_STENCILOPVAL_BF(1));
1209 }
1210
1211 static void
1212 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1213 {
1214 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1215
1216 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1217 fui(d->depth_bounds.min));
1218 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1219 fui(d->depth_bounds.max));
1220 }
1221
1222 static void
1223 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1224 {
1225 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1226 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1227 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1228
1229
1230 radeon_set_context_reg_seq(cmd_buffer->cs,
1231 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1232 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1233 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1234 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1235 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1236 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1237 }
1238
1239 static void
1240 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1241 int index,
1242 struct radv_attachment_info *att,
1243 struct radv_image_view *iview,
1244 VkImageLayout layout)
1245 {
1246 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1247 struct radv_color_buffer_info *cb = &att->cb;
1248 uint32_t cb_color_info = cb->cb_color_info;
1249 struct radv_image *image = iview->image;
1250
1251 if (!radv_layout_dcc_compressed(image, layout,
1252 radv_image_queue_family_mask(image,
1253 cmd_buffer->queue_family_index,
1254 cmd_buffer->queue_family_index))) {
1255 cb_color_info &= C_028C70_DCC_ENABLE;
1256 }
1257
1258 if (radv_image_is_tc_compat_cmask(image) &&
1259 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1260 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1261 /* If this bit is set, the FMASK decompression operation
1262 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1263 */
1264 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1265 }
1266
1267 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1268 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1269 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1270 radeon_emit(cmd_buffer->cs, 0);
1271 radeon_emit(cmd_buffer->cs, 0);
1272 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1273 radeon_emit(cmd_buffer->cs, cb_color_info);
1274 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1275 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1276 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1277 radeon_emit(cmd_buffer->cs, 0);
1278 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1279 radeon_emit(cmd_buffer->cs, 0);
1280
1281 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1282 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1283
1284 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1285 cb->cb_color_base >> 32);
1286 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1287 cb->cb_color_cmask >> 32);
1288 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1289 cb->cb_color_fmask >> 32);
1290 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1291 cb->cb_dcc_base >> 32);
1292 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1293 cb->cb_color_attrib2);
1294 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1295 cb->cb_color_attrib3);
1296 } else if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1297 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1298 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1299 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1300 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1301 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1302 radeon_emit(cmd_buffer->cs, cb_color_info);
1303 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1304 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1305 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1306 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1307 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1308 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1309
1310 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1311 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1312 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1313
1314 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1315 cb->cb_mrt_epitch);
1316 } else {
1317 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1318 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1319 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1320 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1321 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1322 radeon_emit(cmd_buffer->cs, cb_color_info);
1323 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1324 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1325 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1326 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1327 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1328 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1329
1330 if (is_vi) { /* DCC BASE */
1331 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1332 }
1333 }
1334
1335 if (radv_dcc_enabled(image, iview->base_mip)) {
1336 /* Drawing with DCC enabled also compresses colorbuffers. */
1337 VkImageSubresourceRange range = {
1338 .aspectMask = iview->aspect_mask,
1339 .baseMipLevel = iview->base_mip,
1340 .levelCount = iview->level_count,
1341 .baseArrayLayer = iview->base_layer,
1342 .layerCount = iview->layer_count,
1343 };
1344
1345 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1346 }
1347 }
1348
1349 static void
1350 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1351 struct radv_ds_buffer_info *ds,
1352 struct radv_image *image, VkImageLayout layout,
1353 bool requires_cond_exec)
1354 {
1355 uint32_t db_z_info = ds->db_z_info;
1356 uint32_t db_z_info_reg;
1357
1358 if (!radv_image_is_tc_compat_htile(image))
1359 return;
1360
1361 if (!radv_layout_has_htile(image, layout,
1362 radv_image_queue_family_mask(image,
1363 cmd_buffer->queue_family_index,
1364 cmd_buffer->queue_family_index))) {
1365 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1366 }
1367
1368 db_z_info &= C_028040_ZRANGE_PRECISION;
1369
1370 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1371 db_z_info_reg = R_028038_DB_Z_INFO;
1372 } else {
1373 db_z_info_reg = R_028040_DB_Z_INFO;
1374 }
1375
1376 /* When we don't know the last fast clear value we need to emit a
1377 * conditional packet that will eventually skip the following
1378 * SET_CONTEXT_REG packet.
1379 */
1380 if (requires_cond_exec) {
1381 uint64_t va = radv_buffer_get_va(image->bo);
1382 va += image->offset + image->tc_compat_zrange_offset;
1383
1384 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1385 radeon_emit(cmd_buffer->cs, va);
1386 radeon_emit(cmd_buffer->cs, va >> 32);
1387 radeon_emit(cmd_buffer->cs, 0);
1388 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1389 }
1390
1391 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1392 }
1393
1394 static void
1395 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1396 struct radv_ds_buffer_info *ds,
1397 struct radv_image *image,
1398 VkImageLayout layout)
1399 {
1400 uint32_t db_z_info = ds->db_z_info;
1401 uint32_t db_stencil_info = ds->db_stencil_info;
1402
1403 if (!radv_layout_has_htile(image, layout,
1404 radv_image_queue_family_mask(image,
1405 cmd_buffer->queue_family_index,
1406 cmd_buffer->queue_family_index))) {
1407 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1408 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1409 }
1410
1411 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1412 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1413
1414 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1415 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1416 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1417
1418 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1419 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1420 radeon_emit(cmd_buffer->cs, db_z_info);
1421 radeon_emit(cmd_buffer->cs, db_stencil_info);
1422 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1423 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1424 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1425 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1426
1427 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1428 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1429 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1430 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1431 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1432 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1433 } else if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1434 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1435 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1436 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1437 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1438
1439 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1440 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1441 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1442 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1443 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1444 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1445 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1446 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1447 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1448 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1449 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1450
1451 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1452 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1453 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1454 } else {
1455 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1456
1457 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1458 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1459 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1460 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1461 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1462 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1463 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1464 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1465 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1466 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1467
1468 }
1469
1470 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1471 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1472
1473 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1474 ds->pa_su_poly_offset_db_fmt_cntl);
1475 }
1476
1477 /**
1478 * Update the fast clear depth/stencil values if the image is bound as a
1479 * depth/stencil buffer.
1480 */
1481 static void
1482 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1483 struct radv_image *image,
1484 VkClearDepthStencilValue ds_clear_value,
1485 VkImageAspectFlags aspects)
1486 {
1487 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1488 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1489 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1490 struct radv_attachment_info *att;
1491 uint32_t att_idx;
1492
1493 if (!framebuffer || !subpass)
1494 return;
1495
1496 if (!subpass->depth_stencil_attachment)
1497 return;
1498
1499 att_idx = subpass->depth_stencil_attachment->attachment;
1500 att = &framebuffer->attachments[att_idx];
1501 if (att->attachment->image != image)
1502 return;
1503
1504 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1505 radeon_emit(cs, ds_clear_value.stencil);
1506 radeon_emit(cs, fui(ds_clear_value.depth));
1507
1508 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1509 * only needed when clearing Z to 0.0.
1510 */
1511 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1512 ds_clear_value.depth == 0.0) {
1513 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1514
1515 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1516 layout, false);
1517 }
1518
1519 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1520 }
1521
1522 /**
1523 * Set the clear depth/stencil values to the image's metadata.
1524 */
1525 static void
1526 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1527 struct radv_image *image,
1528 VkClearDepthStencilValue ds_clear_value,
1529 VkImageAspectFlags aspects)
1530 {
1531 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1532 uint64_t va = radv_buffer_get_va(image->bo);
1533 unsigned reg_offset = 0, reg_count = 0;
1534
1535 va += image->offset + image->clear_value_offset;
1536
1537 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1538 ++reg_count;
1539 } else {
1540 ++reg_offset;
1541 va += 4;
1542 }
1543 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1544 ++reg_count;
1545
1546 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
1547 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1548 S_370_WR_CONFIRM(1) |
1549 S_370_ENGINE_SEL(V_370_PFP));
1550 radeon_emit(cs, va);
1551 radeon_emit(cs, va >> 32);
1552 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1553 radeon_emit(cs, ds_clear_value.stencil);
1554 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1555 radeon_emit(cs, fui(ds_clear_value.depth));
1556 }
1557
1558 /**
1559 * Update the TC-compat metadata value for this image.
1560 */
1561 static void
1562 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1563 struct radv_image *image,
1564 uint32_t value)
1565 {
1566 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1567 uint64_t va = radv_buffer_get_va(image->bo);
1568 va += image->offset + image->tc_compat_zrange_offset;
1569
1570 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1571 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1572 S_370_WR_CONFIRM(1) |
1573 S_370_ENGINE_SEL(V_370_PFP));
1574 radeon_emit(cs, va);
1575 radeon_emit(cs, va >> 32);
1576 radeon_emit(cs, value);
1577 }
1578
1579 static void
1580 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1581 struct radv_image *image,
1582 VkClearDepthStencilValue ds_clear_value)
1583 {
1584 uint32_t cond_val;
1585
1586 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1587 * depth clear value is 0.0f.
1588 */
1589 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1590
1591 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1592 }
1593
1594 /**
1595 * Update the clear depth/stencil values for this image.
1596 */
1597 void
1598 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1599 struct radv_image *image,
1600 VkClearDepthStencilValue ds_clear_value,
1601 VkImageAspectFlags aspects)
1602 {
1603 assert(radv_image_has_htile(image));
1604
1605 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1606
1607 if (radv_image_is_tc_compat_htile(image) &&
1608 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1609 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1610 ds_clear_value);
1611 }
1612
1613 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1614 aspects);
1615 }
1616
1617 /**
1618 * Load the clear depth/stencil values from the image's metadata.
1619 */
1620 static void
1621 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1622 struct radv_image *image)
1623 {
1624 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1625 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1626 uint64_t va = radv_buffer_get_va(image->bo);
1627 unsigned reg_offset = 0, reg_count = 0;
1628
1629 va += image->offset + image->clear_value_offset;
1630
1631 if (!radv_image_has_htile(image))
1632 return;
1633
1634 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1635 ++reg_count;
1636 } else {
1637 ++reg_offset;
1638 va += 4;
1639 }
1640 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1641 ++reg_count;
1642
1643 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1644
1645 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1646 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1647 radeon_emit(cs, va);
1648 radeon_emit(cs, va >> 32);
1649 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1650 radeon_emit(cs, reg_count);
1651 } else {
1652 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1653 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1654 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1655 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1656 radeon_emit(cs, va);
1657 radeon_emit(cs, va >> 32);
1658 radeon_emit(cs, reg >> 2);
1659 radeon_emit(cs, 0);
1660
1661 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1662 radeon_emit(cs, 0);
1663 }
1664 }
1665
1666 /*
1667 * With DCC some colors don't require CMASK elimination before being
1668 * used as a texture. This sets a predicate value to determine if the
1669 * cmask eliminate is required.
1670 */
1671 void
1672 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1673 struct radv_image *image,
1674 const VkImageSubresourceRange *range, bool value)
1675 {
1676 uint64_t pred_val = value;
1677 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1678 uint32_t level_count = radv_get_levelCount(image, range);
1679 uint32_t count = 2 * level_count;
1680
1681 assert(radv_dcc_enabled(image, range->baseMipLevel));
1682
1683 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1684 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1685 S_370_WR_CONFIRM(1) |
1686 S_370_ENGINE_SEL(V_370_PFP));
1687 radeon_emit(cmd_buffer->cs, va);
1688 radeon_emit(cmd_buffer->cs, va >> 32);
1689
1690 for (uint32_t l = 0; l < level_count; l++) {
1691 radeon_emit(cmd_buffer->cs, pred_val);
1692 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1693 }
1694 }
1695
1696 /**
1697 * Update the DCC predicate to reflect the compression state.
1698 */
1699 void
1700 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1701 struct radv_image *image,
1702 const VkImageSubresourceRange *range, bool value)
1703 {
1704 uint64_t pred_val = value;
1705 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1706 uint32_t level_count = radv_get_levelCount(image, range);
1707 uint32_t count = 2 * level_count;
1708
1709 assert(radv_dcc_enabled(image, range->baseMipLevel));
1710
1711 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1712 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1713 S_370_WR_CONFIRM(1) |
1714 S_370_ENGINE_SEL(V_370_PFP));
1715 radeon_emit(cmd_buffer->cs, va);
1716 radeon_emit(cmd_buffer->cs, va >> 32);
1717
1718 for (uint32_t l = 0; l < level_count; l++) {
1719 radeon_emit(cmd_buffer->cs, pred_val);
1720 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1721 }
1722 }
1723
1724 /**
1725 * Update the fast clear color values if the image is bound as a color buffer.
1726 */
1727 static void
1728 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1729 struct radv_image *image,
1730 int cb_idx,
1731 uint32_t color_values[2])
1732 {
1733 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1734 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1735 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1736 struct radv_attachment_info *att;
1737 uint32_t att_idx;
1738
1739 if (!framebuffer || !subpass)
1740 return;
1741
1742 att_idx = subpass->color_attachments[cb_idx].attachment;
1743 if (att_idx == VK_ATTACHMENT_UNUSED)
1744 return;
1745
1746 att = &framebuffer->attachments[att_idx];
1747 if (att->attachment->image != image)
1748 return;
1749
1750 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1751 radeon_emit(cs, color_values[0]);
1752 radeon_emit(cs, color_values[1]);
1753
1754 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1755 }
1756
1757 /**
1758 * Set the clear color values to the image's metadata.
1759 */
1760 static void
1761 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1762 struct radv_image *image,
1763 const VkImageSubresourceRange *range,
1764 uint32_t color_values[2])
1765 {
1766 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1767 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1768 uint32_t level_count = radv_get_levelCount(image, range);
1769 uint32_t count = 2 * level_count;
1770
1771 assert(radv_image_has_cmask(image) ||
1772 radv_dcc_enabled(image, range->baseMipLevel));
1773
1774 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1775 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1776 S_370_WR_CONFIRM(1) |
1777 S_370_ENGINE_SEL(V_370_PFP));
1778 radeon_emit(cs, va);
1779 radeon_emit(cs, va >> 32);
1780
1781 for (uint32_t l = 0; l < level_count; l++) {
1782 radeon_emit(cs, color_values[0]);
1783 radeon_emit(cs, color_values[1]);
1784 }
1785 }
1786
1787 /**
1788 * Update the clear color values for this image.
1789 */
1790 void
1791 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1792 const struct radv_image_view *iview,
1793 int cb_idx,
1794 uint32_t color_values[2])
1795 {
1796 struct radv_image *image = iview->image;
1797 VkImageSubresourceRange range = {
1798 .aspectMask = iview->aspect_mask,
1799 .baseMipLevel = iview->base_mip,
1800 .levelCount = iview->level_count,
1801 .baseArrayLayer = iview->base_layer,
1802 .layerCount = iview->layer_count,
1803 };
1804
1805 assert(radv_image_has_cmask(image) ||
1806 radv_dcc_enabled(image, iview->base_mip));
1807
1808 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1809
1810 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1811 color_values);
1812 }
1813
1814 /**
1815 * Load the clear color values from the image's metadata.
1816 */
1817 static void
1818 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1819 struct radv_image_view *iview,
1820 int cb_idx)
1821 {
1822 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1823 struct radv_image *image = iview->image;
1824 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1825
1826 if (!radv_image_has_cmask(image) &&
1827 !radv_dcc_enabled(image, iview->base_mip))
1828 return;
1829
1830 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1831
1832 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1833 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1834 radeon_emit(cs, va);
1835 radeon_emit(cs, va >> 32);
1836 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1837 radeon_emit(cs, 2);
1838 } else {
1839 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1840 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1841 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1842 COPY_DATA_COUNT_SEL);
1843 radeon_emit(cs, va);
1844 radeon_emit(cs, va >> 32);
1845 radeon_emit(cs, reg >> 2);
1846 radeon_emit(cs, 0);
1847
1848 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1849 radeon_emit(cs, 0);
1850 }
1851 }
1852
1853 static void
1854 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1855 {
1856 int i;
1857 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1858 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1859 unsigned num_bpp64_colorbufs = 0;
1860
1861 /* this may happen for inherited secondary recording */
1862 if (!framebuffer)
1863 return;
1864
1865 for (i = 0; i < 8; ++i) {
1866 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1867 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1868 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1869 continue;
1870 }
1871
1872 int idx = subpass->color_attachments[i].attachment;
1873 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1874 struct radv_image_view *iview = att->attachment;
1875 struct radv_image *image = iview->image;
1876 VkImageLayout layout = subpass->color_attachments[i].layout;
1877
1878 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1879
1880 assert(att->attachment->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1881 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1882 radv_emit_fb_color_state(cmd_buffer, i, att, iview, layout);
1883
1884 radv_load_color_clear_metadata(cmd_buffer, iview, i);
1885
1886 if (image->planes[0].surface.bpe >= 8)
1887 num_bpp64_colorbufs++;
1888 }
1889
1890 if (subpass->depth_stencil_attachment) {
1891 int idx = subpass->depth_stencil_attachment->attachment;
1892 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1893 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1894 struct radv_image *image = att->attachment->image;
1895 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1896 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1897 cmd_buffer->queue_family_index,
1898 cmd_buffer->queue_family_index);
1899 /* We currently don't support writing decompressed HTILE */
1900 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1901 radv_layout_is_htile_compressed(image, layout, queue_mask));
1902
1903 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1904
1905 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1906 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1907 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1908 }
1909 radv_load_ds_clear_metadata(cmd_buffer, image);
1910 } else {
1911 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1912 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1913 else
1914 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1915
1916 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1917 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1918 }
1919 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1920 S_028208_BR_X(framebuffer->width) |
1921 S_028208_BR_Y(framebuffer->height));
1922
1923 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
1924 bool disable_constant_encode =
1925 cmd_buffer->device->physical_device->has_dcc_constant_encode;
1926 uint8_t watermark = 4; /* Default value for GFX8. */
1927
1928 /* For optimal DCC performance. */
1929 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1930 if (num_bpp64_colorbufs >= 5) {
1931 watermark = 8;
1932 } else {
1933 watermark = 6;
1934 }
1935 }
1936
1937 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1938 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1939 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
1940 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
1941 }
1942
1943 if (cmd_buffer->device->dfsm_allowed) {
1944 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1945 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1946 }
1947
1948 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1949 }
1950
1951 static void
1952 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1953 {
1954 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1955 struct radv_cmd_state *state = &cmd_buffer->state;
1956
1957 if (state->index_type != state->last_index_type) {
1958 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1959 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1960 2, state->index_type);
1961 } else {
1962 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1963 radeon_emit(cs, state->index_type);
1964 }
1965
1966 state->last_index_type = state->index_type;
1967 }
1968
1969 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1970 radeon_emit(cs, state->index_va);
1971 radeon_emit(cs, state->index_va >> 32);
1972
1973 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1974 radeon_emit(cs, state->max_index_count);
1975
1976 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1977 }
1978
1979 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1980 {
1981 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1982 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1983 uint32_t pa_sc_mode_cntl_1 =
1984 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1985 uint32_t db_count_control;
1986
1987 if(!cmd_buffer->state.active_occlusion_queries) {
1988 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1989 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1990 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1991 has_perfect_queries) {
1992 /* Re-enable out-of-order rasterization if the
1993 * bound pipeline supports it and if it's has
1994 * been disabled before starting any perfect
1995 * occlusion queries.
1996 */
1997 radeon_set_context_reg(cmd_buffer->cs,
1998 R_028A4C_PA_SC_MODE_CNTL_1,
1999 pa_sc_mode_cntl_1);
2000 }
2001 }
2002 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2003 } else {
2004 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2005 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2006
2007 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2008 db_count_control =
2009 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2010 S_028004_SAMPLE_RATE(sample_rate) |
2011 S_028004_ZPASS_ENABLE(1) |
2012 S_028004_SLICE_EVEN_ENABLE(1) |
2013 S_028004_SLICE_ODD_ENABLE(1);
2014
2015 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2016 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2017 has_perfect_queries) {
2018 /* If the bound pipeline has enabled
2019 * out-of-order rasterization, we should
2020 * disable it before starting any perfect
2021 * occlusion queries.
2022 */
2023 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2024
2025 radeon_set_context_reg(cmd_buffer->cs,
2026 R_028A4C_PA_SC_MODE_CNTL_1,
2027 pa_sc_mode_cntl_1);
2028 }
2029 } else {
2030 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2031 S_028004_SAMPLE_RATE(sample_rate);
2032 }
2033 }
2034
2035 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2036
2037 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2038 }
2039
2040 static void
2041 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2042 {
2043 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2044
2045 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2046 radv_emit_viewport(cmd_buffer);
2047
2048 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2049 !cmd_buffer->device->physical_device->has_scissor_bug)
2050 radv_emit_scissor(cmd_buffer);
2051
2052 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2053 radv_emit_line_width(cmd_buffer);
2054
2055 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2056 radv_emit_blend_constants(cmd_buffer);
2057
2058 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2059 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2060 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2061 radv_emit_stencil(cmd_buffer);
2062
2063 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2064 radv_emit_depth_bounds(cmd_buffer);
2065
2066 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2067 radv_emit_depth_bias(cmd_buffer);
2068
2069 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2070 radv_emit_discard_rectangle(cmd_buffer);
2071
2072 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2073 radv_emit_sample_locations(cmd_buffer);
2074
2075 cmd_buffer->state.dirty &= ~states;
2076 }
2077
2078 static void
2079 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2080 VkPipelineBindPoint bind_point)
2081 {
2082 struct radv_descriptor_state *descriptors_state =
2083 radv_get_descriptors_state(cmd_buffer, bind_point);
2084 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2085 unsigned bo_offset;
2086
2087 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2088 set->mapped_ptr,
2089 &bo_offset))
2090 return;
2091
2092 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2093 set->va += bo_offset;
2094 }
2095
2096 static void
2097 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2098 VkPipelineBindPoint bind_point)
2099 {
2100 struct radv_descriptor_state *descriptors_state =
2101 radv_get_descriptors_state(cmd_buffer, bind_point);
2102 uint32_t size = MAX_SETS * 4;
2103 uint32_t offset;
2104 void *ptr;
2105
2106 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2107 256, &offset, &ptr))
2108 return;
2109
2110 for (unsigned i = 0; i < MAX_SETS; i++) {
2111 uint32_t *uptr = ((uint32_t *)ptr) + i;
2112 uint64_t set_va = 0;
2113 struct radv_descriptor_set *set = descriptors_state->sets[i];
2114 if (descriptors_state->valid & (1u << i))
2115 set_va = set->va;
2116 uptr[0] = set_va & 0xffffffff;
2117 }
2118
2119 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2120 va += offset;
2121
2122 if (cmd_buffer->state.pipeline) {
2123 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2124 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2125 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2126
2127 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2128 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2129 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2130
2131 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2132 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2133 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2134
2135 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2136 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2137 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2138
2139 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2140 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2141 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2142 }
2143
2144 if (cmd_buffer->state.compute_pipeline)
2145 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2146 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2147 }
2148
2149 static void
2150 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2151 VkShaderStageFlags stages)
2152 {
2153 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2154 VK_PIPELINE_BIND_POINT_COMPUTE :
2155 VK_PIPELINE_BIND_POINT_GRAPHICS;
2156 struct radv_descriptor_state *descriptors_state =
2157 radv_get_descriptors_state(cmd_buffer, bind_point);
2158 struct radv_cmd_state *state = &cmd_buffer->state;
2159 bool flush_indirect_descriptors;
2160
2161 if (!descriptors_state->dirty)
2162 return;
2163
2164 if (descriptors_state->push_dirty)
2165 radv_flush_push_descriptors(cmd_buffer, bind_point);
2166
2167 flush_indirect_descriptors =
2168 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2169 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2170 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2171 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2172
2173 if (flush_indirect_descriptors)
2174 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2175
2176 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2177 cmd_buffer->cs,
2178 MAX_SETS * MESA_SHADER_STAGES * 4);
2179
2180 if (cmd_buffer->state.pipeline) {
2181 radv_foreach_stage(stage, stages) {
2182 if (!cmd_buffer->state.pipeline->shaders[stage])
2183 continue;
2184
2185 radv_emit_descriptor_pointers(cmd_buffer,
2186 cmd_buffer->state.pipeline,
2187 descriptors_state, stage);
2188 }
2189 }
2190
2191 if (cmd_buffer->state.compute_pipeline &&
2192 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2193 radv_emit_descriptor_pointers(cmd_buffer,
2194 cmd_buffer->state.compute_pipeline,
2195 descriptors_state,
2196 MESA_SHADER_COMPUTE);
2197 }
2198
2199 descriptors_state->dirty = 0;
2200 descriptors_state->push_dirty = false;
2201
2202 assert(cmd_buffer->cs->cdw <= cdw_max);
2203
2204 if (unlikely(cmd_buffer->device->trace_bo))
2205 radv_save_descriptors(cmd_buffer, bind_point);
2206 }
2207
2208 static void
2209 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2210 VkShaderStageFlags stages)
2211 {
2212 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2213 ? cmd_buffer->state.compute_pipeline
2214 : cmd_buffer->state.pipeline;
2215 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2216 VK_PIPELINE_BIND_POINT_COMPUTE :
2217 VK_PIPELINE_BIND_POINT_GRAPHICS;
2218 struct radv_descriptor_state *descriptors_state =
2219 radv_get_descriptors_state(cmd_buffer, bind_point);
2220 struct radv_pipeline_layout *layout = pipeline->layout;
2221 struct radv_shader_variant *shader, *prev_shader;
2222 bool need_push_constants = false;
2223 unsigned offset;
2224 void *ptr;
2225 uint64_t va;
2226
2227 stages &= cmd_buffer->push_constant_stages;
2228 if (!stages ||
2229 (!layout->push_constant_size && !layout->dynamic_offset_count))
2230 return;
2231
2232 radv_foreach_stage(stage, stages) {
2233 if (!pipeline->shaders[stage])
2234 continue;
2235
2236 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
2237 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
2238
2239 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
2240 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
2241
2242 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2243 AC_UD_INLINE_PUSH_CONSTANTS,
2244 count,
2245 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2246 }
2247
2248 if (need_push_constants) {
2249 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2250 16 * layout->dynamic_offset_count,
2251 256, &offset, &ptr))
2252 return;
2253
2254 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2255 memcpy((char*)ptr + layout->push_constant_size,
2256 descriptors_state->dynamic_buffers,
2257 16 * layout->dynamic_offset_count);
2258
2259 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2260 va += offset;
2261
2262 MAYBE_UNUSED unsigned cdw_max =
2263 radeon_check_space(cmd_buffer->device->ws,
2264 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2265
2266 prev_shader = NULL;
2267 radv_foreach_stage(stage, stages) {
2268 shader = radv_get_shader(pipeline, stage);
2269
2270 /* Avoid redundantly emitting the address for merged stages. */
2271 if (shader && shader != prev_shader) {
2272 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2273 AC_UD_PUSH_CONSTANTS, va);
2274
2275 prev_shader = shader;
2276 }
2277 }
2278 assert(cmd_buffer->cs->cdw <= cdw_max);
2279 }
2280
2281 cmd_buffer->push_constant_stages &= ~stages;
2282 }
2283
2284 static void
2285 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2286 bool pipeline_is_dirty)
2287 {
2288 if ((pipeline_is_dirty ||
2289 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2290 cmd_buffer->state.pipeline->num_vertex_bindings &&
2291 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
2292 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
2293 unsigned vb_offset;
2294 void *vb_ptr;
2295 uint32_t i = 0;
2296 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2297 uint64_t va;
2298
2299 /* allocate some descriptor state for vertex buffers */
2300 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2301 &vb_offset, &vb_ptr))
2302 return;
2303
2304 for (i = 0; i < count; i++) {
2305 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2306 uint32_t offset;
2307 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2308 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2309
2310 if (!buffer)
2311 continue;
2312
2313 va = radv_buffer_get_va(buffer->bo);
2314
2315 offset = cmd_buffer->vertex_bindings[i].offset;
2316 va += offset + buffer->offset;
2317 desc[0] = va;
2318 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2319 if (cmd_buffer->device->physical_device->rad_info.chip_class <= GFX7 && stride)
2320 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2321 else
2322 desc[2] = buffer->size - offset;
2323 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2324 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2325 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2326 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2327 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2328 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2329 }
2330
2331 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2332 va += vb_offset;
2333
2334 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2335 AC_UD_VS_VERTEX_BUFFERS, va);
2336
2337 cmd_buffer->state.vb_va = va;
2338 cmd_buffer->state.vb_size = count * 16;
2339 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2340 }
2341 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2342 }
2343
2344 static void
2345 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2346 {
2347 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2348 struct radv_userdata_info *loc;
2349 uint32_t base_reg;
2350
2351 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2352 if (!radv_get_shader(pipeline, stage))
2353 continue;
2354
2355 loc = radv_lookup_user_sgpr(pipeline, stage,
2356 AC_UD_STREAMOUT_BUFFERS);
2357 if (loc->sgpr_idx == -1)
2358 continue;
2359
2360 base_reg = pipeline->user_data_0[stage];
2361
2362 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2363 base_reg + loc->sgpr_idx * 4, va, false);
2364 }
2365
2366 if (pipeline->gs_copy_shader) {
2367 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2368 if (loc->sgpr_idx != -1) {
2369 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2370
2371 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2372 base_reg + loc->sgpr_idx * 4, va, false);
2373 }
2374 }
2375 }
2376
2377 static void
2378 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2379 {
2380 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2381 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2382 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2383 unsigned so_offset;
2384 void *so_ptr;
2385 uint64_t va;
2386
2387 /* Allocate some descriptor state for streamout buffers. */
2388 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2389 MAX_SO_BUFFERS * 16, 256,
2390 &so_offset, &so_ptr))
2391 return;
2392
2393 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2394 struct radv_buffer *buffer = sb[i].buffer;
2395 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2396
2397 if (!(so->enabled_mask & (1 << i)))
2398 continue;
2399
2400 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2401
2402 va += sb[i].offset;
2403
2404 /* Set the descriptor.
2405 *
2406 * On GFX8, the format must be non-INVALID, otherwise
2407 * the buffer will be considered not bound and store
2408 * instructions will be no-ops.
2409 */
2410 desc[0] = va;
2411 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2412 desc[2] = 0xffffffff;
2413 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2414 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2415 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2416 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2417 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2418 }
2419
2420 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2421 va += so_offset;
2422
2423 radv_emit_streamout_buffers(cmd_buffer, va);
2424 }
2425
2426 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2427 }
2428
2429 static void
2430 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2431 {
2432 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2433 radv_flush_streamout_descriptors(cmd_buffer);
2434 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2435 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2436 }
2437
2438 struct radv_draw_info {
2439 /**
2440 * Number of vertices.
2441 */
2442 uint32_t count;
2443
2444 /**
2445 * Index of the first vertex.
2446 */
2447 int32_t vertex_offset;
2448
2449 /**
2450 * First instance id.
2451 */
2452 uint32_t first_instance;
2453
2454 /**
2455 * Number of instances.
2456 */
2457 uint32_t instance_count;
2458
2459 /**
2460 * First index (indexed draws only).
2461 */
2462 uint32_t first_index;
2463
2464 /**
2465 * Whether it's an indexed draw.
2466 */
2467 bool indexed;
2468
2469 /**
2470 * Indirect draw parameters resource.
2471 */
2472 struct radv_buffer *indirect;
2473 uint64_t indirect_offset;
2474 uint32_t stride;
2475
2476 /**
2477 * Draw count parameters resource.
2478 */
2479 struct radv_buffer *count_buffer;
2480 uint64_t count_buffer_offset;
2481
2482 /**
2483 * Stream output parameters resource.
2484 */
2485 struct radv_buffer *strmout_buffer;
2486 uint64_t strmout_buffer_offset;
2487 };
2488
2489 static void
2490 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2491 bool instanced_draw, bool indirect_draw,
2492 bool count_from_stream_output,
2493 uint32_t draw_vertex_count)
2494 {
2495 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2496 struct radv_cmd_state *state = &cmd_buffer->state;
2497 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2498 unsigned ia_multi_vgt_param;
2499
2500 ia_multi_vgt_param =
2501 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2502 indirect_draw,
2503 count_from_stream_output,
2504 draw_vertex_count);
2505
2506 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2507 if (info->chip_class >= GFX9) {
2508 radeon_set_uconfig_reg_idx(cs,
2509 R_030960_IA_MULTI_VGT_PARAM,
2510 4, ia_multi_vgt_param);
2511 } else if (info->chip_class >= GFX7) {
2512 radeon_set_context_reg_idx(cs,
2513 R_028AA8_IA_MULTI_VGT_PARAM,
2514 1, ia_multi_vgt_param);
2515 } else {
2516 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2517 ia_multi_vgt_param);
2518 }
2519 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2520 }
2521 }
2522
2523 static void
2524 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2525 const struct radv_draw_info *draw_info)
2526 {
2527 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2528 struct radv_cmd_state *state = &cmd_buffer->state;
2529 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2530 int32_t primitive_reset_en;
2531
2532 /* Draw state. */
2533 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2534 draw_info->indirect,
2535 !!draw_info->strmout_buffer,
2536 draw_info->indirect ? 0 : draw_info->count);
2537
2538 /* Primitive restart. */
2539 primitive_reset_en =
2540 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2541
2542 if (primitive_reset_en != state->last_primitive_reset_en) {
2543 state->last_primitive_reset_en = primitive_reset_en;
2544 if (info->chip_class >= GFX9) {
2545 radeon_set_uconfig_reg(cs,
2546 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2547 primitive_reset_en);
2548 } else {
2549 radeon_set_context_reg(cs,
2550 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2551 primitive_reset_en);
2552 }
2553 }
2554
2555 if (primitive_reset_en) {
2556 uint32_t primitive_reset_index =
2557 state->index_type ? 0xffffffffu : 0xffffu;
2558
2559 if (primitive_reset_index != state->last_primitive_reset_index) {
2560 radeon_set_context_reg(cs,
2561 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2562 primitive_reset_index);
2563 state->last_primitive_reset_index = primitive_reset_index;
2564 }
2565 }
2566
2567 if (draw_info->strmout_buffer) {
2568 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2569
2570 va += draw_info->strmout_buffer->offset +
2571 draw_info->strmout_buffer_offset;
2572
2573 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2574 draw_info->stride);
2575
2576 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2577 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2578 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2579 COPY_DATA_WR_CONFIRM);
2580 radeon_emit(cs, va);
2581 radeon_emit(cs, va >> 32);
2582 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2583 radeon_emit(cs, 0); /* unused */
2584
2585 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2586 }
2587 }
2588
2589 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2590 VkPipelineStageFlags src_stage_mask)
2591 {
2592 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2593 VK_PIPELINE_STAGE_TRANSFER_BIT |
2594 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2595 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2596 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2597 }
2598
2599 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2600 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2601 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2602 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2603 VK_PIPELINE_STAGE_TRANSFER_BIT |
2604 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2605 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2606 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2607 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2608 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2609 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2610 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2611 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2612 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2613 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2614 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2615 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2616 }
2617 }
2618
2619 static enum radv_cmd_flush_bits
2620 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2621 VkAccessFlags src_flags,
2622 struct radv_image *image)
2623 {
2624 bool flush_CB_meta = true, flush_DB_meta = true;
2625 enum radv_cmd_flush_bits flush_bits = 0;
2626 uint32_t b;
2627
2628 if (image) {
2629 if (!radv_image_has_CB_metadata(image))
2630 flush_CB_meta = false;
2631 if (!radv_image_has_htile(image))
2632 flush_DB_meta = false;
2633 }
2634
2635 for_each_bit(b, src_flags) {
2636 switch ((VkAccessFlagBits)(1 << b)) {
2637 case VK_ACCESS_SHADER_WRITE_BIT:
2638 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2639 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2640 flush_bits |= RADV_CMD_FLAG_WB_L2;
2641 break;
2642 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2643 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2644 if (flush_CB_meta)
2645 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2646 break;
2647 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2648 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2649 if (flush_DB_meta)
2650 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2651 break;
2652 case VK_ACCESS_TRANSFER_WRITE_BIT:
2653 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2654 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2655 RADV_CMD_FLAG_INV_L2;
2656
2657 if (flush_CB_meta)
2658 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2659 if (flush_DB_meta)
2660 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2661 break;
2662 default:
2663 break;
2664 }
2665 }
2666 return flush_bits;
2667 }
2668
2669 static enum radv_cmd_flush_bits
2670 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2671 VkAccessFlags dst_flags,
2672 struct radv_image *image)
2673 {
2674 bool flush_CB_meta = true, flush_DB_meta = true;
2675 enum radv_cmd_flush_bits flush_bits = 0;
2676 bool flush_CB = true, flush_DB = true;
2677 bool image_is_coherent = false;
2678 uint32_t b;
2679
2680 if (image) {
2681 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2682 flush_CB = false;
2683 flush_DB = false;
2684 }
2685
2686 if (!radv_image_has_CB_metadata(image))
2687 flush_CB_meta = false;
2688 if (!radv_image_has_htile(image))
2689 flush_DB_meta = false;
2690
2691 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2692 if (image->info.samples == 1 &&
2693 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2694 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2695 !vk_format_is_stencil(image->vk_format)) {
2696 /* Single-sample color and single-sample depth
2697 * (not stencil) are coherent with shaders on
2698 * GFX9.
2699 */
2700 image_is_coherent = true;
2701 }
2702 }
2703 }
2704
2705 for_each_bit(b, dst_flags) {
2706 switch ((VkAccessFlagBits)(1 << b)) {
2707 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2708 case VK_ACCESS_INDEX_READ_BIT:
2709 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2710 break;
2711 case VK_ACCESS_UNIFORM_READ_BIT:
2712 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2713 break;
2714 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2715 case VK_ACCESS_TRANSFER_READ_BIT:
2716 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2717 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2718 RADV_CMD_FLAG_INV_L2;
2719 break;
2720 case VK_ACCESS_SHADER_READ_BIT:
2721 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2722
2723 if (!image_is_coherent)
2724 flush_bits |= RADV_CMD_FLAG_INV_L2;
2725 break;
2726 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2727 if (flush_CB)
2728 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2729 if (flush_CB_meta)
2730 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2731 break;
2732 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2733 if (flush_DB)
2734 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2735 if (flush_DB_meta)
2736 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2737 break;
2738 default:
2739 break;
2740 }
2741 }
2742 return flush_bits;
2743 }
2744
2745 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2746 const struct radv_subpass_barrier *barrier)
2747 {
2748 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2749 NULL);
2750 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2751 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2752 NULL);
2753 }
2754
2755 uint32_t
2756 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2757 {
2758 struct radv_cmd_state *state = &cmd_buffer->state;
2759 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2760
2761 /* The id of this subpass shouldn't exceed the number of subpasses in
2762 * this render pass minus 1.
2763 */
2764 assert(subpass_id < state->pass->subpass_count);
2765 return subpass_id;
2766 }
2767
2768 static struct radv_sample_locations_state *
2769 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2770 uint32_t att_idx,
2771 bool begin_subpass)
2772 {
2773 struct radv_cmd_state *state = &cmd_buffer->state;
2774 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2775 struct radv_image_view *view = state->framebuffer->attachments[att_idx].attachment;
2776
2777 if (view->image->info.samples == 1)
2778 return NULL;
2779
2780 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2781 /* Return the initial sample locations if this is the initial
2782 * layout transition of the given subpass attachemnt.
2783 */
2784 if (state->attachments[att_idx].sample_location.count > 0)
2785 return &state->attachments[att_idx].sample_location;
2786 } else {
2787 /* Otherwise return the subpass sample locations if defined. */
2788 if (state->subpass_sample_locs) {
2789 /* Because the driver sets the current subpass before
2790 * initial layout transitions, we should use the sample
2791 * locations from the previous subpass to avoid an
2792 * off-by-one problem. Otherwise, use the sample
2793 * locations for the current subpass for final layout
2794 * transitions.
2795 */
2796 if (begin_subpass)
2797 subpass_id--;
2798
2799 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2800 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2801 return &state->subpass_sample_locs[i].sample_location;
2802 }
2803 }
2804 }
2805
2806 return NULL;
2807 }
2808
2809 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2810 struct radv_subpass_attachment att,
2811 bool begin_subpass)
2812 {
2813 unsigned idx = att.attachment;
2814 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2815 struct radv_sample_locations_state *sample_locs;
2816 VkImageSubresourceRange range;
2817 range.aspectMask = 0;
2818 range.baseMipLevel = view->base_mip;
2819 range.levelCount = 1;
2820 range.baseArrayLayer = view->base_layer;
2821 range.layerCount = cmd_buffer->state.framebuffer->layers;
2822
2823 if (cmd_buffer->state.subpass->view_mask) {
2824 /* If the current subpass uses multiview, the driver might have
2825 * performed a fast color/depth clear to the whole image
2826 * (including all layers). To make sure the driver will
2827 * decompress the image correctly (if needed), we have to
2828 * account for the "real" number of layers. If the view mask is
2829 * sparse, this will decompress more layers than needed.
2830 */
2831 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2832 }
2833
2834 /* Get the subpass sample locations for the given attachment, if NULL
2835 * is returned the driver will use the default HW locations.
2836 */
2837 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2838 begin_subpass);
2839
2840 radv_handle_image_transition(cmd_buffer,
2841 view->image,
2842 cmd_buffer->state.attachments[idx].current_layout,
2843 att.layout, 0, 0, &range, sample_locs);
2844
2845 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2846
2847
2848 }
2849
2850 void
2851 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2852 const struct radv_subpass *subpass)
2853 {
2854 cmd_buffer->state.subpass = subpass;
2855
2856 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2857 }
2858
2859 static VkResult
2860 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2861 struct radv_render_pass *pass,
2862 const VkRenderPassBeginInfo *info)
2863 {
2864 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
2865 vk_find_struct_const(info->pNext,
2866 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
2867 struct radv_cmd_state *state = &cmd_buffer->state;
2868 struct radv_framebuffer *framebuffer = state->framebuffer;
2869
2870 if (!sample_locs) {
2871 state->subpass_sample_locs = NULL;
2872 return VK_SUCCESS;
2873 }
2874
2875 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
2876 const VkAttachmentSampleLocationsEXT *att_sample_locs =
2877 &sample_locs->pAttachmentInitialSampleLocations[i];
2878 uint32_t att_idx = att_sample_locs->attachmentIndex;
2879 struct radv_attachment_info *att = &framebuffer->attachments[att_idx];
2880 struct radv_image *image = att->attachment->image;
2881
2882 assert(vk_format_is_depth_or_stencil(image->vk_format));
2883
2884 /* From the Vulkan spec 1.1.108:
2885 *
2886 * "If the image referenced by the framebuffer attachment at
2887 * index attachmentIndex was not created with
2888 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
2889 * then the values specified in sampleLocationsInfo are
2890 * ignored."
2891 */
2892 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
2893 continue;
2894
2895 const VkSampleLocationsInfoEXT *sample_locs_info =
2896 &att_sample_locs->sampleLocationsInfo;
2897
2898 state->attachments[att_idx].sample_location.per_pixel =
2899 sample_locs_info->sampleLocationsPerPixel;
2900 state->attachments[att_idx].sample_location.grid_size =
2901 sample_locs_info->sampleLocationGridSize;
2902 state->attachments[att_idx].sample_location.count =
2903 sample_locs_info->sampleLocationsCount;
2904 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
2905 sample_locs_info->pSampleLocations,
2906 sample_locs_info->sampleLocationsCount);
2907 }
2908
2909 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
2910 sample_locs->postSubpassSampleLocationsCount *
2911 sizeof(state->subpass_sample_locs[0]),
2912 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2913 if (state->subpass_sample_locs == NULL) {
2914 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2915 return cmd_buffer->record_result;
2916 }
2917
2918 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
2919
2920 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
2921 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
2922 &sample_locs->pPostSubpassSampleLocations[i];
2923 const VkSampleLocationsInfoEXT *sample_locs_info =
2924 &subpass_sample_locs_info->sampleLocationsInfo;
2925
2926 state->subpass_sample_locs[i].subpass_idx =
2927 subpass_sample_locs_info->subpassIndex;
2928 state->subpass_sample_locs[i].sample_location.per_pixel =
2929 sample_locs_info->sampleLocationsPerPixel;
2930 state->subpass_sample_locs[i].sample_location.grid_size =
2931 sample_locs_info->sampleLocationGridSize;
2932 state->subpass_sample_locs[i].sample_location.count =
2933 sample_locs_info->sampleLocationsCount;
2934 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
2935 sample_locs_info->pSampleLocations,
2936 sample_locs_info->sampleLocationsCount);
2937 }
2938
2939 return VK_SUCCESS;
2940 }
2941
2942 static VkResult
2943 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2944 struct radv_render_pass *pass,
2945 const VkRenderPassBeginInfo *info)
2946 {
2947 struct radv_cmd_state *state = &cmd_buffer->state;
2948
2949 if (pass->attachment_count == 0) {
2950 state->attachments = NULL;
2951 return VK_SUCCESS;
2952 }
2953
2954 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2955 pass->attachment_count *
2956 sizeof(state->attachments[0]),
2957 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2958 if (state->attachments == NULL) {
2959 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2960 return cmd_buffer->record_result;
2961 }
2962
2963 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2964 struct radv_render_pass_attachment *att = &pass->attachments[i];
2965 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2966 VkImageAspectFlags clear_aspects = 0;
2967
2968 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2969 /* color attachment */
2970 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2971 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2972 }
2973 } else {
2974 /* depthstencil attachment */
2975 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2976 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2977 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2978 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2979 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2980 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2981 }
2982 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2983 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2984 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2985 }
2986 }
2987
2988 state->attachments[i].pending_clear_aspects = clear_aspects;
2989 state->attachments[i].cleared_views = 0;
2990 if (clear_aspects && info) {
2991 assert(info->clearValueCount > i);
2992 state->attachments[i].clear_value = info->pClearValues[i];
2993 }
2994
2995 state->attachments[i].current_layout = att->initial_layout;
2996 state->attachments[i].sample_location.count = 0;
2997 }
2998
2999 return VK_SUCCESS;
3000 }
3001
3002 VkResult radv_AllocateCommandBuffers(
3003 VkDevice _device,
3004 const VkCommandBufferAllocateInfo *pAllocateInfo,
3005 VkCommandBuffer *pCommandBuffers)
3006 {
3007 RADV_FROM_HANDLE(radv_device, device, _device);
3008 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3009
3010 VkResult result = VK_SUCCESS;
3011 uint32_t i;
3012
3013 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3014
3015 if (!list_empty(&pool->free_cmd_buffers)) {
3016 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3017
3018 list_del(&cmd_buffer->pool_link);
3019 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3020
3021 result = radv_reset_cmd_buffer(cmd_buffer);
3022 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3023 cmd_buffer->level = pAllocateInfo->level;
3024
3025 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3026 } else {
3027 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3028 &pCommandBuffers[i]);
3029 }
3030 if (result != VK_SUCCESS)
3031 break;
3032 }
3033
3034 if (result != VK_SUCCESS) {
3035 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3036 i, pCommandBuffers);
3037
3038 /* From the Vulkan 1.0.66 spec:
3039 *
3040 * "vkAllocateCommandBuffers can be used to create multiple
3041 * command buffers. If the creation of any of those command
3042 * buffers fails, the implementation must destroy all
3043 * successfully created command buffer objects from this
3044 * command, set all entries of the pCommandBuffers array to
3045 * NULL and return the error."
3046 */
3047 memset(pCommandBuffers, 0,
3048 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3049 }
3050
3051 return result;
3052 }
3053
3054 void radv_FreeCommandBuffers(
3055 VkDevice device,
3056 VkCommandPool commandPool,
3057 uint32_t commandBufferCount,
3058 const VkCommandBuffer *pCommandBuffers)
3059 {
3060 for (uint32_t i = 0; i < commandBufferCount; i++) {
3061 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3062
3063 if (cmd_buffer) {
3064 if (cmd_buffer->pool) {
3065 list_del(&cmd_buffer->pool_link);
3066 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3067 } else
3068 radv_cmd_buffer_destroy(cmd_buffer);
3069
3070 }
3071 }
3072 }
3073
3074 VkResult radv_ResetCommandBuffer(
3075 VkCommandBuffer commandBuffer,
3076 VkCommandBufferResetFlags flags)
3077 {
3078 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3079 return radv_reset_cmd_buffer(cmd_buffer);
3080 }
3081
3082 VkResult radv_BeginCommandBuffer(
3083 VkCommandBuffer commandBuffer,
3084 const VkCommandBufferBeginInfo *pBeginInfo)
3085 {
3086 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3087 VkResult result = VK_SUCCESS;
3088
3089 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3090 /* If the command buffer has already been resetted with
3091 * vkResetCommandBuffer, no need to do it again.
3092 */
3093 result = radv_reset_cmd_buffer(cmd_buffer);
3094 if (result != VK_SUCCESS)
3095 return result;
3096 }
3097
3098 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3099 cmd_buffer->state.last_primitive_reset_en = -1;
3100 cmd_buffer->state.last_index_type = -1;
3101 cmd_buffer->state.last_num_instances = -1;
3102 cmd_buffer->state.last_vertex_offset = -1;
3103 cmd_buffer->state.last_first_instance = -1;
3104 cmd_buffer->state.predication_type = -1;
3105 cmd_buffer->usage_flags = pBeginInfo->flags;
3106
3107 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3108 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3109 assert(pBeginInfo->pInheritanceInfo);
3110 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3111 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3112
3113 struct radv_subpass *subpass =
3114 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3115
3116 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3117 if (result != VK_SUCCESS)
3118 return result;
3119
3120 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3121 }
3122
3123 if (unlikely(cmd_buffer->device->trace_bo)) {
3124 struct radv_device *device = cmd_buffer->device;
3125
3126 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3127 device->trace_bo);
3128
3129 radv_cmd_buffer_trace_emit(cmd_buffer);
3130 }
3131
3132 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3133
3134 return result;
3135 }
3136
3137 void radv_CmdBindVertexBuffers(
3138 VkCommandBuffer commandBuffer,
3139 uint32_t firstBinding,
3140 uint32_t bindingCount,
3141 const VkBuffer* pBuffers,
3142 const VkDeviceSize* pOffsets)
3143 {
3144 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3145 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3146 bool changed = false;
3147
3148 /* We have to defer setting up vertex buffer since we need the buffer
3149 * stride from the pipeline. */
3150
3151 assert(firstBinding + bindingCount <= MAX_VBS);
3152 for (uint32_t i = 0; i < bindingCount; i++) {
3153 uint32_t idx = firstBinding + i;
3154
3155 if (!changed &&
3156 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3157 vb[idx].offset != pOffsets[i])) {
3158 changed = true;
3159 }
3160
3161 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3162 vb[idx].offset = pOffsets[i];
3163
3164 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3165 vb[idx].buffer->bo);
3166 }
3167
3168 if (!changed) {
3169 /* No state changes. */
3170 return;
3171 }
3172
3173 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3174 }
3175
3176 void radv_CmdBindIndexBuffer(
3177 VkCommandBuffer commandBuffer,
3178 VkBuffer buffer,
3179 VkDeviceSize offset,
3180 VkIndexType indexType)
3181 {
3182 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3183 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3184
3185 if (cmd_buffer->state.index_buffer == index_buffer &&
3186 cmd_buffer->state.index_offset == offset &&
3187 cmd_buffer->state.index_type == indexType) {
3188 /* No state changes. */
3189 return;
3190 }
3191
3192 cmd_buffer->state.index_buffer = index_buffer;
3193 cmd_buffer->state.index_offset = offset;
3194 cmd_buffer->state.index_type = indexType; /* vk matches hw */
3195 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3196 cmd_buffer->state.index_va += index_buffer->offset + offset;
3197
3198 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
3199 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
3200 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3201 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3202 }
3203
3204
3205 static void
3206 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3207 VkPipelineBindPoint bind_point,
3208 struct radv_descriptor_set *set, unsigned idx)
3209 {
3210 struct radeon_winsys *ws = cmd_buffer->device->ws;
3211
3212 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3213
3214 assert(set);
3215 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3216
3217 if (!cmd_buffer->device->use_global_bo_list) {
3218 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3219 if (set->descriptors[j])
3220 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3221 }
3222
3223 if(set->bo)
3224 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3225 }
3226
3227 void radv_CmdBindDescriptorSets(
3228 VkCommandBuffer commandBuffer,
3229 VkPipelineBindPoint pipelineBindPoint,
3230 VkPipelineLayout _layout,
3231 uint32_t firstSet,
3232 uint32_t descriptorSetCount,
3233 const VkDescriptorSet* pDescriptorSets,
3234 uint32_t dynamicOffsetCount,
3235 const uint32_t* pDynamicOffsets)
3236 {
3237 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3238 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3239 unsigned dyn_idx = 0;
3240
3241 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3242 struct radv_descriptor_state *descriptors_state =
3243 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3244
3245 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3246 unsigned idx = i + firstSet;
3247 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3248 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3249
3250 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3251 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3252 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3253 assert(dyn_idx < dynamicOffsetCount);
3254
3255 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3256 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3257 dst[0] = va;
3258 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3259 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3260 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3261 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3262 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3263 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3264 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3265 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3266 cmd_buffer->push_constant_stages |=
3267 set->layout->dynamic_shader_stages;
3268 }
3269 }
3270 }
3271
3272 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3273 struct radv_descriptor_set *set,
3274 struct radv_descriptor_set_layout *layout,
3275 VkPipelineBindPoint bind_point)
3276 {
3277 struct radv_descriptor_state *descriptors_state =
3278 radv_get_descriptors_state(cmd_buffer, bind_point);
3279 set->size = layout->size;
3280 set->layout = layout;
3281
3282 if (descriptors_state->push_set.capacity < set->size) {
3283 size_t new_size = MAX2(set->size, 1024);
3284 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3285 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3286
3287 free(set->mapped_ptr);
3288 set->mapped_ptr = malloc(new_size);
3289
3290 if (!set->mapped_ptr) {
3291 descriptors_state->push_set.capacity = 0;
3292 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3293 return false;
3294 }
3295
3296 descriptors_state->push_set.capacity = new_size;
3297 }
3298
3299 return true;
3300 }
3301
3302 void radv_meta_push_descriptor_set(
3303 struct radv_cmd_buffer* cmd_buffer,
3304 VkPipelineBindPoint pipelineBindPoint,
3305 VkPipelineLayout _layout,
3306 uint32_t set,
3307 uint32_t descriptorWriteCount,
3308 const VkWriteDescriptorSet* pDescriptorWrites)
3309 {
3310 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3311 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3312 unsigned bo_offset;
3313
3314 assert(set == 0);
3315 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3316
3317 push_set->size = layout->set[set].layout->size;
3318 push_set->layout = layout->set[set].layout;
3319
3320 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3321 &bo_offset,
3322 (void**) &push_set->mapped_ptr))
3323 return;
3324
3325 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3326 push_set->va += bo_offset;
3327
3328 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3329 radv_descriptor_set_to_handle(push_set),
3330 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3331
3332 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3333 }
3334
3335 void radv_CmdPushDescriptorSetKHR(
3336 VkCommandBuffer commandBuffer,
3337 VkPipelineBindPoint pipelineBindPoint,
3338 VkPipelineLayout _layout,
3339 uint32_t set,
3340 uint32_t descriptorWriteCount,
3341 const VkWriteDescriptorSet* pDescriptorWrites)
3342 {
3343 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3344 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3345 struct radv_descriptor_state *descriptors_state =
3346 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3347 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3348
3349 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3350
3351 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3352 layout->set[set].layout,
3353 pipelineBindPoint))
3354 return;
3355
3356 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3357 * because it is invalid, according to Vulkan spec.
3358 */
3359 for (int i = 0; i < descriptorWriteCount; i++) {
3360 MAYBE_UNUSED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3361 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3362 }
3363
3364 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3365 radv_descriptor_set_to_handle(push_set),
3366 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3367
3368 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3369 descriptors_state->push_dirty = true;
3370 }
3371
3372 void radv_CmdPushDescriptorSetWithTemplateKHR(
3373 VkCommandBuffer commandBuffer,
3374 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3375 VkPipelineLayout _layout,
3376 uint32_t set,
3377 const void* pData)
3378 {
3379 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3380 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3381 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3382 struct radv_descriptor_state *descriptors_state =
3383 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3384 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3385
3386 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3387
3388 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3389 layout->set[set].layout,
3390 templ->bind_point))
3391 return;
3392
3393 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3394 descriptorUpdateTemplate, pData);
3395
3396 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3397 descriptors_state->push_dirty = true;
3398 }
3399
3400 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3401 VkPipelineLayout layout,
3402 VkShaderStageFlags stageFlags,
3403 uint32_t offset,
3404 uint32_t size,
3405 const void* pValues)
3406 {
3407 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3408 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3409 cmd_buffer->push_constant_stages |= stageFlags;
3410 }
3411
3412 VkResult radv_EndCommandBuffer(
3413 VkCommandBuffer commandBuffer)
3414 {
3415 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3416
3417 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3418 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3419 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3420
3421 /* Make sure to sync all pending active queries at the end of
3422 * command buffer.
3423 */
3424 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3425
3426 si_emit_cache_flush(cmd_buffer);
3427 }
3428
3429 /* Make sure CP DMA is idle at the end of IBs because the kernel
3430 * doesn't wait for it.
3431 */
3432 si_cp_dma_wait_for_idle(cmd_buffer);
3433
3434 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3435 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3436
3437 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3438 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3439
3440 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3441
3442 return cmd_buffer->record_result;
3443 }
3444
3445 static void
3446 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3447 {
3448 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3449
3450 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3451 return;
3452
3453 assert(!pipeline->ctx_cs.cdw);
3454
3455 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3456
3457 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3458 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3459
3460 cmd_buffer->compute_scratch_size_needed =
3461 MAX2(cmd_buffer->compute_scratch_size_needed,
3462 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
3463
3464 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3465 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3466
3467 if (unlikely(cmd_buffer->device->trace_bo))
3468 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3469 }
3470
3471 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3472 VkPipelineBindPoint bind_point)
3473 {
3474 struct radv_descriptor_state *descriptors_state =
3475 radv_get_descriptors_state(cmd_buffer, bind_point);
3476
3477 descriptors_state->dirty |= descriptors_state->valid;
3478 }
3479
3480 void radv_CmdBindPipeline(
3481 VkCommandBuffer commandBuffer,
3482 VkPipelineBindPoint pipelineBindPoint,
3483 VkPipeline _pipeline)
3484 {
3485 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3486 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3487
3488 switch (pipelineBindPoint) {
3489 case VK_PIPELINE_BIND_POINT_COMPUTE:
3490 if (cmd_buffer->state.compute_pipeline == pipeline)
3491 return;
3492 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3493
3494 cmd_buffer->state.compute_pipeline = pipeline;
3495 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3496 break;
3497 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3498 if (cmd_buffer->state.pipeline == pipeline)
3499 return;
3500 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3501
3502 cmd_buffer->state.pipeline = pipeline;
3503 if (!pipeline)
3504 break;
3505
3506 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3507 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3508
3509 /* the new vertex shader might not have the same user regs */
3510 cmd_buffer->state.last_first_instance = -1;
3511 cmd_buffer->state.last_vertex_offset = -1;
3512
3513 /* Prefetch all pipeline shaders at first draw time. */
3514 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3515
3516 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3517 radv_bind_streamout_state(cmd_buffer, pipeline);
3518
3519 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3520 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3521 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3522 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3523
3524 if (radv_pipeline_has_tess(pipeline))
3525 cmd_buffer->tess_rings_needed = true;
3526 break;
3527 default:
3528 assert(!"invalid bind point");
3529 break;
3530 }
3531 }
3532
3533 void radv_CmdSetViewport(
3534 VkCommandBuffer commandBuffer,
3535 uint32_t firstViewport,
3536 uint32_t viewportCount,
3537 const VkViewport* pViewports)
3538 {
3539 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3540 struct radv_cmd_state *state = &cmd_buffer->state;
3541 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3542
3543 assert(firstViewport < MAX_VIEWPORTS);
3544 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3545
3546 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3547 pViewports, viewportCount * sizeof(*pViewports))) {
3548 return;
3549 }
3550
3551 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3552 viewportCount * sizeof(*pViewports));
3553
3554 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3555 }
3556
3557 void radv_CmdSetScissor(
3558 VkCommandBuffer commandBuffer,
3559 uint32_t firstScissor,
3560 uint32_t scissorCount,
3561 const VkRect2D* pScissors)
3562 {
3563 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3564 struct radv_cmd_state *state = &cmd_buffer->state;
3565 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3566
3567 assert(firstScissor < MAX_SCISSORS);
3568 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3569
3570 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3571 scissorCount * sizeof(*pScissors))) {
3572 return;
3573 }
3574
3575 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3576 scissorCount * sizeof(*pScissors));
3577
3578 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3579 }
3580
3581 void radv_CmdSetLineWidth(
3582 VkCommandBuffer commandBuffer,
3583 float lineWidth)
3584 {
3585 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3586
3587 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3588 return;
3589
3590 cmd_buffer->state.dynamic.line_width = lineWidth;
3591 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3592 }
3593
3594 void radv_CmdSetDepthBias(
3595 VkCommandBuffer commandBuffer,
3596 float depthBiasConstantFactor,
3597 float depthBiasClamp,
3598 float depthBiasSlopeFactor)
3599 {
3600 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3601 struct radv_cmd_state *state = &cmd_buffer->state;
3602
3603 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3604 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3605 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3606 return;
3607 }
3608
3609 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3610 state->dynamic.depth_bias.clamp = depthBiasClamp;
3611 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3612
3613 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3614 }
3615
3616 void radv_CmdSetBlendConstants(
3617 VkCommandBuffer commandBuffer,
3618 const float blendConstants[4])
3619 {
3620 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3621 struct radv_cmd_state *state = &cmd_buffer->state;
3622
3623 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3624 return;
3625
3626 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3627
3628 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3629 }
3630
3631 void radv_CmdSetDepthBounds(
3632 VkCommandBuffer commandBuffer,
3633 float minDepthBounds,
3634 float maxDepthBounds)
3635 {
3636 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3637 struct radv_cmd_state *state = &cmd_buffer->state;
3638
3639 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3640 state->dynamic.depth_bounds.max == maxDepthBounds) {
3641 return;
3642 }
3643
3644 state->dynamic.depth_bounds.min = minDepthBounds;
3645 state->dynamic.depth_bounds.max = maxDepthBounds;
3646
3647 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3648 }
3649
3650 void radv_CmdSetStencilCompareMask(
3651 VkCommandBuffer commandBuffer,
3652 VkStencilFaceFlags faceMask,
3653 uint32_t compareMask)
3654 {
3655 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3656 struct radv_cmd_state *state = &cmd_buffer->state;
3657 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3658 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3659
3660 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3661 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3662 return;
3663 }
3664
3665 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3666 state->dynamic.stencil_compare_mask.front = compareMask;
3667 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3668 state->dynamic.stencil_compare_mask.back = compareMask;
3669
3670 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3671 }
3672
3673 void radv_CmdSetStencilWriteMask(
3674 VkCommandBuffer commandBuffer,
3675 VkStencilFaceFlags faceMask,
3676 uint32_t writeMask)
3677 {
3678 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3679 struct radv_cmd_state *state = &cmd_buffer->state;
3680 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3681 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3682
3683 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3684 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3685 return;
3686 }
3687
3688 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3689 state->dynamic.stencil_write_mask.front = writeMask;
3690 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3691 state->dynamic.stencil_write_mask.back = writeMask;
3692
3693 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3694 }
3695
3696 void radv_CmdSetStencilReference(
3697 VkCommandBuffer commandBuffer,
3698 VkStencilFaceFlags faceMask,
3699 uint32_t reference)
3700 {
3701 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3702 struct radv_cmd_state *state = &cmd_buffer->state;
3703 bool front_same = state->dynamic.stencil_reference.front == reference;
3704 bool back_same = state->dynamic.stencil_reference.back == reference;
3705
3706 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3707 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3708 return;
3709 }
3710
3711 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3712 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3713 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3714 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3715
3716 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3717 }
3718
3719 void radv_CmdSetDiscardRectangleEXT(
3720 VkCommandBuffer commandBuffer,
3721 uint32_t firstDiscardRectangle,
3722 uint32_t discardRectangleCount,
3723 const VkRect2D* pDiscardRectangles)
3724 {
3725 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3726 struct radv_cmd_state *state = &cmd_buffer->state;
3727 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3728
3729 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3730 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3731
3732 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3733 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3734 return;
3735 }
3736
3737 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3738 pDiscardRectangles, discardRectangleCount);
3739
3740 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3741 }
3742
3743 void radv_CmdSetSampleLocationsEXT(
3744 VkCommandBuffer commandBuffer,
3745 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3746 {
3747 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3748 struct radv_cmd_state *state = &cmd_buffer->state;
3749
3750 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3751
3752 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3753 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3754 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3755 typed_memcpy(&state->dynamic.sample_location.locations[0],
3756 pSampleLocationsInfo->pSampleLocations,
3757 pSampleLocationsInfo->sampleLocationsCount);
3758
3759 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3760 }
3761
3762 void radv_CmdExecuteCommands(
3763 VkCommandBuffer commandBuffer,
3764 uint32_t commandBufferCount,
3765 const VkCommandBuffer* pCmdBuffers)
3766 {
3767 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3768
3769 assert(commandBufferCount > 0);
3770
3771 /* Emit pending flushes on primary prior to executing secondary */
3772 si_emit_cache_flush(primary);
3773
3774 for (uint32_t i = 0; i < commandBufferCount; i++) {
3775 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3776
3777 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3778 secondary->scratch_size_needed);
3779 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3780 secondary->compute_scratch_size_needed);
3781
3782 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3783 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3784 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3785 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3786 if (secondary->tess_rings_needed)
3787 primary->tess_rings_needed = true;
3788 if (secondary->sample_positions_needed)
3789 primary->sample_positions_needed = true;
3790
3791 if (!secondary->state.framebuffer &&
3792 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
3793 /* Emit the framebuffer state from primary if secondary
3794 * has been recorded without a framebuffer, otherwise
3795 * fast color/depth clears can't work.
3796 */
3797 radv_emit_framebuffer_state(primary);
3798 }
3799
3800 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3801
3802
3803 /* When the secondary command buffer is compute only we don't
3804 * need to re-emit the current graphics pipeline.
3805 */
3806 if (secondary->state.emitted_pipeline) {
3807 primary->state.emitted_pipeline =
3808 secondary->state.emitted_pipeline;
3809 }
3810
3811 /* When the secondary command buffer is graphics only we don't
3812 * need to re-emit the current compute pipeline.
3813 */
3814 if (secondary->state.emitted_compute_pipeline) {
3815 primary->state.emitted_compute_pipeline =
3816 secondary->state.emitted_compute_pipeline;
3817 }
3818
3819 /* Only re-emit the draw packets when needed. */
3820 if (secondary->state.last_primitive_reset_en != -1) {
3821 primary->state.last_primitive_reset_en =
3822 secondary->state.last_primitive_reset_en;
3823 }
3824
3825 if (secondary->state.last_primitive_reset_index) {
3826 primary->state.last_primitive_reset_index =
3827 secondary->state.last_primitive_reset_index;
3828 }
3829
3830 if (secondary->state.last_ia_multi_vgt_param) {
3831 primary->state.last_ia_multi_vgt_param =
3832 secondary->state.last_ia_multi_vgt_param;
3833 }
3834
3835 primary->state.last_first_instance = secondary->state.last_first_instance;
3836 primary->state.last_num_instances = secondary->state.last_num_instances;
3837 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3838
3839 if (secondary->state.last_index_type != -1) {
3840 primary->state.last_index_type =
3841 secondary->state.last_index_type;
3842 }
3843 }
3844
3845 /* After executing commands from secondary buffers we have to dirty
3846 * some states.
3847 */
3848 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3849 RADV_CMD_DIRTY_INDEX_BUFFER |
3850 RADV_CMD_DIRTY_DYNAMIC_ALL;
3851 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3852 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3853 }
3854
3855 VkResult radv_CreateCommandPool(
3856 VkDevice _device,
3857 const VkCommandPoolCreateInfo* pCreateInfo,
3858 const VkAllocationCallbacks* pAllocator,
3859 VkCommandPool* pCmdPool)
3860 {
3861 RADV_FROM_HANDLE(radv_device, device, _device);
3862 struct radv_cmd_pool *pool;
3863
3864 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3865 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3866 if (pool == NULL)
3867 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3868
3869 if (pAllocator)
3870 pool->alloc = *pAllocator;
3871 else
3872 pool->alloc = device->alloc;
3873
3874 list_inithead(&pool->cmd_buffers);
3875 list_inithead(&pool->free_cmd_buffers);
3876
3877 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3878
3879 *pCmdPool = radv_cmd_pool_to_handle(pool);
3880
3881 return VK_SUCCESS;
3882
3883 }
3884
3885 void radv_DestroyCommandPool(
3886 VkDevice _device,
3887 VkCommandPool commandPool,
3888 const VkAllocationCallbacks* pAllocator)
3889 {
3890 RADV_FROM_HANDLE(radv_device, device, _device);
3891 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3892
3893 if (!pool)
3894 return;
3895
3896 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3897 &pool->cmd_buffers, pool_link) {
3898 radv_cmd_buffer_destroy(cmd_buffer);
3899 }
3900
3901 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3902 &pool->free_cmd_buffers, pool_link) {
3903 radv_cmd_buffer_destroy(cmd_buffer);
3904 }
3905
3906 vk_free2(&device->alloc, pAllocator, pool);
3907 }
3908
3909 VkResult radv_ResetCommandPool(
3910 VkDevice device,
3911 VkCommandPool commandPool,
3912 VkCommandPoolResetFlags flags)
3913 {
3914 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3915 VkResult result;
3916
3917 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3918 &pool->cmd_buffers, pool_link) {
3919 result = radv_reset_cmd_buffer(cmd_buffer);
3920 if (result != VK_SUCCESS)
3921 return result;
3922 }
3923
3924 return VK_SUCCESS;
3925 }
3926
3927 void radv_TrimCommandPool(
3928 VkDevice device,
3929 VkCommandPool commandPool,
3930 VkCommandPoolTrimFlags flags)
3931 {
3932 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3933
3934 if (!pool)
3935 return;
3936
3937 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3938 &pool->free_cmd_buffers, pool_link) {
3939 radv_cmd_buffer_destroy(cmd_buffer);
3940 }
3941 }
3942
3943 static void
3944 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
3945 uint32_t subpass_id)
3946 {
3947 struct radv_cmd_state *state = &cmd_buffer->state;
3948 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
3949
3950 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3951 cmd_buffer->cs, 4096);
3952
3953 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
3954
3955 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3956
3957 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3958 const uint32_t a = subpass->attachments[i].attachment;
3959 if (a == VK_ATTACHMENT_UNUSED)
3960 continue;
3961
3962 radv_handle_subpass_image_transition(cmd_buffer,
3963 subpass->attachments[i],
3964 true);
3965 }
3966
3967 radv_cmd_buffer_clear_subpass(cmd_buffer);
3968
3969 assert(cmd_buffer->cs->cdw <= cdw_max);
3970 }
3971
3972 static void
3973 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
3974 {
3975 struct radv_cmd_state *state = &cmd_buffer->state;
3976 const struct radv_subpass *subpass = state->subpass;
3977 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3978
3979 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3980
3981 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3982 const uint32_t a = subpass->attachments[i].attachment;
3983 if (a == VK_ATTACHMENT_UNUSED)
3984 continue;
3985
3986 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
3987 continue;
3988
3989 VkImageLayout layout = state->pass->attachments[a].final_layout;
3990 struct radv_subpass_attachment att = { a, layout };
3991 radv_handle_subpass_image_transition(cmd_buffer, att, false);
3992 }
3993 }
3994
3995 void radv_CmdBeginRenderPass(
3996 VkCommandBuffer commandBuffer,
3997 const VkRenderPassBeginInfo* pRenderPassBegin,
3998 VkSubpassContents contents)
3999 {
4000 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4001 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4002 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4003 VkResult result;
4004
4005 cmd_buffer->state.framebuffer = framebuffer;
4006 cmd_buffer->state.pass = pass;
4007 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4008
4009 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4010 if (result != VK_SUCCESS)
4011 return;
4012
4013 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4014 if (result != VK_SUCCESS)
4015 return;
4016
4017 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4018 }
4019
4020 void radv_CmdBeginRenderPass2KHR(
4021 VkCommandBuffer commandBuffer,
4022 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4023 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
4024 {
4025 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4026 pSubpassBeginInfo->contents);
4027 }
4028
4029 void radv_CmdNextSubpass(
4030 VkCommandBuffer commandBuffer,
4031 VkSubpassContents contents)
4032 {
4033 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4034
4035 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4036 radv_cmd_buffer_end_subpass(cmd_buffer);
4037 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4038 }
4039
4040 void radv_CmdNextSubpass2KHR(
4041 VkCommandBuffer commandBuffer,
4042 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
4043 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4044 {
4045 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4046 }
4047
4048 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4049 {
4050 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4051 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4052 if (!radv_get_shader(pipeline, stage))
4053 continue;
4054
4055 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4056 if (loc->sgpr_idx == -1)
4057 continue;
4058 uint32_t base_reg = pipeline->user_data_0[stage];
4059 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4060
4061 }
4062 if (pipeline->gs_copy_shader) {
4063 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4064 if (loc->sgpr_idx != -1) {
4065 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4066 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4067 }
4068 }
4069 }
4070
4071 static void
4072 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4073 uint32_t vertex_count,
4074 bool use_opaque)
4075 {
4076 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4077 radeon_emit(cmd_buffer->cs, vertex_count);
4078 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4079 S_0287F0_USE_OPAQUE(use_opaque));
4080 }
4081
4082 static void
4083 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4084 uint64_t index_va,
4085 uint32_t index_count)
4086 {
4087 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4088 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4089 radeon_emit(cmd_buffer->cs, index_va);
4090 radeon_emit(cmd_buffer->cs, index_va >> 32);
4091 radeon_emit(cmd_buffer->cs, index_count);
4092 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4093 }
4094
4095 static void
4096 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4097 bool indexed,
4098 uint32_t draw_count,
4099 uint64_t count_va,
4100 uint32_t stride)
4101 {
4102 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4103 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4104 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4105 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
4106 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4107 bool predicating = cmd_buffer->state.predicating;
4108 assert(base_reg);
4109
4110 /* just reset draw state for vertex data */
4111 cmd_buffer->state.last_first_instance = -1;
4112 cmd_buffer->state.last_num_instances = -1;
4113 cmd_buffer->state.last_vertex_offset = -1;
4114
4115 if (draw_count == 1 && !count_va && !draw_id_enable) {
4116 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4117 PKT3_DRAW_INDIRECT, 3, predicating));
4118 radeon_emit(cs, 0);
4119 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4120 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4121 radeon_emit(cs, di_src_sel);
4122 } else {
4123 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4124 PKT3_DRAW_INDIRECT_MULTI,
4125 8, predicating));
4126 radeon_emit(cs, 0);
4127 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4128 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4129 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4130 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4131 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4132 radeon_emit(cs, draw_count); /* count */
4133 radeon_emit(cs, count_va); /* count_addr */
4134 radeon_emit(cs, count_va >> 32);
4135 radeon_emit(cs, stride); /* stride */
4136 radeon_emit(cs, di_src_sel);
4137 }
4138 }
4139
4140 static void
4141 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4142 const struct radv_draw_info *info)
4143 {
4144 struct radv_cmd_state *state = &cmd_buffer->state;
4145 struct radeon_winsys *ws = cmd_buffer->device->ws;
4146 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4147
4148 if (info->indirect) {
4149 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4150 uint64_t count_va = 0;
4151
4152 va += info->indirect->offset + info->indirect_offset;
4153
4154 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4155
4156 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4157 radeon_emit(cs, 1);
4158 radeon_emit(cs, va);
4159 radeon_emit(cs, va >> 32);
4160
4161 if (info->count_buffer) {
4162 count_va = radv_buffer_get_va(info->count_buffer->bo);
4163 count_va += info->count_buffer->offset +
4164 info->count_buffer_offset;
4165
4166 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4167 }
4168
4169 if (!state->subpass->view_mask) {
4170 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4171 info->indexed,
4172 info->count,
4173 count_va,
4174 info->stride);
4175 } else {
4176 unsigned i;
4177 for_each_bit(i, state->subpass->view_mask) {
4178 radv_emit_view_index(cmd_buffer, i);
4179
4180 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4181 info->indexed,
4182 info->count,
4183 count_va,
4184 info->stride);
4185 }
4186 }
4187 } else {
4188 assert(state->pipeline->graphics.vtx_base_sgpr);
4189
4190 if (info->vertex_offset != state->last_vertex_offset ||
4191 info->first_instance != state->last_first_instance) {
4192 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4193 state->pipeline->graphics.vtx_emit_num);
4194
4195 radeon_emit(cs, info->vertex_offset);
4196 radeon_emit(cs, info->first_instance);
4197 if (state->pipeline->graphics.vtx_emit_num == 3)
4198 radeon_emit(cs, 0);
4199 state->last_first_instance = info->first_instance;
4200 state->last_vertex_offset = info->vertex_offset;
4201 }
4202
4203 if (state->last_num_instances != info->instance_count) {
4204 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4205 radeon_emit(cs, info->instance_count);
4206 state->last_num_instances = info->instance_count;
4207 }
4208
4209 if (info->indexed) {
4210 int index_size = state->index_type ? 4 : 2;
4211 uint64_t index_va;
4212
4213 index_va = state->index_va;
4214 index_va += info->first_index * index_size;
4215
4216 if (!state->subpass->view_mask) {
4217 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4218 index_va,
4219 info->count);
4220 } else {
4221 unsigned i;
4222 for_each_bit(i, state->subpass->view_mask) {
4223 radv_emit_view_index(cmd_buffer, i);
4224
4225 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4226 index_va,
4227 info->count);
4228 }
4229 }
4230 } else {
4231 if (!state->subpass->view_mask) {
4232 radv_cs_emit_draw_packet(cmd_buffer,
4233 info->count,
4234 !!info->strmout_buffer);
4235 } else {
4236 unsigned i;
4237 for_each_bit(i, state->subpass->view_mask) {
4238 radv_emit_view_index(cmd_buffer, i);
4239
4240 radv_cs_emit_draw_packet(cmd_buffer,
4241 info->count,
4242 !!info->strmout_buffer);
4243 }
4244 }
4245 }
4246 }
4247 }
4248
4249 /*
4250 * Vega and raven have a bug which triggers if there are multiple context
4251 * register contexts active at the same time with different scissor values.
4252 *
4253 * There are two possible workarounds:
4254 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4255 * there is only ever 1 active set of scissor values at the same time.
4256 *
4257 * 2) Whenever the hardware switches contexts we have to set the scissor
4258 * registers again even if it is a noop. That way the new context gets
4259 * the correct scissor values.
4260 *
4261 * This implements option 2. radv_need_late_scissor_emission needs to
4262 * return true on affected HW if radv_emit_all_graphics_states sets
4263 * any context registers.
4264 */
4265 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4266 const struct radv_draw_info *info)
4267 {
4268 struct radv_cmd_state *state = &cmd_buffer->state;
4269
4270 if (!cmd_buffer->device->physical_device->has_scissor_bug)
4271 return false;
4272
4273 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4274 return true;
4275
4276 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4277
4278 /* Index, vertex and streamout buffers don't change context regs, and
4279 * pipeline is already handled.
4280 */
4281 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4282 RADV_CMD_DIRTY_VERTEX_BUFFER |
4283 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4284 RADV_CMD_DIRTY_PIPELINE);
4285
4286 if (cmd_buffer->state.dirty & used_states)
4287 return true;
4288
4289 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4290 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
4291 return true;
4292
4293 return false;
4294 }
4295
4296 static void
4297 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4298 const struct radv_draw_info *info)
4299 {
4300 bool late_scissor_emission;
4301
4302 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4303 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4304 radv_emit_rbplus_state(cmd_buffer);
4305
4306 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4307 radv_emit_graphics_pipeline(cmd_buffer);
4308
4309 /* This should be before the cmd_buffer->state.dirty is cleared
4310 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4311 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4312 late_scissor_emission =
4313 radv_need_late_scissor_emission(cmd_buffer, info);
4314
4315 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4316 radv_emit_framebuffer_state(cmd_buffer);
4317
4318 if (info->indexed) {
4319 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4320 radv_emit_index_buffer(cmd_buffer);
4321 } else {
4322 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4323 * so the state must be re-emitted before the next indexed
4324 * draw.
4325 */
4326 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4327 cmd_buffer->state.last_index_type = -1;
4328 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4329 }
4330 }
4331
4332 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4333
4334 radv_emit_draw_registers(cmd_buffer, info);
4335
4336 if (late_scissor_emission)
4337 radv_emit_scissor(cmd_buffer);
4338 }
4339
4340 static void
4341 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4342 const struct radv_draw_info *info)
4343 {
4344 struct radeon_info *rad_info =
4345 &cmd_buffer->device->physical_device->rad_info;
4346 bool has_prefetch =
4347 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4348 bool pipeline_is_dirty =
4349 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4350 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4351
4352 MAYBE_UNUSED unsigned cdw_max =
4353 radeon_check_space(cmd_buffer->device->ws,
4354 cmd_buffer->cs, 4096);
4355
4356 if (likely(!info->indirect)) {
4357 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4358 * no workaround for indirect draws, but we can at least skip
4359 * direct draws.
4360 */
4361 if (unlikely(!info->instance_count))
4362 return;
4363
4364 /* Handle count == 0. */
4365 if (unlikely(!info->count && !info->strmout_buffer))
4366 return;
4367 }
4368
4369 /* Use optimal packet order based on whether we need to sync the
4370 * pipeline.
4371 */
4372 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4373 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4374 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4375 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4376 /* If we have to wait for idle, set all states first, so that
4377 * all SET packets are processed in parallel with previous draw
4378 * calls. Then upload descriptors, set shader pointers, and
4379 * draw, and prefetch at the end. This ensures that the time
4380 * the CUs are idle is very short. (there are only SET_SH
4381 * packets between the wait and the draw)
4382 */
4383 radv_emit_all_graphics_states(cmd_buffer, info);
4384 si_emit_cache_flush(cmd_buffer);
4385 /* <-- CUs are idle here --> */
4386
4387 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4388
4389 radv_emit_draw_packets(cmd_buffer, info);
4390 /* <-- CUs are busy here --> */
4391
4392 /* Start prefetches after the draw has been started. Both will
4393 * run in parallel, but starting the draw first is more
4394 * important.
4395 */
4396 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4397 radv_emit_prefetch_L2(cmd_buffer,
4398 cmd_buffer->state.pipeline, false);
4399 }
4400 } else {
4401 /* If we don't wait for idle, start prefetches first, then set
4402 * states, and draw at the end.
4403 */
4404 si_emit_cache_flush(cmd_buffer);
4405
4406 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4407 /* Only prefetch the vertex shader and VBO descriptors
4408 * in order to start the draw as soon as possible.
4409 */
4410 radv_emit_prefetch_L2(cmd_buffer,
4411 cmd_buffer->state.pipeline, true);
4412 }
4413
4414 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4415
4416 radv_emit_all_graphics_states(cmd_buffer, info);
4417 radv_emit_draw_packets(cmd_buffer, info);
4418
4419 /* Prefetch the remaining shaders after the draw has been
4420 * started.
4421 */
4422 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4423 radv_emit_prefetch_L2(cmd_buffer,
4424 cmd_buffer->state.pipeline, false);
4425 }
4426 }
4427
4428 /* Workaround for a VGT hang when streamout is enabled.
4429 * It must be done after drawing.
4430 */
4431 if (cmd_buffer->state.streamout.streamout_enabled &&
4432 (rad_info->family == CHIP_HAWAII ||
4433 rad_info->family == CHIP_TONGA ||
4434 rad_info->family == CHIP_FIJI)) {
4435 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4436 }
4437
4438 assert(cmd_buffer->cs->cdw <= cdw_max);
4439 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4440 }
4441
4442 void radv_CmdDraw(
4443 VkCommandBuffer commandBuffer,
4444 uint32_t vertexCount,
4445 uint32_t instanceCount,
4446 uint32_t firstVertex,
4447 uint32_t firstInstance)
4448 {
4449 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4450 struct radv_draw_info info = {};
4451
4452 info.count = vertexCount;
4453 info.instance_count = instanceCount;
4454 info.first_instance = firstInstance;
4455 info.vertex_offset = firstVertex;
4456
4457 radv_draw(cmd_buffer, &info);
4458 }
4459
4460 void radv_CmdDrawIndexed(
4461 VkCommandBuffer commandBuffer,
4462 uint32_t indexCount,
4463 uint32_t instanceCount,
4464 uint32_t firstIndex,
4465 int32_t vertexOffset,
4466 uint32_t firstInstance)
4467 {
4468 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4469 struct radv_draw_info info = {};
4470
4471 info.indexed = true;
4472 info.count = indexCount;
4473 info.instance_count = instanceCount;
4474 info.first_index = firstIndex;
4475 info.vertex_offset = vertexOffset;
4476 info.first_instance = firstInstance;
4477
4478 radv_draw(cmd_buffer, &info);
4479 }
4480
4481 void radv_CmdDrawIndirect(
4482 VkCommandBuffer commandBuffer,
4483 VkBuffer _buffer,
4484 VkDeviceSize offset,
4485 uint32_t drawCount,
4486 uint32_t stride)
4487 {
4488 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4489 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4490 struct radv_draw_info info = {};
4491
4492 info.count = drawCount;
4493 info.indirect = buffer;
4494 info.indirect_offset = offset;
4495 info.stride = stride;
4496
4497 radv_draw(cmd_buffer, &info);
4498 }
4499
4500 void radv_CmdDrawIndexedIndirect(
4501 VkCommandBuffer commandBuffer,
4502 VkBuffer _buffer,
4503 VkDeviceSize offset,
4504 uint32_t drawCount,
4505 uint32_t stride)
4506 {
4507 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4508 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4509 struct radv_draw_info info = {};
4510
4511 info.indexed = true;
4512 info.count = drawCount;
4513 info.indirect = buffer;
4514 info.indirect_offset = offset;
4515 info.stride = stride;
4516
4517 radv_draw(cmd_buffer, &info);
4518 }
4519
4520 void radv_CmdDrawIndirectCountKHR(
4521 VkCommandBuffer commandBuffer,
4522 VkBuffer _buffer,
4523 VkDeviceSize offset,
4524 VkBuffer _countBuffer,
4525 VkDeviceSize countBufferOffset,
4526 uint32_t maxDrawCount,
4527 uint32_t stride)
4528 {
4529 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4530 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4531 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4532 struct radv_draw_info info = {};
4533
4534 info.count = maxDrawCount;
4535 info.indirect = buffer;
4536 info.indirect_offset = offset;
4537 info.count_buffer = count_buffer;
4538 info.count_buffer_offset = countBufferOffset;
4539 info.stride = stride;
4540
4541 radv_draw(cmd_buffer, &info);
4542 }
4543
4544 void radv_CmdDrawIndexedIndirectCountKHR(
4545 VkCommandBuffer commandBuffer,
4546 VkBuffer _buffer,
4547 VkDeviceSize offset,
4548 VkBuffer _countBuffer,
4549 VkDeviceSize countBufferOffset,
4550 uint32_t maxDrawCount,
4551 uint32_t stride)
4552 {
4553 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4554 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4555 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4556 struct radv_draw_info info = {};
4557
4558 info.indexed = true;
4559 info.count = maxDrawCount;
4560 info.indirect = buffer;
4561 info.indirect_offset = offset;
4562 info.count_buffer = count_buffer;
4563 info.count_buffer_offset = countBufferOffset;
4564 info.stride = stride;
4565
4566 radv_draw(cmd_buffer, &info);
4567 }
4568
4569 struct radv_dispatch_info {
4570 /**
4571 * Determine the layout of the grid (in block units) to be used.
4572 */
4573 uint32_t blocks[3];
4574
4575 /**
4576 * A starting offset for the grid. If unaligned is set, the offset
4577 * must still be aligned.
4578 */
4579 uint32_t offsets[3];
4580 /**
4581 * Whether it's an unaligned compute dispatch.
4582 */
4583 bool unaligned;
4584
4585 /**
4586 * Indirect compute parameters resource.
4587 */
4588 struct radv_buffer *indirect;
4589 uint64_t indirect_offset;
4590 };
4591
4592 static void
4593 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4594 const struct radv_dispatch_info *info)
4595 {
4596 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4597 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4598 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4599 struct radeon_winsys *ws = cmd_buffer->device->ws;
4600 bool predicating = cmd_buffer->state.predicating;
4601 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4602 struct radv_userdata_info *loc;
4603
4604 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4605 AC_UD_CS_GRID_SIZE);
4606
4607 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4608
4609 if (info->indirect) {
4610 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4611
4612 va += info->indirect->offset + info->indirect_offset;
4613
4614 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4615
4616 if (loc->sgpr_idx != -1) {
4617 for (unsigned i = 0; i < 3; ++i) {
4618 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4619 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4620 COPY_DATA_DST_SEL(COPY_DATA_REG));
4621 radeon_emit(cs, (va + 4 * i));
4622 radeon_emit(cs, (va + 4 * i) >> 32);
4623 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4624 + loc->sgpr_idx * 4) >> 2) + i);
4625 radeon_emit(cs, 0);
4626 }
4627 }
4628
4629 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4630 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4631 PKT3_SHADER_TYPE_S(1));
4632 radeon_emit(cs, va);
4633 radeon_emit(cs, va >> 32);
4634 radeon_emit(cs, dispatch_initiator);
4635 } else {
4636 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4637 PKT3_SHADER_TYPE_S(1));
4638 radeon_emit(cs, 1);
4639 radeon_emit(cs, va);
4640 radeon_emit(cs, va >> 32);
4641
4642 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4643 PKT3_SHADER_TYPE_S(1));
4644 radeon_emit(cs, 0);
4645 radeon_emit(cs, dispatch_initiator);
4646 }
4647 } else {
4648 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4649 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4650
4651 if (info->unaligned) {
4652 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4653 unsigned remainder[3];
4654
4655 /* If aligned, these should be an entire block size,
4656 * not 0.
4657 */
4658 remainder[0] = blocks[0] + cs_block_size[0] -
4659 align_u32_npot(blocks[0], cs_block_size[0]);
4660 remainder[1] = blocks[1] + cs_block_size[1] -
4661 align_u32_npot(blocks[1], cs_block_size[1]);
4662 remainder[2] = blocks[2] + cs_block_size[2] -
4663 align_u32_npot(blocks[2], cs_block_size[2]);
4664
4665 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4666 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4667 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4668
4669 for(unsigned i = 0; i < 3; ++i) {
4670 assert(offsets[i] % cs_block_size[i] == 0);
4671 offsets[i] /= cs_block_size[i];
4672 }
4673
4674 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4675 radeon_emit(cs,
4676 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4677 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4678 radeon_emit(cs,
4679 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4680 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4681 radeon_emit(cs,
4682 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4683 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4684
4685 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4686 }
4687
4688 if (loc->sgpr_idx != -1) {
4689 assert(loc->num_sgprs == 3);
4690
4691 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4692 loc->sgpr_idx * 4, 3);
4693 radeon_emit(cs, blocks[0]);
4694 radeon_emit(cs, blocks[1]);
4695 radeon_emit(cs, blocks[2]);
4696 }
4697
4698 if (offsets[0] || offsets[1] || offsets[2]) {
4699 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4700 radeon_emit(cs, offsets[0]);
4701 radeon_emit(cs, offsets[1]);
4702 radeon_emit(cs, offsets[2]);
4703
4704 /* The blocks in the packet are not counts but end values. */
4705 for (unsigned i = 0; i < 3; ++i)
4706 blocks[i] += offsets[i];
4707 } else {
4708 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4709 }
4710
4711 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4712 PKT3_SHADER_TYPE_S(1));
4713 radeon_emit(cs, blocks[0]);
4714 radeon_emit(cs, blocks[1]);
4715 radeon_emit(cs, blocks[2]);
4716 radeon_emit(cs, dispatch_initiator);
4717 }
4718
4719 assert(cmd_buffer->cs->cdw <= cdw_max);
4720 }
4721
4722 static void
4723 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4724 {
4725 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4726 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4727 }
4728
4729 static void
4730 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4731 const struct radv_dispatch_info *info)
4732 {
4733 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4734 bool has_prefetch =
4735 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4736 bool pipeline_is_dirty = pipeline &&
4737 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4738
4739 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4740 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4741 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4742 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4743 /* If we have to wait for idle, set all states first, so that
4744 * all SET packets are processed in parallel with previous draw
4745 * calls. Then upload descriptors, set shader pointers, and
4746 * dispatch, and prefetch at the end. This ensures that the
4747 * time the CUs are idle is very short. (there are only SET_SH
4748 * packets between the wait and the draw)
4749 */
4750 radv_emit_compute_pipeline(cmd_buffer);
4751 si_emit_cache_flush(cmd_buffer);
4752 /* <-- CUs are idle here --> */
4753
4754 radv_upload_compute_shader_descriptors(cmd_buffer);
4755
4756 radv_emit_dispatch_packets(cmd_buffer, info);
4757 /* <-- CUs are busy here --> */
4758
4759 /* Start prefetches after the dispatch has been started. Both
4760 * will run in parallel, but starting the dispatch first is
4761 * more important.
4762 */
4763 if (has_prefetch && pipeline_is_dirty) {
4764 radv_emit_shader_prefetch(cmd_buffer,
4765 pipeline->shaders[MESA_SHADER_COMPUTE]);
4766 }
4767 } else {
4768 /* If we don't wait for idle, start prefetches first, then set
4769 * states, and dispatch at the end.
4770 */
4771 si_emit_cache_flush(cmd_buffer);
4772
4773 if (has_prefetch && pipeline_is_dirty) {
4774 radv_emit_shader_prefetch(cmd_buffer,
4775 pipeline->shaders[MESA_SHADER_COMPUTE]);
4776 }
4777
4778 radv_upload_compute_shader_descriptors(cmd_buffer);
4779
4780 radv_emit_compute_pipeline(cmd_buffer);
4781 radv_emit_dispatch_packets(cmd_buffer, info);
4782 }
4783
4784 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4785 }
4786
4787 void radv_CmdDispatchBase(
4788 VkCommandBuffer commandBuffer,
4789 uint32_t base_x,
4790 uint32_t base_y,
4791 uint32_t base_z,
4792 uint32_t x,
4793 uint32_t y,
4794 uint32_t z)
4795 {
4796 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4797 struct radv_dispatch_info info = {};
4798
4799 info.blocks[0] = x;
4800 info.blocks[1] = y;
4801 info.blocks[2] = z;
4802
4803 info.offsets[0] = base_x;
4804 info.offsets[1] = base_y;
4805 info.offsets[2] = base_z;
4806 radv_dispatch(cmd_buffer, &info);
4807 }
4808
4809 void radv_CmdDispatch(
4810 VkCommandBuffer commandBuffer,
4811 uint32_t x,
4812 uint32_t y,
4813 uint32_t z)
4814 {
4815 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4816 }
4817
4818 void radv_CmdDispatchIndirect(
4819 VkCommandBuffer commandBuffer,
4820 VkBuffer _buffer,
4821 VkDeviceSize offset)
4822 {
4823 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4824 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4825 struct radv_dispatch_info info = {};
4826
4827 info.indirect = buffer;
4828 info.indirect_offset = offset;
4829
4830 radv_dispatch(cmd_buffer, &info);
4831 }
4832
4833 void radv_unaligned_dispatch(
4834 struct radv_cmd_buffer *cmd_buffer,
4835 uint32_t x,
4836 uint32_t y,
4837 uint32_t z)
4838 {
4839 struct radv_dispatch_info info = {};
4840
4841 info.blocks[0] = x;
4842 info.blocks[1] = y;
4843 info.blocks[2] = z;
4844 info.unaligned = 1;
4845
4846 radv_dispatch(cmd_buffer, &info);
4847 }
4848
4849 void radv_CmdEndRenderPass(
4850 VkCommandBuffer commandBuffer)
4851 {
4852 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4853
4854 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4855
4856 radv_cmd_buffer_end_subpass(cmd_buffer);
4857
4858 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4859 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
4860
4861 cmd_buffer->state.pass = NULL;
4862 cmd_buffer->state.subpass = NULL;
4863 cmd_buffer->state.attachments = NULL;
4864 cmd_buffer->state.framebuffer = NULL;
4865 cmd_buffer->state.subpass_sample_locs = NULL;
4866 }
4867
4868 void radv_CmdEndRenderPass2KHR(
4869 VkCommandBuffer commandBuffer,
4870 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4871 {
4872 radv_CmdEndRenderPass(commandBuffer);
4873 }
4874
4875 /*
4876 * For HTILE we have the following interesting clear words:
4877 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4878 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4879 * 0xfffffff0: Clear depth to 1.0
4880 * 0x00000000: Clear depth to 0.0
4881 */
4882 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4883 struct radv_image *image,
4884 const VkImageSubresourceRange *range,
4885 uint32_t clear_word)
4886 {
4887 assert(range->baseMipLevel == 0);
4888 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4889 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4890 struct radv_cmd_state *state = &cmd_buffer->state;
4891 VkClearDepthStencilValue value = {};
4892
4893 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4894 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4895
4896 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
4897
4898 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4899
4900 if (vk_format_is_stencil(image->vk_format))
4901 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4902
4903 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4904
4905 if (radv_image_is_tc_compat_htile(image)) {
4906 /* Initialize the TC-compat metada value to 0 because by
4907 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4908 * need have to conditionally update its value when performing
4909 * a fast depth clear.
4910 */
4911 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4912 }
4913 }
4914
4915 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4916 struct radv_image *image,
4917 VkImageLayout src_layout,
4918 VkImageLayout dst_layout,
4919 unsigned src_queue_mask,
4920 unsigned dst_queue_mask,
4921 const VkImageSubresourceRange *range,
4922 struct radv_sample_locations_state *sample_locs)
4923 {
4924 if (!radv_image_has_htile(image))
4925 return;
4926
4927 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4928 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4929
4930 if (radv_layout_is_htile_compressed(image, dst_layout,
4931 dst_queue_mask)) {
4932 clear_value = 0;
4933 }
4934
4935 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4936 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4937 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4938 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4939 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4940 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4941 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4942 VkImageSubresourceRange local_range = *range;
4943 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4944 local_range.baseMipLevel = 0;
4945 local_range.levelCount = 1;
4946
4947 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4948 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4949
4950 radv_decompress_depth_image_inplace(cmd_buffer, image,
4951 &local_range, sample_locs);
4952
4953 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4954 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4955 }
4956 }
4957
4958 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4959 struct radv_image *image,
4960 const VkImageSubresourceRange *range,
4961 uint32_t value)
4962 {
4963 struct radv_cmd_state *state = &cmd_buffer->state;
4964
4965 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4966 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4967
4968 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
4969
4970 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4971 }
4972
4973 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4974 struct radv_image *image,
4975 const VkImageSubresourceRange *range)
4976 {
4977 struct radv_cmd_state *state = &cmd_buffer->state;
4978 static const uint32_t fmask_clear_values[4] = {
4979 0x00000000,
4980 0x02020202,
4981 0xE4E4E4E4,
4982 0x76543210
4983 };
4984 uint32_t log2_samples = util_logbase2(image->info.samples);
4985 uint32_t value = fmask_clear_values[log2_samples];
4986
4987 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4988 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4989
4990 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
4991
4992 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4993 }
4994
4995 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4996 struct radv_image *image,
4997 const VkImageSubresourceRange *range, uint32_t value)
4998 {
4999 struct radv_cmd_state *state = &cmd_buffer->state;
5000 unsigned size = 0;
5001
5002 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5003 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5004
5005 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5006
5007 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5008 /* When DCC is enabled with mipmaps, some levels might not
5009 * support fast clears and we have to initialize them as "fully
5010 * expanded".
5011 */
5012 /* Compute the size of all fast clearable DCC levels. */
5013 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5014 struct legacy_surf_level *surf_level =
5015 &image->planes[0].surface.u.legacy.level[i];
5016 unsigned dcc_fast_clear_size =
5017 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5018
5019 if (!dcc_fast_clear_size)
5020 break;
5021
5022 size = surf_level->dcc_offset + dcc_fast_clear_size;
5023 }
5024
5025 /* Initialize the mipmap levels without DCC. */
5026 if (size != image->planes[0].surface.dcc_size) {
5027 state->flush_bits |=
5028 radv_fill_buffer(cmd_buffer, image->bo,
5029 image->offset + image->dcc_offset + size,
5030 image->planes[0].surface.dcc_size - size,
5031 0xffffffff);
5032 }
5033 }
5034
5035 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5036 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5037 }
5038
5039 /**
5040 * Initialize DCC/FMASK/CMASK metadata for a color image.
5041 */
5042 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5043 struct radv_image *image,
5044 VkImageLayout src_layout,
5045 VkImageLayout dst_layout,
5046 unsigned src_queue_mask,
5047 unsigned dst_queue_mask,
5048 const VkImageSubresourceRange *range)
5049 {
5050 if (radv_image_has_cmask(image)) {
5051 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5052
5053 /* TODO: clarify this. */
5054 if (radv_image_has_fmask(image)) {
5055 value = 0xccccccccu;
5056 }
5057
5058 radv_initialise_cmask(cmd_buffer, image, range, value);
5059 }
5060
5061 if (radv_image_has_fmask(image)) {
5062 radv_initialize_fmask(cmd_buffer, image, range);
5063 }
5064
5065 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5066 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5067 bool need_decompress_pass = false;
5068
5069 if (radv_layout_dcc_compressed(image, dst_layout,
5070 dst_queue_mask)) {
5071 value = 0x20202020u;
5072 need_decompress_pass = true;
5073 }
5074
5075 radv_initialize_dcc(cmd_buffer, image, range, value);
5076
5077 radv_update_fce_metadata(cmd_buffer, image, range,
5078 need_decompress_pass);
5079 }
5080
5081 if (radv_image_has_cmask(image) ||
5082 radv_dcc_enabled(image, range->baseMipLevel)) {
5083 uint32_t color_values[2] = {};
5084 radv_set_color_clear_metadata(cmd_buffer, image, range,
5085 color_values);
5086 }
5087 }
5088
5089 /**
5090 * Handle color image transitions for DCC/FMASK/CMASK.
5091 */
5092 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5093 struct radv_image *image,
5094 VkImageLayout src_layout,
5095 VkImageLayout dst_layout,
5096 unsigned src_queue_mask,
5097 unsigned dst_queue_mask,
5098 const VkImageSubresourceRange *range)
5099 {
5100 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5101 radv_init_color_image_metadata(cmd_buffer, image,
5102 src_layout, dst_layout,
5103 src_queue_mask, dst_queue_mask,
5104 range);
5105 return;
5106 }
5107
5108 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5109 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5110 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5111 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
5112 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
5113 radv_decompress_dcc(cmd_buffer, image, range);
5114 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5115 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5116 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5117 }
5118 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5119 bool fce_eliminate = false, fmask_expand = false;
5120
5121 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5122 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5123 fce_eliminate = true;
5124 }
5125
5126 if (radv_image_has_fmask(image)) {
5127 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5128 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5129 /* A FMASK decompress is required before doing
5130 * a MSAA decompress using FMASK.
5131 */
5132 fmask_expand = true;
5133 }
5134 }
5135
5136 if (fce_eliminate || fmask_expand)
5137 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5138
5139 if (fmask_expand)
5140 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5141 }
5142 }
5143
5144 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5145 struct radv_image *image,
5146 VkImageLayout src_layout,
5147 VkImageLayout dst_layout,
5148 uint32_t src_family,
5149 uint32_t dst_family,
5150 const VkImageSubresourceRange *range,
5151 struct radv_sample_locations_state *sample_locs)
5152 {
5153 if (image->exclusive && src_family != dst_family) {
5154 /* This is an acquire or a release operation and there will be
5155 * a corresponding release/acquire. Do the transition in the
5156 * most flexible queue. */
5157
5158 assert(src_family == cmd_buffer->queue_family_index ||
5159 dst_family == cmd_buffer->queue_family_index);
5160
5161 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5162 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5163 return;
5164
5165 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5166 return;
5167
5168 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5169 (src_family == RADV_QUEUE_GENERAL ||
5170 dst_family == RADV_QUEUE_GENERAL))
5171 return;
5172 }
5173
5174 if (src_layout == dst_layout)
5175 return;
5176
5177 unsigned src_queue_mask =
5178 radv_image_queue_family_mask(image, src_family,
5179 cmd_buffer->queue_family_index);
5180 unsigned dst_queue_mask =
5181 radv_image_queue_family_mask(image, dst_family,
5182 cmd_buffer->queue_family_index);
5183
5184 if (vk_format_is_depth(image->vk_format)) {
5185 radv_handle_depth_image_transition(cmd_buffer, image,
5186 src_layout, dst_layout,
5187 src_queue_mask, dst_queue_mask,
5188 range, sample_locs);
5189 } else {
5190 radv_handle_color_image_transition(cmd_buffer, image,
5191 src_layout, dst_layout,
5192 src_queue_mask, dst_queue_mask,
5193 range);
5194 }
5195 }
5196
5197 struct radv_barrier_info {
5198 uint32_t eventCount;
5199 const VkEvent *pEvents;
5200 VkPipelineStageFlags srcStageMask;
5201 VkPipelineStageFlags dstStageMask;
5202 };
5203
5204 static void
5205 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5206 uint32_t memoryBarrierCount,
5207 const VkMemoryBarrier *pMemoryBarriers,
5208 uint32_t bufferMemoryBarrierCount,
5209 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5210 uint32_t imageMemoryBarrierCount,
5211 const VkImageMemoryBarrier *pImageMemoryBarriers,
5212 const struct radv_barrier_info *info)
5213 {
5214 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5215 enum radv_cmd_flush_bits src_flush_bits = 0;
5216 enum radv_cmd_flush_bits dst_flush_bits = 0;
5217
5218 for (unsigned i = 0; i < info->eventCount; ++i) {
5219 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5220 uint64_t va = radv_buffer_get_va(event->bo);
5221
5222 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5223
5224 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5225
5226 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5227 assert(cmd_buffer->cs->cdw <= cdw_max);
5228 }
5229
5230 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5231 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5232 NULL);
5233 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5234 NULL);
5235 }
5236
5237 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5238 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5239 NULL);
5240 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5241 NULL);
5242 }
5243
5244 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5245 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5246
5247 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5248 image);
5249 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5250 image);
5251 }
5252
5253 /* The Vulkan spec 1.1.98 says:
5254 *
5255 * "An execution dependency with only
5256 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5257 * will only prevent that stage from executing in subsequently
5258 * submitted commands. As this stage does not perform any actual
5259 * execution, this is not observable - in effect, it does not delay
5260 * processing of subsequent commands. Similarly an execution dependency
5261 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5262 * will effectively not wait for any prior commands to complete."
5263 */
5264 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5265 radv_stage_flush(cmd_buffer, info->srcStageMask);
5266 cmd_buffer->state.flush_bits |= src_flush_bits;
5267
5268 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5269 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5270
5271 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5272 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5273 SAMPLE_LOCATIONS_INFO_EXT);
5274 struct radv_sample_locations_state sample_locations = {};
5275
5276 if (sample_locs_info) {
5277 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5278 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5279 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5280 sample_locations.count = sample_locs_info->sampleLocationsCount;
5281 typed_memcpy(&sample_locations.locations[0],
5282 sample_locs_info->pSampleLocations,
5283 sample_locs_info->sampleLocationsCount);
5284 }
5285
5286 radv_handle_image_transition(cmd_buffer, image,
5287 pImageMemoryBarriers[i].oldLayout,
5288 pImageMemoryBarriers[i].newLayout,
5289 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5290 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5291 &pImageMemoryBarriers[i].subresourceRange,
5292 sample_locs_info ? &sample_locations : NULL);
5293 }
5294
5295 /* Make sure CP DMA is idle because the driver might have performed a
5296 * DMA operation for copying or filling buffers/images.
5297 */
5298 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5299 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5300 si_cp_dma_wait_for_idle(cmd_buffer);
5301
5302 cmd_buffer->state.flush_bits |= dst_flush_bits;
5303 }
5304
5305 void radv_CmdPipelineBarrier(
5306 VkCommandBuffer commandBuffer,
5307 VkPipelineStageFlags srcStageMask,
5308 VkPipelineStageFlags destStageMask,
5309 VkBool32 byRegion,
5310 uint32_t memoryBarrierCount,
5311 const VkMemoryBarrier* pMemoryBarriers,
5312 uint32_t bufferMemoryBarrierCount,
5313 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5314 uint32_t imageMemoryBarrierCount,
5315 const VkImageMemoryBarrier* pImageMemoryBarriers)
5316 {
5317 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5318 struct radv_barrier_info info;
5319
5320 info.eventCount = 0;
5321 info.pEvents = NULL;
5322 info.srcStageMask = srcStageMask;
5323 info.dstStageMask = destStageMask;
5324
5325 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5326 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5327 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5328 }
5329
5330
5331 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5332 struct radv_event *event,
5333 VkPipelineStageFlags stageMask,
5334 unsigned value)
5335 {
5336 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5337 uint64_t va = radv_buffer_get_va(event->bo);
5338
5339 si_emit_cache_flush(cmd_buffer);
5340
5341 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5342
5343 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5344
5345 /* Flags that only require a top-of-pipe event. */
5346 VkPipelineStageFlags top_of_pipe_flags =
5347 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5348
5349 /* Flags that only require a post-index-fetch event. */
5350 VkPipelineStageFlags post_index_fetch_flags =
5351 top_of_pipe_flags |
5352 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5353 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5354
5355 /* Make sure CP DMA is idle because the driver might have performed a
5356 * DMA operation for copying or filling buffers/images.
5357 */
5358 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5359 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5360 si_cp_dma_wait_for_idle(cmd_buffer);
5361
5362 /* TODO: Emit EOS events for syncing PS/CS stages. */
5363
5364 if (!(stageMask & ~top_of_pipe_flags)) {
5365 /* Just need to sync the PFP engine. */
5366 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5367 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5368 S_370_WR_CONFIRM(1) |
5369 S_370_ENGINE_SEL(V_370_PFP));
5370 radeon_emit(cs, va);
5371 radeon_emit(cs, va >> 32);
5372 radeon_emit(cs, value);
5373 } else if (!(stageMask & ~post_index_fetch_flags)) {
5374 /* Sync ME because PFP reads index and indirect buffers. */
5375 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5376 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5377 S_370_WR_CONFIRM(1) |
5378 S_370_ENGINE_SEL(V_370_ME));
5379 radeon_emit(cs, va);
5380 radeon_emit(cs, va >> 32);
5381 radeon_emit(cs, value);
5382 } else {
5383 /* Otherwise, sync all prior GPU work using an EOP event. */
5384 si_cs_emit_write_event_eop(cs,
5385 cmd_buffer->device->physical_device->rad_info.chip_class,
5386 radv_cmd_buffer_uses_mec(cmd_buffer),
5387 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5388 EOP_DATA_SEL_VALUE_32BIT, va, value,
5389 cmd_buffer->gfx9_eop_bug_va);
5390 }
5391
5392 assert(cmd_buffer->cs->cdw <= cdw_max);
5393 }
5394
5395 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5396 VkEvent _event,
5397 VkPipelineStageFlags stageMask)
5398 {
5399 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5400 RADV_FROM_HANDLE(radv_event, event, _event);
5401
5402 write_event(cmd_buffer, event, stageMask, 1);
5403 }
5404
5405 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5406 VkEvent _event,
5407 VkPipelineStageFlags stageMask)
5408 {
5409 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5410 RADV_FROM_HANDLE(radv_event, event, _event);
5411
5412 write_event(cmd_buffer, event, stageMask, 0);
5413 }
5414
5415 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5416 uint32_t eventCount,
5417 const VkEvent* pEvents,
5418 VkPipelineStageFlags srcStageMask,
5419 VkPipelineStageFlags dstStageMask,
5420 uint32_t memoryBarrierCount,
5421 const VkMemoryBarrier* pMemoryBarriers,
5422 uint32_t bufferMemoryBarrierCount,
5423 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5424 uint32_t imageMemoryBarrierCount,
5425 const VkImageMemoryBarrier* pImageMemoryBarriers)
5426 {
5427 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5428 struct radv_barrier_info info;
5429
5430 info.eventCount = eventCount;
5431 info.pEvents = pEvents;
5432 info.srcStageMask = 0;
5433
5434 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5435 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5436 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5437 }
5438
5439
5440 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5441 uint32_t deviceMask)
5442 {
5443 /* No-op */
5444 }
5445
5446 /* VK_EXT_conditional_rendering */
5447 void radv_CmdBeginConditionalRenderingEXT(
5448 VkCommandBuffer commandBuffer,
5449 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5450 {
5451 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5452 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5453 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5454 bool draw_visible = true;
5455 uint64_t pred_value = 0;
5456 uint64_t va, new_va;
5457 unsigned pred_offset;
5458
5459 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5460
5461 /* By default, if the 32-bit value at offset in buffer memory is zero,
5462 * then the rendering commands are discarded, otherwise they are
5463 * executed as normal. If the inverted flag is set, all commands are
5464 * discarded if the value is non zero.
5465 */
5466 if (pConditionalRenderingBegin->flags &
5467 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5468 draw_visible = false;
5469 }
5470
5471 si_emit_cache_flush(cmd_buffer);
5472
5473 /* From the Vulkan spec 1.1.107:
5474 *
5475 * "If the 32-bit value at offset in buffer memory is zero, then the
5476 * rendering commands are discarded, otherwise they are executed as
5477 * normal. If the value of the predicate in buffer memory changes while
5478 * conditional rendering is active, the rendering commands may be
5479 * discarded in an implementation-dependent way. Some implementations
5480 * may latch the value of the predicate upon beginning conditional
5481 * rendering while others may read it before every rendering command."
5482 *
5483 * But, the AMD hardware treats the predicate as a 64-bit value which
5484 * means we need a workaround in the driver. Luckily, it's not required
5485 * to support if the value changes when predication is active.
5486 *
5487 * The workaround is as follows:
5488 * 1) allocate a 64-value in the upload BO and initialize it to 0
5489 * 2) copy the 32-bit predicate value to the upload BO
5490 * 3) use the new allocated VA address for predication
5491 *
5492 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5493 * in ME (+ sync PFP) instead of PFP.
5494 */
5495 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5496
5497 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5498
5499 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5500 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5501 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5502 COPY_DATA_WR_CONFIRM);
5503 radeon_emit(cs, va);
5504 radeon_emit(cs, va >> 32);
5505 radeon_emit(cs, new_va);
5506 radeon_emit(cs, new_va >> 32);
5507
5508 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5509 radeon_emit(cs, 0);
5510
5511 /* Enable predication for this command buffer. */
5512 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5513 cmd_buffer->state.predicating = true;
5514
5515 /* Store conditional rendering user info. */
5516 cmd_buffer->state.predication_type = draw_visible;
5517 cmd_buffer->state.predication_va = new_va;
5518 }
5519
5520 void radv_CmdEndConditionalRenderingEXT(
5521 VkCommandBuffer commandBuffer)
5522 {
5523 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5524
5525 /* Disable predication for this command buffer. */
5526 si_emit_set_predication_state(cmd_buffer, false, 0);
5527 cmd_buffer->state.predicating = false;
5528
5529 /* Reset conditional rendering user info. */
5530 cmd_buffer->state.predication_type = -1;
5531 cmd_buffer->state.predication_va = 0;
5532 }
5533
5534 /* VK_EXT_transform_feedback */
5535 void radv_CmdBindTransformFeedbackBuffersEXT(
5536 VkCommandBuffer commandBuffer,
5537 uint32_t firstBinding,
5538 uint32_t bindingCount,
5539 const VkBuffer* pBuffers,
5540 const VkDeviceSize* pOffsets,
5541 const VkDeviceSize* pSizes)
5542 {
5543 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5544 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5545 uint8_t enabled_mask = 0;
5546
5547 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5548 for (uint32_t i = 0; i < bindingCount; i++) {
5549 uint32_t idx = firstBinding + i;
5550
5551 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5552 sb[idx].offset = pOffsets[i];
5553 sb[idx].size = pSizes[i];
5554
5555 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5556 sb[idx].buffer->bo);
5557
5558 enabled_mask |= 1 << idx;
5559 }
5560
5561 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5562
5563 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5564 }
5565
5566 static void
5567 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5568 {
5569 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5570 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5571
5572 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5573 radeon_emit(cs,
5574 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5575 S_028B94_RAST_STREAM(0) |
5576 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5577 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5578 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5579 radeon_emit(cs, so->hw_enabled_mask &
5580 so->enabled_stream_buffers_mask);
5581
5582 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5583 }
5584
5585 static void
5586 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5587 {
5588 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5589 bool old_streamout_enabled = so->streamout_enabled;
5590 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5591
5592 so->streamout_enabled = enable;
5593
5594 so->hw_enabled_mask = so->enabled_mask |
5595 (so->enabled_mask << 4) |
5596 (so->enabled_mask << 8) |
5597 (so->enabled_mask << 12);
5598
5599 if ((old_streamout_enabled != so->streamout_enabled) ||
5600 (old_hw_enabled_mask != so->hw_enabled_mask))
5601 radv_emit_streamout_enable(cmd_buffer);
5602 }
5603
5604 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5605 {
5606 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5607 unsigned reg_strmout_cntl;
5608
5609 /* The register is at different places on different ASICs. */
5610 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5611 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5612 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5613 } else {
5614 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5615 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5616 }
5617
5618 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5619 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5620
5621 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5622 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5623 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5624 radeon_emit(cs, 0);
5625 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5626 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5627 radeon_emit(cs, 4); /* poll interval */
5628 }
5629
5630 void radv_CmdBeginTransformFeedbackEXT(
5631 VkCommandBuffer commandBuffer,
5632 uint32_t firstCounterBuffer,
5633 uint32_t counterBufferCount,
5634 const VkBuffer* pCounterBuffers,
5635 const VkDeviceSize* pCounterBufferOffsets)
5636 {
5637 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5638 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5639 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5640 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5641 uint32_t i;
5642
5643 radv_flush_vgt_streamout(cmd_buffer);
5644
5645 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5646 for_each_bit(i, so->enabled_mask) {
5647 int32_t counter_buffer_idx = i - firstCounterBuffer;
5648 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5649 counter_buffer_idx = -1;
5650
5651 /* AMD GCN binds streamout buffers as shader resources.
5652 * VGT only counts primitives and tells the shader through
5653 * SGPRs what to do.
5654 */
5655 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5656 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5657 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5658
5659 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5660
5661 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5662 /* The array of counter buffers is optional. */
5663 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5664 uint64_t va = radv_buffer_get_va(buffer->bo);
5665
5666 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5667
5668 /* Append */
5669 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5670 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5671 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5672 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5673 radeon_emit(cs, 0); /* unused */
5674 radeon_emit(cs, 0); /* unused */
5675 radeon_emit(cs, va); /* src address lo */
5676 radeon_emit(cs, va >> 32); /* src address hi */
5677
5678 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5679 } else {
5680 /* Start from the beginning. */
5681 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5682 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5683 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5684 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5685 radeon_emit(cs, 0); /* unused */
5686 radeon_emit(cs, 0); /* unused */
5687 radeon_emit(cs, 0); /* unused */
5688 radeon_emit(cs, 0); /* unused */
5689 }
5690 }
5691
5692 radv_set_streamout_enable(cmd_buffer, true);
5693 }
5694
5695 void radv_CmdEndTransformFeedbackEXT(
5696 VkCommandBuffer commandBuffer,
5697 uint32_t firstCounterBuffer,
5698 uint32_t counterBufferCount,
5699 const VkBuffer* pCounterBuffers,
5700 const VkDeviceSize* pCounterBufferOffsets)
5701 {
5702 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5703 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5704 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5705 uint32_t i;
5706
5707 radv_flush_vgt_streamout(cmd_buffer);
5708
5709 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5710 for_each_bit(i, so->enabled_mask) {
5711 int32_t counter_buffer_idx = i - firstCounterBuffer;
5712 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5713 counter_buffer_idx = -1;
5714
5715 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5716 /* The array of counters buffer is optional. */
5717 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5718 uint64_t va = radv_buffer_get_va(buffer->bo);
5719
5720 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5721
5722 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5723 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5724 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5725 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5726 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5727 radeon_emit(cs, va); /* dst address lo */
5728 radeon_emit(cs, va >> 32); /* dst address hi */
5729 radeon_emit(cs, 0); /* unused */
5730 radeon_emit(cs, 0); /* unused */
5731
5732 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5733 }
5734
5735 /* Deactivate transform feedback by zeroing the buffer size.
5736 * The counters (primitives generated, primitives emitted) may
5737 * be enabled even if there is not buffer bound. This ensures
5738 * that the primitives-emitted query won't increment.
5739 */
5740 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5741
5742 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5743 }
5744
5745 radv_set_streamout_enable(cmd_buffer, false);
5746 }
5747
5748 void radv_CmdDrawIndirectByteCountEXT(
5749 VkCommandBuffer commandBuffer,
5750 uint32_t instanceCount,
5751 uint32_t firstInstance,
5752 VkBuffer _counterBuffer,
5753 VkDeviceSize counterBufferOffset,
5754 uint32_t counterOffset,
5755 uint32_t vertexStride)
5756 {
5757 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5758 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5759 struct radv_draw_info info = {};
5760
5761 info.instance_count = instanceCount;
5762 info.first_instance = firstInstance;
5763 info.strmout_buffer = counterBuffer;
5764 info.strmout_buffer_offset = counterBufferOffset;
5765 info.stride = vertexStride;
5766
5767 radv_draw(cmd_buffer, &info);
5768 }
5769
5770 /* VK_AMD_buffer_marker */
5771 void radv_CmdWriteBufferMarkerAMD(
5772 VkCommandBuffer commandBuffer,
5773 VkPipelineStageFlagBits pipelineStage,
5774 VkBuffer dstBuffer,
5775 VkDeviceSize dstOffset,
5776 uint32_t marker)
5777 {
5778 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5779 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
5780 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5781 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
5782
5783 si_emit_cache_flush(cmd_buffer);
5784
5785 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
5786 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5787 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
5788 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5789 COPY_DATA_WR_CONFIRM);
5790 radeon_emit(cs, marker);
5791 radeon_emit(cs, 0);
5792 radeon_emit(cs, va);
5793 radeon_emit(cs, va >> 32);
5794 } else {
5795 si_cs_emit_write_event_eop(cs,
5796 cmd_buffer->device->physical_device->rad_info.chip_class,
5797 radv_cmd_buffer_uses_mec(cmd_buffer),
5798 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5799 EOP_DATA_SEL_VALUE_32BIT,
5800 va, marker,
5801 cmd_buffer->gfx9_eop_bug_va);
5802 }
5803 }