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radv: add radv_cmd_buffer_begin_subpass() helper
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range);
61
62 const struct radv_dynamic_state default_dynamic_state = {
63 .viewport = {
64 .count = 0,
65 },
66 .scissor = {
67 .count = 0,
68 },
69 .line_width = 1.0f,
70 .depth_bias = {
71 .bias = 0.0f,
72 .clamp = 0.0f,
73 .slope = 0.0f,
74 },
75 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
76 .depth_bounds = {
77 .min = 0.0f,
78 .max = 1.0f,
79 },
80 .stencil_compare_mask = {
81 .front = ~0u,
82 .back = ~0u,
83 },
84 .stencil_write_mask = {
85 .front = ~0u,
86 .back = ~0u,
87 },
88 .stencil_reference = {
89 .front = 0u,
90 .back = 0u,
91 },
92 };
93
94 static void
95 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
96 const struct radv_dynamic_state *src)
97 {
98 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
99 uint32_t copy_mask = src->mask;
100 uint32_t dest_mask = 0;
101
102 /* Make sure to copy the number of viewports/scissors because they can
103 * only be specified at pipeline creation time.
104 */
105 dest->viewport.count = src->viewport.count;
106 dest->scissor.count = src->scissor.count;
107 dest->discard_rectangle.count = src->discard_rectangle.count;
108
109 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
110 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
111 src->viewport.count * sizeof(VkViewport))) {
112 typed_memcpy(dest->viewport.viewports,
113 src->viewport.viewports,
114 src->viewport.count);
115 dest_mask |= RADV_DYNAMIC_VIEWPORT;
116 }
117 }
118
119 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
120 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
121 src->scissor.count * sizeof(VkRect2D))) {
122 typed_memcpy(dest->scissor.scissors,
123 src->scissor.scissors, src->scissor.count);
124 dest_mask |= RADV_DYNAMIC_SCISSOR;
125 }
126 }
127
128 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
129 if (dest->line_width != src->line_width) {
130 dest->line_width = src->line_width;
131 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
132 }
133 }
134
135 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
136 if (memcmp(&dest->depth_bias, &src->depth_bias,
137 sizeof(src->depth_bias))) {
138 dest->depth_bias = src->depth_bias;
139 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
144 if (memcmp(&dest->blend_constants, &src->blend_constants,
145 sizeof(src->blend_constants))) {
146 typed_memcpy(dest->blend_constants,
147 src->blend_constants, 4);
148 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
149 }
150 }
151
152 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
153 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
154 sizeof(src->depth_bounds))) {
155 dest->depth_bounds = src->depth_bounds;
156 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
161 if (memcmp(&dest->stencil_compare_mask,
162 &src->stencil_compare_mask,
163 sizeof(src->stencil_compare_mask))) {
164 dest->stencil_compare_mask = src->stencil_compare_mask;
165 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
166 }
167 }
168
169 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
170 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
171 sizeof(src->stencil_write_mask))) {
172 dest->stencil_write_mask = src->stencil_write_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
178 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
179 sizeof(src->stencil_reference))) {
180 dest->stencil_reference = src->stencil_reference;
181 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
186 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
187 src->discard_rectangle.count * sizeof(VkRect2D))) {
188 typed_memcpy(dest->discard_rectangle.rectangles,
189 src->discard_rectangle.rectangles,
190 src->discard_rectangle.count);
191 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
192 }
193 }
194
195 cmd_buffer->state.dirty |= dest_mask;
196 }
197
198 static void
199 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
200 struct radv_pipeline *pipeline)
201 {
202 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
203 struct radv_shader_info *info;
204
205 if (!pipeline->streamout_shader)
206 return;
207
208 info = &pipeline->streamout_shader->info.info;
209 for (int i = 0; i < MAX_SO_BUFFERS; i++)
210 so->stride_in_dw[i] = info->so.strides[i];
211
212 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
213 }
214
215 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
216 {
217 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
218 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
219 }
220
221 enum ring_type radv_queue_family_to_ring(int f) {
222 switch (f) {
223 case RADV_QUEUE_GENERAL:
224 return RING_GFX;
225 case RADV_QUEUE_COMPUTE:
226 return RING_COMPUTE;
227 case RADV_QUEUE_TRANSFER:
228 return RING_DMA;
229 default:
230 unreachable("Unknown queue family");
231 }
232 }
233
234 static VkResult radv_create_cmd_buffer(
235 struct radv_device * device,
236 struct radv_cmd_pool * pool,
237 VkCommandBufferLevel level,
238 VkCommandBuffer* pCommandBuffer)
239 {
240 struct radv_cmd_buffer *cmd_buffer;
241 unsigned ring;
242 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
243 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
244 if (cmd_buffer == NULL)
245 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
246
247 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
248 cmd_buffer->device = device;
249 cmd_buffer->pool = pool;
250 cmd_buffer->level = level;
251
252 if (pool) {
253 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
254 cmd_buffer->queue_family_index = pool->queue_family_index;
255
256 } else {
257 /* Init the pool_link so we can safely call list_del when we destroy
258 * the command buffer
259 */
260 list_inithead(&cmd_buffer->pool_link);
261 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
262 }
263
264 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
265
266 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
267 if (!cmd_buffer->cs) {
268 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
269 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
270 }
271
272 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
273
274 list_inithead(&cmd_buffer->upload.list);
275
276 return VK_SUCCESS;
277 }
278
279 static void
280 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
281 {
282 list_del(&cmd_buffer->pool_link);
283
284 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
285 &cmd_buffer->upload.list, list) {
286 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
287 list_del(&up->list);
288 free(up);
289 }
290
291 if (cmd_buffer->upload.upload_bo)
292 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
293 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
294
295 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
296 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
297
298 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
299 }
300
301 static VkResult
302 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
303 {
304
305 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
306
307 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
308 &cmd_buffer->upload.list, list) {
309 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
310 list_del(&up->list);
311 free(up);
312 }
313
314 cmd_buffer->push_constant_stages = 0;
315 cmd_buffer->scratch_size_needed = 0;
316 cmd_buffer->compute_scratch_size_needed = 0;
317 cmd_buffer->esgs_ring_size_needed = 0;
318 cmd_buffer->gsvs_ring_size_needed = 0;
319 cmd_buffer->tess_rings_needed = false;
320 cmd_buffer->sample_positions_needed = false;
321
322 if (cmd_buffer->upload.upload_bo)
323 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
324 cmd_buffer->upload.upload_bo);
325 cmd_buffer->upload.offset = 0;
326
327 cmd_buffer->record_result = VK_SUCCESS;
328
329 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
330 cmd_buffer->descriptors[i].dirty = 0;
331 cmd_buffer->descriptors[i].valid = 0;
332 cmd_buffer->descriptors[i].push_dirty = false;
333 }
334
335 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
336 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
337 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
338 unsigned fence_offset, eop_bug_offset;
339 void *fence_ptr;
340
341 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0, &fence_offset,
342 &fence_ptr);
343 cmd_buffer->gfx9_fence_va =
344 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
345 cmd_buffer->gfx9_fence_va += fence_offset;
346
347 /* Allocate a buffer for the EOP bug on GFX9. */
348 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
349 &eop_bug_offset, &fence_ptr);
350 cmd_buffer->gfx9_eop_bug_va =
351 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
352 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
353 }
354
355 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
356
357 return cmd_buffer->record_result;
358 }
359
360 static bool
361 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
362 uint64_t min_needed)
363 {
364 uint64_t new_size;
365 struct radeon_winsys_bo *bo;
366 struct radv_cmd_buffer_upload *upload;
367 struct radv_device *device = cmd_buffer->device;
368
369 new_size = MAX2(min_needed, 16 * 1024);
370 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
371
372 bo = device->ws->buffer_create(device->ws,
373 new_size, 4096,
374 RADEON_DOMAIN_GTT,
375 RADEON_FLAG_CPU_ACCESS|
376 RADEON_FLAG_NO_INTERPROCESS_SHARING |
377 RADEON_FLAG_32BIT,
378 RADV_BO_PRIORITY_UPLOAD_BUFFER);
379
380 if (!bo) {
381 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
382 return false;
383 }
384
385 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
386 if (cmd_buffer->upload.upload_bo) {
387 upload = malloc(sizeof(*upload));
388
389 if (!upload) {
390 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
391 device->ws->buffer_destroy(bo);
392 return false;
393 }
394
395 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
396 list_add(&upload->list, &cmd_buffer->upload.list);
397 }
398
399 cmd_buffer->upload.upload_bo = bo;
400 cmd_buffer->upload.size = new_size;
401 cmd_buffer->upload.offset = 0;
402 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
403
404 if (!cmd_buffer->upload.map) {
405 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
406 return false;
407 }
408
409 return true;
410 }
411
412 bool
413 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
414 unsigned size,
415 unsigned alignment,
416 unsigned *out_offset,
417 void **ptr)
418 {
419 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
420 if (offset + size > cmd_buffer->upload.size) {
421 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
422 return false;
423 offset = 0;
424 }
425
426 *out_offset = offset;
427 *ptr = cmd_buffer->upload.map + offset;
428
429 cmd_buffer->upload.offset = offset + size;
430 return true;
431 }
432
433 bool
434 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
435 unsigned size, unsigned alignment,
436 const void *data, unsigned *out_offset)
437 {
438 uint8_t *ptr;
439
440 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
441 out_offset, (void **)&ptr))
442 return false;
443
444 if (ptr)
445 memcpy(ptr, data, size);
446
447 return true;
448 }
449
450 static void
451 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
452 unsigned count, const uint32_t *data)
453 {
454 struct radeon_cmdbuf *cs = cmd_buffer->cs;
455
456 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
457
458 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
459 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
460 S_370_WR_CONFIRM(1) |
461 S_370_ENGINE_SEL(V_370_ME));
462 radeon_emit(cs, va);
463 radeon_emit(cs, va >> 32);
464 radeon_emit_array(cs, data, count);
465 }
466
467 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
468 {
469 struct radv_device *device = cmd_buffer->device;
470 struct radeon_cmdbuf *cs = cmd_buffer->cs;
471 uint64_t va;
472
473 va = radv_buffer_get_va(device->trace_bo);
474 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
475 va += 4;
476
477 ++cmd_buffer->state.trace_id;
478 radv_emit_write_data_packet(cmd_buffer, va, 1,
479 &cmd_buffer->state.trace_id);
480
481 radeon_check_space(cmd_buffer->device->ws, cs, 2);
482
483 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
484 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
485 }
486
487 static void
488 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
489 enum radv_cmd_flush_bits flags)
490 {
491 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
492 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
493 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
494
495 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
496
497 /* Force wait for graphics or compute engines to be idle. */
498 si_cs_emit_cache_flush(cmd_buffer->cs,
499 cmd_buffer->device->physical_device->rad_info.chip_class,
500 &cmd_buffer->gfx9_fence_idx,
501 cmd_buffer->gfx9_fence_va,
502 radv_cmd_buffer_uses_mec(cmd_buffer),
503 flags, cmd_buffer->gfx9_eop_bug_va);
504 }
505
506 if (unlikely(cmd_buffer->device->trace_bo))
507 radv_cmd_buffer_trace_emit(cmd_buffer);
508 }
509
510 static void
511 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
512 struct radv_pipeline *pipeline, enum ring_type ring)
513 {
514 struct radv_device *device = cmd_buffer->device;
515 uint32_t data[2];
516 uint64_t va;
517
518 va = radv_buffer_get_va(device->trace_bo);
519
520 switch (ring) {
521 case RING_GFX:
522 va += 8;
523 break;
524 case RING_COMPUTE:
525 va += 16;
526 break;
527 default:
528 assert(!"invalid ring type");
529 }
530
531 data[0] = (uintptr_t)pipeline;
532 data[1] = (uintptr_t)pipeline >> 32;
533
534 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
535 }
536
537 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
538 VkPipelineBindPoint bind_point,
539 struct radv_descriptor_set *set,
540 unsigned idx)
541 {
542 struct radv_descriptor_state *descriptors_state =
543 radv_get_descriptors_state(cmd_buffer, bind_point);
544
545 descriptors_state->sets[idx] = set;
546
547 descriptors_state->valid |= (1u << idx); /* active descriptors */
548 descriptors_state->dirty |= (1u << idx);
549 }
550
551 static void
552 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
553 VkPipelineBindPoint bind_point)
554 {
555 struct radv_descriptor_state *descriptors_state =
556 radv_get_descriptors_state(cmd_buffer, bind_point);
557 struct radv_device *device = cmd_buffer->device;
558 uint32_t data[MAX_SETS * 2] = {};
559 uint64_t va;
560 unsigned i;
561 va = radv_buffer_get_va(device->trace_bo) + 24;
562
563 for_each_bit(i, descriptors_state->valid) {
564 struct radv_descriptor_set *set = descriptors_state->sets[i];
565 data[i * 2] = (uintptr_t)set;
566 data[i * 2 + 1] = (uintptr_t)set >> 32;
567 }
568
569 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
570 }
571
572 struct radv_userdata_info *
573 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
574 gl_shader_stage stage,
575 int idx)
576 {
577 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
578 return &shader->info.user_sgprs_locs.shader_data[idx];
579 }
580
581 static void
582 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
583 struct radv_pipeline *pipeline,
584 gl_shader_stage stage,
585 int idx, uint64_t va)
586 {
587 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
588 uint32_t base_reg = pipeline->user_data_0[stage];
589 if (loc->sgpr_idx == -1)
590 return;
591
592 assert(loc->num_sgprs == 1);
593
594 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
595 base_reg + loc->sgpr_idx * 4, va, false);
596 }
597
598 static void
599 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
600 struct radv_pipeline *pipeline,
601 struct radv_descriptor_state *descriptors_state,
602 gl_shader_stage stage)
603 {
604 struct radv_device *device = cmd_buffer->device;
605 struct radeon_cmdbuf *cs = cmd_buffer->cs;
606 uint32_t sh_base = pipeline->user_data_0[stage];
607 struct radv_userdata_locations *locs =
608 &pipeline->shaders[stage]->info.user_sgprs_locs;
609 unsigned mask = locs->descriptor_sets_enabled;
610
611 mask &= descriptors_state->dirty & descriptors_state->valid;
612
613 while (mask) {
614 int start, count;
615
616 u_bit_scan_consecutive_range(&mask, &start, &count);
617
618 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
619 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
620
621 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
622 for (int i = 0; i < count; i++) {
623 struct radv_descriptor_set *set =
624 descriptors_state->sets[start + i];
625
626 radv_emit_shader_pointer_body(device, cs, set->va, true);
627 }
628 }
629 }
630
631 static void
632 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
633 struct radv_pipeline *pipeline)
634 {
635 int num_samples = pipeline->graphics.ms.num_samples;
636 struct radv_multisample_state *ms = &pipeline->graphics.ms;
637 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
638
639 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
640 cmd_buffer->sample_positions_needed = true;
641
642 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
643 return;
644
645 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
646 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
647 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
648
649 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
650
651 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
652
653 /* GFX9: Flush DFSM when the AA mode changes. */
654 if (cmd_buffer->device->dfsm_allowed) {
655 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
656 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
657 }
658
659 cmd_buffer->state.context_roll_without_scissor_emitted = true;
660 }
661
662 static void
663 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
664 struct radv_shader_variant *shader)
665 {
666 uint64_t va;
667
668 if (!shader)
669 return;
670
671 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
672
673 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
674 }
675
676 static void
677 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
678 struct radv_pipeline *pipeline,
679 bool vertex_stage_only)
680 {
681 struct radv_cmd_state *state = &cmd_buffer->state;
682 uint32_t mask = state->prefetch_L2_mask;
683
684 if (vertex_stage_only) {
685 /* Fast prefetch path for starting draws as soon as possible.
686 */
687 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
688 RADV_PREFETCH_VBO_DESCRIPTORS);
689 }
690
691 if (mask & RADV_PREFETCH_VS)
692 radv_emit_shader_prefetch(cmd_buffer,
693 pipeline->shaders[MESA_SHADER_VERTEX]);
694
695 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
696 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
697
698 if (mask & RADV_PREFETCH_TCS)
699 radv_emit_shader_prefetch(cmd_buffer,
700 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
701
702 if (mask & RADV_PREFETCH_TES)
703 radv_emit_shader_prefetch(cmd_buffer,
704 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
705
706 if (mask & RADV_PREFETCH_GS) {
707 radv_emit_shader_prefetch(cmd_buffer,
708 pipeline->shaders[MESA_SHADER_GEOMETRY]);
709 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
710 }
711
712 if (mask & RADV_PREFETCH_PS)
713 radv_emit_shader_prefetch(cmd_buffer,
714 pipeline->shaders[MESA_SHADER_FRAGMENT]);
715
716 state->prefetch_L2_mask &= ~mask;
717 }
718
719 static void
720 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
721 {
722 if (!cmd_buffer->device->physical_device->rbplus_allowed)
723 return;
724
725 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
726 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
727 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
728
729 unsigned sx_ps_downconvert = 0;
730 unsigned sx_blend_opt_epsilon = 0;
731 unsigned sx_blend_opt_control = 0;
732
733 for (unsigned i = 0; i < subpass->color_count; ++i) {
734 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
735 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
736 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
737 continue;
738 }
739
740 int idx = subpass->color_attachments[i].attachment;
741 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
742
743 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
744 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
745 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
746 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
747
748 bool has_alpha, has_rgb;
749
750 /* Set if RGB and A are present. */
751 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
752
753 if (format == V_028C70_COLOR_8 ||
754 format == V_028C70_COLOR_16 ||
755 format == V_028C70_COLOR_32)
756 has_rgb = !has_alpha;
757 else
758 has_rgb = true;
759
760 /* Check the colormask and export format. */
761 if (!(colormask & 0x7))
762 has_rgb = false;
763 if (!(colormask & 0x8))
764 has_alpha = false;
765
766 if (spi_format == V_028714_SPI_SHADER_ZERO) {
767 has_rgb = false;
768 has_alpha = false;
769 }
770
771 /* Disable value checking for disabled channels. */
772 if (!has_rgb)
773 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
774 if (!has_alpha)
775 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
776
777 /* Enable down-conversion for 32bpp and smaller formats. */
778 switch (format) {
779 case V_028C70_COLOR_8:
780 case V_028C70_COLOR_8_8:
781 case V_028C70_COLOR_8_8_8_8:
782 /* For 1 and 2-channel formats, use the superset thereof. */
783 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
784 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
785 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
786 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
787 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
788 }
789 break;
790
791 case V_028C70_COLOR_5_6_5:
792 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
793 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
794 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
795 }
796 break;
797
798 case V_028C70_COLOR_1_5_5_5:
799 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
800 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
801 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
802 }
803 break;
804
805 case V_028C70_COLOR_4_4_4_4:
806 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
807 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
808 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
809 }
810 break;
811
812 case V_028C70_COLOR_32:
813 if (swap == V_028C70_SWAP_STD &&
814 spi_format == V_028714_SPI_SHADER_32_R)
815 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
816 else if (swap == V_028C70_SWAP_ALT_REV &&
817 spi_format == V_028714_SPI_SHADER_32_AR)
818 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
819 break;
820
821 case V_028C70_COLOR_16:
822 case V_028C70_COLOR_16_16:
823 /* For 1-channel formats, use the superset thereof. */
824 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
825 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
826 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
827 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
828 if (swap == V_028C70_SWAP_STD ||
829 swap == V_028C70_SWAP_STD_REV)
830 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
831 else
832 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
833 }
834 break;
835
836 case V_028C70_COLOR_10_11_11:
837 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
838 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
839 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
840 }
841 break;
842
843 case V_028C70_COLOR_2_10_10_10:
844 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
845 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
846 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
847 }
848 break;
849 }
850 }
851
852 for (unsigned i = subpass->color_count; i < 8; ++i) {
853 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
854 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
855 }
856 /* TODO: avoid redundantly setting context registers */
857 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
858 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
859 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
860 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
861
862 cmd_buffer->state.context_roll_without_scissor_emitted = true;
863 }
864
865 static void
866 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
867 {
868 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
869
870 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
871 return;
872
873 radv_update_multisample_state(cmd_buffer, pipeline);
874
875 cmd_buffer->scratch_size_needed =
876 MAX2(cmd_buffer->scratch_size_needed,
877 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
878
879 if (!cmd_buffer->state.emitted_pipeline ||
880 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
881 pipeline->graphics.can_use_guardband)
882 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
883
884 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
885
886 if (!cmd_buffer->state.emitted_pipeline ||
887 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
888 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
889 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
890 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
891 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
892 cmd_buffer->state.context_roll_without_scissor_emitted = true;
893 }
894
895 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
896 if (!pipeline->shaders[i])
897 continue;
898
899 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
900 pipeline->shaders[i]->bo);
901 }
902
903 if (radv_pipeline_has_gs(pipeline))
904 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
905 pipeline->gs_copy_shader->bo);
906
907 if (unlikely(cmd_buffer->device->trace_bo))
908 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
909
910 cmd_buffer->state.emitted_pipeline = pipeline;
911
912 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
913 }
914
915 static void
916 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
917 {
918 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
919 cmd_buffer->state.dynamic.viewport.viewports);
920 }
921
922 static void
923 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
924 {
925 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
926
927 si_write_scissors(cmd_buffer->cs, 0, count,
928 cmd_buffer->state.dynamic.scissor.scissors,
929 cmd_buffer->state.dynamic.viewport.viewports,
930 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
931
932 cmd_buffer->state.context_roll_without_scissor_emitted = false;
933 }
934
935 static void
936 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
937 {
938 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
939 return;
940
941 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
942 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
943 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
944 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
945 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
946 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
947 S_028214_BR_Y(rect.offset.y + rect.extent.height));
948 }
949 }
950
951 static void
952 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
953 {
954 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
955
956 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
957 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
958 }
959
960 static void
961 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
962 {
963 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
964
965 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
966 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
967 }
968
969 static void
970 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
971 {
972 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
973
974 radeon_set_context_reg_seq(cmd_buffer->cs,
975 R_028430_DB_STENCILREFMASK, 2);
976 radeon_emit(cmd_buffer->cs,
977 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
978 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
979 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
980 S_028430_STENCILOPVAL(1));
981 radeon_emit(cmd_buffer->cs,
982 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
983 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
984 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
985 S_028434_STENCILOPVAL_BF(1));
986 }
987
988 static void
989 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
990 {
991 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
992
993 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
994 fui(d->depth_bounds.min));
995 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
996 fui(d->depth_bounds.max));
997 }
998
999 static void
1000 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1001 {
1002 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1003 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1004 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1005
1006
1007 radeon_set_context_reg_seq(cmd_buffer->cs,
1008 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1009 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1010 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1011 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1012 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1013 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1014 }
1015
1016 static void
1017 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1018 int index,
1019 struct radv_attachment_info *att,
1020 struct radv_image *image,
1021 VkImageLayout layout)
1022 {
1023 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1024 struct radv_color_buffer_info *cb = &att->cb;
1025 uint32_t cb_color_info = cb->cb_color_info;
1026
1027 if (!radv_layout_dcc_compressed(image, layout,
1028 radv_image_queue_family_mask(image,
1029 cmd_buffer->queue_family_index,
1030 cmd_buffer->queue_family_index))) {
1031 cb_color_info &= C_028C70_DCC_ENABLE;
1032 }
1033
1034 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1035 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1036 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1037 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1038 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1039 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1040 radeon_emit(cmd_buffer->cs, cb_color_info);
1041 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1042 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1043 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1044 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1045 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1046 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1047
1048 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1049 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1050 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1051
1052 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1053 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1054 } else {
1055 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1056 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1057 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1058 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1059 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1060 radeon_emit(cmd_buffer->cs, cb_color_info);
1061 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1062 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1063 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1064 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1065 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1066 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1067
1068 if (is_vi) { /* DCC BASE */
1069 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1070 }
1071 }
1072
1073 if (radv_image_has_dcc(image)) {
1074 /* Drawing with DCC enabled also compresses colorbuffers. */
1075 radv_update_dcc_metadata(cmd_buffer, image, true);
1076 }
1077 }
1078
1079 static void
1080 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1081 struct radv_ds_buffer_info *ds,
1082 struct radv_image *image, VkImageLayout layout,
1083 bool requires_cond_exec)
1084 {
1085 uint32_t db_z_info = ds->db_z_info;
1086 uint32_t db_z_info_reg;
1087
1088 if (!radv_image_is_tc_compat_htile(image))
1089 return;
1090
1091 if (!radv_layout_has_htile(image, layout,
1092 radv_image_queue_family_mask(image,
1093 cmd_buffer->queue_family_index,
1094 cmd_buffer->queue_family_index))) {
1095 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1096 }
1097
1098 db_z_info &= C_028040_ZRANGE_PRECISION;
1099
1100 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1101 db_z_info_reg = R_028038_DB_Z_INFO;
1102 } else {
1103 db_z_info_reg = R_028040_DB_Z_INFO;
1104 }
1105
1106 /* When we don't know the last fast clear value we need to emit a
1107 * conditional packet that will eventually skip the following
1108 * SET_CONTEXT_REG packet.
1109 */
1110 if (requires_cond_exec) {
1111 uint64_t va = radv_buffer_get_va(image->bo);
1112 va += image->offset + image->tc_compat_zrange_offset;
1113
1114 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1115 radeon_emit(cmd_buffer->cs, va);
1116 radeon_emit(cmd_buffer->cs, va >> 32);
1117 radeon_emit(cmd_buffer->cs, 0);
1118 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1119 }
1120
1121 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1122 }
1123
1124 static void
1125 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1126 struct radv_ds_buffer_info *ds,
1127 struct radv_image *image,
1128 VkImageLayout layout)
1129 {
1130 uint32_t db_z_info = ds->db_z_info;
1131 uint32_t db_stencil_info = ds->db_stencil_info;
1132
1133 if (!radv_layout_has_htile(image, layout,
1134 radv_image_queue_family_mask(image,
1135 cmd_buffer->queue_family_index,
1136 cmd_buffer->queue_family_index))) {
1137 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1138 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1139 }
1140
1141 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1142 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1143
1144
1145 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1146 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1147 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1148 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1149 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1150
1151 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1152 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1153 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1154 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1155 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1156 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1157 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1158 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1159 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1160 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1161 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1162
1163 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1164 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1165 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1166 } else {
1167 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1168
1169 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1170 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1171 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1172 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1173 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1174 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1175 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1176 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1177 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1178 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1179
1180 }
1181
1182 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1183 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1184
1185 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1186 ds->pa_su_poly_offset_db_fmt_cntl);
1187 }
1188
1189 /**
1190 * Update the fast clear depth/stencil values if the image is bound as a
1191 * depth/stencil buffer.
1192 */
1193 static void
1194 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1195 struct radv_image *image,
1196 VkClearDepthStencilValue ds_clear_value,
1197 VkImageAspectFlags aspects)
1198 {
1199 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1200 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1201 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1202 struct radv_attachment_info *att;
1203 uint32_t att_idx;
1204
1205 if (!framebuffer || !subpass)
1206 return;
1207
1208 att_idx = subpass->depth_stencil_attachment.attachment;
1209 if (att_idx == VK_ATTACHMENT_UNUSED)
1210 return;
1211
1212 att = &framebuffer->attachments[att_idx];
1213 if (att->attachment->image != image)
1214 return;
1215
1216 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1217 radeon_emit(cs, ds_clear_value.stencil);
1218 radeon_emit(cs, fui(ds_clear_value.depth));
1219
1220 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1221 * only needed when clearing Z to 0.0.
1222 */
1223 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1224 ds_clear_value.depth == 0.0) {
1225 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1226
1227 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1228 layout, false);
1229 }
1230
1231 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1232 }
1233
1234 /**
1235 * Set the clear depth/stencil values to the image's metadata.
1236 */
1237 static void
1238 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1239 struct radv_image *image,
1240 VkClearDepthStencilValue ds_clear_value,
1241 VkImageAspectFlags aspects)
1242 {
1243 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1244 uint64_t va = radv_buffer_get_va(image->bo);
1245 unsigned reg_offset = 0, reg_count = 0;
1246
1247 va += image->offset + image->clear_value_offset;
1248
1249 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1250 ++reg_count;
1251 } else {
1252 ++reg_offset;
1253 va += 4;
1254 }
1255 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1256 ++reg_count;
1257
1258 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1259 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1260 S_370_WR_CONFIRM(1) |
1261 S_370_ENGINE_SEL(V_370_PFP));
1262 radeon_emit(cs, va);
1263 radeon_emit(cs, va >> 32);
1264 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1265 radeon_emit(cs, ds_clear_value.stencil);
1266 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1267 radeon_emit(cs, fui(ds_clear_value.depth));
1268 }
1269
1270 /**
1271 * Update the TC-compat metadata value for this image.
1272 */
1273 static void
1274 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1275 struct radv_image *image,
1276 uint32_t value)
1277 {
1278 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1279 uint64_t va = radv_buffer_get_va(image->bo);
1280 va += image->offset + image->tc_compat_zrange_offset;
1281
1282 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1283 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1284 S_370_WR_CONFIRM(1) |
1285 S_370_ENGINE_SEL(V_370_PFP));
1286 radeon_emit(cs, va);
1287 radeon_emit(cs, va >> 32);
1288 radeon_emit(cs, value);
1289 }
1290
1291 static void
1292 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1293 struct radv_image *image,
1294 VkClearDepthStencilValue ds_clear_value)
1295 {
1296 uint64_t va = radv_buffer_get_va(image->bo);
1297 va += image->offset + image->tc_compat_zrange_offset;
1298 uint32_t cond_val;
1299
1300 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1301 * depth clear value is 0.0f.
1302 */
1303 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1304
1305 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1306 }
1307
1308 /**
1309 * Update the clear depth/stencil values for this image.
1310 */
1311 void
1312 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1313 struct radv_image *image,
1314 VkClearDepthStencilValue ds_clear_value,
1315 VkImageAspectFlags aspects)
1316 {
1317 assert(radv_image_has_htile(image));
1318
1319 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1320
1321 if (radv_image_is_tc_compat_htile(image) &&
1322 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1323 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1324 ds_clear_value);
1325 }
1326
1327 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1328 aspects);
1329 }
1330
1331 /**
1332 * Load the clear depth/stencil values from the image's metadata.
1333 */
1334 static void
1335 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1336 struct radv_image *image)
1337 {
1338 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1339 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1340 uint64_t va = radv_buffer_get_va(image->bo);
1341 unsigned reg_offset = 0, reg_count = 0;
1342
1343 va += image->offset + image->clear_value_offset;
1344
1345 if (!radv_image_has_htile(image))
1346 return;
1347
1348 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1349 ++reg_count;
1350 } else {
1351 ++reg_offset;
1352 va += 4;
1353 }
1354 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1355 ++reg_count;
1356
1357 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1358
1359 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1360 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1361 radeon_emit(cs, va);
1362 radeon_emit(cs, va >> 32);
1363 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1364 radeon_emit(cs, reg_count);
1365 } else {
1366 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1367 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1368 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1369 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1370 radeon_emit(cs, va);
1371 radeon_emit(cs, va >> 32);
1372 radeon_emit(cs, reg >> 2);
1373 radeon_emit(cs, 0);
1374
1375 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1376 radeon_emit(cs, 0);
1377 }
1378 }
1379
1380 /*
1381 * With DCC some colors don't require CMASK elimination before being
1382 * used as a texture. This sets a predicate value to determine if the
1383 * cmask eliminate is required.
1384 */
1385 void
1386 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1387 struct radv_image *image, bool value)
1388 {
1389 uint64_t pred_val = value;
1390 uint64_t va = radv_buffer_get_va(image->bo);
1391 va += image->offset + image->fce_pred_offset;
1392
1393 assert(radv_image_has_dcc(image));
1394
1395 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1396 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1397 S_370_WR_CONFIRM(1) |
1398 S_370_ENGINE_SEL(V_370_PFP));
1399 radeon_emit(cmd_buffer->cs, va);
1400 radeon_emit(cmd_buffer->cs, va >> 32);
1401 radeon_emit(cmd_buffer->cs, pred_val);
1402 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1403 }
1404
1405 /**
1406 * Update the DCC predicate to reflect the compression state.
1407 */
1408 void
1409 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1410 struct radv_image *image, bool value)
1411 {
1412 uint64_t pred_val = value;
1413 uint64_t va = radv_buffer_get_va(image->bo);
1414 va += image->offset + image->dcc_pred_offset;
1415
1416 assert(radv_image_has_dcc(image));
1417
1418 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1419 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1420 S_370_WR_CONFIRM(1) |
1421 S_370_ENGINE_SEL(V_370_PFP));
1422 radeon_emit(cmd_buffer->cs, va);
1423 radeon_emit(cmd_buffer->cs, va >> 32);
1424 radeon_emit(cmd_buffer->cs, pred_val);
1425 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1426 }
1427
1428 /**
1429 * Update the fast clear color values if the image is bound as a color buffer.
1430 */
1431 static void
1432 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1433 struct radv_image *image,
1434 int cb_idx,
1435 uint32_t color_values[2])
1436 {
1437 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1438 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1439 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1440 struct radv_attachment_info *att;
1441 uint32_t att_idx;
1442
1443 if (!framebuffer || !subpass)
1444 return;
1445
1446 att_idx = subpass->color_attachments[cb_idx].attachment;
1447 if (att_idx == VK_ATTACHMENT_UNUSED)
1448 return;
1449
1450 att = &framebuffer->attachments[att_idx];
1451 if (att->attachment->image != image)
1452 return;
1453
1454 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1455 radeon_emit(cs, color_values[0]);
1456 radeon_emit(cs, color_values[1]);
1457
1458 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1459 }
1460
1461 /**
1462 * Set the clear color values to the image's metadata.
1463 */
1464 static void
1465 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1466 struct radv_image *image,
1467 uint32_t color_values[2])
1468 {
1469 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1470 uint64_t va = radv_buffer_get_va(image->bo);
1471
1472 va += image->offset + image->clear_value_offset;
1473
1474 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1475
1476 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1477 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1478 S_370_WR_CONFIRM(1) |
1479 S_370_ENGINE_SEL(V_370_PFP));
1480 radeon_emit(cs, va);
1481 radeon_emit(cs, va >> 32);
1482 radeon_emit(cs, color_values[0]);
1483 radeon_emit(cs, color_values[1]);
1484 }
1485
1486 /**
1487 * Update the clear color values for this image.
1488 */
1489 void
1490 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1491 struct radv_image *image,
1492 int cb_idx,
1493 uint32_t color_values[2])
1494 {
1495 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1496
1497 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1498
1499 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1500 color_values);
1501 }
1502
1503 /**
1504 * Load the clear color values from the image's metadata.
1505 */
1506 static void
1507 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1508 struct radv_image *image,
1509 int cb_idx)
1510 {
1511 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1512 uint64_t va = radv_buffer_get_va(image->bo);
1513
1514 va += image->offset + image->clear_value_offset;
1515
1516 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1517 return;
1518
1519 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1520
1521 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1522 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1523 radeon_emit(cs, va);
1524 radeon_emit(cs, va >> 32);
1525 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1526 radeon_emit(cs, 2);
1527 } else {
1528 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
1529 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1530 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1531 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1532 COPY_DATA_COUNT_SEL);
1533 radeon_emit(cs, va);
1534 radeon_emit(cs, va >> 32);
1535 radeon_emit(cs, reg >> 2);
1536 radeon_emit(cs, 0);
1537
1538 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1539 radeon_emit(cs, 0);
1540 }
1541 }
1542
1543 static void
1544 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1545 {
1546 int i;
1547 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1548 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1549 unsigned num_bpp64_colorbufs = 0;
1550
1551 /* this may happen for inherited secondary recording */
1552 if (!framebuffer)
1553 return;
1554
1555 for (i = 0; i < 8; ++i) {
1556 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1557 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1558 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1559 continue;
1560 }
1561
1562 int idx = subpass->color_attachments[i].attachment;
1563 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1564 struct radv_image *image = att->attachment->image;
1565 VkImageLayout layout = subpass->color_attachments[i].layout;
1566
1567 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1568
1569 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1570 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1571
1572 radv_load_color_clear_metadata(cmd_buffer, image, i);
1573
1574 if (image->surface.bpe >= 8)
1575 num_bpp64_colorbufs++;
1576 }
1577
1578 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1579 int idx = subpass->depth_stencil_attachment.attachment;
1580 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1581 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1582 struct radv_image *image = att->attachment->image;
1583 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1584 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1585 cmd_buffer->queue_family_index,
1586 cmd_buffer->queue_family_index);
1587 /* We currently don't support writing decompressed HTILE */
1588 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1589 radv_layout_is_htile_compressed(image, layout, queue_mask));
1590
1591 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1592
1593 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1594 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1595 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1596 }
1597 radv_load_ds_clear_metadata(cmd_buffer, image);
1598 } else {
1599 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1600 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1601 else
1602 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1603
1604 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1605 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1606 }
1607 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1608 S_028208_BR_X(framebuffer->width) |
1609 S_028208_BR_Y(framebuffer->height));
1610
1611 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1612 uint8_t watermark = 4; /* Default value for VI. */
1613
1614 /* For optimal DCC performance. */
1615 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1616 if (num_bpp64_colorbufs >= 5) {
1617 watermark = 8;
1618 } else {
1619 watermark = 6;
1620 }
1621 }
1622
1623 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1624 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1625 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1626 }
1627
1628 if (cmd_buffer->device->dfsm_allowed) {
1629 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1630 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1631 }
1632
1633 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1634 }
1635
1636 static void
1637 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1638 {
1639 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1640 struct radv_cmd_state *state = &cmd_buffer->state;
1641
1642 if (state->index_type != state->last_index_type) {
1643 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1644 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1645 2, state->index_type);
1646 } else {
1647 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1648 radeon_emit(cs, state->index_type);
1649 }
1650
1651 state->last_index_type = state->index_type;
1652 }
1653
1654 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1655 radeon_emit(cs, state->index_va);
1656 radeon_emit(cs, state->index_va >> 32);
1657
1658 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1659 radeon_emit(cs, state->max_index_count);
1660
1661 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1662 }
1663
1664 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1665 {
1666 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1667 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1668 uint32_t pa_sc_mode_cntl_1 =
1669 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1670 uint32_t db_count_control;
1671
1672 if(!cmd_buffer->state.active_occlusion_queries) {
1673 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1674 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1675 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1676 has_perfect_queries) {
1677 /* Re-enable out-of-order rasterization if the
1678 * bound pipeline supports it and if it's has
1679 * been disabled before starting any perfect
1680 * occlusion queries.
1681 */
1682 radeon_set_context_reg(cmd_buffer->cs,
1683 R_028A4C_PA_SC_MODE_CNTL_1,
1684 pa_sc_mode_cntl_1);
1685 }
1686 }
1687 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1688 } else {
1689 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1690 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1691
1692 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1693 db_count_control =
1694 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1695 S_028004_SAMPLE_RATE(sample_rate) |
1696 S_028004_ZPASS_ENABLE(1) |
1697 S_028004_SLICE_EVEN_ENABLE(1) |
1698 S_028004_SLICE_ODD_ENABLE(1);
1699
1700 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1701 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1702 has_perfect_queries) {
1703 /* If the bound pipeline has enabled
1704 * out-of-order rasterization, we should
1705 * disable it before starting any perfect
1706 * occlusion queries.
1707 */
1708 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1709
1710 radeon_set_context_reg(cmd_buffer->cs,
1711 R_028A4C_PA_SC_MODE_CNTL_1,
1712 pa_sc_mode_cntl_1);
1713 }
1714 } else {
1715 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1716 S_028004_SAMPLE_RATE(sample_rate);
1717 }
1718 }
1719
1720 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1721
1722 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1723 }
1724
1725 static void
1726 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1727 {
1728 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1729
1730 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1731 radv_emit_viewport(cmd_buffer);
1732
1733 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1734 !cmd_buffer->device->physical_device->has_scissor_bug)
1735 radv_emit_scissor(cmd_buffer);
1736
1737 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1738 radv_emit_line_width(cmd_buffer);
1739
1740 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1741 radv_emit_blend_constants(cmd_buffer);
1742
1743 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1744 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1745 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1746 radv_emit_stencil(cmd_buffer);
1747
1748 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1749 radv_emit_depth_bounds(cmd_buffer);
1750
1751 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1752 radv_emit_depth_bias(cmd_buffer);
1753
1754 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1755 radv_emit_discard_rectangle(cmd_buffer);
1756
1757 cmd_buffer->state.dirty &= ~states;
1758 }
1759
1760 static void
1761 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1762 VkPipelineBindPoint bind_point)
1763 {
1764 struct radv_descriptor_state *descriptors_state =
1765 radv_get_descriptors_state(cmd_buffer, bind_point);
1766 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1767 unsigned bo_offset;
1768
1769 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1770 set->mapped_ptr,
1771 &bo_offset))
1772 return;
1773
1774 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1775 set->va += bo_offset;
1776 }
1777
1778 static void
1779 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1780 VkPipelineBindPoint bind_point)
1781 {
1782 struct radv_descriptor_state *descriptors_state =
1783 radv_get_descriptors_state(cmd_buffer, bind_point);
1784 uint32_t size = MAX_SETS * 4;
1785 uint32_t offset;
1786 void *ptr;
1787
1788 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1789 256, &offset, &ptr))
1790 return;
1791
1792 for (unsigned i = 0; i < MAX_SETS; i++) {
1793 uint32_t *uptr = ((uint32_t *)ptr) + i;
1794 uint64_t set_va = 0;
1795 struct radv_descriptor_set *set = descriptors_state->sets[i];
1796 if (descriptors_state->valid & (1u << i))
1797 set_va = set->va;
1798 uptr[0] = set_va & 0xffffffff;
1799 }
1800
1801 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1802 va += offset;
1803
1804 if (cmd_buffer->state.pipeline) {
1805 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1806 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1807 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1808
1809 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1810 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1811 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1812
1813 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1814 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1815 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1816
1817 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1818 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1819 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1820
1821 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1822 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1823 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1824 }
1825
1826 if (cmd_buffer->state.compute_pipeline)
1827 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1828 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1829 }
1830
1831 static void
1832 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1833 VkShaderStageFlags stages)
1834 {
1835 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1836 VK_PIPELINE_BIND_POINT_COMPUTE :
1837 VK_PIPELINE_BIND_POINT_GRAPHICS;
1838 struct radv_descriptor_state *descriptors_state =
1839 radv_get_descriptors_state(cmd_buffer, bind_point);
1840 struct radv_cmd_state *state = &cmd_buffer->state;
1841 bool flush_indirect_descriptors;
1842
1843 if (!descriptors_state->dirty)
1844 return;
1845
1846 if (descriptors_state->push_dirty)
1847 radv_flush_push_descriptors(cmd_buffer, bind_point);
1848
1849 flush_indirect_descriptors =
1850 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1851 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1852 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1853 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1854
1855 if (flush_indirect_descriptors)
1856 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1857
1858 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1859 cmd_buffer->cs,
1860 MAX_SETS * MESA_SHADER_STAGES * 4);
1861
1862 if (cmd_buffer->state.pipeline) {
1863 radv_foreach_stage(stage, stages) {
1864 if (!cmd_buffer->state.pipeline->shaders[stage])
1865 continue;
1866
1867 radv_emit_descriptor_pointers(cmd_buffer,
1868 cmd_buffer->state.pipeline,
1869 descriptors_state, stage);
1870 }
1871 }
1872
1873 if (cmd_buffer->state.compute_pipeline &&
1874 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1875 radv_emit_descriptor_pointers(cmd_buffer,
1876 cmd_buffer->state.compute_pipeline,
1877 descriptors_state,
1878 MESA_SHADER_COMPUTE);
1879 }
1880
1881 descriptors_state->dirty = 0;
1882 descriptors_state->push_dirty = false;
1883
1884 assert(cmd_buffer->cs->cdw <= cdw_max);
1885
1886 if (unlikely(cmd_buffer->device->trace_bo))
1887 radv_save_descriptors(cmd_buffer, bind_point);
1888 }
1889
1890 static void
1891 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1892 VkShaderStageFlags stages)
1893 {
1894 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1895 ? cmd_buffer->state.compute_pipeline
1896 : cmd_buffer->state.pipeline;
1897 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1898 VK_PIPELINE_BIND_POINT_COMPUTE :
1899 VK_PIPELINE_BIND_POINT_GRAPHICS;
1900 struct radv_descriptor_state *descriptors_state =
1901 radv_get_descriptors_state(cmd_buffer, bind_point);
1902 struct radv_pipeline_layout *layout = pipeline->layout;
1903 struct radv_shader_variant *shader, *prev_shader;
1904 unsigned offset;
1905 void *ptr;
1906 uint64_t va;
1907
1908 stages &= cmd_buffer->push_constant_stages;
1909 if (!stages ||
1910 (!layout->push_constant_size && !layout->dynamic_offset_count))
1911 return;
1912
1913 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1914 16 * layout->dynamic_offset_count,
1915 256, &offset, &ptr))
1916 return;
1917
1918 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1919 memcpy((char*)ptr + layout->push_constant_size,
1920 descriptors_state->dynamic_buffers,
1921 16 * layout->dynamic_offset_count);
1922
1923 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1924 va += offset;
1925
1926 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1927 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1928
1929 prev_shader = NULL;
1930 radv_foreach_stage(stage, stages) {
1931 shader = radv_get_shader(pipeline, stage);
1932
1933 /* Avoid redundantly emitting the address for merged stages. */
1934 if (shader && shader != prev_shader) {
1935 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1936 AC_UD_PUSH_CONSTANTS, va);
1937
1938 prev_shader = shader;
1939 }
1940 }
1941
1942 cmd_buffer->push_constant_stages &= ~stages;
1943 assert(cmd_buffer->cs->cdw <= cdw_max);
1944 }
1945
1946 static void
1947 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1948 bool pipeline_is_dirty)
1949 {
1950 if ((pipeline_is_dirty ||
1951 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1952 cmd_buffer->state.pipeline->vertex_elements.count &&
1953 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1954 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1955 unsigned vb_offset;
1956 void *vb_ptr;
1957 uint32_t i = 0;
1958 uint32_t count = velems->count;
1959 uint64_t va;
1960
1961 /* allocate some descriptor state for vertex buffers */
1962 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1963 &vb_offset, &vb_ptr))
1964 return;
1965
1966 for (i = 0; i < count; i++) {
1967 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1968 uint32_t offset;
1969 int vb = velems->binding[i];
1970 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1971 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1972
1973 va = radv_buffer_get_va(buffer->bo);
1974
1975 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1976 va += offset + buffer->offset;
1977 desc[0] = va;
1978 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1979 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1980 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1981 else
1982 desc[2] = buffer->size - offset;
1983 desc[3] = velems->rsrc_word3[i];
1984 }
1985
1986 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1987 va += vb_offset;
1988
1989 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1990 AC_UD_VS_VERTEX_BUFFERS, va);
1991
1992 cmd_buffer->state.vb_va = va;
1993 cmd_buffer->state.vb_size = count * 16;
1994 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1995 }
1996 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1997 }
1998
1999 static void
2000 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2001 {
2002 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2003 struct radv_userdata_info *loc;
2004 uint32_t base_reg;
2005
2006 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2007 if (!radv_get_shader(pipeline, stage))
2008 continue;
2009
2010 loc = radv_lookup_user_sgpr(pipeline, stage,
2011 AC_UD_STREAMOUT_BUFFERS);
2012 if (loc->sgpr_idx == -1)
2013 continue;
2014
2015 base_reg = pipeline->user_data_0[stage];
2016
2017 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2018 base_reg + loc->sgpr_idx * 4, va, false);
2019 }
2020
2021 if (pipeline->gs_copy_shader) {
2022 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2023 if (loc->sgpr_idx != -1) {
2024 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2025
2026 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2027 base_reg + loc->sgpr_idx * 4, va, false);
2028 }
2029 }
2030 }
2031
2032 static void
2033 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2034 {
2035 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2036 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2037 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2038 unsigned so_offset;
2039 void *so_ptr;
2040 uint64_t va;
2041
2042 /* Allocate some descriptor state for streamout buffers. */
2043 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2044 MAX_SO_BUFFERS * 16, 256,
2045 &so_offset, &so_ptr))
2046 return;
2047
2048 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2049 struct radv_buffer *buffer = sb[i].buffer;
2050 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2051
2052 if (!(so->enabled_mask & (1 << i)))
2053 continue;
2054
2055 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2056
2057 va += sb[i].offset;
2058
2059 /* Set the descriptor.
2060 *
2061 * On VI, the format must be non-INVALID, otherwise
2062 * the buffer will be considered not bound and store
2063 * instructions will be no-ops.
2064 */
2065 desc[0] = va;
2066 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2067 desc[2] = 0xffffffff;
2068 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2069 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2070 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2071 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2072 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2073 }
2074
2075 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2076 va += so_offset;
2077
2078 radv_emit_streamout_buffers(cmd_buffer, va);
2079 }
2080
2081 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2082 }
2083
2084 static void
2085 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2086 {
2087 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2088 radv_flush_streamout_descriptors(cmd_buffer);
2089 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2090 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2091 }
2092
2093 struct radv_draw_info {
2094 /**
2095 * Number of vertices.
2096 */
2097 uint32_t count;
2098
2099 /**
2100 * Index of the first vertex.
2101 */
2102 int32_t vertex_offset;
2103
2104 /**
2105 * First instance id.
2106 */
2107 uint32_t first_instance;
2108
2109 /**
2110 * Number of instances.
2111 */
2112 uint32_t instance_count;
2113
2114 /**
2115 * First index (indexed draws only).
2116 */
2117 uint32_t first_index;
2118
2119 /**
2120 * Whether it's an indexed draw.
2121 */
2122 bool indexed;
2123
2124 /**
2125 * Indirect draw parameters resource.
2126 */
2127 struct radv_buffer *indirect;
2128 uint64_t indirect_offset;
2129 uint32_t stride;
2130
2131 /**
2132 * Draw count parameters resource.
2133 */
2134 struct radv_buffer *count_buffer;
2135 uint64_t count_buffer_offset;
2136
2137 /**
2138 * Stream output parameters resource.
2139 */
2140 struct radv_buffer *strmout_buffer;
2141 uint64_t strmout_buffer_offset;
2142 };
2143
2144 static void
2145 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2146 const struct radv_draw_info *draw_info)
2147 {
2148 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2149 struct radv_cmd_state *state = &cmd_buffer->state;
2150 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2151 uint32_t ia_multi_vgt_param;
2152 int32_t primitive_reset_en;
2153
2154 /* Draw state. */
2155 ia_multi_vgt_param =
2156 si_get_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2157 draw_info->indirect,
2158 draw_info->indirect ? 0 : draw_info->count);
2159
2160 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2161 if (info->chip_class >= GFX9) {
2162 radeon_set_uconfig_reg_idx(cs,
2163 R_030960_IA_MULTI_VGT_PARAM,
2164 4, ia_multi_vgt_param);
2165 } else if (info->chip_class >= CIK) {
2166 radeon_set_context_reg_idx(cs,
2167 R_028AA8_IA_MULTI_VGT_PARAM,
2168 1, ia_multi_vgt_param);
2169 } else {
2170 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2171 ia_multi_vgt_param);
2172 }
2173 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2174 }
2175
2176 /* Primitive restart. */
2177 primitive_reset_en =
2178 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2179
2180 if (primitive_reset_en != state->last_primitive_reset_en) {
2181 state->last_primitive_reset_en = primitive_reset_en;
2182 if (info->chip_class >= GFX9) {
2183 radeon_set_uconfig_reg(cs,
2184 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2185 primitive_reset_en);
2186 } else {
2187 radeon_set_context_reg(cs,
2188 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2189 primitive_reset_en);
2190 }
2191 }
2192
2193 if (primitive_reset_en) {
2194 uint32_t primitive_reset_index =
2195 state->index_type ? 0xffffffffu : 0xffffu;
2196
2197 if (primitive_reset_index != state->last_primitive_reset_index) {
2198 radeon_set_context_reg(cs,
2199 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2200 primitive_reset_index);
2201 state->last_primitive_reset_index = primitive_reset_index;
2202 }
2203 }
2204
2205 if (draw_info->strmout_buffer) {
2206 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2207
2208 va += draw_info->strmout_buffer->offset +
2209 draw_info->strmout_buffer_offset;
2210
2211 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2212 draw_info->stride);
2213
2214 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2215 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2216 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2217 COPY_DATA_WR_CONFIRM);
2218 radeon_emit(cs, va);
2219 radeon_emit(cs, va >> 32);
2220 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2221 radeon_emit(cs, 0); /* unused */
2222
2223 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2224 }
2225 }
2226
2227 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2228 VkPipelineStageFlags src_stage_mask)
2229 {
2230 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2231 VK_PIPELINE_STAGE_TRANSFER_BIT |
2232 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2233 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2234 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2235 }
2236
2237 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2238 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2239 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2240 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2241 VK_PIPELINE_STAGE_TRANSFER_BIT |
2242 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2243 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2244 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2245 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2246 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2247 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2248 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2249 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2250 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2251 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2252 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2253 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2254 }
2255 }
2256
2257 static enum radv_cmd_flush_bits
2258 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2259 VkAccessFlags src_flags,
2260 struct radv_image *image)
2261 {
2262 bool flush_CB_meta = true, flush_DB_meta = true;
2263 enum radv_cmd_flush_bits flush_bits = 0;
2264 uint32_t b;
2265
2266 if (image) {
2267 if (!radv_image_has_CB_metadata(image))
2268 flush_CB_meta = false;
2269 if (!radv_image_has_htile(image))
2270 flush_DB_meta = false;
2271 }
2272
2273 for_each_bit(b, src_flags) {
2274 switch ((VkAccessFlagBits)(1 << b)) {
2275 case VK_ACCESS_SHADER_WRITE_BIT:
2276 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2277 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2278 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2279 break;
2280 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2281 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2282 if (flush_CB_meta)
2283 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2284 break;
2285 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2286 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2287 if (flush_DB_meta)
2288 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2289 break;
2290 case VK_ACCESS_TRANSFER_WRITE_BIT:
2291 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2292 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2293 RADV_CMD_FLAG_INV_GLOBAL_L2;
2294
2295 if (flush_CB_meta)
2296 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2297 if (flush_DB_meta)
2298 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2299 break;
2300 default:
2301 break;
2302 }
2303 }
2304 return flush_bits;
2305 }
2306
2307 static enum radv_cmd_flush_bits
2308 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2309 VkAccessFlags dst_flags,
2310 struct radv_image *image)
2311 {
2312 bool flush_CB_meta = true, flush_DB_meta = true;
2313 enum radv_cmd_flush_bits flush_bits = 0;
2314 bool flush_CB = true, flush_DB = true;
2315 bool image_is_coherent = false;
2316 uint32_t b;
2317
2318 if (image) {
2319 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2320 flush_CB = false;
2321 flush_DB = false;
2322 }
2323
2324 if (!radv_image_has_CB_metadata(image))
2325 flush_CB_meta = false;
2326 if (!radv_image_has_htile(image))
2327 flush_DB_meta = false;
2328
2329 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2330 if (image->info.samples == 1 &&
2331 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2332 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2333 !vk_format_is_stencil(image->vk_format)) {
2334 /* Single-sample color and single-sample depth
2335 * (not stencil) are coherent with shaders on
2336 * GFX9.
2337 */
2338 image_is_coherent = true;
2339 }
2340 }
2341 }
2342
2343 for_each_bit(b, dst_flags) {
2344 switch ((VkAccessFlagBits)(1 << b)) {
2345 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2346 case VK_ACCESS_INDEX_READ_BIT:
2347 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2348 break;
2349 case VK_ACCESS_UNIFORM_READ_BIT:
2350 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2351 break;
2352 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2353 case VK_ACCESS_TRANSFER_READ_BIT:
2354 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2355 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2356 RADV_CMD_FLAG_INV_GLOBAL_L2;
2357 break;
2358 case VK_ACCESS_SHADER_READ_BIT:
2359 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2360
2361 if (!image_is_coherent)
2362 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2363 break;
2364 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2365 if (flush_CB)
2366 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2367 if (flush_CB_meta)
2368 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2369 break;
2370 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2371 if (flush_DB)
2372 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2373 if (flush_DB_meta)
2374 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2375 break;
2376 default:
2377 break;
2378 }
2379 }
2380 return flush_bits;
2381 }
2382
2383 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2384 const struct radv_subpass_barrier *barrier)
2385 {
2386 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2387 NULL);
2388 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2389 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2390 NULL);
2391 }
2392
2393 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2394 struct radv_subpass_attachment att)
2395 {
2396 unsigned idx = att.attachment;
2397 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2398 VkImageSubresourceRange range;
2399 range.aspectMask = 0;
2400 range.baseMipLevel = view->base_mip;
2401 range.levelCount = 1;
2402 range.baseArrayLayer = view->base_layer;
2403 range.layerCount = cmd_buffer->state.framebuffer->layers;
2404
2405 if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
2406 /* If the current subpass uses multiview, the driver might have
2407 * performed a fast color/depth clear to the whole image
2408 * (including all layers). To make sure the driver will
2409 * decompress the image correctly (if needed), we have to
2410 * account for the "real" number of layers. If the view mask is
2411 * sparse, this will decompress more layers than needed.
2412 */
2413 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2414 }
2415
2416 radv_handle_image_transition(cmd_buffer,
2417 view->image,
2418 cmd_buffer->state.attachments[idx].current_layout,
2419 att.layout, 0, 0, &range);
2420
2421 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2422
2423
2424 }
2425
2426 void
2427 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2428 const struct radv_subpass *subpass, bool transitions)
2429 {
2430 if (transitions) {
2431 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2432
2433 for (unsigned i = 0; i < subpass->color_count; ++i) {
2434 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2435 radv_handle_subpass_image_transition(cmd_buffer,
2436 subpass->color_attachments[i]);
2437 }
2438
2439 for (unsigned i = 0; i < subpass->input_count; ++i) {
2440 radv_handle_subpass_image_transition(cmd_buffer,
2441 subpass->input_attachments[i]);
2442 }
2443
2444 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2445 radv_handle_subpass_image_transition(cmd_buffer,
2446 subpass->depth_stencil_attachment);
2447 }
2448 }
2449
2450 cmd_buffer->state.subpass = subpass;
2451
2452 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2453 }
2454
2455 static VkResult
2456 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2457 struct radv_render_pass *pass,
2458 const VkRenderPassBeginInfo *info)
2459 {
2460 struct radv_cmd_state *state = &cmd_buffer->state;
2461
2462 if (pass->attachment_count == 0) {
2463 state->attachments = NULL;
2464 return VK_SUCCESS;
2465 }
2466
2467 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2468 pass->attachment_count *
2469 sizeof(state->attachments[0]),
2470 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2471 if (state->attachments == NULL) {
2472 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2473 return cmd_buffer->record_result;
2474 }
2475
2476 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2477 struct radv_render_pass_attachment *att = &pass->attachments[i];
2478 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2479 VkImageAspectFlags clear_aspects = 0;
2480
2481 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2482 /* color attachment */
2483 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2484 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2485 }
2486 } else {
2487 /* depthstencil attachment */
2488 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2489 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2490 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2491 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2492 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2493 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2494 }
2495 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2496 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2497 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2498 }
2499 }
2500
2501 state->attachments[i].pending_clear_aspects = clear_aspects;
2502 state->attachments[i].cleared_views = 0;
2503 if (clear_aspects && info) {
2504 assert(info->clearValueCount > i);
2505 state->attachments[i].clear_value = info->pClearValues[i];
2506 }
2507
2508 state->attachments[i].current_layout = att->initial_layout;
2509 }
2510
2511 return VK_SUCCESS;
2512 }
2513
2514 VkResult radv_AllocateCommandBuffers(
2515 VkDevice _device,
2516 const VkCommandBufferAllocateInfo *pAllocateInfo,
2517 VkCommandBuffer *pCommandBuffers)
2518 {
2519 RADV_FROM_HANDLE(radv_device, device, _device);
2520 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2521
2522 VkResult result = VK_SUCCESS;
2523 uint32_t i;
2524
2525 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2526
2527 if (!list_empty(&pool->free_cmd_buffers)) {
2528 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2529
2530 list_del(&cmd_buffer->pool_link);
2531 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2532
2533 result = radv_reset_cmd_buffer(cmd_buffer);
2534 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2535 cmd_buffer->level = pAllocateInfo->level;
2536
2537 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2538 } else {
2539 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2540 &pCommandBuffers[i]);
2541 }
2542 if (result != VK_SUCCESS)
2543 break;
2544 }
2545
2546 if (result != VK_SUCCESS) {
2547 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2548 i, pCommandBuffers);
2549
2550 /* From the Vulkan 1.0.66 spec:
2551 *
2552 * "vkAllocateCommandBuffers can be used to create multiple
2553 * command buffers. If the creation of any of those command
2554 * buffers fails, the implementation must destroy all
2555 * successfully created command buffer objects from this
2556 * command, set all entries of the pCommandBuffers array to
2557 * NULL and return the error."
2558 */
2559 memset(pCommandBuffers, 0,
2560 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2561 }
2562
2563 return result;
2564 }
2565
2566 void radv_FreeCommandBuffers(
2567 VkDevice device,
2568 VkCommandPool commandPool,
2569 uint32_t commandBufferCount,
2570 const VkCommandBuffer *pCommandBuffers)
2571 {
2572 for (uint32_t i = 0; i < commandBufferCount; i++) {
2573 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2574
2575 if (cmd_buffer) {
2576 if (cmd_buffer->pool) {
2577 list_del(&cmd_buffer->pool_link);
2578 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2579 } else
2580 radv_cmd_buffer_destroy(cmd_buffer);
2581
2582 }
2583 }
2584 }
2585
2586 VkResult radv_ResetCommandBuffer(
2587 VkCommandBuffer commandBuffer,
2588 VkCommandBufferResetFlags flags)
2589 {
2590 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2591 return radv_reset_cmd_buffer(cmd_buffer);
2592 }
2593
2594 VkResult radv_BeginCommandBuffer(
2595 VkCommandBuffer commandBuffer,
2596 const VkCommandBufferBeginInfo *pBeginInfo)
2597 {
2598 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2599 VkResult result = VK_SUCCESS;
2600
2601 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2602 /* If the command buffer has already been resetted with
2603 * vkResetCommandBuffer, no need to do it again.
2604 */
2605 result = radv_reset_cmd_buffer(cmd_buffer);
2606 if (result != VK_SUCCESS)
2607 return result;
2608 }
2609
2610 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2611 cmd_buffer->state.last_primitive_reset_en = -1;
2612 cmd_buffer->state.last_index_type = -1;
2613 cmd_buffer->state.last_num_instances = -1;
2614 cmd_buffer->state.last_vertex_offset = -1;
2615 cmd_buffer->state.last_first_instance = -1;
2616 cmd_buffer->state.predication_type = -1;
2617 cmd_buffer->usage_flags = pBeginInfo->flags;
2618
2619 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2620 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2621 assert(pBeginInfo->pInheritanceInfo);
2622 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2623 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2624
2625 struct radv_subpass *subpass =
2626 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2627
2628 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2629 if (result != VK_SUCCESS)
2630 return result;
2631
2632 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2633 }
2634
2635 if (unlikely(cmd_buffer->device->trace_bo)) {
2636 struct radv_device *device = cmd_buffer->device;
2637
2638 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2639 device->trace_bo);
2640
2641 radv_cmd_buffer_trace_emit(cmd_buffer);
2642 }
2643
2644 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2645
2646 return result;
2647 }
2648
2649 void radv_CmdBindVertexBuffers(
2650 VkCommandBuffer commandBuffer,
2651 uint32_t firstBinding,
2652 uint32_t bindingCount,
2653 const VkBuffer* pBuffers,
2654 const VkDeviceSize* pOffsets)
2655 {
2656 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2657 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2658 bool changed = false;
2659
2660 /* We have to defer setting up vertex buffer since we need the buffer
2661 * stride from the pipeline. */
2662
2663 assert(firstBinding + bindingCount <= MAX_VBS);
2664 for (uint32_t i = 0; i < bindingCount; i++) {
2665 uint32_t idx = firstBinding + i;
2666
2667 if (!changed &&
2668 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2669 vb[idx].offset != pOffsets[i])) {
2670 changed = true;
2671 }
2672
2673 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2674 vb[idx].offset = pOffsets[i];
2675
2676 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2677 vb[idx].buffer->bo);
2678 }
2679
2680 if (!changed) {
2681 /* No state changes. */
2682 return;
2683 }
2684
2685 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2686 }
2687
2688 void radv_CmdBindIndexBuffer(
2689 VkCommandBuffer commandBuffer,
2690 VkBuffer buffer,
2691 VkDeviceSize offset,
2692 VkIndexType indexType)
2693 {
2694 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2695 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2696
2697 if (cmd_buffer->state.index_buffer == index_buffer &&
2698 cmd_buffer->state.index_offset == offset &&
2699 cmd_buffer->state.index_type == indexType) {
2700 /* No state changes. */
2701 return;
2702 }
2703
2704 cmd_buffer->state.index_buffer = index_buffer;
2705 cmd_buffer->state.index_offset = offset;
2706 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2707 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2708 cmd_buffer->state.index_va += index_buffer->offset + offset;
2709
2710 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2711 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2712 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2713 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2714 }
2715
2716
2717 static void
2718 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2719 VkPipelineBindPoint bind_point,
2720 struct radv_descriptor_set *set, unsigned idx)
2721 {
2722 struct radeon_winsys *ws = cmd_buffer->device->ws;
2723
2724 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2725
2726 assert(set);
2727 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2728
2729 if (!cmd_buffer->device->use_global_bo_list) {
2730 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2731 if (set->descriptors[j])
2732 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2733 }
2734
2735 if(set->bo)
2736 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2737 }
2738
2739 void radv_CmdBindDescriptorSets(
2740 VkCommandBuffer commandBuffer,
2741 VkPipelineBindPoint pipelineBindPoint,
2742 VkPipelineLayout _layout,
2743 uint32_t firstSet,
2744 uint32_t descriptorSetCount,
2745 const VkDescriptorSet* pDescriptorSets,
2746 uint32_t dynamicOffsetCount,
2747 const uint32_t* pDynamicOffsets)
2748 {
2749 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2750 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2751 unsigned dyn_idx = 0;
2752
2753 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2754 struct radv_descriptor_state *descriptors_state =
2755 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2756
2757 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2758 unsigned idx = i + firstSet;
2759 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2760 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2761
2762 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2763 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2764 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2765 assert(dyn_idx < dynamicOffsetCount);
2766
2767 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2768 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2769 dst[0] = va;
2770 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2771 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2772 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2773 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2774 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2775 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2776 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2777 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2778 cmd_buffer->push_constant_stages |=
2779 set->layout->dynamic_shader_stages;
2780 }
2781 }
2782 }
2783
2784 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2785 struct radv_descriptor_set *set,
2786 struct radv_descriptor_set_layout *layout,
2787 VkPipelineBindPoint bind_point)
2788 {
2789 struct radv_descriptor_state *descriptors_state =
2790 radv_get_descriptors_state(cmd_buffer, bind_point);
2791 set->size = layout->size;
2792 set->layout = layout;
2793
2794 if (descriptors_state->push_set.capacity < set->size) {
2795 size_t new_size = MAX2(set->size, 1024);
2796 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2797 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2798
2799 free(set->mapped_ptr);
2800 set->mapped_ptr = malloc(new_size);
2801
2802 if (!set->mapped_ptr) {
2803 descriptors_state->push_set.capacity = 0;
2804 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2805 return false;
2806 }
2807
2808 descriptors_state->push_set.capacity = new_size;
2809 }
2810
2811 return true;
2812 }
2813
2814 void radv_meta_push_descriptor_set(
2815 struct radv_cmd_buffer* cmd_buffer,
2816 VkPipelineBindPoint pipelineBindPoint,
2817 VkPipelineLayout _layout,
2818 uint32_t set,
2819 uint32_t descriptorWriteCount,
2820 const VkWriteDescriptorSet* pDescriptorWrites)
2821 {
2822 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2823 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2824 unsigned bo_offset;
2825
2826 assert(set == 0);
2827 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2828
2829 push_set->size = layout->set[set].layout->size;
2830 push_set->layout = layout->set[set].layout;
2831
2832 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2833 &bo_offset,
2834 (void**) &push_set->mapped_ptr))
2835 return;
2836
2837 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2838 push_set->va += bo_offset;
2839
2840 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2841 radv_descriptor_set_to_handle(push_set),
2842 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2843
2844 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2845 }
2846
2847 void radv_CmdPushDescriptorSetKHR(
2848 VkCommandBuffer commandBuffer,
2849 VkPipelineBindPoint pipelineBindPoint,
2850 VkPipelineLayout _layout,
2851 uint32_t set,
2852 uint32_t descriptorWriteCount,
2853 const VkWriteDescriptorSet* pDescriptorWrites)
2854 {
2855 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2856 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2857 struct radv_descriptor_state *descriptors_state =
2858 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2859 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2860
2861 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2862
2863 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2864 layout->set[set].layout,
2865 pipelineBindPoint))
2866 return;
2867
2868 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2869 radv_descriptor_set_to_handle(push_set),
2870 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2871
2872 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2873 descriptors_state->push_dirty = true;
2874 }
2875
2876 void radv_CmdPushDescriptorSetWithTemplateKHR(
2877 VkCommandBuffer commandBuffer,
2878 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2879 VkPipelineLayout _layout,
2880 uint32_t set,
2881 const void* pData)
2882 {
2883 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2884 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2885 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2886 struct radv_descriptor_state *descriptors_state =
2887 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2888 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2889
2890 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2891
2892 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2893 layout->set[set].layout,
2894 templ->bind_point))
2895 return;
2896
2897 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2898 descriptorUpdateTemplate, pData);
2899
2900 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2901 descriptors_state->push_dirty = true;
2902 }
2903
2904 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2905 VkPipelineLayout layout,
2906 VkShaderStageFlags stageFlags,
2907 uint32_t offset,
2908 uint32_t size,
2909 const void* pValues)
2910 {
2911 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2912 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2913 cmd_buffer->push_constant_stages |= stageFlags;
2914 }
2915
2916 VkResult radv_EndCommandBuffer(
2917 VkCommandBuffer commandBuffer)
2918 {
2919 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2920
2921 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2922 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2923 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2924 si_emit_cache_flush(cmd_buffer);
2925 }
2926
2927 /* Make sure CP DMA is idle at the end of IBs because the kernel
2928 * doesn't wait for it.
2929 */
2930 si_cp_dma_wait_for_idle(cmd_buffer);
2931
2932 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2933
2934 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2935 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2936
2937 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2938
2939 return cmd_buffer->record_result;
2940 }
2941
2942 static void
2943 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2944 {
2945 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2946
2947 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2948 return;
2949
2950 assert(!pipeline->ctx_cs.cdw);
2951
2952 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2953
2954 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2955 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2956
2957 cmd_buffer->compute_scratch_size_needed =
2958 MAX2(cmd_buffer->compute_scratch_size_needed,
2959 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2960
2961 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2962 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2963
2964 if (unlikely(cmd_buffer->device->trace_bo))
2965 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2966 }
2967
2968 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2969 VkPipelineBindPoint bind_point)
2970 {
2971 struct radv_descriptor_state *descriptors_state =
2972 radv_get_descriptors_state(cmd_buffer, bind_point);
2973
2974 descriptors_state->dirty |= descriptors_state->valid;
2975 }
2976
2977 void radv_CmdBindPipeline(
2978 VkCommandBuffer commandBuffer,
2979 VkPipelineBindPoint pipelineBindPoint,
2980 VkPipeline _pipeline)
2981 {
2982 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2983 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2984
2985 switch (pipelineBindPoint) {
2986 case VK_PIPELINE_BIND_POINT_COMPUTE:
2987 if (cmd_buffer->state.compute_pipeline == pipeline)
2988 return;
2989 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2990
2991 cmd_buffer->state.compute_pipeline = pipeline;
2992 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2993 break;
2994 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2995 if (cmd_buffer->state.pipeline == pipeline)
2996 return;
2997 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2998
2999 cmd_buffer->state.pipeline = pipeline;
3000 if (!pipeline)
3001 break;
3002
3003 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3004 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3005
3006 /* the new vertex shader might not have the same user regs */
3007 cmd_buffer->state.last_first_instance = -1;
3008 cmd_buffer->state.last_vertex_offset = -1;
3009
3010 /* Prefetch all pipeline shaders at first draw time. */
3011 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3012
3013 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3014 radv_bind_streamout_state(cmd_buffer, pipeline);
3015
3016 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3017 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3018 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3019 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3020
3021 if (radv_pipeline_has_tess(pipeline))
3022 cmd_buffer->tess_rings_needed = true;
3023 break;
3024 default:
3025 assert(!"invalid bind point");
3026 break;
3027 }
3028 }
3029
3030 void radv_CmdSetViewport(
3031 VkCommandBuffer commandBuffer,
3032 uint32_t firstViewport,
3033 uint32_t viewportCount,
3034 const VkViewport* pViewports)
3035 {
3036 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3037 struct radv_cmd_state *state = &cmd_buffer->state;
3038 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3039
3040 assert(firstViewport < MAX_VIEWPORTS);
3041 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3042
3043 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3044 pViewports, viewportCount * sizeof(*pViewports))) {
3045 return;
3046 }
3047
3048 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3049 viewportCount * sizeof(*pViewports));
3050
3051 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3052 }
3053
3054 void radv_CmdSetScissor(
3055 VkCommandBuffer commandBuffer,
3056 uint32_t firstScissor,
3057 uint32_t scissorCount,
3058 const VkRect2D* pScissors)
3059 {
3060 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3061 struct radv_cmd_state *state = &cmd_buffer->state;
3062 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3063
3064 assert(firstScissor < MAX_SCISSORS);
3065 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3066
3067 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3068 scissorCount * sizeof(*pScissors))) {
3069 return;
3070 }
3071
3072 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3073 scissorCount * sizeof(*pScissors));
3074
3075 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3076 }
3077
3078 void radv_CmdSetLineWidth(
3079 VkCommandBuffer commandBuffer,
3080 float lineWidth)
3081 {
3082 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3083
3084 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3085 return;
3086
3087 cmd_buffer->state.dynamic.line_width = lineWidth;
3088 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3089 }
3090
3091 void radv_CmdSetDepthBias(
3092 VkCommandBuffer commandBuffer,
3093 float depthBiasConstantFactor,
3094 float depthBiasClamp,
3095 float depthBiasSlopeFactor)
3096 {
3097 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3098 struct radv_cmd_state *state = &cmd_buffer->state;
3099
3100 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3101 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3102 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3103 return;
3104 }
3105
3106 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3107 state->dynamic.depth_bias.clamp = depthBiasClamp;
3108 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3109
3110 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3111 }
3112
3113 void radv_CmdSetBlendConstants(
3114 VkCommandBuffer commandBuffer,
3115 const float blendConstants[4])
3116 {
3117 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3118 struct radv_cmd_state *state = &cmd_buffer->state;
3119
3120 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3121 return;
3122
3123 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3124
3125 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3126 }
3127
3128 void radv_CmdSetDepthBounds(
3129 VkCommandBuffer commandBuffer,
3130 float minDepthBounds,
3131 float maxDepthBounds)
3132 {
3133 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3134 struct radv_cmd_state *state = &cmd_buffer->state;
3135
3136 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3137 state->dynamic.depth_bounds.max == maxDepthBounds) {
3138 return;
3139 }
3140
3141 state->dynamic.depth_bounds.min = minDepthBounds;
3142 state->dynamic.depth_bounds.max = maxDepthBounds;
3143
3144 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3145 }
3146
3147 void radv_CmdSetStencilCompareMask(
3148 VkCommandBuffer commandBuffer,
3149 VkStencilFaceFlags faceMask,
3150 uint32_t compareMask)
3151 {
3152 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3153 struct radv_cmd_state *state = &cmd_buffer->state;
3154 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3155 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3156
3157 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3158 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3159 return;
3160 }
3161
3162 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3163 state->dynamic.stencil_compare_mask.front = compareMask;
3164 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3165 state->dynamic.stencil_compare_mask.back = compareMask;
3166
3167 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3168 }
3169
3170 void radv_CmdSetStencilWriteMask(
3171 VkCommandBuffer commandBuffer,
3172 VkStencilFaceFlags faceMask,
3173 uint32_t writeMask)
3174 {
3175 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3176 struct radv_cmd_state *state = &cmd_buffer->state;
3177 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3178 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3179
3180 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3181 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3182 return;
3183 }
3184
3185 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3186 state->dynamic.stencil_write_mask.front = writeMask;
3187 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3188 state->dynamic.stencil_write_mask.back = writeMask;
3189
3190 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3191 }
3192
3193 void radv_CmdSetStencilReference(
3194 VkCommandBuffer commandBuffer,
3195 VkStencilFaceFlags faceMask,
3196 uint32_t reference)
3197 {
3198 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3199 struct radv_cmd_state *state = &cmd_buffer->state;
3200 bool front_same = state->dynamic.stencil_reference.front == reference;
3201 bool back_same = state->dynamic.stencil_reference.back == reference;
3202
3203 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3204 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3205 return;
3206 }
3207
3208 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3209 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3210 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3211 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3212
3213 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3214 }
3215
3216 void radv_CmdSetDiscardRectangleEXT(
3217 VkCommandBuffer commandBuffer,
3218 uint32_t firstDiscardRectangle,
3219 uint32_t discardRectangleCount,
3220 const VkRect2D* pDiscardRectangles)
3221 {
3222 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3223 struct radv_cmd_state *state = &cmd_buffer->state;
3224 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3225
3226 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3227 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3228
3229 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3230 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3231 return;
3232 }
3233
3234 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3235 pDiscardRectangles, discardRectangleCount);
3236
3237 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3238 }
3239
3240 void radv_CmdExecuteCommands(
3241 VkCommandBuffer commandBuffer,
3242 uint32_t commandBufferCount,
3243 const VkCommandBuffer* pCmdBuffers)
3244 {
3245 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3246
3247 assert(commandBufferCount > 0);
3248
3249 /* Emit pending flushes on primary prior to executing secondary */
3250 si_emit_cache_flush(primary);
3251
3252 for (uint32_t i = 0; i < commandBufferCount; i++) {
3253 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3254
3255 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3256 secondary->scratch_size_needed);
3257 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3258 secondary->compute_scratch_size_needed);
3259
3260 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3261 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3262 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3263 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3264 if (secondary->tess_rings_needed)
3265 primary->tess_rings_needed = true;
3266 if (secondary->sample_positions_needed)
3267 primary->sample_positions_needed = true;
3268
3269 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3270
3271
3272 /* When the secondary command buffer is compute only we don't
3273 * need to re-emit the current graphics pipeline.
3274 */
3275 if (secondary->state.emitted_pipeline) {
3276 primary->state.emitted_pipeline =
3277 secondary->state.emitted_pipeline;
3278 }
3279
3280 /* When the secondary command buffer is graphics only we don't
3281 * need to re-emit the current compute pipeline.
3282 */
3283 if (secondary->state.emitted_compute_pipeline) {
3284 primary->state.emitted_compute_pipeline =
3285 secondary->state.emitted_compute_pipeline;
3286 }
3287
3288 /* Only re-emit the draw packets when needed. */
3289 if (secondary->state.last_primitive_reset_en != -1) {
3290 primary->state.last_primitive_reset_en =
3291 secondary->state.last_primitive_reset_en;
3292 }
3293
3294 if (secondary->state.last_primitive_reset_index) {
3295 primary->state.last_primitive_reset_index =
3296 secondary->state.last_primitive_reset_index;
3297 }
3298
3299 if (secondary->state.last_ia_multi_vgt_param) {
3300 primary->state.last_ia_multi_vgt_param =
3301 secondary->state.last_ia_multi_vgt_param;
3302 }
3303
3304 primary->state.last_first_instance = secondary->state.last_first_instance;
3305 primary->state.last_num_instances = secondary->state.last_num_instances;
3306 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3307
3308 if (secondary->state.last_index_type != -1) {
3309 primary->state.last_index_type =
3310 secondary->state.last_index_type;
3311 }
3312 }
3313
3314 /* After executing commands from secondary buffers we have to dirty
3315 * some states.
3316 */
3317 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3318 RADV_CMD_DIRTY_INDEX_BUFFER |
3319 RADV_CMD_DIRTY_DYNAMIC_ALL;
3320 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3321 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3322 }
3323
3324 VkResult radv_CreateCommandPool(
3325 VkDevice _device,
3326 const VkCommandPoolCreateInfo* pCreateInfo,
3327 const VkAllocationCallbacks* pAllocator,
3328 VkCommandPool* pCmdPool)
3329 {
3330 RADV_FROM_HANDLE(radv_device, device, _device);
3331 struct radv_cmd_pool *pool;
3332
3333 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3334 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3335 if (pool == NULL)
3336 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3337
3338 if (pAllocator)
3339 pool->alloc = *pAllocator;
3340 else
3341 pool->alloc = device->alloc;
3342
3343 list_inithead(&pool->cmd_buffers);
3344 list_inithead(&pool->free_cmd_buffers);
3345
3346 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3347
3348 *pCmdPool = radv_cmd_pool_to_handle(pool);
3349
3350 return VK_SUCCESS;
3351
3352 }
3353
3354 void radv_DestroyCommandPool(
3355 VkDevice _device,
3356 VkCommandPool commandPool,
3357 const VkAllocationCallbacks* pAllocator)
3358 {
3359 RADV_FROM_HANDLE(radv_device, device, _device);
3360 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3361
3362 if (!pool)
3363 return;
3364
3365 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3366 &pool->cmd_buffers, pool_link) {
3367 radv_cmd_buffer_destroy(cmd_buffer);
3368 }
3369
3370 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3371 &pool->free_cmd_buffers, pool_link) {
3372 radv_cmd_buffer_destroy(cmd_buffer);
3373 }
3374
3375 vk_free2(&device->alloc, pAllocator, pool);
3376 }
3377
3378 VkResult radv_ResetCommandPool(
3379 VkDevice device,
3380 VkCommandPool commandPool,
3381 VkCommandPoolResetFlags flags)
3382 {
3383 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3384 VkResult result;
3385
3386 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3387 &pool->cmd_buffers, pool_link) {
3388 result = radv_reset_cmd_buffer(cmd_buffer);
3389 if (result != VK_SUCCESS)
3390 return result;
3391 }
3392
3393 return VK_SUCCESS;
3394 }
3395
3396 void radv_TrimCommandPool(
3397 VkDevice device,
3398 VkCommandPool commandPool,
3399 VkCommandPoolTrimFlags flags)
3400 {
3401 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3402
3403 if (!pool)
3404 return;
3405
3406 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3407 &pool->free_cmd_buffers, pool_link) {
3408 radv_cmd_buffer_destroy(cmd_buffer);
3409 }
3410 }
3411
3412 static void
3413 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
3414 uint32_t subpass_id)
3415 {
3416 struct radv_cmd_state *state = &cmd_buffer->state;
3417 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
3418
3419 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3420 cmd_buffer->cs, 2048);
3421
3422 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, true);
3423 radv_cmd_buffer_clear_subpass(cmd_buffer);
3424
3425 assert(cmd_buffer->cs->cdw <= cdw_max);
3426 }
3427
3428 void radv_CmdBeginRenderPass(
3429 VkCommandBuffer commandBuffer,
3430 const VkRenderPassBeginInfo* pRenderPassBegin,
3431 VkSubpassContents contents)
3432 {
3433 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3434 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3435 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3436 VkResult result;
3437
3438 cmd_buffer->state.framebuffer = framebuffer;
3439 cmd_buffer->state.pass = pass;
3440 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3441
3442 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3443 if (result != VK_SUCCESS)
3444 return;
3445
3446 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
3447 }
3448
3449 void radv_CmdBeginRenderPass2KHR(
3450 VkCommandBuffer commandBuffer,
3451 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3452 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3453 {
3454 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3455 pSubpassBeginInfo->contents);
3456 }
3457
3458 static uint32_t
3459 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3460 {
3461 struct radv_cmd_state *state = &cmd_buffer->state;
3462 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3463
3464 /* The id of this subpass shouldn't exceed the number of subpasses in
3465 * this render pass minus 1.
3466 */
3467 assert(subpass_id < state->pass->subpass_count);
3468 return subpass_id;
3469 }
3470
3471 void radv_CmdNextSubpass(
3472 VkCommandBuffer commandBuffer,
3473 VkSubpassContents contents)
3474 {
3475 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3476
3477 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3478
3479 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
3480 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
3481 }
3482
3483 void radv_CmdNextSubpass2KHR(
3484 VkCommandBuffer commandBuffer,
3485 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3486 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3487 {
3488 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3489 }
3490
3491 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3492 {
3493 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3494 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3495 if (!radv_get_shader(pipeline, stage))
3496 continue;
3497
3498 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3499 if (loc->sgpr_idx == -1)
3500 continue;
3501 uint32_t base_reg = pipeline->user_data_0[stage];
3502 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3503
3504 }
3505 if (pipeline->gs_copy_shader) {
3506 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3507 if (loc->sgpr_idx != -1) {
3508 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3509 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3510 }
3511 }
3512 }
3513
3514 static void
3515 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3516 uint32_t vertex_count,
3517 bool use_opaque)
3518 {
3519 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3520 radeon_emit(cmd_buffer->cs, vertex_count);
3521 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3522 S_0287F0_USE_OPAQUE(use_opaque));
3523 }
3524
3525 static void
3526 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3527 uint64_t index_va,
3528 uint32_t index_count)
3529 {
3530 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3531 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3532 radeon_emit(cmd_buffer->cs, index_va);
3533 radeon_emit(cmd_buffer->cs, index_va >> 32);
3534 radeon_emit(cmd_buffer->cs, index_count);
3535 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3536 }
3537
3538 static void
3539 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3540 bool indexed,
3541 uint32_t draw_count,
3542 uint64_t count_va,
3543 uint32_t stride)
3544 {
3545 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3546 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3547 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3548 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3549 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3550 bool predicating = cmd_buffer->state.predicating;
3551 assert(base_reg);
3552
3553 /* just reset draw state for vertex data */
3554 cmd_buffer->state.last_first_instance = -1;
3555 cmd_buffer->state.last_num_instances = -1;
3556 cmd_buffer->state.last_vertex_offset = -1;
3557
3558 if (draw_count == 1 && !count_va && !draw_id_enable) {
3559 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3560 PKT3_DRAW_INDIRECT, 3, predicating));
3561 radeon_emit(cs, 0);
3562 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3563 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3564 radeon_emit(cs, di_src_sel);
3565 } else {
3566 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3567 PKT3_DRAW_INDIRECT_MULTI,
3568 8, predicating));
3569 radeon_emit(cs, 0);
3570 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3571 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3572 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3573 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3574 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3575 radeon_emit(cs, draw_count); /* count */
3576 radeon_emit(cs, count_va); /* count_addr */
3577 radeon_emit(cs, count_va >> 32);
3578 radeon_emit(cs, stride); /* stride */
3579 radeon_emit(cs, di_src_sel);
3580 }
3581 }
3582
3583 static void
3584 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3585 const struct radv_draw_info *info)
3586 {
3587 struct radv_cmd_state *state = &cmd_buffer->state;
3588 struct radeon_winsys *ws = cmd_buffer->device->ws;
3589 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3590
3591 if (info->indirect) {
3592 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3593 uint64_t count_va = 0;
3594
3595 va += info->indirect->offset + info->indirect_offset;
3596
3597 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3598
3599 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3600 radeon_emit(cs, 1);
3601 radeon_emit(cs, va);
3602 radeon_emit(cs, va >> 32);
3603
3604 if (info->count_buffer) {
3605 count_va = radv_buffer_get_va(info->count_buffer->bo);
3606 count_va += info->count_buffer->offset +
3607 info->count_buffer_offset;
3608
3609 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3610 }
3611
3612 if (!state->subpass->view_mask) {
3613 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3614 info->indexed,
3615 info->count,
3616 count_va,
3617 info->stride);
3618 } else {
3619 unsigned i;
3620 for_each_bit(i, state->subpass->view_mask) {
3621 radv_emit_view_index(cmd_buffer, i);
3622
3623 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3624 info->indexed,
3625 info->count,
3626 count_va,
3627 info->stride);
3628 }
3629 }
3630 } else {
3631 assert(state->pipeline->graphics.vtx_base_sgpr);
3632
3633 if (info->vertex_offset != state->last_vertex_offset ||
3634 info->first_instance != state->last_first_instance) {
3635 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3636 state->pipeline->graphics.vtx_emit_num);
3637
3638 radeon_emit(cs, info->vertex_offset);
3639 radeon_emit(cs, info->first_instance);
3640 if (state->pipeline->graphics.vtx_emit_num == 3)
3641 radeon_emit(cs, 0);
3642 state->last_first_instance = info->first_instance;
3643 state->last_vertex_offset = info->vertex_offset;
3644 }
3645
3646 if (state->last_num_instances != info->instance_count) {
3647 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3648 radeon_emit(cs, info->instance_count);
3649 state->last_num_instances = info->instance_count;
3650 }
3651
3652 if (info->indexed) {
3653 int index_size = state->index_type ? 4 : 2;
3654 uint64_t index_va;
3655
3656 index_va = state->index_va;
3657 index_va += info->first_index * index_size;
3658
3659 if (!state->subpass->view_mask) {
3660 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3661 index_va,
3662 info->count);
3663 } else {
3664 unsigned i;
3665 for_each_bit(i, state->subpass->view_mask) {
3666 radv_emit_view_index(cmd_buffer, i);
3667
3668 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3669 index_va,
3670 info->count);
3671 }
3672 }
3673 } else {
3674 if (!state->subpass->view_mask) {
3675 radv_cs_emit_draw_packet(cmd_buffer,
3676 info->count,
3677 !!info->strmout_buffer);
3678 } else {
3679 unsigned i;
3680 for_each_bit(i, state->subpass->view_mask) {
3681 radv_emit_view_index(cmd_buffer, i);
3682
3683 radv_cs_emit_draw_packet(cmd_buffer,
3684 info->count,
3685 !!info->strmout_buffer);
3686 }
3687 }
3688 }
3689 }
3690 }
3691
3692 /*
3693 * Vega and raven have a bug which triggers if there are multiple context
3694 * register contexts active at the same time with different scissor values.
3695 *
3696 * There are two possible workarounds:
3697 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3698 * there is only ever 1 active set of scissor values at the same time.
3699 *
3700 * 2) Whenever the hardware switches contexts we have to set the scissor
3701 * registers again even if it is a noop. That way the new context gets
3702 * the correct scissor values.
3703 *
3704 * This implements option 2. radv_need_late_scissor_emission needs to
3705 * return true on affected HW if radv_emit_all_graphics_states sets
3706 * any context registers.
3707 */
3708 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3709 const struct radv_draw_info *info)
3710 {
3711 struct radv_cmd_state *state = &cmd_buffer->state;
3712
3713 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3714 return false;
3715
3716 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
3717 return true;
3718
3719 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3720
3721 /* Index, vertex and streamout buffers don't change context regs, and
3722 * pipeline is already handled.
3723 */
3724 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3725 RADV_CMD_DIRTY_VERTEX_BUFFER |
3726 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
3727 RADV_CMD_DIRTY_PIPELINE);
3728
3729 if (cmd_buffer->state.dirty & used_states)
3730 return true;
3731
3732 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
3733 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3734 return true;
3735
3736 return false;
3737 }
3738
3739 static void
3740 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3741 const struct radv_draw_info *info)
3742 {
3743 bool late_scissor_emission;
3744
3745 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3746 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3747 radv_emit_rbplus_state(cmd_buffer);
3748
3749 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3750 radv_emit_graphics_pipeline(cmd_buffer);
3751
3752 /* This should be before the cmd_buffer->state.dirty is cleared
3753 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
3754 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
3755 late_scissor_emission =
3756 radv_need_late_scissor_emission(cmd_buffer, info);
3757
3758 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3759 radv_emit_framebuffer_state(cmd_buffer);
3760
3761 if (info->indexed) {
3762 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3763 radv_emit_index_buffer(cmd_buffer);
3764 } else {
3765 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3766 * so the state must be re-emitted before the next indexed
3767 * draw.
3768 */
3769 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3770 cmd_buffer->state.last_index_type = -1;
3771 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3772 }
3773 }
3774
3775 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3776
3777 radv_emit_draw_registers(cmd_buffer, info);
3778
3779 if (late_scissor_emission)
3780 radv_emit_scissor(cmd_buffer);
3781 }
3782
3783 static void
3784 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3785 const struct radv_draw_info *info)
3786 {
3787 struct radeon_info *rad_info =
3788 &cmd_buffer->device->physical_device->rad_info;
3789 bool has_prefetch =
3790 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3791 bool pipeline_is_dirty =
3792 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3793 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3794
3795 MAYBE_UNUSED unsigned cdw_max =
3796 radeon_check_space(cmd_buffer->device->ws,
3797 cmd_buffer->cs, 4096);
3798
3799 if (likely(!info->indirect)) {
3800 /* SI-CI treat instance_count==0 as instance_count==1. There is
3801 * no workaround for indirect draws, but we can at least skip
3802 * direct draws.
3803 */
3804 if (unlikely(!info->instance_count))
3805 return;
3806
3807 /* Handle count == 0. */
3808 if (unlikely(!info->count && !info->strmout_buffer))
3809 return;
3810 }
3811
3812 /* Use optimal packet order based on whether we need to sync the
3813 * pipeline.
3814 */
3815 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3816 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3817 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3818 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3819 /* If we have to wait for idle, set all states first, so that
3820 * all SET packets are processed in parallel with previous draw
3821 * calls. Then upload descriptors, set shader pointers, and
3822 * draw, and prefetch at the end. This ensures that the time
3823 * the CUs are idle is very short. (there are only SET_SH
3824 * packets between the wait and the draw)
3825 */
3826 radv_emit_all_graphics_states(cmd_buffer, info);
3827 si_emit_cache_flush(cmd_buffer);
3828 /* <-- CUs are idle here --> */
3829
3830 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3831
3832 radv_emit_draw_packets(cmd_buffer, info);
3833 /* <-- CUs are busy here --> */
3834
3835 /* Start prefetches after the draw has been started. Both will
3836 * run in parallel, but starting the draw first is more
3837 * important.
3838 */
3839 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3840 radv_emit_prefetch_L2(cmd_buffer,
3841 cmd_buffer->state.pipeline, false);
3842 }
3843 } else {
3844 /* If we don't wait for idle, start prefetches first, then set
3845 * states, and draw at the end.
3846 */
3847 si_emit_cache_flush(cmd_buffer);
3848
3849 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3850 /* Only prefetch the vertex shader and VBO descriptors
3851 * in order to start the draw as soon as possible.
3852 */
3853 radv_emit_prefetch_L2(cmd_buffer,
3854 cmd_buffer->state.pipeline, true);
3855 }
3856
3857 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3858
3859 radv_emit_all_graphics_states(cmd_buffer, info);
3860 radv_emit_draw_packets(cmd_buffer, info);
3861
3862 /* Prefetch the remaining shaders after the draw has been
3863 * started.
3864 */
3865 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3866 radv_emit_prefetch_L2(cmd_buffer,
3867 cmd_buffer->state.pipeline, false);
3868 }
3869 }
3870
3871 /* Workaround for a VGT hang when streamout is enabled.
3872 * It must be done after drawing.
3873 */
3874 if (cmd_buffer->state.streamout.streamout_enabled &&
3875 (rad_info->family == CHIP_HAWAII ||
3876 rad_info->family == CHIP_TONGA ||
3877 rad_info->family == CHIP_FIJI)) {
3878 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
3879 }
3880
3881 assert(cmd_buffer->cs->cdw <= cdw_max);
3882 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3883 }
3884
3885 void radv_CmdDraw(
3886 VkCommandBuffer commandBuffer,
3887 uint32_t vertexCount,
3888 uint32_t instanceCount,
3889 uint32_t firstVertex,
3890 uint32_t firstInstance)
3891 {
3892 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3893 struct radv_draw_info info = {};
3894
3895 info.count = vertexCount;
3896 info.instance_count = instanceCount;
3897 info.first_instance = firstInstance;
3898 info.vertex_offset = firstVertex;
3899
3900 radv_draw(cmd_buffer, &info);
3901 }
3902
3903 void radv_CmdDrawIndexed(
3904 VkCommandBuffer commandBuffer,
3905 uint32_t indexCount,
3906 uint32_t instanceCount,
3907 uint32_t firstIndex,
3908 int32_t vertexOffset,
3909 uint32_t firstInstance)
3910 {
3911 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3912 struct radv_draw_info info = {};
3913
3914 info.indexed = true;
3915 info.count = indexCount;
3916 info.instance_count = instanceCount;
3917 info.first_index = firstIndex;
3918 info.vertex_offset = vertexOffset;
3919 info.first_instance = firstInstance;
3920
3921 radv_draw(cmd_buffer, &info);
3922 }
3923
3924 void radv_CmdDrawIndirect(
3925 VkCommandBuffer commandBuffer,
3926 VkBuffer _buffer,
3927 VkDeviceSize offset,
3928 uint32_t drawCount,
3929 uint32_t stride)
3930 {
3931 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3932 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3933 struct radv_draw_info info = {};
3934
3935 info.count = drawCount;
3936 info.indirect = buffer;
3937 info.indirect_offset = offset;
3938 info.stride = stride;
3939
3940 radv_draw(cmd_buffer, &info);
3941 }
3942
3943 void radv_CmdDrawIndexedIndirect(
3944 VkCommandBuffer commandBuffer,
3945 VkBuffer _buffer,
3946 VkDeviceSize offset,
3947 uint32_t drawCount,
3948 uint32_t stride)
3949 {
3950 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3951 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3952 struct radv_draw_info info = {};
3953
3954 info.indexed = true;
3955 info.count = drawCount;
3956 info.indirect = buffer;
3957 info.indirect_offset = offset;
3958 info.stride = stride;
3959
3960 radv_draw(cmd_buffer, &info);
3961 }
3962
3963 void radv_CmdDrawIndirectCountAMD(
3964 VkCommandBuffer commandBuffer,
3965 VkBuffer _buffer,
3966 VkDeviceSize offset,
3967 VkBuffer _countBuffer,
3968 VkDeviceSize countBufferOffset,
3969 uint32_t maxDrawCount,
3970 uint32_t stride)
3971 {
3972 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3973 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3974 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3975 struct radv_draw_info info = {};
3976
3977 info.count = maxDrawCount;
3978 info.indirect = buffer;
3979 info.indirect_offset = offset;
3980 info.count_buffer = count_buffer;
3981 info.count_buffer_offset = countBufferOffset;
3982 info.stride = stride;
3983
3984 radv_draw(cmd_buffer, &info);
3985 }
3986
3987 void radv_CmdDrawIndexedIndirectCountAMD(
3988 VkCommandBuffer commandBuffer,
3989 VkBuffer _buffer,
3990 VkDeviceSize offset,
3991 VkBuffer _countBuffer,
3992 VkDeviceSize countBufferOffset,
3993 uint32_t maxDrawCount,
3994 uint32_t stride)
3995 {
3996 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3997 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3998 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3999 struct radv_draw_info info = {};
4000
4001 info.indexed = true;
4002 info.count = maxDrawCount;
4003 info.indirect = buffer;
4004 info.indirect_offset = offset;
4005 info.count_buffer = count_buffer;
4006 info.count_buffer_offset = countBufferOffset;
4007 info.stride = stride;
4008
4009 radv_draw(cmd_buffer, &info);
4010 }
4011
4012 void radv_CmdDrawIndirectCountKHR(
4013 VkCommandBuffer commandBuffer,
4014 VkBuffer _buffer,
4015 VkDeviceSize offset,
4016 VkBuffer _countBuffer,
4017 VkDeviceSize countBufferOffset,
4018 uint32_t maxDrawCount,
4019 uint32_t stride)
4020 {
4021 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4022 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4023 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4024 struct radv_draw_info info = {};
4025
4026 info.count = maxDrawCount;
4027 info.indirect = buffer;
4028 info.indirect_offset = offset;
4029 info.count_buffer = count_buffer;
4030 info.count_buffer_offset = countBufferOffset;
4031 info.stride = stride;
4032
4033 radv_draw(cmd_buffer, &info);
4034 }
4035
4036 void radv_CmdDrawIndexedIndirectCountKHR(
4037 VkCommandBuffer commandBuffer,
4038 VkBuffer _buffer,
4039 VkDeviceSize offset,
4040 VkBuffer _countBuffer,
4041 VkDeviceSize countBufferOffset,
4042 uint32_t maxDrawCount,
4043 uint32_t stride)
4044 {
4045 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4046 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4047 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4048 struct radv_draw_info info = {};
4049
4050 info.indexed = true;
4051 info.count = maxDrawCount;
4052 info.indirect = buffer;
4053 info.indirect_offset = offset;
4054 info.count_buffer = count_buffer;
4055 info.count_buffer_offset = countBufferOffset;
4056 info.stride = stride;
4057
4058 radv_draw(cmd_buffer, &info);
4059 }
4060
4061 struct radv_dispatch_info {
4062 /**
4063 * Determine the layout of the grid (in block units) to be used.
4064 */
4065 uint32_t blocks[3];
4066
4067 /**
4068 * A starting offset for the grid. If unaligned is set, the offset
4069 * must still be aligned.
4070 */
4071 uint32_t offsets[3];
4072 /**
4073 * Whether it's an unaligned compute dispatch.
4074 */
4075 bool unaligned;
4076
4077 /**
4078 * Indirect compute parameters resource.
4079 */
4080 struct radv_buffer *indirect;
4081 uint64_t indirect_offset;
4082 };
4083
4084 static void
4085 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4086 const struct radv_dispatch_info *info)
4087 {
4088 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4089 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4090 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4091 struct radeon_winsys *ws = cmd_buffer->device->ws;
4092 bool predicating = cmd_buffer->state.predicating;
4093 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4094 struct radv_userdata_info *loc;
4095
4096 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4097 AC_UD_CS_GRID_SIZE);
4098
4099 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4100
4101 if (info->indirect) {
4102 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4103
4104 va += info->indirect->offset + info->indirect_offset;
4105
4106 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4107
4108 if (loc->sgpr_idx != -1) {
4109 for (unsigned i = 0; i < 3; ++i) {
4110 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4111 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4112 COPY_DATA_DST_SEL(COPY_DATA_REG));
4113 radeon_emit(cs, (va + 4 * i));
4114 radeon_emit(cs, (va + 4 * i) >> 32);
4115 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4116 + loc->sgpr_idx * 4) >> 2) + i);
4117 radeon_emit(cs, 0);
4118 }
4119 }
4120
4121 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4122 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4123 PKT3_SHADER_TYPE_S(1));
4124 radeon_emit(cs, va);
4125 radeon_emit(cs, va >> 32);
4126 radeon_emit(cs, dispatch_initiator);
4127 } else {
4128 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4129 PKT3_SHADER_TYPE_S(1));
4130 radeon_emit(cs, 1);
4131 radeon_emit(cs, va);
4132 radeon_emit(cs, va >> 32);
4133
4134 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4135 PKT3_SHADER_TYPE_S(1));
4136 radeon_emit(cs, 0);
4137 radeon_emit(cs, dispatch_initiator);
4138 }
4139 } else {
4140 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4141 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4142
4143 if (info->unaligned) {
4144 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4145 unsigned remainder[3];
4146
4147 /* If aligned, these should be an entire block size,
4148 * not 0.
4149 */
4150 remainder[0] = blocks[0] + cs_block_size[0] -
4151 align_u32_npot(blocks[0], cs_block_size[0]);
4152 remainder[1] = blocks[1] + cs_block_size[1] -
4153 align_u32_npot(blocks[1], cs_block_size[1]);
4154 remainder[2] = blocks[2] + cs_block_size[2] -
4155 align_u32_npot(blocks[2], cs_block_size[2]);
4156
4157 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4158 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4159 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4160
4161 for(unsigned i = 0; i < 3; ++i) {
4162 assert(offsets[i] % cs_block_size[i] == 0);
4163 offsets[i] /= cs_block_size[i];
4164 }
4165
4166 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4167 radeon_emit(cs,
4168 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4169 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4170 radeon_emit(cs,
4171 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4172 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4173 radeon_emit(cs,
4174 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4175 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4176
4177 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4178 }
4179
4180 if (loc->sgpr_idx != -1) {
4181 assert(loc->num_sgprs == 3);
4182
4183 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4184 loc->sgpr_idx * 4, 3);
4185 radeon_emit(cs, blocks[0]);
4186 radeon_emit(cs, blocks[1]);
4187 radeon_emit(cs, blocks[2]);
4188 }
4189
4190 if (offsets[0] || offsets[1] || offsets[2]) {
4191 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4192 radeon_emit(cs, offsets[0]);
4193 radeon_emit(cs, offsets[1]);
4194 radeon_emit(cs, offsets[2]);
4195
4196 /* The blocks in the packet are not counts but end values. */
4197 for (unsigned i = 0; i < 3; ++i)
4198 blocks[i] += offsets[i];
4199 } else {
4200 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4201 }
4202
4203 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4204 PKT3_SHADER_TYPE_S(1));
4205 radeon_emit(cs, blocks[0]);
4206 radeon_emit(cs, blocks[1]);
4207 radeon_emit(cs, blocks[2]);
4208 radeon_emit(cs, dispatch_initiator);
4209 }
4210
4211 assert(cmd_buffer->cs->cdw <= cdw_max);
4212 }
4213
4214 static void
4215 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4216 {
4217 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4218 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4219 }
4220
4221 static void
4222 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4223 const struct radv_dispatch_info *info)
4224 {
4225 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4226 bool has_prefetch =
4227 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
4228 bool pipeline_is_dirty = pipeline &&
4229 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4230
4231 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4232 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4233 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4234 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4235 /* If we have to wait for idle, set all states first, so that
4236 * all SET packets are processed in parallel with previous draw
4237 * calls. Then upload descriptors, set shader pointers, and
4238 * dispatch, and prefetch at the end. This ensures that the
4239 * time the CUs are idle is very short. (there are only SET_SH
4240 * packets between the wait and the draw)
4241 */
4242 radv_emit_compute_pipeline(cmd_buffer);
4243 si_emit_cache_flush(cmd_buffer);
4244 /* <-- CUs are idle here --> */
4245
4246 radv_upload_compute_shader_descriptors(cmd_buffer);
4247
4248 radv_emit_dispatch_packets(cmd_buffer, info);
4249 /* <-- CUs are busy here --> */
4250
4251 /* Start prefetches after the dispatch has been started. Both
4252 * will run in parallel, but starting the dispatch first is
4253 * more important.
4254 */
4255 if (has_prefetch && pipeline_is_dirty) {
4256 radv_emit_shader_prefetch(cmd_buffer,
4257 pipeline->shaders[MESA_SHADER_COMPUTE]);
4258 }
4259 } else {
4260 /* If we don't wait for idle, start prefetches first, then set
4261 * states, and dispatch at the end.
4262 */
4263 si_emit_cache_flush(cmd_buffer);
4264
4265 if (has_prefetch && pipeline_is_dirty) {
4266 radv_emit_shader_prefetch(cmd_buffer,
4267 pipeline->shaders[MESA_SHADER_COMPUTE]);
4268 }
4269
4270 radv_upload_compute_shader_descriptors(cmd_buffer);
4271
4272 radv_emit_compute_pipeline(cmd_buffer);
4273 radv_emit_dispatch_packets(cmd_buffer, info);
4274 }
4275
4276 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4277 }
4278
4279 void radv_CmdDispatchBase(
4280 VkCommandBuffer commandBuffer,
4281 uint32_t base_x,
4282 uint32_t base_y,
4283 uint32_t base_z,
4284 uint32_t x,
4285 uint32_t y,
4286 uint32_t z)
4287 {
4288 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4289 struct radv_dispatch_info info = {};
4290
4291 info.blocks[0] = x;
4292 info.blocks[1] = y;
4293 info.blocks[2] = z;
4294
4295 info.offsets[0] = base_x;
4296 info.offsets[1] = base_y;
4297 info.offsets[2] = base_z;
4298 radv_dispatch(cmd_buffer, &info);
4299 }
4300
4301 void radv_CmdDispatch(
4302 VkCommandBuffer commandBuffer,
4303 uint32_t x,
4304 uint32_t y,
4305 uint32_t z)
4306 {
4307 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4308 }
4309
4310 void radv_CmdDispatchIndirect(
4311 VkCommandBuffer commandBuffer,
4312 VkBuffer _buffer,
4313 VkDeviceSize offset)
4314 {
4315 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4316 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4317 struct radv_dispatch_info info = {};
4318
4319 info.indirect = buffer;
4320 info.indirect_offset = offset;
4321
4322 radv_dispatch(cmd_buffer, &info);
4323 }
4324
4325 void radv_unaligned_dispatch(
4326 struct radv_cmd_buffer *cmd_buffer,
4327 uint32_t x,
4328 uint32_t y,
4329 uint32_t z)
4330 {
4331 struct radv_dispatch_info info = {};
4332
4333 info.blocks[0] = x;
4334 info.blocks[1] = y;
4335 info.blocks[2] = z;
4336 info.unaligned = 1;
4337
4338 radv_dispatch(cmd_buffer, &info);
4339 }
4340
4341 void radv_CmdEndRenderPass(
4342 VkCommandBuffer commandBuffer)
4343 {
4344 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4345
4346 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4347
4348 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4349
4350 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
4351 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
4352 radv_handle_subpass_image_transition(cmd_buffer,
4353 (struct radv_subpass_attachment){i, layout});
4354 }
4355
4356 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4357
4358 cmd_buffer->state.pass = NULL;
4359 cmd_buffer->state.subpass = NULL;
4360 cmd_buffer->state.attachments = NULL;
4361 cmd_buffer->state.framebuffer = NULL;
4362 }
4363
4364 void radv_CmdEndRenderPass2KHR(
4365 VkCommandBuffer commandBuffer,
4366 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4367 {
4368 radv_CmdEndRenderPass(commandBuffer);
4369 }
4370
4371 /*
4372 * For HTILE we have the following interesting clear words:
4373 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4374 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4375 * 0xfffffff0: Clear depth to 1.0
4376 * 0x00000000: Clear depth to 0.0
4377 */
4378 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4379 struct radv_image *image,
4380 const VkImageSubresourceRange *range,
4381 uint32_t clear_word)
4382 {
4383 assert(range->baseMipLevel == 0);
4384 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4385 unsigned layer_count = radv_get_layerCount(image, range);
4386 uint64_t size = image->surface.htile_slice_size * layer_count;
4387 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4388 uint64_t offset = image->offset + image->htile_offset +
4389 image->surface.htile_slice_size * range->baseArrayLayer;
4390 struct radv_cmd_state *state = &cmd_buffer->state;
4391 VkClearDepthStencilValue value = {};
4392
4393 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4394 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4395
4396 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4397 size, clear_word);
4398
4399 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4400
4401 if (vk_format_is_stencil(image->vk_format))
4402 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4403
4404 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4405
4406 if (radv_image_is_tc_compat_htile(image)) {
4407 /* Initialize the TC-compat metada value to 0 because by
4408 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4409 * need have to conditionally update its value when performing
4410 * a fast depth clear.
4411 */
4412 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4413 }
4414 }
4415
4416 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4417 struct radv_image *image,
4418 VkImageLayout src_layout,
4419 VkImageLayout dst_layout,
4420 unsigned src_queue_mask,
4421 unsigned dst_queue_mask,
4422 const VkImageSubresourceRange *range)
4423 {
4424 if (!radv_image_has_htile(image))
4425 return;
4426
4427 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4428 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4429 /* TODO: merge with the clear if applicable */
4430 radv_initialize_htile(cmd_buffer, image, range, 0);
4431 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4432 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4433 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4434 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4435 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4436 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4437 VkImageSubresourceRange local_range = *range;
4438 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4439 local_range.baseMipLevel = 0;
4440 local_range.levelCount = 1;
4441
4442 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4443 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4444
4445 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4446
4447 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4448 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4449 }
4450 }
4451
4452 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4453 struct radv_image *image, uint32_t value)
4454 {
4455 struct radv_cmd_state *state = &cmd_buffer->state;
4456
4457 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4458 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4459
4460 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4461
4462 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4463 }
4464
4465 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4466 struct radv_image *image)
4467 {
4468 struct radv_cmd_state *state = &cmd_buffer->state;
4469 static const uint32_t fmask_clear_values[4] = {
4470 0x00000000,
4471 0x02020202,
4472 0xE4E4E4E4,
4473 0x76543210
4474 };
4475 uint32_t log2_samples = util_logbase2(image->info.samples);
4476 uint32_t value = fmask_clear_values[log2_samples];
4477
4478 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4479 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4480
4481 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
4482
4483 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4484 }
4485
4486 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4487 struct radv_image *image, uint32_t value)
4488 {
4489 struct radv_cmd_state *state = &cmd_buffer->state;
4490
4491 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4492 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4493
4494 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4495
4496 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4497 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4498 }
4499
4500 /**
4501 * Initialize DCC/FMASK/CMASK metadata for a color image.
4502 */
4503 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4504 struct radv_image *image,
4505 VkImageLayout src_layout,
4506 VkImageLayout dst_layout,
4507 unsigned src_queue_mask,
4508 unsigned dst_queue_mask)
4509 {
4510 if (radv_image_has_cmask(image)) {
4511 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4512
4513 /* TODO: clarify this. */
4514 if (radv_image_has_fmask(image)) {
4515 value = 0xccccccccu;
4516 }
4517
4518 radv_initialise_cmask(cmd_buffer, image, value);
4519 }
4520
4521 if (radv_image_has_fmask(image)) {
4522 radv_initialize_fmask(cmd_buffer, image);
4523 }
4524
4525 if (radv_image_has_dcc(image)) {
4526 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4527 bool need_decompress_pass = false;
4528
4529 if (radv_layout_dcc_compressed(image, dst_layout,
4530 dst_queue_mask)) {
4531 value = 0x20202020u;
4532 need_decompress_pass = true;
4533 }
4534
4535 radv_initialize_dcc(cmd_buffer, image, value);
4536
4537 radv_update_fce_metadata(cmd_buffer, image,
4538 need_decompress_pass);
4539 }
4540
4541 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4542 uint32_t color_values[2] = {};
4543 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4544 }
4545 }
4546
4547 /**
4548 * Handle color image transitions for DCC/FMASK/CMASK.
4549 */
4550 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4551 struct radv_image *image,
4552 VkImageLayout src_layout,
4553 VkImageLayout dst_layout,
4554 unsigned src_queue_mask,
4555 unsigned dst_queue_mask,
4556 const VkImageSubresourceRange *range)
4557 {
4558 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4559 radv_init_color_image_metadata(cmd_buffer, image,
4560 src_layout, dst_layout,
4561 src_queue_mask, dst_queue_mask);
4562 return;
4563 }
4564
4565 if (radv_image_has_dcc(image)) {
4566 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4567 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4568 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4569 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4570 radv_decompress_dcc(cmd_buffer, image, range);
4571 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4572 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4573 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4574 }
4575 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4576 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4577 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4578 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4579 }
4580
4581 if (radv_image_has_fmask(image)) {
4582 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
4583 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
4584 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
4585 }
4586 }
4587 }
4588 }
4589
4590 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4591 struct radv_image *image,
4592 VkImageLayout src_layout,
4593 VkImageLayout dst_layout,
4594 uint32_t src_family,
4595 uint32_t dst_family,
4596 const VkImageSubresourceRange *range)
4597 {
4598 if (image->exclusive && src_family != dst_family) {
4599 /* This is an acquire or a release operation and there will be
4600 * a corresponding release/acquire. Do the transition in the
4601 * most flexible queue. */
4602
4603 assert(src_family == cmd_buffer->queue_family_index ||
4604 dst_family == cmd_buffer->queue_family_index);
4605
4606 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4607 return;
4608
4609 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4610 (src_family == RADV_QUEUE_GENERAL ||
4611 dst_family == RADV_QUEUE_GENERAL))
4612 return;
4613 }
4614
4615 if (src_layout == dst_layout)
4616 return;
4617
4618 unsigned src_queue_mask =
4619 radv_image_queue_family_mask(image, src_family,
4620 cmd_buffer->queue_family_index);
4621 unsigned dst_queue_mask =
4622 radv_image_queue_family_mask(image, dst_family,
4623 cmd_buffer->queue_family_index);
4624
4625 if (vk_format_is_depth(image->vk_format)) {
4626 radv_handle_depth_image_transition(cmd_buffer, image,
4627 src_layout, dst_layout,
4628 src_queue_mask, dst_queue_mask,
4629 range);
4630 } else {
4631 radv_handle_color_image_transition(cmd_buffer, image,
4632 src_layout, dst_layout,
4633 src_queue_mask, dst_queue_mask,
4634 range);
4635 }
4636 }
4637
4638 struct radv_barrier_info {
4639 uint32_t eventCount;
4640 const VkEvent *pEvents;
4641 VkPipelineStageFlags srcStageMask;
4642 };
4643
4644 static void
4645 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4646 uint32_t memoryBarrierCount,
4647 const VkMemoryBarrier *pMemoryBarriers,
4648 uint32_t bufferMemoryBarrierCount,
4649 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4650 uint32_t imageMemoryBarrierCount,
4651 const VkImageMemoryBarrier *pImageMemoryBarriers,
4652 const struct radv_barrier_info *info)
4653 {
4654 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4655 enum radv_cmd_flush_bits src_flush_bits = 0;
4656 enum radv_cmd_flush_bits dst_flush_bits = 0;
4657
4658 for (unsigned i = 0; i < info->eventCount; ++i) {
4659 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4660 uint64_t va = radv_buffer_get_va(event->bo);
4661
4662 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4663
4664 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4665
4666 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
4667 assert(cmd_buffer->cs->cdw <= cdw_max);
4668 }
4669
4670 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4671 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4672 NULL);
4673 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4674 NULL);
4675 }
4676
4677 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4678 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4679 NULL);
4680 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4681 NULL);
4682 }
4683
4684 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4685 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4686
4687 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4688 image);
4689 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4690 image);
4691 }
4692
4693 radv_stage_flush(cmd_buffer, info->srcStageMask);
4694 cmd_buffer->state.flush_bits |= src_flush_bits;
4695
4696 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4697 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4698 radv_handle_image_transition(cmd_buffer, image,
4699 pImageMemoryBarriers[i].oldLayout,
4700 pImageMemoryBarriers[i].newLayout,
4701 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4702 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4703 &pImageMemoryBarriers[i].subresourceRange);
4704 }
4705
4706 /* Make sure CP DMA is idle because the driver might have performed a
4707 * DMA operation for copying or filling buffers/images.
4708 */
4709 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4710 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4711 si_cp_dma_wait_for_idle(cmd_buffer);
4712
4713 cmd_buffer->state.flush_bits |= dst_flush_bits;
4714 }
4715
4716 void radv_CmdPipelineBarrier(
4717 VkCommandBuffer commandBuffer,
4718 VkPipelineStageFlags srcStageMask,
4719 VkPipelineStageFlags destStageMask,
4720 VkBool32 byRegion,
4721 uint32_t memoryBarrierCount,
4722 const VkMemoryBarrier* pMemoryBarriers,
4723 uint32_t bufferMemoryBarrierCount,
4724 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4725 uint32_t imageMemoryBarrierCount,
4726 const VkImageMemoryBarrier* pImageMemoryBarriers)
4727 {
4728 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4729 struct radv_barrier_info info;
4730
4731 info.eventCount = 0;
4732 info.pEvents = NULL;
4733 info.srcStageMask = srcStageMask;
4734
4735 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4736 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4737 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4738 }
4739
4740
4741 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4742 struct radv_event *event,
4743 VkPipelineStageFlags stageMask,
4744 unsigned value)
4745 {
4746 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4747 uint64_t va = radv_buffer_get_va(event->bo);
4748
4749 si_emit_cache_flush(cmd_buffer);
4750
4751 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4752
4753 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4754
4755 /* Flags that only require a top-of-pipe event. */
4756 VkPipelineStageFlags top_of_pipe_flags =
4757 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4758
4759 /* Flags that only require a post-index-fetch event. */
4760 VkPipelineStageFlags post_index_fetch_flags =
4761 top_of_pipe_flags |
4762 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4763 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4764
4765 /* Make sure CP DMA is idle because the driver might have performed a
4766 * DMA operation for copying or filling buffers/images.
4767 */
4768 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4769 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4770 si_cp_dma_wait_for_idle(cmd_buffer);
4771
4772 /* TODO: Emit EOS events for syncing PS/CS stages. */
4773
4774 if (!(stageMask & ~top_of_pipe_flags)) {
4775 /* Just need to sync the PFP engine. */
4776 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4777 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4778 S_370_WR_CONFIRM(1) |
4779 S_370_ENGINE_SEL(V_370_PFP));
4780 radeon_emit(cs, va);
4781 radeon_emit(cs, va >> 32);
4782 radeon_emit(cs, value);
4783 } else if (!(stageMask & ~post_index_fetch_flags)) {
4784 /* Sync ME because PFP reads index and indirect buffers. */
4785 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4786 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4787 S_370_WR_CONFIRM(1) |
4788 S_370_ENGINE_SEL(V_370_ME));
4789 radeon_emit(cs, va);
4790 radeon_emit(cs, va >> 32);
4791 radeon_emit(cs, value);
4792 } else {
4793 /* Otherwise, sync all prior GPU work using an EOP event. */
4794 si_cs_emit_write_event_eop(cs,
4795 cmd_buffer->device->physical_device->rad_info.chip_class,
4796 radv_cmd_buffer_uses_mec(cmd_buffer),
4797 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4798 EOP_DATA_SEL_VALUE_32BIT, va, value,
4799 cmd_buffer->gfx9_eop_bug_va);
4800 }
4801
4802 assert(cmd_buffer->cs->cdw <= cdw_max);
4803 }
4804
4805 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4806 VkEvent _event,
4807 VkPipelineStageFlags stageMask)
4808 {
4809 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4810 RADV_FROM_HANDLE(radv_event, event, _event);
4811
4812 write_event(cmd_buffer, event, stageMask, 1);
4813 }
4814
4815 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4816 VkEvent _event,
4817 VkPipelineStageFlags stageMask)
4818 {
4819 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4820 RADV_FROM_HANDLE(radv_event, event, _event);
4821
4822 write_event(cmd_buffer, event, stageMask, 0);
4823 }
4824
4825 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4826 uint32_t eventCount,
4827 const VkEvent* pEvents,
4828 VkPipelineStageFlags srcStageMask,
4829 VkPipelineStageFlags dstStageMask,
4830 uint32_t memoryBarrierCount,
4831 const VkMemoryBarrier* pMemoryBarriers,
4832 uint32_t bufferMemoryBarrierCount,
4833 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4834 uint32_t imageMemoryBarrierCount,
4835 const VkImageMemoryBarrier* pImageMemoryBarriers)
4836 {
4837 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4838 struct radv_barrier_info info;
4839
4840 info.eventCount = eventCount;
4841 info.pEvents = pEvents;
4842 info.srcStageMask = 0;
4843
4844 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4845 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4846 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4847 }
4848
4849
4850 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4851 uint32_t deviceMask)
4852 {
4853 /* No-op */
4854 }
4855
4856 /* VK_EXT_conditional_rendering */
4857 void radv_CmdBeginConditionalRenderingEXT(
4858 VkCommandBuffer commandBuffer,
4859 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4860 {
4861 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4862 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4863 bool draw_visible = true;
4864 uint64_t va;
4865
4866 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4867
4868 /* By default, if the 32-bit value at offset in buffer memory is zero,
4869 * then the rendering commands are discarded, otherwise they are
4870 * executed as normal. If the inverted flag is set, all commands are
4871 * discarded if the value is non zero.
4872 */
4873 if (pConditionalRenderingBegin->flags &
4874 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4875 draw_visible = false;
4876 }
4877
4878 si_emit_cache_flush(cmd_buffer);
4879
4880 /* Enable predication for this command buffer. */
4881 si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4882 cmd_buffer->state.predicating = true;
4883
4884 /* Store conditional rendering user info. */
4885 cmd_buffer->state.predication_type = draw_visible;
4886 cmd_buffer->state.predication_va = va;
4887 }
4888
4889 void radv_CmdEndConditionalRenderingEXT(
4890 VkCommandBuffer commandBuffer)
4891 {
4892 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4893
4894 /* Disable predication for this command buffer. */
4895 si_emit_set_predication_state(cmd_buffer, false, 0);
4896 cmd_buffer->state.predicating = false;
4897
4898 /* Reset conditional rendering user info. */
4899 cmd_buffer->state.predication_type = -1;
4900 cmd_buffer->state.predication_va = 0;
4901 }
4902
4903 /* VK_EXT_transform_feedback */
4904 void radv_CmdBindTransformFeedbackBuffersEXT(
4905 VkCommandBuffer commandBuffer,
4906 uint32_t firstBinding,
4907 uint32_t bindingCount,
4908 const VkBuffer* pBuffers,
4909 const VkDeviceSize* pOffsets,
4910 const VkDeviceSize* pSizes)
4911 {
4912 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4913 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4914 uint8_t enabled_mask = 0;
4915
4916 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
4917 for (uint32_t i = 0; i < bindingCount; i++) {
4918 uint32_t idx = firstBinding + i;
4919
4920 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
4921 sb[idx].offset = pOffsets[i];
4922 sb[idx].size = pSizes[i];
4923
4924 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4925 sb[idx].buffer->bo);
4926
4927 enabled_mask |= 1 << idx;
4928 }
4929
4930 cmd_buffer->state.streamout.enabled_mask = enabled_mask;
4931
4932 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
4933 }
4934
4935 static void
4936 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
4937 {
4938 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4939 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4940
4941 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
4942 radeon_emit(cs,
4943 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
4944 S_028B94_RAST_STREAM(0) |
4945 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
4946 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
4947 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
4948 radeon_emit(cs, so->hw_enabled_mask &
4949 so->enabled_stream_buffers_mask);
4950
4951 cmd_buffer->state.context_roll_without_scissor_emitted = true;
4952 }
4953
4954 static void
4955 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
4956 {
4957 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4958 bool old_streamout_enabled = so->streamout_enabled;
4959 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
4960
4961 so->streamout_enabled = enable;
4962
4963 so->hw_enabled_mask = so->enabled_mask |
4964 (so->enabled_mask << 4) |
4965 (so->enabled_mask << 8) |
4966 (so->enabled_mask << 12);
4967
4968 if ((old_streamout_enabled != so->streamout_enabled) ||
4969 (old_hw_enabled_mask != so->hw_enabled_mask))
4970 radv_emit_streamout_enable(cmd_buffer);
4971 }
4972
4973 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
4974 {
4975 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4976 unsigned reg_strmout_cntl;
4977
4978 /* The register is at different places on different ASICs. */
4979 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
4980 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
4981 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
4982 } else {
4983 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
4984 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
4985 }
4986
4987 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4988 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
4989
4990 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
4991 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
4992 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
4993 radeon_emit(cs, 0);
4994 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
4995 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
4996 radeon_emit(cs, 4); /* poll interval */
4997 }
4998
4999 void radv_CmdBeginTransformFeedbackEXT(
5000 VkCommandBuffer commandBuffer,
5001 uint32_t firstCounterBuffer,
5002 uint32_t counterBufferCount,
5003 const VkBuffer* pCounterBuffers,
5004 const VkDeviceSize* pCounterBufferOffsets)
5005 {
5006 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5007 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5008 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5009 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5010 uint32_t i;
5011
5012 radv_flush_vgt_streamout(cmd_buffer);
5013
5014 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5015 for_each_bit(i, so->enabled_mask) {
5016 int32_t counter_buffer_idx = i - firstCounterBuffer;
5017 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5018 counter_buffer_idx = -1;
5019
5020 /* SI binds streamout buffers as shader resources.
5021 * VGT only counts primitives and tells the shader through
5022 * SGPRs what to do.
5023 */
5024 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5025 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5026 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5027
5028 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5029
5030 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5031 /* The array of counter buffers is optional. */
5032 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5033 uint64_t va = radv_buffer_get_va(buffer->bo);
5034
5035 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5036
5037 /* Append */
5038 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5039 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5040 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5041 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5042 radeon_emit(cs, 0); /* unused */
5043 radeon_emit(cs, 0); /* unused */
5044 radeon_emit(cs, va); /* src address lo */
5045 radeon_emit(cs, va >> 32); /* src address hi */
5046
5047 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5048 } else {
5049 /* Start from the beginning. */
5050 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5051 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5052 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5053 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5054 radeon_emit(cs, 0); /* unused */
5055 radeon_emit(cs, 0); /* unused */
5056 radeon_emit(cs, 0); /* unused */
5057 radeon_emit(cs, 0); /* unused */
5058 }
5059 }
5060
5061 radv_set_streamout_enable(cmd_buffer, true);
5062 }
5063
5064 void radv_CmdEndTransformFeedbackEXT(
5065 VkCommandBuffer commandBuffer,
5066 uint32_t firstCounterBuffer,
5067 uint32_t counterBufferCount,
5068 const VkBuffer* pCounterBuffers,
5069 const VkDeviceSize* pCounterBufferOffsets)
5070 {
5071 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5072 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5073 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5074 uint32_t i;
5075
5076 radv_flush_vgt_streamout(cmd_buffer);
5077
5078 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5079 for_each_bit(i, so->enabled_mask) {
5080 int32_t counter_buffer_idx = i - firstCounterBuffer;
5081 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5082 counter_buffer_idx = -1;
5083
5084 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5085 /* The array of counters buffer is optional. */
5086 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5087 uint64_t va = radv_buffer_get_va(buffer->bo);
5088
5089 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5090
5091 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5092 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5093 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5094 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5095 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5096 radeon_emit(cs, va); /* dst address lo */
5097 radeon_emit(cs, va >> 32); /* dst address hi */
5098 radeon_emit(cs, 0); /* unused */
5099 radeon_emit(cs, 0); /* unused */
5100
5101 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5102 }
5103
5104 /* Deactivate transform feedback by zeroing the buffer size.
5105 * The counters (primitives generated, primitives emitted) may
5106 * be enabled even if there is not buffer bound. This ensures
5107 * that the primitives-emitted query won't increment.
5108 */
5109 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5110
5111 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5112 }
5113
5114 radv_set_streamout_enable(cmd_buffer, false);
5115 }
5116
5117 void radv_CmdDrawIndirectByteCountEXT(
5118 VkCommandBuffer commandBuffer,
5119 uint32_t instanceCount,
5120 uint32_t firstInstance,
5121 VkBuffer _counterBuffer,
5122 VkDeviceSize counterBufferOffset,
5123 uint32_t counterOffset,
5124 uint32_t vertexStride)
5125 {
5126 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5127 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5128 struct radv_draw_info info = {};
5129
5130 info.instance_count = instanceCount;
5131 info.first_instance = firstInstance;
5132 info.strmout_buffer = counterBuffer;
5133 info.strmout_buffer_offset = counterBufferOffset;
5134 info.stride = vertexStride;
5135
5136 radv_draw(cmd_buffer, &info);
5137 }