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radv/gfx10: add a separate flag for creating a GDS OA buffer
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 };
96
97 static void
98 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
99 const struct radv_dynamic_state *src)
100 {
101 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
102 uint32_t copy_mask = src->mask;
103 uint32_t dest_mask = 0;
104
105 /* Make sure to copy the number of viewports/scissors because they can
106 * only be specified at pipeline creation time.
107 */
108 dest->viewport.count = src->viewport.count;
109 dest->scissor.count = src->scissor.count;
110 dest->discard_rectangle.count = src->discard_rectangle.count;
111 dest->sample_location.count = src->sample_location.count;
112
113 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
114 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
115 src->viewport.count * sizeof(VkViewport))) {
116 typed_memcpy(dest->viewport.viewports,
117 src->viewport.viewports,
118 src->viewport.count);
119 dest_mask |= RADV_DYNAMIC_VIEWPORT;
120 }
121 }
122
123 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
124 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
125 src->scissor.count * sizeof(VkRect2D))) {
126 typed_memcpy(dest->scissor.scissors,
127 src->scissor.scissors, src->scissor.count);
128 dest_mask |= RADV_DYNAMIC_SCISSOR;
129 }
130 }
131
132 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
133 if (dest->line_width != src->line_width) {
134 dest->line_width = src->line_width;
135 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
136 }
137 }
138
139 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
140 if (memcmp(&dest->depth_bias, &src->depth_bias,
141 sizeof(src->depth_bias))) {
142 dest->depth_bias = src->depth_bias;
143 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
144 }
145 }
146
147 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
148 if (memcmp(&dest->blend_constants, &src->blend_constants,
149 sizeof(src->blend_constants))) {
150 typed_memcpy(dest->blend_constants,
151 src->blend_constants, 4);
152 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
153 }
154 }
155
156 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
157 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
158 sizeof(src->depth_bounds))) {
159 dest->depth_bounds = src->depth_bounds;
160 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
161 }
162 }
163
164 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
165 if (memcmp(&dest->stencil_compare_mask,
166 &src->stencil_compare_mask,
167 sizeof(src->stencil_compare_mask))) {
168 dest->stencil_compare_mask = src->stencil_compare_mask;
169 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
170 }
171 }
172
173 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
174 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
175 sizeof(src->stencil_write_mask))) {
176 dest->stencil_write_mask = src->stencil_write_mask;
177 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
178 }
179 }
180
181 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
182 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
183 sizeof(src->stencil_reference))) {
184 dest->stencil_reference = src->stencil_reference;
185 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
186 }
187 }
188
189 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
190 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
191 src->discard_rectangle.count * sizeof(VkRect2D))) {
192 typed_memcpy(dest->discard_rectangle.rectangles,
193 src->discard_rectangle.rectangles,
194 src->discard_rectangle.count);
195 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
196 }
197 }
198
199 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
200 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
201 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
202 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
203 memcmp(&dest->sample_location.locations,
204 &src->sample_location.locations,
205 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
206 dest->sample_location.per_pixel = src->sample_location.per_pixel;
207 dest->sample_location.grid_size = src->sample_location.grid_size;
208 typed_memcpy(dest->sample_location.locations,
209 src->sample_location.locations,
210 src->sample_location.count);
211 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
212 }
213 }
214
215 cmd_buffer->state.dirty |= dest_mask;
216 }
217
218 static void
219 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
220 struct radv_pipeline *pipeline)
221 {
222 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
223 struct radv_shader_info *info;
224
225 if (!pipeline->streamout_shader ||
226 cmd_buffer->device->physical_device->use_ngg_streamout)
227 return;
228
229 info = &pipeline->streamout_shader->info;
230 for (int i = 0; i < MAX_SO_BUFFERS; i++)
231 so->stride_in_dw[i] = info->so.strides[i];
232
233 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
234 }
235
236 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
237 {
238 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
239 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
240 }
241
242 enum ring_type radv_queue_family_to_ring(int f) {
243 switch (f) {
244 case RADV_QUEUE_GENERAL:
245 return RING_GFX;
246 case RADV_QUEUE_COMPUTE:
247 return RING_COMPUTE;
248 case RADV_QUEUE_TRANSFER:
249 return RING_DMA;
250 default:
251 unreachable("Unknown queue family");
252 }
253 }
254
255 static VkResult radv_create_cmd_buffer(
256 struct radv_device * device,
257 struct radv_cmd_pool * pool,
258 VkCommandBufferLevel level,
259 VkCommandBuffer* pCommandBuffer)
260 {
261 struct radv_cmd_buffer *cmd_buffer;
262 unsigned ring;
263 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
264 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
265 if (cmd_buffer == NULL)
266 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
267
268 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
269 cmd_buffer->device = device;
270 cmd_buffer->pool = pool;
271 cmd_buffer->level = level;
272
273 if (pool) {
274 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
275 cmd_buffer->queue_family_index = pool->queue_family_index;
276
277 } else {
278 /* Init the pool_link so we can safely call list_del when we destroy
279 * the command buffer
280 */
281 list_inithead(&cmd_buffer->pool_link);
282 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
283 }
284
285 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
286
287 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
288 if (!cmd_buffer->cs) {
289 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
290 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
291 }
292
293 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
294
295 list_inithead(&cmd_buffer->upload.list);
296
297 return VK_SUCCESS;
298 }
299
300 static void
301 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
302 {
303 list_del(&cmd_buffer->pool_link);
304
305 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
306 &cmd_buffer->upload.list, list) {
307 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
308 list_del(&up->list);
309 free(up);
310 }
311
312 if (cmd_buffer->upload.upload_bo)
313 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
314 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
315
316 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
317 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
318
319 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
320 }
321
322 static VkResult
323 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
324 {
325 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
326
327 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
328 &cmd_buffer->upload.list, list) {
329 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
330 list_del(&up->list);
331 free(up);
332 }
333
334 cmd_buffer->push_constant_stages = 0;
335 cmd_buffer->scratch_size_per_wave_needed = 0;
336 cmd_buffer->scratch_waves_wanted = 0;
337 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
338 cmd_buffer->compute_scratch_waves_wanted = 0;
339 cmd_buffer->esgs_ring_size_needed = 0;
340 cmd_buffer->gsvs_ring_size_needed = 0;
341 cmd_buffer->tess_rings_needed = false;
342 cmd_buffer->gds_needed = false;
343 cmd_buffer->gds_oa_needed = false;
344 cmd_buffer->sample_positions_needed = false;
345
346 if (cmd_buffer->upload.upload_bo)
347 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
348 cmd_buffer->upload.upload_bo);
349 cmd_buffer->upload.offset = 0;
350
351 cmd_buffer->record_result = VK_SUCCESS;
352
353 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
354
355 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
356 cmd_buffer->descriptors[i].dirty = 0;
357 cmd_buffer->descriptors[i].valid = 0;
358 cmd_buffer->descriptors[i].push_dirty = false;
359 }
360
361 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
362 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
363 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
364 unsigned fence_offset, eop_bug_offset;
365 void *fence_ptr;
366
367 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
368 &fence_ptr);
369
370 cmd_buffer->gfx9_fence_va =
371 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
372 cmd_buffer->gfx9_fence_va += fence_offset;
373
374 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
375 /* Allocate a buffer for the EOP bug on GFX9. */
376 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
377 &eop_bug_offset, &fence_ptr);
378 cmd_buffer->gfx9_eop_bug_va =
379 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
380 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
381 }
382 }
383
384 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
385
386 return cmd_buffer->record_result;
387 }
388
389 static bool
390 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
391 uint64_t min_needed)
392 {
393 uint64_t new_size;
394 struct radeon_winsys_bo *bo;
395 struct radv_cmd_buffer_upload *upload;
396 struct radv_device *device = cmd_buffer->device;
397
398 new_size = MAX2(min_needed, 16 * 1024);
399 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
400
401 bo = device->ws->buffer_create(device->ws,
402 new_size, 4096,
403 RADEON_DOMAIN_GTT,
404 RADEON_FLAG_CPU_ACCESS|
405 RADEON_FLAG_NO_INTERPROCESS_SHARING |
406 RADEON_FLAG_32BIT,
407 RADV_BO_PRIORITY_UPLOAD_BUFFER);
408
409 if (!bo) {
410 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
411 return false;
412 }
413
414 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
415 if (cmd_buffer->upload.upload_bo) {
416 upload = malloc(sizeof(*upload));
417
418 if (!upload) {
419 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
420 device->ws->buffer_destroy(bo);
421 return false;
422 }
423
424 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
425 list_add(&upload->list, &cmd_buffer->upload.list);
426 }
427
428 cmd_buffer->upload.upload_bo = bo;
429 cmd_buffer->upload.size = new_size;
430 cmd_buffer->upload.offset = 0;
431 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
432
433 if (!cmd_buffer->upload.map) {
434 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
435 return false;
436 }
437
438 return true;
439 }
440
441 bool
442 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
443 unsigned size,
444 unsigned alignment,
445 unsigned *out_offset,
446 void **ptr)
447 {
448 assert(util_is_power_of_two_nonzero(alignment));
449
450 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
451 if (offset + size > cmd_buffer->upload.size) {
452 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
453 return false;
454 offset = 0;
455 }
456
457 *out_offset = offset;
458 *ptr = cmd_buffer->upload.map + offset;
459
460 cmd_buffer->upload.offset = offset + size;
461 return true;
462 }
463
464 bool
465 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
466 unsigned size, unsigned alignment,
467 const void *data, unsigned *out_offset)
468 {
469 uint8_t *ptr;
470
471 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
472 out_offset, (void **)&ptr))
473 return false;
474
475 if (ptr)
476 memcpy(ptr, data, size);
477
478 return true;
479 }
480
481 static void
482 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
483 unsigned count, const uint32_t *data)
484 {
485 struct radeon_cmdbuf *cs = cmd_buffer->cs;
486
487 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
488
489 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
490 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
491 S_370_WR_CONFIRM(1) |
492 S_370_ENGINE_SEL(V_370_ME));
493 radeon_emit(cs, va);
494 radeon_emit(cs, va >> 32);
495 radeon_emit_array(cs, data, count);
496 }
497
498 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
499 {
500 struct radv_device *device = cmd_buffer->device;
501 struct radeon_cmdbuf *cs = cmd_buffer->cs;
502 uint64_t va;
503
504 va = radv_buffer_get_va(device->trace_bo);
505 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
506 va += 4;
507
508 ++cmd_buffer->state.trace_id;
509 radv_emit_write_data_packet(cmd_buffer, va, 1,
510 &cmd_buffer->state.trace_id);
511
512 radeon_check_space(cmd_buffer->device->ws, cs, 2);
513
514 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
515 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
516 }
517
518 static void
519 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
520 enum radv_cmd_flush_bits flags)
521 {
522 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
523 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
524 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
525
526 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
527
528 /* Force wait for graphics or compute engines to be idle. */
529 si_cs_emit_cache_flush(cmd_buffer->cs,
530 cmd_buffer->device->physical_device->rad_info.chip_class,
531 &cmd_buffer->gfx9_fence_idx,
532 cmd_buffer->gfx9_fence_va,
533 radv_cmd_buffer_uses_mec(cmd_buffer),
534 flags, cmd_buffer->gfx9_eop_bug_va);
535 }
536
537 if (unlikely(cmd_buffer->device->trace_bo))
538 radv_cmd_buffer_trace_emit(cmd_buffer);
539 }
540
541 static void
542 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
543 struct radv_pipeline *pipeline, enum ring_type ring)
544 {
545 struct radv_device *device = cmd_buffer->device;
546 uint32_t data[2];
547 uint64_t va;
548
549 va = radv_buffer_get_va(device->trace_bo);
550
551 switch (ring) {
552 case RING_GFX:
553 va += 8;
554 break;
555 case RING_COMPUTE:
556 va += 16;
557 break;
558 default:
559 assert(!"invalid ring type");
560 }
561
562 uint64_t pipeline_address = (uintptr_t)pipeline;
563 data[0] = pipeline_address;
564 data[1] = pipeline_address >> 32;
565
566 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
567 }
568
569 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
570 VkPipelineBindPoint bind_point,
571 struct radv_descriptor_set *set,
572 unsigned idx)
573 {
574 struct radv_descriptor_state *descriptors_state =
575 radv_get_descriptors_state(cmd_buffer, bind_point);
576
577 descriptors_state->sets[idx] = set;
578
579 descriptors_state->valid |= (1u << idx); /* active descriptors */
580 descriptors_state->dirty |= (1u << idx);
581 }
582
583 static void
584 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
585 VkPipelineBindPoint bind_point)
586 {
587 struct radv_descriptor_state *descriptors_state =
588 radv_get_descriptors_state(cmd_buffer, bind_point);
589 struct radv_device *device = cmd_buffer->device;
590 uint32_t data[MAX_SETS * 2] = {};
591 uint64_t va;
592 unsigned i;
593 va = radv_buffer_get_va(device->trace_bo) + 24;
594
595 for_each_bit(i, descriptors_state->valid) {
596 struct radv_descriptor_set *set = descriptors_state->sets[i];
597 data[i * 2] = (uint64_t)(uintptr_t)set;
598 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
599 }
600
601 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
602 }
603
604 struct radv_userdata_info *
605 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
606 gl_shader_stage stage,
607 int idx)
608 {
609 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
610 return &shader->info.user_sgprs_locs.shader_data[idx];
611 }
612
613 static void
614 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
615 struct radv_pipeline *pipeline,
616 gl_shader_stage stage,
617 int idx, uint64_t va)
618 {
619 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
620 uint32_t base_reg = pipeline->user_data_0[stage];
621 if (loc->sgpr_idx == -1)
622 return;
623
624 assert(loc->num_sgprs == 1);
625
626 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
627 base_reg + loc->sgpr_idx * 4, va, false);
628 }
629
630 static void
631 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
632 struct radv_pipeline *pipeline,
633 struct radv_descriptor_state *descriptors_state,
634 gl_shader_stage stage)
635 {
636 struct radv_device *device = cmd_buffer->device;
637 struct radeon_cmdbuf *cs = cmd_buffer->cs;
638 uint32_t sh_base = pipeline->user_data_0[stage];
639 struct radv_userdata_locations *locs =
640 &pipeline->shaders[stage]->info.user_sgprs_locs;
641 unsigned mask = locs->descriptor_sets_enabled;
642
643 mask &= descriptors_state->dirty & descriptors_state->valid;
644
645 while (mask) {
646 int start, count;
647
648 u_bit_scan_consecutive_range(&mask, &start, &count);
649
650 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
651 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
652
653 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
654 for (int i = 0; i < count; i++) {
655 struct radv_descriptor_set *set =
656 descriptors_state->sets[start + i];
657
658 radv_emit_shader_pointer_body(device, cs, set->va, true);
659 }
660 }
661 }
662
663 /**
664 * Convert the user sample locations to hardware sample locations (the values
665 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
666 */
667 static void
668 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
669 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
670 {
671 uint32_t x_offset = x % state->grid_size.width;
672 uint32_t y_offset = y % state->grid_size.height;
673 uint32_t num_samples = (uint32_t)state->per_pixel;
674 VkSampleLocationEXT *user_locs;
675 uint32_t pixel_offset;
676
677 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
678
679 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
680 user_locs = &state->locations[pixel_offset];
681
682 for (uint32_t i = 0; i < num_samples; i++) {
683 float shifted_pos_x = user_locs[i].x - 0.5;
684 float shifted_pos_y = user_locs[i].y - 0.5;
685
686 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
687 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
688
689 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
690 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
691 }
692 }
693
694 /**
695 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
696 * locations.
697 */
698 static void
699 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
700 uint32_t *sample_locs_pixel)
701 {
702 for (uint32_t i = 0; i < num_samples; i++) {
703 uint32_t sample_reg_idx = i / 4;
704 uint32_t sample_loc_idx = i % 4;
705 int32_t pos_x = sample_locs[i].x;
706 int32_t pos_y = sample_locs[i].y;
707
708 uint32_t shift_x = 8 * sample_loc_idx;
709 uint32_t shift_y = shift_x + 4;
710
711 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
712 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
713 }
714 }
715
716 /**
717 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
718 * sample locations.
719 */
720 static uint64_t
721 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
722 VkOffset2D *sample_locs,
723 uint32_t num_samples)
724 {
725 uint32_t centroid_priorities[num_samples];
726 uint32_t sample_mask = num_samples - 1;
727 uint32_t distances[num_samples];
728 uint64_t centroid_priority = 0;
729
730 /* Compute the distances from center for each sample. */
731 for (int i = 0; i < num_samples; i++) {
732 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
733 (sample_locs[i].y * sample_locs[i].y);
734 }
735
736 /* Compute the centroid priorities by looking at the distances array. */
737 for (int i = 0; i < num_samples; i++) {
738 uint32_t min_idx = 0;
739
740 for (int j = 1; j < num_samples; j++) {
741 if (distances[j] < distances[min_idx])
742 min_idx = j;
743 }
744
745 centroid_priorities[i] = min_idx;
746 distances[min_idx] = 0xffffffff;
747 }
748
749 /* Compute the final centroid priority. */
750 for (int i = 0; i < 8; i++) {
751 centroid_priority |=
752 centroid_priorities[i & sample_mask] << (i * 4);
753 }
754
755 return centroid_priority << 32 | centroid_priority;
756 }
757
758 /**
759 * Emit the sample locations that are specified with VK_EXT_sample_locations.
760 */
761 static void
762 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
763 {
764 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
765 struct radv_multisample_state *ms = &pipeline->graphics.ms;
766 struct radv_sample_locations_state *sample_location =
767 &cmd_buffer->state.dynamic.sample_location;
768 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
769 struct radeon_cmdbuf *cs = cmd_buffer->cs;
770 uint32_t sample_locs_pixel[4][2] = {};
771 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
772 uint32_t max_sample_dist = 0;
773 uint64_t centroid_priority;
774
775 if (!cmd_buffer->state.dynamic.sample_location.count)
776 return;
777
778 /* Convert the user sample locations to hardware sample locations. */
779 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
780 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
781 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
782 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
783
784 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
785 for (uint32_t i = 0; i < 4; i++) {
786 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
787 sample_locs_pixel[i]);
788 }
789
790 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
791 centroid_priority =
792 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
793 num_samples);
794
795 /* Compute the maximum sample distance from the specified locations. */
796 for (uint32_t i = 0; i < num_samples; i++) {
797 VkOffset2D offset = sample_locs[0][i];
798 max_sample_dist = MAX2(max_sample_dist,
799 MAX2(abs(offset.x), abs(offset.y)));
800 }
801
802 /* Emit the specified user sample locations. */
803 switch (num_samples) {
804 case 2:
805 case 4:
806 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
807 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
808 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
809 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
810 break;
811 case 8:
812 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
813 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
814 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
815 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
816 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
817 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
818 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
819 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
820 break;
821 default:
822 unreachable("invalid number of samples");
823 }
824
825 /* Emit the maximum sample distance and the centroid priority. */
826 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
827
828 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
829 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
830
831 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
832 radeon_emit(cs, pa_sc_aa_config);
833
834 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
835 radeon_emit(cs, centroid_priority);
836 radeon_emit(cs, centroid_priority >> 32);
837
838 /* GFX9: Flush DFSM when the AA mode changes. */
839 if (cmd_buffer->device->dfsm_allowed) {
840 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
841 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
842 }
843
844 cmd_buffer->state.context_roll_without_scissor_emitted = true;
845 }
846
847 static void
848 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
849 struct radv_pipeline *pipeline,
850 gl_shader_stage stage,
851 int idx, int count, uint32_t *values)
852 {
853 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
854 uint32_t base_reg = pipeline->user_data_0[stage];
855 if (loc->sgpr_idx == -1)
856 return;
857
858 assert(loc->num_sgprs == count);
859
860 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
861 radeon_emit_array(cmd_buffer->cs, values, count);
862 }
863
864 static void
865 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
866 struct radv_pipeline *pipeline)
867 {
868 int num_samples = pipeline->graphics.ms.num_samples;
869 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
870
871 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
872 cmd_buffer->sample_positions_needed = true;
873
874 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
875 return;
876
877 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
878
879 cmd_buffer->state.context_roll_without_scissor_emitted = true;
880 }
881
882 static void
883 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
884 struct radv_pipeline *pipeline)
885 {
886 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
887
888
889 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
890 return;
891
892 if (old_pipeline &&
893 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
894 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
895 return;
896
897 bool binning_flush = false;
898 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
899 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
900 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
901 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
902 binning_flush = !old_pipeline ||
903 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
904 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
905 }
906
907 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
908 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
909 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
910
911 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
912 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
913 pipeline->graphics.binning.db_dfsm_control);
914 } else {
915 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
916 pipeline->graphics.binning.db_dfsm_control);
917 }
918
919 cmd_buffer->state.context_roll_without_scissor_emitted = true;
920 }
921
922
923 static void
924 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
925 struct radv_shader_variant *shader)
926 {
927 uint64_t va;
928
929 if (!shader)
930 return;
931
932 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
933
934 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
935 }
936
937 static void
938 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
939 struct radv_pipeline *pipeline,
940 bool vertex_stage_only)
941 {
942 struct radv_cmd_state *state = &cmd_buffer->state;
943 uint32_t mask = state->prefetch_L2_mask;
944
945 if (vertex_stage_only) {
946 /* Fast prefetch path for starting draws as soon as possible.
947 */
948 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
949 RADV_PREFETCH_VBO_DESCRIPTORS);
950 }
951
952 if (mask & RADV_PREFETCH_VS)
953 radv_emit_shader_prefetch(cmd_buffer,
954 pipeline->shaders[MESA_SHADER_VERTEX]);
955
956 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
957 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
958
959 if (mask & RADV_PREFETCH_TCS)
960 radv_emit_shader_prefetch(cmd_buffer,
961 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
962
963 if (mask & RADV_PREFETCH_TES)
964 radv_emit_shader_prefetch(cmd_buffer,
965 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
966
967 if (mask & RADV_PREFETCH_GS) {
968 radv_emit_shader_prefetch(cmd_buffer,
969 pipeline->shaders[MESA_SHADER_GEOMETRY]);
970 if (radv_pipeline_has_gs_copy_shader(pipeline))
971 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
972 }
973
974 if (mask & RADV_PREFETCH_PS)
975 radv_emit_shader_prefetch(cmd_buffer,
976 pipeline->shaders[MESA_SHADER_FRAGMENT]);
977
978 state->prefetch_L2_mask &= ~mask;
979 }
980
981 static void
982 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
983 {
984 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
985 return;
986
987 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
988 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
989
990 unsigned sx_ps_downconvert = 0;
991 unsigned sx_blend_opt_epsilon = 0;
992 unsigned sx_blend_opt_control = 0;
993
994 if (!cmd_buffer->state.attachments || !subpass)
995 return;
996
997 for (unsigned i = 0; i < subpass->color_count; ++i) {
998 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
999 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1000 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1001 continue;
1002 }
1003
1004 int idx = subpass->color_attachments[i].attachment;
1005 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1006
1007 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1008 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1009 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1010 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1011
1012 bool has_alpha, has_rgb;
1013
1014 /* Set if RGB and A are present. */
1015 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1016
1017 if (format == V_028C70_COLOR_8 ||
1018 format == V_028C70_COLOR_16 ||
1019 format == V_028C70_COLOR_32)
1020 has_rgb = !has_alpha;
1021 else
1022 has_rgb = true;
1023
1024 /* Check the colormask and export format. */
1025 if (!(colormask & 0x7))
1026 has_rgb = false;
1027 if (!(colormask & 0x8))
1028 has_alpha = false;
1029
1030 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1031 has_rgb = false;
1032 has_alpha = false;
1033 }
1034
1035 /* Disable value checking for disabled channels. */
1036 if (!has_rgb)
1037 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1038 if (!has_alpha)
1039 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1040
1041 /* Enable down-conversion for 32bpp and smaller formats. */
1042 switch (format) {
1043 case V_028C70_COLOR_8:
1044 case V_028C70_COLOR_8_8:
1045 case V_028C70_COLOR_8_8_8_8:
1046 /* For 1 and 2-channel formats, use the superset thereof. */
1047 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1048 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1049 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1050 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1051 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1052 }
1053 break;
1054
1055 case V_028C70_COLOR_5_6_5:
1056 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1057 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1058 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1059 }
1060 break;
1061
1062 case V_028C70_COLOR_1_5_5_5:
1063 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1064 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1065 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1066 }
1067 break;
1068
1069 case V_028C70_COLOR_4_4_4_4:
1070 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1071 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1072 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1073 }
1074 break;
1075
1076 case V_028C70_COLOR_32:
1077 if (swap == V_028C70_SWAP_STD &&
1078 spi_format == V_028714_SPI_SHADER_32_R)
1079 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1080 else if (swap == V_028C70_SWAP_ALT_REV &&
1081 spi_format == V_028714_SPI_SHADER_32_AR)
1082 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1083 break;
1084
1085 case V_028C70_COLOR_16:
1086 case V_028C70_COLOR_16_16:
1087 /* For 1-channel formats, use the superset thereof. */
1088 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1089 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1090 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1091 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1092 if (swap == V_028C70_SWAP_STD ||
1093 swap == V_028C70_SWAP_STD_REV)
1094 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1095 else
1096 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1097 }
1098 break;
1099
1100 case V_028C70_COLOR_10_11_11:
1101 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1102 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1103 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1104 }
1105 break;
1106
1107 case V_028C70_COLOR_2_10_10_10:
1108 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1109 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1110 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1111 }
1112 break;
1113 }
1114 }
1115
1116 for (unsigned i = subpass->color_count; i < 8; ++i) {
1117 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1118 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1119 }
1120 /* TODO: avoid redundantly setting context registers */
1121 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1122 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1123 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1124 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1125
1126 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1127 }
1128
1129 static void
1130 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1131 {
1132 if (!cmd_buffer->device->pbb_allowed)
1133 return;
1134
1135 struct radv_binning_settings settings =
1136 radv_get_binning_settings(cmd_buffer->device->physical_device);
1137 bool break_for_new_ps =
1138 (!cmd_buffer->state.emitted_pipeline ||
1139 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1140 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1141 (settings.context_states_per_bin > 1 ||
1142 settings.persistent_states_per_bin > 1);
1143 bool break_for_new_cb_target_mask =
1144 (!cmd_buffer->state.emitted_pipeline ||
1145 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1146 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1147 settings.context_states_per_bin > 1;
1148
1149 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1150 return;
1151
1152 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1153 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1154 }
1155
1156 static void
1157 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1158 {
1159 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1160
1161 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1162 return;
1163
1164 radv_update_multisample_state(cmd_buffer, pipeline);
1165 radv_update_binning_state(cmd_buffer, pipeline);
1166
1167 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1168 pipeline->scratch_bytes_per_wave);
1169 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1170 pipeline->max_waves);
1171
1172 if (!cmd_buffer->state.emitted_pipeline ||
1173 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1174 pipeline->graphics.can_use_guardband)
1175 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1176
1177 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1178
1179 if (!cmd_buffer->state.emitted_pipeline ||
1180 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1181 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1182 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1183 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1184 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1185 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1186 }
1187
1188 radv_emit_batch_break_on_new_ps(cmd_buffer);
1189
1190 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1191 if (!pipeline->shaders[i])
1192 continue;
1193
1194 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1195 pipeline->shaders[i]->bo);
1196 }
1197
1198 if (radv_pipeline_has_gs_copy_shader(pipeline))
1199 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1200 pipeline->gs_copy_shader->bo);
1201
1202 if (unlikely(cmd_buffer->device->trace_bo))
1203 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1204
1205 cmd_buffer->state.emitted_pipeline = pipeline;
1206
1207 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1208 }
1209
1210 static void
1211 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1212 {
1213 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1214 cmd_buffer->state.dynamic.viewport.viewports);
1215 }
1216
1217 static void
1218 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1219 {
1220 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1221
1222 si_write_scissors(cmd_buffer->cs, 0, count,
1223 cmd_buffer->state.dynamic.scissor.scissors,
1224 cmd_buffer->state.dynamic.viewport.viewports,
1225 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1226
1227 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1228 }
1229
1230 static void
1231 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1232 {
1233 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1234 return;
1235
1236 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1237 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1238 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1239 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1240 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1241 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1242 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1243 }
1244 }
1245
1246 static void
1247 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1248 {
1249 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1250
1251 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1252 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1253 }
1254
1255 static void
1256 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1257 {
1258 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1259
1260 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1261 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1262 }
1263
1264 static void
1265 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1266 {
1267 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1268
1269 radeon_set_context_reg_seq(cmd_buffer->cs,
1270 R_028430_DB_STENCILREFMASK, 2);
1271 radeon_emit(cmd_buffer->cs,
1272 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1273 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1274 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1275 S_028430_STENCILOPVAL(1));
1276 radeon_emit(cmd_buffer->cs,
1277 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1278 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1279 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1280 S_028434_STENCILOPVAL_BF(1));
1281 }
1282
1283 static void
1284 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1285 {
1286 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1287
1288 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1289 fui(d->depth_bounds.min));
1290 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1291 fui(d->depth_bounds.max));
1292 }
1293
1294 static void
1295 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1296 {
1297 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1298 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1299 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1300
1301
1302 radeon_set_context_reg_seq(cmd_buffer->cs,
1303 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1304 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1305 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1306 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1307 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1308 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1309 }
1310
1311 static void
1312 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1313 int index,
1314 struct radv_color_buffer_info *cb,
1315 struct radv_image_view *iview,
1316 VkImageLayout layout,
1317 bool in_render_loop)
1318 {
1319 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1320 uint32_t cb_color_info = cb->cb_color_info;
1321 struct radv_image *image = iview->image;
1322
1323 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1324 radv_image_queue_family_mask(image,
1325 cmd_buffer->queue_family_index,
1326 cmd_buffer->queue_family_index))) {
1327 cb_color_info &= C_028C70_DCC_ENABLE;
1328 }
1329
1330 if (radv_image_is_tc_compat_cmask(image) &&
1331 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1332 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1333 /* If this bit is set, the FMASK decompression operation
1334 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1335 */
1336 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1337 }
1338
1339 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1340 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1341 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1342 radeon_emit(cmd_buffer->cs, 0);
1343 radeon_emit(cmd_buffer->cs, 0);
1344 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1345 radeon_emit(cmd_buffer->cs, cb_color_info);
1346 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1347 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1348 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1349 radeon_emit(cmd_buffer->cs, 0);
1350 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1351 radeon_emit(cmd_buffer->cs, 0);
1352
1353 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1354 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1355
1356 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1357 cb->cb_color_base >> 32);
1358 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1359 cb->cb_color_cmask >> 32);
1360 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1361 cb->cb_color_fmask >> 32);
1362 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1363 cb->cb_dcc_base >> 32);
1364 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1365 cb->cb_color_attrib2);
1366 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1367 cb->cb_color_attrib3);
1368 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1369 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1370 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1371 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1372 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1373 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1374 radeon_emit(cmd_buffer->cs, cb_color_info);
1375 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1376 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1377 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1378 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1379 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1380 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1381
1382 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1383 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1384 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1385
1386 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1387 cb->cb_mrt_epitch);
1388 } else {
1389 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1390 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1391 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1392 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1393 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1394 radeon_emit(cmd_buffer->cs, cb_color_info);
1395 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1396 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1397 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1398 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1399 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1400 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1401
1402 if (is_vi) { /* DCC BASE */
1403 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1404 }
1405 }
1406
1407 if (radv_dcc_enabled(image, iview->base_mip)) {
1408 /* Drawing with DCC enabled also compresses colorbuffers. */
1409 VkImageSubresourceRange range = {
1410 .aspectMask = iview->aspect_mask,
1411 .baseMipLevel = iview->base_mip,
1412 .levelCount = iview->level_count,
1413 .baseArrayLayer = iview->base_layer,
1414 .layerCount = iview->layer_count,
1415 };
1416
1417 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1418 }
1419 }
1420
1421 static void
1422 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1423 struct radv_ds_buffer_info *ds,
1424 const struct radv_image_view *iview,
1425 VkImageLayout layout,
1426 bool in_render_loop, bool requires_cond_exec)
1427 {
1428 const struct radv_image *image = iview->image;
1429 uint32_t db_z_info = ds->db_z_info;
1430 uint32_t db_z_info_reg;
1431
1432 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1433 !radv_image_is_tc_compat_htile(image))
1434 return;
1435
1436 if (!radv_layout_has_htile(image, layout, in_render_loop,
1437 radv_image_queue_family_mask(image,
1438 cmd_buffer->queue_family_index,
1439 cmd_buffer->queue_family_index))) {
1440 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1441 }
1442
1443 db_z_info &= C_028040_ZRANGE_PRECISION;
1444
1445 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1446 db_z_info_reg = R_028038_DB_Z_INFO;
1447 } else {
1448 db_z_info_reg = R_028040_DB_Z_INFO;
1449 }
1450
1451 /* When we don't know the last fast clear value we need to emit a
1452 * conditional packet that will eventually skip the following
1453 * SET_CONTEXT_REG packet.
1454 */
1455 if (requires_cond_exec) {
1456 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1457
1458 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1459 radeon_emit(cmd_buffer->cs, va);
1460 radeon_emit(cmd_buffer->cs, va >> 32);
1461 radeon_emit(cmd_buffer->cs, 0);
1462 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1463 }
1464
1465 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1466 }
1467
1468 static void
1469 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1470 struct radv_ds_buffer_info *ds,
1471 struct radv_image_view *iview,
1472 VkImageLayout layout,
1473 bool in_render_loop)
1474 {
1475 const struct radv_image *image = iview->image;
1476 uint32_t db_z_info = ds->db_z_info;
1477 uint32_t db_stencil_info = ds->db_stencil_info;
1478
1479 if (!radv_layout_has_htile(image, layout, in_render_loop,
1480 radv_image_queue_family_mask(image,
1481 cmd_buffer->queue_family_index,
1482 cmd_buffer->queue_family_index))) {
1483 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1484 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1485 }
1486
1487 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1488 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1489
1490 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1491 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1492 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1493
1494 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1495 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1496 radeon_emit(cmd_buffer->cs, db_z_info);
1497 radeon_emit(cmd_buffer->cs, db_stencil_info);
1498 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1499 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1500 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1501 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1502
1503 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1504 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1505 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1506 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1507 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1508 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1509 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1510 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1511 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1512 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1513 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1514
1515 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1516 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1517 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1518 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1519 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1520 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1521 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1522 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1523 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1524 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1525 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1526
1527 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1528 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1529 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1530 } else {
1531 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1532
1533 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1534 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1535 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1536 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1537 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1538 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1539 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1540 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1541 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1542 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1543
1544 }
1545
1546 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1547 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1548 in_render_loop, true);
1549
1550 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1551 ds->pa_su_poly_offset_db_fmt_cntl);
1552 }
1553
1554 /**
1555 * Update the fast clear depth/stencil values if the image is bound as a
1556 * depth/stencil buffer.
1557 */
1558 static void
1559 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1560 const struct radv_image_view *iview,
1561 VkClearDepthStencilValue ds_clear_value,
1562 VkImageAspectFlags aspects)
1563 {
1564 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1565 const struct radv_image *image = iview->image;
1566 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1567 uint32_t att_idx;
1568
1569 if (!cmd_buffer->state.attachments || !subpass)
1570 return;
1571
1572 if (!subpass->depth_stencil_attachment)
1573 return;
1574
1575 att_idx = subpass->depth_stencil_attachment->attachment;
1576 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1577 return;
1578
1579 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1580 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1581 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1582 radeon_emit(cs, ds_clear_value.stencil);
1583 radeon_emit(cs, fui(ds_clear_value.depth));
1584 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1585 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1586 radeon_emit(cs, fui(ds_clear_value.depth));
1587 } else {
1588 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1589 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1590 radeon_emit(cs, ds_clear_value.stencil);
1591 }
1592
1593 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1594 * only needed when clearing Z to 0.0.
1595 */
1596 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1597 ds_clear_value.depth == 0.0) {
1598 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1599 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1600
1601 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1602 iview, layout, in_render_loop, false);
1603 }
1604
1605 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1606 }
1607
1608 /**
1609 * Set the clear depth/stencil values to the image's metadata.
1610 */
1611 static void
1612 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1613 struct radv_image *image,
1614 const VkImageSubresourceRange *range,
1615 VkClearDepthStencilValue ds_clear_value,
1616 VkImageAspectFlags aspects)
1617 {
1618 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1619 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1620 uint32_t level_count = radv_get_levelCount(image, range);
1621
1622 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1623 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1624 /* Use the fastest way when both aspects are used. */
1625 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1626 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1627 S_370_WR_CONFIRM(1) |
1628 S_370_ENGINE_SEL(V_370_PFP));
1629 radeon_emit(cs, va);
1630 radeon_emit(cs, va >> 32);
1631
1632 for (uint32_t l = 0; l < level_count; l++) {
1633 radeon_emit(cs, ds_clear_value.stencil);
1634 radeon_emit(cs, fui(ds_clear_value.depth));
1635 }
1636 } else {
1637 /* Otherwise we need one WRITE_DATA packet per level. */
1638 for (uint32_t l = 0; l < level_count; l++) {
1639 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1640 unsigned value;
1641
1642 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1643 value = fui(ds_clear_value.depth);
1644 va += 4;
1645 } else {
1646 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1647 value = ds_clear_value.stencil;
1648 }
1649
1650 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1651 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1652 S_370_WR_CONFIRM(1) |
1653 S_370_ENGINE_SEL(V_370_PFP));
1654 radeon_emit(cs, va);
1655 radeon_emit(cs, va >> 32);
1656 radeon_emit(cs, value);
1657 }
1658 }
1659 }
1660
1661 /**
1662 * Update the TC-compat metadata value for this image.
1663 */
1664 static void
1665 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1666 struct radv_image *image,
1667 const VkImageSubresourceRange *range,
1668 uint32_t value)
1669 {
1670 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1671
1672 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1673 return;
1674
1675 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1676 uint32_t level_count = radv_get_levelCount(image, range);
1677
1678 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1679 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1680 S_370_WR_CONFIRM(1) |
1681 S_370_ENGINE_SEL(V_370_PFP));
1682 radeon_emit(cs, va);
1683 radeon_emit(cs, va >> 32);
1684
1685 for (uint32_t l = 0; l < level_count; l++)
1686 radeon_emit(cs, value);
1687 }
1688
1689 static void
1690 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1691 const struct radv_image_view *iview,
1692 VkClearDepthStencilValue ds_clear_value)
1693 {
1694 VkImageSubresourceRange range = {
1695 .aspectMask = iview->aspect_mask,
1696 .baseMipLevel = iview->base_mip,
1697 .levelCount = iview->level_count,
1698 .baseArrayLayer = iview->base_layer,
1699 .layerCount = iview->layer_count,
1700 };
1701 uint32_t cond_val;
1702
1703 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1704 * depth clear value is 0.0f.
1705 */
1706 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1707
1708 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1709 cond_val);
1710 }
1711
1712 /**
1713 * Update the clear depth/stencil values for this image.
1714 */
1715 void
1716 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1717 const struct radv_image_view *iview,
1718 VkClearDepthStencilValue ds_clear_value,
1719 VkImageAspectFlags aspects)
1720 {
1721 VkImageSubresourceRange range = {
1722 .aspectMask = iview->aspect_mask,
1723 .baseMipLevel = iview->base_mip,
1724 .levelCount = iview->level_count,
1725 .baseArrayLayer = iview->base_layer,
1726 .layerCount = iview->layer_count,
1727 };
1728 struct radv_image *image = iview->image;
1729
1730 assert(radv_image_has_htile(image));
1731
1732 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1733 ds_clear_value, aspects);
1734
1735 if (radv_image_is_tc_compat_htile(image) &&
1736 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1737 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1738 ds_clear_value);
1739 }
1740
1741 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1742 aspects);
1743 }
1744
1745 /**
1746 * Load the clear depth/stencil values from the image's metadata.
1747 */
1748 static void
1749 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1750 const struct radv_image_view *iview)
1751 {
1752 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1753 const struct radv_image *image = iview->image;
1754 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1755 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1756 unsigned reg_offset = 0, reg_count = 0;
1757
1758 if (!radv_image_has_htile(image))
1759 return;
1760
1761 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1762 ++reg_count;
1763 } else {
1764 ++reg_offset;
1765 va += 4;
1766 }
1767 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1768 ++reg_count;
1769
1770 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1771
1772 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1773 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1774 radeon_emit(cs, va);
1775 radeon_emit(cs, va >> 32);
1776 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1777 radeon_emit(cs, reg_count);
1778 } else {
1779 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1780 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1781 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1782 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1783 radeon_emit(cs, va);
1784 radeon_emit(cs, va >> 32);
1785 radeon_emit(cs, reg >> 2);
1786 radeon_emit(cs, 0);
1787
1788 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1789 radeon_emit(cs, 0);
1790 }
1791 }
1792
1793 /*
1794 * With DCC some colors don't require CMASK elimination before being
1795 * used as a texture. This sets a predicate value to determine if the
1796 * cmask eliminate is required.
1797 */
1798 void
1799 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1800 struct radv_image *image,
1801 const VkImageSubresourceRange *range, bool value)
1802 {
1803 uint64_t pred_val = value;
1804 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1805 uint32_t level_count = radv_get_levelCount(image, range);
1806 uint32_t count = 2 * level_count;
1807
1808 assert(radv_dcc_enabled(image, range->baseMipLevel));
1809
1810 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1811 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1812 S_370_WR_CONFIRM(1) |
1813 S_370_ENGINE_SEL(V_370_PFP));
1814 radeon_emit(cmd_buffer->cs, va);
1815 radeon_emit(cmd_buffer->cs, va >> 32);
1816
1817 for (uint32_t l = 0; l < level_count; l++) {
1818 radeon_emit(cmd_buffer->cs, pred_val);
1819 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1820 }
1821 }
1822
1823 /**
1824 * Update the DCC predicate to reflect the compression state.
1825 */
1826 void
1827 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1828 struct radv_image *image,
1829 const VkImageSubresourceRange *range, bool value)
1830 {
1831 uint64_t pred_val = value;
1832 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1833 uint32_t level_count = radv_get_levelCount(image, range);
1834 uint32_t count = 2 * level_count;
1835
1836 assert(radv_dcc_enabled(image, range->baseMipLevel));
1837
1838 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1839 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1840 S_370_WR_CONFIRM(1) |
1841 S_370_ENGINE_SEL(V_370_PFP));
1842 radeon_emit(cmd_buffer->cs, va);
1843 radeon_emit(cmd_buffer->cs, va >> 32);
1844
1845 for (uint32_t l = 0; l < level_count; l++) {
1846 radeon_emit(cmd_buffer->cs, pred_val);
1847 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1848 }
1849 }
1850
1851 /**
1852 * Update the fast clear color values if the image is bound as a color buffer.
1853 */
1854 static void
1855 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1856 struct radv_image *image,
1857 int cb_idx,
1858 uint32_t color_values[2])
1859 {
1860 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1861 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1862 uint32_t att_idx;
1863
1864 if (!cmd_buffer->state.attachments || !subpass)
1865 return;
1866
1867 att_idx = subpass->color_attachments[cb_idx].attachment;
1868 if (att_idx == VK_ATTACHMENT_UNUSED)
1869 return;
1870
1871 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1872 return;
1873
1874 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1875 radeon_emit(cs, color_values[0]);
1876 radeon_emit(cs, color_values[1]);
1877
1878 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1879 }
1880
1881 /**
1882 * Set the clear color values to the image's metadata.
1883 */
1884 static void
1885 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1886 struct radv_image *image,
1887 const VkImageSubresourceRange *range,
1888 uint32_t color_values[2])
1889 {
1890 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1891 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1892 uint32_t level_count = radv_get_levelCount(image, range);
1893 uint32_t count = 2 * level_count;
1894
1895 assert(radv_image_has_cmask(image) ||
1896 radv_dcc_enabled(image, range->baseMipLevel));
1897
1898 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1899 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1900 S_370_WR_CONFIRM(1) |
1901 S_370_ENGINE_SEL(V_370_PFP));
1902 radeon_emit(cs, va);
1903 radeon_emit(cs, va >> 32);
1904
1905 for (uint32_t l = 0; l < level_count; l++) {
1906 radeon_emit(cs, color_values[0]);
1907 radeon_emit(cs, color_values[1]);
1908 }
1909 }
1910
1911 /**
1912 * Update the clear color values for this image.
1913 */
1914 void
1915 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1916 const struct radv_image_view *iview,
1917 int cb_idx,
1918 uint32_t color_values[2])
1919 {
1920 struct radv_image *image = iview->image;
1921 VkImageSubresourceRange range = {
1922 .aspectMask = iview->aspect_mask,
1923 .baseMipLevel = iview->base_mip,
1924 .levelCount = iview->level_count,
1925 .baseArrayLayer = iview->base_layer,
1926 .layerCount = iview->layer_count,
1927 };
1928
1929 assert(radv_image_has_cmask(image) ||
1930 radv_dcc_enabled(image, iview->base_mip));
1931
1932 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1933
1934 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1935 color_values);
1936 }
1937
1938 /**
1939 * Load the clear color values from the image's metadata.
1940 */
1941 static void
1942 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1943 struct radv_image_view *iview,
1944 int cb_idx)
1945 {
1946 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1947 struct radv_image *image = iview->image;
1948 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1949
1950 if (!radv_image_has_cmask(image) &&
1951 !radv_dcc_enabled(image, iview->base_mip))
1952 return;
1953
1954 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1955
1956 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1957 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1958 radeon_emit(cs, va);
1959 radeon_emit(cs, va >> 32);
1960 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1961 radeon_emit(cs, 2);
1962 } else {
1963 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1964 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1965 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1966 COPY_DATA_COUNT_SEL);
1967 radeon_emit(cs, va);
1968 radeon_emit(cs, va >> 32);
1969 radeon_emit(cs, reg >> 2);
1970 radeon_emit(cs, 0);
1971
1972 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1973 radeon_emit(cs, 0);
1974 }
1975 }
1976
1977 static void
1978 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1979 {
1980 int i;
1981 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1982 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1983
1984 /* this may happen for inherited secondary recording */
1985 if (!framebuffer)
1986 return;
1987
1988 for (i = 0; i < 8; ++i) {
1989 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1990 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1991 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1992 continue;
1993 }
1994
1995 int idx = subpass->color_attachments[i].attachment;
1996 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
1997 VkImageLayout layout = subpass->color_attachments[i].layout;
1998 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
1999
2000 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2001
2002 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2003 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2004 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2005
2006 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2007 }
2008
2009 if (subpass->depth_stencil_attachment) {
2010 int idx = subpass->depth_stencil_attachment->attachment;
2011 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2012 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2013 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2014 struct radv_image *image = iview->image;
2015 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2016 ASSERTED uint32_t queue_mask = radv_image_queue_family_mask(image,
2017 cmd_buffer->queue_family_index,
2018 cmd_buffer->queue_family_index);
2019 /* We currently don't support writing decompressed HTILE */
2020 assert(radv_layout_has_htile(image, layout, in_render_loop, queue_mask) ==
2021 radv_layout_is_htile_compressed(image, layout, in_render_loop, queue_mask));
2022
2023 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2024
2025 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2026 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2027 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2028 }
2029 radv_load_ds_clear_metadata(cmd_buffer, iview);
2030 } else {
2031 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2032 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2033 else
2034 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2035
2036 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2037 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2038 }
2039 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2040 S_028208_BR_X(framebuffer->width) |
2041 S_028208_BR_Y(framebuffer->height));
2042
2043 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2044 bool disable_constant_encode =
2045 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2046 enum chip_class chip_class =
2047 cmd_buffer->device->physical_device->rad_info.chip_class;
2048 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2049
2050 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2051 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2052 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2053 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2054 }
2055
2056 if (cmd_buffer->device->dfsm_allowed) {
2057 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2058 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2059 }
2060
2061 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2062 }
2063
2064 static void
2065 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
2066 {
2067 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2068 struct radv_cmd_state *state = &cmd_buffer->state;
2069
2070 if (state->index_type != state->last_index_type) {
2071 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2072 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2073 cs, R_03090C_VGT_INDEX_TYPE,
2074 2, state->index_type);
2075 } else {
2076 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2077 radeon_emit(cs, state->index_type);
2078 }
2079
2080 state->last_index_type = state->index_type;
2081 }
2082
2083 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2084 radeon_emit(cs, state->index_va);
2085 radeon_emit(cs, state->index_va >> 32);
2086
2087 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2088 radeon_emit(cs, state->max_index_count);
2089
2090 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2091 }
2092
2093 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2094 {
2095 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2096 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2097 uint32_t pa_sc_mode_cntl_1 =
2098 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2099 uint32_t db_count_control;
2100
2101 if(!cmd_buffer->state.active_occlusion_queries) {
2102 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2103 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2104 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2105 has_perfect_queries) {
2106 /* Re-enable out-of-order rasterization if the
2107 * bound pipeline supports it and if it's has
2108 * been disabled before starting any perfect
2109 * occlusion queries.
2110 */
2111 radeon_set_context_reg(cmd_buffer->cs,
2112 R_028A4C_PA_SC_MODE_CNTL_1,
2113 pa_sc_mode_cntl_1);
2114 }
2115 }
2116 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2117 } else {
2118 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2119 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2120 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2121
2122 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2123 db_count_control =
2124 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2125 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2126 S_028004_SAMPLE_RATE(sample_rate) |
2127 S_028004_ZPASS_ENABLE(1) |
2128 S_028004_SLICE_EVEN_ENABLE(1) |
2129 S_028004_SLICE_ODD_ENABLE(1);
2130
2131 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2132 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2133 has_perfect_queries) {
2134 /* If the bound pipeline has enabled
2135 * out-of-order rasterization, we should
2136 * disable it before starting any perfect
2137 * occlusion queries.
2138 */
2139 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2140
2141 radeon_set_context_reg(cmd_buffer->cs,
2142 R_028A4C_PA_SC_MODE_CNTL_1,
2143 pa_sc_mode_cntl_1);
2144 }
2145 } else {
2146 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2147 S_028004_SAMPLE_RATE(sample_rate);
2148 }
2149 }
2150
2151 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2152
2153 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2154 }
2155
2156 static void
2157 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2158 {
2159 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2160
2161 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2162 radv_emit_viewport(cmd_buffer);
2163
2164 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2165 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2166 radv_emit_scissor(cmd_buffer);
2167
2168 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2169 radv_emit_line_width(cmd_buffer);
2170
2171 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2172 radv_emit_blend_constants(cmd_buffer);
2173
2174 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2175 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2176 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2177 radv_emit_stencil(cmd_buffer);
2178
2179 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2180 radv_emit_depth_bounds(cmd_buffer);
2181
2182 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2183 radv_emit_depth_bias(cmd_buffer);
2184
2185 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2186 radv_emit_discard_rectangle(cmd_buffer);
2187
2188 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2189 radv_emit_sample_locations(cmd_buffer);
2190
2191 cmd_buffer->state.dirty &= ~states;
2192 }
2193
2194 static void
2195 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2196 VkPipelineBindPoint bind_point)
2197 {
2198 struct radv_descriptor_state *descriptors_state =
2199 radv_get_descriptors_state(cmd_buffer, bind_point);
2200 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2201 unsigned bo_offset;
2202
2203 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2204 set->mapped_ptr,
2205 &bo_offset))
2206 return;
2207
2208 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2209 set->va += bo_offset;
2210 }
2211
2212 static void
2213 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2214 VkPipelineBindPoint bind_point)
2215 {
2216 struct radv_descriptor_state *descriptors_state =
2217 radv_get_descriptors_state(cmd_buffer, bind_point);
2218 uint32_t size = MAX_SETS * 4;
2219 uint32_t offset;
2220 void *ptr;
2221
2222 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2223 256, &offset, &ptr))
2224 return;
2225
2226 for (unsigned i = 0; i < MAX_SETS; i++) {
2227 uint32_t *uptr = ((uint32_t *)ptr) + i;
2228 uint64_t set_va = 0;
2229 struct radv_descriptor_set *set = descriptors_state->sets[i];
2230 if (descriptors_state->valid & (1u << i))
2231 set_va = set->va;
2232 uptr[0] = set_va & 0xffffffff;
2233 }
2234
2235 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2236 va += offset;
2237
2238 if (cmd_buffer->state.pipeline) {
2239 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2240 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2241 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2242
2243 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2244 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2245 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2246
2247 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2248 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2249 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2250
2251 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2252 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2253 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2254
2255 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2256 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2257 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2258 }
2259
2260 if (cmd_buffer->state.compute_pipeline)
2261 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2262 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2263 }
2264
2265 static void
2266 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2267 VkShaderStageFlags stages)
2268 {
2269 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2270 VK_PIPELINE_BIND_POINT_COMPUTE :
2271 VK_PIPELINE_BIND_POINT_GRAPHICS;
2272 struct radv_descriptor_state *descriptors_state =
2273 radv_get_descriptors_state(cmd_buffer, bind_point);
2274 struct radv_cmd_state *state = &cmd_buffer->state;
2275 bool flush_indirect_descriptors;
2276
2277 if (!descriptors_state->dirty)
2278 return;
2279
2280 if (descriptors_state->push_dirty)
2281 radv_flush_push_descriptors(cmd_buffer, bind_point);
2282
2283 flush_indirect_descriptors =
2284 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2285 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2286 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2287 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2288
2289 if (flush_indirect_descriptors)
2290 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2291
2292 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2293 cmd_buffer->cs,
2294 MAX_SETS * MESA_SHADER_STAGES * 4);
2295
2296 if (cmd_buffer->state.pipeline) {
2297 radv_foreach_stage(stage, stages) {
2298 if (!cmd_buffer->state.pipeline->shaders[stage])
2299 continue;
2300
2301 radv_emit_descriptor_pointers(cmd_buffer,
2302 cmd_buffer->state.pipeline,
2303 descriptors_state, stage);
2304 }
2305 }
2306
2307 if (cmd_buffer->state.compute_pipeline &&
2308 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2309 radv_emit_descriptor_pointers(cmd_buffer,
2310 cmd_buffer->state.compute_pipeline,
2311 descriptors_state,
2312 MESA_SHADER_COMPUTE);
2313 }
2314
2315 descriptors_state->dirty = 0;
2316 descriptors_state->push_dirty = false;
2317
2318 assert(cmd_buffer->cs->cdw <= cdw_max);
2319
2320 if (unlikely(cmd_buffer->device->trace_bo))
2321 radv_save_descriptors(cmd_buffer, bind_point);
2322 }
2323
2324 static void
2325 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2326 VkShaderStageFlags stages)
2327 {
2328 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2329 ? cmd_buffer->state.compute_pipeline
2330 : cmd_buffer->state.pipeline;
2331 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2332 VK_PIPELINE_BIND_POINT_COMPUTE :
2333 VK_PIPELINE_BIND_POINT_GRAPHICS;
2334 struct radv_descriptor_state *descriptors_state =
2335 radv_get_descriptors_state(cmd_buffer, bind_point);
2336 struct radv_pipeline_layout *layout = pipeline->layout;
2337 struct radv_shader_variant *shader, *prev_shader;
2338 bool need_push_constants = false;
2339 unsigned offset;
2340 void *ptr;
2341 uint64_t va;
2342
2343 stages &= cmd_buffer->push_constant_stages;
2344 if (!stages ||
2345 (!layout->push_constant_size && !layout->dynamic_offset_count))
2346 return;
2347
2348 radv_foreach_stage(stage, stages) {
2349 shader = radv_get_shader(pipeline, stage);
2350 if (!shader)
2351 continue;
2352
2353 need_push_constants |= shader->info.loads_push_constants;
2354 need_push_constants |= shader->info.loads_dynamic_offsets;
2355
2356 uint8_t base = shader->info.base_inline_push_consts;
2357 uint8_t count = shader->info.num_inline_push_consts;
2358
2359 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2360 AC_UD_INLINE_PUSH_CONSTANTS,
2361 count,
2362 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2363 }
2364
2365 if (need_push_constants) {
2366 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2367 16 * layout->dynamic_offset_count,
2368 256, &offset, &ptr))
2369 return;
2370
2371 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2372 memcpy((char*)ptr + layout->push_constant_size,
2373 descriptors_state->dynamic_buffers,
2374 16 * layout->dynamic_offset_count);
2375
2376 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2377 va += offset;
2378
2379 ASSERTED unsigned cdw_max =
2380 radeon_check_space(cmd_buffer->device->ws,
2381 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2382
2383 prev_shader = NULL;
2384 radv_foreach_stage(stage, stages) {
2385 shader = radv_get_shader(pipeline, stage);
2386
2387 /* Avoid redundantly emitting the address for merged stages. */
2388 if (shader && shader != prev_shader) {
2389 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2390 AC_UD_PUSH_CONSTANTS, va);
2391
2392 prev_shader = shader;
2393 }
2394 }
2395 assert(cmd_buffer->cs->cdw <= cdw_max);
2396 }
2397
2398 cmd_buffer->push_constant_stages &= ~stages;
2399 }
2400
2401 static void
2402 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2403 bool pipeline_is_dirty)
2404 {
2405 if ((pipeline_is_dirty ||
2406 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2407 cmd_buffer->state.pipeline->num_vertex_bindings &&
2408 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2409 unsigned vb_offset;
2410 void *vb_ptr;
2411 uint32_t i = 0;
2412 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2413 uint64_t va;
2414
2415 /* allocate some descriptor state for vertex buffers */
2416 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2417 &vb_offset, &vb_ptr))
2418 return;
2419
2420 for (i = 0; i < count; i++) {
2421 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2422 uint32_t offset;
2423 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2424 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2425 unsigned num_records;
2426
2427 if (!buffer)
2428 continue;
2429
2430 va = radv_buffer_get_va(buffer->bo);
2431
2432 offset = cmd_buffer->vertex_bindings[i].offset;
2433 va += offset + buffer->offset;
2434
2435 num_records = buffer->size - offset;
2436 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2437 num_records /= stride;
2438
2439 desc[0] = va;
2440 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2441 desc[2] = num_records;
2442 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2443 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2444 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2445 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2446
2447 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2448 /* OOB_SELECT chooses the out-of-bounds check:
2449 * - 1: index >= NUM_RECORDS (Structured)
2450 * - 3: offset >= NUM_RECORDS (Raw)
2451 */
2452 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2453
2454 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2455 S_008F0C_OOB_SELECT(oob_select) |
2456 S_008F0C_RESOURCE_LEVEL(1);
2457 } else {
2458 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2459 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2460 }
2461 }
2462
2463 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2464 va += vb_offset;
2465
2466 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2467 AC_UD_VS_VERTEX_BUFFERS, va);
2468
2469 cmd_buffer->state.vb_va = va;
2470 cmd_buffer->state.vb_size = count * 16;
2471 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2472 }
2473 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2474 }
2475
2476 static void
2477 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2478 {
2479 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2480 struct radv_userdata_info *loc;
2481 uint32_t base_reg;
2482
2483 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2484 if (!radv_get_shader(pipeline, stage))
2485 continue;
2486
2487 loc = radv_lookup_user_sgpr(pipeline, stage,
2488 AC_UD_STREAMOUT_BUFFERS);
2489 if (loc->sgpr_idx == -1)
2490 continue;
2491
2492 base_reg = pipeline->user_data_0[stage];
2493
2494 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2495 base_reg + loc->sgpr_idx * 4, va, false);
2496 }
2497
2498 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2499 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2500 if (loc->sgpr_idx != -1) {
2501 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2502
2503 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2504 base_reg + loc->sgpr_idx * 4, va, false);
2505 }
2506 }
2507 }
2508
2509 static void
2510 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2511 {
2512 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2513 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2514 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2515 unsigned so_offset;
2516 void *so_ptr;
2517 uint64_t va;
2518
2519 /* Allocate some descriptor state for streamout buffers. */
2520 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2521 MAX_SO_BUFFERS * 16, 256,
2522 &so_offset, &so_ptr))
2523 return;
2524
2525 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2526 struct radv_buffer *buffer = sb[i].buffer;
2527 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2528
2529 if (!(so->enabled_mask & (1 << i)))
2530 continue;
2531
2532 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2533
2534 va += sb[i].offset;
2535
2536 /* Set the descriptor.
2537 *
2538 * On GFX8, the format must be non-INVALID, otherwise
2539 * the buffer will be considered not bound and store
2540 * instructions will be no-ops.
2541 */
2542 uint32_t size = 0xffffffff;
2543
2544 /* Compute the correct buffer size for NGG streamout
2545 * because it's used to determine the max emit per
2546 * buffer.
2547 */
2548 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2549 size = buffer->size - sb[i].offset;
2550
2551 desc[0] = va;
2552 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2553 desc[2] = size;
2554 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2555 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2556 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2557 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2558
2559 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2560 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2561 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2562 S_008F0C_RESOURCE_LEVEL(1);
2563 } else {
2564 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2565 }
2566 }
2567
2568 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2569 va += so_offset;
2570
2571 radv_emit_streamout_buffers(cmd_buffer, va);
2572 }
2573
2574 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2575 }
2576
2577 static void
2578 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2579 {
2580 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2581 radv_flush_streamout_descriptors(cmd_buffer);
2582 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2583 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2584 }
2585
2586 struct radv_draw_info {
2587 /**
2588 * Number of vertices.
2589 */
2590 uint32_t count;
2591
2592 /**
2593 * Index of the first vertex.
2594 */
2595 int32_t vertex_offset;
2596
2597 /**
2598 * First instance id.
2599 */
2600 uint32_t first_instance;
2601
2602 /**
2603 * Number of instances.
2604 */
2605 uint32_t instance_count;
2606
2607 /**
2608 * First index (indexed draws only).
2609 */
2610 uint32_t first_index;
2611
2612 /**
2613 * Whether it's an indexed draw.
2614 */
2615 bool indexed;
2616
2617 /**
2618 * Indirect draw parameters resource.
2619 */
2620 struct radv_buffer *indirect;
2621 uint64_t indirect_offset;
2622 uint32_t stride;
2623
2624 /**
2625 * Draw count parameters resource.
2626 */
2627 struct radv_buffer *count_buffer;
2628 uint64_t count_buffer_offset;
2629
2630 /**
2631 * Stream output parameters resource.
2632 */
2633 struct radv_buffer *strmout_buffer;
2634 uint64_t strmout_buffer_offset;
2635 };
2636
2637 static uint32_t
2638 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2639 {
2640 switch (cmd_buffer->state.index_type) {
2641 case V_028A7C_VGT_INDEX_8:
2642 return 0xffu;
2643 case V_028A7C_VGT_INDEX_16:
2644 return 0xffffu;
2645 case V_028A7C_VGT_INDEX_32:
2646 return 0xffffffffu;
2647 default:
2648 unreachable("invalid index type");
2649 }
2650 }
2651
2652 static void
2653 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2654 bool instanced_draw, bool indirect_draw,
2655 bool count_from_stream_output,
2656 uint32_t draw_vertex_count)
2657 {
2658 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2659 struct radv_cmd_state *state = &cmd_buffer->state;
2660 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2661 unsigned ia_multi_vgt_param;
2662
2663 ia_multi_vgt_param =
2664 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2665 indirect_draw,
2666 count_from_stream_output,
2667 draw_vertex_count);
2668
2669 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2670 if (info->chip_class == GFX9) {
2671 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2672 cs,
2673 R_030960_IA_MULTI_VGT_PARAM,
2674 4, ia_multi_vgt_param);
2675 } else if (info->chip_class >= GFX7) {
2676 radeon_set_context_reg_idx(cs,
2677 R_028AA8_IA_MULTI_VGT_PARAM,
2678 1, ia_multi_vgt_param);
2679 } else {
2680 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2681 ia_multi_vgt_param);
2682 }
2683 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2684 }
2685 }
2686
2687 static void
2688 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2689 const struct radv_draw_info *draw_info)
2690 {
2691 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2692 struct radv_cmd_state *state = &cmd_buffer->state;
2693 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2694 int32_t primitive_reset_en;
2695
2696 /* Draw state. */
2697 if (info->chip_class < GFX10) {
2698 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2699 draw_info->indirect,
2700 !!draw_info->strmout_buffer,
2701 draw_info->indirect ? 0 : draw_info->count);
2702 }
2703
2704 /* Primitive restart. */
2705 primitive_reset_en =
2706 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2707
2708 if (primitive_reset_en != state->last_primitive_reset_en) {
2709 state->last_primitive_reset_en = primitive_reset_en;
2710 if (info->chip_class >= GFX9) {
2711 radeon_set_uconfig_reg(cs,
2712 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2713 primitive_reset_en);
2714 } else {
2715 radeon_set_context_reg(cs,
2716 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2717 primitive_reset_en);
2718 }
2719 }
2720
2721 if (primitive_reset_en) {
2722 uint32_t primitive_reset_index =
2723 radv_get_primitive_reset_index(cmd_buffer);
2724
2725 if (primitive_reset_index != state->last_primitive_reset_index) {
2726 radeon_set_context_reg(cs,
2727 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2728 primitive_reset_index);
2729 state->last_primitive_reset_index = primitive_reset_index;
2730 }
2731 }
2732
2733 if (draw_info->strmout_buffer) {
2734 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2735
2736 va += draw_info->strmout_buffer->offset +
2737 draw_info->strmout_buffer_offset;
2738
2739 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2740 draw_info->stride);
2741
2742 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2743 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2744 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2745 COPY_DATA_WR_CONFIRM);
2746 radeon_emit(cs, va);
2747 radeon_emit(cs, va >> 32);
2748 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2749 radeon_emit(cs, 0); /* unused */
2750
2751 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2752 }
2753 }
2754
2755 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2756 VkPipelineStageFlags src_stage_mask)
2757 {
2758 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2759 VK_PIPELINE_STAGE_TRANSFER_BIT |
2760 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2761 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2762 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2763 }
2764
2765 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2766 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2767 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2768 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2769 VK_PIPELINE_STAGE_TRANSFER_BIT |
2770 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2771 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2772 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2773 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2774 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2775 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2776 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2777 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2778 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2779 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2780 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2781 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2782 }
2783 }
2784
2785 static enum radv_cmd_flush_bits
2786 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2787 VkAccessFlags src_flags,
2788 struct radv_image *image)
2789 {
2790 bool flush_CB_meta = true, flush_DB_meta = true;
2791 enum radv_cmd_flush_bits flush_bits = 0;
2792 uint32_t b;
2793
2794 if (image) {
2795 if (!radv_image_has_CB_metadata(image))
2796 flush_CB_meta = false;
2797 if (!radv_image_has_htile(image))
2798 flush_DB_meta = false;
2799 }
2800
2801 for_each_bit(b, src_flags) {
2802 switch ((VkAccessFlagBits)(1 << b)) {
2803 case VK_ACCESS_SHADER_WRITE_BIT:
2804 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2805 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2806 flush_bits |= RADV_CMD_FLAG_WB_L2;
2807 break;
2808 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2809 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2810 if (flush_CB_meta)
2811 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2812 break;
2813 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2814 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2815 if (flush_DB_meta)
2816 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2817 break;
2818 case VK_ACCESS_TRANSFER_WRITE_BIT:
2819 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2820 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2821 RADV_CMD_FLAG_INV_L2;
2822
2823 if (flush_CB_meta)
2824 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2825 if (flush_DB_meta)
2826 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2827 break;
2828 default:
2829 break;
2830 }
2831 }
2832 return flush_bits;
2833 }
2834
2835 static enum radv_cmd_flush_bits
2836 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2837 VkAccessFlags dst_flags,
2838 struct radv_image *image)
2839 {
2840 bool flush_CB_meta = true, flush_DB_meta = true;
2841 enum radv_cmd_flush_bits flush_bits = 0;
2842 bool flush_CB = true, flush_DB = true;
2843 bool image_is_coherent = false;
2844 uint32_t b;
2845
2846 if (image) {
2847 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2848 flush_CB = false;
2849 flush_DB = false;
2850 }
2851
2852 if (!radv_image_has_CB_metadata(image))
2853 flush_CB_meta = false;
2854 if (!radv_image_has_htile(image))
2855 flush_DB_meta = false;
2856
2857 /* TODO: implement shader coherent for GFX10 */
2858
2859 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2860 if (image->info.samples == 1 &&
2861 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2862 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2863 !vk_format_is_stencil(image->vk_format)) {
2864 /* Single-sample color and single-sample depth
2865 * (not stencil) are coherent with shaders on
2866 * GFX9.
2867 */
2868 image_is_coherent = true;
2869 }
2870 }
2871 }
2872
2873 for_each_bit(b, dst_flags) {
2874 switch ((VkAccessFlagBits)(1 << b)) {
2875 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2876 case VK_ACCESS_INDEX_READ_BIT:
2877 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2878 break;
2879 case VK_ACCESS_UNIFORM_READ_BIT:
2880 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2881 break;
2882 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2883 case VK_ACCESS_TRANSFER_READ_BIT:
2884 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2885 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2886 RADV_CMD_FLAG_INV_L2;
2887 break;
2888 case VK_ACCESS_SHADER_READ_BIT:
2889 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2890 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2891 * invalidate the scalar cache. */
2892 if (cmd_buffer->device->physical_device->use_aco &&
2893 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8)
2894 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
2895
2896 if (!image_is_coherent)
2897 flush_bits |= RADV_CMD_FLAG_INV_L2;
2898 break;
2899 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2900 if (flush_CB)
2901 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2902 if (flush_CB_meta)
2903 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2904 break;
2905 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2906 if (flush_DB)
2907 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2908 if (flush_DB_meta)
2909 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2910 break;
2911 default:
2912 break;
2913 }
2914 }
2915 return flush_bits;
2916 }
2917
2918 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2919 const struct radv_subpass_barrier *barrier)
2920 {
2921 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2922 NULL);
2923 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2924 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2925 NULL);
2926 }
2927
2928 uint32_t
2929 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2930 {
2931 struct radv_cmd_state *state = &cmd_buffer->state;
2932 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2933
2934 /* The id of this subpass shouldn't exceed the number of subpasses in
2935 * this render pass minus 1.
2936 */
2937 assert(subpass_id < state->pass->subpass_count);
2938 return subpass_id;
2939 }
2940
2941 static struct radv_sample_locations_state *
2942 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2943 uint32_t att_idx,
2944 bool begin_subpass)
2945 {
2946 struct radv_cmd_state *state = &cmd_buffer->state;
2947 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2948 struct radv_image_view *view = state->attachments[att_idx].iview;
2949
2950 if (view->image->info.samples == 1)
2951 return NULL;
2952
2953 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2954 /* Return the initial sample locations if this is the initial
2955 * layout transition of the given subpass attachemnt.
2956 */
2957 if (state->attachments[att_idx].sample_location.count > 0)
2958 return &state->attachments[att_idx].sample_location;
2959 } else {
2960 /* Otherwise return the subpass sample locations if defined. */
2961 if (state->subpass_sample_locs) {
2962 /* Because the driver sets the current subpass before
2963 * initial layout transitions, we should use the sample
2964 * locations from the previous subpass to avoid an
2965 * off-by-one problem. Otherwise, use the sample
2966 * locations for the current subpass for final layout
2967 * transitions.
2968 */
2969 if (begin_subpass)
2970 subpass_id--;
2971
2972 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2973 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2974 return &state->subpass_sample_locs[i].sample_location;
2975 }
2976 }
2977 }
2978
2979 return NULL;
2980 }
2981
2982 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2983 struct radv_subpass_attachment att,
2984 bool begin_subpass)
2985 {
2986 unsigned idx = att.attachment;
2987 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
2988 struct radv_sample_locations_state *sample_locs;
2989 VkImageSubresourceRange range;
2990 range.aspectMask = view->aspect_mask;
2991 range.baseMipLevel = view->base_mip;
2992 range.levelCount = 1;
2993 range.baseArrayLayer = view->base_layer;
2994 range.layerCount = cmd_buffer->state.framebuffer->layers;
2995
2996 if (cmd_buffer->state.subpass->view_mask) {
2997 /* If the current subpass uses multiview, the driver might have
2998 * performed a fast color/depth clear to the whole image
2999 * (including all layers). To make sure the driver will
3000 * decompress the image correctly (if needed), we have to
3001 * account for the "real" number of layers. If the view mask is
3002 * sparse, this will decompress more layers than needed.
3003 */
3004 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3005 }
3006
3007 /* Get the subpass sample locations for the given attachment, if NULL
3008 * is returned the driver will use the default HW locations.
3009 */
3010 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3011 begin_subpass);
3012
3013 /* Determine if the subpass uses separate depth/stencil layouts. */
3014 bool uses_separate_depth_stencil_layouts = false;
3015 if ((cmd_buffer->state.attachments[idx].current_layout !=
3016 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3017 (att.layout != att.stencil_layout)) {
3018 uses_separate_depth_stencil_layouts = true;
3019 }
3020
3021 /* For separate layouts, perform depth and stencil transitions
3022 * separately.
3023 */
3024 if (uses_separate_depth_stencil_layouts &&
3025 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3026 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3027 /* Depth-only transitions. */
3028 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3029 radv_handle_image_transition(cmd_buffer,
3030 view->image,
3031 cmd_buffer->state.attachments[idx].current_layout,
3032 cmd_buffer->state.attachments[idx].current_in_render_loop,
3033 att.layout, att.in_render_loop,
3034 0, 0, &range, sample_locs);
3035
3036 /* Stencil-only transitions. */
3037 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3038 radv_handle_image_transition(cmd_buffer,
3039 view->image,
3040 cmd_buffer->state.attachments[idx].current_stencil_layout,
3041 cmd_buffer->state.attachments[idx].current_in_render_loop,
3042 att.stencil_layout, att.in_render_loop,
3043 0, 0, &range, sample_locs);
3044 } else {
3045 radv_handle_image_transition(cmd_buffer,
3046 view->image,
3047 cmd_buffer->state.attachments[idx].current_layout,
3048 cmd_buffer->state.attachments[idx].current_in_render_loop,
3049 att.layout, att.in_render_loop,
3050 0, 0, &range, sample_locs);
3051 }
3052
3053 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3054 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3055 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3056
3057
3058 }
3059
3060 void
3061 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3062 const struct radv_subpass *subpass)
3063 {
3064 cmd_buffer->state.subpass = subpass;
3065
3066 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3067 }
3068
3069 static VkResult
3070 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3071 struct radv_render_pass *pass,
3072 const VkRenderPassBeginInfo *info)
3073 {
3074 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3075 vk_find_struct_const(info->pNext,
3076 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3077 struct radv_cmd_state *state = &cmd_buffer->state;
3078
3079 if (!sample_locs) {
3080 state->subpass_sample_locs = NULL;
3081 return VK_SUCCESS;
3082 }
3083
3084 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3085 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3086 &sample_locs->pAttachmentInitialSampleLocations[i];
3087 uint32_t att_idx = att_sample_locs->attachmentIndex;
3088 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3089
3090 assert(vk_format_is_depth_or_stencil(image->vk_format));
3091
3092 /* From the Vulkan spec 1.1.108:
3093 *
3094 * "If the image referenced by the framebuffer attachment at
3095 * index attachmentIndex was not created with
3096 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3097 * then the values specified in sampleLocationsInfo are
3098 * ignored."
3099 */
3100 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3101 continue;
3102
3103 const VkSampleLocationsInfoEXT *sample_locs_info =
3104 &att_sample_locs->sampleLocationsInfo;
3105
3106 state->attachments[att_idx].sample_location.per_pixel =
3107 sample_locs_info->sampleLocationsPerPixel;
3108 state->attachments[att_idx].sample_location.grid_size =
3109 sample_locs_info->sampleLocationGridSize;
3110 state->attachments[att_idx].sample_location.count =
3111 sample_locs_info->sampleLocationsCount;
3112 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3113 sample_locs_info->pSampleLocations,
3114 sample_locs_info->sampleLocationsCount);
3115 }
3116
3117 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3118 sample_locs->postSubpassSampleLocationsCount *
3119 sizeof(state->subpass_sample_locs[0]),
3120 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3121 if (state->subpass_sample_locs == NULL) {
3122 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3123 return cmd_buffer->record_result;
3124 }
3125
3126 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3127
3128 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3129 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3130 &sample_locs->pPostSubpassSampleLocations[i];
3131 const VkSampleLocationsInfoEXT *sample_locs_info =
3132 &subpass_sample_locs_info->sampleLocationsInfo;
3133
3134 state->subpass_sample_locs[i].subpass_idx =
3135 subpass_sample_locs_info->subpassIndex;
3136 state->subpass_sample_locs[i].sample_location.per_pixel =
3137 sample_locs_info->sampleLocationsPerPixel;
3138 state->subpass_sample_locs[i].sample_location.grid_size =
3139 sample_locs_info->sampleLocationGridSize;
3140 state->subpass_sample_locs[i].sample_location.count =
3141 sample_locs_info->sampleLocationsCount;
3142 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3143 sample_locs_info->pSampleLocations,
3144 sample_locs_info->sampleLocationsCount);
3145 }
3146
3147 return VK_SUCCESS;
3148 }
3149
3150 static VkResult
3151 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3152 struct radv_render_pass *pass,
3153 const VkRenderPassBeginInfo *info)
3154 {
3155 struct radv_cmd_state *state = &cmd_buffer->state;
3156 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3157
3158 if (info) {
3159 attachment_info = vk_find_struct_const(info->pNext,
3160 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3161 }
3162
3163
3164 if (pass->attachment_count == 0) {
3165 state->attachments = NULL;
3166 return VK_SUCCESS;
3167 }
3168
3169 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3170 pass->attachment_count *
3171 sizeof(state->attachments[0]),
3172 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3173 if (state->attachments == NULL) {
3174 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3175 return cmd_buffer->record_result;
3176 }
3177
3178 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3179 struct radv_render_pass_attachment *att = &pass->attachments[i];
3180 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3181 VkImageAspectFlags clear_aspects = 0;
3182
3183 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3184 /* color attachment */
3185 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3186 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3187 }
3188 } else {
3189 /* depthstencil attachment */
3190 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3191 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3192 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3193 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3194 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3195 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3196 }
3197 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3198 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3199 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3200 }
3201 }
3202
3203 state->attachments[i].pending_clear_aspects = clear_aspects;
3204 state->attachments[i].cleared_views = 0;
3205 if (clear_aspects && info) {
3206 assert(info->clearValueCount > i);
3207 state->attachments[i].clear_value = info->pClearValues[i];
3208 }
3209
3210 state->attachments[i].current_layout = att->initial_layout;
3211 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3212 state->attachments[i].sample_location.count = 0;
3213
3214 struct radv_image_view *iview;
3215 if (attachment_info && attachment_info->attachmentCount > i) {
3216 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3217 } else {
3218 iview = state->framebuffer->attachments[i];
3219 }
3220
3221 state->attachments[i].iview = iview;
3222 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3223 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3224 } else {
3225 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3226 }
3227 }
3228
3229 return VK_SUCCESS;
3230 }
3231
3232 VkResult radv_AllocateCommandBuffers(
3233 VkDevice _device,
3234 const VkCommandBufferAllocateInfo *pAllocateInfo,
3235 VkCommandBuffer *pCommandBuffers)
3236 {
3237 RADV_FROM_HANDLE(radv_device, device, _device);
3238 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3239
3240 VkResult result = VK_SUCCESS;
3241 uint32_t i;
3242
3243 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3244
3245 if (!list_is_empty(&pool->free_cmd_buffers)) {
3246 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3247
3248 list_del(&cmd_buffer->pool_link);
3249 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3250
3251 result = radv_reset_cmd_buffer(cmd_buffer);
3252 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3253 cmd_buffer->level = pAllocateInfo->level;
3254
3255 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3256 } else {
3257 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3258 &pCommandBuffers[i]);
3259 }
3260 if (result != VK_SUCCESS)
3261 break;
3262 }
3263
3264 if (result != VK_SUCCESS) {
3265 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3266 i, pCommandBuffers);
3267
3268 /* From the Vulkan 1.0.66 spec:
3269 *
3270 * "vkAllocateCommandBuffers can be used to create multiple
3271 * command buffers. If the creation of any of those command
3272 * buffers fails, the implementation must destroy all
3273 * successfully created command buffer objects from this
3274 * command, set all entries of the pCommandBuffers array to
3275 * NULL and return the error."
3276 */
3277 memset(pCommandBuffers, 0,
3278 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3279 }
3280
3281 return result;
3282 }
3283
3284 void radv_FreeCommandBuffers(
3285 VkDevice device,
3286 VkCommandPool commandPool,
3287 uint32_t commandBufferCount,
3288 const VkCommandBuffer *pCommandBuffers)
3289 {
3290 for (uint32_t i = 0; i < commandBufferCount; i++) {
3291 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3292
3293 if (cmd_buffer) {
3294 if (cmd_buffer->pool) {
3295 list_del(&cmd_buffer->pool_link);
3296 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3297 } else
3298 radv_cmd_buffer_destroy(cmd_buffer);
3299
3300 }
3301 }
3302 }
3303
3304 VkResult radv_ResetCommandBuffer(
3305 VkCommandBuffer commandBuffer,
3306 VkCommandBufferResetFlags flags)
3307 {
3308 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3309 return radv_reset_cmd_buffer(cmd_buffer);
3310 }
3311
3312 VkResult radv_BeginCommandBuffer(
3313 VkCommandBuffer commandBuffer,
3314 const VkCommandBufferBeginInfo *pBeginInfo)
3315 {
3316 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3317 VkResult result = VK_SUCCESS;
3318
3319 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3320 /* If the command buffer has already been resetted with
3321 * vkResetCommandBuffer, no need to do it again.
3322 */
3323 result = radv_reset_cmd_buffer(cmd_buffer);
3324 if (result != VK_SUCCESS)
3325 return result;
3326 }
3327
3328 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3329 cmd_buffer->state.last_primitive_reset_en = -1;
3330 cmd_buffer->state.last_index_type = -1;
3331 cmd_buffer->state.last_num_instances = -1;
3332 cmd_buffer->state.last_vertex_offset = -1;
3333 cmd_buffer->state.last_first_instance = -1;
3334 cmd_buffer->state.predication_type = -1;
3335 cmd_buffer->usage_flags = pBeginInfo->flags;
3336
3337 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3338 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3339 assert(pBeginInfo->pInheritanceInfo);
3340 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3341 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3342
3343 struct radv_subpass *subpass =
3344 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3345
3346 if (cmd_buffer->state.framebuffer) {
3347 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3348 if (result != VK_SUCCESS)
3349 return result;
3350 }
3351
3352 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3353 }
3354
3355 if (unlikely(cmd_buffer->device->trace_bo)) {
3356 struct radv_device *device = cmd_buffer->device;
3357
3358 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3359 device->trace_bo);
3360
3361 radv_cmd_buffer_trace_emit(cmd_buffer);
3362 }
3363
3364 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3365
3366 return result;
3367 }
3368
3369 void radv_CmdBindVertexBuffers(
3370 VkCommandBuffer commandBuffer,
3371 uint32_t firstBinding,
3372 uint32_t bindingCount,
3373 const VkBuffer* pBuffers,
3374 const VkDeviceSize* pOffsets)
3375 {
3376 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3377 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3378 bool changed = false;
3379
3380 /* We have to defer setting up vertex buffer since we need the buffer
3381 * stride from the pipeline. */
3382
3383 assert(firstBinding + bindingCount <= MAX_VBS);
3384 for (uint32_t i = 0; i < bindingCount; i++) {
3385 uint32_t idx = firstBinding + i;
3386
3387 if (!changed &&
3388 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3389 vb[idx].offset != pOffsets[i])) {
3390 changed = true;
3391 }
3392
3393 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3394 vb[idx].offset = pOffsets[i];
3395
3396 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3397 vb[idx].buffer->bo);
3398 }
3399
3400 if (!changed) {
3401 /* No state changes. */
3402 return;
3403 }
3404
3405 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3406 }
3407
3408 static uint32_t
3409 vk_to_index_type(VkIndexType type)
3410 {
3411 switch (type) {
3412 case VK_INDEX_TYPE_UINT8_EXT:
3413 return V_028A7C_VGT_INDEX_8;
3414 case VK_INDEX_TYPE_UINT16:
3415 return V_028A7C_VGT_INDEX_16;
3416 case VK_INDEX_TYPE_UINT32:
3417 return V_028A7C_VGT_INDEX_32;
3418 default:
3419 unreachable("invalid index type");
3420 }
3421 }
3422
3423 static uint32_t
3424 radv_get_vgt_index_size(uint32_t type)
3425 {
3426 switch (type) {
3427 case V_028A7C_VGT_INDEX_8:
3428 return 1;
3429 case V_028A7C_VGT_INDEX_16:
3430 return 2;
3431 case V_028A7C_VGT_INDEX_32:
3432 return 4;
3433 default:
3434 unreachable("invalid index type");
3435 }
3436 }
3437
3438 void radv_CmdBindIndexBuffer(
3439 VkCommandBuffer commandBuffer,
3440 VkBuffer buffer,
3441 VkDeviceSize offset,
3442 VkIndexType indexType)
3443 {
3444 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3445 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3446
3447 if (cmd_buffer->state.index_buffer == index_buffer &&
3448 cmd_buffer->state.index_offset == offset &&
3449 cmd_buffer->state.index_type == indexType) {
3450 /* No state changes. */
3451 return;
3452 }
3453
3454 cmd_buffer->state.index_buffer = index_buffer;
3455 cmd_buffer->state.index_offset = offset;
3456 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3457 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3458 cmd_buffer->state.index_va += index_buffer->offset + offset;
3459
3460 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3461 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3462 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3463 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3464 }
3465
3466
3467 static void
3468 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3469 VkPipelineBindPoint bind_point,
3470 struct radv_descriptor_set *set, unsigned idx)
3471 {
3472 struct radeon_winsys *ws = cmd_buffer->device->ws;
3473
3474 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3475
3476 assert(set);
3477 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3478
3479 if (!cmd_buffer->device->use_global_bo_list) {
3480 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3481 if (set->descriptors[j])
3482 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3483 }
3484
3485 if(set->bo)
3486 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3487 }
3488
3489 void radv_CmdBindDescriptorSets(
3490 VkCommandBuffer commandBuffer,
3491 VkPipelineBindPoint pipelineBindPoint,
3492 VkPipelineLayout _layout,
3493 uint32_t firstSet,
3494 uint32_t descriptorSetCount,
3495 const VkDescriptorSet* pDescriptorSets,
3496 uint32_t dynamicOffsetCount,
3497 const uint32_t* pDynamicOffsets)
3498 {
3499 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3500 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3501 unsigned dyn_idx = 0;
3502
3503 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3504 struct radv_descriptor_state *descriptors_state =
3505 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3506
3507 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3508 unsigned idx = i + firstSet;
3509 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3510
3511 /* If the set is already bound we only need to update the
3512 * (potentially changed) dynamic offsets. */
3513 if (descriptors_state->sets[idx] != set ||
3514 !(descriptors_state->valid & (1u << idx))) {
3515 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3516 }
3517
3518 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3519 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3520 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3521 assert(dyn_idx < dynamicOffsetCount);
3522
3523 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3524 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3525 dst[0] = va;
3526 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3527 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3528 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3529 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3530 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3531 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3532
3533 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3534 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3535 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3536 S_008F0C_RESOURCE_LEVEL(1);
3537 } else {
3538 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3539 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3540 }
3541
3542 cmd_buffer->push_constant_stages |=
3543 set->layout->dynamic_shader_stages;
3544 }
3545 }
3546 }
3547
3548 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3549 struct radv_descriptor_set *set,
3550 struct radv_descriptor_set_layout *layout,
3551 VkPipelineBindPoint bind_point)
3552 {
3553 struct radv_descriptor_state *descriptors_state =
3554 radv_get_descriptors_state(cmd_buffer, bind_point);
3555 set->size = layout->size;
3556 set->layout = layout;
3557
3558 if (descriptors_state->push_set.capacity < set->size) {
3559 size_t new_size = MAX2(set->size, 1024);
3560 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3561 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3562
3563 free(set->mapped_ptr);
3564 set->mapped_ptr = malloc(new_size);
3565
3566 if (!set->mapped_ptr) {
3567 descriptors_state->push_set.capacity = 0;
3568 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3569 return false;
3570 }
3571
3572 descriptors_state->push_set.capacity = new_size;
3573 }
3574
3575 return true;
3576 }
3577
3578 void radv_meta_push_descriptor_set(
3579 struct radv_cmd_buffer* cmd_buffer,
3580 VkPipelineBindPoint pipelineBindPoint,
3581 VkPipelineLayout _layout,
3582 uint32_t set,
3583 uint32_t descriptorWriteCount,
3584 const VkWriteDescriptorSet* pDescriptorWrites)
3585 {
3586 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3587 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3588 unsigned bo_offset;
3589
3590 assert(set == 0);
3591 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3592
3593 push_set->size = layout->set[set].layout->size;
3594 push_set->layout = layout->set[set].layout;
3595
3596 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3597 &bo_offset,
3598 (void**) &push_set->mapped_ptr))
3599 return;
3600
3601 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3602 push_set->va += bo_offset;
3603
3604 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3605 radv_descriptor_set_to_handle(push_set),
3606 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3607
3608 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3609 }
3610
3611 void radv_CmdPushDescriptorSetKHR(
3612 VkCommandBuffer commandBuffer,
3613 VkPipelineBindPoint pipelineBindPoint,
3614 VkPipelineLayout _layout,
3615 uint32_t set,
3616 uint32_t descriptorWriteCount,
3617 const VkWriteDescriptorSet* pDescriptorWrites)
3618 {
3619 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3620 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3621 struct radv_descriptor_state *descriptors_state =
3622 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3623 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3624
3625 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3626
3627 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3628 layout->set[set].layout,
3629 pipelineBindPoint))
3630 return;
3631
3632 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3633 * because it is invalid, according to Vulkan spec.
3634 */
3635 for (int i = 0; i < descriptorWriteCount; i++) {
3636 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3637 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3638 }
3639
3640 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3641 radv_descriptor_set_to_handle(push_set),
3642 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3643
3644 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3645 descriptors_state->push_dirty = true;
3646 }
3647
3648 void radv_CmdPushDescriptorSetWithTemplateKHR(
3649 VkCommandBuffer commandBuffer,
3650 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3651 VkPipelineLayout _layout,
3652 uint32_t set,
3653 const void* pData)
3654 {
3655 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3656 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3657 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3658 struct radv_descriptor_state *descriptors_state =
3659 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3660 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3661
3662 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3663
3664 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3665 layout->set[set].layout,
3666 templ->bind_point))
3667 return;
3668
3669 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3670 descriptorUpdateTemplate, pData);
3671
3672 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3673 descriptors_state->push_dirty = true;
3674 }
3675
3676 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3677 VkPipelineLayout layout,
3678 VkShaderStageFlags stageFlags,
3679 uint32_t offset,
3680 uint32_t size,
3681 const void* pValues)
3682 {
3683 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3684 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3685 cmd_buffer->push_constant_stages |= stageFlags;
3686 }
3687
3688 VkResult radv_EndCommandBuffer(
3689 VkCommandBuffer commandBuffer)
3690 {
3691 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3692
3693 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3694 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3695 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3696
3697 /* Make sure to sync all pending active queries at the end of
3698 * command buffer.
3699 */
3700 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3701
3702 /* Since NGG streamout uses GDS, we need to make GDS idle when
3703 * we leave the IB, otherwise another process might overwrite
3704 * it while our shaders are busy.
3705 */
3706 if (cmd_buffer->gds_needed)
3707 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3708
3709 si_emit_cache_flush(cmd_buffer);
3710 }
3711
3712 /* Make sure CP DMA is idle at the end of IBs because the kernel
3713 * doesn't wait for it.
3714 */
3715 si_cp_dma_wait_for_idle(cmd_buffer);
3716
3717 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3718 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3719
3720 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3721 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3722
3723 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3724
3725 return cmd_buffer->record_result;
3726 }
3727
3728 static void
3729 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3730 {
3731 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3732
3733 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3734 return;
3735
3736 assert(!pipeline->ctx_cs.cdw);
3737
3738 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3739
3740 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3741 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3742
3743 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
3744 pipeline->scratch_bytes_per_wave);
3745 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
3746 pipeline->max_waves);
3747
3748 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3749 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3750
3751 if (unlikely(cmd_buffer->device->trace_bo))
3752 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3753 }
3754
3755 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3756 VkPipelineBindPoint bind_point)
3757 {
3758 struct radv_descriptor_state *descriptors_state =
3759 radv_get_descriptors_state(cmd_buffer, bind_point);
3760
3761 descriptors_state->dirty |= descriptors_state->valid;
3762 }
3763
3764 void radv_CmdBindPipeline(
3765 VkCommandBuffer commandBuffer,
3766 VkPipelineBindPoint pipelineBindPoint,
3767 VkPipeline _pipeline)
3768 {
3769 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3770 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3771
3772 switch (pipelineBindPoint) {
3773 case VK_PIPELINE_BIND_POINT_COMPUTE:
3774 if (cmd_buffer->state.compute_pipeline == pipeline)
3775 return;
3776 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3777
3778 cmd_buffer->state.compute_pipeline = pipeline;
3779 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3780 break;
3781 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3782 if (cmd_buffer->state.pipeline == pipeline)
3783 return;
3784 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3785
3786 cmd_buffer->state.pipeline = pipeline;
3787 if (!pipeline)
3788 break;
3789
3790 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3791 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3792
3793 /* the new vertex shader might not have the same user regs */
3794 cmd_buffer->state.last_first_instance = -1;
3795 cmd_buffer->state.last_vertex_offset = -1;
3796
3797 /* Prefetch all pipeline shaders at first draw time. */
3798 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3799
3800 if ((cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3801 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3802 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3803 cmd_buffer->state.emitted_pipeline &&
3804 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3805 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3806 /* Transitioning from NGG to legacy GS requires
3807 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3808 * at the beginning of IBs when legacy GS ring pointers
3809 * are set.
3810 */
3811 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3812 }
3813
3814 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3815 radv_bind_streamout_state(cmd_buffer, pipeline);
3816
3817 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3818 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3819 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3820 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3821
3822 if (radv_pipeline_has_tess(pipeline))
3823 cmd_buffer->tess_rings_needed = true;
3824 break;
3825 default:
3826 assert(!"invalid bind point");
3827 break;
3828 }
3829 }
3830
3831 void radv_CmdSetViewport(
3832 VkCommandBuffer commandBuffer,
3833 uint32_t firstViewport,
3834 uint32_t viewportCount,
3835 const VkViewport* pViewports)
3836 {
3837 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3838 struct radv_cmd_state *state = &cmd_buffer->state;
3839 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
3840
3841 assert(firstViewport < MAX_VIEWPORTS);
3842 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3843
3844 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3845 pViewports, viewportCount * sizeof(*pViewports))) {
3846 return;
3847 }
3848
3849 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3850 viewportCount * sizeof(*pViewports));
3851
3852 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3853 }
3854
3855 void radv_CmdSetScissor(
3856 VkCommandBuffer commandBuffer,
3857 uint32_t firstScissor,
3858 uint32_t scissorCount,
3859 const VkRect2D* pScissors)
3860 {
3861 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3862 struct radv_cmd_state *state = &cmd_buffer->state;
3863 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
3864
3865 assert(firstScissor < MAX_SCISSORS);
3866 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3867
3868 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3869 scissorCount * sizeof(*pScissors))) {
3870 return;
3871 }
3872
3873 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3874 scissorCount * sizeof(*pScissors));
3875
3876 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3877 }
3878
3879 void radv_CmdSetLineWidth(
3880 VkCommandBuffer commandBuffer,
3881 float lineWidth)
3882 {
3883 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3884
3885 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3886 return;
3887
3888 cmd_buffer->state.dynamic.line_width = lineWidth;
3889 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3890 }
3891
3892 void radv_CmdSetDepthBias(
3893 VkCommandBuffer commandBuffer,
3894 float depthBiasConstantFactor,
3895 float depthBiasClamp,
3896 float depthBiasSlopeFactor)
3897 {
3898 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3899 struct radv_cmd_state *state = &cmd_buffer->state;
3900
3901 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3902 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3903 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3904 return;
3905 }
3906
3907 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3908 state->dynamic.depth_bias.clamp = depthBiasClamp;
3909 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3910
3911 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3912 }
3913
3914 void radv_CmdSetBlendConstants(
3915 VkCommandBuffer commandBuffer,
3916 const float blendConstants[4])
3917 {
3918 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3919 struct radv_cmd_state *state = &cmd_buffer->state;
3920
3921 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3922 return;
3923
3924 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3925
3926 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3927 }
3928
3929 void radv_CmdSetDepthBounds(
3930 VkCommandBuffer commandBuffer,
3931 float minDepthBounds,
3932 float maxDepthBounds)
3933 {
3934 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3935 struct radv_cmd_state *state = &cmd_buffer->state;
3936
3937 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3938 state->dynamic.depth_bounds.max == maxDepthBounds) {
3939 return;
3940 }
3941
3942 state->dynamic.depth_bounds.min = minDepthBounds;
3943 state->dynamic.depth_bounds.max = maxDepthBounds;
3944
3945 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3946 }
3947
3948 void radv_CmdSetStencilCompareMask(
3949 VkCommandBuffer commandBuffer,
3950 VkStencilFaceFlags faceMask,
3951 uint32_t compareMask)
3952 {
3953 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3954 struct radv_cmd_state *state = &cmd_buffer->state;
3955 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3956 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3957
3958 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3959 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3960 return;
3961 }
3962
3963 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3964 state->dynamic.stencil_compare_mask.front = compareMask;
3965 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3966 state->dynamic.stencil_compare_mask.back = compareMask;
3967
3968 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3969 }
3970
3971 void radv_CmdSetStencilWriteMask(
3972 VkCommandBuffer commandBuffer,
3973 VkStencilFaceFlags faceMask,
3974 uint32_t writeMask)
3975 {
3976 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3977 struct radv_cmd_state *state = &cmd_buffer->state;
3978 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3979 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3980
3981 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3982 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3983 return;
3984 }
3985
3986 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3987 state->dynamic.stencil_write_mask.front = writeMask;
3988 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3989 state->dynamic.stencil_write_mask.back = writeMask;
3990
3991 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3992 }
3993
3994 void radv_CmdSetStencilReference(
3995 VkCommandBuffer commandBuffer,
3996 VkStencilFaceFlags faceMask,
3997 uint32_t reference)
3998 {
3999 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4000 struct radv_cmd_state *state = &cmd_buffer->state;
4001 bool front_same = state->dynamic.stencil_reference.front == reference;
4002 bool back_same = state->dynamic.stencil_reference.back == reference;
4003
4004 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4005 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4006 return;
4007 }
4008
4009 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4010 cmd_buffer->state.dynamic.stencil_reference.front = reference;
4011 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4012 cmd_buffer->state.dynamic.stencil_reference.back = reference;
4013
4014 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
4015 }
4016
4017 void radv_CmdSetDiscardRectangleEXT(
4018 VkCommandBuffer commandBuffer,
4019 uint32_t firstDiscardRectangle,
4020 uint32_t discardRectangleCount,
4021 const VkRect2D* pDiscardRectangles)
4022 {
4023 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4024 struct radv_cmd_state *state = &cmd_buffer->state;
4025 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
4026
4027 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
4028 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
4029
4030 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
4031 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
4032 return;
4033 }
4034
4035 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
4036 pDiscardRectangles, discardRectangleCount);
4037
4038 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
4039 }
4040
4041 void radv_CmdSetSampleLocationsEXT(
4042 VkCommandBuffer commandBuffer,
4043 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
4044 {
4045 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4046 struct radv_cmd_state *state = &cmd_buffer->state;
4047
4048 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
4049
4050 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
4051 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
4052 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
4053 typed_memcpy(&state->dynamic.sample_location.locations[0],
4054 pSampleLocationsInfo->pSampleLocations,
4055 pSampleLocationsInfo->sampleLocationsCount);
4056
4057 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
4058 }
4059
4060 void radv_CmdExecuteCommands(
4061 VkCommandBuffer commandBuffer,
4062 uint32_t commandBufferCount,
4063 const VkCommandBuffer* pCmdBuffers)
4064 {
4065 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4066
4067 assert(commandBufferCount > 0);
4068
4069 /* Emit pending flushes on primary prior to executing secondary */
4070 si_emit_cache_flush(primary);
4071
4072 for (uint32_t i = 0; i < commandBufferCount; i++) {
4073 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4074
4075 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4076 secondary->scratch_size_per_wave_needed);
4077 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4078 secondary->scratch_waves_wanted);
4079 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4080 secondary->compute_scratch_size_per_wave_needed);
4081 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4082 secondary->compute_scratch_waves_wanted);
4083
4084 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4085 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4086 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4087 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4088 if (secondary->tess_rings_needed)
4089 primary->tess_rings_needed = true;
4090 if (secondary->sample_positions_needed)
4091 primary->sample_positions_needed = true;
4092
4093 if (!secondary->state.framebuffer &&
4094 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4095 /* Emit the framebuffer state from primary if secondary
4096 * has been recorded without a framebuffer, otherwise
4097 * fast color/depth clears can't work.
4098 */
4099 radv_emit_framebuffer_state(primary);
4100 }
4101
4102 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4103
4104
4105 /* When the secondary command buffer is compute only we don't
4106 * need to re-emit the current graphics pipeline.
4107 */
4108 if (secondary->state.emitted_pipeline) {
4109 primary->state.emitted_pipeline =
4110 secondary->state.emitted_pipeline;
4111 }
4112
4113 /* When the secondary command buffer is graphics only we don't
4114 * need to re-emit the current compute pipeline.
4115 */
4116 if (secondary->state.emitted_compute_pipeline) {
4117 primary->state.emitted_compute_pipeline =
4118 secondary->state.emitted_compute_pipeline;
4119 }
4120
4121 /* Only re-emit the draw packets when needed. */
4122 if (secondary->state.last_primitive_reset_en != -1) {
4123 primary->state.last_primitive_reset_en =
4124 secondary->state.last_primitive_reset_en;
4125 }
4126
4127 if (secondary->state.last_primitive_reset_index) {
4128 primary->state.last_primitive_reset_index =
4129 secondary->state.last_primitive_reset_index;
4130 }
4131
4132 if (secondary->state.last_ia_multi_vgt_param) {
4133 primary->state.last_ia_multi_vgt_param =
4134 secondary->state.last_ia_multi_vgt_param;
4135 }
4136
4137 primary->state.last_first_instance = secondary->state.last_first_instance;
4138 primary->state.last_num_instances = secondary->state.last_num_instances;
4139 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4140
4141 if (secondary->state.last_index_type != -1) {
4142 primary->state.last_index_type =
4143 secondary->state.last_index_type;
4144 }
4145 }
4146
4147 /* After executing commands from secondary buffers we have to dirty
4148 * some states.
4149 */
4150 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4151 RADV_CMD_DIRTY_INDEX_BUFFER |
4152 RADV_CMD_DIRTY_DYNAMIC_ALL;
4153 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4154 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4155 }
4156
4157 VkResult radv_CreateCommandPool(
4158 VkDevice _device,
4159 const VkCommandPoolCreateInfo* pCreateInfo,
4160 const VkAllocationCallbacks* pAllocator,
4161 VkCommandPool* pCmdPool)
4162 {
4163 RADV_FROM_HANDLE(radv_device, device, _device);
4164 struct radv_cmd_pool *pool;
4165
4166 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
4167 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4168 if (pool == NULL)
4169 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4170
4171 if (pAllocator)
4172 pool->alloc = *pAllocator;
4173 else
4174 pool->alloc = device->alloc;
4175
4176 list_inithead(&pool->cmd_buffers);
4177 list_inithead(&pool->free_cmd_buffers);
4178
4179 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4180
4181 *pCmdPool = radv_cmd_pool_to_handle(pool);
4182
4183 return VK_SUCCESS;
4184
4185 }
4186
4187 void radv_DestroyCommandPool(
4188 VkDevice _device,
4189 VkCommandPool commandPool,
4190 const VkAllocationCallbacks* pAllocator)
4191 {
4192 RADV_FROM_HANDLE(radv_device, device, _device);
4193 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4194
4195 if (!pool)
4196 return;
4197
4198 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4199 &pool->cmd_buffers, pool_link) {
4200 radv_cmd_buffer_destroy(cmd_buffer);
4201 }
4202
4203 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4204 &pool->free_cmd_buffers, pool_link) {
4205 radv_cmd_buffer_destroy(cmd_buffer);
4206 }
4207
4208 vk_free2(&device->alloc, pAllocator, pool);
4209 }
4210
4211 VkResult radv_ResetCommandPool(
4212 VkDevice device,
4213 VkCommandPool commandPool,
4214 VkCommandPoolResetFlags flags)
4215 {
4216 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4217 VkResult result;
4218
4219 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4220 &pool->cmd_buffers, pool_link) {
4221 result = radv_reset_cmd_buffer(cmd_buffer);
4222 if (result != VK_SUCCESS)
4223 return result;
4224 }
4225
4226 return VK_SUCCESS;
4227 }
4228
4229 void radv_TrimCommandPool(
4230 VkDevice device,
4231 VkCommandPool commandPool,
4232 VkCommandPoolTrimFlags flags)
4233 {
4234 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4235
4236 if (!pool)
4237 return;
4238
4239 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4240 &pool->free_cmd_buffers, pool_link) {
4241 radv_cmd_buffer_destroy(cmd_buffer);
4242 }
4243 }
4244
4245 static void
4246 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4247 uint32_t subpass_id)
4248 {
4249 struct radv_cmd_state *state = &cmd_buffer->state;
4250 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4251
4252 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4253 cmd_buffer->cs, 4096);
4254
4255 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4256
4257 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4258
4259 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4260 const uint32_t a = subpass->attachments[i].attachment;
4261 if (a == VK_ATTACHMENT_UNUSED)
4262 continue;
4263
4264 radv_handle_subpass_image_transition(cmd_buffer,
4265 subpass->attachments[i],
4266 true);
4267 }
4268
4269 radv_cmd_buffer_clear_subpass(cmd_buffer);
4270
4271 assert(cmd_buffer->cs->cdw <= cdw_max);
4272 }
4273
4274 static void
4275 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4276 {
4277 struct radv_cmd_state *state = &cmd_buffer->state;
4278 const struct radv_subpass *subpass = state->subpass;
4279 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4280
4281 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4282
4283 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4284 const uint32_t a = subpass->attachments[i].attachment;
4285 if (a == VK_ATTACHMENT_UNUSED)
4286 continue;
4287
4288 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4289 continue;
4290
4291 VkImageLayout layout = state->pass->attachments[a].final_layout;
4292 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
4293 struct radv_subpass_attachment att = { a, layout, stencil_layout };
4294 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4295 }
4296 }
4297
4298 void radv_CmdBeginRenderPass(
4299 VkCommandBuffer commandBuffer,
4300 const VkRenderPassBeginInfo* pRenderPassBegin,
4301 VkSubpassContents contents)
4302 {
4303 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4304 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4305 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4306 VkResult result;
4307
4308 cmd_buffer->state.framebuffer = framebuffer;
4309 cmd_buffer->state.pass = pass;
4310 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4311
4312 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4313 if (result != VK_SUCCESS)
4314 return;
4315
4316 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4317 if (result != VK_SUCCESS)
4318 return;
4319
4320 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4321 }
4322
4323 void radv_CmdBeginRenderPass2(
4324 VkCommandBuffer commandBuffer,
4325 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4326 const VkSubpassBeginInfo* pSubpassBeginInfo)
4327 {
4328 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4329 pSubpassBeginInfo->contents);
4330 }
4331
4332 void radv_CmdNextSubpass(
4333 VkCommandBuffer commandBuffer,
4334 VkSubpassContents contents)
4335 {
4336 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4337
4338 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4339 radv_cmd_buffer_end_subpass(cmd_buffer);
4340 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4341 }
4342
4343 void radv_CmdNextSubpass2(
4344 VkCommandBuffer commandBuffer,
4345 const VkSubpassBeginInfo* pSubpassBeginInfo,
4346 const VkSubpassEndInfo* pSubpassEndInfo)
4347 {
4348 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4349 }
4350
4351 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4352 {
4353 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4354 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4355 if (!radv_get_shader(pipeline, stage))
4356 continue;
4357
4358 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4359 if (loc->sgpr_idx == -1)
4360 continue;
4361 uint32_t base_reg = pipeline->user_data_0[stage];
4362 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4363
4364 }
4365 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4366 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4367 if (loc->sgpr_idx != -1) {
4368 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4369 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4370 }
4371 }
4372 }
4373
4374 static void
4375 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4376 uint32_t vertex_count,
4377 bool use_opaque)
4378 {
4379 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4380 radeon_emit(cmd_buffer->cs, vertex_count);
4381 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4382 S_0287F0_USE_OPAQUE(use_opaque));
4383 }
4384
4385 static void
4386 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4387 uint64_t index_va,
4388 uint32_t index_count)
4389 {
4390 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4391 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4392 radeon_emit(cmd_buffer->cs, index_va);
4393 radeon_emit(cmd_buffer->cs, index_va >> 32);
4394 radeon_emit(cmd_buffer->cs, index_count);
4395 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4396 }
4397
4398 static void
4399 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4400 bool indexed,
4401 uint32_t draw_count,
4402 uint64_t count_va,
4403 uint32_t stride)
4404 {
4405 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4406 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4407 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4408 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4409 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4410 bool predicating = cmd_buffer->state.predicating;
4411 assert(base_reg);
4412
4413 /* just reset draw state for vertex data */
4414 cmd_buffer->state.last_first_instance = -1;
4415 cmd_buffer->state.last_num_instances = -1;
4416 cmd_buffer->state.last_vertex_offset = -1;
4417
4418 if (draw_count == 1 && !count_va && !draw_id_enable) {
4419 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4420 PKT3_DRAW_INDIRECT, 3, predicating));
4421 radeon_emit(cs, 0);
4422 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4423 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4424 radeon_emit(cs, di_src_sel);
4425 } else {
4426 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4427 PKT3_DRAW_INDIRECT_MULTI,
4428 8, predicating));
4429 radeon_emit(cs, 0);
4430 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4431 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4432 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4433 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4434 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4435 radeon_emit(cs, draw_count); /* count */
4436 radeon_emit(cs, count_va); /* count_addr */
4437 radeon_emit(cs, count_va >> 32);
4438 radeon_emit(cs, stride); /* stride */
4439 radeon_emit(cs, di_src_sel);
4440 }
4441 }
4442
4443 static void
4444 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4445 const struct radv_draw_info *info)
4446 {
4447 struct radv_cmd_state *state = &cmd_buffer->state;
4448 struct radeon_winsys *ws = cmd_buffer->device->ws;
4449 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4450
4451 if (info->indirect) {
4452 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4453 uint64_t count_va = 0;
4454
4455 va += info->indirect->offset + info->indirect_offset;
4456
4457 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4458
4459 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4460 radeon_emit(cs, 1);
4461 radeon_emit(cs, va);
4462 radeon_emit(cs, va >> 32);
4463
4464 if (info->count_buffer) {
4465 count_va = radv_buffer_get_va(info->count_buffer->bo);
4466 count_va += info->count_buffer->offset +
4467 info->count_buffer_offset;
4468
4469 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4470 }
4471
4472 if (!state->subpass->view_mask) {
4473 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4474 info->indexed,
4475 info->count,
4476 count_va,
4477 info->stride);
4478 } else {
4479 unsigned i;
4480 for_each_bit(i, state->subpass->view_mask) {
4481 radv_emit_view_index(cmd_buffer, i);
4482
4483 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4484 info->indexed,
4485 info->count,
4486 count_va,
4487 info->stride);
4488 }
4489 }
4490 } else {
4491 assert(state->pipeline->graphics.vtx_base_sgpr);
4492
4493 if (info->vertex_offset != state->last_vertex_offset ||
4494 info->first_instance != state->last_first_instance) {
4495 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4496 state->pipeline->graphics.vtx_emit_num);
4497
4498 radeon_emit(cs, info->vertex_offset);
4499 radeon_emit(cs, info->first_instance);
4500 if (state->pipeline->graphics.vtx_emit_num == 3)
4501 radeon_emit(cs, 0);
4502 state->last_first_instance = info->first_instance;
4503 state->last_vertex_offset = info->vertex_offset;
4504 }
4505
4506 if (state->last_num_instances != info->instance_count) {
4507 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4508 radeon_emit(cs, info->instance_count);
4509 state->last_num_instances = info->instance_count;
4510 }
4511
4512 if (info->indexed) {
4513 int index_size = radv_get_vgt_index_size(state->index_type);
4514 uint64_t index_va;
4515
4516 /* Skip draw calls with 0-sized index buffers. They
4517 * cause a hang on some chips, like Navi10-14.
4518 */
4519 if (!cmd_buffer->state.max_index_count)
4520 return;
4521
4522 index_va = state->index_va;
4523 index_va += info->first_index * index_size;
4524
4525 if (!state->subpass->view_mask) {
4526 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4527 index_va,
4528 info->count);
4529 } else {
4530 unsigned i;
4531 for_each_bit(i, state->subpass->view_mask) {
4532 radv_emit_view_index(cmd_buffer, i);
4533
4534 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4535 index_va,
4536 info->count);
4537 }
4538 }
4539 } else {
4540 if (!state->subpass->view_mask) {
4541 radv_cs_emit_draw_packet(cmd_buffer,
4542 info->count,
4543 !!info->strmout_buffer);
4544 } else {
4545 unsigned i;
4546 for_each_bit(i, state->subpass->view_mask) {
4547 radv_emit_view_index(cmd_buffer, i);
4548
4549 radv_cs_emit_draw_packet(cmd_buffer,
4550 info->count,
4551 !!info->strmout_buffer);
4552 }
4553 }
4554 }
4555 }
4556 }
4557
4558 /*
4559 * Vega and raven have a bug which triggers if there are multiple context
4560 * register contexts active at the same time with different scissor values.
4561 *
4562 * There are two possible workarounds:
4563 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4564 * there is only ever 1 active set of scissor values at the same time.
4565 *
4566 * 2) Whenever the hardware switches contexts we have to set the scissor
4567 * registers again even if it is a noop. That way the new context gets
4568 * the correct scissor values.
4569 *
4570 * This implements option 2. radv_need_late_scissor_emission needs to
4571 * return true on affected HW if radv_emit_all_graphics_states sets
4572 * any context registers.
4573 */
4574 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4575 const struct radv_draw_info *info)
4576 {
4577 struct radv_cmd_state *state = &cmd_buffer->state;
4578
4579 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
4580 return false;
4581
4582 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4583 return true;
4584
4585 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4586
4587 /* Index, vertex and streamout buffers don't change context regs, and
4588 * pipeline is already handled.
4589 */
4590 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4591 RADV_CMD_DIRTY_VERTEX_BUFFER |
4592 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4593 RADV_CMD_DIRTY_PIPELINE);
4594
4595 if (cmd_buffer->state.dirty & used_states)
4596 return true;
4597
4598 uint32_t primitive_reset_index =
4599 radv_get_primitive_reset_index(cmd_buffer);
4600
4601 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4602 primitive_reset_index != state->last_primitive_reset_index)
4603 return true;
4604
4605 return false;
4606 }
4607
4608 static void
4609 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4610 const struct radv_draw_info *info)
4611 {
4612 bool late_scissor_emission;
4613
4614 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4615 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4616 radv_emit_rbplus_state(cmd_buffer);
4617
4618 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4619 radv_emit_graphics_pipeline(cmd_buffer);
4620
4621 /* This should be before the cmd_buffer->state.dirty is cleared
4622 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4623 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4624 late_scissor_emission =
4625 radv_need_late_scissor_emission(cmd_buffer, info);
4626
4627 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4628 radv_emit_framebuffer_state(cmd_buffer);
4629
4630 if (info->indexed) {
4631 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4632 radv_emit_index_buffer(cmd_buffer);
4633 } else {
4634 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4635 * so the state must be re-emitted before the next indexed
4636 * draw.
4637 */
4638 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4639 cmd_buffer->state.last_index_type = -1;
4640 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4641 }
4642 }
4643
4644 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4645
4646 radv_emit_draw_registers(cmd_buffer, info);
4647
4648 if (late_scissor_emission)
4649 radv_emit_scissor(cmd_buffer);
4650 }
4651
4652 static void
4653 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4654 const struct radv_draw_info *info)
4655 {
4656 struct radeon_info *rad_info =
4657 &cmd_buffer->device->physical_device->rad_info;
4658 bool has_prefetch =
4659 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4660 bool pipeline_is_dirty =
4661 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4662 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4663
4664 ASSERTED unsigned cdw_max =
4665 radeon_check_space(cmd_buffer->device->ws,
4666 cmd_buffer->cs, 4096);
4667
4668 if (likely(!info->indirect)) {
4669 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4670 * no workaround for indirect draws, but we can at least skip
4671 * direct draws.
4672 */
4673 if (unlikely(!info->instance_count))
4674 return;
4675
4676 /* Handle count == 0. */
4677 if (unlikely(!info->count && !info->strmout_buffer))
4678 return;
4679 }
4680
4681 /* Use optimal packet order based on whether we need to sync the
4682 * pipeline.
4683 */
4684 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4685 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4686 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4687 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4688 /* If we have to wait for idle, set all states first, so that
4689 * all SET packets are processed in parallel with previous draw
4690 * calls. Then upload descriptors, set shader pointers, and
4691 * draw, and prefetch at the end. This ensures that the time
4692 * the CUs are idle is very short. (there are only SET_SH
4693 * packets between the wait and the draw)
4694 */
4695 radv_emit_all_graphics_states(cmd_buffer, info);
4696 si_emit_cache_flush(cmd_buffer);
4697 /* <-- CUs are idle here --> */
4698
4699 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4700
4701 radv_emit_draw_packets(cmd_buffer, info);
4702 /* <-- CUs are busy here --> */
4703
4704 /* Start prefetches after the draw has been started. Both will
4705 * run in parallel, but starting the draw first is more
4706 * important.
4707 */
4708 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4709 radv_emit_prefetch_L2(cmd_buffer,
4710 cmd_buffer->state.pipeline, false);
4711 }
4712 } else {
4713 /* If we don't wait for idle, start prefetches first, then set
4714 * states, and draw at the end.
4715 */
4716 si_emit_cache_flush(cmd_buffer);
4717
4718 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4719 /* Only prefetch the vertex shader and VBO descriptors
4720 * in order to start the draw as soon as possible.
4721 */
4722 radv_emit_prefetch_L2(cmd_buffer,
4723 cmd_buffer->state.pipeline, true);
4724 }
4725
4726 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4727
4728 radv_emit_all_graphics_states(cmd_buffer, info);
4729 radv_emit_draw_packets(cmd_buffer, info);
4730
4731 /* Prefetch the remaining shaders after the draw has been
4732 * started.
4733 */
4734 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4735 radv_emit_prefetch_L2(cmd_buffer,
4736 cmd_buffer->state.pipeline, false);
4737 }
4738 }
4739
4740 /* Workaround for a VGT hang when streamout is enabled.
4741 * It must be done after drawing.
4742 */
4743 if (cmd_buffer->state.streamout.streamout_enabled &&
4744 (rad_info->family == CHIP_HAWAII ||
4745 rad_info->family == CHIP_TONGA ||
4746 rad_info->family == CHIP_FIJI)) {
4747 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4748 }
4749
4750 assert(cmd_buffer->cs->cdw <= cdw_max);
4751 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4752 }
4753
4754 void radv_CmdDraw(
4755 VkCommandBuffer commandBuffer,
4756 uint32_t vertexCount,
4757 uint32_t instanceCount,
4758 uint32_t firstVertex,
4759 uint32_t firstInstance)
4760 {
4761 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4762 struct radv_draw_info info = {};
4763
4764 info.count = vertexCount;
4765 info.instance_count = instanceCount;
4766 info.first_instance = firstInstance;
4767 info.vertex_offset = firstVertex;
4768
4769 radv_draw(cmd_buffer, &info);
4770 }
4771
4772 void radv_CmdDrawIndexed(
4773 VkCommandBuffer commandBuffer,
4774 uint32_t indexCount,
4775 uint32_t instanceCount,
4776 uint32_t firstIndex,
4777 int32_t vertexOffset,
4778 uint32_t firstInstance)
4779 {
4780 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4781 struct radv_draw_info info = {};
4782
4783 info.indexed = true;
4784 info.count = indexCount;
4785 info.instance_count = instanceCount;
4786 info.first_index = firstIndex;
4787 info.vertex_offset = vertexOffset;
4788 info.first_instance = firstInstance;
4789
4790 radv_draw(cmd_buffer, &info);
4791 }
4792
4793 void radv_CmdDrawIndirect(
4794 VkCommandBuffer commandBuffer,
4795 VkBuffer _buffer,
4796 VkDeviceSize offset,
4797 uint32_t drawCount,
4798 uint32_t stride)
4799 {
4800 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4801 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4802 struct radv_draw_info info = {};
4803
4804 info.count = drawCount;
4805 info.indirect = buffer;
4806 info.indirect_offset = offset;
4807 info.stride = stride;
4808
4809 radv_draw(cmd_buffer, &info);
4810 }
4811
4812 void radv_CmdDrawIndexedIndirect(
4813 VkCommandBuffer commandBuffer,
4814 VkBuffer _buffer,
4815 VkDeviceSize offset,
4816 uint32_t drawCount,
4817 uint32_t stride)
4818 {
4819 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4820 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4821 struct radv_draw_info info = {};
4822
4823 info.indexed = true;
4824 info.count = drawCount;
4825 info.indirect = buffer;
4826 info.indirect_offset = offset;
4827 info.stride = stride;
4828
4829 radv_draw(cmd_buffer, &info);
4830 }
4831
4832 void radv_CmdDrawIndirectCount(
4833 VkCommandBuffer commandBuffer,
4834 VkBuffer _buffer,
4835 VkDeviceSize offset,
4836 VkBuffer _countBuffer,
4837 VkDeviceSize countBufferOffset,
4838 uint32_t maxDrawCount,
4839 uint32_t stride)
4840 {
4841 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4842 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4843 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4844 struct radv_draw_info info = {};
4845
4846 info.count = maxDrawCount;
4847 info.indirect = buffer;
4848 info.indirect_offset = offset;
4849 info.count_buffer = count_buffer;
4850 info.count_buffer_offset = countBufferOffset;
4851 info.stride = stride;
4852
4853 radv_draw(cmd_buffer, &info);
4854 }
4855
4856 void radv_CmdDrawIndexedIndirectCount(
4857 VkCommandBuffer commandBuffer,
4858 VkBuffer _buffer,
4859 VkDeviceSize offset,
4860 VkBuffer _countBuffer,
4861 VkDeviceSize countBufferOffset,
4862 uint32_t maxDrawCount,
4863 uint32_t stride)
4864 {
4865 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4866 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4867 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4868 struct radv_draw_info info = {};
4869
4870 info.indexed = true;
4871 info.count = maxDrawCount;
4872 info.indirect = buffer;
4873 info.indirect_offset = offset;
4874 info.count_buffer = count_buffer;
4875 info.count_buffer_offset = countBufferOffset;
4876 info.stride = stride;
4877
4878 radv_draw(cmd_buffer, &info);
4879 }
4880
4881 struct radv_dispatch_info {
4882 /**
4883 * Determine the layout of the grid (in block units) to be used.
4884 */
4885 uint32_t blocks[3];
4886
4887 /**
4888 * A starting offset for the grid. If unaligned is set, the offset
4889 * must still be aligned.
4890 */
4891 uint32_t offsets[3];
4892 /**
4893 * Whether it's an unaligned compute dispatch.
4894 */
4895 bool unaligned;
4896
4897 /**
4898 * Indirect compute parameters resource.
4899 */
4900 struct radv_buffer *indirect;
4901 uint64_t indirect_offset;
4902 };
4903
4904 static void
4905 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4906 const struct radv_dispatch_info *info)
4907 {
4908 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4909 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4910 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4911 struct radeon_winsys *ws = cmd_buffer->device->ws;
4912 bool predicating = cmd_buffer->state.predicating;
4913 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4914 struct radv_userdata_info *loc;
4915
4916 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4917 AC_UD_CS_GRID_SIZE);
4918
4919 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4920
4921 if (compute_shader->info.wave_size == 32) {
4922 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
4923 dispatch_initiator |= S_00B800_CS_W32_EN(1);
4924 }
4925
4926 if (info->indirect) {
4927 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4928
4929 va += info->indirect->offset + info->indirect_offset;
4930
4931 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4932
4933 if (loc->sgpr_idx != -1) {
4934 for (unsigned i = 0; i < 3; ++i) {
4935 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4936 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4937 COPY_DATA_DST_SEL(COPY_DATA_REG));
4938 radeon_emit(cs, (va + 4 * i));
4939 radeon_emit(cs, (va + 4 * i) >> 32);
4940 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4941 + loc->sgpr_idx * 4) >> 2) + i);
4942 radeon_emit(cs, 0);
4943 }
4944 }
4945
4946 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4947 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4948 PKT3_SHADER_TYPE_S(1));
4949 radeon_emit(cs, va);
4950 radeon_emit(cs, va >> 32);
4951 radeon_emit(cs, dispatch_initiator);
4952 } else {
4953 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4954 PKT3_SHADER_TYPE_S(1));
4955 radeon_emit(cs, 1);
4956 radeon_emit(cs, va);
4957 radeon_emit(cs, va >> 32);
4958
4959 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4960 PKT3_SHADER_TYPE_S(1));
4961 radeon_emit(cs, 0);
4962 radeon_emit(cs, dispatch_initiator);
4963 }
4964 } else {
4965 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4966 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4967
4968 if (info->unaligned) {
4969 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4970 unsigned remainder[3];
4971
4972 /* If aligned, these should be an entire block size,
4973 * not 0.
4974 */
4975 remainder[0] = blocks[0] + cs_block_size[0] -
4976 align_u32_npot(blocks[0], cs_block_size[0]);
4977 remainder[1] = blocks[1] + cs_block_size[1] -
4978 align_u32_npot(blocks[1], cs_block_size[1]);
4979 remainder[2] = blocks[2] + cs_block_size[2] -
4980 align_u32_npot(blocks[2], cs_block_size[2]);
4981
4982 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4983 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4984 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4985
4986 for(unsigned i = 0; i < 3; ++i) {
4987 assert(offsets[i] % cs_block_size[i] == 0);
4988 offsets[i] /= cs_block_size[i];
4989 }
4990
4991 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4992 radeon_emit(cs,
4993 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4994 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4995 radeon_emit(cs,
4996 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4997 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4998 radeon_emit(cs,
4999 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
5000 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
5001
5002 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
5003 }
5004
5005 if (loc->sgpr_idx != -1) {
5006 assert(loc->num_sgprs == 3);
5007
5008 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
5009 loc->sgpr_idx * 4, 3);
5010 radeon_emit(cs, blocks[0]);
5011 radeon_emit(cs, blocks[1]);
5012 radeon_emit(cs, blocks[2]);
5013 }
5014
5015 if (offsets[0] || offsets[1] || offsets[2]) {
5016 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
5017 radeon_emit(cs, offsets[0]);
5018 radeon_emit(cs, offsets[1]);
5019 radeon_emit(cs, offsets[2]);
5020
5021 /* The blocks in the packet are not counts but end values. */
5022 for (unsigned i = 0; i < 3; ++i)
5023 blocks[i] += offsets[i];
5024 } else {
5025 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
5026 }
5027
5028 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
5029 PKT3_SHADER_TYPE_S(1));
5030 radeon_emit(cs, blocks[0]);
5031 radeon_emit(cs, blocks[1]);
5032 radeon_emit(cs, blocks[2]);
5033 radeon_emit(cs, dispatch_initiator);
5034 }
5035
5036 assert(cmd_buffer->cs->cdw <= cdw_max);
5037 }
5038
5039 static void
5040 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
5041 {
5042 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5043 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5044 }
5045
5046 static void
5047 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
5048 const struct radv_dispatch_info *info)
5049 {
5050 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5051 bool has_prefetch =
5052 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5053 bool pipeline_is_dirty = pipeline &&
5054 pipeline != cmd_buffer->state.emitted_compute_pipeline;
5055
5056 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5057 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5058 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5059 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5060 /* If we have to wait for idle, set all states first, so that
5061 * all SET packets are processed in parallel with previous draw
5062 * calls. Then upload descriptors, set shader pointers, and
5063 * dispatch, and prefetch at the end. This ensures that the
5064 * time the CUs are idle is very short. (there are only SET_SH
5065 * packets between the wait and the draw)
5066 */
5067 radv_emit_compute_pipeline(cmd_buffer);
5068 si_emit_cache_flush(cmd_buffer);
5069 /* <-- CUs are idle here --> */
5070
5071 radv_upload_compute_shader_descriptors(cmd_buffer);
5072
5073 radv_emit_dispatch_packets(cmd_buffer, info);
5074 /* <-- CUs are busy here --> */
5075
5076 /* Start prefetches after the dispatch has been started. Both
5077 * will run in parallel, but starting the dispatch first is
5078 * more important.
5079 */
5080 if (has_prefetch && pipeline_is_dirty) {
5081 radv_emit_shader_prefetch(cmd_buffer,
5082 pipeline->shaders[MESA_SHADER_COMPUTE]);
5083 }
5084 } else {
5085 /* If we don't wait for idle, start prefetches first, then set
5086 * states, and dispatch at the end.
5087 */
5088 si_emit_cache_flush(cmd_buffer);
5089
5090 if (has_prefetch && pipeline_is_dirty) {
5091 radv_emit_shader_prefetch(cmd_buffer,
5092 pipeline->shaders[MESA_SHADER_COMPUTE]);
5093 }
5094
5095 radv_upload_compute_shader_descriptors(cmd_buffer);
5096
5097 radv_emit_compute_pipeline(cmd_buffer);
5098 radv_emit_dispatch_packets(cmd_buffer, info);
5099 }
5100
5101 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5102 }
5103
5104 void radv_CmdDispatchBase(
5105 VkCommandBuffer commandBuffer,
5106 uint32_t base_x,
5107 uint32_t base_y,
5108 uint32_t base_z,
5109 uint32_t x,
5110 uint32_t y,
5111 uint32_t z)
5112 {
5113 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5114 struct radv_dispatch_info info = {};
5115
5116 info.blocks[0] = x;
5117 info.blocks[1] = y;
5118 info.blocks[2] = z;
5119
5120 info.offsets[0] = base_x;
5121 info.offsets[1] = base_y;
5122 info.offsets[2] = base_z;
5123 radv_dispatch(cmd_buffer, &info);
5124 }
5125
5126 void radv_CmdDispatch(
5127 VkCommandBuffer commandBuffer,
5128 uint32_t x,
5129 uint32_t y,
5130 uint32_t z)
5131 {
5132 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5133 }
5134
5135 void radv_CmdDispatchIndirect(
5136 VkCommandBuffer commandBuffer,
5137 VkBuffer _buffer,
5138 VkDeviceSize offset)
5139 {
5140 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5141 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5142 struct radv_dispatch_info info = {};
5143
5144 info.indirect = buffer;
5145 info.indirect_offset = offset;
5146
5147 radv_dispatch(cmd_buffer, &info);
5148 }
5149
5150 void radv_unaligned_dispatch(
5151 struct radv_cmd_buffer *cmd_buffer,
5152 uint32_t x,
5153 uint32_t y,
5154 uint32_t z)
5155 {
5156 struct radv_dispatch_info info = {};
5157
5158 info.blocks[0] = x;
5159 info.blocks[1] = y;
5160 info.blocks[2] = z;
5161 info.unaligned = 1;
5162
5163 radv_dispatch(cmd_buffer, &info);
5164 }
5165
5166 void radv_CmdEndRenderPass(
5167 VkCommandBuffer commandBuffer)
5168 {
5169 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5170
5171 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5172
5173 radv_cmd_buffer_end_subpass(cmd_buffer);
5174
5175 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5176 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5177
5178 cmd_buffer->state.pass = NULL;
5179 cmd_buffer->state.subpass = NULL;
5180 cmd_buffer->state.attachments = NULL;
5181 cmd_buffer->state.framebuffer = NULL;
5182 cmd_buffer->state.subpass_sample_locs = NULL;
5183 }
5184
5185 void radv_CmdEndRenderPass2(
5186 VkCommandBuffer commandBuffer,
5187 const VkSubpassEndInfo* pSubpassEndInfo)
5188 {
5189 radv_CmdEndRenderPass(commandBuffer);
5190 }
5191
5192 /*
5193 * For HTILE we have the following interesting clear words:
5194 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5195 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5196 * 0xfffffff0: Clear depth to 1.0
5197 * 0x00000000: Clear depth to 0.0
5198 */
5199 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5200 struct radv_image *image,
5201 const VkImageSubresourceRange *range)
5202 {
5203 assert(range->baseMipLevel == 0);
5204 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5205 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5206 struct radv_cmd_state *state = &cmd_buffer->state;
5207 uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5208 VkClearDepthStencilValue value = {};
5209
5210 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5211 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5212
5213 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
5214
5215 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5216
5217 if (vk_format_is_stencil(image->vk_format))
5218 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5219
5220 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5221
5222 if (radv_image_is_tc_compat_htile(image)) {
5223 /* Initialize the TC-compat metada value to 0 because by
5224 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5225 * need have to conditionally update its value when performing
5226 * a fast depth clear.
5227 */
5228 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5229 }
5230 }
5231
5232 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5233 struct radv_image *image,
5234 VkImageLayout src_layout,
5235 bool src_render_loop,
5236 VkImageLayout dst_layout,
5237 bool dst_render_loop,
5238 unsigned src_queue_mask,
5239 unsigned dst_queue_mask,
5240 const VkImageSubresourceRange *range,
5241 struct radv_sample_locations_state *sample_locs)
5242 {
5243 if (!radv_image_has_htile(image))
5244 return;
5245
5246 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5247 radv_initialize_htile(cmd_buffer, image, range);
5248 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5249 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5250 radv_initialize_htile(cmd_buffer, image, range);
5251 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5252 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5253 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5254 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5255
5256 radv_decompress_depth_image_inplace(cmd_buffer, image, range,
5257 sample_locs);
5258
5259 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5260 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5261 }
5262 }
5263
5264 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5265 struct radv_image *image,
5266 const VkImageSubresourceRange *range,
5267 uint32_t value)
5268 {
5269 struct radv_cmd_state *state = &cmd_buffer->state;
5270
5271 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5272 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5273
5274 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5275
5276 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5277 }
5278
5279 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5280 struct radv_image *image,
5281 const VkImageSubresourceRange *range)
5282 {
5283 struct radv_cmd_state *state = &cmd_buffer->state;
5284 static const uint32_t fmask_clear_values[4] = {
5285 0x00000000,
5286 0x02020202,
5287 0xE4E4E4E4,
5288 0x76543210
5289 };
5290 uint32_t log2_samples = util_logbase2(image->info.samples);
5291 uint32_t value = fmask_clear_values[log2_samples];
5292
5293 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5294 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5295
5296 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5297
5298 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5299 }
5300
5301 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5302 struct radv_image *image,
5303 const VkImageSubresourceRange *range, uint32_t value)
5304 {
5305 struct radv_cmd_state *state = &cmd_buffer->state;
5306 unsigned size = 0;
5307
5308 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5309 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5310
5311 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5312
5313 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5314 /* When DCC is enabled with mipmaps, some levels might not
5315 * support fast clears and we have to initialize them as "fully
5316 * expanded".
5317 */
5318 /* Compute the size of all fast clearable DCC levels. */
5319 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5320 struct legacy_surf_level *surf_level =
5321 &image->planes[0].surface.u.legacy.level[i];
5322 unsigned dcc_fast_clear_size =
5323 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5324
5325 if (!dcc_fast_clear_size)
5326 break;
5327
5328 size = surf_level->dcc_offset + dcc_fast_clear_size;
5329 }
5330
5331 /* Initialize the mipmap levels without DCC. */
5332 if (size != image->planes[0].surface.dcc_size) {
5333 state->flush_bits |=
5334 radv_fill_buffer(cmd_buffer, image->bo,
5335 image->offset + image->dcc_offset + size,
5336 image->planes[0].surface.dcc_size - size,
5337 0xffffffff);
5338 }
5339 }
5340
5341 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5342 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5343 }
5344
5345 /**
5346 * Initialize DCC/FMASK/CMASK metadata for a color image.
5347 */
5348 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5349 struct radv_image *image,
5350 VkImageLayout src_layout,
5351 bool src_render_loop,
5352 VkImageLayout dst_layout,
5353 bool dst_render_loop,
5354 unsigned src_queue_mask,
5355 unsigned dst_queue_mask,
5356 const VkImageSubresourceRange *range)
5357 {
5358 if (radv_image_has_cmask(image)) {
5359 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5360
5361 /* TODO: clarify this. */
5362 if (radv_image_has_fmask(image)) {
5363 value = 0xccccccccu;
5364 }
5365
5366 radv_initialise_cmask(cmd_buffer, image, range, value);
5367 }
5368
5369 if (radv_image_has_fmask(image)) {
5370 radv_initialize_fmask(cmd_buffer, image, range);
5371 }
5372
5373 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5374 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5375 bool need_decompress_pass = false;
5376
5377 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5378 dst_render_loop,
5379 dst_queue_mask)) {
5380 value = 0x20202020u;
5381 need_decompress_pass = true;
5382 }
5383
5384 radv_initialize_dcc(cmd_buffer, image, range, value);
5385
5386 radv_update_fce_metadata(cmd_buffer, image, range,
5387 need_decompress_pass);
5388 }
5389
5390 if (radv_image_has_cmask(image) ||
5391 radv_dcc_enabled(image, range->baseMipLevel)) {
5392 uint32_t color_values[2] = {};
5393 radv_set_color_clear_metadata(cmd_buffer, image, range,
5394 color_values);
5395 }
5396 }
5397
5398 /**
5399 * Handle color image transitions for DCC/FMASK/CMASK.
5400 */
5401 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5402 struct radv_image *image,
5403 VkImageLayout src_layout,
5404 bool src_render_loop,
5405 VkImageLayout dst_layout,
5406 bool dst_render_loop,
5407 unsigned src_queue_mask,
5408 unsigned dst_queue_mask,
5409 const VkImageSubresourceRange *range)
5410 {
5411 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5412 radv_init_color_image_metadata(cmd_buffer, image,
5413 src_layout, src_render_loop,
5414 dst_layout, dst_render_loop,
5415 src_queue_mask, dst_queue_mask,
5416 range);
5417 return;
5418 }
5419
5420 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5421 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5422 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5423 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5424 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5425 radv_decompress_dcc(cmd_buffer, image, range);
5426 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5427 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5428 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5429 }
5430 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5431 bool fce_eliminate = false, fmask_expand = false;
5432
5433 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5434 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5435 fce_eliminate = true;
5436 }
5437
5438 if (radv_image_has_fmask(image)) {
5439 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5440 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5441 /* A FMASK decompress is required before doing
5442 * a MSAA decompress using FMASK.
5443 */
5444 fmask_expand = true;
5445 }
5446 }
5447
5448 if (fce_eliminate || fmask_expand)
5449 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5450
5451 if (fmask_expand)
5452 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5453 }
5454 }
5455
5456 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5457 struct radv_image *image,
5458 VkImageLayout src_layout,
5459 bool src_render_loop,
5460 VkImageLayout dst_layout,
5461 bool dst_render_loop,
5462 uint32_t src_family,
5463 uint32_t dst_family,
5464 const VkImageSubresourceRange *range,
5465 struct radv_sample_locations_state *sample_locs)
5466 {
5467 if (image->exclusive && src_family != dst_family) {
5468 /* This is an acquire or a release operation and there will be
5469 * a corresponding release/acquire. Do the transition in the
5470 * most flexible queue. */
5471
5472 assert(src_family == cmd_buffer->queue_family_index ||
5473 dst_family == cmd_buffer->queue_family_index);
5474
5475 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5476 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5477 return;
5478
5479 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5480 return;
5481
5482 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5483 (src_family == RADV_QUEUE_GENERAL ||
5484 dst_family == RADV_QUEUE_GENERAL))
5485 return;
5486 }
5487
5488 if (src_layout == dst_layout)
5489 return;
5490
5491 unsigned src_queue_mask =
5492 radv_image_queue_family_mask(image, src_family,
5493 cmd_buffer->queue_family_index);
5494 unsigned dst_queue_mask =
5495 radv_image_queue_family_mask(image, dst_family,
5496 cmd_buffer->queue_family_index);
5497
5498 if (vk_format_is_depth(image->vk_format)) {
5499 radv_handle_depth_image_transition(cmd_buffer, image,
5500 src_layout, src_render_loop,
5501 dst_layout, dst_render_loop,
5502 src_queue_mask, dst_queue_mask,
5503 range, sample_locs);
5504 } else {
5505 radv_handle_color_image_transition(cmd_buffer, image,
5506 src_layout, src_render_loop,
5507 dst_layout, dst_render_loop,
5508 src_queue_mask, dst_queue_mask,
5509 range);
5510 }
5511 }
5512
5513 struct radv_barrier_info {
5514 uint32_t eventCount;
5515 const VkEvent *pEvents;
5516 VkPipelineStageFlags srcStageMask;
5517 VkPipelineStageFlags dstStageMask;
5518 };
5519
5520 static void
5521 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5522 uint32_t memoryBarrierCount,
5523 const VkMemoryBarrier *pMemoryBarriers,
5524 uint32_t bufferMemoryBarrierCount,
5525 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5526 uint32_t imageMemoryBarrierCount,
5527 const VkImageMemoryBarrier *pImageMemoryBarriers,
5528 const struct radv_barrier_info *info)
5529 {
5530 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5531 enum radv_cmd_flush_bits src_flush_bits = 0;
5532 enum radv_cmd_flush_bits dst_flush_bits = 0;
5533
5534 for (unsigned i = 0; i < info->eventCount; ++i) {
5535 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5536 uint64_t va = radv_buffer_get_va(event->bo);
5537
5538 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5539
5540 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5541
5542 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5543 assert(cmd_buffer->cs->cdw <= cdw_max);
5544 }
5545
5546 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5547 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5548 NULL);
5549 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5550 NULL);
5551 }
5552
5553 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5554 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5555 NULL);
5556 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5557 NULL);
5558 }
5559
5560 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5561 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5562
5563 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5564 image);
5565 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5566 image);
5567 }
5568
5569 /* The Vulkan spec 1.1.98 says:
5570 *
5571 * "An execution dependency with only
5572 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5573 * will only prevent that stage from executing in subsequently
5574 * submitted commands. As this stage does not perform any actual
5575 * execution, this is not observable - in effect, it does not delay
5576 * processing of subsequent commands. Similarly an execution dependency
5577 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5578 * will effectively not wait for any prior commands to complete."
5579 */
5580 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5581 radv_stage_flush(cmd_buffer, info->srcStageMask);
5582 cmd_buffer->state.flush_bits |= src_flush_bits;
5583
5584 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5585 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5586
5587 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5588 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5589 SAMPLE_LOCATIONS_INFO_EXT);
5590 struct radv_sample_locations_state sample_locations = {};
5591
5592 if (sample_locs_info) {
5593 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5594 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5595 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5596 sample_locations.count = sample_locs_info->sampleLocationsCount;
5597 typed_memcpy(&sample_locations.locations[0],
5598 sample_locs_info->pSampleLocations,
5599 sample_locs_info->sampleLocationsCount);
5600 }
5601
5602 radv_handle_image_transition(cmd_buffer, image,
5603 pImageMemoryBarriers[i].oldLayout,
5604 false, /* Outside of a renderpass we are never in a renderloop */
5605 pImageMemoryBarriers[i].newLayout,
5606 false, /* Outside of a renderpass we are never in a renderloop */
5607 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5608 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5609 &pImageMemoryBarriers[i].subresourceRange,
5610 sample_locs_info ? &sample_locations : NULL);
5611 }
5612
5613 /* Make sure CP DMA is idle because the driver might have performed a
5614 * DMA operation for copying or filling buffers/images.
5615 */
5616 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5617 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5618 si_cp_dma_wait_for_idle(cmd_buffer);
5619
5620 cmd_buffer->state.flush_bits |= dst_flush_bits;
5621 }
5622
5623 void radv_CmdPipelineBarrier(
5624 VkCommandBuffer commandBuffer,
5625 VkPipelineStageFlags srcStageMask,
5626 VkPipelineStageFlags destStageMask,
5627 VkBool32 byRegion,
5628 uint32_t memoryBarrierCount,
5629 const VkMemoryBarrier* pMemoryBarriers,
5630 uint32_t bufferMemoryBarrierCount,
5631 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5632 uint32_t imageMemoryBarrierCount,
5633 const VkImageMemoryBarrier* pImageMemoryBarriers)
5634 {
5635 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5636 struct radv_barrier_info info;
5637
5638 info.eventCount = 0;
5639 info.pEvents = NULL;
5640 info.srcStageMask = srcStageMask;
5641 info.dstStageMask = destStageMask;
5642
5643 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5644 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5645 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5646 }
5647
5648
5649 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5650 struct radv_event *event,
5651 VkPipelineStageFlags stageMask,
5652 unsigned value)
5653 {
5654 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5655 uint64_t va = radv_buffer_get_va(event->bo);
5656
5657 si_emit_cache_flush(cmd_buffer);
5658
5659 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5660
5661 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5662
5663 /* Flags that only require a top-of-pipe event. */
5664 VkPipelineStageFlags top_of_pipe_flags =
5665 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5666
5667 /* Flags that only require a post-index-fetch event. */
5668 VkPipelineStageFlags post_index_fetch_flags =
5669 top_of_pipe_flags |
5670 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5671 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5672
5673 /* Make sure CP DMA is idle because the driver might have performed a
5674 * DMA operation for copying or filling buffers/images.
5675 */
5676 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5677 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5678 si_cp_dma_wait_for_idle(cmd_buffer);
5679
5680 /* TODO: Emit EOS events for syncing PS/CS stages. */
5681
5682 if (!(stageMask & ~top_of_pipe_flags)) {
5683 /* Just need to sync the PFP engine. */
5684 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5685 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5686 S_370_WR_CONFIRM(1) |
5687 S_370_ENGINE_SEL(V_370_PFP));
5688 radeon_emit(cs, va);
5689 radeon_emit(cs, va >> 32);
5690 radeon_emit(cs, value);
5691 } else if (!(stageMask & ~post_index_fetch_flags)) {
5692 /* Sync ME because PFP reads index and indirect buffers. */
5693 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5694 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5695 S_370_WR_CONFIRM(1) |
5696 S_370_ENGINE_SEL(V_370_ME));
5697 radeon_emit(cs, va);
5698 radeon_emit(cs, va >> 32);
5699 radeon_emit(cs, value);
5700 } else {
5701 /* Otherwise, sync all prior GPU work using an EOP event. */
5702 si_cs_emit_write_event_eop(cs,
5703 cmd_buffer->device->physical_device->rad_info.chip_class,
5704 radv_cmd_buffer_uses_mec(cmd_buffer),
5705 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5706 EOP_DST_SEL_MEM,
5707 EOP_DATA_SEL_VALUE_32BIT, va, value,
5708 cmd_buffer->gfx9_eop_bug_va);
5709 }
5710
5711 assert(cmd_buffer->cs->cdw <= cdw_max);
5712 }
5713
5714 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5715 VkEvent _event,
5716 VkPipelineStageFlags stageMask)
5717 {
5718 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5719 RADV_FROM_HANDLE(radv_event, event, _event);
5720
5721 write_event(cmd_buffer, event, stageMask, 1);
5722 }
5723
5724 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5725 VkEvent _event,
5726 VkPipelineStageFlags stageMask)
5727 {
5728 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5729 RADV_FROM_HANDLE(radv_event, event, _event);
5730
5731 write_event(cmd_buffer, event, stageMask, 0);
5732 }
5733
5734 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5735 uint32_t eventCount,
5736 const VkEvent* pEvents,
5737 VkPipelineStageFlags srcStageMask,
5738 VkPipelineStageFlags dstStageMask,
5739 uint32_t memoryBarrierCount,
5740 const VkMemoryBarrier* pMemoryBarriers,
5741 uint32_t bufferMemoryBarrierCount,
5742 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5743 uint32_t imageMemoryBarrierCount,
5744 const VkImageMemoryBarrier* pImageMemoryBarriers)
5745 {
5746 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5747 struct radv_barrier_info info;
5748
5749 info.eventCount = eventCount;
5750 info.pEvents = pEvents;
5751 info.srcStageMask = 0;
5752
5753 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5754 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5755 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5756 }
5757
5758
5759 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5760 uint32_t deviceMask)
5761 {
5762 /* No-op */
5763 }
5764
5765 /* VK_EXT_conditional_rendering */
5766 void radv_CmdBeginConditionalRenderingEXT(
5767 VkCommandBuffer commandBuffer,
5768 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5769 {
5770 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5771 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5772 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5773 bool draw_visible = true;
5774 uint64_t pred_value = 0;
5775 uint64_t va, new_va;
5776 unsigned pred_offset;
5777
5778 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5779
5780 /* By default, if the 32-bit value at offset in buffer memory is zero,
5781 * then the rendering commands are discarded, otherwise they are
5782 * executed as normal. If the inverted flag is set, all commands are
5783 * discarded if the value is non zero.
5784 */
5785 if (pConditionalRenderingBegin->flags &
5786 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5787 draw_visible = false;
5788 }
5789
5790 si_emit_cache_flush(cmd_buffer);
5791
5792 /* From the Vulkan spec 1.1.107:
5793 *
5794 * "If the 32-bit value at offset in buffer memory is zero, then the
5795 * rendering commands are discarded, otherwise they are executed as
5796 * normal. If the value of the predicate in buffer memory changes while
5797 * conditional rendering is active, the rendering commands may be
5798 * discarded in an implementation-dependent way. Some implementations
5799 * may latch the value of the predicate upon beginning conditional
5800 * rendering while others may read it before every rendering command."
5801 *
5802 * But, the AMD hardware treats the predicate as a 64-bit value which
5803 * means we need a workaround in the driver. Luckily, it's not required
5804 * to support if the value changes when predication is active.
5805 *
5806 * The workaround is as follows:
5807 * 1) allocate a 64-value in the upload BO and initialize it to 0
5808 * 2) copy the 32-bit predicate value to the upload BO
5809 * 3) use the new allocated VA address for predication
5810 *
5811 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5812 * in ME (+ sync PFP) instead of PFP.
5813 */
5814 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5815
5816 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5817
5818 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5819 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5820 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5821 COPY_DATA_WR_CONFIRM);
5822 radeon_emit(cs, va);
5823 radeon_emit(cs, va >> 32);
5824 radeon_emit(cs, new_va);
5825 radeon_emit(cs, new_va >> 32);
5826
5827 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5828 radeon_emit(cs, 0);
5829
5830 /* Enable predication for this command buffer. */
5831 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5832 cmd_buffer->state.predicating = true;
5833
5834 /* Store conditional rendering user info. */
5835 cmd_buffer->state.predication_type = draw_visible;
5836 cmd_buffer->state.predication_va = new_va;
5837 }
5838
5839 void radv_CmdEndConditionalRenderingEXT(
5840 VkCommandBuffer commandBuffer)
5841 {
5842 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5843
5844 /* Disable predication for this command buffer. */
5845 si_emit_set_predication_state(cmd_buffer, false, 0);
5846 cmd_buffer->state.predicating = false;
5847
5848 /* Reset conditional rendering user info. */
5849 cmd_buffer->state.predication_type = -1;
5850 cmd_buffer->state.predication_va = 0;
5851 }
5852
5853 /* VK_EXT_transform_feedback */
5854 void radv_CmdBindTransformFeedbackBuffersEXT(
5855 VkCommandBuffer commandBuffer,
5856 uint32_t firstBinding,
5857 uint32_t bindingCount,
5858 const VkBuffer* pBuffers,
5859 const VkDeviceSize* pOffsets,
5860 const VkDeviceSize* pSizes)
5861 {
5862 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5863 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5864 uint8_t enabled_mask = 0;
5865
5866 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5867 for (uint32_t i = 0; i < bindingCount; i++) {
5868 uint32_t idx = firstBinding + i;
5869
5870 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5871 sb[idx].offset = pOffsets[i];
5872 sb[idx].size = pSizes[i];
5873
5874 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5875 sb[idx].buffer->bo);
5876
5877 enabled_mask |= 1 << idx;
5878 }
5879
5880 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5881
5882 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5883 }
5884
5885 static void
5886 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5887 {
5888 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5889 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5890
5891 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5892 radeon_emit(cs,
5893 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5894 S_028B94_RAST_STREAM(0) |
5895 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5896 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5897 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5898 radeon_emit(cs, so->hw_enabled_mask &
5899 so->enabled_stream_buffers_mask);
5900
5901 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5902 }
5903
5904 static void
5905 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5906 {
5907 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5908 bool old_streamout_enabled = so->streamout_enabled;
5909 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5910
5911 so->streamout_enabled = enable;
5912
5913 so->hw_enabled_mask = so->enabled_mask |
5914 (so->enabled_mask << 4) |
5915 (so->enabled_mask << 8) |
5916 (so->enabled_mask << 12);
5917
5918 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
5919 ((old_streamout_enabled != so->streamout_enabled) ||
5920 (old_hw_enabled_mask != so->hw_enabled_mask)))
5921 radv_emit_streamout_enable(cmd_buffer);
5922
5923 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
5924 cmd_buffer->gds_needed = true;
5925 cmd_buffer->gds_oa_needed = true;
5926 }
5927 }
5928
5929 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5930 {
5931 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5932 unsigned reg_strmout_cntl;
5933
5934 /* The register is at different places on different ASICs. */
5935 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5936 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5937 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5938 } else {
5939 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5940 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5941 }
5942
5943 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5944 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5945
5946 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5947 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5948 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5949 radeon_emit(cs, 0);
5950 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5951 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5952 radeon_emit(cs, 4); /* poll interval */
5953 }
5954
5955 static void
5956 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5957 uint32_t firstCounterBuffer,
5958 uint32_t counterBufferCount,
5959 const VkBuffer *pCounterBuffers,
5960 const VkDeviceSize *pCounterBufferOffsets)
5961
5962 {
5963 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5964 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5965 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5966 uint32_t i;
5967
5968 radv_flush_vgt_streamout(cmd_buffer);
5969
5970 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5971 for_each_bit(i, so->enabled_mask) {
5972 int32_t counter_buffer_idx = i - firstCounterBuffer;
5973 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5974 counter_buffer_idx = -1;
5975
5976 /* AMD GCN binds streamout buffers as shader resources.
5977 * VGT only counts primitives and tells the shader through
5978 * SGPRs what to do.
5979 */
5980 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5981 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5982 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5983
5984 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5985
5986 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5987 /* The array of counter buffers is optional. */
5988 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5989 uint64_t va = radv_buffer_get_va(buffer->bo);
5990
5991 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5992
5993 /* Append */
5994 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5995 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5996 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5997 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5998 radeon_emit(cs, 0); /* unused */
5999 radeon_emit(cs, 0); /* unused */
6000 radeon_emit(cs, va); /* src address lo */
6001 radeon_emit(cs, va >> 32); /* src address hi */
6002
6003 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6004 } else {
6005 /* Start from the beginning. */
6006 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6007 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6008 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6009 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
6010 radeon_emit(cs, 0); /* unused */
6011 radeon_emit(cs, 0); /* unused */
6012 radeon_emit(cs, 0); /* unused */
6013 radeon_emit(cs, 0); /* unused */
6014 }
6015 }
6016
6017 radv_set_streamout_enable(cmd_buffer, true);
6018 }
6019
6020 static void
6021 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6022 uint32_t firstCounterBuffer,
6023 uint32_t counterBufferCount,
6024 const VkBuffer *pCounterBuffers,
6025 const VkDeviceSize *pCounterBufferOffsets)
6026 {
6027 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6028 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
6029 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6030 uint32_t i;
6031
6032 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6033 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6034
6035 /* Sync because the next streamout operation will overwrite GDS and we
6036 * have to make sure it's idle.
6037 * TODO: Improve by tracking if there is a streamout operation in
6038 * flight.
6039 */
6040 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
6041 si_emit_cache_flush(cmd_buffer);
6042
6043 for_each_bit(i, so->enabled_mask) {
6044 int32_t counter_buffer_idx = i - firstCounterBuffer;
6045 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6046 counter_buffer_idx = -1;
6047
6048 bool append = counter_buffer_idx >= 0 &&
6049 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
6050 uint64_t va = 0;
6051
6052 if (append) {
6053 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6054
6055 va += radv_buffer_get_va(buffer->bo);
6056 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6057
6058 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6059 }
6060
6061 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6062 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6063 S_411_DST_SEL(V_411_GDS) |
6064 S_411_CP_SYNC(i == last_target));
6065 radeon_emit(cs, va);
6066 radeon_emit(cs, va >> 32);
6067 radeon_emit(cs, 4 * i); /* destination in GDS */
6068 radeon_emit(cs, 0);
6069 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6070 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6071 }
6072
6073 radv_set_streamout_enable(cmd_buffer, true);
6074 }
6075
6076 void radv_CmdBeginTransformFeedbackEXT(
6077 VkCommandBuffer commandBuffer,
6078 uint32_t firstCounterBuffer,
6079 uint32_t counterBufferCount,
6080 const VkBuffer* pCounterBuffers,
6081 const VkDeviceSize* pCounterBufferOffsets)
6082 {
6083 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6084
6085 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6086 gfx10_emit_streamout_begin(cmd_buffer,
6087 firstCounterBuffer, counterBufferCount,
6088 pCounterBuffers, pCounterBufferOffsets);
6089 } else {
6090 radv_emit_streamout_begin(cmd_buffer,
6091 firstCounterBuffer, counterBufferCount,
6092 pCounterBuffers, pCounterBufferOffsets);
6093 }
6094 }
6095
6096 static void
6097 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6098 uint32_t firstCounterBuffer,
6099 uint32_t counterBufferCount,
6100 const VkBuffer *pCounterBuffers,
6101 const VkDeviceSize *pCounterBufferOffsets)
6102 {
6103 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6104 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6105 uint32_t i;
6106
6107 radv_flush_vgt_streamout(cmd_buffer);
6108
6109 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6110 for_each_bit(i, so->enabled_mask) {
6111 int32_t counter_buffer_idx = i - firstCounterBuffer;
6112 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6113 counter_buffer_idx = -1;
6114
6115 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6116 /* The array of counters buffer is optional. */
6117 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6118 uint64_t va = radv_buffer_get_va(buffer->bo);
6119
6120 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6121
6122 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6123 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6124 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6125 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6126 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6127 radeon_emit(cs, va); /* dst address lo */
6128 radeon_emit(cs, va >> 32); /* dst address hi */
6129 radeon_emit(cs, 0); /* unused */
6130 radeon_emit(cs, 0); /* unused */
6131
6132 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6133 }
6134
6135 /* Deactivate transform feedback by zeroing the buffer size.
6136 * The counters (primitives generated, primitives emitted) may
6137 * be enabled even if there is not buffer bound. This ensures
6138 * that the primitives-emitted query won't increment.
6139 */
6140 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6141
6142 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6143 }
6144
6145 radv_set_streamout_enable(cmd_buffer, false);
6146 }
6147
6148 static void
6149 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6150 uint32_t firstCounterBuffer,
6151 uint32_t counterBufferCount,
6152 const VkBuffer *pCounterBuffers,
6153 const VkDeviceSize *pCounterBufferOffsets)
6154 {
6155 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6156 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6157 uint32_t i;
6158
6159 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6160 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6161
6162 for_each_bit(i, so->enabled_mask) {
6163 int32_t counter_buffer_idx = i - firstCounterBuffer;
6164 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6165 counter_buffer_idx = -1;
6166
6167 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6168 /* The array of counters buffer is optional. */
6169 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6170 uint64_t va = radv_buffer_get_va(buffer->bo);
6171
6172 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6173
6174 si_cs_emit_write_event_eop(cs,
6175 cmd_buffer->device->physical_device->rad_info.chip_class,
6176 radv_cmd_buffer_uses_mec(cmd_buffer),
6177 V_028A90_PS_DONE, 0,
6178 EOP_DST_SEL_TC_L2,
6179 EOP_DATA_SEL_GDS,
6180 va, EOP_DATA_GDS(i, 1), 0);
6181
6182 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6183 }
6184 }
6185
6186 radv_set_streamout_enable(cmd_buffer, false);
6187 }
6188
6189 void radv_CmdEndTransformFeedbackEXT(
6190 VkCommandBuffer commandBuffer,
6191 uint32_t firstCounterBuffer,
6192 uint32_t counterBufferCount,
6193 const VkBuffer* pCounterBuffers,
6194 const VkDeviceSize* pCounterBufferOffsets)
6195 {
6196 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6197
6198 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6199 gfx10_emit_streamout_end(cmd_buffer,
6200 firstCounterBuffer, counterBufferCount,
6201 pCounterBuffers, pCounterBufferOffsets);
6202 } else {
6203 radv_emit_streamout_end(cmd_buffer,
6204 firstCounterBuffer, counterBufferCount,
6205 pCounterBuffers, pCounterBufferOffsets);
6206 }
6207 }
6208
6209 void radv_CmdDrawIndirectByteCountEXT(
6210 VkCommandBuffer commandBuffer,
6211 uint32_t instanceCount,
6212 uint32_t firstInstance,
6213 VkBuffer _counterBuffer,
6214 VkDeviceSize counterBufferOffset,
6215 uint32_t counterOffset,
6216 uint32_t vertexStride)
6217 {
6218 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6219 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6220 struct radv_draw_info info = {};
6221
6222 info.instance_count = instanceCount;
6223 info.first_instance = firstInstance;
6224 info.strmout_buffer = counterBuffer;
6225 info.strmout_buffer_offset = counterBufferOffset;
6226 info.stride = vertexStride;
6227
6228 radv_draw(cmd_buffer, &info);
6229 }
6230
6231 /* VK_AMD_buffer_marker */
6232 void radv_CmdWriteBufferMarkerAMD(
6233 VkCommandBuffer commandBuffer,
6234 VkPipelineStageFlagBits pipelineStage,
6235 VkBuffer dstBuffer,
6236 VkDeviceSize dstOffset,
6237 uint32_t marker)
6238 {
6239 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6240 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6241 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6242 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6243
6244 si_emit_cache_flush(cmd_buffer);
6245
6246 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6247
6248 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6249 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6250 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6251 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6252 COPY_DATA_WR_CONFIRM);
6253 radeon_emit(cs, marker);
6254 radeon_emit(cs, 0);
6255 radeon_emit(cs, va);
6256 radeon_emit(cs, va >> 32);
6257 } else {
6258 si_cs_emit_write_event_eop(cs,
6259 cmd_buffer->device->physical_device->rad_info.chip_class,
6260 radv_cmd_buffer_uses_mec(cmd_buffer),
6261 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6262 EOP_DST_SEL_MEM,
6263 EOP_DATA_SEL_VALUE_32BIT,
6264 va, marker,
6265 cmd_buffer->gfx9_eop_bug_va);
6266 }
6267
6268 assert(cmd_buffer->cs->cdw <= cdw_max);
6269 }