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radv: Add multiple planes to images.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range);
61
62 const struct radv_dynamic_state default_dynamic_state = {
63 .viewport = {
64 .count = 0,
65 },
66 .scissor = {
67 .count = 0,
68 },
69 .line_width = 1.0f,
70 .depth_bias = {
71 .bias = 0.0f,
72 .clamp = 0.0f,
73 .slope = 0.0f,
74 },
75 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
76 .depth_bounds = {
77 .min = 0.0f,
78 .max = 1.0f,
79 },
80 .stencil_compare_mask = {
81 .front = ~0u,
82 .back = ~0u,
83 },
84 .stencil_write_mask = {
85 .front = ~0u,
86 .back = ~0u,
87 },
88 .stencil_reference = {
89 .front = 0u,
90 .back = 0u,
91 },
92 };
93
94 static void
95 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
96 const struct radv_dynamic_state *src)
97 {
98 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
99 uint32_t copy_mask = src->mask;
100 uint32_t dest_mask = 0;
101
102 /* Make sure to copy the number of viewports/scissors because they can
103 * only be specified at pipeline creation time.
104 */
105 dest->viewport.count = src->viewport.count;
106 dest->scissor.count = src->scissor.count;
107 dest->discard_rectangle.count = src->discard_rectangle.count;
108
109 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
110 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
111 src->viewport.count * sizeof(VkViewport))) {
112 typed_memcpy(dest->viewport.viewports,
113 src->viewport.viewports,
114 src->viewport.count);
115 dest_mask |= RADV_DYNAMIC_VIEWPORT;
116 }
117 }
118
119 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
120 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
121 src->scissor.count * sizeof(VkRect2D))) {
122 typed_memcpy(dest->scissor.scissors,
123 src->scissor.scissors, src->scissor.count);
124 dest_mask |= RADV_DYNAMIC_SCISSOR;
125 }
126 }
127
128 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
129 if (dest->line_width != src->line_width) {
130 dest->line_width = src->line_width;
131 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
132 }
133 }
134
135 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
136 if (memcmp(&dest->depth_bias, &src->depth_bias,
137 sizeof(src->depth_bias))) {
138 dest->depth_bias = src->depth_bias;
139 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
144 if (memcmp(&dest->blend_constants, &src->blend_constants,
145 sizeof(src->blend_constants))) {
146 typed_memcpy(dest->blend_constants,
147 src->blend_constants, 4);
148 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
149 }
150 }
151
152 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
153 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
154 sizeof(src->depth_bounds))) {
155 dest->depth_bounds = src->depth_bounds;
156 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
161 if (memcmp(&dest->stencil_compare_mask,
162 &src->stencil_compare_mask,
163 sizeof(src->stencil_compare_mask))) {
164 dest->stencil_compare_mask = src->stencil_compare_mask;
165 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
166 }
167 }
168
169 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
170 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
171 sizeof(src->stencil_write_mask))) {
172 dest->stencil_write_mask = src->stencil_write_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
178 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
179 sizeof(src->stencil_reference))) {
180 dest->stencil_reference = src->stencil_reference;
181 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
186 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
187 src->discard_rectangle.count * sizeof(VkRect2D))) {
188 typed_memcpy(dest->discard_rectangle.rectangles,
189 src->discard_rectangle.rectangles,
190 src->discard_rectangle.count);
191 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
192 }
193 }
194
195 cmd_buffer->state.dirty |= dest_mask;
196 }
197
198 static void
199 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
200 struct radv_pipeline *pipeline)
201 {
202 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
203 struct radv_shader_info *info;
204
205 if (!pipeline->streamout_shader)
206 return;
207
208 info = &pipeline->streamout_shader->info.info;
209 for (int i = 0; i < MAX_SO_BUFFERS; i++)
210 so->stride_in_dw[i] = info->so.strides[i];
211
212 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
213 }
214
215 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
216 {
217 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
218 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
219 }
220
221 enum ring_type radv_queue_family_to_ring(int f) {
222 switch (f) {
223 case RADV_QUEUE_GENERAL:
224 return RING_GFX;
225 case RADV_QUEUE_COMPUTE:
226 return RING_COMPUTE;
227 case RADV_QUEUE_TRANSFER:
228 return RING_DMA;
229 default:
230 unreachable("Unknown queue family");
231 }
232 }
233
234 static VkResult radv_create_cmd_buffer(
235 struct radv_device * device,
236 struct radv_cmd_pool * pool,
237 VkCommandBufferLevel level,
238 VkCommandBuffer* pCommandBuffer)
239 {
240 struct radv_cmd_buffer *cmd_buffer;
241 unsigned ring;
242 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
243 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
244 if (cmd_buffer == NULL)
245 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
246
247 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
248 cmd_buffer->device = device;
249 cmd_buffer->pool = pool;
250 cmd_buffer->level = level;
251
252 if (pool) {
253 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
254 cmd_buffer->queue_family_index = pool->queue_family_index;
255
256 } else {
257 /* Init the pool_link so we can safely call list_del when we destroy
258 * the command buffer
259 */
260 list_inithead(&cmd_buffer->pool_link);
261 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
262 }
263
264 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
265
266 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
267 if (!cmd_buffer->cs) {
268 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
269 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
270 }
271
272 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
273
274 list_inithead(&cmd_buffer->upload.list);
275
276 return VK_SUCCESS;
277 }
278
279 static void
280 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
281 {
282 list_del(&cmd_buffer->pool_link);
283
284 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
285 &cmd_buffer->upload.list, list) {
286 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
287 list_del(&up->list);
288 free(up);
289 }
290
291 if (cmd_buffer->upload.upload_bo)
292 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
293 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
294
295 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
296 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
297
298 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
299 }
300
301 static VkResult
302 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
303 {
304
305 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
306
307 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
308 &cmd_buffer->upload.list, list) {
309 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
310 list_del(&up->list);
311 free(up);
312 }
313
314 cmd_buffer->push_constant_stages = 0;
315 cmd_buffer->scratch_size_needed = 0;
316 cmd_buffer->compute_scratch_size_needed = 0;
317 cmd_buffer->esgs_ring_size_needed = 0;
318 cmd_buffer->gsvs_ring_size_needed = 0;
319 cmd_buffer->tess_rings_needed = false;
320 cmd_buffer->sample_positions_needed = false;
321
322 if (cmd_buffer->upload.upload_bo)
323 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
324 cmd_buffer->upload.upload_bo);
325 cmd_buffer->upload.offset = 0;
326
327 cmd_buffer->record_result = VK_SUCCESS;
328
329 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
330 cmd_buffer->descriptors[i].dirty = 0;
331 cmd_buffer->descriptors[i].valid = 0;
332 cmd_buffer->descriptors[i].push_dirty = false;
333 }
334
335 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
336 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
337 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
338 unsigned fence_offset, eop_bug_offset;
339 void *fence_ptr;
340
341 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
342 &fence_ptr);
343
344 cmd_buffer->gfx9_fence_va =
345 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
346 cmd_buffer->gfx9_fence_va += fence_offset;
347
348 /* Allocate a buffer for the EOP bug on GFX9. */
349 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
350 &eop_bug_offset, &fence_ptr);
351 cmd_buffer->gfx9_eop_bug_va =
352 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
353 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
354 }
355
356 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
357
358 return cmd_buffer->record_result;
359 }
360
361 static bool
362 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
363 uint64_t min_needed)
364 {
365 uint64_t new_size;
366 struct radeon_winsys_bo *bo;
367 struct radv_cmd_buffer_upload *upload;
368 struct radv_device *device = cmd_buffer->device;
369
370 new_size = MAX2(min_needed, 16 * 1024);
371 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
372
373 bo = device->ws->buffer_create(device->ws,
374 new_size, 4096,
375 RADEON_DOMAIN_GTT,
376 RADEON_FLAG_CPU_ACCESS|
377 RADEON_FLAG_NO_INTERPROCESS_SHARING |
378 RADEON_FLAG_32BIT,
379 RADV_BO_PRIORITY_UPLOAD_BUFFER);
380
381 if (!bo) {
382 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
383 return false;
384 }
385
386 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
387 if (cmd_buffer->upload.upload_bo) {
388 upload = malloc(sizeof(*upload));
389
390 if (!upload) {
391 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
392 device->ws->buffer_destroy(bo);
393 return false;
394 }
395
396 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
397 list_add(&upload->list, &cmd_buffer->upload.list);
398 }
399
400 cmd_buffer->upload.upload_bo = bo;
401 cmd_buffer->upload.size = new_size;
402 cmd_buffer->upload.offset = 0;
403 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
404
405 if (!cmd_buffer->upload.map) {
406 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
407 return false;
408 }
409
410 return true;
411 }
412
413 bool
414 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
415 unsigned size,
416 unsigned alignment,
417 unsigned *out_offset,
418 void **ptr)
419 {
420 assert(util_is_power_of_two_nonzero(alignment));
421
422 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
423 if (offset + size > cmd_buffer->upload.size) {
424 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
425 return false;
426 offset = 0;
427 }
428
429 *out_offset = offset;
430 *ptr = cmd_buffer->upload.map + offset;
431
432 cmd_buffer->upload.offset = offset + size;
433 return true;
434 }
435
436 bool
437 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
438 unsigned size, unsigned alignment,
439 const void *data, unsigned *out_offset)
440 {
441 uint8_t *ptr;
442
443 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
444 out_offset, (void **)&ptr))
445 return false;
446
447 if (ptr)
448 memcpy(ptr, data, size);
449
450 return true;
451 }
452
453 static void
454 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
455 unsigned count, const uint32_t *data)
456 {
457 struct radeon_cmdbuf *cs = cmd_buffer->cs;
458
459 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
460
461 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
462 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
463 S_370_WR_CONFIRM(1) |
464 S_370_ENGINE_SEL(V_370_ME));
465 radeon_emit(cs, va);
466 radeon_emit(cs, va >> 32);
467 radeon_emit_array(cs, data, count);
468 }
469
470 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
471 {
472 struct radv_device *device = cmd_buffer->device;
473 struct radeon_cmdbuf *cs = cmd_buffer->cs;
474 uint64_t va;
475
476 va = radv_buffer_get_va(device->trace_bo);
477 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
478 va += 4;
479
480 ++cmd_buffer->state.trace_id;
481 radv_emit_write_data_packet(cmd_buffer, va, 1,
482 &cmd_buffer->state.trace_id);
483
484 radeon_check_space(cmd_buffer->device->ws, cs, 2);
485
486 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
487 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
488 }
489
490 static void
491 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
492 enum radv_cmd_flush_bits flags)
493 {
494 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
495 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
496 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
497
498 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
499
500 /* Force wait for graphics or compute engines to be idle. */
501 si_cs_emit_cache_flush(cmd_buffer->cs,
502 cmd_buffer->device->physical_device->rad_info.chip_class,
503 &cmd_buffer->gfx9_fence_idx,
504 cmd_buffer->gfx9_fence_va,
505 radv_cmd_buffer_uses_mec(cmd_buffer),
506 flags, cmd_buffer->gfx9_eop_bug_va);
507 }
508
509 if (unlikely(cmd_buffer->device->trace_bo))
510 radv_cmd_buffer_trace_emit(cmd_buffer);
511 }
512
513 static void
514 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
515 struct radv_pipeline *pipeline, enum ring_type ring)
516 {
517 struct radv_device *device = cmd_buffer->device;
518 uint32_t data[2];
519 uint64_t va;
520
521 va = radv_buffer_get_va(device->trace_bo);
522
523 switch (ring) {
524 case RING_GFX:
525 va += 8;
526 break;
527 case RING_COMPUTE:
528 va += 16;
529 break;
530 default:
531 assert(!"invalid ring type");
532 }
533
534 data[0] = (uintptr_t)pipeline;
535 data[1] = (uintptr_t)pipeline >> 32;
536
537 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
538 }
539
540 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
541 VkPipelineBindPoint bind_point,
542 struct radv_descriptor_set *set,
543 unsigned idx)
544 {
545 struct radv_descriptor_state *descriptors_state =
546 radv_get_descriptors_state(cmd_buffer, bind_point);
547
548 descriptors_state->sets[idx] = set;
549
550 descriptors_state->valid |= (1u << idx); /* active descriptors */
551 descriptors_state->dirty |= (1u << idx);
552 }
553
554 static void
555 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
556 VkPipelineBindPoint bind_point)
557 {
558 struct radv_descriptor_state *descriptors_state =
559 radv_get_descriptors_state(cmd_buffer, bind_point);
560 struct radv_device *device = cmd_buffer->device;
561 uint32_t data[MAX_SETS * 2] = {};
562 uint64_t va;
563 unsigned i;
564 va = radv_buffer_get_va(device->trace_bo) + 24;
565
566 for_each_bit(i, descriptors_state->valid) {
567 struct radv_descriptor_set *set = descriptors_state->sets[i];
568 data[i * 2] = (uintptr_t)set;
569 data[i * 2 + 1] = (uintptr_t)set >> 32;
570 }
571
572 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
573 }
574
575 struct radv_userdata_info *
576 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
577 gl_shader_stage stage,
578 int idx)
579 {
580 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
581 return &shader->info.user_sgprs_locs.shader_data[idx];
582 }
583
584 static void
585 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
586 struct radv_pipeline *pipeline,
587 gl_shader_stage stage,
588 int idx, uint64_t va)
589 {
590 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
591 uint32_t base_reg = pipeline->user_data_0[stage];
592 if (loc->sgpr_idx == -1)
593 return;
594
595 assert(loc->num_sgprs == 1);
596
597 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
598 base_reg + loc->sgpr_idx * 4, va, false);
599 }
600
601 static void
602 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
603 struct radv_pipeline *pipeline,
604 struct radv_descriptor_state *descriptors_state,
605 gl_shader_stage stage)
606 {
607 struct radv_device *device = cmd_buffer->device;
608 struct radeon_cmdbuf *cs = cmd_buffer->cs;
609 uint32_t sh_base = pipeline->user_data_0[stage];
610 struct radv_userdata_locations *locs =
611 &pipeline->shaders[stage]->info.user_sgprs_locs;
612 unsigned mask = locs->descriptor_sets_enabled;
613
614 mask &= descriptors_state->dirty & descriptors_state->valid;
615
616 while (mask) {
617 int start, count;
618
619 u_bit_scan_consecutive_range(&mask, &start, &count);
620
621 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
622 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
623
624 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
625 for (int i = 0; i < count; i++) {
626 struct radv_descriptor_set *set =
627 descriptors_state->sets[start + i];
628
629 radv_emit_shader_pointer_body(device, cs, set->va, true);
630 }
631 }
632 }
633
634 static void
635 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
636 struct radv_pipeline *pipeline,
637 gl_shader_stage stage,
638 int idx, int count, uint32_t *values)
639 {
640 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
641 uint32_t base_reg = pipeline->user_data_0[stage];
642 if (loc->sgpr_idx == -1)
643 return;
644
645 assert(loc->num_sgprs == count);
646
647 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
648 radeon_emit_array(cmd_buffer->cs, values, count);
649 }
650
651 static void
652 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
653 struct radv_pipeline *pipeline)
654 {
655 int num_samples = pipeline->graphics.ms.num_samples;
656 struct radv_multisample_state *ms = &pipeline->graphics.ms;
657 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
658
659 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
660 cmd_buffer->sample_positions_needed = true;
661
662 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
663 return;
664
665 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
666 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
667 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
668
669 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
670
671 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
672
673 /* GFX9: Flush DFSM when the AA mode changes. */
674 if (cmd_buffer->device->dfsm_allowed) {
675 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
676 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
677 }
678
679 cmd_buffer->state.context_roll_without_scissor_emitted = true;
680 }
681
682 static void
683 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
684 struct radv_shader_variant *shader)
685 {
686 uint64_t va;
687
688 if (!shader)
689 return;
690
691 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
692
693 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
694 }
695
696 static void
697 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
698 struct radv_pipeline *pipeline,
699 bool vertex_stage_only)
700 {
701 struct radv_cmd_state *state = &cmd_buffer->state;
702 uint32_t mask = state->prefetch_L2_mask;
703
704 if (vertex_stage_only) {
705 /* Fast prefetch path for starting draws as soon as possible.
706 */
707 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
708 RADV_PREFETCH_VBO_DESCRIPTORS);
709 }
710
711 if (mask & RADV_PREFETCH_VS)
712 radv_emit_shader_prefetch(cmd_buffer,
713 pipeline->shaders[MESA_SHADER_VERTEX]);
714
715 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
716 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
717
718 if (mask & RADV_PREFETCH_TCS)
719 radv_emit_shader_prefetch(cmd_buffer,
720 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
721
722 if (mask & RADV_PREFETCH_TES)
723 radv_emit_shader_prefetch(cmd_buffer,
724 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
725
726 if (mask & RADV_PREFETCH_GS) {
727 radv_emit_shader_prefetch(cmd_buffer,
728 pipeline->shaders[MESA_SHADER_GEOMETRY]);
729 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
730 }
731
732 if (mask & RADV_PREFETCH_PS)
733 radv_emit_shader_prefetch(cmd_buffer,
734 pipeline->shaders[MESA_SHADER_FRAGMENT]);
735
736 state->prefetch_L2_mask &= ~mask;
737 }
738
739 static void
740 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
741 {
742 if (!cmd_buffer->device->physical_device->rbplus_allowed)
743 return;
744
745 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
746 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
747 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
748
749 unsigned sx_ps_downconvert = 0;
750 unsigned sx_blend_opt_epsilon = 0;
751 unsigned sx_blend_opt_control = 0;
752
753 for (unsigned i = 0; i < subpass->color_count; ++i) {
754 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
755 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
756 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
757 continue;
758 }
759
760 int idx = subpass->color_attachments[i].attachment;
761 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
762
763 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
764 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
765 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
766 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
767
768 bool has_alpha, has_rgb;
769
770 /* Set if RGB and A are present. */
771 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
772
773 if (format == V_028C70_COLOR_8 ||
774 format == V_028C70_COLOR_16 ||
775 format == V_028C70_COLOR_32)
776 has_rgb = !has_alpha;
777 else
778 has_rgb = true;
779
780 /* Check the colormask and export format. */
781 if (!(colormask & 0x7))
782 has_rgb = false;
783 if (!(colormask & 0x8))
784 has_alpha = false;
785
786 if (spi_format == V_028714_SPI_SHADER_ZERO) {
787 has_rgb = false;
788 has_alpha = false;
789 }
790
791 /* Disable value checking for disabled channels. */
792 if (!has_rgb)
793 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
794 if (!has_alpha)
795 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
796
797 /* Enable down-conversion for 32bpp and smaller formats. */
798 switch (format) {
799 case V_028C70_COLOR_8:
800 case V_028C70_COLOR_8_8:
801 case V_028C70_COLOR_8_8_8_8:
802 /* For 1 and 2-channel formats, use the superset thereof. */
803 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
804 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
805 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
806 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
807 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
808 }
809 break;
810
811 case V_028C70_COLOR_5_6_5:
812 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
813 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
814 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
815 }
816 break;
817
818 case V_028C70_COLOR_1_5_5_5:
819 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
820 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
821 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
822 }
823 break;
824
825 case V_028C70_COLOR_4_4_4_4:
826 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
827 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
828 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
829 }
830 break;
831
832 case V_028C70_COLOR_32:
833 if (swap == V_028C70_SWAP_STD &&
834 spi_format == V_028714_SPI_SHADER_32_R)
835 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
836 else if (swap == V_028C70_SWAP_ALT_REV &&
837 spi_format == V_028714_SPI_SHADER_32_AR)
838 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
839 break;
840
841 case V_028C70_COLOR_16:
842 case V_028C70_COLOR_16_16:
843 /* For 1-channel formats, use the superset thereof. */
844 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
845 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
846 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
847 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
848 if (swap == V_028C70_SWAP_STD ||
849 swap == V_028C70_SWAP_STD_REV)
850 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
851 else
852 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
853 }
854 break;
855
856 case V_028C70_COLOR_10_11_11:
857 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
858 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
859 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
860 }
861 break;
862
863 case V_028C70_COLOR_2_10_10_10:
864 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
865 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
866 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
867 }
868 break;
869 }
870 }
871
872 for (unsigned i = subpass->color_count; i < 8; ++i) {
873 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
874 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
875 }
876 /* TODO: avoid redundantly setting context registers */
877 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
878 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
879 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
880 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
881
882 cmd_buffer->state.context_roll_without_scissor_emitted = true;
883 }
884
885 static void
886 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
887 {
888 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
889
890 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
891 return;
892
893 radv_update_multisample_state(cmd_buffer, pipeline);
894
895 cmd_buffer->scratch_size_needed =
896 MAX2(cmd_buffer->scratch_size_needed,
897 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
898
899 if (!cmd_buffer->state.emitted_pipeline ||
900 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
901 pipeline->graphics.can_use_guardband)
902 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
903
904 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
905
906 if (!cmd_buffer->state.emitted_pipeline ||
907 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
908 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
909 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
910 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
911 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
912 cmd_buffer->state.context_roll_without_scissor_emitted = true;
913 }
914
915 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
916 if (!pipeline->shaders[i])
917 continue;
918
919 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
920 pipeline->shaders[i]->bo);
921 }
922
923 if (radv_pipeline_has_gs(pipeline))
924 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
925 pipeline->gs_copy_shader->bo);
926
927 if (unlikely(cmd_buffer->device->trace_bo))
928 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
929
930 cmd_buffer->state.emitted_pipeline = pipeline;
931
932 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
933 }
934
935 static void
936 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
937 {
938 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
939 cmd_buffer->state.dynamic.viewport.viewports);
940 }
941
942 static void
943 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
944 {
945 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
946
947 si_write_scissors(cmd_buffer->cs, 0, count,
948 cmd_buffer->state.dynamic.scissor.scissors,
949 cmd_buffer->state.dynamic.viewport.viewports,
950 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
951
952 cmd_buffer->state.context_roll_without_scissor_emitted = false;
953 }
954
955 static void
956 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
957 {
958 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
959 return;
960
961 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
962 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
963 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
964 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
965 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
966 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
967 S_028214_BR_Y(rect.offset.y + rect.extent.height));
968 }
969 }
970
971 static void
972 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
973 {
974 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
975
976 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
977 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
978 }
979
980 static void
981 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
982 {
983 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
984
985 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
986 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
987 }
988
989 static void
990 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
991 {
992 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
993
994 radeon_set_context_reg_seq(cmd_buffer->cs,
995 R_028430_DB_STENCILREFMASK, 2);
996 radeon_emit(cmd_buffer->cs,
997 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
998 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
999 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1000 S_028430_STENCILOPVAL(1));
1001 radeon_emit(cmd_buffer->cs,
1002 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1003 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1004 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1005 S_028434_STENCILOPVAL_BF(1));
1006 }
1007
1008 static void
1009 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1010 {
1011 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1012
1013 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1014 fui(d->depth_bounds.min));
1015 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1016 fui(d->depth_bounds.max));
1017 }
1018
1019 static void
1020 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1021 {
1022 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1023 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1024 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1025
1026
1027 radeon_set_context_reg_seq(cmd_buffer->cs,
1028 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1029 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1030 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1031 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1032 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1033 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1034 }
1035
1036 static void
1037 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1038 int index,
1039 struct radv_attachment_info *att,
1040 struct radv_image *image,
1041 VkImageLayout layout)
1042 {
1043 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1044 struct radv_color_buffer_info *cb = &att->cb;
1045 uint32_t cb_color_info = cb->cb_color_info;
1046
1047 if (!radv_layout_dcc_compressed(image, layout,
1048 radv_image_queue_family_mask(image,
1049 cmd_buffer->queue_family_index,
1050 cmd_buffer->queue_family_index))) {
1051 cb_color_info &= C_028C70_DCC_ENABLE;
1052 }
1053
1054 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1055 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1056 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1057 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1058 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1059 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1060 radeon_emit(cmd_buffer->cs, cb_color_info);
1061 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1062 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1063 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1064 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1065 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1066 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1067
1068 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1069 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1070 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1071
1072 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1073 cb->cb_mrt_epitch);
1074 } else {
1075 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1076 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1077 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1078 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1079 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1080 radeon_emit(cmd_buffer->cs, cb_color_info);
1081 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1082 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1083 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1084 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1085 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1086 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1087
1088 if (is_vi) { /* DCC BASE */
1089 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1090 }
1091 }
1092
1093 if (radv_image_has_dcc(image)) {
1094 /* Drawing with DCC enabled also compresses colorbuffers. */
1095 radv_update_dcc_metadata(cmd_buffer, image, true);
1096 }
1097 }
1098
1099 static void
1100 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1101 struct radv_ds_buffer_info *ds,
1102 struct radv_image *image, VkImageLayout layout,
1103 bool requires_cond_exec)
1104 {
1105 uint32_t db_z_info = ds->db_z_info;
1106 uint32_t db_z_info_reg;
1107
1108 if (!radv_image_is_tc_compat_htile(image))
1109 return;
1110
1111 if (!radv_layout_has_htile(image, layout,
1112 radv_image_queue_family_mask(image,
1113 cmd_buffer->queue_family_index,
1114 cmd_buffer->queue_family_index))) {
1115 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1116 }
1117
1118 db_z_info &= C_028040_ZRANGE_PRECISION;
1119
1120 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1121 db_z_info_reg = R_028038_DB_Z_INFO;
1122 } else {
1123 db_z_info_reg = R_028040_DB_Z_INFO;
1124 }
1125
1126 /* When we don't know the last fast clear value we need to emit a
1127 * conditional packet that will eventually skip the following
1128 * SET_CONTEXT_REG packet.
1129 */
1130 if (requires_cond_exec) {
1131 uint64_t va = radv_buffer_get_va(image->bo);
1132 va += image->offset + image->tc_compat_zrange_offset;
1133
1134 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1135 radeon_emit(cmd_buffer->cs, va);
1136 radeon_emit(cmd_buffer->cs, va >> 32);
1137 radeon_emit(cmd_buffer->cs, 0);
1138 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1139 }
1140
1141 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1142 }
1143
1144 static void
1145 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1146 struct radv_ds_buffer_info *ds,
1147 struct radv_image *image,
1148 VkImageLayout layout)
1149 {
1150 uint32_t db_z_info = ds->db_z_info;
1151 uint32_t db_stencil_info = ds->db_stencil_info;
1152
1153 if (!radv_layout_has_htile(image, layout,
1154 radv_image_queue_family_mask(image,
1155 cmd_buffer->queue_family_index,
1156 cmd_buffer->queue_family_index))) {
1157 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1158 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1159 }
1160
1161 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1162 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1163
1164
1165 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1166 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1167 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1168 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1169 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1170
1171 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1172 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1173 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1174 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1175 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1176 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1177 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1178 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1179 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1180 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1181 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1182
1183 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1184 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1185 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1186 } else {
1187 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1188
1189 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1190 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1191 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1192 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1193 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1194 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1195 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1196 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1197 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1198 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1199
1200 }
1201
1202 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1203 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1204
1205 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1206 ds->pa_su_poly_offset_db_fmt_cntl);
1207 }
1208
1209 /**
1210 * Update the fast clear depth/stencil values if the image is bound as a
1211 * depth/stencil buffer.
1212 */
1213 static void
1214 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1215 struct radv_image *image,
1216 VkClearDepthStencilValue ds_clear_value,
1217 VkImageAspectFlags aspects)
1218 {
1219 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1220 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1221 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1222 struct radv_attachment_info *att;
1223 uint32_t att_idx;
1224
1225 if (!framebuffer || !subpass)
1226 return;
1227
1228 if (!subpass->depth_stencil_attachment)
1229 return;
1230
1231 att_idx = subpass->depth_stencil_attachment->attachment;
1232 att = &framebuffer->attachments[att_idx];
1233 if (att->attachment->image != image)
1234 return;
1235
1236 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1237 radeon_emit(cs, ds_clear_value.stencil);
1238 radeon_emit(cs, fui(ds_clear_value.depth));
1239
1240 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1241 * only needed when clearing Z to 0.0.
1242 */
1243 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1244 ds_clear_value.depth == 0.0) {
1245 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1246
1247 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1248 layout, false);
1249 }
1250
1251 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1252 }
1253
1254 /**
1255 * Set the clear depth/stencil values to the image's metadata.
1256 */
1257 static void
1258 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1259 struct radv_image *image,
1260 VkClearDepthStencilValue ds_clear_value,
1261 VkImageAspectFlags aspects)
1262 {
1263 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1264 uint64_t va = radv_buffer_get_va(image->bo);
1265 unsigned reg_offset = 0, reg_count = 0;
1266
1267 va += image->offset + image->clear_value_offset;
1268
1269 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1270 ++reg_count;
1271 } else {
1272 ++reg_offset;
1273 va += 4;
1274 }
1275 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1276 ++reg_count;
1277
1278 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
1279 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1280 S_370_WR_CONFIRM(1) |
1281 S_370_ENGINE_SEL(V_370_PFP));
1282 radeon_emit(cs, va);
1283 radeon_emit(cs, va >> 32);
1284 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1285 radeon_emit(cs, ds_clear_value.stencil);
1286 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1287 radeon_emit(cs, fui(ds_clear_value.depth));
1288 }
1289
1290 /**
1291 * Update the TC-compat metadata value for this image.
1292 */
1293 static void
1294 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1295 struct radv_image *image,
1296 uint32_t value)
1297 {
1298 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1299 uint64_t va = radv_buffer_get_va(image->bo);
1300 va += image->offset + image->tc_compat_zrange_offset;
1301
1302 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1303 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1304 S_370_WR_CONFIRM(1) |
1305 S_370_ENGINE_SEL(V_370_PFP));
1306 radeon_emit(cs, va);
1307 radeon_emit(cs, va >> 32);
1308 radeon_emit(cs, value);
1309 }
1310
1311 static void
1312 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1313 struct radv_image *image,
1314 VkClearDepthStencilValue ds_clear_value)
1315 {
1316 uint64_t va = radv_buffer_get_va(image->bo);
1317 va += image->offset + image->tc_compat_zrange_offset;
1318 uint32_t cond_val;
1319
1320 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1321 * depth clear value is 0.0f.
1322 */
1323 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1324
1325 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1326 }
1327
1328 /**
1329 * Update the clear depth/stencil values for this image.
1330 */
1331 void
1332 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1333 struct radv_image *image,
1334 VkClearDepthStencilValue ds_clear_value,
1335 VkImageAspectFlags aspects)
1336 {
1337 assert(radv_image_has_htile(image));
1338
1339 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1340
1341 if (radv_image_is_tc_compat_htile(image) &&
1342 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1343 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1344 ds_clear_value);
1345 }
1346
1347 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1348 aspects);
1349 }
1350
1351 /**
1352 * Load the clear depth/stencil values from the image's metadata.
1353 */
1354 static void
1355 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1356 struct radv_image *image)
1357 {
1358 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1359 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1360 uint64_t va = radv_buffer_get_va(image->bo);
1361 unsigned reg_offset = 0, reg_count = 0;
1362
1363 va += image->offset + image->clear_value_offset;
1364
1365 if (!radv_image_has_htile(image))
1366 return;
1367
1368 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1369 ++reg_count;
1370 } else {
1371 ++reg_offset;
1372 va += 4;
1373 }
1374 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1375 ++reg_count;
1376
1377 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1378
1379 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1380 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1381 radeon_emit(cs, va);
1382 radeon_emit(cs, va >> 32);
1383 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1384 radeon_emit(cs, reg_count);
1385 } else {
1386 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1387 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1388 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1389 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1390 radeon_emit(cs, va);
1391 radeon_emit(cs, va >> 32);
1392 radeon_emit(cs, reg >> 2);
1393 radeon_emit(cs, 0);
1394
1395 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1396 radeon_emit(cs, 0);
1397 }
1398 }
1399
1400 /*
1401 * With DCC some colors don't require CMASK elimination before being
1402 * used as a texture. This sets a predicate value to determine if the
1403 * cmask eliminate is required.
1404 */
1405 void
1406 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1407 struct radv_image *image, bool value)
1408 {
1409 uint64_t pred_val = value;
1410 uint64_t va = radv_buffer_get_va(image->bo);
1411 va += image->offset + image->fce_pred_offset;
1412
1413 assert(radv_image_has_dcc(image));
1414
1415 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1416 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1417 S_370_WR_CONFIRM(1) |
1418 S_370_ENGINE_SEL(V_370_PFP));
1419 radeon_emit(cmd_buffer->cs, va);
1420 radeon_emit(cmd_buffer->cs, va >> 32);
1421 radeon_emit(cmd_buffer->cs, pred_val);
1422 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1423 }
1424
1425 /**
1426 * Update the DCC predicate to reflect the compression state.
1427 */
1428 void
1429 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1430 struct radv_image *image, bool value)
1431 {
1432 uint64_t pred_val = value;
1433 uint64_t va = radv_buffer_get_va(image->bo);
1434 va += image->offset + image->dcc_pred_offset;
1435
1436 assert(radv_image_has_dcc(image));
1437
1438 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1439 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1440 S_370_WR_CONFIRM(1) |
1441 S_370_ENGINE_SEL(V_370_PFP));
1442 radeon_emit(cmd_buffer->cs, va);
1443 radeon_emit(cmd_buffer->cs, va >> 32);
1444 radeon_emit(cmd_buffer->cs, pred_val);
1445 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1446 }
1447
1448 /**
1449 * Update the fast clear color values if the image is bound as a color buffer.
1450 */
1451 static void
1452 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1453 struct radv_image *image,
1454 int cb_idx,
1455 uint32_t color_values[2])
1456 {
1457 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1458 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1459 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1460 struct radv_attachment_info *att;
1461 uint32_t att_idx;
1462
1463 if (!framebuffer || !subpass)
1464 return;
1465
1466 att_idx = subpass->color_attachments[cb_idx].attachment;
1467 if (att_idx == VK_ATTACHMENT_UNUSED)
1468 return;
1469
1470 att = &framebuffer->attachments[att_idx];
1471 if (att->attachment->image != image)
1472 return;
1473
1474 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1475 radeon_emit(cs, color_values[0]);
1476 radeon_emit(cs, color_values[1]);
1477
1478 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1479 }
1480
1481 /**
1482 * Set the clear color values to the image's metadata.
1483 */
1484 static void
1485 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1486 struct radv_image *image,
1487 uint32_t color_values[2])
1488 {
1489 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1490 uint64_t va = radv_buffer_get_va(image->bo);
1491
1492 va += image->offset + image->clear_value_offset;
1493
1494 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1495
1496 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, cmd_buffer->state.predicating));
1497 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1498 S_370_WR_CONFIRM(1) |
1499 S_370_ENGINE_SEL(V_370_PFP));
1500 radeon_emit(cs, va);
1501 radeon_emit(cs, va >> 32);
1502 radeon_emit(cs, color_values[0]);
1503 radeon_emit(cs, color_values[1]);
1504 }
1505
1506 /**
1507 * Update the clear color values for this image.
1508 */
1509 void
1510 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1511 struct radv_image *image,
1512 int cb_idx,
1513 uint32_t color_values[2])
1514 {
1515 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1516
1517 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1518
1519 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1520 color_values);
1521 }
1522
1523 /**
1524 * Load the clear color values from the image's metadata.
1525 */
1526 static void
1527 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1528 struct radv_image *image,
1529 int cb_idx)
1530 {
1531 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1532 uint64_t va = radv_buffer_get_va(image->bo);
1533
1534 va += image->offset + image->clear_value_offset;
1535
1536 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1537 return;
1538
1539 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1540
1541 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1542 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1543 radeon_emit(cs, va);
1544 radeon_emit(cs, va >> 32);
1545 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1546 radeon_emit(cs, 2);
1547 } else {
1548 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1549 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1550 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1551 COPY_DATA_COUNT_SEL);
1552 radeon_emit(cs, va);
1553 radeon_emit(cs, va >> 32);
1554 radeon_emit(cs, reg >> 2);
1555 radeon_emit(cs, 0);
1556
1557 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1558 radeon_emit(cs, 0);
1559 }
1560 }
1561
1562 static void
1563 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1564 {
1565 int i;
1566 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1567 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1568 unsigned num_bpp64_colorbufs = 0;
1569
1570 /* this may happen for inherited secondary recording */
1571 if (!framebuffer)
1572 return;
1573
1574 for (i = 0; i < 8; ++i) {
1575 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1576 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1577 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1578 continue;
1579 }
1580
1581 int idx = subpass->color_attachments[i].attachment;
1582 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1583 struct radv_image *image = att->attachment->image;
1584 VkImageLayout layout = subpass->color_attachments[i].layout;
1585
1586 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1587
1588 assert(att->attachment->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1589 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1590 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1591
1592 radv_load_color_clear_metadata(cmd_buffer, image, i);
1593
1594 if (image->planes[0].surface.bpe >= 8)
1595 num_bpp64_colorbufs++;
1596 }
1597
1598 if (subpass->depth_stencil_attachment) {
1599 int idx = subpass->depth_stencil_attachment->attachment;
1600 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1601 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1602 struct radv_image *image = att->attachment->image;
1603 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1604 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1605 cmd_buffer->queue_family_index,
1606 cmd_buffer->queue_family_index);
1607 /* We currently don't support writing decompressed HTILE */
1608 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1609 radv_layout_is_htile_compressed(image, layout, queue_mask));
1610
1611 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1612
1613 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1614 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1615 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1616 }
1617 radv_load_ds_clear_metadata(cmd_buffer, image);
1618 } else {
1619 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1620 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1621 else
1622 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1623
1624 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1625 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1626 }
1627 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1628 S_028208_BR_X(framebuffer->width) |
1629 S_028208_BR_Y(framebuffer->height));
1630
1631 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1632 uint8_t watermark = 4; /* Default value for VI. */
1633
1634 /* For optimal DCC performance. */
1635 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1636 if (num_bpp64_colorbufs >= 5) {
1637 watermark = 8;
1638 } else {
1639 watermark = 6;
1640 }
1641 }
1642
1643 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1644 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1645 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1646 }
1647
1648 if (cmd_buffer->device->dfsm_allowed) {
1649 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1650 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1651 }
1652
1653 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1654 }
1655
1656 static void
1657 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1658 {
1659 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1660 struct radv_cmd_state *state = &cmd_buffer->state;
1661
1662 if (state->index_type != state->last_index_type) {
1663 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1664 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1665 2, state->index_type);
1666 } else {
1667 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1668 radeon_emit(cs, state->index_type);
1669 }
1670
1671 state->last_index_type = state->index_type;
1672 }
1673
1674 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1675 radeon_emit(cs, state->index_va);
1676 radeon_emit(cs, state->index_va >> 32);
1677
1678 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1679 radeon_emit(cs, state->max_index_count);
1680
1681 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1682 }
1683
1684 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1685 {
1686 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1687 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1688 uint32_t pa_sc_mode_cntl_1 =
1689 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1690 uint32_t db_count_control;
1691
1692 if(!cmd_buffer->state.active_occlusion_queries) {
1693 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1694 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1695 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1696 has_perfect_queries) {
1697 /* Re-enable out-of-order rasterization if the
1698 * bound pipeline supports it and if it's has
1699 * been disabled before starting any perfect
1700 * occlusion queries.
1701 */
1702 radeon_set_context_reg(cmd_buffer->cs,
1703 R_028A4C_PA_SC_MODE_CNTL_1,
1704 pa_sc_mode_cntl_1);
1705 }
1706 }
1707 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1708 } else {
1709 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1710 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1711
1712 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1713 db_count_control =
1714 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1715 S_028004_SAMPLE_RATE(sample_rate) |
1716 S_028004_ZPASS_ENABLE(1) |
1717 S_028004_SLICE_EVEN_ENABLE(1) |
1718 S_028004_SLICE_ODD_ENABLE(1);
1719
1720 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1721 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1722 has_perfect_queries) {
1723 /* If the bound pipeline has enabled
1724 * out-of-order rasterization, we should
1725 * disable it before starting any perfect
1726 * occlusion queries.
1727 */
1728 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1729
1730 radeon_set_context_reg(cmd_buffer->cs,
1731 R_028A4C_PA_SC_MODE_CNTL_1,
1732 pa_sc_mode_cntl_1);
1733 }
1734 } else {
1735 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1736 S_028004_SAMPLE_RATE(sample_rate);
1737 }
1738 }
1739
1740 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1741
1742 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1743 }
1744
1745 static void
1746 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1747 {
1748 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1749
1750 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1751 radv_emit_viewport(cmd_buffer);
1752
1753 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1754 !cmd_buffer->device->physical_device->has_scissor_bug)
1755 radv_emit_scissor(cmd_buffer);
1756
1757 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1758 radv_emit_line_width(cmd_buffer);
1759
1760 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1761 radv_emit_blend_constants(cmd_buffer);
1762
1763 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1764 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1765 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1766 radv_emit_stencil(cmd_buffer);
1767
1768 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1769 radv_emit_depth_bounds(cmd_buffer);
1770
1771 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1772 radv_emit_depth_bias(cmd_buffer);
1773
1774 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1775 radv_emit_discard_rectangle(cmd_buffer);
1776
1777 cmd_buffer->state.dirty &= ~states;
1778 }
1779
1780 static void
1781 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1782 VkPipelineBindPoint bind_point)
1783 {
1784 struct radv_descriptor_state *descriptors_state =
1785 radv_get_descriptors_state(cmd_buffer, bind_point);
1786 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1787 unsigned bo_offset;
1788
1789 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1790 set->mapped_ptr,
1791 &bo_offset))
1792 return;
1793
1794 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1795 set->va += bo_offset;
1796 }
1797
1798 static void
1799 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1800 VkPipelineBindPoint bind_point)
1801 {
1802 struct radv_descriptor_state *descriptors_state =
1803 radv_get_descriptors_state(cmd_buffer, bind_point);
1804 uint32_t size = MAX_SETS * 4;
1805 uint32_t offset;
1806 void *ptr;
1807
1808 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1809 256, &offset, &ptr))
1810 return;
1811
1812 for (unsigned i = 0; i < MAX_SETS; i++) {
1813 uint32_t *uptr = ((uint32_t *)ptr) + i;
1814 uint64_t set_va = 0;
1815 struct radv_descriptor_set *set = descriptors_state->sets[i];
1816 if (descriptors_state->valid & (1u << i))
1817 set_va = set->va;
1818 uptr[0] = set_va & 0xffffffff;
1819 }
1820
1821 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1822 va += offset;
1823
1824 if (cmd_buffer->state.pipeline) {
1825 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1826 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1827 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1828
1829 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1830 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1831 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1832
1833 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1834 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1835 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1836
1837 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1838 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1839 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1840
1841 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1842 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1843 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1844 }
1845
1846 if (cmd_buffer->state.compute_pipeline)
1847 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1848 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1849 }
1850
1851 static void
1852 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1853 VkShaderStageFlags stages)
1854 {
1855 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1856 VK_PIPELINE_BIND_POINT_COMPUTE :
1857 VK_PIPELINE_BIND_POINT_GRAPHICS;
1858 struct radv_descriptor_state *descriptors_state =
1859 radv_get_descriptors_state(cmd_buffer, bind_point);
1860 struct radv_cmd_state *state = &cmd_buffer->state;
1861 bool flush_indirect_descriptors;
1862
1863 if (!descriptors_state->dirty)
1864 return;
1865
1866 if (descriptors_state->push_dirty)
1867 radv_flush_push_descriptors(cmd_buffer, bind_point);
1868
1869 flush_indirect_descriptors =
1870 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1871 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1872 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1873 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1874
1875 if (flush_indirect_descriptors)
1876 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1877
1878 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1879 cmd_buffer->cs,
1880 MAX_SETS * MESA_SHADER_STAGES * 4);
1881
1882 if (cmd_buffer->state.pipeline) {
1883 radv_foreach_stage(stage, stages) {
1884 if (!cmd_buffer->state.pipeline->shaders[stage])
1885 continue;
1886
1887 radv_emit_descriptor_pointers(cmd_buffer,
1888 cmd_buffer->state.pipeline,
1889 descriptors_state, stage);
1890 }
1891 }
1892
1893 if (cmd_buffer->state.compute_pipeline &&
1894 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1895 radv_emit_descriptor_pointers(cmd_buffer,
1896 cmd_buffer->state.compute_pipeline,
1897 descriptors_state,
1898 MESA_SHADER_COMPUTE);
1899 }
1900
1901 descriptors_state->dirty = 0;
1902 descriptors_state->push_dirty = false;
1903
1904 assert(cmd_buffer->cs->cdw <= cdw_max);
1905
1906 if (unlikely(cmd_buffer->device->trace_bo))
1907 radv_save_descriptors(cmd_buffer, bind_point);
1908 }
1909
1910 static void
1911 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1912 VkShaderStageFlags stages)
1913 {
1914 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1915 ? cmd_buffer->state.compute_pipeline
1916 : cmd_buffer->state.pipeline;
1917 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1918 VK_PIPELINE_BIND_POINT_COMPUTE :
1919 VK_PIPELINE_BIND_POINT_GRAPHICS;
1920 struct radv_descriptor_state *descriptors_state =
1921 radv_get_descriptors_state(cmd_buffer, bind_point);
1922 struct radv_pipeline_layout *layout = pipeline->layout;
1923 struct radv_shader_variant *shader, *prev_shader;
1924 bool need_push_constants = false;
1925 unsigned offset;
1926 void *ptr;
1927 uint64_t va;
1928
1929 stages &= cmd_buffer->push_constant_stages;
1930 if (!stages ||
1931 (!layout->push_constant_size && !layout->dynamic_offset_count))
1932 return;
1933
1934 radv_foreach_stage(stage, stages) {
1935 if (!pipeline->shaders[stage])
1936 continue;
1937
1938 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
1939 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
1940
1941 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
1942 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
1943
1944 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
1945 AC_UD_INLINE_PUSH_CONSTANTS,
1946 count,
1947 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
1948 }
1949
1950 if (need_push_constants) {
1951 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1952 16 * layout->dynamic_offset_count,
1953 256, &offset, &ptr))
1954 return;
1955
1956 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1957 memcpy((char*)ptr + layout->push_constant_size,
1958 descriptors_state->dynamic_buffers,
1959 16 * layout->dynamic_offset_count);
1960
1961 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1962 va += offset;
1963
1964 MAYBE_UNUSED unsigned cdw_max =
1965 radeon_check_space(cmd_buffer->device->ws,
1966 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1967
1968 prev_shader = NULL;
1969 radv_foreach_stage(stage, stages) {
1970 shader = radv_get_shader(pipeline, stage);
1971
1972 /* Avoid redundantly emitting the address for merged stages. */
1973 if (shader && shader != prev_shader) {
1974 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1975 AC_UD_PUSH_CONSTANTS, va);
1976
1977 prev_shader = shader;
1978 }
1979 }
1980 assert(cmd_buffer->cs->cdw <= cdw_max);
1981 }
1982
1983 cmd_buffer->push_constant_stages &= ~stages;
1984 }
1985
1986 static void
1987 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1988 bool pipeline_is_dirty)
1989 {
1990 if ((pipeline_is_dirty ||
1991 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1992 cmd_buffer->state.pipeline->num_vertex_bindings &&
1993 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1994 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1995 unsigned vb_offset;
1996 void *vb_ptr;
1997 uint32_t i = 0;
1998 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
1999 uint64_t va;
2000
2001 /* allocate some descriptor state for vertex buffers */
2002 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2003 &vb_offset, &vb_ptr))
2004 return;
2005
2006 for (i = 0; i < count; i++) {
2007 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2008 uint32_t offset;
2009 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2010 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2011
2012 if (!buffer)
2013 continue;
2014
2015 va = radv_buffer_get_va(buffer->bo);
2016
2017 offset = cmd_buffer->vertex_bindings[i].offset;
2018 va += offset + buffer->offset;
2019 desc[0] = va;
2020 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2021 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
2022 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2023 else
2024 desc[2] = buffer->size - offset;
2025 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2026 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2027 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2028 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2029 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2030 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2031 }
2032
2033 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2034 va += vb_offset;
2035
2036 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2037 AC_UD_VS_VERTEX_BUFFERS, va);
2038
2039 cmd_buffer->state.vb_va = va;
2040 cmd_buffer->state.vb_size = count * 16;
2041 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2042 }
2043 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2044 }
2045
2046 static void
2047 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2048 {
2049 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2050 struct radv_userdata_info *loc;
2051 uint32_t base_reg;
2052
2053 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2054 if (!radv_get_shader(pipeline, stage))
2055 continue;
2056
2057 loc = radv_lookup_user_sgpr(pipeline, stage,
2058 AC_UD_STREAMOUT_BUFFERS);
2059 if (loc->sgpr_idx == -1)
2060 continue;
2061
2062 base_reg = pipeline->user_data_0[stage];
2063
2064 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2065 base_reg + loc->sgpr_idx * 4, va, false);
2066 }
2067
2068 if (pipeline->gs_copy_shader) {
2069 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2070 if (loc->sgpr_idx != -1) {
2071 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2072
2073 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2074 base_reg + loc->sgpr_idx * 4, va, false);
2075 }
2076 }
2077 }
2078
2079 static void
2080 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2081 {
2082 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2083 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2084 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2085 unsigned so_offset;
2086 void *so_ptr;
2087 uint64_t va;
2088
2089 /* Allocate some descriptor state for streamout buffers. */
2090 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2091 MAX_SO_BUFFERS * 16, 256,
2092 &so_offset, &so_ptr))
2093 return;
2094
2095 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2096 struct radv_buffer *buffer = sb[i].buffer;
2097 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2098
2099 if (!(so->enabled_mask & (1 << i)))
2100 continue;
2101
2102 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2103
2104 va += sb[i].offset;
2105
2106 /* Set the descriptor.
2107 *
2108 * On VI, the format must be non-INVALID, otherwise
2109 * the buffer will be considered not bound and store
2110 * instructions will be no-ops.
2111 */
2112 desc[0] = va;
2113 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2114 desc[2] = 0xffffffff;
2115 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2116 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2117 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2118 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2119 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2120 }
2121
2122 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2123 va += so_offset;
2124
2125 radv_emit_streamout_buffers(cmd_buffer, va);
2126 }
2127
2128 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2129 }
2130
2131 static void
2132 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2133 {
2134 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2135 radv_flush_streamout_descriptors(cmd_buffer);
2136 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2137 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2138 }
2139
2140 struct radv_draw_info {
2141 /**
2142 * Number of vertices.
2143 */
2144 uint32_t count;
2145
2146 /**
2147 * Index of the first vertex.
2148 */
2149 int32_t vertex_offset;
2150
2151 /**
2152 * First instance id.
2153 */
2154 uint32_t first_instance;
2155
2156 /**
2157 * Number of instances.
2158 */
2159 uint32_t instance_count;
2160
2161 /**
2162 * First index (indexed draws only).
2163 */
2164 uint32_t first_index;
2165
2166 /**
2167 * Whether it's an indexed draw.
2168 */
2169 bool indexed;
2170
2171 /**
2172 * Indirect draw parameters resource.
2173 */
2174 struct radv_buffer *indirect;
2175 uint64_t indirect_offset;
2176 uint32_t stride;
2177
2178 /**
2179 * Draw count parameters resource.
2180 */
2181 struct radv_buffer *count_buffer;
2182 uint64_t count_buffer_offset;
2183
2184 /**
2185 * Stream output parameters resource.
2186 */
2187 struct radv_buffer *strmout_buffer;
2188 uint64_t strmout_buffer_offset;
2189 };
2190
2191 static void
2192 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2193 const struct radv_draw_info *draw_info)
2194 {
2195 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2196 struct radv_cmd_state *state = &cmd_buffer->state;
2197 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2198 uint32_t ia_multi_vgt_param;
2199 int32_t primitive_reset_en;
2200
2201 /* Draw state. */
2202 ia_multi_vgt_param =
2203 si_get_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2204 draw_info->indirect,
2205 draw_info->indirect ? 0 : draw_info->count);
2206
2207 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2208 if (info->chip_class >= GFX9) {
2209 radeon_set_uconfig_reg_idx(cs,
2210 R_030960_IA_MULTI_VGT_PARAM,
2211 4, ia_multi_vgt_param);
2212 } else if (info->chip_class >= CIK) {
2213 radeon_set_context_reg_idx(cs,
2214 R_028AA8_IA_MULTI_VGT_PARAM,
2215 1, ia_multi_vgt_param);
2216 } else {
2217 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2218 ia_multi_vgt_param);
2219 }
2220 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2221 }
2222
2223 /* Primitive restart. */
2224 primitive_reset_en =
2225 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2226
2227 if (primitive_reset_en != state->last_primitive_reset_en) {
2228 state->last_primitive_reset_en = primitive_reset_en;
2229 if (info->chip_class >= GFX9) {
2230 radeon_set_uconfig_reg(cs,
2231 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2232 primitive_reset_en);
2233 } else {
2234 radeon_set_context_reg(cs,
2235 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2236 primitive_reset_en);
2237 }
2238 }
2239
2240 if (primitive_reset_en) {
2241 uint32_t primitive_reset_index =
2242 state->index_type ? 0xffffffffu : 0xffffu;
2243
2244 if (primitive_reset_index != state->last_primitive_reset_index) {
2245 radeon_set_context_reg(cs,
2246 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2247 primitive_reset_index);
2248 state->last_primitive_reset_index = primitive_reset_index;
2249 }
2250 }
2251
2252 if (draw_info->strmout_buffer) {
2253 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2254
2255 va += draw_info->strmout_buffer->offset +
2256 draw_info->strmout_buffer_offset;
2257
2258 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2259 draw_info->stride);
2260
2261 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2262 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2263 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2264 COPY_DATA_WR_CONFIRM);
2265 radeon_emit(cs, va);
2266 radeon_emit(cs, va >> 32);
2267 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2268 radeon_emit(cs, 0); /* unused */
2269
2270 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2271 }
2272 }
2273
2274 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2275 VkPipelineStageFlags src_stage_mask)
2276 {
2277 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2278 VK_PIPELINE_STAGE_TRANSFER_BIT |
2279 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2280 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2281 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2282 }
2283
2284 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2285 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2286 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2287 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2288 VK_PIPELINE_STAGE_TRANSFER_BIT |
2289 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2290 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2291 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2292 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2293 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2294 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2295 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2296 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2297 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2298 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2299 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2300 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2301 }
2302 }
2303
2304 static enum radv_cmd_flush_bits
2305 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2306 VkAccessFlags src_flags,
2307 struct radv_image *image)
2308 {
2309 bool flush_CB_meta = true, flush_DB_meta = true;
2310 enum radv_cmd_flush_bits flush_bits = 0;
2311 uint32_t b;
2312
2313 if (image) {
2314 if (!radv_image_has_CB_metadata(image))
2315 flush_CB_meta = false;
2316 if (!radv_image_has_htile(image))
2317 flush_DB_meta = false;
2318 }
2319
2320 for_each_bit(b, src_flags) {
2321 switch ((VkAccessFlagBits)(1 << b)) {
2322 case VK_ACCESS_SHADER_WRITE_BIT:
2323 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2324 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2325 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2326 break;
2327 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2328 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2329 if (flush_CB_meta)
2330 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2331 break;
2332 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2333 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2334 if (flush_DB_meta)
2335 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2336 break;
2337 case VK_ACCESS_TRANSFER_WRITE_BIT:
2338 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2339 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2340 RADV_CMD_FLAG_INV_GLOBAL_L2;
2341
2342 if (flush_CB_meta)
2343 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2344 if (flush_DB_meta)
2345 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2346 break;
2347 default:
2348 break;
2349 }
2350 }
2351 return flush_bits;
2352 }
2353
2354 static enum radv_cmd_flush_bits
2355 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2356 VkAccessFlags dst_flags,
2357 struct radv_image *image)
2358 {
2359 bool flush_CB_meta = true, flush_DB_meta = true;
2360 enum radv_cmd_flush_bits flush_bits = 0;
2361 bool flush_CB = true, flush_DB = true;
2362 bool image_is_coherent = false;
2363 uint32_t b;
2364
2365 if (image) {
2366 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2367 flush_CB = false;
2368 flush_DB = false;
2369 }
2370
2371 if (!radv_image_has_CB_metadata(image))
2372 flush_CB_meta = false;
2373 if (!radv_image_has_htile(image))
2374 flush_DB_meta = false;
2375
2376 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2377 if (image->info.samples == 1 &&
2378 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2379 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2380 !vk_format_is_stencil(image->vk_format)) {
2381 /* Single-sample color and single-sample depth
2382 * (not stencil) are coherent with shaders on
2383 * GFX9.
2384 */
2385 image_is_coherent = true;
2386 }
2387 }
2388 }
2389
2390 for_each_bit(b, dst_flags) {
2391 switch ((VkAccessFlagBits)(1 << b)) {
2392 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2393 case VK_ACCESS_INDEX_READ_BIT:
2394 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2395 break;
2396 case VK_ACCESS_UNIFORM_READ_BIT:
2397 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2398 break;
2399 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2400 case VK_ACCESS_TRANSFER_READ_BIT:
2401 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2402 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2403 RADV_CMD_FLAG_INV_GLOBAL_L2;
2404 break;
2405 case VK_ACCESS_SHADER_READ_BIT:
2406 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2407
2408 if (!image_is_coherent)
2409 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2410 break;
2411 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2412 if (flush_CB)
2413 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2414 if (flush_CB_meta)
2415 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2416 break;
2417 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2418 if (flush_DB)
2419 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2420 if (flush_DB_meta)
2421 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2422 break;
2423 default:
2424 break;
2425 }
2426 }
2427 return flush_bits;
2428 }
2429
2430 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2431 const struct radv_subpass_barrier *barrier)
2432 {
2433 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2434 NULL);
2435 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2436 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2437 NULL);
2438 }
2439
2440 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2441 struct radv_subpass_attachment att)
2442 {
2443 unsigned idx = att.attachment;
2444 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2445 VkImageSubresourceRange range;
2446 range.aspectMask = 0;
2447 range.baseMipLevel = view->base_mip;
2448 range.levelCount = 1;
2449 range.baseArrayLayer = view->base_layer;
2450 range.layerCount = cmd_buffer->state.framebuffer->layers;
2451
2452 if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
2453 /* If the current subpass uses multiview, the driver might have
2454 * performed a fast color/depth clear to the whole image
2455 * (including all layers). To make sure the driver will
2456 * decompress the image correctly (if needed), we have to
2457 * account for the "real" number of layers. If the view mask is
2458 * sparse, this will decompress more layers than needed.
2459 */
2460 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2461 }
2462
2463 radv_handle_image_transition(cmd_buffer,
2464 view->image,
2465 cmd_buffer->state.attachments[idx].current_layout,
2466 att.layout, 0, 0, &range);
2467
2468 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2469
2470
2471 }
2472
2473 void
2474 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2475 const struct radv_subpass *subpass)
2476 {
2477 cmd_buffer->state.subpass = subpass;
2478
2479 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2480 }
2481
2482 static VkResult
2483 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2484 struct radv_render_pass *pass,
2485 const VkRenderPassBeginInfo *info)
2486 {
2487 struct radv_cmd_state *state = &cmd_buffer->state;
2488
2489 if (pass->attachment_count == 0) {
2490 state->attachments = NULL;
2491 return VK_SUCCESS;
2492 }
2493
2494 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2495 pass->attachment_count *
2496 sizeof(state->attachments[0]),
2497 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2498 if (state->attachments == NULL) {
2499 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2500 return cmd_buffer->record_result;
2501 }
2502
2503 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2504 struct radv_render_pass_attachment *att = &pass->attachments[i];
2505 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2506 VkImageAspectFlags clear_aspects = 0;
2507
2508 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2509 /* color attachment */
2510 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2511 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2512 }
2513 } else {
2514 /* depthstencil attachment */
2515 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2516 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2517 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2518 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2519 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2520 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2521 }
2522 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2523 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2524 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2525 }
2526 }
2527
2528 state->attachments[i].pending_clear_aspects = clear_aspects;
2529 state->attachments[i].cleared_views = 0;
2530 if (clear_aspects && info) {
2531 assert(info->clearValueCount > i);
2532 state->attachments[i].clear_value = info->pClearValues[i];
2533 }
2534
2535 state->attachments[i].current_layout = att->initial_layout;
2536 }
2537
2538 return VK_SUCCESS;
2539 }
2540
2541 VkResult radv_AllocateCommandBuffers(
2542 VkDevice _device,
2543 const VkCommandBufferAllocateInfo *pAllocateInfo,
2544 VkCommandBuffer *pCommandBuffers)
2545 {
2546 RADV_FROM_HANDLE(radv_device, device, _device);
2547 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2548
2549 VkResult result = VK_SUCCESS;
2550 uint32_t i;
2551
2552 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2553
2554 if (!list_empty(&pool->free_cmd_buffers)) {
2555 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2556
2557 list_del(&cmd_buffer->pool_link);
2558 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2559
2560 result = radv_reset_cmd_buffer(cmd_buffer);
2561 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2562 cmd_buffer->level = pAllocateInfo->level;
2563
2564 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2565 } else {
2566 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2567 &pCommandBuffers[i]);
2568 }
2569 if (result != VK_SUCCESS)
2570 break;
2571 }
2572
2573 if (result != VK_SUCCESS) {
2574 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2575 i, pCommandBuffers);
2576
2577 /* From the Vulkan 1.0.66 spec:
2578 *
2579 * "vkAllocateCommandBuffers can be used to create multiple
2580 * command buffers. If the creation of any of those command
2581 * buffers fails, the implementation must destroy all
2582 * successfully created command buffer objects from this
2583 * command, set all entries of the pCommandBuffers array to
2584 * NULL and return the error."
2585 */
2586 memset(pCommandBuffers, 0,
2587 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2588 }
2589
2590 return result;
2591 }
2592
2593 void radv_FreeCommandBuffers(
2594 VkDevice device,
2595 VkCommandPool commandPool,
2596 uint32_t commandBufferCount,
2597 const VkCommandBuffer *pCommandBuffers)
2598 {
2599 for (uint32_t i = 0; i < commandBufferCount; i++) {
2600 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2601
2602 if (cmd_buffer) {
2603 if (cmd_buffer->pool) {
2604 list_del(&cmd_buffer->pool_link);
2605 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2606 } else
2607 radv_cmd_buffer_destroy(cmd_buffer);
2608
2609 }
2610 }
2611 }
2612
2613 VkResult radv_ResetCommandBuffer(
2614 VkCommandBuffer commandBuffer,
2615 VkCommandBufferResetFlags flags)
2616 {
2617 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2618 return radv_reset_cmd_buffer(cmd_buffer);
2619 }
2620
2621 VkResult radv_BeginCommandBuffer(
2622 VkCommandBuffer commandBuffer,
2623 const VkCommandBufferBeginInfo *pBeginInfo)
2624 {
2625 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2626 VkResult result = VK_SUCCESS;
2627
2628 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2629 /* If the command buffer has already been resetted with
2630 * vkResetCommandBuffer, no need to do it again.
2631 */
2632 result = radv_reset_cmd_buffer(cmd_buffer);
2633 if (result != VK_SUCCESS)
2634 return result;
2635 }
2636
2637 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2638 cmd_buffer->state.last_primitive_reset_en = -1;
2639 cmd_buffer->state.last_index_type = -1;
2640 cmd_buffer->state.last_num_instances = -1;
2641 cmd_buffer->state.last_vertex_offset = -1;
2642 cmd_buffer->state.last_first_instance = -1;
2643 cmd_buffer->state.predication_type = -1;
2644 cmd_buffer->usage_flags = pBeginInfo->flags;
2645
2646 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2647 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2648 assert(pBeginInfo->pInheritanceInfo);
2649 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2650 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2651
2652 struct radv_subpass *subpass =
2653 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2654
2655 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2656 if (result != VK_SUCCESS)
2657 return result;
2658
2659 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
2660 }
2661
2662 if (unlikely(cmd_buffer->device->trace_bo)) {
2663 struct radv_device *device = cmd_buffer->device;
2664
2665 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2666 device->trace_bo);
2667
2668 radv_cmd_buffer_trace_emit(cmd_buffer);
2669 }
2670
2671 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2672
2673 return result;
2674 }
2675
2676 void radv_CmdBindVertexBuffers(
2677 VkCommandBuffer commandBuffer,
2678 uint32_t firstBinding,
2679 uint32_t bindingCount,
2680 const VkBuffer* pBuffers,
2681 const VkDeviceSize* pOffsets)
2682 {
2683 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2684 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2685 bool changed = false;
2686
2687 /* We have to defer setting up vertex buffer since we need the buffer
2688 * stride from the pipeline. */
2689
2690 assert(firstBinding + bindingCount <= MAX_VBS);
2691 for (uint32_t i = 0; i < bindingCount; i++) {
2692 uint32_t idx = firstBinding + i;
2693
2694 if (!changed &&
2695 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2696 vb[idx].offset != pOffsets[i])) {
2697 changed = true;
2698 }
2699
2700 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2701 vb[idx].offset = pOffsets[i];
2702
2703 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2704 vb[idx].buffer->bo);
2705 }
2706
2707 if (!changed) {
2708 /* No state changes. */
2709 return;
2710 }
2711
2712 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2713 }
2714
2715 void radv_CmdBindIndexBuffer(
2716 VkCommandBuffer commandBuffer,
2717 VkBuffer buffer,
2718 VkDeviceSize offset,
2719 VkIndexType indexType)
2720 {
2721 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2722 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2723
2724 if (cmd_buffer->state.index_buffer == index_buffer &&
2725 cmd_buffer->state.index_offset == offset &&
2726 cmd_buffer->state.index_type == indexType) {
2727 /* No state changes. */
2728 return;
2729 }
2730
2731 cmd_buffer->state.index_buffer = index_buffer;
2732 cmd_buffer->state.index_offset = offset;
2733 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2734 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2735 cmd_buffer->state.index_va += index_buffer->offset + offset;
2736
2737 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2738 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2739 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2740 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2741 }
2742
2743
2744 static void
2745 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2746 VkPipelineBindPoint bind_point,
2747 struct radv_descriptor_set *set, unsigned idx)
2748 {
2749 struct radeon_winsys *ws = cmd_buffer->device->ws;
2750
2751 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2752
2753 assert(set);
2754 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2755
2756 if (!cmd_buffer->device->use_global_bo_list) {
2757 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2758 if (set->descriptors[j])
2759 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2760 }
2761
2762 if(set->bo)
2763 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2764 }
2765
2766 void radv_CmdBindDescriptorSets(
2767 VkCommandBuffer commandBuffer,
2768 VkPipelineBindPoint pipelineBindPoint,
2769 VkPipelineLayout _layout,
2770 uint32_t firstSet,
2771 uint32_t descriptorSetCount,
2772 const VkDescriptorSet* pDescriptorSets,
2773 uint32_t dynamicOffsetCount,
2774 const uint32_t* pDynamicOffsets)
2775 {
2776 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2777 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2778 unsigned dyn_idx = 0;
2779
2780 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2781 struct radv_descriptor_state *descriptors_state =
2782 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2783
2784 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2785 unsigned idx = i + firstSet;
2786 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2787 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2788
2789 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2790 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2791 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2792 assert(dyn_idx < dynamicOffsetCount);
2793
2794 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2795 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2796 dst[0] = va;
2797 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2798 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2799 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2800 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2801 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2802 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2803 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2804 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2805 cmd_buffer->push_constant_stages |=
2806 set->layout->dynamic_shader_stages;
2807 }
2808 }
2809 }
2810
2811 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2812 struct radv_descriptor_set *set,
2813 struct radv_descriptor_set_layout *layout,
2814 VkPipelineBindPoint bind_point)
2815 {
2816 struct radv_descriptor_state *descriptors_state =
2817 radv_get_descriptors_state(cmd_buffer, bind_point);
2818 set->size = layout->size;
2819 set->layout = layout;
2820
2821 if (descriptors_state->push_set.capacity < set->size) {
2822 size_t new_size = MAX2(set->size, 1024);
2823 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2824 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2825
2826 free(set->mapped_ptr);
2827 set->mapped_ptr = malloc(new_size);
2828
2829 if (!set->mapped_ptr) {
2830 descriptors_state->push_set.capacity = 0;
2831 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2832 return false;
2833 }
2834
2835 descriptors_state->push_set.capacity = new_size;
2836 }
2837
2838 return true;
2839 }
2840
2841 void radv_meta_push_descriptor_set(
2842 struct radv_cmd_buffer* cmd_buffer,
2843 VkPipelineBindPoint pipelineBindPoint,
2844 VkPipelineLayout _layout,
2845 uint32_t set,
2846 uint32_t descriptorWriteCount,
2847 const VkWriteDescriptorSet* pDescriptorWrites)
2848 {
2849 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2850 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2851 unsigned bo_offset;
2852
2853 assert(set == 0);
2854 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2855
2856 push_set->size = layout->set[set].layout->size;
2857 push_set->layout = layout->set[set].layout;
2858
2859 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2860 &bo_offset,
2861 (void**) &push_set->mapped_ptr))
2862 return;
2863
2864 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2865 push_set->va += bo_offset;
2866
2867 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2868 radv_descriptor_set_to_handle(push_set),
2869 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2870
2871 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2872 }
2873
2874 void radv_CmdPushDescriptorSetKHR(
2875 VkCommandBuffer commandBuffer,
2876 VkPipelineBindPoint pipelineBindPoint,
2877 VkPipelineLayout _layout,
2878 uint32_t set,
2879 uint32_t descriptorWriteCount,
2880 const VkWriteDescriptorSet* pDescriptorWrites)
2881 {
2882 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2883 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2884 struct radv_descriptor_state *descriptors_state =
2885 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2886 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2887
2888 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2889
2890 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2891 layout->set[set].layout,
2892 pipelineBindPoint))
2893 return;
2894
2895 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2896 radv_descriptor_set_to_handle(push_set),
2897 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2898
2899 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2900 descriptors_state->push_dirty = true;
2901 }
2902
2903 void radv_CmdPushDescriptorSetWithTemplateKHR(
2904 VkCommandBuffer commandBuffer,
2905 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2906 VkPipelineLayout _layout,
2907 uint32_t set,
2908 const void* pData)
2909 {
2910 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2911 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2912 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2913 struct radv_descriptor_state *descriptors_state =
2914 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2915 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2916
2917 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2918
2919 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2920 layout->set[set].layout,
2921 templ->bind_point))
2922 return;
2923
2924 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2925 descriptorUpdateTemplate, pData);
2926
2927 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2928 descriptors_state->push_dirty = true;
2929 }
2930
2931 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2932 VkPipelineLayout layout,
2933 VkShaderStageFlags stageFlags,
2934 uint32_t offset,
2935 uint32_t size,
2936 const void* pValues)
2937 {
2938 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2939 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2940 cmd_buffer->push_constant_stages |= stageFlags;
2941 }
2942
2943 VkResult radv_EndCommandBuffer(
2944 VkCommandBuffer commandBuffer)
2945 {
2946 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2947
2948 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2949 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2950 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2951 si_emit_cache_flush(cmd_buffer);
2952 }
2953
2954 /* Make sure CP DMA is idle at the end of IBs because the kernel
2955 * doesn't wait for it.
2956 */
2957 si_cp_dma_wait_for_idle(cmd_buffer);
2958
2959 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2960
2961 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2962 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2963
2964 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2965
2966 return cmd_buffer->record_result;
2967 }
2968
2969 static void
2970 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2971 {
2972 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2973
2974 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2975 return;
2976
2977 assert(!pipeline->ctx_cs.cdw);
2978
2979 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2980
2981 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2982 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2983
2984 cmd_buffer->compute_scratch_size_needed =
2985 MAX2(cmd_buffer->compute_scratch_size_needed,
2986 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2987
2988 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2989 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2990
2991 if (unlikely(cmd_buffer->device->trace_bo))
2992 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2993 }
2994
2995 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2996 VkPipelineBindPoint bind_point)
2997 {
2998 struct radv_descriptor_state *descriptors_state =
2999 radv_get_descriptors_state(cmd_buffer, bind_point);
3000
3001 descriptors_state->dirty |= descriptors_state->valid;
3002 }
3003
3004 void radv_CmdBindPipeline(
3005 VkCommandBuffer commandBuffer,
3006 VkPipelineBindPoint pipelineBindPoint,
3007 VkPipeline _pipeline)
3008 {
3009 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3010 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3011
3012 switch (pipelineBindPoint) {
3013 case VK_PIPELINE_BIND_POINT_COMPUTE:
3014 if (cmd_buffer->state.compute_pipeline == pipeline)
3015 return;
3016 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3017
3018 cmd_buffer->state.compute_pipeline = pipeline;
3019 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3020 break;
3021 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3022 if (cmd_buffer->state.pipeline == pipeline)
3023 return;
3024 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3025
3026 cmd_buffer->state.pipeline = pipeline;
3027 if (!pipeline)
3028 break;
3029
3030 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3031 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3032
3033 /* the new vertex shader might not have the same user regs */
3034 cmd_buffer->state.last_first_instance = -1;
3035 cmd_buffer->state.last_vertex_offset = -1;
3036
3037 /* Prefetch all pipeline shaders at first draw time. */
3038 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3039
3040 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3041 radv_bind_streamout_state(cmd_buffer, pipeline);
3042
3043 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3044 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3045 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3046 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3047
3048 if (radv_pipeline_has_tess(pipeline))
3049 cmd_buffer->tess_rings_needed = true;
3050 break;
3051 default:
3052 assert(!"invalid bind point");
3053 break;
3054 }
3055 }
3056
3057 void radv_CmdSetViewport(
3058 VkCommandBuffer commandBuffer,
3059 uint32_t firstViewport,
3060 uint32_t viewportCount,
3061 const VkViewport* pViewports)
3062 {
3063 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3064 struct radv_cmd_state *state = &cmd_buffer->state;
3065 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3066
3067 assert(firstViewport < MAX_VIEWPORTS);
3068 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3069
3070 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3071 pViewports, viewportCount * sizeof(*pViewports))) {
3072 return;
3073 }
3074
3075 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3076 viewportCount * sizeof(*pViewports));
3077
3078 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3079 }
3080
3081 void radv_CmdSetScissor(
3082 VkCommandBuffer commandBuffer,
3083 uint32_t firstScissor,
3084 uint32_t scissorCount,
3085 const VkRect2D* pScissors)
3086 {
3087 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3088 struct radv_cmd_state *state = &cmd_buffer->state;
3089 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3090
3091 assert(firstScissor < MAX_SCISSORS);
3092 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3093
3094 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3095 scissorCount * sizeof(*pScissors))) {
3096 return;
3097 }
3098
3099 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3100 scissorCount * sizeof(*pScissors));
3101
3102 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3103 }
3104
3105 void radv_CmdSetLineWidth(
3106 VkCommandBuffer commandBuffer,
3107 float lineWidth)
3108 {
3109 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3110
3111 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3112 return;
3113
3114 cmd_buffer->state.dynamic.line_width = lineWidth;
3115 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3116 }
3117
3118 void radv_CmdSetDepthBias(
3119 VkCommandBuffer commandBuffer,
3120 float depthBiasConstantFactor,
3121 float depthBiasClamp,
3122 float depthBiasSlopeFactor)
3123 {
3124 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3125 struct radv_cmd_state *state = &cmd_buffer->state;
3126
3127 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3128 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3129 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3130 return;
3131 }
3132
3133 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3134 state->dynamic.depth_bias.clamp = depthBiasClamp;
3135 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3136
3137 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3138 }
3139
3140 void radv_CmdSetBlendConstants(
3141 VkCommandBuffer commandBuffer,
3142 const float blendConstants[4])
3143 {
3144 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3145 struct radv_cmd_state *state = &cmd_buffer->state;
3146
3147 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3148 return;
3149
3150 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3151
3152 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3153 }
3154
3155 void radv_CmdSetDepthBounds(
3156 VkCommandBuffer commandBuffer,
3157 float minDepthBounds,
3158 float maxDepthBounds)
3159 {
3160 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3161 struct radv_cmd_state *state = &cmd_buffer->state;
3162
3163 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3164 state->dynamic.depth_bounds.max == maxDepthBounds) {
3165 return;
3166 }
3167
3168 state->dynamic.depth_bounds.min = minDepthBounds;
3169 state->dynamic.depth_bounds.max = maxDepthBounds;
3170
3171 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3172 }
3173
3174 void radv_CmdSetStencilCompareMask(
3175 VkCommandBuffer commandBuffer,
3176 VkStencilFaceFlags faceMask,
3177 uint32_t compareMask)
3178 {
3179 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3180 struct radv_cmd_state *state = &cmd_buffer->state;
3181 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3182 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3183
3184 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3185 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3186 return;
3187 }
3188
3189 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3190 state->dynamic.stencil_compare_mask.front = compareMask;
3191 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3192 state->dynamic.stencil_compare_mask.back = compareMask;
3193
3194 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3195 }
3196
3197 void radv_CmdSetStencilWriteMask(
3198 VkCommandBuffer commandBuffer,
3199 VkStencilFaceFlags faceMask,
3200 uint32_t writeMask)
3201 {
3202 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3203 struct radv_cmd_state *state = &cmd_buffer->state;
3204 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3205 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3206
3207 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3208 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3209 return;
3210 }
3211
3212 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3213 state->dynamic.stencil_write_mask.front = writeMask;
3214 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3215 state->dynamic.stencil_write_mask.back = writeMask;
3216
3217 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3218 }
3219
3220 void radv_CmdSetStencilReference(
3221 VkCommandBuffer commandBuffer,
3222 VkStencilFaceFlags faceMask,
3223 uint32_t reference)
3224 {
3225 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3226 struct radv_cmd_state *state = &cmd_buffer->state;
3227 bool front_same = state->dynamic.stencil_reference.front == reference;
3228 bool back_same = state->dynamic.stencil_reference.back == reference;
3229
3230 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3231 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3232 return;
3233 }
3234
3235 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3236 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3237 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3238 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3239
3240 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3241 }
3242
3243 void radv_CmdSetDiscardRectangleEXT(
3244 VkCommandBuffer commandBuffer,
3245 uint32_t firstDiscardRectangle,
3246 uint32_t discardRectangleCount,
3247 const VkRect2D* pDiscardRectangles)
3248 {
3249 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3250 struct radv_cmd_state *state = &cmd_buffer->state;
3251 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3252
3253 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3254 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3255
3256 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3257 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3258 return;
3259 }
3260
3261 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3262 pDiscardRectangles, discardRectangleCount);
3263
3264 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3265 }
3266
3267 void radv_CmdExecuteCommands(
3268 VkCommandBuffer commandBuffer,
3269 uint32_t commandBufferCount,
3270 const VkCommandBuffer* pCmdBuffers)
3271 {
3272 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3273
3274 assert(commandBufferCount > 0);
3275
3276 /* Emit pending flushes on primary prior to executing secondary */
3277 si_emit_cache_flush(primary);
3278
3279 for (uint32_t i = 0; i < commandBufferCount; i++) {
3280 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3281
3282 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3283 secondary->scratch_size_needed);
3284 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3285 secondary->compute_scratch_size_needed);
3286
3287 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3288 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3289 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3290 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3291 if (secondary->tess_rings_needed)
3292 primary->tess_rings_needed = true;
3293 if (secondary->sample_positions_needed)
3294 primary->sample_positions_needed = true;
3295
3296 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3297
3298
3299 /* When the secondary command buffer is compute only we don't
3300 * need to re-emit the current graphics pipeline.
3301 */
3302 if (secondary->state.emitted_pipeline) {
3303 primary->state.emitted_pipeline =
3304 secondary->state.emitted_pipeline;
3305 }
3306
3307 /* When the secondary command buffer is graphics only we don't
3308 * need to re-emit the current compute pipeline.
3309 */
3310 if (secondary->state.emitted_compute_pipeline) {
3311 primary->state.emitted_compute_pipeline =
3312 secondary->state.emitted_compute_pipeline;
3313 }
3314
3315 /* Only re-emit the draw packets when needed. */
3316 if (secondary->state.last_primitive_reset_en != -1) {
3317 primary->state.last_primitive_reset_en =
3318 secondary->state.last_primitive_reset_en;
3319 }
3320
3321 if (secondary->state.last_primitive_reset_index) {
3322 primary->state.last_primitive_reset_index =
3323 secondary->state.last_primitive_reset_index;
3324 }
3325
3326 if (secondary->state.last_ia_multi_vgt_param) {
3327 primary->state.last_ia_multi_vgt_param =
3328 secondary->state.last_ia_multi_vgt_param;
3329 }
3330
3331 primary->state.last_first_instance = secondary->state.last_first_instance;
3332 primary->state.last_num_instances = secondary->state.last_num_instances;
3333 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3334
3335 if (secondary->state.last_index_type != -1) {
3336 primary->state.last_index_type =
3337 secondary->state.last_index_type;
3338 }
3339 }
3340
3341 /* After executing commands from secondary buffers we have to dirty
3342 * some states.
3343 */
3344 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3345 RADV_CMD_DIRTY_INDEX_BUFFER |
3346 RADV_CMD_DIRTY_DYNAMIC_ALL;
3347 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3348 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3349 }
3350
3351 VkResult radv_CreateCommandPool(
3352 VkDevice _device,
3353 const VkCommandPoolCreateInfo* pCreateInfo,
3354 const VkAllocationCallbacks* pAllocator,
3355 VkCommandPool* pCmdPool)
3356 {
3357 RADV_FROM_HANDLE(radv_device, device, _device);
3358 struct radv_cmd_pool *pool;
3359
3360 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3361 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3362 if (pool == NULL)
3363 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3364
3365 if (pAllocator)
3366 pool->alloc = *pAllocator;
3367 else
3368 pool->alloc = device->alloc;
3369
3370 list_inithead(&pool->cmd_buffers);
3371 list_inithead(&pool->free_cmd_buffers);
3372
3373 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3374
3375 *pCmdPool = radv_cmd_pool_to_handle(pool);
3376
3377 return VK_SUCCESS;
3378
3379 }
3380
3381 void radv_DestroyCommandPool(
3382 VkDevice _device,
3383 VkCommandPool commandPool,
3384 const VkAllocationCallbacks* pAllocator)
3385 {
3386 RADV_FROM_HANDLE(radv_device, device, _device);
3387 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3388
3389 if (!pool)
3390 return;
3391
3392 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3393 &pool->cmd_buffers, pool_link) {
3394 radv_cmd_buffer_destroy(cmd_buffer);
3395 }
3396
3397 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3398 &pool->free_cmd_buffers, pool_link) {
3399 radv_cmd_buffer_destroy(cmd_buffer);
3400 }
3401
3402 vk_free2(&device->alloc, pAllocator, pool);
3403 }
3404
3405 VkResult radv_ResetCommandPool(
3406 VkDevice device,
3407 VkCommandPool commandPool,
3408 VkCommandPoolResetFlags flags)
3409 {
3410 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3411 VkResult result;
3412
3413 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3414 &pool->cmd_buffers, pool_link) {
3415 result = radv_reset_cmd_buffer(cmd_buffer);
3416 if (result != VK_SUCCESS)
3417 return result;
3418 }
3419
3420 return VK_SUCCESS;
3421 }
3422
3423 void radv_TrimCommandPool(
3424 VkDevice device,
3425 VkCommandPool commandPool,
3426 VkCommandPoolTrimFlags flags)
3427 {
3428 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3429
3430 if (!pool)
3431 return;
3432
3433 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3434 &pool->free_cmd_buffers, pool_link) {
3435 radv_cmd_buffer_destroy(cmd_buffer);
3436 }
3437 }
3438
3439 static uint32_t
3440 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3441 {
3442 struct radv_cmd_state *state = &cmd_buffer->state;
3443 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3444
3445 /* The id of this subpass shouldn't exceed the number of subpasses in
3446 * this render pass minus 1.
3447 */
3448 assert(subpass_id < state->pass->subpass_count);
3449 return subpass_id;
3450 }
3451
3452 static void
3453 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
3454 uint32_t subpass_id)
3455 {
3456 struct radv_cmd_state *state = &cmd_buffer->state;
3457 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
3458
3459 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3460 cmd_buffer->cs, 4096);
3461
3462 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
3463
3464 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3465 const uint32_t a = subpass->attachments[i].attachment;
3466 if (a == VK_ATTACHMENT_UNUSED)
3467 continue;
3468
3469 radv_handle_subpass_image_transition(cmd_buffer,
3470 subpass->attachments[i]);
3471 }
3472
3473 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3474 radv_cmd_buffer_clear_subpass(cmd_buffer);
3475
3476 assert(cmd_buffer->cs->cdw <= cdw_max);
3477 }
3478
3479 static void
3480 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
3481 {
3482 struct radv_cmd_state *state = &cmd_buffer->state;
3483 const struct radv_subpass *subpass = state->subpass;
3484 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3485
3486 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3487
3488 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3489 const uint32_t a = subpass->attachments[i].attachment;
3490 if (a == VK_ATTACHMENT_UNUSED)
3491 continue;
3492
3493 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
3494 continue;
3495
3496 VkImageLayout layout = state->pass->attachments[a].final_layout;
3497 radv_handle_subpass_image_transition(cmd_buffer,
3498 (struct radv_subpass_attachment){a, layout});
3499 }
3500 }
3501
3502 void radv_CmdBeginRenderPass(
3503 VkCommandBuffer commandBuffer,
3504 const VkRenderPassBeginInfo* pRenderPassBegin,
3505 VkSubpassContents contents)
3506 {
3507 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3508 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3509 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3510 VkResult result;
3511
3512 cmd_buffer->state.framebuffer = framebuffer;
3513 cmd_buffer->state.pass = pass;
3514 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3515
3516 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3517 if (result != VK_SUCCESS)
3518 return;
3519
3520 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
3521 }
3522
3523 void radv_CmdBeginRenderPass2KHR(
3524 VkCommandBuffer commandBuffer,
3525 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3526 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3527 {
3528 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3529 pSubpassBeginInfo->contents);
3530 }
3531
3532 void radv_CmdNextSubpass(
3533 VkCommandBuffer commandBuffer,
3534 VkSubpassContents contents)
3535 {
3536 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3537
3538 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
3539 radv_cmd_buffer_end_subpass(cmd_buffer);
3540 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
3541 }
3542
3543 void radv_CmdNextSubpass2KHR(
3544 VkCommandBuffer commandBuffer,
3545 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3546 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3547 {
3548 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3549 }
3550
3551 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3552 {
3553 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3554 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3555 if (!radv_get_shader(pipeline, stage))
3556 continue;
3557
3558 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3559 if (loc->sgpr_idx == -1)
3560 continue;
3561 uint32_t base_reg = pipeline->user_data_0[stage];
3562 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3563
3564 }
3565 if (pipeline->gs_copy_shader) {
3566 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3567 if (loc->sgpr_idx != -1) {
3568 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3569 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3570 }
3571 }
3572 }
3573
3574 static void
3575 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3576 uint32_t vertex_count,
3577 bool use_opaque)
3578 {
3579 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3580 radeon_emit(cmd_buffer->cs, vertex_count);
3581 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3582 S_0287F0_USE_OPAQUE(use_opaque));
3583 }
3584
3585 static void
3586 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3587 uint64_t index_va,
3588 uint32_t index_count)
3589 {
3590 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3591 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3592 radeon_emit(cmd_buffer->cs, index_va);
3593 radeon_emit(cmd_buffer->cs, index_va >> 32);
3594 radeon_emit(cmd_buffer->cs, index_count);
3595 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3596 }
3597
3598 static void
3599 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3600 bool indexed,
3601 uint32_t draw_count,
3602 uint64_t count_va,
3603 uint32_t stride)
3604 {
3605 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3606 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3607 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3608 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3609 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3610 bool predicating = cmd_buffer->state.predicating;
3611 assert(base_reg);
3612
3613 /* just reset draw state for vertex data */
3614 cmd_buffer->state.last_first_instance = -1;
3615 cmd_buffer->state.last_num_instances = -1;
3616 cmd_buffer->state.last_vertex_offset = -1;
3617
3618 if (draw_count == 1 && !count_va && !draw_id_enable) {
3619 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3620 PKT3_DRAW_INDIRECT, 3, predicating));
3621 radeon_emit(cs, 0);
3622 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3623 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3624 radeon_emit(cs, di_src_sel);
3625 } else {
3626 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3627 PKT3_DRAW_INDIRECT_MULTI,
3628 8, predicating));
3629 radeon_emit(cs, 0);
3630 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3631 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3632 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3633 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3634 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3635 radeon_emit(cs, draw_count); /* count */
3636 radeon_emit(cs, count_va); /* count_addr */
3637 radeon_emit(cs, count_va >> 32);
3638 radeon_emit(cs, stride); /* stride */
3639 radeon_emit(cs, di_src_sel);
3640 }
3641 }
3642
3643 static void
3644 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3645 const struct radv_draw_info *info)
3646 {
3647 struct radv_cmd_state *state = &cmd_buffer->state;
3648 struct radeon_winsys *ws = cmd_buffer->device->ws;
3649 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3650
3651 if (info->indirect) {
3652 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3653 uint64_t count_va = 0;
3654
3655 va += info->indirect->offset + info->indirect_offset;
3656
3657 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3658
3659 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3660 radeon_emit(cs, 1);
3661 radeon_emit(cs, va);
3662 radeon_emit(cs, va >> 32);
3663
3664 if (info->count_buffer) {
3665 count_va = radv_buffer_get_va(info->count_buffer->bo);
3666 count_va += info->count_buffer->offset +
3667 info->count_buffer_offset;
3668
3669 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3670 }
3671
3672 if (!state->subpass->view_mask) {
3673 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3674 info->indexed,
3675 info->count,
3676 count_va,
3677 info->stride);
3678 } else {
3679 unsigned i;
3680 for_each_bit(i, state->subpass->view_mask) {
3681 radv_emit_view_index(cmd_buffer, i);
3682
3683 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3684 info->indexed,
3685 info->count,
3686 count_va,
3687 info->stride);
3688 }
3689 }
3690 } else {
3691 assert(state->pipeline->graphics.vtx_base_sgpr);
3692
3693 if (info->vertex_offset != state->last_vertex_offset ||
3694 info->first_instance != state->last_first_instance) {
3695 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3696 state->pipeline->graphics.vtx_emit_num);
3697
3698 radeon_emit(cs, info->vertex_offset);
3699 radeon_emit(cs, info->first_instance);
3700 if (state->pipeline->graphics.vtx_emit_num == 3)
3701 radeon_emit(cs, 0);
3702 state->last_first_instance = info->first_instance;
3703 state->last_vertex_offset = info->vertex_offset;
3704 }
3705
3706 if (state->last_num_instances != info->instance_count) {
3707 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3708 radeon_emit(cs, info->instance_count);
3709 state->last_num_instances = info->instance_count;
3710 }
3711
3712 if (info->indexed) {
3713 int index_size = state->index_type ? 4 : 2;
3714 uint64_t index_va;
3715
3716 index_va = state->index_va;
3717 index_va += info->first_index * index_size;
3718
3719 if (!state->subpass->view_mask) {
3720 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3721 index_va,
3722 info->count);
3723 } else {
3724 unsigned i;
3725 for_each_bit(i, state->subpass->view_mask) {
3726 radv_emit_view_index(cmd_buffer, i);
3727
3728 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3729 index_va,
3730 info->count);
3731 }
3732 }
3733 } else {
3734 if (!state->subpass->view_mask) {
3735 radv_cs_emit_draw_packet(cmd_buffer,
3736 info->count,
3737 !!info->strmout_buffer);
3738 } else {
3739 unsigned i;
3740 for_each_bit(i, state->subpass->view_mask) {
3741 radv_emit_view_index(cmd_buffer, i);
3742
3743 radv_cs_emit_draw_packet(cmd_buffer,
3744 info->count,
3745 !!info->strmout_buffer);
3746 }
3747 }
3748 }
3749 }
3750 }
3751
3752 /*
3753 * Vega and raven have a bug which triggers if there are multiple context
3754 * register contexts active at the same time with different scissor values.
3755 *
3756 * There are two possible workarounds:
3757 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3758 * there is only ever 1 active set of scissor values at the same time.
3759 *
3760 * 2) Whenever the hardware switches contexts we have to set the scissor
3761 * registers again even if it is a noop. That way the new context gets
3762 * the correct scissor values.
3763 *
3764 * This implements option 2. radv_need_late_scissor_emission needs to
3765 * return true on affected HW if radv_emit_all_graphics_states sets
3766 * any context registers.
3767 */
3768 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3769 const struct radv_draw_info *info)
3770 {
3771 struct radv_cmd_state *state = &cmd_buffer->state;
3772
3773 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3774 return false;
3775
3776 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
3777 return true;
3778
3779 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3780
3781 /* Index, vertex and streamout buffers don't change context regs, and
3782 * pipeline is already handled.
3783 */
3784 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3785 RADV_CMD_DIRTY_VERTEX_BUFFER |
3786 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
3787 RADV_CMD_DIRTY_PIPELINE);
3788
3789 if (cmd_buffer->state.dirty & used_states)
3790 return true;
3791
3792 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
3793 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3794 return true;
3795
3796 return false;
3797 }
3798
3799 static void
3800 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3801 const struct radv_draw_info *info)
3802 {
3803 bool late_scissor_emission;
3804
3805 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3806 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3807 radv_emit_rbplus_state(cmd_buffer);
3808
3809 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3810 radv_emit_graphics_pipeline(cmd_buffer);
3811
3812 /* This should be before the cmd_buffer->state.dirty is cleared
3813 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
3814 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
3815 late_scissor_emission =
3816 radv_need_late_scissor_emission(cmd_buffer, info);
3817
3818 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3819 radv_emit_framebuffer_state(cmd_buffer);
3820
3821 if (info->indexed) {
3822 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3823 radv_emit_index_buffer(cmd_buffer);
3824 } else {
3825 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3826 * so the state must be re-emitted before the next indexed
3827 * draw.
3828 */
3829 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3830 cmd_buffer->state.last_index_type = -1;
3831 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3832 }
3833 }
3834
3835 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3836
3837 radv_emit_draw_registers(cmd_buffer, info);
3838
3839 if (late_scissor_emission)
3840 radv_emit_scissor(cmd_buffer);
3841 }
3842
3843 static void
3844 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3845 const struct radv_draw_info *info)
3846 {
3847 struct radeon_info *rad_info =
3848 &cmd_buffer->device->physical_device->rad_info;
3849 bool has_prefetch =
3850 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3851 bool pipeline_is_dirty =
3852 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3853 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3854
3855 MAYBE_UNUSED unsigned cdw_max =
3856 radeon_check_space(cmd_buffer->device->ws,
3857 cmd_buffer->cs, 4096);
3858
3859 if (likely(!info->indirect)) {
3860 /* SI-CI treat instance_count==0 as instance_count==1. There is
3861 * no workaround for indirect draws, but we can at least skip
3862 * direct draws.
3863 */
3864 if (unlikely(!info->instance_count))
3865 return;
3866
3867 /* Handle count == 0. */
3868 if (unlikely(!info->count && !info->strmout_buffer))
3869 return;
3870 }
3871
3872 /* Use optimal packet order based on whether we need to sync the
3873 * pipeline.
3874 */
3875 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3876 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3877 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3878 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3879 /* If we have to wait for idle, set all states first, so that
3880 * all SET packets are processed in parallel with previous draw
3881 * calls. Then upload descriptors, set shader pointers, and
3882 * draw, and prefetch at the end. This ensures that the time
3883 * the CUs are idle is very short. (there are only SET_SH
3884 * packets between the wait and the draw)
3885 */
3886 radv_emit_all_graphics_states(cmd_buffer, info);
3887 si_emit_cache_flush(cmd_buffer);
3888 /* <-- CUs are idle here --> */
3889
3890 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3891
3892 radv_emit_draw_packets(cmd_buffer, info);
3893 /* <-- CUs are busy here --> */
3894
3895 /* Start prefetches after the draw has been started. Both will
3896 * run in parallel, but starting the draw first is more
3897 * important.
3898 */
3899 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3900 radv_emit_prefetch_L2(cmd_buffer,
3901 cmd_buffer->state.pipeline, false);
3902 }
3903 } else {
3904 /* If we don't wait for idle, start prefetches first, then set
3905 * states, and draw at the end.
3906 */
3907 si_emit_cache_flush(cmd_buffer);
3908
3909 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3910 /* Only prefetch the vertex shader and VBO descriptors
3911 * in order to start the draw as soon as possible.
3912 */
3913 radv_emit_prefetch_L2(cmd_buffer,
3914 cmd_buffer->state.pipeline, true);
3915 }
3916
3917 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3918
3919 radv_emit_all_graphics_states(cmd_buffer, info);
3920 radv_emit_draw_packets(cmd_buffer, info);
3921
3922 /* Prefetch the remaining shaders after the draw has been
3923 * started.
3924 */
3925 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3926 radv_emit_prefetch_L2(cmd_buffer,
3927 cmd_buffer->state.pipeline, false);
3928 }
3929 }
3930
3931 /* Workaround for a VGT hang when streamout is enabled.
3932 * It must be done after drawing.
3933 */
3934 if (cmd_buffer->state.streamout.streamout_enabled &&
3935 (rad_info->family == CHIP_HAWAII ||
3936 rad_info->family == CHIP_TONGA ||
3937 rad_info->family == CHIP_FIJI)) {
3938 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
3939 }
3940
3941 assert(cmd_buffer->cs->cdw <= cdw_max);
3942 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3943 }
3944
3945 void radv_CmdDraw(
3946 VkCommandBuffer commandBuffer,
3947 uint32_t vertexCount,
3948 uint32_t instanceCount,
3949 uint32_t firstVertex,
3950 uint32_t firstInstance)
3951 {
3952 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3953 struct radv_draw_info info = {};
3954
3955 info.count = vertexCount;
3956 info.instance_count = instanceCount;
3957 info.first_instance = firstInstance;
3958 info.vertex_offset = firstVertex;
3959
3960 radv_draw(cmd_buffer, &info);
3961 }
3962
3963 void radv_CmdDrawIndexed(
3964 VkCommandBuffer commandBuffer,
3965 uint32_t indexCount,
3966 uint32_t instanceCount,
3967 uint32_t firstIndex,
3968 int32_t vertexOffset,
3969 uint32_t firstInstance)
3970 {
3971 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3972 struct radv_draw_info info = {};
3973
3974 info.indexed = true;
3975 info.count = indexCount;
3976 info.instance_count = instanceCount;
3977 info.first_index = firstIndex;
3978 info.vertex_offset = vertexOffset;
3979 info.first_instance = firstInstance;
3980
3981 radv_draw(cmd_buffer, &info);
3982 }
3983
3984 void radv_CmdDrawIndirect(
3985 VkCommandBuffer commandBuffer,
3986 VkBuffer _buffer,
3987 VkDeviceSize offset,
3988 uint32_t drawCount,
3989 uint32_t stride)
3990 {
3991 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3992 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3993 struct radv_draw_info info = {};
3994
3995 info.count = drawCount;
3996 info.indirect = buffer;
3997 info.indirect_offset = offset;
3998 info.stride = stride;
3999
4000 radv_draw(cmd_buffer, &info);
4001 }
4002
4003 void radv_CmdDrawIndexedIndirect(
4004 VkCommandBuffer commandBuffer,
4005 VkBuffer _buffer,
4006 VkDeviceSize offset,
4007 uint32_t drawCount,
4008 uint32_t stride)
4009 {
4010 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4011 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4012 struct radv_draw_info info = {};
4013
4014 info.indexed = true;
4015 info.count = drawCount;
4016 info.indirect = buffer;
4017 info.indirect_offset = offset;
4018 info.stride = stride;
4019
4020 radv_draw(cmd_buffer, &info);
4021 }
4022
4023 void radv_CmdDrawIndirectCountAMD(
4024 VkCommandBuffer commandBuffer,
4025 VkBuffer _buffer,
4026 VkDeviceSize offset,
4027 VkBuffer _countBuffer,
4028 VkDeviceSize countBufferOffset,
4029 uint32_t maxDrawCount,
4030 uint32_t stride)
4031 {
4032 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4033 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4034 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4035 struct radv_draw_info info = {};
4036
4037 info.count = maxDrawCount;
4038 info.indirect = buffer;
4039 info.indirect_offset = offset;
4040 info.count_buffer = count_buffer;
4041 info.count_buffer_offset = countBufferOffset;
4042 info.stride = stride;
4043
4044 radv_draw(cmd_buffer, &info);
4045 }
4046
4047 void radv_CmdDrawIndexedIndirectCountAMD(
4048 VkCommandBuffer commandBuffer,
4049 VkBuffer _buffer,
4050 VkDeviceSize offset,
4051 VkBuffer _countBuffer,
4052 VkDeviceSize countBufferOffset,
4053 uint32_t maxDrawCount,
4054 uint32_t stride)
4055 {
4056 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4057 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4058 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4059 struct radv_draw_info info = {};
4060
4061 info.indexed = true;
4062 info.count = maxDrawCount;
4063 info.indirect = buffer;
4064 info.indirect_offset = offset;
4065 info.count_buffer = count_buffer;
4066 info.count_buffer_offset = countBufferOffset;
4067 info.stride = stride;
4068
4069 radv_draw(cmd_buffer, &info);
4070 }
4071
4072 void radv_CmdDrawIndirectCountKHR(
4073 VkCommandBuffer commandBuffer,
4074 VkBuffer _buffer,
4075 VkDeviceSize offset,
4076 VkBuffer _countBuffer,
4077 VkDeviceSize countBufferOffset,
4078 uint32_t maxDrawCount,
4079 uint32_t stride)
4080 {
4081 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4082 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4083 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4084 struct radv_draw_info info = {};
4085
4086 info.count = maxDrawCount;
4087 info.indirect = buffer;
4088 info.indirect_offset = offset;
4089 info.count_buffer = count_buffer;
4090 info.count_buffer_offset = countBufferOffset;
4091 info.stride = stride;
4092
4093 radv_draw(cmd_buffer, &info);
4094 }
4095
4096 void radv_CmdDrawIndexedIndirectCountKHR(
4097 VkCommandBuffer commandBuffer,
4098 VkBuffer _buffer,
4099 VkDeviceSize offset,
4100 VkBuffer _countBuffer,
4101 VkDeviceSize countBufferOffset,
4102 uint32_t maxDrawCount,
4103 uint32_t stride)
4104 {
4105 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4106 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4107 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4108 struct radv_draw_info info = {};
4109
4110 info.indexed = true;
4111 info.count = maxDrawCount;
4112 info.indirect = buffer;
4113 info.indirect_offset = offset;
4114 info.count_buffer = count_buffer;
4115 info.count_buffer_offset = countBufferOffset;
4116 info.stride = stride;
4117
4118 radv_draw(cmd_buffer, &info);
4119 }
4120
4121 struct radv_dispatch_info {
4122 /**
4123 * Determine the layout of the grid (in block units) to be used.
4124 */
4125 uint32_t blocks[3];
4126
4127 /**
4128 * A starting offset for the grid. If unaligned is set, the offset
4129 * must still be aligned.
4130 */
4131 uint32_t offsets[3];
4132 /**
4133 * Whether it's an unaligned compute dispatch.
4134 */
4135 bool unaligned;
4136
4137 /**
4138 * Indirect compute parameters resource.
4139 */
4140 struct radv_buffer *indirect;
4141 uint64_t indirect_offset;
4142 };
4143
4144 static void
4145 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4146 const struct radv_dispatch_info *info)
4147 {
4148 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4149 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4150 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4151 struct radeon_winsys *ws = cmd_buffer->device->ws;
4152 bool predicating = cmd_buffer->state.predicating;
4153 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4154 struct radv_userdata_info *loc;
4155
4156 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4157 AC_UD_CS_GRID_SIZE);
4158
4159 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4160
4161 if (info->indirect) {
4162 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4163
4164 va += info->indirect->offset + info->indirect_offset;
4165
4166 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4167
4168 if (loc->sgpr_idx != -1) {
4169 for (unsigned i = 0; i < 3; ++i) {
4170 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4171 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4172 COPY_DATA_DST_SEL(COPY_DATA_REG));
4173 radeon_emit(cs, (va + 4 * i));
4174 radeon_emit(cs, (va + 4 * i) >> 32);
4175 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4176 + loc->sgpr_idx * 4) >> 2) + i);
4177 radeon_emit(cs, 0);
4178 }
4179 }
4180
4181 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4182 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4183 PKT3_SHADER_TYPE_S(1));
4184 radeon_emit(cs, va);
4185 radeon_emit(cs, va >> 32);
4186 radeon_emit(cs, dispatch_initiator);
4187 } else {
4188 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4189 PKT3_SHADER_TYPE_S(1));
4190 radeon_emit(cs, 1);
4191 radeon_emit(cs, va);
4192 radeon_emit(cs, va >> 32);
4193
4194 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4195 PKT3_SHADER_TYPE_S(1));
4196 radeon_emit(cs, 0);
4197 radeon_emit(cs, dispatch_initiator);
4198 }
4199 } else {
4200 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4201 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4202
4203 if (info->unaligned) {
4204 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4205 unsigned remainder[3];
4206
4207 /* If aligned, these should be an entire block size,
4208 * not 0.
4209 */
4210 remainder[0] = blocks[0] + cs_block_size[0] -
4211 align_u32_npot(blocks[0], cs_block_size[0]);
4212 remainder[1] = blocks[1] + cs_block_size[1] -
4213 align_u32_npot(blocks[1], cs_block_size[1]);
4214 remainder[2] = blocks[2] + cs_block_size[2] -
4215 align_u32_npot(blocks[2], cs_block_size[2]);
4216
4217 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4218 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4219 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4220
4221 for(unsigned i = 0; i < 3; ++i) {
4222 assert(offsets[i] % cs_block_size[i] == 0);
4223 offsets[i] /= cs_block_size[i];
4224 }
4225
4226 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4227 radeon_emit(cs,
4228 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4229 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4230 radeon_emit(cs,
4231 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4232 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4233 radeon_emit(cs,
4234 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4235 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4236
4237 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4238 }
4239
4240 if (loc->sgpr_idx != -1) {
4241 assert(loc->num_sgprs == 3);
4242
4243 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4244 loc->sgpr_idx * 4, 3);
4245 radeon_emit(cs, blocks[0]);
4246 radeon_emit(cs, blocks[1]);
4247 radeon_emit(cs, blocks[2]);
4248 }
4249
4250 if (offsets[0] || offsets[1] || offsets[2]) {
4251 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4252 radeon_emit(cs, offsets[0]);
4253 radeon_emit(cs, offsets[1]);
4254 radeon_emit(cs, offsets[2]);
4255
4256 /* The blocks in the packet are not counts but end values. */
4257 for (unsigned i = 0; i < 3; ++i)
4258 blocks[i] += offsets[i];
4259 } else {
4260 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4261 }
4262
4263 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4264 PKT3_SHADER_TYPE_S(1));
4265 radeon_emit(cs, blocks[0]);
4266 radeon_emit(cs, blocks[1]);
4267 radeon_emit(cs, blocks[2]);
4268 radeon_emit(cs, dispatch_initiator);
4269 }
4270
4271 assert(cmd_buffer->cs->cdw <= cdw_max);
4272 }
4273
4274 static void
4275 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4276 {
4277 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4278 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4279 }
4280
4281 static void
4282 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4283 const struct radv_dispatch_info *info)
4284 {
4285 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4286 bool has_prefetch =
4287 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
4288 bool pipeline_is_dirty = pipeline &&
4289 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4290
4291 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4292 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4293 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4294 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4295 /* If we have to wait for idle, set all states first, so that
4296 * all SET packets are processed in parallel with previous draw
4297 * calls. Then upload descriptors, set shader pointers, and
4298 * dispatch, and prefetch at the end. This ensures that the
4299 * time the CUs are idle is very short. (there are only SET_SH
4300 * packets between the wait and the draw)
4301 */
4302 radv_emit_compute_pipeline(cmd_buffer);
4303 si_emit_cache_flush(cmd_buffer);
4304 /* <-- CUs are idle here --> */
4305
4306 radv_upload_compute_shader_descriptors(cmd_buffer);
4307
4308 radv_emit_dispatch_packets(cmd_buffer, info);
4309 /* <-- CUs are busy here --> */
4310
4311 /* Start prefetches after the dispatch has been started. Both
4312 * will run in parallel, but starting the dispatch first is
4313 * more important.
4314 */
4315 if (has_prefetch && pipeline_is_dirty) {
4316 radv_emit_shader_prefetch(cmd_buffer,
4317 pipeline->shaders[MESA_SHADER_COMPUTE]);
4318 }
4319 } else {
4320 /* If we don't wait for idle, start prefetches first, then set
4321 * states, and dispatch at the end.
4322 */
4323 si_emit_cache_flush(cmd_buffer);
4324
4325 if (has_prefetch && pipeline_is_dirty) {
4326 radv_emit_shader_prefetch(cmd_buffer,
4327 pipeline->shaders[MESA_SHADER_COMPUTE]);
4328 }
4329
4330 radv_upload_compute_shader_descriptors(cmd_buffer);
4331
4332 radv_emit_compute_pipeline(cmd_buffer);
4333 radv_emit_dispatch_packets(cmd_buffer, info);
4334 }
4335
4336 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4337 }
4338
4339 void radv_CmdDispatchBase(
4340 VkCommandBuffer commandBuffer,
4341 uint32_t base_x,
4342 uint32_t base_y,
4343 uint32_t base_z,
4344 uint32_t x,
4345 uint32_t y,
4346 uint32_t z)
4347 {
4348 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4349 struct radv_dispatch_info info = {};
4350
4351 info.blocks[0] = x;
4352 info.blocks[1] = y;
4353 info.blocks[2] = z;
4354
4355 info.offsets[0] = base_x;
4356 info.offsets[1] = base_y;
4357 info.offsets[2] = base_z;
4358 radv_dispatch(cmd_buffer, &info);
4359 }
4360
4361 void radv_CmdDispatch(
4362 VkCommandBuffer commandBuffer,
4363 uint32_t x,
4364 uint32_t y,
4365 uint32_t z)
4366 {
4367 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4368 }
4369
4370 void radv_CmdDispatchIndirect(
4371 VkCommandBuffer commandBuffer,
4372 VkBuffer _buffer,
4373 VkDeviceSize offset)
4374 {
4375 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4376 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4377 struct radv_dispatch_info info = {};
4378
4379 info.indirect = buffer;
4380 info.indirect_offset = offset;
4381
4382 radv_dispatch(cmd_buffer, &info);
4383 }
4384
4385 void radv_unaligned_dispatch(
4386 struct radv_cmd_buffer *cmd_buffer,
4387 uint32_t x,
4388 uint32_t y,
4389 uint32_t z)
4390 {
4391 struct radv_dispatch_info info = {};
4392
4393 info.blocks[0] = x;
4394 info.blocks[1] = y;
4395 info.blocks[2] = z;
4396 info.unaligned = 1;
4397
4398 radv_dispatch(cmd_buffer, &info);
4399 }
4400
4401 void radv_CmdEndRenderPass(
4402 VkCommandBuffer commandBuffer)
4403 {
4404 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4405
4406 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4407
4408 radv_cmd_buffer_end_subpass(cmd_buffer);
4409
4410 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4411
4412 cmd_buffer->state.pass = NULL;
4413 cmd_buffer->state.subpass = NULL;
4414 cmd_buffer->state.attachments = NULL;
4415 cmd_buffer->state.framebuffer = NULL;
4416 }
4417
4418 void radv_CmdEndRenderPass2KHR(
4419 VkCommandBuffer commandBuffer,
4420 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4421 {
4422 radv_CmdEndRenderPass(commandBuffer);
4423 }
4424
4425 /*
4426 * For HTILE we have the following interesting clear words:
4427 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4428 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4429 * 0xfffffff0: Clear depth to 1.0
4430 * 0x00000000: Clear depth to 0.0
4431 */
4432 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4433 struct radv_image *image,
4434 const VkImageSubresourceRange *range,
4435 uint32_t clear_word)
4436 {
4437 assert(range->baseMipLevel == 0);
4438 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4439 unsigned layer_count = radv_get_layerCount(image, range);
4440 uint64_t size = image->planes[0].surface.htile_slice_size * layer_count;
4441 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4442 uint64_t offset = image->offset + image->htile_offset +
4443 image->planes[0].surface.htile_slice_size * range->baseArrayLayer;
4444 struct radv_cmd_state *state = &cmd_buffer->state;
4445 VkClearDepthStencilValue value = {};
4446
4447 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4448 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4449
4450 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4451 size, clear_word);
4452
4453 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4454
4455 if (vk_format_is_stencil(image->vk_format))
4456 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4457
4458 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4459
4460 if (radv_image_is_tc_compat_htile(image)) {
4461 /* Initialize the TC-compat metada value to 0 because by
4462 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4463 * need have to conditionally update its value when performing
4464 * a fast depth clear.
4465 */
4466 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4467 }
4468 }
4469
4470 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4471 struct radv_image *image,
4472 VkImageLayout src_layout,
4473 VkImageLayout dst_layout,
4474 unsigned src_queue_mask,
4475 unsigned dst_queue_mask,
4476 const VkImageSubresourceRange *range)
4477 {
4478 if (!radv_image_has_htile(image))
4479 return;
4480
4481 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4482 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4483
4484 if (radv_layout_is_htile_compressed(image, dst_layout,
4485 dst_queue_mask)) {
4486 clear_value = 0;
4487 }
4488
4489 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4490 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4491 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4492 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4493 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4494 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4495 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4496 VkImageSubresourceRange local_range = *range;
4497 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4498 local_range.baseMipLevel = 0;
4499 local_range.levelCount = 1;
4500
4501 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4502 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4503
4504 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4505
4506 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4507 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4508 }
4509 }
4510
4511 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4512 struct radv_image *image, uint32_t value)
4513 {
4514 struct radv_cmd_state *state = &cmd_buffer->state;
4515
4516 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4517 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4518
4519 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4520
4521 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4522 }
4523
4524 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4525 struct radv_image *image)
4526 {
4527 struct radv_cmd_state *state = &cmd_buffer->state;
4528 static const uint32_t fmask_clear_values[4] = {
4529 0x00000000,
4530 0x02020202,
4531 0xE4E4E4E4,
4532 0x76543210
4533 };
4534 uint32_t log2_samples = util_logbase2(image->info.samples);
4535 uint32_t value = fmask_clear_values[log2_samples];
4536
4537 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4538 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4539
4540 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
4541
4542 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4543 }
4544
4545 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4546 struct radv_image *image, uint32_t value)
4547 {
4548 struct radv_cmd_state *state = &cmd_buffer->state;
4549
4550 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4551 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4552
4553 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4554
4555 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4556 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4557 }
4558
4559 /**
4560 * Initialize DCC/FMASK/CMASK metadata for a color image.
4561 */
4562 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4563 struct radv_image *image,
4564 VkImageLayout src_layout,
4565 VkImageLayout dst_layout,
4566 unsigned src_queue_mask,
4567 unsigned dst_queue_mask)
4568 {
4569 if (radv_image_has_cmask(image)) {
4570 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4571
4572 /* TODO: clarify this. */
4573 if (radv_image_has_fmask(image)) {
4574 value = 0xccccccccu;
4575 }
4576
4577 radv_initialise_cmask(cmd_buffer, image, value);
4578 }
4579
4580 if (radv_image_has_fmask(image)) {
4581 radv_initialize_fmask(cmd_buffer, image);
4582 }
4583
4584 if (radv_image_has_dcc(image)) {
4585 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4586 bool need_decompress_pass = false;
4587
4588 if (radv_layout_dcc_compressed(image, dst_layout,
4589 dst_queue_mask)) {
4590 value = 0x20202020u;
4591 need_decompress_pass = true;
4592 }
4593
4594 radv_initialize_dcc(cmd_buffer, image, value);
4595
4596 radv_update_fce_metadata(cmd_buffer, image,
4597 need_decompress_pass);
4598 }
4599
4600 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4601 uint32_t color_values[2] = {};
4602 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4603 }
4604 }
4605
4606 /**
4607 * Handle color image transitions for DCC/FMASK/CMASK.
4608 */
4609 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4610 struct radv_image *image,
4611 VkImageLayout src_layout,
4612 VkImageLayout dst_layout,
4613 unsigned src_queue_mask,
4614 unsigned dst_queue_mask,
4615 const VkImageSubresourceRange *range)
4616 {
4617 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4618 radv_init_color_image_metadata(cmd_buffer, image,
4619 src_layout, dst_layout,
4620 src_queue_mask, dst_queue_mask);
4621 return;
4622 }
4623
4624 if (radv_image_has_dcc(image)) {
4625 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4626 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4627 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4628 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4629 radv_decompress_dcc(cmd_buffer, image, range);
4630 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4631 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4632 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4633 }
4634 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4635 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4636 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4637 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4638 }
4639
4640 if (radv_image_has_fmask(image)) {
4641 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
4642 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
4643 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
4644 }
4645 }
4646 }
4647 }
4648
4649 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4650 struct radv_image *image,
4651 VkImageLayout src_layout,
4652 VkImageLayout dst_layout,
4653 uint32_t src_family,
4654 uint32_t dst_family,
4655 const VkImageSubresourceRange *range)
4656 {
4657 if (image->exclusive && src_family != dst_family) {
4658 /* This is an acquire or a release operation and there will be
4659 * a corresponding release/acquire. Do the transition in the
4660 * most flexible queue. */
4661
4662 assert(src_family == cmd_buffer->queue_family_index ||
4663 dst_family == cmd_buffer->queue_family_index);
4664
4665 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4666 return;
4667
4668 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4669 (src_family == RADV_QUEUE_GENERAL ||
4670 dst_family == RADV_QUEUE_GENERAL))
4671 return;
4672 }
4673
4674 if (src_layout == dst_layout)
4675 return;
4676
4677 unsigned src_queue_mask =
4678 radv_image_queue_family_mask(image, src_family,
4679 cmd_buffer->queue_family_index);
4680 unsigned dst_queue_mask =
4681 radv_image_queue_family_mask(image, dst_family,
4682 cmd_buffer->queue_family_index);
4683
4684 if (vk_format_is_depth(image->vk_format)) {
4685 radv_handle_depth_image_transition(cmd_buffer, image,
4686 src_layout, dst_layout,
4687 src_queue_mask, dst_queue_mask,
4688 range);
4689 } else {
4690 radv_handle_color_image_transition(cmd_buffer, image,
4691 src_layout, dst_layout,
4692 src_queue_mask, dst_queue_mask,
4693 range);
4694 }
4695 }
4696
4697 struct radv_barrier_info {
4698 uint32_t eventCount;
4699 const VkEvent *pEvents;
4700 VkPipelineStageFlags srcStageMask;
4701 VkPipelineStageFlags dstStageMask;
4702 };
4703
4704 static void
4705 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4706 uint32_t memoryBarrierCount,
4707 const VkMemoryBarrier *pMemoryBarriers,
4708 uint32_t bufferMemoryBarrierCount,
4709 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4710 uint32_t imageMemoryBarrierCount,
4711 const VkImageMemoryBarrier *pImageMemoryBarriers,
4712 const struct radv_barrier_info *info)
4713 {
4714 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4715 enum radv_cmd_flush_bits src_flush_bits = 0;
4716 enum radv_cmd_flush_bits dst_flush_bits = 0;
4717
4718 for (unsigned i = 0; i < info->eventCount; ++i) {
4719 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4720 uint64_t va = radv_buffer_get_va(event->bo);
4721
4722 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4723
4724 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4725
4726 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
4727 assert(cmd_buffer->cs->cdw <= cdw_max);
4728 }
4729
4730 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4731 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4732 NULL);
4733 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4734 NULL);
4735 }
4736
4737 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4738 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4739 NULL);
4740 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4741 NULL);
4742 }
4743
4744 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4745 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4746
4747 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4748 image);
4749 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4750 image);
4751 }
4752
4753 /* The Vulkan spec 1.1.98 says:
4754 *
4755 * "An execution dependency with only
4756 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
4757 * will only prevent that stage from executing in subsequently
4758 * submitted commands. As this stage does not perform any actual
4759 * execution, this is not observable - in effect, it does not delay
4760 * processing of subsequent commands. Similarly an execution dependency
4761 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
4762 * will effectively not wait for any prior commands to complete."
4763 */
4764 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
4765 radv_stage_flush(cmd_buffer, info->srcStageMask);
4766 cmd_buffer->state.flush_bits |= src_flush_bits;
4767
4768 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4769 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4770 radv_handle_image_transition(cmd_buffer, image,
4771 pImageMemoryBarriers[i].oldLayout,
4772 pImageMemoryBarriers[i].newLayout,
4773 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4774 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4775 &pImageMemoryBarriers[i].subresourceRange);
4776 }
4777
4778 /* Make sure CP DMA is idle because the driver might have performed a
4779 * DMA operation for copying or filling buffers/images.
4780 */
4781 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4782 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4783 si_cp_dma_wait_for_idle(cmd_buffer);
4784
4785 cmd_buffer->state.flush_bits |= dst_flush_bits;
4786 }
4787
4788 void radv_CmdPipelineBarrier(
4789 VkCommandBuffer commandBuffer,
4790 VkPipelineStageFlags srcStageMask,
4791 VkPipelineStageFlags destStageMask,
4792 VkBool32 byRegion,
4793 uint32_t memoryBarrierCount,
4794 const VkMemoryBarrier* pMemoryBarriers,
4795 uint32_t bufferMemoryBarrierCount,
4796 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4797 uint32_t imageMemoryBarrierCount,
4798 const VkImageMemoryBarrier* pImageMemoryBarriers)
4799 {
4800 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4801 struct radv_barrier_info info;
4802
4803 info.eventCount = 0;
4804 info.pEvents = NULL;
4805 info.srcStageMask = srcStageMask;
4806 info.dstStageMask = destStageMask;
4807
4808 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4809 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4810 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4811 }
4812
4813
4814 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4815 struct radv_event *event,
4816 VkPipelineStageFlags stageMask,
4817 unsigned value)
4818 {
4819 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4820 uint64_t va = radv_buffer_get_va(event->bo);
4821
4822 si_emit_cache_flush(cmd_buffer);
4823
4824 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4825
4826 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4827
4828 /* Flags that only require a top-of-pipe event. */
4829 VkPipelineStageFlags top_of_pipe_flags =
4830 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4831
4832 /* Flags that only require a post-index-fetch event. */
4833 VkPipelineStageFlags post_index_fetch_flags =
4834 top_of_pipe_flags |
4835 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4836 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4837
4838 /* Make sure CP DMA is idle because the driver might have performed a
4839 * DMA operation for copying or filling buffers/images.
4840 */
4841 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4842 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4843 si_cp_dma_wait_for_idle(cmd_buffer);
4844
4845 /* TODO: Emit EOS events for syncing PS/CS stages. */
4846
4847 if (!(stageMask & ~top_of_pipe_flags)) {
4848 /* Just need to sync the PFP engine. */
4849 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4850 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4851 S_370_WR_CONFIRM(1) |
4852 S_370_ENGINE_SEL(V_370_PFP));
4853 radeon_emit(cs, va);
4854 radeon_emit(cs, va >> 32);
4855 radeon_emit(cs, value);
4856 } else if (!(stageMask & ~post_index_fetch_flags)) {
4857 /* Sync ME because PFP reads index and indirect buffers. */
4858 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4859 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4860 S_370_WR_CONFIRM(1) |
4861 S_370_ENGINE_SEL(V_370_ME));
4862 radeon_emit(cs, va);
4863 radeon_emit(cs, va >> 32);
4864 radeon_emit(cs, value);
4865 } else {
4866 /* Otherwise, sync all prior GPU work using an EOP event. */
4867 si_cs_emit_write_event_eop(cs,
4868 cmd_buffer->device->physical_device->rad_info.chip_class,
4869 radv_cmd_buffer_uses_mec(cmd_buffer),
4870 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4871 EOP_DATA_SEL_VALUE_32BIT, va, value,
4872 cmd_buffer->gfx9_eop_bug_va);
4873 }
4874
4875 assert(cmd_buffer->cs->cdw <= cdw_max);
4876 }
4877
4878 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4879 VkEvent _event,
4880 VkPipelineStageFlags stageMask)
4881 {
4882 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4883 RADV_FROM_HANDLE(radv_event, event, _event);
4884
4885 write_event(cmd_buffer, event, stageMask, 1);
4886 }
4887
4888 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4889 VkEvent _event,
4890 VkPipelineStageFlags stageMask)
4891 {
4892 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4893 RADV_FROM_HANDLE(radv_event, event, _event);
4894
4895 write_event(cmd_buffer, event, stageMask, 0);
4896 }
4897
4898 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4899 uint32_t eventCount,
4900 const VkEvent* pEvents,
4901 VkPipelineStageFlags srcStageMask,
4902 VkPipelineStageFlags dstStageMask,
4903 uint32_t memoryBarrierCount,
4904 const VkMemoryBarrier* pMemoryBarriers,
4905 uint32_t bufferMemoryBarrierCount,
4906 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4907 uint32_t imageMemoryBarrierCount,
4908 const VkImageMemoryBarrier* pImageMemoryBarriers)
4909 {
4910 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4911 struct radv_barrier_info info;
4912
4913 info.eventCount = eventCount;
4914 info.pEvents = pEvents;
4915 info.srcStageMask = 0;
4916
4917 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4918 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4919 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4920 }
4921
4922
4923 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4924 uint32_t deviceMask)
4925 {
4926 /* No-op */
4927 }
4928
4929 /* VK_EXT_conditional_rendering */
4930 void radv_CmdBeginConditionalRenderingEXT(
4931 VkCommandBuffer commandBuffer,
4932 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4933 {
4934 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4935 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4936 bool draw_visible = true;
4937 uint64_t va;
4938
4939 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4940
4941 /* By default, if the 32-bit value at offset in buffer memory is zero,
4942 * then the rendering commands are discarded, otherwise they are
4943 * executed as normal. If the inverted flag is set, all commands are
4944 * discarded if the value is non zero.
4945 */
4946 if (pConditionalRenderingBegin->flags &
4947 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4948 draw_visible = false;
4949 }
4950
4951 si_emit_cache_flush(cmd_buffer);
4952
4953 /* Enable predication for this command buffer. */
4954 si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4955 cmd_buffer->state.predicating = true;
4956
4957 /* Store conditional rendering user info. */
4958 cmd_buffer->state.predication_type = draw_visible;
4959 cmd_buffer->state.predication_va = va;
4960 }
4961
4962 void radv_CmdEndConditionalRenderingEXT(
4963 VkCommandBuffer commandBuffer)
4964 {
4965 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4966
4967 /* Disable predication for this command buffer. */
4968 si_emit_set_predication_state(cmd_buffer, false, 0);
4969 cmd_buffer->state.predicating = false;
4970
4971 /* Reset conditional rendering user info. */
4972 cmd_buffer->state.predication_type = -1;
4973 cmd_buffer->state.predication_va = 0;
4974 }
4975
4976 /* VK_EXT_transform_feedback */
4977 void radv_CmdBindTransformFeedbackBuffersEXT(
4978 VkCommandBuffer commandBuffer,
4979 uint32_t firstBinding,
4980 uint32_t bindingCount,
4981 const VkBuffer* pBuffers,
4982 const VkDeviceSize* pOffsets,
4983 const VkDeviceSize* pSizes)
4984 {
4985 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4986 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4987 uint8_t enabled_mask = 0;
4988
4989 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
4990 for (uint32_t i = 0; i < bindingCount; i++) {
4991 uint32_t idx = firstBinding + i;
4992
4993 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
4994 sb[idx].offset = pOffsets[i];
4995 sb[idx].size = pSizes[i];
4996
4997 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4998 sb[idx].buffer->bo);
4999
5000 enabled_mask |= 1 << idx;
5001 }
5002
5003 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5004
5005 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5006 }
5007
5008 static void
5009 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5010 {
5011 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5012 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5013
5014 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5015 radeon_emit(cs,
5016 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5017 S_028B94_RAST_STREAM(0) |
5018 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5019 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5020 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5021 radeon_emit(cs, so->hw_enabled_mask &
5022 so->enabled_stream_buffers_mask);
5023
5024 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5025 }
5026
5027 static void
5028 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5029 {
5030 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5031 bool old_streamout_enabled = so->streamout_enabled;
5032 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5033
5034 so->streamout_enabled = enable;
5035
5036 so->hw_enabled_mask = so->enabled_mask |
5037 (so->enabled_mask << 4) |
5038 (so->enabled_mask << 8) |
5039 (so->enabled_mask << 12);
5040
5041 if ((old_streamout_enabled != so->streamout_enabled) ||
5042 (old_hw_enabled_mask != so->hw_enabled_mask))
5043 radv_emit_streamout_enable(cmd_buffer);
5044 }
5045
5046 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5047 {
5048 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5049 unsigned reg_strmout_cntl;
5050
5051 /* The register is at different places on different ASICs. */
5052 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
5053 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5054 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5055 } else {
5056 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5057 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5058 }
5059
5060 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5061 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5062
5063 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5064 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5065 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5066 radeon_emit(cs, 0);
5067 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5068 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5069 radeon_emit(cs, 4); /* poll interval */
5070 }
5071
5072 void radv_CmdBeginTransformFeedbackEXT(
5073 VkCommandBuffer commandBuffer,
5074 uint32_t firstCounterBuffer,
5075 uint32_t counterBufferCount,
5076 const VkBuffer* pCounterBuffers,
5077 const VkDeviceSize* pCounterBufferOffsets)
5078 {
5079 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5080 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5081 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5082 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5083 uint32_t i;
5084
5085 radv_flush_vgt_streamout(cmd_buffer);
5086
5087 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5088 for_each_bit(i, so->enabled_mask) {
5089 int32_t counter_buffer_idx = i - firstCounterBuffer;
5090 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5091 counter_buffer_idx = -1;
5092
5093 /* SI binds streamout buffers as shader resources.
5094 * VGT only counts primitives and tells the shader through
5095 * SGPRs what to do.
5096 */
5097 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5098 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5099 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5100
5101 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5102
5103 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5104 /* The array of counter buffers is optional. */
5105 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5106 uint64_t va = radv_buffer_get_va(buffer->bo);
5107
5108 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5109
5110 /* Append */
5111 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5112 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5113 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5114 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5115 radeon_emit(cs, 0); /* unused */
5116 radeon_emit(cs, 0); /* unused */
5117 radeon_emit(cs, va); /* src address lo */
5118 radeon_emit(cs, va >> 32); /* src address hi */
5119
5120 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5121 } else {
5122 /* Start from the beginning. */
5123 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5124 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5125 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5126 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5127 radeon_emit(cs, 0); /* unused */
5128 radeon_emit(cs, 0); /* unused */
5129 radeon_emit(cs, 0); /* unused */
5130 radeon_emit(cs, 0); /* unused */
5131 }
5132 }
5133
5134 radv_set_streamout_enable(cmd_buffer, true);
5135 }
5136
5137 void radv_CmdEndTransformFeedbackEXT(
5138 VkCommandBuffer commandBuffer,
5139 uint32_t firstCounterBuffer,
5140 uint32_t counterBufferCount,
5141 const VkBuffer* pCounterBuffers,
5142 const VkDeviceSize* pCounterBufferOffsets)
5143 {
5144 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5145 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5146 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5147 uint32_t i;
5148
5149 radv_flush_vgt_streamout(cmd_buffer);
5150
5151 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5152 for_each_bit(i, so->enabled_mask) {
5153 int32_t counter_buffer_idx = i - firstCounterBuffer;
5154 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5155 counter_buffer_idx = -1;
5156
5157 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5158 /* The array of counters buffer is optional. */
5159 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5160 uint64_t va = radv_buffer_get_va(buffer->bo);
5161
5162 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5163
5164 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5165 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5166 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5167 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5168 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5169 radeon_emit(cs, va); /* dst address lo */
5170 radeon_emit(cs, va >> 32); /* dst address hi */
5171 radeon_emit(cs, 0); /* unused */
5172 radeon_emit(cs, 0); /* unused */
5173
5174 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5175 }
5176
5177 /* Deactivate transform feedback by zeroing the buffer size.
5178 * The counters (primitives generated, primitives emitted) may
5179 * be enabled even if there is not buffer bound. This ensures
5180 * that the primitives-emitted query won't increment.
5181 */
5182 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5183
5184 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5185 }
5186
5187 radv_set_streamout_enable(cmd_buffer, false);
5188 }
5189
5190 void radv_CmdDrawIndirectByteCountEXT(
5191 VkCommandBuffer commandBuffer,
5192 uint32_t instanceCount,
5193 uint32_t firstInstance,
5194 VkBuffer _counterBuffer,
5195 VkDeviceSize counterBufferOffset,
5196 uint32_t counterOffset,
5197 uint32_t vertexStride)
5198 {
5199 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5200 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5201 struct radv_draw_info info = {};
5202
5203 info.instance_count = instanceCount;
5204 info.first_instance = firstInstance;
5205 info.strmout_buffer = counterBuffer;
5206 info.strmout_buffer_offset = counterBufferOffset;
5207 info.stride = vertexStride;
5208
5209 radv_draw(cmd_buffer, &info);
5210 }