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radv: Do not set SX DISABLE bits for RB+ with unused surfaces.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 };
96
97 static void
98 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
99 const struct radv_dynamic_state *src)
100 {
101 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
102 uint32_t copy_mask = src->mask;
103 uint32_t dest_mask = 0;
104
105 /* Make sure to copy the number of viewports/scissors because they can
106 * only be specified at pipeline creation time.
107 */
108 dest->viewport.count = src->viewport.count;
109 dest->scissor.count = src->scissor.count;
110 dest->discard_rectangle.count = src->discard_rectangle.count;
111 dest->sample_location.count = src->sample_location.count;
112
113 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
114 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
115 src->viewport.count * sizeof(VkViewport))) {
116 typed_memcpy(dest->viewport.viewports,
117 src->viewport.viewports,
118 src->viewport.count);
119 dest_mask |= RADV_DYNAMIC_VIEWPORT;
120 }
121 }
122
123 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
124 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
125 src->scissor.count * sizeof(VkRect2D))) {
126 typed_memcpy(dest->scissor.scissors,
127 src->scissor.scissors, src->scissor.count);
128 dest_mask |= RADV_DYNAMIC_SCISSOR;
129 }
130 }
131
132 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
133 if (dest->line_width != src->line_width) {
134 dest->line_width = src->line_width;
135 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
136 }
137 }
138
139 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
140 if (memcmp(&dest->depth_bias, &src->depth_bias,
141 sizeof(src->depth_bias))) {
142 dest->depth_bias = src->depth_bias;
143 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
144 }
145 }
146
147 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
148 if (memcmp(&dest->blend_constants, &src->blend_constants,
149 sizeof(src->blend_constants))) {
150 typed_memcpy(dest->blend_constants,
151 src->blend_constants, 4);
152 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
153 }
154 }
155
156 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
157 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
158 sizeof(src->depth_bounds))) {
159 dest->depth_bounds = src->depth_bounds;
160 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
161 }
162 }
163
164 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
165 if (memcmp(&dest->stencil_compare_mask,
166 &src->stencil_compare_mask,
167 sizeof(src->stencil_compare_mask))) {
168 dest->stencil_compare_mask = src->stencil_compare_mask;
169 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
170 }
171 }
172
173 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
174 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
175 sizeof(src->stencil_write_mask))) {
176 dest->stencil_write_mask = src->stencil_write_mask;
177 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
178 }
179 }
180
181 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
182 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
183 sizeof(src->stencil_reference))) {
184 dest->stencil_reference = src->stencil_reference;
185 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
186 }
187 }
188
189 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
190 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
191 src->discard_rectangle.count * sizeof(VkRect2D))) {
192 typed_memcpy(dest->discard_rectangle.rectangles,
193 src->discard_rectangle.rectangles,
194 src->discard_rectangle.count);
195 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
196 }
197 }
198
199 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
200 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
201 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
202 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
203 memcmp(&dest->sample_location.locations,
204 &src->sample_location.locations,
205 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
206 dest->sample_location.per_pixel = src->sample_location.per_pixel;
207 dest->sample_location.grid_size = src->sample_location.grid_size;
208 typed_memcpy(dest->sample_location.locations,
209 src->sample_location.locations,
210 src->sample_location.count);
211 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
212 }
213 }
214
215 cmd_buffer->state.dirty |= dest_mask;
216 }
217
218 static void
219 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
220 struct radv_pipeline *pipeline)
221 {
222 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
223 struct radv_shader_info *info;
224
225 if (!pipeline->streamout_shader ||
226 cmd_buffer->device->physical_device->use_ngg_streamout)
227 return;
228
229 info = &pipeline->streamout_shader->info;
230 for (int i = 0; i < MAX_SO_BUFFERS; i++)
231 so->stride_in_dw[i] = info->so.strides[i];
232
233 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
234 }
235
236 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
237 {
238 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
239 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
240 }
241
242 enum ring_type radv_queue_family_to_ring(int f) {
243 switch (f) {
244 case RADV_QUEUE_GENERAL:
245 return RING_GFX;
246 case RADV_QUEUE_COMPUTE:
247 return RING_COMPUTE;
248 case RADV_QUEUE_TRANSFER:
249 return RING_DMA;
250 default:
251 unreachable("Unknown queue family");
252 }
253 }
254
255 static VkResult radv_create_cmd_buffer(
256 struct radv_device * device,
257 struct radv_cmd_pool * pool,
258 VkCommandBufferLevel level,
259 VkCommandBuffer* pCommandBuffer)
260 {
261 struct radv_cmd_buffer *cmd_buffer;
262 unsigned ring;
263 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
264 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
265 if (cmd_buffer == NULL)
266 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
267
268 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
269 cmd_buffer->device = device;
270 cmd_buffer->pool = pool;
271 cmd_buffer->level = level;
272
273 if (pool) {
274 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
275 cmd_buffer->queue_family_index = pool->queue_family_index;
276
277 } else {
278 /* Init the pool_link so we can safely call list_del when we destroy
279 * the command buffer
280 */
281 list_inithead(&cmd_buffer->pool_link);
282 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
283 }
284
285 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
286
287 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
288 if (!cmd_buffer->cs) {
289 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
290 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
291 }
292
293 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
294
295 list_inithead(&cmd_buffer->upload.list);
296
297 return VK_SUCCESS;
298 }
299
300 static void
301 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
302 {
303 list_del(&cmd_buffer->pool_link);
304
305 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
306 &cmd_buffer->upload.list, list) {
307 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
308 list_del(&up->list);
309 free(up);
310 }
311
312 if (cmd_buffer->upload.upload_bo)
313 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
314 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
315
316 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
317 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
318
319 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
320 }
321
322 static VkResult
323 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
324 {
325 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
326
327 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
328 &cmd_buffer->upload.list, list) {
329 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
330 list_del(&up->list);
331 free(up);
332 }
333
334 cmd_buffer->push_constant_stages = 0;
335 cmd_buffer->scratch_size_per_wave_needed = 0;
336 cmd_buffer->scratch_waves_wanted = 0;
337 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
338 cmd_buffer->compute_scratch_waves_wanted = 0;
339 cmd_buffer->esgs_ring_size_needed = 0;
340 cmd_buffer->gsvs_ring_size_needed = 0;
341 cmd_buffer->tess_rings_needed = false;
342 cmd_buffer->gds_needed = false;
343 cmd_buffer->gds_oa_needed = false;
344 cmd_buffer->sample_positions_needed = false;
345
346 if (cmd_buffer->upload.upload_bo)
347 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
348 cmd_buffer->upload.upload_bo);
349 cmd_buffer->upload.offset = 0;
350
351 cmd_buffer->record_result = VK_SUCCESS;
352
353 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
354
355 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
356 cmd_buffer->descriptors[i].dirty = 0;
357 cmd_buffer->descriptors[i].valid = 0;
358 cmd_buffer->descriptors[i].push_dirty = false;
359 }
360
361 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
362 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
363 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
364 unsigned fence_offset, eop_bug_offset;
365 void *fence_ptr;
366
367 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
368 &fence_ptr);
369
370 cmd_buffer->gfx9_fence_va =
371 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
372 cmd_buffer->gfx9_fence_va += fence_offset;
373
374 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
375 /* Allocate a buffer for the EOP bug on GFX9. */
376 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
377 &eop_bug_offset, &fence_ptr);
378 cmd_buffer->gfx9_eop_bug_va =
379 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
380 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
381 }
382 }
383
384 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
385
386 return cmd_buffer->record_result;
387 }
388
389 static bool
390 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
391 uint64_t min_needed)
392 {
393 uint64_t new_size;
394 struct radeon_winsys_bo *bo;
395 struct radv_cmd_buffer_upload *upload;
396 struct radv_device *device = cmd_buffer->device;
397
398 new_size = MAX2(min_needed, 16 * 1024);
399 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
400
401 bo = device->ws->buffer_create(device->ws,
402 new_size, 4096,
403 RADEON_DOMAIN_GTT,
404 RADEON_FLAG_CPU_ACCESS|
405 RADEON_FLAG_NO_INTERPROCESS_SHARING |
406 RADEON_FLAG_32BIT,
407 RADV_BO_PRIORITY_UPLOAD_BUFFER);
408
409 if (!bo) {
410 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
411 return false;
412 }
413
414 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
415 if (cmd_buffer->upload.upload_bo) {
416 upload = malloc(sizeof(*upload));
417
418 if (!upload) {
419 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
420 device->ws->buffer_destroy(bo);
421 return false;
422 }
423
424 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
425 list_add(&upload->list, &cmd_buffer->upload.list);
426 }
427
428 cmd_buffer->upload.upload_bo = bo;
429 cmd_buffer->upload.size = new_size;
430 cmd_buffer->upload.offset = 0;
431 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
432
433 if (!cmd_buffer->upload.map) {
434 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
435 return false;
436 }
437
438 return true;
439 }
440
441 bool
442 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
443 unsigned size,
444 unsigned alignment,
445 unsigned *out_offset,
446 void **ptr)
447 {
448 assert(util_is_power_of_two_nonzero(alignment));
449
450 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
451 if (offset + size > cmd_buffer->upload.size) {
452 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
453 return false;
454 offset = 0;
455 }
456
457 *out_offset = offset;
458 *ptr = cmd_buffer->upload.map + offset;
459
460 cmd_buffer->upload.offset = offset + size;
461 return true;
462 }
463
464 bool
465 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
466 unsigned size, unsigned alignment,
467 const void *data, unsigned *out_offset)
468 {
469 uint8_t *ptr;
470
471 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
472 out_offset, (void **)&ptr))
473 return false;
474
475 if (ptr)
476 memcpy(ptr, data, size);
477
478 return true;
479 }
480
481 static void
482 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
483 unsigned count, const uint32_t *data)
484 {
485 struct radeon_cmdbuf *cs = cmd_buffer->cs;
486
487 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
488
489 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
490 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
491 S_370_WR_CONFIRM(1) |
492 S_370_ENGINE_SEL(V_370_ME));
493 radeon_emit(cs, va);
494 radeon_emit(cs, va >> 32);
495 radeon_emit_array(cs, data, count);
496 }
497
498 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
499 {
500 struct radv_device *device = cmd_buffer->device;
501 struct radeon_cmdbuf *cs = cmd_buffer->cs;
502 uint64_t va;
503
504 va = radv_buffer_get_va(device->trace_bo);
505 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
506 va += 4;
507
508 ++cmd_buffer->state.trace_id;
509 radv_emit_write_data_packet(cmd_buffer, va, 1,
510 &cmd_buffer->state.trace_id);
511
512 radeon_check_space(cmd_buffer->device->ws, cs, 2);
513
514 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
515 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
516 }
517
518 static void
519 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
520 enum radv_cmd_flush_bits flags)
521 {
522 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
523 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
524 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
525
526 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
527
528 /* Force wait for graphics or compute engines to be idle. */
529 si_cs_emit_cache_flush(cmd_buffer->cs,
530 cmd_buffer->device->physical_device->rad_info.chip_class,
531 &cmd_buffer->gfx9_fence_idx,
532 cmd_buffer->gfx9_fence_va,
533 radv_cmd_buffer_uses_mec(cmd_buffer),
534 flags, cmd_buffer->gfx9_eop_bug_va);
535 }
536
537 if (unlikely(cmd_buffer->device->trace_bo))
538 radv_cmd_buffer_trace_emit(cmd_buffer);
539 }
540
541 static void
542 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
543 struct radv_pipeline *pipeline, enum ring_type ring)
544 {
545 struct radv_device *device = cmd_buffer->device;
546 uint32_t data[2];
547 uint64_t va;
548
549 va = radv_buffer_get_va(device->trace_bo);
550
551 switch (ring) {
552 case RING_GFX:
553 va += 8;
554 break;
555 case RING_COMPUTE:
556 va += 16;
557 break;
558 default:
559 assert(!"invalid ring type");
560 }
561
562 uint64_t pipeline_address = (uintptr_t)pipeline;
563 data[0] = pipeline_address;
564 data[1] = pipeline_address >> 32;
565
566 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
567 }
568
569 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
570 VkPipelineBindPoint bind_point,
571 struct radv_descriptor_set *set,
572 unsigned idx)
573 {
574 struct radv_descriptor_state *descriptors_state =
575 radv_get_descriptors_state(cmd_buffer, bind_point);
576
577 descriptors_state->sets[idx] = set;
578
579 descriptors_state->valid |= (1u << idx); /* active descriptors */
580 descriptors_state->dirty |= (1u << idx);
581 }
582
583 static void
584 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
585 VkPipelineBindPoint bind_point)
586 {
587 struct radv_descriptor_state *descriptors_state =
588 radv_get_descriptors_state(cmd_buffer, bind_point);
589 struct radv_device *device = cmd_buffer->device;
590 uint32_t data[MAX_SETS * 2] = {};
591 uint64_t va;
592 unsigned i;
593 va = radv_buffer_get_va(device->trace_bo) + 24;
594
595 for_each_bit(i, descriptors_state->valid) {
596 struct radv_descriptor_set *set = descriptors_state->sets[i];
597 data[i * 2] = (uint64_t)(uintptr_t)set;
598 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
599 }
600
601 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
602 }
603
604 struct radv_userdata_info *
605 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
606 gl_shader_stage stage,
607 int idx)
608 {
609 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
610 return &shader->info.user_sgprs_locs.shader_data[idx];
611 }
612
613 static void
614 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
615 struct radv_pipeline *pipeline,
616 gl_shader_stage stage,
617 int idx, uint64_t va)
618 {
619 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
620 uint32_t base_reg = pipeline->user_data_0[stage];
621 if (loc->sgpr_idx == -1)
622 return;
623
624 assert(loc->num_sgprs == 1);
625
626 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
627 base_reg + loc->sgpr_idx * 4, va, false);
628 }
629
630 static void
631 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
632 struct radv_pipeline *pipeline,
633 struct radv_descriptor_state *descriptors_state,
634 gl_shader_stage stage)
635 {
636 struct radv_device *device = cmd_buffer->device;
637 struct radeon_cmdbuf *cs = cmd_buffer->cs;
638 uint32_t sh_base = pipeline->user_data_0[stage];
639 struct radv_userdata_locations *locs =
640 &pipeline->shaders[stage]->info.user_sgprs_locs;
641 unsigned mask = locs->descriptor_sets_enabled;
642
643 mask &= descriptors_state->dirty & descriptors_state->valid;
644
645 while (mask) {
646 int start, count;
647
648 u_bit_scan_consecutive_range(&mask, &start, &count);
649
650 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
651 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
652
653 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
654 for (int i = 0; i < count; i++) {
655 struct radv_descriptor_set *set =
656 descriptors_state->sets[start + i];
657
658 radv_emit_shader_pointer_body(device, cs, set->va, true);
659 }
660 }
661 }
662
663 /**
664 * Convert the user sample locations to hardware sample locations (the values
665 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
666 */
667 static void
668 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
669 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
670 {
671 uint32_t x_offset = x % state->grid_size.width;
672 uint32_t y_offset = y % state->grid_size.height;
673 uint32_t num_samples = (uint32_t)state->per_pixel;
674 VkSampleLocationEXT *user_locs;
675 uint32_t pixel_offset;
676
677 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
678
679 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
680 user_locs = &state->locations[pixel_offset];
681
682 for (uint32_t i = 0; i < num_samples; i++) {
683 float shifted_pos_x = user_locs[i].x - 0.5;
684 float shifted_pos_y = user_locs[i].y - 0.5;
685
686 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
687 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
688
689 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
690 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
691 }
692 }
693
694 /**
695 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
696 * locations.
697 */
698 static void
699 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
700 uint32_t *sample_locs_pixel)
701 {
702 for (uint32_t i = 0; i < num_samples; i++) {
703 uint32_t sample_reg_idx = i / 4;
704 uint32_t sample_loc_idx = i % 4;
705 int32_t pos_x = sample_locs[i].x;
706 int32_t pos_y = sample_locs[i].y;
707
708 uint32_t shift_x = 8 * sample_loc_idx;
709 uint32_t shift_y = shift_x + 4;
710
711 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
712 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
713 }
714 }
715
716 /**
717 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
718 * sample locations.
719 */
720 static uint64_t
721 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
722 VkOffset2D *sample_locs,
723 uint32_t num_samples)
724 {
725 uint32_t centroid_priorities[num_samples];
726 uint32_t sample_mask = num_samples - 1;
727 uint32_t distances[num_samples];
728 uint64_t centroid_priority = 0;
729
730 /* Compute the distances from center for each sample. */
731 for (int i = 0; i < num_samples; i++) {
732 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
733 (sample_locs[i].y * sample_locs[i].y);
734 }
735
736 /* Compute the centroid priorities by looking at the distances array. */
737 for (int i = 0; i < num_samples; i++) {
738 uint32_t min_idx = 0;
739
740 for (int j = 1; j < num_samples; j++) {
741 if (distances[j] < distances[min_idx])
742 min_idx = j;
743 }
744
745 centroid_priorities[i] = min_idx;
746 distances[min_idx] = 0xffffffff;
747 }
748
749 /* Compute the final centroid priority. */
750 for (int i = 0; i < 8; i++) {
751 centroid_priority |=
752 centroid_priorities[i & sample_mask] << (i * 4);
753 }
754
755 return centroid_priority << 32 | centroid_priority;
756 }
757
758 /**
759 * Emit the sample locations that are specified with VK_EXT_sample_locations.
760 */
761 static void
762 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
763 {
764 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
765 struct radv_multisample_state *ms = &pipeline->graphics.ms;
766 struct radv_sample_locations_state *sample_location =
767 &cmd_buffer->state.dynamic.sample_location;
768 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
769 struct radeon_cmdbuf *cs = cmd_buffer->cs;
770 uint32_t sample_locs_pixel[4][2] = {};
771 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
772 uint32_t max_sample_dist = 0;
773 uint64_t centroid_priority;
774
775 if (!cmd_buffer->state.dynamic.sample_location.count)
776 return;
777
778 /* Convert the user sample locations to hardware sample locations. */
779 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
780 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
781 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
782 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
783
784 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
785 for (uint32_t i = 0; i < 4; i++) {
786 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
787 sample_locs_pixel[i]);
788 }
789
790 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
791 centroid_priority =
792 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
793 num_samples);
794
795 /* Compute the maximum sample distance from the specified locations. */
796 for (uint32_t i = 0; i < num_samples; i++) {
797 VkOffset2D offset = sample_locs[0][i];
798 max_sample_dist = MAX2(max_sample_dist,
799 MAX2(abs(offset.x), abs(offset.y)));
800 }
801
802 /* Emit the specified user sample locations. */
803 switch (num_samples) {
804 case 2:
805 case 4:
806 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
807 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
808 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
809 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
810 break;
811 case 8:
812 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
813 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
814 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
815 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
816 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
817 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
818 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
819 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
820 break;
821 default:
822 unreachable("invalid number of samples");
823 }
824
825 /* Emit the maximum sample distance and the centroid priority. */
826 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
827
828 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
829 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
830
831 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
832 radeon_emit(cs, pa_sc_aa_config);
833
834 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
835 radeon_emit(cs, centroid_priority);
836 radeon_emit(cs, centroid_priority >> 32);
837
838 /* GFX9: Flush DFSM when the AA mode changes. */
839 if (cmd_buffer->device->dfsm_allowed) {
840 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
841 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
842 }
843
844 cmd_buffer->state.context_roll_without_scissor_emitted = true;
845 }
846
847 static void
848 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
849 struct radv_pipeline *pipeline,
850 gl_shader_stage stage,
851 int idx, int count, uint32_t *values)
852 {
853 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
854 uint32_t base_reg = pipeline->user_data_0[stage];
855 if (loc->sgpr_idx == -1)
856 return;
857
858 assert(loc->num_sgprs == count);
859
860 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
861 radeon_emit_array(cmd_buffer->cs, values, count);
862 }
863
864 static void
865 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
866 struct radv_pipeline *pipeline)
867 {
868 int num_samples = pipeline->graphics.ms.num_samples;
869 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
870
871 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
872 cmd_buffer->sample_positions_needed = true;
873
874 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
875 return;
876
877 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
878
879 cmd_buffer->state.context_roll_without_scissor_emitted = true;
880 }
881
882 static void
883 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
884 struct radv_pipeline *pipeline)
885 {
886 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
887
888
889 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
890 return;
891
892 if (old_pipeline &&
893 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
894 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
895 return;
896
897 bool binning_flush = false;
898 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
899 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
900 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
901 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
902 binning_flush = !old_pipeline ||
903 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
904 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
905 }
906
907 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
908 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
909 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
910
911 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
912 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
913 pipeline->graphics.binning.db_dfsm_control);
914 } else {
915 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
916 pipeline->graphics.binning.db_dfsm_control);
917 }
918
919 cmd_buffer->state.context_roll_without_scissor_emitted = true;
920 }
921
922
923 static void
924 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
925 struct radv_shader_variant *shader)
926 {
927 uint64_t va;
928
929 if (!shader)
930 return;
931
932 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
933
934 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
935 }
936
937 static void
938 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
939 struct radv_pipeline *pipeline,
940 bool vertex_stage_only)
941 {
942 struct radv_cmd_state *state = &cmd_buffer->state;
943 uint32_t mask = state->prefetch_L2_mask;
944
945 if (vertex_stage_only) {
946 /* Fast prefetch path for starting draws as soon as possible.
947 */
948 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
949 RADV_PREFETCH_VBO_DESCRIPTORS);
950 }
951
952 if (mask & RADV_PREFETCH_VS)
953 radv_emit_shader_prefetch(cmd_buffer,
954 pipeline->shaders[MESA_SHADER_VERTEX]);
955
956 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
957 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
958
959 if (mask & RADV_PREFETCH_TCS)
960 radv_emit_shader_prefetch(cmd_buffer,
961 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
962
963 if (mask & RADV_PREFETCH_TES)
964 radv_emit_shader_prefetch(cmd_buffer,
965 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
966
967 if (mask & RADV_PREFETCH_GS) {
968 radv_emit_shader_prefetch(cmd_buffer,
969 pipeline->shaders[MESA_SHADER_GEOMETRY]);
970 if (radv_pipeline_has_gs_copy_shader(pipeline))
971 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
972 }
973
974 if (mask & RADV_PREFETCH_PS)
975 radv_emit_shader_prefetch(cmd_buffer,
976 pipeline->shaders[MESA_SHADER_FRAGMENT]);
977
978 state->prefetch_L2_mask &= ~mask;
979 }
980
981 static void
982 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
983 {
984 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
985 return;
986
987 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
988 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
989
990 unsigned sx_ps_downconvert = 0;
991 unsigned sx_blend_opt_epsilon = 0;
992 unsigned sx_blend_opt_control = 0;
993
994 if (!cmd_buffer->state.attachments || !subpass)
995 return;
996
997 for (unsigned i = 0; i < subpass->color_count; ++i) {
998 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
999 /* We don't set the DISABLE bits, because the HW can't have holes,
1000 * so the SPI color format is set to 32-bit 1-component. */
1001 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1002 continue;
1003 }
1004
1005 int idx = subpass->color_attachments[i].attachment;
1006 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1007
1008 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1009 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1010 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1011 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1012
1013 bool has_alpha, has_rgb;
1014
1015 /* Set if RGB and A are present. */
1016 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1017
1018 if (format == V_028C70_COLOR_8 ||
1019 format == V_028C70_COLOR_16 ||
1020 format == V_028C70_COLOR_32)
1021 has_rgb = !has_alpha;
1022 else
1023 has_rgb = true;
1024
1025 /* Check the colormask and export format. */
1026 if (!(colormask & 0x7))
1027 has_rgb = false;
1028 if (!(colormask & 0x8))
1029 has_alpha = false;
1030
1031 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1032 has_rgb = false;
1033 has_alpha = false;
1034 }
1035
1036 /* Disable value checking for disabled channels. */
1037 if (!has_rgb)
1038 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1039 if (!has_alpha)
1040 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1041
1042 /* Enable down-conversion for 32bpp and smaller formats. */
1043 switch (format) {
1044 case V_028C70_COLOR_8:
1045 case V_028C70_COLOR_8_8:
1046 case V_028C70_COLOR_8_8_8_8:
1047 /* For 1 and 2-channel formats, use the superset thereof. */
1048 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1049 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1050 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1051 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1052 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1053 }
1054 break;
1055
1056 case V_028C70_COLOR_5_6_5:
1057 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1058 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1059 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1060 }
1061 break;
1062
1063 case V_028C70_COLOR_1_5_5_5:
1064 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1065 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1066 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1067 }
1068 break;
1069
1070 case V_028C70_COLOR_4_4_4_4:
1071 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1072 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1073 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1074 }
1075 break;
1076
1077 case V_028C70_COLOR_32:
1078 if (swap == V_028C70_SWAP_STD &&
1079 spi_format == V_028714_SPI_SHADER_32_R)
1080 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1081 else if (swap == V_028C70_SWAP_ALT_REV &&
1082 spi_format == V_028714_SPI_SHADER_32_AR)
1083 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1084 break;
1085
1086 case V_028C70_COLOR_16:
1087 case V_028C70_COLOR_16_16:
1088 /* For 1-channel formats, use the superset thereof. */
1089 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1090 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1091 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1092 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1093 if (swap == V_028C70_SWAP_STD ||
1094 swap == V_028C70_SWAP_STD_REV)
1095 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1096 else
1097 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1098 }
1099 break;
1100
1101 case V_028C70_COLOR_10_11_11:
1102 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1103 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1104 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1105 }
1106 break;
1107
1108 case V_028C70_COLOR_2_10_10_10:
1109 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1110 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1111 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1112 }
1113 break;
1114 }
1115 }
1116
1117 /* Do not set the DISABLE bits for the unused attachments, as that
1118 * breaks dual source blending in SkQP and does not seem to improve
1119 * performance. */
1120
1121 /* TODO: avoid redundantly setting context registers */
1122 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1123 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1124 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1125 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1126
1127 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1128 }
1129
1130 static void
1131 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1132 {
1133 if (!cmd_buffer->device->pbb_allowed)
1134 return;
1135
1136 struct radv_binning_settings settings =
1137 radv_get_binning_settings(cmd_buffer->device->physical_device);
1138 bool break_for_new_ps =
1139 (!cmd_buffer->state.emitted_pipeline ||
1140 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1141 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1142 (settings.context_states_per_bin > 1 ||
1143 settings.persistent_states_per_bin > 1);
1144 bool break_for_new_cb_target_mask =
1145 (!cmd_buffer->state.emitted_pipeline ||
1146 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1147 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1148 settings.context_states_per_bin > 1;
1149
1150 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1151 return;
1152
1153 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1154 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1155 }
1156
1157 static void
1158 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1159 {
1160 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1161
1162 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1163 return;
1164
1165 radv_update_multisample_state(cmd_buffer, pipeline);
1166 radv_update_binning_state(cmd_buffer, pipeline);
1167
1168 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1169 pipeline->scratch_bytes_per_wave);
1170 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1171 pipeline->max_waves);
1172
1173 if (!cmd_buffer->state.emitted_pipeline ||
1174 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1175 pipeline->graphics.can_use_guardband)
1176 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1177
1178 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1179
1180 if (!cmd_buffer->state.emitted_pipeline ||
1181 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1182 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1183 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1184 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1185 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1186 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1187 }
1188
1189 radv_emit_batch_break_on_new_ps(cmd_buffer);
1190
1191 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1192 if (!pipeline->shaders[i])
1193 continue;
1194
1195 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1196 pipeline->shaders[i]->bo);
1197 }
1198
1199 if (radv_pipeline_has_gs_copy_shader(pipeline))
1200 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1201 pipeline->gs_copy_shader->bo);
1202
1203 if (unlikely(cmd_buffer->device->trace_bo))
1204 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1205
1206 cmd_buffer->state.emitted_pipeline = pipeline;
1207
1208 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1209 }
1210
1211 static void
1212 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1213 {
1214 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1215 cmd_buffer->state.dynamic.viewport.viewports);
1216 }
1217
1218 static void
1219 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1220 {
1221 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1222
1223 si_write_scissors(cmd_buffer->cs, 0, count,
1224 cmd_buffer->state.dynamic.scissor.scissors,
1225 cmd_buffer->state.dynamic.viewport.viewports,
1226 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1227
1228 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1229 }
1230
1231 static void
1232 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1233 {
1234 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1235 return;
1236
1237 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1238 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1239 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1240 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1241 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1242 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1243 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1244 }
1245 }
1246
1247 static void
1248 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1249 {
1250 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1251
1252 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1253 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1254 }
1255
1256 static void
1257 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1258 {
1259 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1260
1261 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1262 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1263 }
1264
1265 static void
1266 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1267 {
1268 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1269
1270 radeon_set_context_reg_seq(cmd_buffer->cs,
1271 R_028430_DB_STENCILREFMASK, 2);
1272 radeon_emit(cmd_buffer->cs,
1273 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1274 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1275 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1276 S_028430_STENCILOPVAL(1));
1277 radeon_emit(cmd_buffer->cs,
1278 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1279 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1280 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1281 S_028434_STENCILOPVAL_BF(1));
1282 }
1283
1284 static void
1285 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1286 {
1287 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1288
1289 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1290 fui(d->depth_bounds.min));
1291 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1292 fui(d->depth_bounds.max));
1293 }
1294
1295 static void
1296 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1297 {
1298 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1299 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1300 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1301
1302
1303 radeon_set_context_reg_seq(cmd_buffer->cs,
1304 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1305 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1306 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1307 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1308 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1309 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1310 }
1311
1312 static void
1313 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1314 int index,
1315 struct radv_color_buffer_info *cb,
1316 struct radv_image_view *iview,
1317 VkImageLayout layout,
1318 bool in_render_loop)
1319 {
1320 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1321 uint32_t cb_color_info = cb->cb_color_info;
1322 struct radv_image *image = iview->image;
1323
1324 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1325 radv_image_queue_family_mask(image,
1326 cmd_buffer->queue_family_index,
1327 cmd_buffer->queue_family_index))) {
1328 cb_color_info &= C_028C70_DCC_ENABLE;
1329 }
1330
1331 if (radv_image_is_tc_compat_cmask(image) &&
1332 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1333 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1334 /* If this bit is set, the FMASK decompression operation
1335 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1336 */
1337 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1338 }
1339
1340 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1341 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1342 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1343 radeon_emit(cmd_buffer->cs, 0);
1344 radeon_emit(cmd_buffer->cs, 0);
1345 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1346 radeon_emit(cmd_buffer->cs, cb_color_info);
1347 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1348 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1349 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1350 radeon_emit(cmd_buffer->cs, 0);
1351 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1352 radeon_emit(cmd_buffer->cs, 0);
1353
1354 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1355 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1356
1357 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1358 cb->cb_color_base >> 32);
1359 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1360 cb->cb_color_cmask >> 32);
1361 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1362 cb->cb_color_fmask >> 32);
1363 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1364 cb->cb_dcc_base >> 32);
1365 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1366 cb->cb_color_attrib2);
1367 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1368 cb->cb_color_attrib3);
1369 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1370 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1371 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1372 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1373 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1374 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1375 radeon_emit(cmd_buffer->cs, cb_color_info);
1376 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1377 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1378 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1379 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1380 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1381 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1382
1383 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1384 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1385 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1386
1387 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1388 cb->cb_mrt_epitch);
1389 } else {
1390 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1391 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1392 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1393 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1394 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1395 radeon_emit(cmd_buffer->cs, cb_color_info);
1396 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1397 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1398 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1399 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1400 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1401 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1402
1403 if (is_vi) { /* DCC BASE */
1404 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1405 }
1406 }
1407
1408 if (radv_dcc_enabled(image, iview->base_mip)) {
1409 /* Drawing with DCC enabled also compresses colorbuffers. */
1410 VkImageSubresourceRange range = {
1411 .aspectMask = iview->aspect_mask,
1412 .baseMipLevel = iview->base_mip,
1413 .levelCount = iview->level_count,
1414 .baseArrayLayer = iview->base_layer,
1415 .layerCount = iview->layer_count,
1416 };
1417
1418 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1419 }
1420 }
1421
1422 static void
1423 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1424 struct radv_ds_buffer_info *ds,
1425 const struct radv_image_view *iview,
1426 VkImageLayout layout,
1427 bool in_render_loop, bool requires_cond_exec)
1428 {
1429 const struct radv_image *image = iview->image;
1430 uint32_t db_z_info = ds->db_z_info;
1431 uint32_t db_z_info_reg;
1432
1433 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1434 !radv_image_is_tc_compat_htile(image))
1435 return;
1436
1437 if (!radv_layout_has_htile(image, layout, in_render_loop,
1438 radv_image_queue_family_mask(image,
1439 cmd_buffer->queue_family_index,
1440 cmd_buffer->queue_family_index))) {
1441 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1442 }
1443
1444 db_z_info &= C_028040_ZRANGE_PRECISION;
1445
1446 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1447 db_z_info_reg = R_028038_DB_Z_INFO;
1448 } else {
1449 db_z_info_reg = R_028040_DB_Z_INFO;
1450 }
1451
1452 /* When we don't know the last fast clear value we need to emit a
1453 * conditional packet that will eventually skip the following
1454 * SET_CONTEXT_REG packet.
1455 */
1456 if (requires_cond_exec) {
1457 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1458
1459 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1460 radeon_emit(cmd_buffer->cs, va);
1461 radeon_emit(cmd_buffer->cs, va >> 32);
1462 radeon_emit(cmd_buffer->cs, 0);
1463 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1464 }
1465
1466 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1467 }
1468
1469 static void
1470 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1471 struct radv_ds_buffer_info *ds,
1472 struct radv_image_view *iview,
1473 VkImageLayout layout,
1474 bool in_render_loop)
1475 {
1476 const struct radv_image *image = iview->image;
1477 uint32_t db_z_info = ds->db_z_info;
1478 uint32_t db_stencil_info = ds->db_stencil_info;
1479
1480 if (!radv_layout_has_htile(image, layout, in_render_loop,
1481 radv_image_queue_family_mask(image,
1482 cmd_buffer->queue_family_index,
1483 cmd_buffer->queue_family_index))) {
1484 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1485 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1486 }
1487
1488 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1489 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1490
1491 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1492 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1493 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1494
1495 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1496 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1497 radeon_emit(cmd_buffer->cs, db_z_info);
1498 radeon_emit(cmd_buffer->cs, db_stencil_info);
1499 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1500 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1501 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1502 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1503
1504 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1505 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1506 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1507 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1508 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1509 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1510 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1511 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1512 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1513 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1514 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1515
1516 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1517 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1518 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1519 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1520 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1521 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1522 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1523 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1524 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1525 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1526 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1527
1528 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1529 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1530 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1531 } else {
1532 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1533
1534 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1535 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1536 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1537 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1538 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1539 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1540 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1541 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1542 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1543 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1544
1545 }
1546
1547 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1548 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1549 in_render_loop, true);
1550
1551 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1552 ds->pa_su_poly_offset_db_fmt_cntl);
1553 }
1554
1555 /**
1556 * Update the fast clear depth/stencil values if the image is bound as a
1557 * depth/stencil buffer.
1558 */
1559 static void
1560 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1561 const struct radv_image_view *iview,
1562 VkClearDepthStencilValue ds_clear_value,
1563 VkImageAspectFlags aspects)
1564 {
1565 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1566 const struct radv_image *image = iview->image;
1567 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1568 uint32_t att_idx;
1569
1570 if (!cmd_buffer->state.attachments || !subpass)
1571 return;
1572
1573 if (!subpass->depth_stencil_attachment)
1574 return;
1575
1576 att_idx = subpass->depth_stencil_attachment->attachment;
1577 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1578 return;
1579
1580 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1581 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1582 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1583 radeon_emit(cs, ds_clear_value.stencil);
1584 radeon_emit(cs, fui(ds_clear_value.depth));
1585 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1586 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1587 radeon_emit(cs, fui(ds_clear_value.depth));
1588 } else {
1589 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1590 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1591 radeon_emit(cs, ds_clear_value.stencil);
1592 }
1593
1594 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1595 * only needed when clearing Z to 0.0.
1596 */
1597 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1598 ds_clear_value.depth == 0.0) {
1599 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1600 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1601
1602 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1603 iview, layout, in_render_loop, false);
1604 }
1605
1606 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1607 }
1608
1609 /**
1610 * Set the clear depth/stencil values to the image's metadata.
1611 */
1612 static void
1613 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1614 struct radv_image *image,
1615 const VkImageSubresourceRange *range,
1616 VkClearDepthStencilValue ds_clear_value,
1617 VkImageAspectFlags aspects)
1618 {
1619 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1620 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1621 uint32_t level_count = radv_get_levelCount(image, range);
1622
1623 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1624 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1625 /* Use the fastest way when both aspects are used. */
1626 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1627 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1628 S_370_WR_CONFIRM(1) |
1629 S_370_ENGINE_SEL(V_370_PFP));
1630 radeon_emit(cs, va);
1631 radeon_emit(cs, va >> 32);
1632
1633 for (uint32_t l = 0; l < level_count; l++) {
1634 radeon_emit(cs, ds_clear_value.stencil);
1635 radeon_emit(cs, fui(ds_clear_value.depth));
1636 }
1637 } else {
1638 /* Otherwise we need one WRITE_DATA packet per level. */
1639 for (uint32_t l = 0; l < level_count; l++) {
1640 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1641 unsigned value;
1642
1643 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1644 value = fui(ds_clear_value.depth);
1645 va += 4;
1646 } else {
1647 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1648 value = ds_clear_value.stencil;
1649 }
1650
1651 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1652 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1653 S_370_WR_CONFIRM(1) |
1654 S_370_ENGINE_SEL(V_370_PFP));
1655 radeon_emit(cs, va);
1656 radeon_emit(cs, va >> 32);
1657 radeon_emit(cs, value);
1658 }
1659 }
1660 }
1661
1662 /**
1663 * Update the TC-compat metadata value for this image.
1664 */
1665 static void
1666 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1667 struct radv_image *image,
1668 const VkImageSubresourceRange *range,
1669 uint32_t value)
1670 {
1671 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1672
1673 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1674 return;
1675
1676 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1677 uint32_t level_count = radv_get_levelCount(image, range);
1678
1679 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1680 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1681 S_370_WR_CONFIRM(1) |
1682 S_370_ENGINE_SEL(V_370_PFP));
1683 radeon_emit(cs, va);
1684 radeon_emit(cs, va >> 32);
1685
1686 for (uint32_t l = 0; l < level_count; l++)
1687 radeon_emit(cs, value);
1688 }
1689
1690 static void
1691 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1692 const struct radv_image_view *iview,
1693 VkClearDepthStencilValue ds_clear_value)
1694 {
1695 VkImageSubresourceRange range = {
1696 .aspectMask = iview->aspect_mask,
1697 .baseMipLevel = iview->base_mip,
1698 .levelCount = iview->level_count,
1699 .baseArrayLayer = iview->base_layer,
1700 .layerCount = iview->layer_count,
1701 };
1702 uint32_t cond_val;
1703
1704 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1705 * depth clear value is 0.0f.
1706 */
1707 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1708
1709 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1710 cond_val);
1711 }
1712
1713 /**
1714 * Update the clear depth/stencil values for this image.
1715 */
1716 void
1717 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1718 const struct radv_image_view *iview,
1719 VkClearDepthStencilValue ds_clear_value,
1720 VkImageAspectFlags aspects)
1721 {
1722 VkImageSubresourceRange range = {
1723 .aspectMask = iview->aspect_mask,
1724 .baseMipLevel = iview->base_mip,
1725 .levelCount = iview->level_count,
1726 .baseArrayLayer = iview->base_layer,
1727 .layerCount = iview->layer_count,
1728 };
1729 struct radv_image *image = iview->image;
1730
1731 assert(radv_image_has_htile(image));
1732
1733 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1734 ds_clear_value, aspects);
1735
1736 if (radv_image_is_tc_compat_htile(image) &&
1737 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1738 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1739 ds_clear_value);
1740 }
1741
1742 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1743 aspects);
1744 }
1745
1746 /**
1747 * Load the clear depth/stencil values from the image's metadata.
1748 */
1749 static void
1750 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1751 const struct radv_image_view *iview)
1752 {
1753 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1754 const struct radv_image *image = iview->image;
1755 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1756 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1757 unsigned reg_offset = 0, reg_count = 0;
1758
1759 if (!radv_image_has_htile(image))
1760 return;
1761
1762 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1763 ++reg_count;
1764 } else {
1765 ++reg_offset;
1766 va += 4;
1767 }
1768 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1769 ++reg_count;
1770
1771 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1772
1773 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1774 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1775 radeon_emit(cs, va);
1776 radeon_emit(cs, va >> 32);
1777 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1778 radeon_emit(cs, reg_count);
1779 } else {
1780 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1781 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1782 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1783 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1784 radeon_emit(cs, va);
1785 radeon_emit(cs, va >> 32);
1786 radeon_emit(cs, reg >> 2);
1787 radeon_emit(cs, 0);
1788
1789 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1790 radeon_emit(cs, 0);
1791 }
1792 }
1793
1794 /*
1795 * With DCC some colors don't require CMASK elimination before being
1796 * used as a texture. This sets a predicate value to determine if the
1797 * cmask eliminate is required.
1798 */
1799 void
1800 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1801 struct radv_image *image,
1802 const VkImageSubresourceRange *range, bool value)
1803 {
1804 uint64_t pred_val = value;
1805 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1806 uint32_t level_count = radv_get_levelCount(image, range);
1807 uint32_t count = 2 * level_count;
1808
1809 assert(radv_dcc_enabled(image, range->baseMipLevel));
1810
1811 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1812 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1813 S_370_WR_CONFIRM(1) |
1814 S_370_ENGINE_SEL(V_370_PFP));
1815 radeon_emit(cmd_buffer->cs, va);
1816 radeon_emit(cmd_buffer->cs, va >> 32);
1817
1818 for (uint32_t l = 0; l < level_count; l++) {
1819 radeon_emit(cmd_buffer->cs, pred_val);
1820 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1821 }
1822 }
1823
1824 /**
1825 * Update the DCC predicate to reflect the compression state.
1826 */
1827 void
1828 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1829 struct radv_image *image,
1830 const VkImageSubresourceRange *range, bool value)
1831 {
1832 uint64_t pred_val = value;
1833 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1834 uint32_t level_count = radv_get_levelCount(image, range);
1835 uint32_t count = 2 * level_count;
1836
1837 assert(radv_dcc_enabled(image, range->baseMipLevel));
1838
1839 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1840 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1841 S_370_WR_CONFIRM(1) |
1842 S_370_ENGINE_SEL(V_370_PFP));
1843 radeon_emit(cmd_buffer->cs, va);
1844 radeon_emit(cmd_buffer->cs, va >> 32);
1845
1846 for (uint32_t l = 0; l < level_count; l++) {
1847 radeon_emit(cmd_buffer->cs, pred_val);
1848 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1849 }
1850 }
1851
1852 /**
1853 * Update the fast clear color values if the image is bound as a color buffer.
1854 */
1855 static void
1856 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1857 struct radv_image *image,
1858 int cb_idx,
1859 uint32_t color_values[2])
1860 {
1861 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1862 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1863 uint32_t att_idx;
1864
1865 if (!cmd_buffer->state.attachments || !subpass)
1866 return;
1867
1868 att_idx = subpass->color_attachments[cb_idx].attachment;
1869 if (att_idx == VK_ATTACHMENT_UNUSED)
1870 return;
1871
1872 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1873 return;
1874
1875 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1876 radeon_emit(cs, color_values[0]);
1877 radeon_emit(cs, color_values[1]);
1878
1879 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1880 }
1881
1882 /**
1883 * Set the clear color values to the image's metadata.
1884 */
1885 static void
1886 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1887 struct radv_image *image,
1888 const VkImageSubresourceRange *range,
1889 uint32_t color_values[2])
1890 {
1891 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1892 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1893 uint32_t level_count = radv_get_levelCount(image, range);
1894 uint32_t count = 2 * level_count;
1895
1896 assert(radv_image_has_cmask(image) ||
1897 radv_dcc_enabled(image, range->baseMipLevel));
1898
1899 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1900 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1901 S_370_WR_CONFIRM(1) |
1902 S_370_ENGINE_SEL(V_370_PFP));
1903 radeon_emit(cs, va);
1904 radeon_emit(cs, va >> 32);
1905
1906 for (uint32_t l = 0; l < level_count; l++) {
1907 radeon_emit(cs, color_values[0]);
1908 radeon_emit(cs, color_values[1]);
1909 }
1910 }
1911
1912 /**
1913 * Update the clear color values for this image.
1914 */
1915 void
1916 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1917 const struct radv_image_view *iview,
1918 int cb_idx,
1919 uint32_t color_values[2])
1920 {
1921 struct radv_image *image = iview->image;
1922 VkImageSubresourceRange range = {
1923 .aspectMask = iview->aspect_mask,
1924 .baseMipLevel = iview->base_mip,
1925 .levelCount = iview->level_count,
1926 .baseArrayLayer = iview->base_layer,
1927 .layerCount = iview->layer_count,
1928 };
1929
1930 assert(radv_image_has_cmask(image) ||
1931 radv_dcc_enabled(image, iview->base_mip));
1932
1933 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1934
1935 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1936 color_values);
1937 }
1938
1939 /**
1940 * Load the clear color values from the image's metadata.
1941 */
1942 static void
1943 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1944 struct radv_image_view *iview,
1945 int cb_idx)
1946 {
1947 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1948 struct radv_image *image = iview->image;
1949 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1950
1951 if (!radv_image_has_cmask(image) &&
1952 !radv_dcc_enabled(image, iview->base_mip))
1953 return;
1954
1955 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1956
1957 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1958 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1959 radeon_emit(cs, va);
1960 radeon_emit(cs, va >> 32);
1961 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1962 radeon_emit(cs, 2);
1963 } else {
1964 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1965 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1966 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1967 COPY_DATA_COUNT_SEL);
1968 radeon_emit(cs, va);
1969 radeon_emit(cs, va >> 32);
1970 radeon_emit(cs, reg >> 2);
1971 radeon_emit(cs, 0);
1972
1973 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1974 radeon_emit(cs, 0);
1975 }
1976 }
1977
1978 static void
1979 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1980 {
1981 int i;
1982 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1983 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1984
1985 /* this may happen for inherited secondary recording */
1986 if (!framebuffer)
1987 return;
1988
1989 for (i = 0; i < 8; ++i) {
1990 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1991 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1992 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1993 continue;
1994 }
1995
1996 int idx = subpass->color_attachments[i].attachment;
1997 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
1998 VkImageLayout layout = subpass->color_attachments[i].layout;
1999 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2000
2001 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2002
2003 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2004 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2005 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2006
2007 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2008 }
2009
2010 if (subpass->depth_stencil_attachment) {
2011 int idx = subpass->depth_stencil_attachment->attachment;
2012 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2013 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2014 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2015 struct radv_image *image = iview->image;
2016 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2017 ASSERTED uint32_t queue_mask = radv_image_queue_family_mask(image,
2018 cmd_buffer->queue_family_index,
2019 cmd_buffer->queue_family_index);
2020 /* We currently don't support writing decompressed HTILE */
2021 assert(radv_layout_has_htile(image, layout, in_render_loop, queue_mask) ==
2022 radv_layout_is_htile_compressed(image, layout, in_render_loop, queue_mask));
2023
2024 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2025
2026 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2027 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2028 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2029 }
2030 radv_load_ds_clear_metadata(cmd_buffer, iview);
2031 } else {
2032 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2033 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2034 else
2035 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2036
2037 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2038 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2039 }
2040 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2041 S_028208_BR_X(framebuffer->width) |
2042 S_028208_BR_Y(framebuffer->height));
2043
2044 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2045 bool disable_constant_encode =
2046 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2047 enum chip_class chip_class =
2048 cmd_buffer->device->physical_device->rad_info.chip_class;
2049 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2050
2051 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2052 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2053 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2054 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2055 }
2056
2057 if (cmd_buffer->device->dfsm_allowed) {
2058 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2059 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2060 }
2061
2062 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2063 }
2064
2065 static void
2066 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
2067 {
2068 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2069 struct radv_cmd_state *state = &cmd_buffer->state;
2070
2071 if (state->index_type != state->last_index_type) {
2072 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2073 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2074 cs, R_03090C_VGT_INDEX_TYPE,
2075 2, state->index_type);
2076 } else {
2077 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2078 radeon_emit(cs, state->index_type);
2079 }
2080
2081 state->last_index_type = state->index_type;
2082 }
2083
2084 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2085 radeon_emit(cs, state->index_va);
2086 radeon_emit(cs, state->index_va >> 32);
2087
2088 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2089 radeon_emit(cs, state->max_index_count);
2090
2091 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2092 }
2093
2094 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2095 {
2096 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2097 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2098 uint32_t pa_sc_mode_cntl_1 =
2099 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2100 uint32_t db_count_control;
2101
2102 if(!cmd_buffer->state.active_occlusion_queries) {
2103 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2104 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2105 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2106 has_perfect_queries) {
2107 /* Re-enable out-of-order rasterization if the
2108 * bound pipeline supports it and if it's has
2109 * been disabled before starting any perfect
2110 * occlusion queries.
2111 */
2112 radeon_set_context_reg(cmd_buffer->cs,
2113 R_028A4C_PA_SC_MODE_CNTL_1,
2114 pa_sc_mode_cntl_1);
2115 }
2116 }
2117 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2118 } else {
2119 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2120 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2121 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2122
2123 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2124 db_count_control =
2125 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2126 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2127 S_028004_SAMPLE_RATE(sample_rate) |
2128 S_028004_ZPASS_ENABLE(1) |
2129 S_028004_SLICE_EVEN_ENABLE(1) |
2130 S_028004_SLICE_ODD_ENABLE(1);
2131
2132 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2133 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2134 has_perfect_queries) {
2135 /* If the bound pipeline has enabled
2136 * out-of-order rasterization, we should
2137 * disable it before starting any perfect
2138 * occlusion queries.
2139 */
2140 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2141
2142 radeon_set_context_reg(cmd_buffer->cs,
2143 R_028A4C_PA_SC_MODE_CNTL_1,
2144 pa_sc_mode_cntl_1);
2145 }
2146 } else {
2147 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2148 S_028004_SAMPLE_RATE(sample_rate);
2149 }
2150 }
2151
2152 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2153
2154 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2155 }
2156
2157 static void
2158 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2159 {
2160 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2161
2162 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2163 radv_emit_viewport(cmd_buffer);
2164
2165 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2166 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2167 radv_emit_scissor(cmd_buffer);
2168
2169 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2170 radv_emit_line_width(cmd_buffer);
2171
2172 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2173 radv_emit_blend_constants(cmd_buffer);
2174
2175 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2176 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2177 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2178 radv_emit_stencil(cmd_buffer);
2179
2180 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2181 radv_emit_depth_bounds(cmd_buffer);
2182
2183 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2184 radv_emit_depth_bias(cmd_buffer);
2185
2186 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2187 radv_emit_discard_rectangle(cmd_buffer);
2188
2189 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2190 radv_emit_sample_locations(cmd_buffer);
2191
2192 cmd_buffer->state.dirty &= ~states;
2193 }
2194
2195 static void
2196 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2197 VkPipelineBindPoint bind_point)
2198 {
2199 struct radv_descriptor_state *descriptors_state =
2200 radv_get_descriptors_state(cmd_buffer, bind_point);
2201 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2202 unsigned bo_offset;
2203
2204 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2205 set->mapped_ptr,
2206 &bo_offset))
2207 return;
2208
2209 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2210 set->va += bo_offset;
2211 }
2212
2213 static void
2214 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2215 VkPipelineBindPoint bind_point)
2216 {
2217 struct radv_descriptor_state *descriptors_state =
2218 radv_get_descriptors_state(cmd_buffer, bind_point);
2219 uint32_t size = MAX_SETS * 4;
2220 uint32_t offset;
2221 void *ptr;
2222
2223 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2224 256, &offset, &ptr))
2225 return;
2226
2227 for (unsigned i = 0; i < MAX_SETS; i++) {
2228 uint32_t *uptr = ((uint32_t *)ptr) + i;
2229 uint64_t set_va = 0;
2230 struct radv_descriptor_set *set = descriptors_state->sets[i];
2231 if (descriptors_state->valid & (1u << i))
2232 set_va = set->va;
2233 uptr[0] = set_va & 0xffffffff;
2234 }
2235
2236 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2237 va += offset;
2238
2239 if (cmd_buffer->state.pipeline) {
2240 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2241 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2242 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2243
2244 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2245 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2246 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2247
2248 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2249 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2250 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2251
2252 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2253 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2254 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2255
2256 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2257 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2258 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2259 }
2260
2261 if (cmd_buffer->state.compute_pipeline)
2262 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2263 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2264 }
2265
2266 static void
2267 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2268 VkShaderStageFlags stages)
2269 {
2270 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2271 VK_PIPELINE_BIND_POINT_COMPUTE :
2272 VK_PIPELINE_BIND_POINT_GRAPHICS;
2273 struct radv_descriptor_state *descriptors_state =
2274 radv_get_descriptors_state(cmd_buffer, bind_point);
2275 struct radv_cmd_state *state = &cmd_buffer->state;
2276 bool flush_indirect_descriptors;
2277
2278 if (!descriptors_state->dirty)
2279 return;
2280
2281 if (descriptors_state->push_dirty)
2282 radv_flush_push_descriptors(cmd_buffer, bind_point);
2283
2284 flush_indirect_descriptors =
2285 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2286 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2287 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2288 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2289
2290 if (flush_indirect_descriptors)
2291 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2292
2293 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2294 cmd_buffer->cs,
2295 MAX_SETS * MESA_SHADER_STAGES * 4);
2296
2297 if (cmd_buffer->state.pipeline) {
2298 radv_foreach_stage(stage, stages) {
2299 if (!cmd_buffer->state.pipeline->shaders[stage])
2300 continue;
2301
2302 radv_emit_descriptor_pointers(cmd_buffer,
2303 cmd_buffer->state.pipeline,
2304 descriptors_state, stage);
2305 }
2306 }
2307
2308 if (cmd_buffer->state.compute_pipeline &&
2309 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2310 radv_emit_descriptor_pointers(cmd_buffer,
2311 cmd_buffer->state.compute_pipeline,
2312 descriptors_state,
2313 MESA_SHADER_COMPUTE);
2314 }
2315
2316 descriptors_state->dirty = 0;
2317 descriptors_state->push_dirty = false;
2318
2319 assert(cmd_buffer->cs->cdw <= cdw_max);
2320
2321 if (unlikely(cmd_buffer->device->trace_bo))
2322 radv_save_descriptors(cmd_buffer, bind_point);
2323 }
2324
2325 static void
2326 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2327 VkShaderStageFlags stages)
2328 {
2329 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2330 ? cmd_buffer->state.compute_pipeline
2331 : cmd_buffer->state.pipeline;
2332 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2333 VK_PIPELINE_BIND_POINT_COMPUTE :
2334 VK_PIPELINE_BIND_POINT_GRAPHICS;
2335 struct radv_descriptor_state *descriptors_state =
2336 radv_get_descriptors_state(cmd_buffer, bind_point);
2337 struct radv_pipeline_layout *layout = pipeline->layout;
2338 struct radv_shader_variant *shader, *prev_shader;
2339 bool need_push_constants = false;
2340 unsigned offset;
2341 void *ptr;
2342 uint64_t va;
2343
2344 stages &= cmd_buffer->push_constant_stages;
2345 if (!stages ||
2346 (!layout->push_constant_size && !layout->dynamic_offset_count))
2347 return;
2348
2349 radv_foreach_stage(stage, stages) {
2350 shader = radv_get_shader(pipeline, stage);
2351 if (!shader)
2352 continue;
2353
2354 need_push_constants |= shader->info.loads_push_constants;
2355 need_push_constants |= shader->info.loads_dynamic_offsets;
2356
2357 uint8_t base = shader->info.base_inline_push_consts;
2358 uint8_t count = shader->info.num_inline_push_consts;
2359
2360 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2361 AC_UD_INLINE_PUSH_CONSTANTS,
2362 count,
2363 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2364 }
2365
2366 if (need_push_constants) {
2367 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2368 16 * layout->dynamic_offset_count,
2369 256, &offset, &ptr))
2370 return;
2371
2372 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2373 memcpy((char*)ptr + layout->push_constant_size,
2374 descriptors_state->dynamic_buffers,
2375 16 * layout->dynamic_offset_count);
2376
2377 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2378 va += offset;
2379
2380 ASSERTED unsigned cdw_max =
2381 radeon_check_space(cmd_buffer->device->ws,
2382 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2383
2384 prev_shader = NULL;
2385 radv_foreach_stage(stage, stages) {
2386 shader = radv_get_shader(pipeline, stage);
2387
2388 /* Avoid redundantly emitting the address for merged stages. */
2389 if (shader && shader != prev_shader) {
2390 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2391 AC_UD_PUSH_CONSTANTS, va);
2392
2393 prev_shader = shader;
2394 }
2395 }
2396 assert(cmd_buffer->cs->cdw <= cdw_max);
2397 }
2398
2399 cmd_buffer->push_constant_stages &= ~stages;
2400 }
2401
2402 static void
2403 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2404 bool pipeline_is_dirty)
2405 {
2406 if ((pipeline_is_dirty ||
2407 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2408 cmd_buffer->state.pipeline->num_vertex_bindings &&
2409 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2410 unsigned vb_offset;
2411 void *vb_ptr;
2412 uint32_t i = 0;
2413 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2414 uint64_t va;
2415
2416 /* allocate some descriptor state for vertex buffers */
2417 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2418 &vb_offset, &vb_ptr))
2419 return;
2420
2421 for (i = 0; i < count; i++) {
2422 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2423 uint32_t offset;
2424 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2425 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2426 unsigned num_records;
2427
2428 if (!buffer)
2429 continue;
2430
2431 va = radv_buffer_get_va(buffer->bo);
2432
2433 offset = cmd_buffer->vertex_bindings[i].offset;
2434 va += offset + buffer->offset;
2435
2436 num_records = buffer->size - offset;
2437 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2438 num_records /= stride;
2439
2440 desc[0] = va;
2441 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2442 desc[2] = num_records;
2443 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2444 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2445 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2446 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2447
2448 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2449 /* OOB_SELECT chooses the out-of-bounds check:
2450 * - 1: index >= NUM_RECORDS (Structured)
2451 * - 3: offset >= NUM_RECORDS (Raw)
2452 */
2453 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2454
2455 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2456 S_008F0C_OOB_SELECT(oob_select) |
2457 S_008F0C_RESOURCE_LEVEL(1);
2458 } else {
2459 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2460 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2461 }
2462 }
2463
2464 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2465 va += vb_offset;
2466
2467 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2468 AC_UD_VS_VERTEX_BUFFERS, va);
2469
2470 cmd_buffer->state.vb_va = va;
2471 cmd_buffer->state.vb_size = count * 16;
2472 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2473 }
2474 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2475 }
2476
2477 static void
2478 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2479 {
2480 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2481 struct radv_userdata_info *loc;
2482 uint32_t base_reg;
2483
2484 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2485 if (!radv_get_shader(pipeline, stage))
2486 continue;
2487
2488 loc = radv_lookup_user_sgpr(pipeline, stage,
2489 AC_UD_STREAMOUT_BUFFERS);
2490 if (loc->sgpr_idx == -1)
2491 continue;
2492
2493 base_reg = pipeline->user_data_0[stage];
2494
2495 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2496 base_reg + loc->sgpr_idx * 4, va, false);
2497 }
2498
2499 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2500 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2501 if (loc->sgpr_idx != -1) {
2502 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2503
2504 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2505 base_reg + loc->sgpr_idx * 4, va, false);
2506 }
2507 }
2508 }
2509
2510 static void
2511 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2512 {
2513 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2514 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2515 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2516 unsigned so_offset;
2517 void *so_ptr;
2518 uint64_t va;
2519
2520 /* Allocate some descriptor state for streamout buffers. */
2521 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2522 MAX_SO_BUFFERS * 16, 256,
2523 &so_offset, &so_ptr))
2524 return;
2525
2526 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2527 struct radv_buffer *buffer = sb[i].buffer;
2528 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2529
2530 if (!(so->enabled_mask & (1 << i)))
2531 continue;
2532
2533 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2534
2535 va += sb[i].offset;
2536
2537 /* Set the descriptor.
2538 *
2539 * On GFX8, the format must be non-INVALID, otherwise
2540 * the buffer will be considered not bound and store
2541 * instructions will be no-ops.
2542 */
2543 uint32_t size = 0xffffffff;
2544
2545 /* Compute the correct buffer size for NGG streamout
2546 * because it's used to determine the max emit per
2547 * buffer.
2548 */
2549 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2550 size = buffer->size - sb[i].offset;
2551
2552 desc[0] = va;
2553 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2554 desc[2] = size;
2555 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2556 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2557 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2558 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2559
2560 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2561 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2562 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2563 S_008F0C_RESOURCE_LEVEL(1);
2564 } else {
2565 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2566 }
2567 }
2568
2569 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2570 va += so_offset;
2571
2572 radv_emit_streamout_buffers(cmd_buffer, va);
2573 }
2574
2575 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2576 }
2577
2578 static void
2579 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2580 {
2581 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2582 struct radv_userdata_info *loc;
2583 uint32_t ngg_gs_state = 0;
2584 uint32_t base_reg;
2585
2586 if (!radv_pipeline_has_gs(pipeline) ||
2587 !radv_pipeline_has_ngg(pipeline))
2588 return;
2589
2590 /* By default NGG GS queries are disabled but they are enabled if the
2591 * command buffer has active GDS queries or if it's a secondary command
2592 * buffer that inherits the number of generated primitives.
2593 */
2594 if (cmd_buffer->state.active_pipeline_gds_queries ||
2595 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2596 ngg_gs_state = 1;
2597
2598 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2599 AC_UD_NGG_GS_STATE);
2600 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2601 assert(loc->sgpr_idx != -1);
2602
2603 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2604 ngg_gs_state);
2605 }
2606
2607 static void
2608 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2609 {
2610 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2611 radv_flush_streamout_descriptors(cmd_buffer);
2612 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2613 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2614 radv_flush_ngg_gs_state(cmd_buffer);
2615 }
2616
2617 struct radv_draw_info {
2618 /**
2619 * Number of vertices.
2620 */
2621 uint32_t count;
2622
2623 /**
2624 * Index of the first vertex.
2625 */
2626 int32_t vertex_offset;
2627
2628 /**
2629 * First instance id.
2630 */
2631 uint32_t first_instance;
2632
2633 /**
2634 * Number of instances.
2635 */
2636 uint32_t instance_count;
2637
2638 /**
2639 * First index (indexed draws only).
2640 */
2641 uint32_t first_index;
2642
2643 /**
2644 * Whether it's an indexed draw.
2645 */
2646 bool indexed;
2647
2648 /**
2649 * Indirect draw parameters resource.
2650 */
2651 struct radv_buffer *indirect;
2652 uint64_t indirect_offset;
2653 uint32_t stride;
2654
2655 /**
2656 * Draw count parameters resource.
2657 */
2658 struct radv_buffer *count_buffer;
2659 uint64_t count_buffer_offset;
2660
2661 /**
2662 * Stream output parameters resource.
2663 */
2664 struct radv_buffer *strmout_buffer;
2665 uint64_t strmout_buffer_offset;
2666 };
2667
2668 static uint32_t
2669 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2670 {
2671 switch (cmd_buffer->state.index_type) {
2672 case V_028A7C_VGT_INDEX_8:
2673 return 0xffu;
2674 case V_028A7C_VGT_INDEX_16:
2675 return 0xffffu;
2676 case V_028A7C_VGT_INDEX_32:
2677 return 0xffffffffu;
2678 default:
2679 unreachable("invalid index type");
2680 }
2681 }
2682
2683 static void
2684 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2685 bool instanced_draw, bool indirect_draw,
2686 bool count_from_stream_output,
2687 uint32_t draw_vertex_count)
2688 {
2689 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2690 struct radv_cmd_state *state = &cmd_buffer->state;
2691 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2692 unsigned ia_multi_vgt_param;
2693
2694 ia_multi_vgt_param =
2695 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2696 indirect_draw,
2697 count_from_stream_output,
2698 draw_vertex_count);
2699
2700 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2701 if (info->chip_class == GFX9) {
2702 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2703 cs,
2704 R_030960_IA_MULTI_VGT_PARAM,
2705 4, ia_multi_vgt_param);
2706 } else if (info->chip_class >= GFX7) {
2707 radeon_set_context_reg_idx(cs,
2708 R_028AA8_IA_MULTI_VGT_PARAM,
2709 1, ia_multi_vgt_param);
2710 } else {
2711 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2712 ia_multi_vgt_param);
2713 }
2714 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2715 }
2716 }
2717
2718 static void
2719 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2720 const struct radv_draw_info *draw_info)
2721 {
2722 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2723 struct radv_cmd_state *state = &cmd_buffer->state;
2724 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2725 int32_t primitive_reset_en;
2726
2727 /* Draw state. */
2728 if (info->chip_class < GFX10) {
2729 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2730 draw_info->indirect,
2731 !!draw_info->strmout_buffer,
2732 draw_info->indirect ? 0 : draw_info->count);
2733 }
2734
2735 /* Primitive restart. */
2736 primitive_reset_en =
2737 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2738
2739 if (primitive_reset_en != state->last_primitive_reset_en) {
2740 state->last_primitive_reset_en = primitive_reset_en;
2741 if (info->chip_class >= GFX9) {
2742 radeon_set_uconfig_reg(cs,
2743 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2744 primitive_reset_en);
2745 } else {
2746 radeon_set_context_reg(cs,
2747 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2748 primitive_reset_en);
2749 }
2750 }
2751
2752 if (primitive_reset_en) {
2753 uint32_t primitive_reset_index =
2754 radv_get_primitive_reset_index(cmd_buffer);
2755
2756 if (primitive_reset_index != state->last_primitive_reset_index) {
2757 radeon_set_context_reg(cs,
2758 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2759 primitive_reset_index);
2760 state->last_primitive_reset_index = primitive_reset_index;
2761 }
2762 }
2763
2764 if (draw_info->strmout_buffer) {
2765 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2766
2767 va += draw_info->strmout_buffer->offset +
2768 draw_info->strmout_buffer_offset;
2769
2770 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2771 draw_info->stride);
2772
2773 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2774 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2775 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2776 COPY_DATA_WR_CONFIRM);
2777 radeon_emit(cs, va);
2778 radeon_emit(cs, va >> 32);
2779 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2780 radeon_emit(cs, 0); /* unused */
2781
2782 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2783 }
2784 }
2785
2786 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2787 VkPipelineStageFlags src_stage_mask)
2788 {
2789 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2790 VK_PIPELINE_STAGE_TRANSFER_BIT |
2791 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2792 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2793 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2794 }
2795
2796 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2797 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2798 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2799 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2800 VK_PIPELINE_STAGE_TRANSFER_BIT |
2801 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2802 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2803 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2804 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2805 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2806 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2807 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2808 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2809 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2810 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2811 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2812 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2813 }
2814 }
2815
2816 static enum radv_cmd_flush_bits
2817 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2818 VkAccessFlags src_flags,
2819 struct radv_image *image)
2820 {
2821 bool flush_CB_meta = true, flush_DB_meta = true;
2822 enum radv_cmd_flush_bits flush_bits = 0;
2823 uint32_t b;
2824
2825 if (image) {
2826 if (!radv_image_has_CB_metadata(image))
2827 flush_CB_meta = false;
2828 if (!radv_image_has_htile(image))
2829 flush_DB_meta = false;
2830 }
2831
2832 for_each_bit(b, src_flags) {
2833 switch ((VkAccessFlagBits)(1 << b)) {
2834 case VK_ACCESS_SHADER_WRITE_BIT:
2835 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2836 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2837 flush_bits |= RADV_CMD_FLAG_WB_L2;
2838 break;
2839 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2840 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2841 if (flush_CB_meta)
2842 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2843 break;
2844 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2845 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2846 if (flush_DB_meta)
2847 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2848 break;
2849 case VK_ACCESS_TRANSFER_WRITE_BIT:
2850 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2851 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2852 RADV_CMD_FLAG_INV_L2;
2853
2854 if (flush_CB_meta)
2855 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2856 if (flush_DB_meta)
2857 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2858 break;
2859 default:
2860 break;
2861 }
2862 }
2863 return flush_bits;
2864 }
2865
2866 static enum radv_cmd_flush_bits
2867 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2868 VkAccessFlags dst_flags,
2869 struct radv_image *image)
2870 {
2871 bool flush_CB_meta = true, flush_DB_meta = true;
2872 enum radv_cmd_flush_bits flush_bits = 0;
2873 bool flush_CB = true, flush_DB = true;
2874 bool image_is_coherent = false;
2875 uint32_t b;
2876
2877 if (image) {
2878 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2879 flush_CB = false;
2880 flush_DB = false;
2881 }
2882
2883 if (!radv_image_has_CB_metadata(image))
2884 flush_CB_meta = false;
2885 if (!radv_image_has_htile(image))
2886 flush_DB_meta = false;
2887
2888 /* TODO: implement shader coherent for GFX10 */
2889
2890 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2891 if (image->info.samples == 1 &&
2892 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2893 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2894 !vk_format_is_stencil(image->vk_format)) {
2895 /* Single-sample color and single-sample depth
2896 * (not stencil) are coherent with shaders on
2897 * GFX9.
2898 */
2899 image_is_coherent = true;
2900 }
2901 }
2902 }
2903
2904 for_each_bit(b, dst_flags) {
2905 switch ((VkAccessFlagBits)(1 << b)) {
2906 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2907 case VK_ACCESS_INDEX_READ_BIT:
2908 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2909 break;
2910 case VK_ACCESS_UNIFORM_READ_BIT:
2911 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2912 break;
2913 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2914 case VK_ACCESS_TRANSFER_READ_BIT:
2915 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2916 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2917 RADV_CMD_FLAG_INV_L2;
2918 break;
2919 case VK_ACCESS_SHADER_READ_BIT:
2920 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2921 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2922 * invalidate the scalar cache. */
2923 if (cmd_buffer->device->physical_device->use_aco &&
2924 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8)
2925 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
2926
2927 if (!image_is_coherent)
2928 flush_bits |= RADV_CMD_FLAG_INV_L2;
2929 break;
2930 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2931 if (flush_CB)
2932 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2933 if (flush_CB_meta)
2934 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2935 break;
2936 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2937 if (flush_DB)
2938 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2939 if (flush_DB_meta)
2940 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2941 break;
2942 default:
2943 break;
2944 }
2945 }
2946 return flush_bits;
2947 }
2948
2949 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2950 const struct radv_subpass_barrier *barrier)
2951 {
2952 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2953 NULL);
2954 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2955 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2956 NULL);
2957 }
2958
2959 uint32_t
2960 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2961 {
2962 struct radv_cmd_state *state = &cmd_buffer->state;
2963 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2964
2965 /* The id of this subpass shouldn't exceed the number of subpasses in
2966 * this render pass minus 1.
2967 */
2968 assert(subpass_id < state->pass->subpass_count);
2969 return subpass_id;
2970 }
2971
2972 static struct radv_sample_locations_state *
2973 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2974 uint32_t att_idx,
2975 bool begin_subpass)
2976 {
2977 struct radv_cmd_state *state = &cmd_buffer->state;
2978 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2979 struct radv_image_view *view = state->attachments[att_idx].iview;
2980
2981 if (view->image->info.samples == 1)
2982 return NULL;
2983
2984 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2985 /* Return the initial sample locations if this is the initial
2986 * layout transition of the given subpass attachemnt.
2987 */
2988 if (state->attachments[att_idx].sample_location.count > 0)
2989 return &state->attachments[att_idx].sample_location;
2990 } else {
2991 /* Otherwise return the subpass sample locations if defined. */
2992 if (state->subpass_sample_locs) {
2993 /* Because the driver sets the current subpass before
2994 * initial layout transitions, we should use the sample
2995 * locations from the previous subpass to avoid an
2996 * off-by-one problem. Otherwise, use the sample
2997 * locations for the current subpass for final layout
2998 * transitions.
2999 */
3000 if (begin_subpass)
3001 subpass_id--;
3002
3003 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
3004 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
3005 return &state->subpass_sample_locs[i].sample_location;
3006 }
3007 }
3008 }
3009
3010 return NULL;
3011 }
3012
3013 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
3014 struct radv_subpass_attachment att,
3015 bool begin_subpass)
3016 {
3017 unsigned idx = att.attachment;
3018 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
3019 struct radv_sample_locations_state *sample_locs;
3020 VkImageSubresourceRange range;
3021 range.aspectMask = view->aspect_mask;
3022 range.baseMipLevel = view->base_mip;
3023 range.levelCount = 1;
3024 range.baseArrayLayer = view->base_layer;
3025 range.layerCount = cmd_buffer->state.framebuffer->layers;
3026
3027 if (cmd_buffer->state.subpass->view_mask) {
3028 /* If the current subpass uses multiview, the driver might have
3029 * performed a fast color/depth clear to the whole image
3030 * (including all layers). To make sure the driver will
3031 * decompress the image correctly (if needed), we have to
3032 * account for the "real" number of layers. If the view mask is
3033 * sparse, this will decompress more layers than needed.
3034 */
3035 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3036 }
3037
3038 /* Get the subpass sample locations for the given attachment, if NULL
3039 * is returned the driver will use the default HW locations.
3040 */
3041 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3042 begin_subpass);
3043
3044 /* Determine if the subpass uses separate depth/stencil layouts. */
3045 bool uses_separate_depth_stencil_layouts = false;
3046 if ((cmd_buffer->state.attachments[idx].current_layout !=
3047 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3048 (att.layout != att.stencil_layout)) {
3049 uses_separate_depth_stencil_layouts = true;
3050 }
3051
3052 /* For separate layouts, perform depth and stencil transitions
3053 * separately.
3054 */
3055 if (uses_separate_depth_stencil_layouts &&
3056 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3057 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3058 /* Depth-only transitions. */
3059 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3060 radv_handle_image_transition(cmd_buffer,
3061 view->image,
3062 cmd_buffer->state.attachments[idx].current_layout,
3063 cmd_buffer->state.attachments[idx].current_in_render_loop,
3064 att.layout, att.in_render_loop,
3065 0, 0, &range, sample_locs);
3066
3067 /* Stencil-only transitions. */
3068 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3069 radv_handle_image_transition(cmd_buffer,
3070 view->image,
3071 cmd_buffer->state.attachments[idx].current_stencil_layout,
3072 cmd_buffer->state.attachments[idx].current_in_render_loop,
3073 att.stencil_layout, att.in_render_loop,
3074 0, 0, &range, sample_locs);
3075 } else {
3076 radv_handle_image_transition(cmd_buffer,
3077 view->image,
3078 cmd_buffer->state.attachments[idx].current_layout,
3079 cmd_buffer->state.attachments[idx].current_in_render_loop,
3080 att.layout, att.in_render_loop,
3081 0, 0, &range, sample_locs);
3082 }
3083
3084 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3085 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3086 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3087
3088
3089 }
3090
3091 void
3092 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3093 const struct radv_subpass *subpass)
3094 {
3095 cmd_buffer->state.subpass = subpass;
3096
3097 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3098 }
3099
3100 static VkResult
3101 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3102 struct radv_render_pass *pass,
3103 const VkRenderPassBeginInfo *info)
3104 {
3105 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3106 vk_find_struct_const(info->pNext,
3107 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3108 struct radv_cmd_state *state = &cmd_buffer->state;
3109
3110 if (!sample_locs) {
3111 state->subpass_sample_locs = NULL;
3112 return VK_SUCCESS;
3113 }
3114
3115 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3116 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3117 &sample_locs->pAttachmentInitialSampleLocations[i];
3118 uint32_t att_idx = att_sample_locs->attachmentIndex;
3119 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3120
3121 assert(vk_format_is_depth_or_stencil(image->vk_format));
3122
3123 /* From the Vulkan spec 1.1.108:
3124 *
3125 * "If the image referenced by the framebuffer attachment at
3126 * index attachmentIndex was not created with
3127 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3128 * then the values specified in sampleLocationsInfo are
3129 * ignored."
3130 */
3131 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3132 continue;
3133
3134 const VkSampleLocationsInfoEXT *sample_locs_info =
3135 &att_sample_locs->sampleLocationsInfo;
3136
3137 state->attachments[att_idx].sample_location.per_pixel =
3138 sample_locs_info->sampleLocationsPerPixel;
3139 state->attachments[att_idx].sample_location.grid_size =
3140 sample_locs_info->sampleLocationGridSize;
3141 state->attachments[att_idx].sample_location.count =
3142 sample_locs_info->sampleLocationsCount;
3143 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3144 sample_locs_info->pSampleLocations,
3145 sample_locs_info->sampleLocationsCount);
3146 }
3147
3148 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3149 sample_locs->postSubpassSampleLocationsCount *
3150 sizeof(state->subpass_sample_locs[0]),
3151 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3152 if (state->subpass_sample_locs == NULL) {
3153 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3154 return cmd_buffer->record_result;
3155 }
3156
3157 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3158
3159 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3160 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3161 &sample_locs->pPostSubpassSampleLocations[i];
3162 const VkSampleLocationsInfoEXT *sample_locs_info =
3163 &subpass_sample_locs_info->sampleLocationsInfo;
3164
3165 state->subpass_sample_locs[i].subpass_idx =
3166 subpass_sample_locs_info->subpassIndex;
3167 state->subpass_sample_locs[i].sample_location.per_pixel =
3168 sample_locs_info->sampleLocationsPerPixel;
3169 state->subpass_sample_locs[i].sample_location.grid_size =
3170 sample_locs_info->sampleLocationGridSize;
3171 state->subpass_sample_locs[i].sample_location.count =
3172 sample_locs_info->sampleLocationsCount;
3173 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3174 sample_locs_info->pSampleLocations,
3175 sample_locs_info->sampleLocationsCount);
3176 }
3177
3178 return VK_SUCCESS;
3179 }
3180
3181 static VkResult
3182 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3183 struct radv_render_pass *pass,
3184 const VkRenderPassBeginInfo *info)
3185 {
3186 struct radv_cmd_state *state = &cmd_buffer->state;
3187 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3188
3189 if (info) {
3190 attachment_info = vk_find_struct_const(info->pNext,
3191 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3192 }
3193
3194
3195 if (pass->attachment_count == 0) {
3196 state->attachments = NULL;
3197 return VK_SUCCESS;
3198 }
3199
3200 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3201 pass->attachment_count *
3202 sizeof(state->attachments[0]),
3203 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3204 if (state->attachments == NULL) {
3205 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3206 return cmd_buffer->record_result;
3207 }
3208
3209 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3210 struct radv_render_pass_attachment *att = &pass->attachments[i];
3211 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3212 VkImageAspectFlags clear_aspects = 0;
3213
3214 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3215 /* color attachment */
3216 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3217 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3218 }
3219 } else {
3220 /* depthstencil attachment */
3221 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3222 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3223 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3224 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3225 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3226 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3227 }
3228 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3229 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3230 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3231 }
3232 }
3233
3234 state->attachments[i].pending_clear_aspects = clear_aspects;
3235 state->attachments[i].cleared_views = 0;
3236 if (clear_aspects && info) {
3237 assert(info->clearValueCount > i);
3238 state->attachments[i].clear_value = info->pClearValues[i];
3239 }
3240
3241 state->attachments[i].current_layout = att->initial_layout;
3242 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3243 state->attachments[i].sample_location.count = 0;
3244
3245 struct radv_image_view *iview;
3246 if (attachment_info && attachment_info->attachmentCount > i) {
3247 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3248 } else {
3249 iview = state->framebuffer->attachments[i];
3250 }
3251
3252 state->attachments[i].iview = iview;
3253 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3254 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3255 } else {
3256 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3257 }
3258 }
3259
3260 return VK_SUCCESS;
3261 }
3262
3263 VkResult radv_AllocateCommandBuffers(
3264 VkDevice _device,
3265 const VkCommandBufferAllocateInfo *pAllocateInfo,
3266 VkCommandBuffer *pCommandBuffers)
3267 {
3268 RADV_FROM_HANDLE(radv_device, device, _device);
3269 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3270
3271 VkResult result = VK_SUCCESS;
3272 uint32_t i;
3273
3274 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3275
3276 if (!list_is_empty(&pool->free_cmd_buffers)) {
3277 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3278
3279 list_del(&cmd_buffer->pool_link);
3280 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3281
3282 result = radv_reset_cmd_buffer(cmd_buffer);
3283 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3284 cmd_buffer->level = pAllocateInfo->level;
3285
3286 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3287 } else {
3288 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3289 &pCommandBuffers[i]);
3290 }
3291 if (result != VK_SUCCESS)
3292 break;
3293 }
3294
3295 if (result != VK_SUCCESS) {
3296 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3297 i, pCommandBuffers);
3298
3299 /* From the Vulkan 1.0.66 spec:
3300 *
3301 * "vkAllocateCommandBuffers can be used to create multiple
3302 * command buffers. If the creation of any of those command
3303 * buffers fails, the implementation must destroy all
3304 * successfully created command buffer objects from this
3305 * command, set all entries of the pCommandBuffers array to
3306 * NULL and return the error."
3307 */
3308 memset(pCommandBuffers, 0,
3309 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3310 }
3311
3312 return result;
3313 }
3314
3315 void radv_FreeCommandBuffers(
3316 VkDevice device,
3317 VkCommandPool commandPool,
3318 uint32_t commandBufferCount,
3319 const VkCommandBuffer *pCommandBuffers)
3320 {
3321 for (uint32_t i = 0; i < commandBufferCount; i++) {
3322 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3323
3324 if (cmd_buffer) {
3325 if (cmd_buffer->pool) {
3326 list_del(&cmd_buffer->pool_link);
3327 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3328 } else
3329 radv_cmd_buffer_destroy(cmd_buffer);
3330
3331 }
3332 }
3333 }
3334
3335 VkResult radv_ResetCommandBuffer(
3336 VkCommandBuffer commandBuffer,
3337 VkCommandBufferResetFlags flags)
3338 {
3339 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3340 return radv_reset_cmd_buffer(cmd_buffer);
3341 }
3342
3343 VkResult radv_BeginCommandBuffer(
3344 VkCommandBuffer commandBuffer,
3345 const VkCommandBufferBeginInfo *pBeginInfo)
3346 {
3347 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3348 VkResult result = VK_SUCCESS;
3349
3350 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3351 /* If the command buffer has already been resetted with
3352 * vkResetCommandBuffer, no need to do it again.
3353 */
3354 result = radv_reset_cmd_buffer(cmd_buffer);
3355 if (result != VK_SUCCESS)
3356 return result;
3357 }
3358
3359 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3360 cmd_buffer->state.last_primitive_reset_en = -1;
3361 cmd_buffer->state.last_index_type = -1;
3362 cmd_buffer->state.last_num_instances = -1;
3363 cmd_buffer->state.last_vertex_offset = -1;
3364 cmd_buffer->state.last_first_instance = -1;
3365 cmd_buffer->state.predication_type = -1;
3366 cmd_buffer->usage_flags = pBeginInfo->flags;
3367
3368 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3369 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3370 assert(pBeginInfo->pInheritanceInfo);
3371 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3372 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3373
3374 struct radv_subpass *subpass =
3375 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3376
3377 if (cmd_buffer->state.framebuffer) {
3378 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3379 if (result != VK_SUCCESS)
3380 return result;
3381 }
3382
3383 cmd_buffer->state.inherited_pipeline_statistics =
3384 pBeginInfo->pInheritanceInfo->pipelineStatistics;
3385
3386 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3387 }
3388
3389 if (unlikely(cmd_buffer->device->trace_bo)) {
3390 struct radv_device *device = cmd_buffer->device;
3391
3392 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3393 device->trace_bo);
3394
3395 radv_cmd_buffer_trace_emit(cmd_buffer);
3396 }
3397
3398 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3399
3400 return result;
3401 }
3402
3403 void radv_CmdBindVertexBuffers(
3404 VkCommandBuffer commandBuffer,
3405 uint32_t firstBinding,
3406 uint32_t bindingCount,
3407 const VkBuffer* pBuffers,
3408 const VkDeviceSize* pOffsets)
3409 {
3410 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3411 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3412 bool changed = false;
3413
3414 /* We have to defer setting up vertex buffer since we need the buffer
3415 * stride from the pipeline. */
3416
3417 assert(firstBinding + bindingCount <= MAX_VBS);
3418 for (uint32_t i = 0; i < bindingCount; i++) {
3419 uint32_t idx = firstBinding + i;
3420
3421 if (!changed &&
3422 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3423 vb[idx].offset != pOffsets[i])) {
3424 changed = true;
3425 }
3426
3427 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3428 vb[idx].offset = pOffsets[i];
3429
3430 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3431 vb[idx].buffer->bo);
3432 }
3433
3434 if (!changed) {
3435 /* No state changes. */
3436 return;
3437 }
3438
3439 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3440 }
3441
3442 static uint32_t
3443 vk_to_index_type(VkIndexType type)
3444 {
3445 switch (type) {
3446 case VK_INDEX_TYPE_UINT8_EXT:
3447 return V_028A7C_VGT_INDEX_8;
3448 case VK_INDEX_TYPE_UINT16:
3449 return V_028A7C_VGT_INDEX_16;
3450 case VK_INDEX_TYPE_UINT32:
3451 return V_028A7C_VGT_INDEX_32;
3452 default:
3453 unreachable("invalid index type");
3454 }
3455 }
3456
3457 static uint32_t
3458 radv_get_vgt_index_size(uint32_t type)
3459 {
3460 switch (type) {
3461 case V_028A7C_VGT_INDEX_8:
3462 return 1;
3463 case V_028A7C_VGT_INDEX_16:
3464 return 2;
3465 case V_028A7C_VGT_INDEX_32:
3466 return 4;
3467 default:
3468 unreachable("invalid index type");
3469 }
3470 }
3471
3472 void radv_CmdBindIndexBuffer(
3473 VkCommandBuffer commandBuffer,
3474 VkBuffer buffer,
3475 VkDeviceSize offset,
3476 VkIndexType indexType)
3477 {
3478 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3479 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3480
3481 if (cmd_buffer->state.index_buffer == index_buffer &&
3482 cmd_buffer->state.index_offset == offset &&
3483 cmd_buffer->state.index_type == indexType) {
3484 /* No state changes. */
3485 return;
3486 }
3487
3488 cmd_buffer->state.index_buffer = index_buffer;
3489 cmd_buffer->state.index_offset = offset;
3490 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3491 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3492 cmd_buffer->state.index_va += index_buffer->offset + offset;
3493
3494 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3495 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3496 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3497 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3498 }
3499
3500
3501 static void
3502 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3503 VkPipelineBindPoint bind_point,
3504 struct radv_descriptor_set *set, unsigned idx)
3505 {
3506 struct radeon_winsys *ws = cmd_buffer->device->ws;
3507
3508 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3509
3510 assert(set);
3511 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3512
3513 if (!cmd_buffer->device->use_global_bo_list) {
3514 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3515 if (set->descriptors[j])
3516 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3517 }
3518
3519 if(set->bo)
3520 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3521 }
3522
3523 void radv_CmdBindDescriptorSets(
3524 VkCommandBuffer commandBuffer,
3525 VkPipelineBindPoint pipelineBindPoint,
3526 VkPipelineLayout _layout,
3527 uint32_t firstSet,
3528 uint32_t descriptorSetCount,
3529 const VkDescriptorSet* pDescriptorSets,
3530 uint32_t dynamicOffsetCount,
3531 const uint32_t* pDynamicOffsets)
3532 {
3533 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3534 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3535 unsigned dyn_idx = 0;
3536
3537 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3538 struct radv_descriptor_state *descriptors_state =
3539 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3540
3541 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3542 unsigned idx = i + firstSet;
3543 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3544
3545 /* If the set is already bound we only need to update the
3546 * (potentially changed) dynamic offsets. */
3547 if (descriptors_state->sets[idx] != set ||
3548 !(descriptors_state->valid & (1u << idx))) {
3549 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3550 }
3551
3552 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3553 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3554 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3555 assert(dyn_idx < dynamicOffsetCount);
3556
3557 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3558 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3559 dst[0] = va;
3560 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3561 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3562 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3563 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3564 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3565 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3566
3567 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3568 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3569 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3570 S_008F0C_RESOURCE_LEVEL(1);
3571 } else {
3572 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3573 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3574 }
3575
3576 cmd_buffer->push_constant_stages |=
3577 set->layout->dynamic_shader_stages;
3578 }
3579 }
3580 }
3581
3582 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3583 struct radv_descriptor_set *set,
3584 struct radv_descriptor_set_layout *layout,
3585 VkPipelineBindPoint bind_point)
3586 {
3587 struct radv_descriptor_state *descriptors_state =
3588 radv_get_descriptors_state(cmd_buffer, bind_point);
3589 set->size = layout->size;
3590 set->layout = layout;
3591
3592 if (descriptors_state->push_set.capacity < set->size) {
3593 size_t new_size = MAX2(set->size, 1024);
3594 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3595 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3596
3597 free(set->mapped_ptr);
3598 set->mapped_ptr = malloc(new_size);
3599
3600 if (!set->mapped_ptr) {
3601 descriptors_state->push_set.capacity = 0;
3602 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3603 return false;
3604 }
3605
3606 descriptors_state->push_set.capacity = new_size;
3607 }
3608
3609 return true;
3610 }
3611
3612 void radv_meta_push_descriptor_set(
3613 struct radv_cmd_buffer* cmd_buffer,
3614 VkPipelineBindPoint pipelineBindPoint,
3615 VkPipelineLayout _layout,
3616 uint32_t set,
3617 uint32_t descriptorWriteCount,
3618 const VkWriteDescriptorSet* pDescriptorWrites)
3619 {
3620 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3621 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3622 unsigned bo_offset;
3623
3624 assert(set == 0);
3625 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3626
3627 push_set->size = layout->set[set].layout->size;
3628 push_set->layout = layout->set[set].layout;
3629
3630 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3631 &bo_offset,
3632 (void**) &push_set->mapped_ptr))
3633 return;
3634
3635 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3636 push_set->va += bo_offset;
3637
3638 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3639 radv_descriptor_set_to_handle(push_set),
3640 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3641
3642 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3643 }
3644
3645 void radv_CmdPushDescriptorSetKHR(
3646 VkCommandBuffer commandBuffer,
3647 VkPipelineBindPoint pipelineBindPoint,
3648 VkPipelineLayout _layout,
3649 uint32_t set,
3650 uint32_t descriptorWriteCount,
3651 const VkWriteDescriptorSet* pDescriptorWrites)
3652 {
3653 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3654 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3655 struct radv_descriptor_state *descriptors_state =
3656 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3657 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3658
3659 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3660
3661 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3662 layout->set[set].layout,
3663 pipelineBindPoint))
3664 return;
3665
3666 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3667 * because it is invalid, according to Vulkan spec.
3668 */
3669 for (int i = 0; i < descriptorWriteCount; i++) {
3670 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3671 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3672 }
3673
3674 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3675 radv_descriptor_set_to_handle(push_set),
3676 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3677
3678 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3679 descriptors_state->push_dirty = true;
3680 }
3681
3682 void radv_CmdPushDescriptorSetWithTemplateKHR(
3683 VkCommandBuffer commandBuffer,
3684 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3685 VkPipelineLayout _layout,
3686 uint32_t set,
3687 const void* pData)
3688 {
3689 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3690 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3691 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3692 struct radv_descriptor_state *descriptors_state =
3693 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3694 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3695
3696 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3697
3698 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3699 layout->set[set].layout,
3700 templ->bind_point))
3701 return;
3702
3703 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3704 descriptorUpdateTemplate, pData);
3705
3706 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3707 descriptors_state->push_dirty = true;
3708 }
3709
3710 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3711 VkPipelineLayout layout,
3712 VkShaderStageFlags stageFlags,
3713 uint32_t offset,
3714 uint32_t size,
3715 const void* pValues)
3716 {
3717 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3718 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3719 cmd_buffer->push_constant_stages |= stageFlags;
3720 }
3721
3722 VkResult radv_EndCommandBuffer(
3723 VkCommandBuffer commandBuffer)
3724 {
3725 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3726
3727 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3728 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3729 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3730
3731 /* Make sure to sync all pending active queries at the end of
3732 * command buffer.
3733 */
3734 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3735
3736 /* Since NGG streamout uses GDS, we need to make GDS idle when
3737 * we leave the IB, otherwise another process might overwrite
3738 * it while our shaders are busy.
3739 */
3740 if (cmd_buffer->gds_needed)
3741 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3742
3743 si_emit_cache_flush(cmd_buffer);
3744 }
3745
3746 /* Make sure CP DMA is idle at the end of IBs because the kernel
3747 * doesn't wait for it.
3748 */
3749 si_cp_dma_wait_for_idle(cmd_buffer);
3750
3751 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3752 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3753
3754 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3755 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3756
3757 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3758
3759 return cmd_buffer->record_result;
3760 }
3761
3762 static void
3763 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3764 {
3765 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3766
3767 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3768 return;
3769
3770 assert(!pipeline->ctx_cs.cdw);
3771
3772 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3773
3774 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3775 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3776
3777 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
3778 pipeline->scratch_bytes_per_wave);
3779 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
3780 pipeline->max_waves);
3781
3782 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3783 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3784
3785 if (unlikely(cmd_buffer->device->trace_bo))
3786 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3787 }
3788
3789 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3790 VkPipelineBindPoint bind_point)
3791 {
3792 struct radv_descriptor_state *descriptors_state =
3793 radv_get_descriptors_state(cmd_buffer, bind_point);
3794
3795 descriptors_state->dirty |= descriptors_state->valid;
3796 }
3797
3798 void radv_CmdBindPipeline(
3799 VkCommandBuffer commandBuffer,
3800 VkPipelineBindPoint pipelineBindPoint,
3801 VkPipeline _pipeline)
3802 {
3803 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3804 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3805
3806 switch (pipelineBindPoint) {
3807 case VK_PIPELINE_BIND_POINT_COMPUTE:
3808 if (cmd_buffer->state.compute_pipeline == pipeline)
3809 return;
3810 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3811
3812 cmd_buffer->state.compute_pipeline = pipeline;
3813 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3814 break;
3815 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3816 if (cmd_buffer->state.pipeline == pipeline)
3817 return;
3818 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3819
3820 cmd_buffer->state.pipeline = pipeline;
3821 if (!pipeline)
3822 break;
3823
3824 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3825 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3826
3827 /* the new vertex shader might not have the same user regs */
3828 cmd_buffer->state.last_first_instance = -1;
3829 cmd_buffer->state.last_vertex_offset = -1;
3830
3831 /* Prefetch all pipeline shaders at first draw time. */
3832 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3833
3834 if ((cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3835 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3836 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3837 cmd_buffer->state.emitted_pipeline &&
3838 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3839 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3840 /* Transitioning from NGG to legacy GS requires
3841 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3842 * at the beginning of IBs when legacy GS ring pointers
3843 * are set.
3844 */
3845 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3846 }
3847
3848 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3849 radv_bind_streamout_state(cmd_buffer, pipeline);
3850
3851 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3852 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3853 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3854 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3855
3856 if (radv_pipeline_has_tess(pipeline))
3857 cmd_buffer->tess_rings_needed = true;
3858 break;
3859 default:
3860 assert(!"invalid bind point");
3861 break;
3862 }
3863 }
3864
3865 void radv_CmdSetViewport(
3866 VkCommandBuffer commandBuffer,
3867 uint32_t firstViewport,
3868 uint32_t viewportCount,
3869 const VkViewport* pViewports)
3870 {
3871 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3872 struct radv_cmd_state *state = &cmd_buffer->state;
3873 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
3874
3875 assert(firstViewport < MAX_VIEWPORTS);
3876 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3877
3878 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3879 pViewports, viewportCount * sizeof(*pViewports))) {
3880 return;
3881 }
3882
3883 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3884 viewportCount * sizeof(*pViewports));
3885
3886 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3887 }
3888
3889 void radv_CmdSetScissor(
3890 VkCommandBuffer commandBuffer,
3891 uint32_t firstScissor,
3892 uint32_t scissorCount,
3893 const VkRect2D* pScissors)
3894 {
3895 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3896 struct radv_cmd_state *state = &cmd_buffer->state;
3897 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
3898
3899 assert(firstScissor < MAX_SCISSORS);
3900 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3901
3902 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3903 scissorCount * sizeof(*pScissors))) {
3904 return;
3905 }
3906
3907 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3908 scissorCount * sizeof(*pScissors));
3909
3910 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3911 }
3912
3913 void radv_CmdSetLineWidth(
3914 VkCommandBuffer commandBuffer,
3915 float lineWidth)
3916 {
3917 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3918
3919 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3920 return;
3921
3922 cmd_buffer->state.dynamic.line_width = lineWidth;
3923 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3924 }
3925
3926 void radv_CmdSetDepthBias(
3927 VkCommandBuffer commandBuffer,
3928 float depthBiasConstantFactor,
3929 float depthBiasClamp,
3930 float depthBiasSlopeFactor)
3931 {
3932 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3933 struct radv_cmd_state *state = &cmd_buffer->state;
3934
3935 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3936 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3937 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3938 return;
3939 }
3940
3941 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3942 state->dynamic.depth_bias.clamp = depthBiasClamp;
3943 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3944
3945 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3946 }
3947
3948 void radv_CmdSetBlendConstants(
3949 VkCommandBuffer commandBuffer,
3950 const float blendConstants[4])
3951 {
3952 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3953 struct radv_cmd_state *state = &cmd_buffer->state;
3954
3955 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3956 return;
3957
3958 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3959
3960 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3961 }
3962
3963 void radv_CmdSetDepthBounds(
3964 VkCommandBuffer commandBuffer,
3965 float minDepthBounds,
3966 float maxDepthBounds)
3967 {
3968 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3969 struct radv_cmd_state *state = &cmd_buffer->state;
3970
3971 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3972 state->dynamic.depth_bounds.max == maxDepthBounds) {
3973 return;
3974 }
3975
3976 state->dynamic.depth_bounds.min = minDepthBounds;
3977 state->dynamic.depth_bounds.max = maxDepthBounds;
3978
3979 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3980 }
3981
3982 void radv_CmdSetStencilCompareMask(
3983 VkCommandBuffer commandBuffer,
3984 VkStencilFaceFlags faceMask,
3985 uint32_t compareMask)
3986 {
3987 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3988 struct radv_cmd_state *state = &cmd_buffer->state;
3989 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3990 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3991
3992 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3993 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3994 return;
3995 }
3996
3997 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3998 state->dynamic.stencil_compare_mask.front = compareMask;
3999 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4000 state->dynamic.stencil_compare_mask.back = compareMask;
4001
4002 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
4003 }
4004
4005 void radv_CmdSetStencilWriteMask(
4006 VkCommandBuffer commandBuffer,
4007 VkStencilFaceFlags faceMask,
4008 uint32_t writeMask)
4009 {
4010 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4011 struct radv_cmd_state *state = &cmd_buffer->state;
4012 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
4013 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
4014
4015 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4016 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4017 return;
4018 }
4019
4020 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4021 state->dynamic.stencil_write_mask.front = writeMask;
4022 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4023 state->dynamic.stencil_write_mask.back = writeMask;
4024
4025 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
4026 }
4027
4028 void radv_CmdSetStencilReference(
4029 VkCommandBuffer commandBuffer,
4030 VkStencilFaceFlags faceMask,
4031 uint32_t reference)
4032 {
4033 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4034 struct radv_cmd_state *state = &cmd_buffer->state;
4035 bool front_same = state->dynamic.stencil_reference.front == reference;
4036 bool back_same = state->dynamic.stencil_reference.back == reference;
4037
4038 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4039 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4040 return;
4041 }
4042
4043 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4044 cmd_buffer->state.dynamic.stencil_reference.front = reference;
4045 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4046 cmd_buffer->state.dynamic.stencil_reference.back = reference;
4047
4048 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
4049 }
4050
4051 void radv_CmdSetDiscardRectangleEXT(
4052 VkCommandBuffer commandBuffer,
4053 uint32_t firstDiscardRectangle,
4054 uint32_t discardRectangleCount,
4055 const VkRect2D* pDiscardRectangles)
4056 {
4057 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4058 struct radv_cmd_state *state = &cmd_buffer->state;
4059 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
4060
4061 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
4062 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
4063
4064 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
4065 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
4066 return;
4067 }
4068
4069 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
4070 pDiscardRectangles, discardRectangleCount);
4071
4072 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
4073 }
4074
4075 void radv_CmdSetSampleLocationsEXT(
4076 VkCommandBuffer commandBuffer,
4077 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
4078 {
4079 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4080 struct radv_cmd_state *state = &cmd_buffer->state;
4081
4082 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
4083
4084 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
4085 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
4086 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
4087 typed_memcpy(&state->dynamic.sample_location.locations[0],
4088 pSampleLocationsInfo->pSampleLocations,
4089 pSampleLocationsInfo->sampleLocationsCount);
4090
4091 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
4092 }
4093
4094 void radv_CmdExecuteCommands(
4095 VkCommandBuffer commandBuffer,
4096 uint32_t commandBufferCount,
4097 const VkCommandBuffer* pCmdBuffers)
4098 {
4099 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4100
4101 assert(commandBufferCount > 0);
4102
4103 /* Emit pending flushes on primary prior to executing secondary */
4104 si_emit_cache_flush(primary);
4105
4106 for (uint32_t i = 0; i < commandBufferCount; i++) {
4107 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4108
4109 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4110 secondary->scratch_size_per_wave_needed);
4111 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4112 secondary->scratch_waves_wanted);
4113 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4114 secondary->compute_scratch_size_per_wave_needed);
4115 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4116 secondary->compute_scratch_waves_wanted);
4117
4118 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4119 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4120 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4121 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4122 if (secondary->tess_rings_needed)
4123 primary->tess_rings_needed = true;
4124 if (secondary->sample_positions_needed)
4125 primary->sample_positions_needed = true;
4126 if (secondary->gds_needed)
4127 primary->gds_needed = true;
4128
4129 if (!secondary->state.framebuffer &&
4130 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4131 /* Emit the framebuffer state from primary if secondary
4132 * has been recorded without a framebuffer, otherwise
4133 * fast color/depth clears can't work.
4134 */
4135 radv_emit_framebuffer_state(primary);
4136 }
4137
4138 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4139
4140
4141 /* When the secondary command buffer is compute only we don't
4142 * need to re-emit the current graphics pipeline.
4143 */
4144 if (secondary->state.emitted_pipeline) {
4145 primary->state.emitted_pipeline =
4146 secondary->state.emitted_pipeline;
4147 }
4148
4149 /* When the secondary command buffer is graphics only we don't
4150 * need to re-emit the current compute pipeline.
4151 */
4152 if (secondary->state.emitted_compute_pipeline) {
4153 primary->state.emitted_compute_pipeline =
4154 secondary->state.emitted_compute_pipeline;
4155 }
4156
4157 /* Only re-emit the draw packets when needed. */
4158 if (secondary->state.last_primitive_reset_en != -1) {
4159 primary->state.last_primitive_reset_en =
4160 secondary->state.last_primitive_reset_en;
4161 }
4162
4163 if (secondary->state.last_primitive_reset_index) {
4164 primary->state.last_primitive_reset_index =
4165 secondary->state.last_primitive_reset_index;
4166 }
4167
4168 if (secondary->state.last_ia_multi_vgt_param) {
4169 primary->state.last_ia_multi_vgt_param =
4170 secondary->state.last_ia_multi_vgt_param;
4171 }
4172
4173 primary->state.last_first_instance = secondary->state.last_first_instance;
4174 primary->state.last_num_instances = secondary->state.last_num_instances;
4175 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4176
4177 if (secondary->state.last_index_type != -1) {
4178 primary->state.last_index_type =
4179 secondary->state.last_index_type;
4180 }
4181 }
4182
4183 /* After executing commands from secondary buffers we have to dirty
4184 * some states.
4185 */
4186 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4187 RADV_CMD_DIRTY_INDEX_BUFFER |
4188 RADV_CMD_DIRTY_DYNAMIC_ALL;
4189 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4190 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4191 }
4192
4193 VkResult radv_CreateCommandPool(
4194 VkDevice _device,
4195 const VkCommandPoolCreateInfo* pCreateInfo,
4196 const VkAllocationCallbacks* pAllocator,
4197 VkCommandPool* pCmdPool)
4198 {
4199 RADV_FROM_HANDLE(radv_device, device, _device);
4200 struct radv_cmd_pool *pool;
4201
4202 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
4203 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4204 if (pool == NULL)
4205 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4206
4207 if (pAllocator)
4208 pool->alloc = *pAllocator;
4209 else
4210 pool->alloc = device->alloc;
4211
4212 list_inithead(&pool->cmd_buffers);
4213 list_inithead(&pool->free_cmd_buffers);
4214
4215 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4216
4217 *pCmdPool = radv_cmd_pool_to_handle(pool);
4218
4219 return VK_SUCCESS;
4220
4221 }
4222
4223 void radv_DestroyCommandPool(
4224 VkDevice _device,
4225 VkCommandPool commandPool,
4226 const VkAllocationCallbacks* pAllocator)
4227 {
4228 RADV_FROM_HANDLE(radv_device, device, _device);
4229 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4230
4231 if (!pool)
4232 return;
4233
4234 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4235 &pool->cmd_buffers, pool_link) {
4236 radv_cmd_buffer_destroy(cmd_buffer);
4237 }
4238
4239 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4240 &pool->free_cmd_buffers, pool_link) {
4241 radv_cmd_buffer_destroy(cmd_buffer);
4242 }
4243
4244 vk_free2(&device->alloc, pAllocator, pool);
4245 }
4246
4247 VkResult radv_ResetCommandPool(
4248 VkDevice device,
4249 VkCommandPool commandPool,
4250 VkCommandPoolResetFlags flags)
4251 {
4252 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4253 VkResult result;
4254
4255 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4256 &pool->cmd_buffers, pool_link) {
4257 result = radv_reset_cmd_buffer(cmd_buffer);
4258 if (result != VK_SUCCESS)
4259 return result;
4260 }
4261
4262 return VK_SUCCESS;
4263 }
4264
4265 void radv_TrimCommandPool(
4266 VkDevice device,
4267 VkCommandPool commandPool,
4268 VkCommandPoolTrimFlags flags)
4269 {
4270 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4271
4272 if (!pool)
4273 return;
4274
4275 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4276 &pool->free_cmd_buffers, pool_link) {
4277 radv_cmd_buffer_destroy(cmd_buffer);
4278 }
4279 }
4280
4281 static void
4282 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4283 uint32_t subpass_id)
4284 {
4285 struct radv_cmd_state *state = &cmd_buffer->state;
4286 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4287
4288 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4289 cmd_buffer->cs, 4096);
4290
4291 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4292
4293 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4294
4295 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4296 const uint32_t a = subpass->attachments[i].attachment;
4297 if (a == VK_ATTACHMENT_UNUSED)
4298 continue;
4299
4300 radv_handle_subpass_image_transition(cmd_buffer,
4301 subpass->attachments[i],
4302 true);
4303 }
4304
4305 radv_cmd_buffer_clear_subpass(cmd_buffer);
4306
4307 assert(cmd_buffer->cs->cdw <= cdw_max);
4308 }
4309
4310 static void
4311 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4312 {
4313 struct radv_cmd_state *state = &cmd_buffer->state;
4314 const struct radv_subpass *subpass = state->subpass;
4315 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4316
4317 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4318
4319 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4320 const uint32_t a = subpass->attachments[i].attachment;
4321 if (a == VK_ATTACHMENT_UNUSED)
4322 continue;
4323
4324 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4325 continue;
4326
4327 VkImageLayout layout = state->pass->attachments[a].final_layout;
4328 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
4329 struct radv_subpass_attachment att = { a, layout, stencil_layout };
4330 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4331 }
4332 }
4333
4334 void radv_CmdBeginRenderPass(
4335 VkCommandBuffer commandBuffer,
4336 const VkRenderPassBeginInfo* pRenderPassBegin,
4337 VkSubpassContents contents)
4338 {
4339 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4340 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4341 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4342 VkResult result;
4343
4344 cmd_buffer->state.framebuffer = framebuffer;
4345 cmd_buffer->state.pass = pass;
4346 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4347
4348 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4349 if (result != VK_SUCCESS)
4350 return;
4351
4352 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4353 if (result != VK_SUCCESS)
4354 return;
4355
4356 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4357 }
4358
4359 void radv_CmdBeginRenderPass2(
4360 VkCommandBuffer commandBuffer,
4361 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4362 const VkSubpassBeginInfo* pSubpassBeginInfo)
4363 {
4364 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4365 pSubpassBeginInfo->contents);
4366 }
4367
4368 void radv_CmdNextSubpass(
4369 VkCommandBuffer commandBuffer,
4370 VkSubpassContents contents)
4371 {
4372 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4373
4374 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4375 radv_cmd_buffer_end_subpass(cmd_buffer);
4376 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4377 }
4378
4379 void radv_CmdNextSubpass2(
4380 VkCommandBuffer commandBuffer,
4381 const VkSubpassBeginInfo* pSubpassBeginInfo,
4382 const VkSubpassEndInfo* pSubpassEndInfo)
4383 {
4384 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4385 }
4386
4387 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4388 {
4389 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4390 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4391 if (!radv_get_shader(pipeline, stage))
4392 continue;
4393
4394 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4395 if (loc->sgpr_idx == -1)
4396 continue;
4397 uint32_t base_reg = pipeline->user_data_0[stage];
4398 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4399
4400 }
4401 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4402 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4403 if (loc->sgpr_idx != -1) {
4404 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4405 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4406 }
4407 }
4408 }
4409
4410 static void
4411 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4412 uint32_t vertex_count,
4413 bool use_opaque)
4414 {
4415 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4416 radeon_emit(cmd_buffer->cs, vertex_count);
4417 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4418 S_0287F0_USE_OPAQUE(use_opaque));
4419 }
4420
4421 static void
4422 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4423 uint64_t index_va,
4424 uint32_t index_count)
4425 {
4426 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4427 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4428 radeon_emit(cmd_buffer->cs, index_va);
4429 radeon_emit(cmd_buffer->cs, index_va >> 32);
4430 radeon_emit(cmd_buffer->cs, index_count);
4431 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4432 }
4433
4434 static void
4435 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4436 bool indexed,
4437 uint32_t draw_count,
4438 uint64_t count_va,
4439 uint32_t stride)
4440 {
4441 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4442 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4443 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4444 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4445 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4446 bool predicating = cmd_buffer->state.predicating;
4447 assert(base_reg);
4448
4449 /* just reset draw state for vertex data */
4450 cmd_buffer->state.last_first_instance = -1;
4451 cmd_buffer->state.last_num_instances = -1;
4452 cmd_buffer->state.last_vertex_offset = -1;
4453
4454 if (draw_count == 1 && !count_va && !draw_id_enable) {
4455 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4456 PKT3_DRAW_INDIRECT, 3, predicating));
4457 radeon_emit(cs, 0);
4458 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4459 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4460 radeon_emit(cs, di_src_sel);
4461 } else {
4462 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4463 PKT3_DRAW_INDIRECT_MULTI,
4464 8, predicating));
4465 radeon_emit(cs, 0);
4466 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4467 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4468 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4469 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4470 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4471 radeon_emit(cs, draw_count); /* count */
4472 radeon_emit(cs, count_va); /* count_addr */
4473 radeon_emit(cs, count_va >> 32);
4474 radeon_emit(cs, stride); /* stride */
4475 radeon_emit(cs, di_src_sel);
4476 }
4477 }
4478
4479 static void
4480 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4481 const struct radv_draw_info *info)
4482 {
4483 struct radv_cmd_state *state = &cmd_buffer->state;
4484 struct radeon_winsys *ws = cmd_buffer->device->ws;
4485 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4486
4487 if (info->indirect) {
4488 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4489 uint64_t count_va = 0;
4490
4491 va += info->indirect->offset + info->indirect_offset;
4492
4493 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4494
4495 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4496 radeon_emit(cs, 1);
4497 radeon_emit(cs, va);
4498 radeon_emit(cs, va >> 32);
4499
4500 if (info->count_buffer) {
4501 count_va = radv_buffer_get_va(info->count_buffer->bo);
4502 count_va += info->count_buffer->offset +
4503 info->count_buffer_offset;
4504
4505 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4506 }
4507
4508 if (!state->subpass->view_mask) {
4509 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4510 info->indexed,
4511 info->count,
4512 count_va,
4513 info->stride);
4514 } else {
4515 unsigned i;
4516 for_each_bit(i, state->subpass->view_mask) {
4517 radv_emit_view_index(cmd_buffer, i);
4518
4519 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4520 info->indexed,
4521 info->count,
4522 count_va,
4523 info->stride);
4524 }
4525 }
4526 } else {
4527 assert(state->pipeline->graphics.vtx_base_sgpr);
4528
4529 if (info->vertex_offset != state->last_vertex_offset ||
4530 info->first_instance != state->last_first_instance) {
4531 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4532 state->pipeline->graphics.vtx_emit_num);
4533
4534 radeon_emit(cs, info->vertex_offset);
4535 radeon_emit(cs, info->first_instance);
4536 if (state->pipeline->graphics.vtx_emit_num == 3)
4537 radeon_emit(cs, 0);
4538 state->last_first_instance = info->first_instance;
4539 state->last_vertex_offset = info->vertex_offset;
4540 }
4541
4542 if (state->last_num_instances != info->instance_count) {
4543 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4544 radeon_emit(cs, info->instance_count);
4545 state->last_num_instances = info->instance_count;
4546 }
4547
4548 if (info->indexed) {
4549 int index_size = radv_get_vgt_index_size(state->index_type);
4550 uint64_t index_va;
4551
4552 /* Skip draw calls with 0-sized index buffers. They
4553 * cause a hang on some chips, like Navi10-14.
4554 */
4555 if (!cmd_buffer->state.max_index_count)
4556 return;
4557
4558 index_va = state->index_va;
4559 index_va += info->first_index * index_size;
4560
4561 if (!state->subpass->view_mask) {
4562 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4563 index_va,
4564 info->count);
4565 } else {
4566 unsigned i;
4567 for_each_bit(i, state->subpass->view_mask) {
4568 radv_emit_view_index(cmd_buffer, i);
4569
4570 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4571 index_va,
4572 info->count);
4573 }
4574 }
4575 } else {
4576 if (!state->subpass->view_mask) {
4577 radv_cs_emit_draw_packet(cmd_buffer,
4578 info->count,
4579 !!info->strmout_buffer);
4580 } else {
4581 unsigned i;
4582 for_each_bit(i, state->subpass->view_mask) {
4583 radv_emit_view_index(cmd_buffer, i);
4584
4585 radv_cs_emit_draw_packet(cmd_buffer,
4586 info->count,
4587 !!info->strmout_buffer);
4588 }
4589 }
4590 }
4591 }
4592 }
4593
4594 /*
4595 * Vega and raven have a bug which triggers if there are multiple context
4596 * register contexts active at the same time with different scissor values.
4597 *
4598 * There are two possible workarounds:
4599 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4600 * there is only ever 1 active set of scissor values at the same time.
4601 *
4602 * 2) Whenever the hardware switches contexts we have to set the scissor
4603 * registers again even if it is a noop. That way the new context gets
4604 * the correct scissor values.
4605 *
4606 * This implements option 2. radv_need_late_scissor_emission needs to
4607 * return true on affected HW if radv_emit_all_graphics_states sets
4608 * any context registers.
4609 */
4610 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4611 const struct radv_draw_info *info)
4612 {
4613 struct radv_cmd_state *state = &cmd_buffer->state;
4614
4615 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
4616 return false;
4617
4618 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4619 return true;
4620
4621 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4622
4623 /* Index, vertex and streamout buffers don't change context regs, and
4624 * pipeline is already handled.
4625 */
4626 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4627 RADV_CMD_DIRTY_VERTEX_BUFFER |
4628 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4629 RADV_CMD_DIRTY_PIPELINE);
4630
4631 if (cmd_buffer->state.dirty & used_states)
4632 return true;
4633
4634 uint32_t primitive_reset_index =
4635 radv_get_primitive_reset_index(cmd_buffer);
4636
4637 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4638 primitive_reset_index != state->last_primitive_reset_index)
4639 return true;
4640
4641 return false;
4642 }
4643
4644 static void
4645 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4646 const struct radv_draw_info *info)
4647 {
4648 bool late_scissor_emission;
4649
4650 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4651 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4652 radv_emit_rbplus_state(cmd_buffer);
4653
4654 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4655 radv_emit_graphics_pipeline(cmd_buffer);
4656
4657 /* This should be before the cmd_buffer->state.dirty is cleared
4658 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4659 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4660 late_scissor_emission =
4661 radv_need_late_scissor_emission(cmd_buffer, info);
4662
4663 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4664 radv_emit_framebuffer_state(cmd_buffer);
4665
4666 if (info->indexed) {
4667 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4668 radv_emit_index_buffer(cmd_buffer);
4669 } else {
4670 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4671 * so the state must be re-emitted before the next indexed
4672 * draw.
4673 */
4674 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4675 cmd_buffer->state.last_index_type = -1;
4676 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4677 }
4678 }
4679
4680 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4681
4682 radv_emit_draw_registers(cmd_buffer, info);
4683
4684 if (late_scissor_emission)
4685 radv_emit_scissor(cmd_buffer);
4686 }
4687
4688 static void
4689 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4690 const struct radv_draw_info *info)
4691 {
4692 struct radeon_info *rad_info =
4693 &cmd_buffer->device->physical_device->rad_info;
4694 bool has_prefetch =
4695 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4696 bool pipeline_is_dirty =
4697 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4698 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4699
4700 ASSERTED unsigned cdw_max =
4701 radeon_check_space(cmd_buffer->device->ws,
4702 cmd_buffer->cs, 4096);
4703
4704 if (likely(!info->indirect)) {
4705 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4706 * no workaround for indirect draws, but we can at least skip
4707 * direct draws.
4708 */
4709 if (unlikely(!info->instance_count))
4710 return;
4711
4712 /* Handle count == 0. */
4713 if (unlikely(!info->count && !info->strmout_buffer))
4714 return;
4715 }
4716
4717 /* Use optimal packet order based on whether we need to sync the
4718 * pipeline.
4719 */
4720 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4721 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4722 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4723 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4724 /* If we have to wait for idle, set all states first, so that
4725 * all SET packets are processed in parallel with previous draw
4726 * calls. Then upload descriptors, set shader pointers, and
4727 * draw, and prefetch at the end. This ensures that the time
4728 * the CUs are idle is very short. (there are only SET_SH
4729 * packets between the wait and the draw)
4730 */
4731 radv_emit_all_graphics_states(cmd_buffer, info);
4732 si_emit_cache_flush(cmd_buffer);
4733 /* <-- CUs are idle here --> */
4734
4735 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4736
4737 radv_emit_draw_packets(cmd_buffer, info);
4738 /* <-- CUs are busy here --> */
4739
4740 /* Start prefetches after the draw has been started. Both will
4741 * run in parallel, but starting the draw first is more
4742 * important.
4743 */
4744 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4745 radv_emit_prefetch_L2(cmd_buffer,
4746 cmd_buffer->state.pipeline, false);
4747 }
4748 } else {
4749 /* If we don't wait for idle, start prefetches first, then set
4750 * states, and draw at the end.
4751 */
4752 si_emit_cache_flush(cmd_buffer);
4753
4754 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4755 /* Only prefetch the vertex shader and VBO descriptors
4756 * in order to start the draw as soon as possible.
4757 */
4758 radv_emit_prefetch_L2(cmd_buffer,
4759 cmd_buffer->state.pipeline, true);
4760 }
4761
4762 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4763
4764 radv_emit_all_graphics_states(cmd_buffer, info);
4765 radv_emit_draw_packets(cmd_buffer, info);
4766
4767 /* Prefetch the remaining shaders after the draw has been
4768 * started.
4769 */
4770 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4771 radv_emit_prefetch_L2(cmd_buffer,
4772 cmd_buffer->state.pipeline, false);
4773 }
4774 }
4775
4776 /* Workaround for a VGT hang when streamout is enabled.
4777 * It must be done after drawing.
4778 */
4779 if (cmd_buffer->state.streamout.streamout_enabled &&
4780 (rad_info->family == CHIP_HAWAII ||
4781 rad_info->family == CHIP_TONGA ||
4782 rad_info->family == CHIP_FIJI)) {
4783 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4784 }
4785
4786 assert(cmd_buffer->cs->cdw <= cdw_max);
4787 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4788 }
4789
4790 void radv_CmdDraw(
4791 VkCommandBuffer commandBuffer,
4792 uint32_t vertexCount,
4793 uint32_t instanceCount,
4794 uint32_t firstVertex,
4795 uint32_t firstInstance)
4796 {
4797 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4798 struct radv_draw_info info = {};
4799
4800 info.count = vertexCount;
4801 info.instance_count = instanceCount;
4802 info.first_instance = firstInstance;
4803 info.vertex_offset = firstVertex;
4804
4805 radv_draw(cmd_buffer, &info);
4806 }
4807
4808 void radv_CmdDrawIndexed(
4809 VkCommandBuffer commandBuffer,
4810 uint32_t indexCount,
4811 uint32_t instanceCount,
4812 uint32_t firstIndex,
4813 int32_t vertexOffset,
4814 uint32_t firstInstance)
4815 {
4816 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4817 struct radv_draw_info info = {};
4818
4819 info.indexed = true;
4820 info.count = indexCount;
4821 info.instance_count = instanceCount;
4822 info.first_index = firstIndex;
4823 info.vertex_offset = vertexOffset;
4824 info.first_instance = firstInstance;
4825
4826 radv_draw(cmd_buffer, &info);
4827 }
4828
4829 void radv_CmdDrawIndirect(
4830 VkCommandBuffer commandBuffer,
4831 VkBuffer _buffer,
4832 VkDeviceSize offset,
4833 uint32_t drawCount,
4834 uint32_t stride)
4835 {
4836 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4837 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4838 struct radv_draw_info info = {};
4839
4840 info.count = drawCount;
4841 info.indirect = buffer;
4842 info.indirect_offset = offset;
4843 info.stride = stride;
4844
4845 radv_draw(cmd_buffer, &info);
4846 }
4847
4848 void radv_CmdDrawIndexedIndirect(
4849 VkCommandBuffer commandBuffer,
4850 VkBuffer _buffer,
4851 VkDeviceSize offset,
4852 uint32_t drawCount,
4853 uint32_t stride)
4854 {
4855 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4856 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4857 struct radv_draw_info info = {};
4858
4859 info.indexed = true;
4860 info.count = drawCount;
4861 info.indirect = buffer;
4862 info.indirect_offset = offset;
4863 info.stride = stride;
4864
4865 radv_draw(cmd_buffer, &info);
4866 }
4867
4868 void radv_CmdDrawIndirectCount(
4869 VkCommandBuffer commandBuffer,
4870 VkBuffer _buffer,
4871 VkDeviceSize offset,
4872 VkBuffer _countBuffer,
4873 VkDeviceSize countBufferOffset,
4874 uint32_t maxDrawCount,
4875 uint32_t stride)
4876 {
4877 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4878 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4879 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4880 struct radv_draw_info info = {};
4881
4882 info.count = maxDrawCount;
4883 info.indirect = buffer;
4884 info.indirect_offset = offset;
4885 info.count_buffer = count_buffer;
4886 info.count_buffer_offset = countBufferOffset;
4887 info.stride = stride;
4888
4889 radv_draw(cmd_buffer, &info);
4890 }
4891
4892 void radv_CmdDrawIndexedIndirectCount(
4893 VkCommandBuffer commandBuffer,
4894 VkBuffer _buffer,
4895 VkDeviceSize offset,
4896 VkBuffer _countBuffer,
4897 VkDeviceSize countBufferOffset,
4898 uint32_t maxDrawCount,
4899 uint32_t stride)
4900 {
4901 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4902 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4903 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4904 struct radv_draw_info info = {};
4905
4906 info.indexed = true;
4907 info.count = maxDrawCount;
4908 info.indirect = buffer;
4909 info.indirect_offset = offset;
4910 info.count_buffer = count_buffer;
4911 info.count_buffer_offset = countBufferOffset;
4912 info.stride = stride;
4913
4914 radv_draw(cmd_buffer, &info);
4915 }
4916
4917 struct radv_dispatch_info {
4918 /**
4919 * Determine the layout of the grid (in block units) to be used.
4920 */
4921 uint32_t blocks[3];
4922
4923 /**
4924 * A starting offset for the grid. If unaligned is set, the offset
4925 * must still be aligned.
4926 */
4927 uint32_t offsets[3];
4928 /**
4929 * Whether it's an unaligned compute dispatch.
4930 */
4931 bool unaligned;
4932
4933 /**
4934 * Indirect compute parameters resource.
4935 */
4936 struct radv_buffer *indirect;
4937 uint64_t indirect_offset;
4938 };
4939
4940 static void
4941 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4942 const struct radv_dispatch_info *info)
4943 {
4944 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4945 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4946 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4947 struct radeon_winsys *ws = cmd_buffer->device->ws;
4948 bool predicating = cmd_buffer->state.predicating;
4949 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4950 struct radv_userdata_info *loc;
4951
4952 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4953 AC_UD_CS_GRID_SIZE);
4954
4955 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4956
4957 if (compute_shader->info.wave_size == 32) {
4958 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
4959 dispatch_initiator |= S_00B800_CS_W32_EN(1);
4960 }
4961
4962 if (info->indirect) {
4963 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4964
4965 va += info->indirect->offset + info->indirect_offset;
4966
4967 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4968
4969 if (loc->sgpr_idx != -1) {
4970 for (unsigned i = 0; i < 3; ++i) {
4971 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4972 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4973 COPY_DATA_DST_SEL(COPY_DATA_REG));
4974 radeon_emit(cs, (va + 4 * i));
4975 radeon_emit(cs, (va + 4 * i) >> 32);
4976 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4977 + loc->sgpr_idx * 4) >> 2) + i);
4978 radeon_emit(cs, 0);
4979 }
4980 }
4981
4982 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4983 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4984 PKT3_SHADER_TYPE_S(1));
4985 radeon_emit(cs, va);
4986 radeon_emit(cs, va >> 32);
4987 radeon_emit(cs, dispatch_initiator);
4988 } else {
4989 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4990 PKT3_SHADER_TYPE_S(1));
4991 radeon_emit(cs, 1);
4992 radeon_emit(cs, va);
4993 radeon_emit(cs, va >> 32);
4994
4995 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4996 PKT3_SHADER_TYPE_S(1));
4997 radeon_emit(cs, 0);
4998 radeon_emit(cs, dispatch_initiator);
4999 }
5000 } else {
5001 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
5002 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
5003
5004 if (info->unaligned) {
5005 unsigned *cs_block_size = compute_shader->info.cs.block_size;
5006 unsigned remainder[3];
5007
5008 /* If aligned, these should be an entire block size,
5009 * not 0.
5010 */
5011 remainder[0] = blocks[0] + cs_block_size[0] -
5012 align_u32_npot(blocks[0], cs_block_size[0]);
5013 remainder[1] = blocks[1] + cs_block_size[1] -
5014 align_u32_npot(blocks[1], cs_block_size[1]);
5015 remainder[2] = blocks[2] + cs_block_size[2] -
5016 align_u32_npot(blocks[2], cs_block_size[2]);
5017
5018 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
5019 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
5020 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
5021
5022 for(unsigned i = 0; i < 3; ++i) {
5023 assert(offsets[i] % cs_block_size[i] == 0);
5024 offsets[i] /= cs_block_size[i];
5025 }
5026
5027 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5028 radeon_emit(cs,
5029 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
5030 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
5031 radeon_emit(cs,
5032 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
5033 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
5034 radeon_emit(cs,
5035 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
5036 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
5037
5038 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
5039 }
5040
5041 if (loc->sgpr_idx != -1) {
5042 assert(loc->num_sgprs == 3);
5043
5044 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
5045 loc->sgpr_idx * 4, 3);
5046 radeon_emit(cs, blocks[0]);
5047 radeon_emit(cs, blocks[1]);
5048 radeon_emit(cs, blocks[2]);
5049 }
5050
5051 if (offsets[0] || offsets[1] || offsets[2]) {
5052 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
5053 radeon_emit(cs, offsets[0]);
5054 radeon_emit(cs, offsets[1]);
5055 radeon_emit(cs, offsets[2]);
5056
5057 /* The blocks in the packet are not counts but end values. */
5058 for (unsigned i = 0; i < 3; ++i)
5059 blocks[i] += offsets[i];
5060 } else {
5061 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
5062 }
5063
5064 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
5065 PKT3_SHADER_TYPE_S(1));
5066 radeon_emit(cs, blocks[0]);
5067 radeon_emit(cs, blocks[1]);
5068 radeon_emit(cs, blocks[2]);
5069 radeon_emit(cs, dispatch_initiator);
5070 }
5071
5072 assert(cmd_buffer->cs->cdw <= cdw_max);
5073 }
5074
5075 static void
5076 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
5077 {
5078 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5079 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5080 }
5081
5082 static void
5083 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
5084 const struct radv_dispatch_info *info)
5085 {
5086 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5087 bool has_prefetch =
5088 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5089 bool pipeline_is_dirty = pipeline &&
5090 pipeline != cmd_buffer->state.emitted_compute_pipeline;
5091
5092 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5093 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5094 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5095 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5096 /* If we have to wait for idle, set all states first, so that
5097 * all SET packets are processed in parallel with previous draw
5098 * calls. Then upload descriptors, set shader pointers, and
5099 * dispatch, and prefetch at the end. This ensures that the
5100 * time the CUs are idle is very short. (there are only SET_SH
5101 * packets between the wait and the draw)
5102 */
5103 radv_emit_compute_pipeline(cmd_buffer);
5104 si_emit_cache_flush(cmd_buffer);
5105 /* <-- CUs are idle here --> */
5106
5107 radv_upload_compute_shader_descriptors(cmd_buffer);
5108
5109 radv_emit_dispatch_packets(cmd_buffer, info);
5110 /* <-- CUs are busy here --> */
5111
5112 /* Start prefetches after the dispatch has been started. Both
5113 * will run in parallel, but starting the dispatch first is
5114 * more important.
5115 */
5116 if (has_prefetch && pipeline_is_dirty) {
5117 radv_emit_shader_prefetch(cmd_buffer,
5118 pipeline->shaders[MESA_SHADER_COMPUTE]);
5119 }
5120 } else {
5121 /* If we don't wait for idle, start prefetches first, then set
5122 * states, and dispatch at the end.
5123 */
5124 si_emit_cache_flush(cmd_buffer);
5125
5126 if (has_prefetch && pipeline_is_dirty) {
5127 radv_emit_shader_prefetch(cmd_buffer,
5128 pipeline->shaders[MESA_SHADER_COMPUTE]);
5129 }
5130
5131 radv_upload_compute_shader_descriptors(cmd_buffer);
5132
5133 radv_emit_compute_pipeline(cmd_buffer);
5134 radv_emit_dispatch_packets(cmd_buffer, info);
5135 }
5136
5137 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5138 }
5139
5140 void radv_CmdDispatchBase(
5141 VkCommandBuffer commandBuffer,
5142 uint32_t base_x,
5143 uint32_t base_y,
5144 uint32_t base_z,
5145 uint32_t x,
5146 uint32_t y,
5147 uint32_t z)
5148 {
5149 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5150 struct radv_dispatch_info info = {};
5151
5152 info.blocks[0] = x;
5153 info.blocks[1] = y;
5154 info.blocks[2] = z;
5155
5156 info.offsets[0] = base_x;
5157 info.offsets[1] = base_y;
5158 info.offsets[2] = base_z;
5159 radv_dispatch(cmd_buffer, &info);
5160 }
5161
5162 void radv_CmdDispatch(
5163 VkCommandBuffer commandBuffer,
5164 uint32_t x,
5165 uint32_t y,
5166 uint32_t z)
5167 {
5168 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5169 }
5170
5171 void radv_CmdDispatchIndirect(
5172 VkCommandBuffer commandBuffer,
5173 VkBuffer _buffer,
5174 VkDeviceSize offset)
5175 {
5176 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5177 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5178 struct radv_dispatch_info info = {};
5179
5180 info.indirect = buffer;
5181 info.indirect_offset = offset;
5182
5183 radv_dispatch(cmd_buffer, &info);
5184 }
5185
5186 void radv_unaligned_dispatch(
5187 struct radv_cmd_buffer *cmd_buffer,
5188 uint32_t x,
5189 uint32_t y,
5190 uint32_t z)
5191 {
5192 struct radv_dispatch_info info = {};
5193
5194 info.blocks[0] = x;
5195 info.blocks[1] = y;
5196 info.blocks[2] = z;
5197 info.unaligned = 1;
5198
5199 radv_dispatch(cmd_buffer, &info);
5200 }
5201
5202 void radv_CmdEndRenderPass(
5203 VkCommandBuffer commandBuffer)
5204 {
5205 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5206
5207 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5208
5209 radv_cmd_buffer_end_subpass(cmd_buffer);
5210
5211 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5212 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5213
5214 cmd_buffer->state.pass = NULL;
5215 cmd_buffer->state.subpass = NULL;
5216 cmd_buffer->state.attachments = NULL;
5217 cmd_buffer->state.framebuffer = NULL;
5218 cmd_buffer->state.subpass_sample_locs = NULL;
5219 }
5220
5221 void radv_CmdEndRenderPass2(
5222 VkCommandBuffer commandBuffer,
5223 const VkSubpassEndInfo* pSubpassEndInfo)
5224 {
5225 radv_CmdEndRenderPass(commandBuffer);
5226 }
5227
5228 /*
5229 * For HTILE we have the following interesting clear words:
5230 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5231 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5232 * 0xfffffff0: Clear depth to 1.0
5233 * 0x00000000: Clear depth to 0.0
5234 */
5235 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5236 struct radv_image *image,
5237 const VkImageSubresourceRange *range)
5238 {
5239 assert(range->baseMipLevel == 0);
5240 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5241 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5242 struct radv_cmd_state *state = &cmd_buffer->state;
5243 uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5244 VkClearDepthStencilValue value = {};
5245
5246 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5247 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5248
5249 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
5250
5251 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5252
5253 if (vk_format_is_stencil(image->vk_format))
5254 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5255
5256 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5257
5258 if (radv_image_is_tc_compat_htile(image)) {
5259 /* Initialize the TC-compat metada value to 0 because by
5260 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5261 * need have to conditionally update its value when performing
5262 * a fast depth clear.
5263 */
5264 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5265 }
5266 }
5267
5268 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5269 struct radv_image *image,
5270 VkImageLayout src_layout,
5271 bool src_render_loop,
5272 VkImageLayout dst_layout,
5273 bool dst_render_loop,
5274 unsigned src_queue_mask,
5275 unsigned dst_queue_mask,
5276 const VkImageSubresourceRange *range,
5277 struct radv_sample_locations_state *sample_locs)
5278 {
5279 if (!radv_image_has_htile(image))
5280 return;
5281
5282 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5283 radv_initialize_htile(cmd_buffer, image, range);
5284 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5285 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5286 radv_initialize_htile(cmd_buffer, image, range);
5287 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5288 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5289 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5290 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5291
5292 radv_decompress_depth_image_inplace(cmd_buffer, image, range,
5293 sample_locs);
5294
5295 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5296 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5297 }
5298 }
5299
5300 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5301 struct radv_image *image,
5302 const VkImageSubresourceRange *range,
5303 uint32_t value)
5304 {
5305 struct radv_cmd_state *state = &cmd_buffer->state;
5306
5307 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5308 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5309
5310 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5311
5312 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5313 }
5314
5315 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5316 struct radv_image *image,
5317 const VkImageSubresourceRange *range)
5318 {
5319 struct radv_cmd_state *state = &cmd_buffer->state;
5320 static const uint32_t fmask_clear_values[4] = {
5321 0x00000000,
5322 0x02020202,
5323 0xE4E4E4E4,
5324 0x76543210
5325 };
5326 uint32_t log2_samples = util_logbase2(image->info.samples);
5327 uint32_t value = fmask_clear_values[log2_samples];
5328
5329 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5330 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5331
5332 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5333
5334 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5335 }
5336
5337 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5338 struct radv_image *image,
5339 const VkImageSubresourceRange *range, uint32_t value)
5340 {
5341 struct radv_cmd_state *state = &cmd_buffer->state;
5342 unsigned size = 0;
5343
5344 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5345 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5346
5347 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5348
5349 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5350 /* When DCC is enabled with mipmaps, some levels might not
5351 * support fast clears and we have to initialize them as "fully
5352 * expanded".
5353 */
5354 /* Compute the size of all fast clearable DCC levels. */
5355 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5356 struct legacy_surf_level *surf_level =
5357 &image->planes[0].surface.u.legacy.level[i];
5358 unsigned dcc_fast_clear_size =
5359 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5360
5361 if (!dcc_fast_clear_size)
5362 break;
5363
5364 size = surf_level->dcc_offset + dcc_fast_clear_size;
5365 }
5366
5367 /* Initialize the mipmap levels without DCC. */
5368 if (size != image->planes[0].surface.dcc_size) {
5369 state->flush_bits |=
5370 radv_fill_buffer(cmd_buffer, image->bo,
5371 image->offset + image->dcc_offset + size,
5372 image->planes[0].surface.dcc_size - size,
5373 0xffffffff);
5374 }
5375 }
5376
5377 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5378 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5379 }
5380
5381 /**
5382 * Initialize DCC/FMASK/CMASK metadata for a color image.
5383 */
5384 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5385 struct radv_image *image,
5386 VkImageLayout src_layout,
5387 bool src_render_loop,
5388 VkImageLayout dst_layout,
5389 bool dst_render_loop,
5390 unsigned src_queue_mask,
5391 unsigned dst_queue_mask,
5392 const VkImageSubresourceRange *range)
5393 {
5394 if (radv_image_has_cmask(image)) {
5395 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5396
5397 /* TODO: clarify this. */
5398 if (radv_image_has_fmask(image)) {
5399 value = 0xccccccccu;
5400 }
5401
5402 radv_initialise_cmask(cmd_buffer, image, range, value);
5403 }
5404
5405 if (radv_image_has_fmask(image)) {
5406 radv_initialize_fmask(cmd_buffer, image, range);
5407 }
5408
5409 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5410 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5411 bool need_decompress_pass = false;
5412
5413 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5414 dst_render_loop,
5415 dst_queue_mask)) {
5416 value = 0x20202020u;
5417 need_decompress_pass = true;
5418 }
5419
5420 radv_initialize_dcc(cmd_buffer, image, range, value);
5421
5422 radv_update_fce_metadata(cmd_buffer, image, range,
5423 need_decompress_pass);
5424 }
5425
5426 if (radv_image_has_cmask(image) ||
5427 radv_dcc_enabled(image, range->baseMipLevel)) {
5428 uint32_t color_values[2] = {};
5429 radv_set_color_clear_metadata(cmd_buffer, image, range,
5430 color_values);
5431 }
5432 }
5433
5434 /**
5435 * Handle color image transitions for DCC/FMASK/CMASK.
5436 */
5437 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5438 struct radv_image *image,
5439 VkImageLayout src_layout,
5440 bool src_render_loop,
5441 VkImageLayout dst_layout,
5442 bool dst_render_loop,
5443 unsigned src_queue_mask,
5444 unsigned dst_queue_mask,
5445 const VkImageSubresourceRange *range)
5446 {
5447 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5448 radv_init_color_image_metadata(cmd_buffer, image,
5449 src_layout, src_render_loop,
5450 dst_layout, dst_render_loop,
5451 src_queue_mask, dst_queue_mask,
5452 range);
5453 return;
5454 }
5455
5456 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5457 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5458 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5459 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5460 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5461 radv_decompress_dcc(cmd_buffer, image, range);
5462 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5463 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5464 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5465 }
5466 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5467 bool fce_eliminate = false, fmask_expand = false;
5468
5469 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5470 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5471 fce_eliminate = true;
5472 }
5473
5474 if (radv_image_has_fmask(image)) {
5475 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5476 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5477 /* A FMASK decompress is required before doing
5478 * a MSAA decompress using FMASK.
5479 */
5480 fmask_expand = true;
5481 }
5482 }
5483
5484 if (fce_eliminate || fmask_expand)
5485 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5486
5487 if (fmask_expand)
5488 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5489 }
5490 }
5491
5492 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5493 struct radv_image *image,
5494 VkImageLayout src_layout,
5495 bool src_render_loop,
5496 VkImageLayout dst_layout,
5497 bool dst_render_loop,
5498 uint32_t src_family,
5499 uint32_t dst_family,
5500 const VkImageSubresourceRange *range,
5501 struct radv_sample_locations_state *sample_locs)
5502 {
5503 if (image->exclusive && src_family != dst_family) {
5504 /* This is an acquire or a release operation and there will be
5505 * a corresponding release/acquire. Do the transition in the
5506 * most flexible queue. */
5507
5508 assert(src_family == cmd_buffer->queue_family_index ||
5509 dst_family == cmd_buffer->queue_family_index);
5510
5511 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5512 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5513 return;
5514
5515 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5516 return;
5517
5518 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5519 (src_family == RADV_QUEUE_GENERAL ||
5520 dst_family == RADV_QUEUE_GENERAL))
5521 return;
5522 }
5523
5524 if (src_layout == dst_layout)
5525 return;
5526
5527 unsigned src_queue_mask =
5528 radv_image_queue_family_mask(image, src_family,
5529 cmd_buffer->queue_family_index);
5530 unsigned dst_queue_mask =
5531 radv_image_queue_family_mask(image, dst_family,
5532 cmd_buffer->queue_family_index);
5533
5534 if (vk_format_is_depth(image->vk_format)) {
5535 radv_handle_depth_image_transition(cmd_buffer, image,
5536 src_layout, src_render_loop,
5537 dst_layout, dst_render_loop,
5538 src_queue_mask, dst_queue_mask,
5539 range, sample_locs);
5540 } else {
5541 radv_handle_color_image_transition(cmd_buffer, image,
5542 src_layout, src_render_loop,
5543 dst_layout, dst_render_loop,
5544 src_queue_mask, dst_queue_mask,
5545 range);
5546 }
5547 }
5548
5549 struct radv_barrier_info {
5550 uint32_t eventCount;
5551 const VkEvent *pEvents;
5552 VkPipelineStageFlags srcStageMask;
5553 VkPipelineStageFlags dstStageMask;
5554 };
5555
5556 static void
5557 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5558 uint32_t memoryBarrierCount,
5559 const VkMemoryBarrier *pMemoryBarriers,
5560 uint32_t bufferMemoryBarrierCount,
5561 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5562 uint32_t imageMemoryBarrierCount,
5563 const VkImageMemoryBarrier *pImageMemoryBarriers,
5564 const struct radv_barrier_info *info)
5565 {
5566 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5567 enum radv_cmd_flush_bits src_flush_bits = 0;
5568 enum radv_cmd_flush_bits dst_flush_bits = 0;
5569
5570 for (unsigned i = 0; i < info->eventCount; ++i) {
5571 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5572 uint64_t va = radv_buffer_get_va(event->bo);
5573
5574 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5575
5576 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5577
5578 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5579 assert(cmd_buffer->cs->cdw <= cdw_max);
5580 }
5581
5582 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5583 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5584 NULL);
5585 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5586 NULL);
5587 }
5588
5589 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5590 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5591 NULL);
5592 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5593 NULL);
5594 }
5595
5596 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5597 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5598
5599 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5600 image);
5601 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5602 image);
5603 }
5604
5605 /* The Vulkan spec 1.1.98 says:
5606 *
5607 * "An execution dependency with only
5608 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5609 * will only prevent that stage from executing in subsequently
5610 * submitted commands. As this stage does not perform any actual
5611 * execution, this is not observable - in effect, it does not delay
5612 * processing of subsequent commands. Similarly an execution dependency
5613 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5614 * will effectively not wait for any prior commands to complete."
5615 */
5616 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5617 radv_stage_flush(cmd_buffer, info->srcStageMask);
5618 cmd_buffer->state.flush_bits |= src_flush_bits;
5619
5620 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5621 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5622
5623 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5624 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5625 SAMPLE_LOCATIONS_INFO_EXT);
5626 struct radv_sample_locations_state sample_locations = {};
5627
5628 if (sample_locs_info) {
5629 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5630 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5631 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5632 sample_locations.count = sample_locs_info->sampleLocationsCount;
5633 typed_memcpy(&sample_locations.locations[0],
5634 sample_locs_info->pSampleLocations,
5635 sample_locs_info->sampleLocationsCount);
5636 }
5637
5638 radv_handle_image_transition(cmd_buffer, image,
5639 pImageMemoryBarriers[i].oldLayout,
5640 false, /* Outside of a renderpass we are never in a renderloop */
5641 pImageMemoryBarriers[i].newLayout,
5642 false, /* Outside of a renderpass we are never in a renderloop */
5643 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5644 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5645 &pImageMemoryBarriers[i].subresourceRange,
5646 sample_locs_info ? &sample_locations : NULL);
5647 }
5648
5649 /* Make sure CP DMA is idle because the driver might have performed a
5650 * DMA operation for copying or filling buffers/images.
5651 */
5652 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5653 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5654 si_cp_dma_wait_for_idle(cmd_buffer);
5655
5656 cmd_buffer->state.flush_bits |= dst_flush_bits;
5657 }
5658
5659 void radv_CmdPipelineBarrier(
5660 VkCommandBuffer commandBuffer,
5661 VkPipelineStageFlags srcStageMask,
5662 VkPipelineStageFlags destStageMask,
5663 VkBool32 byRegion,
5664 uint32_t memoryBarrierCount,
5665 const VkMemoryBarrier* pMemoryBarriers,
5666 uint32_t bufferMemoryBarrierCount,
5667 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5668 uint32_t imageMemoryBarrierCount,
5669 const VkImageMemoryBarrier* pImageMemoryBarriers)
5670 {
5671 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5672 struct radv_barrier_info info;
5673
5674 info.eventCount = 0;
5675 info.pEvents = NULL;
5676 info.srcStageMask = srcStageMask;
5677 info.dstStageMask = destStageMask;
5678
5679 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5680 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5681 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5682 }
5683
5684
5685 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5686 struct radv_event *event,
5687 VkPipelineStageFlags stageMask,
5688 unsigned value)
5689 {
5690 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5691 uint64_t va = radv_buffer_get_va(event->bo);
5692
5693 si_emit_cache_flush(cmd_buffer);
5694
5695 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5696
5697 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5698
5699 /* Flags that only require a top-of-pipe event. */
5700 VkPipelineStageFlags top_of_pipe_flags =
5701 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5702
5703 /* Flags that only require a post-index-fetch event. */
5704 VkPipelineStageFlags post_index_fetch_flags =
5705 top_of_pipe_flags |
5706 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5707 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5708
5709 /* Make sure CP DMA is idle because the driver might have performed a
5710 * DMA operation for copying or filling buffers/images.
5711 */
5712 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5713 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5714 si_cp_dma_wait_for_idle(cmd_buffer);
5715
5716 /* TODO: Emit EOS events for syncing PS/CS stages. */
5717
5718 if (!(stageMask & ~top_of_pipe_flags)) {
5719 /* Just need to sync the PFP engine. */
5720 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5721 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5722 S_370_WR_CONFIRM(1) |
5723 S_370_ENGINE_SEL(V_370_PFP));
5724 radeon_emit(cs, va);
5725 radeon_emit(cs, va >> 32);
5726 radeon_emit(cs, value);
5727 } else if (!(stageMask & ~post_index_fetch_flags)) {
5728 /* Sync ME because PFP reads index and indirect buffers. */
5729 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5730 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5731 S_370_WR_CONFIRM(1) |
5732 S_370_ENGINE_SEL(V_370_ME));
5733 radeon_emit(cs, va);
5734 radeon_emit(cs, va >> 32);
5735 radeon_emit(cs, value);
5736 } else {
5737 /* Otherwise, sync all prior GPU work using an EOP event. */
5738 si_cs_emit_write_event_eop(cs,
5739 cmd_buffer->device->physical_device->rad_info.chip_class,
5740 radv_cmd_buffer_uses_mec(cmd_buffer),
5741 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5742 EOP_DST_SEL_MEM,
5743 EOP_DATA_SEL_VALUE_32BIT, va, value,
5744 cmd_buffer->gfx9_eop_bug_va);
5745 }
5746
5747 assert(cmd_buffer->cs->cdw <= cdw_max);
5748 }
5749
5750 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5751 VkEvent _event,
5752 VkPipelineStageFlags stageMask)
5753 {
5754 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5755 RADV_FROM_HANDLE(radv_event, event, _event);
5756
5757 write_event(cmd_buffer, event, stageMask, 1);
5758 }
5759
5760 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5761 VkEvent _event,
5762 VkPipelineStageFlags stageMask)
5763 {
5764 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5765 RADV_FROM_HANDLE(radv_event, event, _event);
5766
5767 write_event(cmd_buffer, event, stageMask, 0);
5768 }
5769
5770 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5771 uint32_t eventCount,
5772 const VkEvent* pEvents,
5773 VkPipelineStageFlags srcStageMask,
5774 VkPipelineStageFlags dstStageMask,
5775 uint32_t memoryBarrierCount,
5776 const VkMemoryBarrier* pMemoryBarriers,
5777 uint32_t bufferMemoryBarrierCount,
5778 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5779 uint32_t imageMemoryBarrierCount,
5780 const VkImageMemoryBarrier* pImageMemoryBarriers)
5781 {
5782 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5783 struct radv_barrier_info info;
5784
5785 info.eventCount = eventCount;
5786 info.pEvents = pEvents;
5787 info.srcStageMask = 0;
5788
5789 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5790 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5791 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5792 }
5793
5794
5795 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5796 uint32_t deviceMask)
5797 {
5798 /* No-op */
5799 }
5800
5801 /* VK_EXT_conditional_rendering */
5802 void radv_CmdBeginConditionalRenderingEXT(
5803 VkCommandBuffer commandBuffer,
5804 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5805 {
5806 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5807 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5808 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5809 bool draw_visible = true;
5810 uint64_t pred_value = 0;
5811 uint64_t va, new_va;
5812 unsigned pred_offset;
5813
5814 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5815
5816 /* By default, if the 32-bit value at offset in buffer memory is zero,
5817 * then the rendering commands are discarded, otherwise they are
5818 * executed as normal. If the inverted flag is set, all commands are
5819 * discarded if the value is non zero.
5820 */
5821 if (pConditionalRenderingBegin->flags &
5822 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5823 draw_visible = false;
5824 }
5825
5826 si_emit_cache_flush(cmd_buffer);
5827
5828 /* From the Vulkan spec 1.1.107:
5829 *
5830 * "If the 32-bit value at offset in buffer memory is zero, then the
5831 * rendering commands are discarded, otherwise they are executed as
5832 * normal. If the value of the predicate in buffer memory changes while
5833 * conditional rendering is active, the rendering commands may be
5834 * discarded in an implementation-dependent way. Some implementations
5835 * may latch the value of the predicate upon beginning conditional
5836 * rendering while others may read it before every rendering command."
5837 *
5838 * But, the AMD hardware treats the predicate as a 64-bit value which
5839 * means we need a workaround in the driver. Luckily, it's not required
5840 * to support if the value changes when predication is active.
5841 *
5842 * The workaround is as follows:
5843 * 1) allocate a 64-value in the upload BO and initialize it to 0
5844 * 2) copy the 32-bit predicate value to the upload BO
5845 * 3) use the new allocated VA address for predication
5846 *
5847 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5848 * in ME (+ sync PFP) instead of PFP.
5849 */
5850 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5851
5852 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5853
5854 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5855 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5856 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5857 COPY_DATA_WR_CONFIRM);
5858 radeon_emit(cs, va);
5859 radeon_emit(cs, va >> 32);
5860 radeon_emit(cs, new_va);
5861 radeon_emit(cs, new_va >> 32);
5862
5863 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5864 radeon_emit(cs, 0);
5865
5866 /* Enable predication for this command buffer. */
5867 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5868 cmd_buffer->state.predicating = true;
5869
5870 /* Store conditional rendering user info. */
5871 cmd_buffer->state.predication_type = draw_visible;
5872 cmd_buffer->state.predication_va = new_va;
5873 }
5874
5875 void radv_CmdEndConditionalRenderingEXT(
5876 VkCommandBuffer commandBuffer)
5877 {
5878 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5879
5880 /* Disable predication for this command buffer. */
5881 si_emit_set_predication_state(cmd_buffer, false, 0);
5882 cmd_buffer->state.predicating = false;
5883
5884 /* Reset conditional rendering user info. */
5885 cmd_buffer->state.predication_type = -1;
5886 cmd_buffer->state.predication_va = 0;
5887 }
5888
5889 /* VK_EXT_transform_feedback */
5890 void radv_CmdBindTransformFeedbackBuffersEXT(
5891 VkCommandBuffer commandBuffer,
5892 uint32_t firstBinding,
5893 uint32_t bindingCount,
5894 const VkBuffer* pBuffers,
5895 const VkDeviceSize* pOffsets,
5896 const VkDeviceSize* pSizes)
5897 {
5898 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5899 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5900 uint8_t enabled_mask = 0;
5901
5902 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5903 for (uint32_t i = 0; i < bindingCount; i++) {
5904 uint32_t idx = firstBinding + i;
5905
5906 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5907 sb[idx].offset = pOffsets[i];
5908 sb[idx].size = pSizes[i];
5909
5910 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5911 sb[idx].buffer->bo);
5912
5913 enabled_mask |= 1 << idx;
5914 }
5915
5916 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5917
5918 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5919 }
5920
5921 static void
5922 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5923 {
5924 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5925 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5926
5927 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5928 radeon_emit(cs,
5929 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5930 S_028B94_RAST_STREAM(0) |
5931 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5932 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5933 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5934 radeon_emit(cs, so->hw_enabled_mask &
5935 so->enabled_stream_buffers_mask);
5936
5937 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5938 }
5939
5940 static void
5941 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5942 {
5943 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5944 bool old_streamout_enabled = so->streamout_enabled;
5945 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5946
5947 so->streamout_enabled = enable;
5948
5949 so->hw_enabled_mask = so->enabled_mask |
5950 (so->enabled_mask << 4) |
5951 (so->enabled_mask << 8) |
5952 (so->enabled_mask << 12);
5953
5954 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
5955 ((old_streamout_enabled != so->streamout_enabled) ||
5956 (old_hw_enabled_mask != so->hw_enabled_mask)))
5957 radv_emit_streamout_enable(cmd_buffer);
5958
5959 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
5960 cmd_buffer->gds_needed = true;
5961 cmd_buffer->gds_oa_needed = true;
5962 }
5963 }
5964
5965 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5966 {
5967 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5968 unsigned reg_strmout_cntl;
5969
5970 /* The register is at different places on different ASICs. */
5971 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5972 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5973 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5974 } else {
5975 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5976 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5977 }
5978
5979 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5980 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5981
5982 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5983 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5984 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5985 radeon_emit(cs, 0);
5986 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5987 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5988 radeon_emit(cs, 4); /* poll interval */
5989 }
5990
5991 static void
5992 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5993 uint32_t firstCounterBuffer,
5994 uint32_t counterBufferCount,
5995 const VkBuffer *pCounterBuffers,
5996 const VkDeviceSize *pCounterBufferOffsets)
5997
5998 {
5999 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6000 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6001 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6002 uint32_t i;
6003
6004 radv_flush_vgt_streamout(cmd_buffer);
6005
6006 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6007 for_each_bit(i, so->enabled_mask) {
6008 int32_t counter_buffer_idx = i - firstCounterBuffer;
6009 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6010 counter_buffer_idx = -1;
6011
6012 /* AMD GCN binds streamout buffers as shader resources.
6013 * VGT only counts primitives and tells the shader through
6014 * SGPRs what to do.
6015 */
6016 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
6017 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
6018 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
6019
6020 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6021
6022 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6023 /* The array of counter buffers is optional. */
6024 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6025 uint64_t va = radv_buffer_get_va(buffer->bo);
6026
6027 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6028
6029 /* Append */
6030 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6031 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6032 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6033 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
6034 radeon_emit(cs, 0); /* unused */
6035 radeon_emit(cs, 0); /* unused */
6036 radeon_emit(cs, va); /* src address lo */
6037 radeon_emit(cs, va >> 32); /* src address hi */
6038
6039 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6040 } else {
6041 /* Start from the beginning. */
6042 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6043 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6044 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6045 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
6046 radeon_emit(cs, 0); /* unused */
6047 radeon_emit(cs, 0); /* unused */
6048 radeon_emit(cs, 0); /* unused */
6049 radeon_emit(cs, 0); /* unused */
6050 }
6051 }
6052
6053 radv_set_streamout_enable(cmd_buffer, true);
6054 }
6055
6056 static void
6057 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6058 uint32_t firstCounterBuffer,
6059 uint32_t counterBufferCount,
6060 const VkBuffer *pCounterBuffers,
6061 const VkDeviceSize *pCounterBufferOffsets)
6062 {
6063 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6064 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
6065 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6066 uint32_t i;
6067
6068 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6069 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6070
6071 /* Sync because the next streamout operation will overwrite GDS and we
6072 * have to make sure it's idle.
6073 * TODO: Improve by tracking if there is a streamout operation in
6074 * flight.
6075 */
6076 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
6077 si_emit_cache_flush(cmd_buffer);
6078
6079 for_each_bit(i, so->enabled_mask) {
6080 int32_t counter_buffer_idx = i - firstCounterBuffer;
6081 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6082 counter_buffer_idx = -1;
6083
6084 bool append = counter_buffer_idx >= 0 &&
6085 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
6086 uint64_t va = 0;
6087
6088 if (append) {
6089 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6090
6091 va += radv_buffer_get_va(buffer->bo);
6092 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6093
6094 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6095 }
6096
6097 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6098 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6099 S_411_DST_SEL(V_411_GDS) |
6100 S_411_CP_SYNC(i == last_target));
6101 radeon_emit(cs, va);
6102 radeon_emit(cs, va >> 32);
6103 radeon_emit(cs, 4 * i); /* destination in GDS */
6104 radeon_emit(cs, 0);
6105 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6106 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6107 }
6108
6109 radv_set_streamout_enable(cmd_buffer, true);
6110 }
6111
6112 void radv_CmdBeginTransformFeedbackEXT(
6113 VkCommandBuffer commandBuffer,
6114 uint32_t firstCounterBuffer,
6115 uint32_t counterBufferCount,
6116 const VkBuffer* pCounterBuffers,
6117 const VkDeviceSize* pCounterBufferOffsets)
6118 {
6119 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6120
6121 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6122 gfx10_emit_streamout_begin(cmd_buffer,
6123 firstCounterBuffer, counterBufferCount,
6124 pCounterBuffers, pCounterBufferOffsets);
6125 } else {
6126 radv_emit_streamout_begin(cmd_buffer,
6127 firstCounterBuffer, counterBufferCount,
6128 pCounterBuffers, pCounterBufferOffsets);
6129 }
6130 }
6131
6132 static void
6133 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6134 uint32_t firstCounterBuffer,
6135 uint32_t counterBufferCount,
6136 const VkBuffer *pCounterBuffers,
6137 const VkDeviceSize *pCounterBufferOffsets)
6138 {
6139 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6140 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6141 uint32_t i;
6142
6143 radv_flush_vgt_streamout(cmd_buffer);
6144
6145 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6146 for_each_bit(i, so->enabled_mask) {
6147 int32_t counter_buffer_idx = i - firstCounterBuffer;
6148 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6149 counter_buffer_idx = -1;
6150
6151 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6152 /* The array of counters buffer is optional. */
6153 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6154 uint64_t va = radv_buffer_get_va(buffer->bo);
6155
6156 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6157
6158 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6159 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6160 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6161 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6162 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6163 radeon_emit(cs, va); /* dst address lo */
6164 radeon_emit(cs, va >> 32); /* dst address hi */
6165 radeon_emit(cs, 0); /* unused */
6166 radeon_emit(cs, 0); /* unused */
6167
6168 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6169 }
6170
6171 /* Deactivate transform feedback by zeroing the buffer size.
6172 * The counters (primitives generated, primitives emitted) may
6173 * be enabled even if there is not buffer bound. This ensures
6174 * that the primitives-emitted query won't increment.
6175 */
6176 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6177
6178 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6179 }
6180
6181 radv_set_streamout_enable(cmd_buffer, false);
6182 }
6183
6184 static void
6185 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6186 uint32_t firstCounterBuffer,
6187 uint32_t counterBufferCount,
6188 const VkBuffer *pCounterBuffers,
6189 const VkDeviceSize *pCounterBufferOffsets)
6190 {
6191 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6192 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6193 uint32_t i;
6194
6195 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6196 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6197
6198 for_each_bit(i, so->enabled_mask) {
6199 int32_t counter_buffer_idx = i - firstCounterBuffer;
6200 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6201 counter_buffer_idx = -1;
6202
6203 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6204 /* The array of counters buffer is optional. */
6205 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6206 uint64_t va = radv_buffer_get_va(buffer->bo);
6207
6208 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6209
6210 si_cs_emit_write_event_eop(cs,
6211 cmd_buffer->device->physical_device->rad_info.chip_class,
6212 radv_cmd_buffer_uses_mec(cmd_buffer),
6213 V_028A90_PS_DONE, 0,
6214 EOP_DST_SEL_TC_L2,
6215 EOP_DATA_SEL_GDS,
6216 va, EOP_DATA_GDS(i, 1), 0);
6217
6218 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6219 }
6220 }
6221
6222 radv_set_streamout_enable(cmd_buffer, false);
6223 }
6224
6225 void radv_CmdEndTransformFeedbackEXT(
6226 VkCommandBuffer commandBuffer,
6227 uint32_t firstCounterBuffer,
6228 uint32_t counterBufferCount,
6229 const VkBuffer* pCounterBuffers,
6230 const VkDeviceSize* pCounterBufferOffsets)
6231 {
6232 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6233
6234 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6235 gfx10_emit_streamout_end(cmd_buffer,
6236 firstCounterBuffer, counterBufferCount,
6237 pCounterBuffers, pCounterBufferOffsets);
6238 } else {
6239 radv_emit_streamout_end(cmd_buffer,
6240 firstCounterBuffer, counterBufferCount,
6241 pCounterBuffers, pCounterBufferOffsets);
6242 }
6243 }
6244
6245 void radv_CmdDrawIndirectByteCountEXT(
6246 VkCommandBuffer commandBuffer,
6247 uint32_t instanceCount,
6248 uint32_t firstInstance,
6249 VkBuffer _counterBuffer,
6250 VkDeviceSize counterBufferOffset,
6251 uint32_t counterOffset,
6252 uint32_t vertexStride)
6253 {
6254 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6255 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6256 struct radv_draw_info info = {};
6257
6258 info.instance_count = instanceCount;
6259 info.first_instance = firstInstance;
6260 info.strmout_buffer = counterBuffer;
6261 info.strmout_buffer_offset = counterBufferOffset;
6262 info.stride = vertexStride;
6263
6264 radv_draw(cmd_buffer, &info);
6265 }
6266
6267 /* VK_AMD_buffer_marker */
6268 void radv_CmdWriteBufferMarkerAMD(
6269 VkCommandBuffer commandBuffer,
6270 VkPipelineStageFlagBits pipelineStage,
6271 VkBuffer dstBuffer,
6272 VkDeviceSize dstOffset,
6273 uint32_t marker)
6274 {
6275 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6276 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6277 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6278 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6279
6280 si_emit_cache_flush(cmd_buffer);
6281
6282 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6283
6284 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6285 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6286 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6287 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6288 COPY_DATA_WR_CONFIRM);
6289 radeon_emit(cs, marker);
6290 radeon_emit(cs, 0);
6291 radeon_emit(cs, va);
6292 radeon_emit(cs, va >> 32);
6293 } else {
6294 si_cs_emit_write_event_eop(cs,
6295 cmd_buffer->device->physical_device->rad_info.chip_class,
6296 radv_cmd_buffer_uses_mec(cmd_buffer),
6297 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6298 EOP_DST_SEL_MEM,
6299 EOP_DATA_SEL_VALUE_32BIT,
6300 va, marker,
6301 cmd_buffer->gfx9_eop_bug_va);
6302 }
6303
6304 assert(cmd_buffer->cs->cdw <= cdw_max);
6305 }