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radv/gfx10: always build the GS copy shader but uses it on-demand
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 struct radv_sample_locations_state *sample_locs);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109 dest->sample_location.count = src->sample_location.count;
110
111 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
112 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
113 src->viewport.count * sizeof(VkViewport))) {
114 typed_memcpy(dest->viewport.viewports,
115 src->viewport.viewports,
116 src->viewport.count);
117 dest_mask |= RADV_DYNAMIC_VIEWPORT;
118 }
119 }
120
121 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
122 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
123 src->scissor.count * sizeof(VkRect2D))) {
124 typed_memcpy(dest->scissor.scissors,
125 src->scissor.scissors, src->scissor.count);
126 dest_mask |= RADV_DYNAMIC_SCISSOR;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
131 if (dest->line_width != src->line_width) {
132 dest->line_width = src->line_width;
133 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
134 }
135 }
136
137 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
138 if (memcmp(&dest->depth_bias, &src->depth_bias,
139 sizeof(src->depth_bias))) {
140 dest->depth_bias = src->depth_bias;
141 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
142 }
143 }
144
145 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
146 if (memcmp(&dest->blend_constants, &src->blend_constants,
147 sizeof(src->blend_constants))) {
148 typed_memcpy(dest->blend_constants,
149 src->blend_constants, 4);
150 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
151 }
152 }
153
154 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
155 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
156 sizeof(src->depth_bounds))) {
157 dest->depth_bounds = src->depth_bounds;
158 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
159 }
160 }
161
162 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
163 if (memcmp(&dest->stencil_compare_mask,
164 &src->stencil_compare_mask,
165 sizeof(src->stencil_compare_mask))) {
166 dest->stencil_compare_mask = src->stencil_compare_mask;
167 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
168 }
169 }
170
171 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
172 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
173 sizeof(src->stencil_write_mask))) {
174 dest->stencil_write_mask = src->stencil_write_mask;
175 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
176 }
177 }
178
179 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
180 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
181 sizeof(src->stencil_reference))) {
182 dest->stencil_reference = src->stencil_reference;
183 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
184 }
185 }
186
187 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
188 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
189 src->discard_rectangle.count * sizeof(VkRect2D))) {
190 typed_memcpy(dest->discard_rectangle.rectangles,
191 src->discard_rectangle.rectangles,
192 src->discard_rectangle.count);
193 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
194 }
195 }
196
197 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
198 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
199 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
200 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
201 memcmp(&dest->sample_location.locations,
202 &src->sample_location.locations,
203 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
204 dest->sample_location.per_pixel = src->sample_location.per_pixel;
205 dest->sample_location.grid_size = src->sample_location.grid_size;
206 typed_memcpy(dest->sample_location.locations,
207 src->sample_location.locations,
208 src->sample_location.count);
209 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
210 }
211 }
212
213 cmd_buffer->state.dirty |= dest_mask;
214 }
215
216 static void
217 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
218 struct radv_pipeline *pipeline)
219 {
220 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
221 struct radv_shader_info *info;
222
223 if (!pipeline->streamout_shader)
224 return;
225
226 info = &pipeline->streamout_shader->info.info;
227 for (int i = 0; i < MAX_SO_BUFFERS; i++)
228 so->stride_in_dw[i] = info->so.strides[i];
229
230 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
231 }
232
233 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
234 {
235 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
236 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
237 }
238
239 enum ring_type radv_queue_family_to_ring(int f) {
240 switch (f) {
241 case RADV_QUEUE_GENERAL:
242 return RING_GFX;
243 case RADV_QUEUE_COMPUTE:
244 return RING_COMPUTE;
245 case RADV_QUEUE_TRANSFER:
246 return RING_DMA;
247 default:
248 unreachable("Unknown queue family");
249 }
250 }
251
252 static VkResult radv_create_cmd_buffer(
253 struct radv_device * device,
254 struct radv_cmd_pool * pool,
255 VkCommandBufferLevel level,
256 VkCommandBuffer* pCommandBuffer)
257 {
258 struct radv_cmd_buffer *cmd_buffer;
259 unsigned ring;
260 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
262 if (cmd_buffer == NULL)
263 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
264
265 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 cmd_buffer->device = device;
267 cmd_buffer->pool = pool;
268 cmd_buffer->level = level;
269
270 if (pool) {
271 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
272 cmd_buffer->queue_family_index = pool->queue_family_index;
273
274 } else {
275 /* Init the pool_link so we can safely call list_del when we destroy
276 * the command buffer
277 */
278 list_inithead(&cmd_buffer->pool_link);
279 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
280 }
281
282 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
283
284 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
285 if (!cmd_buffer->cs) {
286 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
287 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
288 }
289
290 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
291
292 list_inithead(&cmd_buffer->upload.list);
293
294 return VK_SUCCESS;
295 }
296
297 static void
298 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
299 {
300 list_del(&cmd_buffer->pool_link);
301
302 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
303 &cmd_buffer->upload.list, list) {
304 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
305 list_del(&up->list);
306 free(up);
307 }
308
309 if (cmd_buffer->upload.upload_bo)
310 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
311 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
312
313 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
314 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
315
316 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
317 }
318
319 static VkResult
320 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
321 {
322 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
323
324 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
325 &cmd_buffer->upload.list, list) {
326 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
327 list_del(&up->list);
328 free(up);
329 }
330
331 cmd_buffer->push_constant_stages = 0;
332 cmd_buffer->scratch_size_needed = 0;
333 cmd_buffer->compute_scratch_size_needed = 0;
334 cmd_buffer->esgs_ring_size_needed = 0;
335 cmd_buffer->gsvs_ring_size_needed = 0;
336 cmd_buffer->tess_rings_needed = false;
337 cmd_buffer->sample_positions_needed = false;
338
339 if (cmd_buffer->upload.upload_bo)
340 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
341 cmd_buffer->upload.upload_bo);
342 cmd_buffer->upload.offset = 0;
343
344 cmd_buffer->record_result = VK_SUCCESS;
345
346 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
347
348 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
349 cmd_buffer->descriptors[i].dirty = 0;
350 cmd_buffer->descriptors[i].valid = 0;
351 cmd_buffer->descriptors[i].push_dirty = false;
352 }
353
354 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
355 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
356 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
357 unsigned fence_offset, eop_bug_offset;
358 void *fence_ptr;
359
360 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
361 &fence_ptr);
362
363 cmd_buffer->gfx9_fence_va =
364 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
365 cmd_buffer->gfx9_fence_va += fence_offset;
366
367 /* Allocate a buffer for the EOP bug on GFX9. */
368 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
369 &eop_bug_offset, &fence_ptr);
370 cmd_buffer->gfx9_eop_bug_va =
371 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
372 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
373 }
374
375 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
376
377 return cmd_buffer->record_result;
378 }
379
380 static bool
381 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
382 uint64_t min_needed)
383 {
384 uint64_t new_size;
385 struct radeon_winsys_bo *bo;
386 struct radv_cmd_buffer_upload *upload;
387 struct radv_device *device = cmd_buffer->device;
388
389 new_size = MAX2(min_needed, 16 * 1024);
390 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
391
392 bo = device->ws->buffer_create(device->ws,
393 new_size, 4096,
394 RADEON_DOMAIN_GTT,
395 RADEON_FLAG_CPU_ACCESS|
396 RADEON_FLAG_NO_INTERPROCESS_SHARING |
397 RADEON_FLAG_32BIT,
398 RADV_BO_PRIORITY_UPLOAD_BUFFER);
399
400 if (!bo) {
401 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
402 return false;
403 }
404
405 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
406 if (cmd_buffer->upload.upload_bo) {
407 upload = malloc(sizeof(*upload));
408
409 if (!upload) {
410 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
411 device->ws->buffer_destroy(bo);
412 return false;
413 }
414
415 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
416 list_add(&upload->list, &cmd_buffer->upload.list);
417 }
418
419 cmd_buffer->upload.upload_bo = bo;
420 cmd_buffer->upload.size = new_size;
421 cmd_buffer->upload.offset = 0;
422 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
423
424 if (!cmd_buffer->upload.map) {
425 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
426 return false;
427 }
428
429 return true;
430 }
431
432 bool
433 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
434 unsigned size,
435 unsigned alignment,
436 unsigned *out_offset,
437 void **ptr)
438 {
439 assert(util_is_power_of_two_nonzero(alignment));
440
441 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
442 if (offset + size > cmd_buffer->upload.size) {
443 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
444 return false;
445 offset = 0;
446 }
447
448 *out_offset = offset;
449 *ptr = cmd_buffer->upload.map + offset;
450
451 cmd_buffer->upload.offset = offset + size;
452 return true;
453 }
454
455 bool
456 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
457 unsigned size, unsigned alignment,
458 const void *data, unsigned *out_offset)
459 {
460 uint8_t *ptr;
461
462 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
463 out_offset, (void **)&ptr))
464 return false;
465
466 if (ptr)
467 memcpy(ptr, data, size);
468
469 return true;
470 }
471
472 static void
473 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
474 unsigned count, const uint32_t *data)
475 {
476 struct radeon_cmdbuf *cs = cmd_buffer->cs;
477
478 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
479
480 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
481 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
482 S_370_WR_CONFIRM(1) |
483 S_370_ENGINE_SEL(V_370_ME));
484 radeon_emit(cs, va);
485 radeon_emit(cs, va >> 32);
486 radeon_emit_array(cs, data, count);
487 }
488
489 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
490 {
491 struct radv_device *device = cmd_buffer->device;
492 struct radeon_cmdbuf *cs = cmd_buffer->cs;
493 uint64_t va;
494
495 va = radv_buffer_get_va(device->trace_bo);
496 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
497 va += 4;
498
499 ++cmd_buffer->state.trace_id;
500 radv_emit_write_data_packet(cmd_buffer, va, 1,
501 &cmd_buffer->state.trace_id);
502
503 radeon_check_space(cmd_buffer->device->ws, cs, 2);
504
505 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
506 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
507 }
508
509 static void
510 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
511 enum radv_cmd_flush_bits flags)
512 {
513 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
514 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
515 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
516
517 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
518
519 /* Force wait for graphics or compute engines to be idle. */
520 si_cs_emit_cache_flush(cmd_buffer->cs,
521 cmd_buffer->device->physical_device->rad_info.chip_class,
522 &cmd_buffer->gfx9_fence_idx,
523 cmd_buffer->gfx9_fence_va,
524 radv_cmd_buffer_uses_mec(cmd_buffer),
525 flags, cmd_buffer->gfx9_eop_bug_va);
526 }
527
528 if (unlikely(cmd_buffer->device->trace_bo))
529 radv_cmd_buffer_trace_emit(cmd_buffer);
530 }
531
532 static void
533 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
534 struct radv_pipeline *pipeline, enum ring_type ring)
535 {
536 struct radv_device *device = cmd_buffer->device;
537 uint32_t data[2];
538 uint64_t va;
539
540 va = radv_buffer_get_va(device->trace_bo);
541
542 switch (ring) {
543 case RING_GFX:
544 va += 8;
545 break;
546 case RING_COMPUTE:
547 va += 16;
548 break;
549 default:
550 assert(!"invalid ring type");
551 }
552
553 data[0] = (uintptr_t)pipeline;
554 data[1] = (uintptr_t)pipeline >> 32;
555
556 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
557 }
558
559 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
560 VkPipelineBindPoint bind_point,
561 struct radv_descriptor_set *set,
562 unsigned idx)
563 {
564 struct radv_descriptor_state *descriptors_state =
565 radv_get_descriptors_state(cmd_buffer, bind_point);
566
567 descriptors_state->sets[idx] = set;
568
569 descriptors_state->valid |= (1u << idx); /* active descriptors */
570 descriptors_state->dirty |= (1u << idx);
571 }
572
573 static void
574 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
575 VkPipelineBindPoint bind_point)
576 {
577 struct radv_descriptor_state *descriptors_state =
578 radv_get_descriptors_state(cmd_buffer, bind_point);
579 struct radv_device *device = cmd_buffer->device;
580 uint32_t data[MAX_SETS * 2] = {};
581 uint64_t va;
582 unsigned i;
583 va = radv_buffer_get_va(device->trace_bo) + 24;
584
585 for_each_bit(i, descriptors_state->valid) {
586 struct radv_descriptor_set *set = descriptors_state->sets[i];
587 data[i * 2] = (uint64_t)(uintptr_t)set;
588 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
589 }
590
591 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
592 }
593
594 struct radv_userdata_info *
595 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
596 gl_shader_stage stage,
597 int idx)
598 {
599 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
600 return &shader->info.user_sgprs_locs.shader_data[idx];
601 }
602
603 static void
604 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
605 struct radv_pipeline *pipeline,
606 gl_shader_stage stage,
607 int idx, uint64_t va)
608 {
609 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
610 uint32_t base_reg = pipeline->user_data_0[stage];
611 if (loc->sgpr_idx == -1)
612 return;
613
614 assert(loc->num_sgprs == 1);
615
616 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
617 base_reg + loc->sgpr_idx * 4, va, false);
618 }
619
620 static void
621 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
622 struct radv_pipeline *pipeline,
623 struct radv_descriptor_state *descriptors_state,
624 gl_shader_stage stage)
625 {
626 struct radv_device *device = cmd_buffer->device;
627 struct radeon_cmdbuf *cs = cmd_buffer->cs;
628 uint32_t sh_base = pipeline->user_data_0[stage];
629 struct radv_userdata_locations *locs =
630 &pipeline->shaders[stage]->info.user_sgprs_locs;
631 unsigned mask = locs->descriptor_sets_enabled;
632
633 mask &= descriptors_state->dirty & descriptors_state->valid;
634
635 while (mask) {
636 int start, count;
637
638 u_bit_scan_consecutive_range(&mask, &start, &count);
639
640 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
641 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
642
643 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
644 for (int i = 0; i < count; i++) {
645 struct radv_descriptor_set *set =
646 descriptors_state->sets[start + i];
647
648 radv_emit_shader_pointer_body(device, cs, set->va, true);
649 }
650 }
651 }
652
653 /**
654 * Convert the user sample locations to hardware sample locations (the values
655 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
656 */
657 static void
658 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
659 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
660 {
661 uint32_t x_offset = x % state->grid_size.width;
662 uint32_t y_offset = y % state->grid_size.height;
663 uint32_t num_samples = (uint32_t)state->per_pixel;
664 VkSampleLocationEXT *user_locs;
665 uint32_t pixel_offset;
666
667 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
668
669 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
670 user_locs = &state->locations[pixel_offset];
671
672 for (uint32_t i = 0; i < num_samples; i++) {
673 float shifted_pos_x = user_locs[i].x - 0.5;
674 float shifted_pos_y = user_locs[i].y - 0.5;
675
676 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
677 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
678
679 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
680 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
681 }
682 }
683
684 /**
685 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
686 * locations.
687 */
688 static void
689 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
690 uint32_t *sample_locs_pixel)
691 {
692 for (uint32_t i = 0; i < num_samples; i++) {
693 uint32_t sample_reg_idx = i / 4;
694 uint32_t sample_loc_idx = i % 4;
695 int32_t pos_x = sample_locs[i].x;
696 int32_t pos_y = sample_locs[i].y;
697
698 uint32_t shift_x = 8 * sample_loc_idx;
699 uint32_t shift_y = shift_x + 4;
700
701 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
702 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
703 }
704 }
705
706 /**
707 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
708 * sample locations.
709 */
710 static uint64_t
711 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
712 VkOffset2D *sample_locs,
713 uint32_t num_samples)
714 {
715 uint32_t centroid_priorities[num_samples];
716 uint32_t sample_mask = num_samples - 1;
717 uint32_t distances[num_samples];
718 uint64_t centroid_priority = 0;
719
720 /* Compute the distances from center for each sample. */
721 for (int i = 0; i < num_samples; i++) {
722 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
723 (sample_locs[i].y * sample_locs[i].y);
724 }
725
726 /* Compute the centroid priorities by looking at the distances array. */
727 for (int i = 0; i < num_samples; i++) {
728 uint32_t min_idx = 0;
729
730 for (int j = 1; j < num_samples; j++) {
731 if (distances[j] < distances[min_idx])
732 min_idx = j;
733 }
734
735 centroid_priorities[i] = min_idx;
736 distances[min_idx] = 0xffffffff;
737 }
738
739 /* Compute the final centroid priority. */
740 for (int i = 0; i < 8; i++) {
741 centroid_priority |=
742 centroid_priorities[i & sample_mask] << (i * 4);
743 }
744
745 return centroid_priority << 32 | centroid_priority;
746 }
747
748 /**
749 * Emit the sample locations that are specified with VK_EXT_sample_locations.
750 */
751 static void
752 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
753 {
754 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
755 struct radv_multisample_state *ms = &pipeline->graphics.ms;
756 struct radv_sample_locations_state *sample_location =
757 &cmd_buffer->state.dynamic.sample_location;
758 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
759 struct radeon_cmdbuf *cs = cmd_buffer->cs;
760 uint32_t sample_locs_pixel[4][2] = {};
761 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
762 uint32_t max_sample_dist = 0;
763 uint64_t centroid_priority;
764
765 if (!cmd_buffer->state.dynamic.sample_location.count)
766 return;
767
768 /* Convert the user sample locations to hardware sample locations. */
769 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
770 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
771 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
772 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
773
774 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
775 for (uint32_t i = 0; i < 4; i++) {
776 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
777 sample_locs_pixel[i]);
778 }
779
780 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
781 centroid_priority =
782 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
783 num_samples);
784
785 /* Compute the maximum sample distance from the specified locations. */
786 for (uint32_t i = 0; i < num_samples; i++) {
787 VkOffset2D offset = sample_locs[0][i];
788 max_sample_dist = MAX2(max_sample_dist,
789 MAX2(abs(offset.x), abs(offset.y)));
790 }
791
792 /* Emit the specified user sample locations. */
793 switch (num_samples) {
794 case 2:
795 case 4:
796 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
797 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
798 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
799 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
800 break;
801 case 8:
802 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
803 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
804 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
805 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
806 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
807 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
808 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
809 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
810 break;
811 default:
812 unreachable("invalid number of samples");
813 }
814
815 /* Emit the maximum sample distance and the centroid priority. */
816 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
817
818 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
819 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
820
821 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
822 radeon_emit(cs, pa_sc_aa_config);
823
824 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
825 radeon_emit(cs, centroid_priority);
826 radeon_emit(cs, centroid_priority >> 32);
827
828 /* GFX9: Flush DFSM when the AA mode changes. */
829 if (cmd_buffer->device->dfsm_allowed) {
830 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
831 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
832 }
833
834 cmd_buffer->state.context_roll_without_scissor_emitted = true;
835 }
836
837 static void
838 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
839 struct radv_pipeline *pipeline,
840 gl_shader_stage stage,
841 int idx, int count, uint32_t *values)
842 {
843 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
844 uint32_t base_reg = pipeline->user_data_0[stage];
845 if (loc->sgpr_idx == -1)
846 return;
847
848 assert(loc->num_sgprs == count);
849
850 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
851 radeon_emit_array(cmd_buffer->cs, values, count);
852 }
853
854 static void
855 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
856 struct radv_pipeline *pipeline)
857 {
858 int num_samples = pipeline->graphics.ms.num_samples;
859 struct radv_multisample_state *ms = &pipeline->graphics.ms;
860 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
861
862 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
863 cmd_buffer->sample_positions_needed = true;
864
865 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
866 return;
867
868 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
869 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
870 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
871
872 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
873
874 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
875
876 /* GFX9: Flush DFSM when the AA mode changes. */
877 if (cmd_buffer->device->dfsm_allowed) {
878 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
879 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
880 }
881
882 cmd_buffer->state.context_roll_without_scissor_emitted = true;
883 }
884
885 static void
886 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
887 struct radv_shader_variant *shader)
888 {
889 uint64_t va;
890
891 if (!shader)
892 return;
893
894 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
895
896 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
897 }
898
899 static void
900 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
901 struct radv_pipeline *pipeline,
902 bool vertex_stage_only)
903 {
904 struct radv_cmd_state *state = &cmd_buffer->state;
905 uint32_t mask = state->prefetch_L2_mask;
906
907 if (vertex_stage_only) {
908 /* Fast prefetch path for starting draws as soon as possible.
909 */
910 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
911 RADV_PREFETCH_VBO_DESCRIPTORS);
912 }
913
914 if (mask & RADV_PREFETCH_VS)
915 radv_emit_shader_prefetch(cmd_buffer,
916 pipeline->shaders[MESA_SHADER_VERTEX]);
917
918 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
919 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
920
921 if (mask & RADV_PREFETCH_TCS)
922 radv_emit_shader_prefetch(cmd_buffer,
923 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
924
925 if (mask & RADV_PREFETCH_TES)
926 radv_emit_shader_prefetch(cmd_buffer,
927 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
928
929 if (mask & RADV_PREFETCH_GS) {
930 radv_emit_shader_prefetch(cmd_buffer,
931 pipeline->shaders[MESA_SHADER_GEOMETRY]);
932 if (radv_pipeline_has_gs_copy_shader(pipeline))
933 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
934 }
935
936 if (mask & RADV_PREFETCH_PS)
937 radv_emit_shader_prefetch(cmd_buffer,
938 pipeline->shaders[MESA_SHADER_FRAGMENT]);
939
940 state->prefetch_L2_mask &= ~mask;
941 }
942
943 static void
944 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
945 {
946 if (!cmd_buffer->device->physical_device->rbplus_allowed)
947 return;
948
949 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
950 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
951 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
952
953 unsigned sx_ps_downconvert = 0;
954 unsigned sx_blend_opt_epsilon = 0;
955 unsigned sx_blend_opt_control = 0;
956
957 for (unsigned i = 0; i < subpass->color_count; ++i) {
958 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
959 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
960 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
961 continue;
962 }
963
964 int idx = subpass->color_attachments[i].attachment;
965 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
966
967 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
968 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
969 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
970 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
971
972 bool has_alpha, has_rgb;
973
974 /* Set if RGB and A are present. */
975 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
976
977 if (format == V_028C70_COLOR_8 ||
978 format == V_028C70_COLOR_16 ||
979 format == V_028C70_COLOR_32)
980 has_rgb = !has_alpha;
981 else
982 has_rgb = true;
983
984 /* Check the colormask and export format. */
985 if (!(colormask & 0x7))
986 has_rgb = false;
987 if (!(colormask & 0x8))
988 has_alpha = false;
989
990 if (spi_format == V_028714_SPI_SHADER_ZERO) {
991 has_rgb = false;
992 has_alpha = false;
993 }
994
995 /* Disable value checking for disabled channels. */
996 if (!has_rgb)
997 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
998 if (!has_alpha)
999 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1000
1001 /* Enable down-conversion for 32bpp and smaller formats. */
1002 switch (format) {
1003 case V_028C70_COLOR_8:
1004 case V_028C70_COLOR_8_8:
1005 case V_028C70_COLOR_8_8_8_8:
1006 /* For 1 and 2-channel formats, use the superset thereof. */
1007 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1008 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1009 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1010 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1011 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1012 }
1013 break;
1014
1015 case V_028C70_COLOR_5_6_5:
1016 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1017 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1018 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1019 }
1020 break;
1021
1022 case V_028C70_COLOR_1_5_5_5:
1023 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1024 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1025 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1026 }
1027 break;
1028
1029 case V_028C70_COLOR_4_4_4_4:
1030 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1031 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1032 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1033 }
1034 break;
1035
1036 case V_028C70_COLOR_32:
1037 if (swap == V_028C70_SWAP_STD &&
1038 spi_format == V_028714_SPI_SHADER_32_R)
1039 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1040 else if (swap == V_028C70_SWAP_ALT_REV &&
1041 spi_format == V_028714_SPI_SHADER_32_AR)
1042 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1043 break;
1044
1045 case V_028C70_COLOR_16:
1046 case V_028C70_COLOR_16_16:
1047 /* For 1-channel formats, use the superset thereof. */
1048 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1049 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1050 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1051 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1052 if (swap == V_028C70_SWAP_STD ||
1053 swap == V_028C70_SWAP_STD_REV)
1054 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1055 else
1056 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1057 }
1058 break;
1059
1060 case V_028C70_COLOR_10_11_11:
1061 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1062 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1063 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1064 }
1065 break;
1066
1067 case V_028C70_COLOR_2_10_10_10:
1068 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1069 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1070 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1071 }
1072 break;
1073 }
1074 }
1075
1076 for (unsigned i = subpass->color_count; i < 8; ++i) {
1077 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1078 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1079 }
1080 /* TODO: avoid redundantly setting context registers */
1081 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1082 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1083 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1084 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1085
1086 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1087 }
1088
1089 static void
1090 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1091 {
1092 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1093
1094 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1095 return;
1096
1097 radv_update_multisample_state(cmd_buffer, pipeline);
1098
1099 cmd_buffer->scratch_size_needed =
1100 MAX2(cmd_buffer->scratch_size_needed,
1101 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1102
1103 if (!cmd_buffer->state.emitted_pipeline ||
1104 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1105 pipeline->graphics.can_use_guardband)
1106 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1107
1108 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1109
1110 if (!cmd_buffer->state.emitted_pipeline ||
1111 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1112 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1113 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1114 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1115 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1116 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1117 }
1118
1119 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1120 if (!pipeline->shaders[i])
1121 continue;
1122
1123 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1124 pipeline->shaders[i]->bo);
1125 }
1126
1127 if (radv_pipeline_has_gs_copy_shader(pipeline))
1128 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1129 pipeline->gs_copy_shader->bo);
1130
1131 if (unlikely(cmd_buffer->device->trace_bo))
1132 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1133
1134 cmd_buffer->state.emitted_pipeline = pipeline;
1135
1136 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1137 }
1138
1139 static void
1140 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1141 {
1142 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1143 cmd_buffer->state.dynamic.viewport.viewports);
1144 }
1145
1146 static void
1147 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1148 {
1149 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1150
1151 si_write_scissors(cmd_buffer->cs, 0, count,
1152 cmd_buffer->state.dynamic.scissor.scissors,
1153 cmd_buffer->state.dynamic.viewport.viewports,
1154 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1155
1156 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1157 }
1158
1159 static void
1160 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1161 {
1162 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1163 return;
1164
1165 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1166 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1167 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1168 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1169 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1170 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1171 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1172 }
1173 }
1174
1175 static void
1176 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1177 {
1178 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1179
1180 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1181 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1182 }
1183
1184 static void
1185 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1186 {
1187 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1188
1189 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1190 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1191 }
1192
1193 static void
1194 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1195 {
1196 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1197
1198 radeon_set_context_reg_seq(cmd_buffer->cs,
1199 R_028430_DB_STENCILREFMASK, 2);
1200 radeon_emit(cmd_buffer->cs,
1201 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1202 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1203 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1204 S_028430_STENCILOPVAL(1));
1205 radeon_emit(cmd_buffer->cs,
1206 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1207 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1208 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1209 S_028434_STENCILOPVAL_BF(1));
1210 }
1211
1212 static void
1213 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1214 {
1215 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1216
1217 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1218 fui(d->depth_bounds.min));
1219 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1220 fui(d->depth_bounds.max));
1221 }
1222
1223 static void
1224 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1225 {
1226 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1227 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1228 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1229
1230
1231 radeon_set_context_reg_seq(cmd_buffer->cs,
1232 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1233 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1234 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1235 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1236 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1237 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1238 }
1239
1240 static void
1241 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1242 int index,
1243 struct radv_attachment_info *att,
1244 struct radv_image_view *iview,
1245 VkImageLayout layout)
1246 {
1247 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1248 struct radv_color_buffer_info *cb = &att->cb;
1249 uint32_t cb_color_info = cb->cb_color_info;
1250 struct radv_image *image = iview->image;
1251
1252 if (!radv_layout_dcc_compressed(image, layout,
1253 radv_image_queue_family_mask(image,
1254 cmd_buffer->queue_family_index,
1255 cmd_buffer->queue_family_index))) {
1256 cb_color_info &= C_028C70_DCC_ENABLE;
1257 }
1258
1259 if (radv_image_is_tc_compat_cmask(image) &&
1260 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1261 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1262 /* If this bit is set, the FMASK decompression operation
1263 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1264 */
1265 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1266 }
1267
1268 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1269 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1270 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1271 radeon_emit(cmd_buffer->cs, 0);
1272 radeon_emit(cmd_buffer->cs, 0);
1273 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1274 radeon_emit(cmd_buffer->cs, cb_color_info);
1275 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1276 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1277 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1278 radeon_emit(cmd_buffer->cs, 0);
1279 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1280 radeon_emit(cmd_buffer->cs, 0);
1281
1282 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1283 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1284
1285 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1286 cb->cb_color_base >> 32);
1287 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1288 cb->cb_color_cmask >> 32);
1289 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1290 cb->cb_color_fmask >> 32);
1291 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1292 cb->cb_dcc_base >> 32);
1293 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1294 cb->cb_color_attrib2);
1295 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1296 cb->cb_color_attrib3);
1297 } else if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1298 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1299 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1300 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1301 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1302 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1303 radeon_emit(cmd_buffer->cs, cb_color_info);
1304 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1305 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1306 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1307 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1308 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1309 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1310
1311 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1312 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1313 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1314
1315 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1316 cb->cb_mrt_epitch);
1317 } else {
1318 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1319 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1320 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1321 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1322 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1323 radeon_emit(cmd_buffer->cs, cb_color_info);
1324 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1325 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1326 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1327 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1328 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1329 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1330
1331 if (is_vi) { /* DCC BASE */
1332 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1333 }
1334 }
1335
1336 if (radv_dcc_enabled(image, iview->base_mip)) {
1337 /* Drawing with DCC enabled also compresses colorbuffers. */
1338 VkImageSubresourceRange range = {
1339 .aspectMask = iview->aspect_mask,
1340 .baseMipLevel = iview->base_mip,
1341 .levelCount = iview->level_count,
1342 .baseArrayLayer = iview->base_layer,
1343 .layerCount = iview->layer_count,
1344 };
1345
1346 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1347 }
1348 }
1349
1350 static void
1351 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1352 struct radv_ds_buffer_info *ds,
1353 struct radv_image *image, VkImageLayout layout,
1354 bool requires_cond_exec)
1355 {
1356 uint32_t db_z_info = ds->db_z_info;
1357 uint32_t db_z_info_reg;
1358
1359 if (!radv_image_is_tc_compat_htile(image))
1360 return;
1361
1362 if (!radv_layout_has_htile(image, layout,
1363 radv_image_queue_family_mask(image,
1364 cmd_buffer->queue_family_index,
1365 cmd_buffer->queue_family_index))) {
1366 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1367 }
1368
1369 db_z_info &= C_028040_ZRANGE_PRECISION;
1370
1371 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1372 db_z_info_reg = R_028038_DB_Z_INFO;
1373 } else {
1374 db_z_info_reg = R_028040_DB_Z_INFO;
1375 }
1376
1377 /* When we don't know the last fast clear value we need to emit a
1378 * conditional packet that will eventually skip the following
1379 * SET_CONTEXT_REG packet.
1380 */
1381 if (requires_cond_exec) {
1382 uint64_t va = radv_buffer_get_va(image->bo);
1383 va += image->offset + image->tc_compat_zrange_offset;
1384
1385 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1386 radeon_emit(cmd_buffer->cs, va);
1387 radeon_emit(cmd_buffer->cs, va >> 32);
1388 radeon_emit(cmd_buffer->cs, 0);
1389 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1390 }
1391
1392 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1393 }
1394
1395 static void
1396 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1397 struct radv_ds_buffer_info *ds,
1398 struct radv_image *image,
1399 VkImageLayout layout)
1400 {
1401 uint32_t db_z_info = ds->db_z_info;
1402 uint32_t db_stencil_info = ds->db_stencil_info;
1403
1404 if (!radv_layout_has_htile(image, layout,
1405 radv_image_queue_family_mask(image,
1406 cmd_buffer->queue_family_index,
1407 cmd_buffer->queue_family_index))) {
1408 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1409 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1410 }
1411
1412 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1413 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1414
1415 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1416 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1417 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1418
1419 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1420 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1421 radeon_emit(cmd_buffer->cs, db_z_info);
1422 radeon_emit(cmd_buffer->cs, db_stencil_info);
1423 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1424 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1425 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1426 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1427
1428 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1429 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1430 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1431 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1432 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1433 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1434 } else if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1435 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1436 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1437 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1438 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1439
1440 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1441 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1442 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1443 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1444 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1445 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1446 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1447 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1448 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1449 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1450 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1451
1452 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1453 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1454 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1455 } else {
1456 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1457
1458 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1459 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1460 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1461 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1462 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1463 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1464 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1465 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1466 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1467 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1468
1469 }
1470
1471 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1472 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1473
1474 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1475 ds->pa_su_poly_offset_db_fmt_cntl);
1476 }
1477
1478 /**
1479 * Update the fast clear depth/stencil values if the image is bound as a
1480 * depth/stencil buffer.
1481 */
1482 static void
1483 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1484 struct radv_image *image,
1485 VkClearDepthStencilValue ds_clear_value,
1486 VkImageAspectFlags aspects)
1487 {
1488 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1489 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1490 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1491 struct radv_attachment_info *att;
1492 uint32_t att_idx;
1493
1494 if (!framebuffer || !subpass)
1495 return;
1496
1497 if (!subpass->depth_stencil_attachment)
1498 return;
1499
1500 att_idx = subpass->depth_stencil_attachment->attachment;
1501 att = &framebuffer->attachments[att_idx];
1502 if (att->attachment->image != image)
1503 return;
1504
1505 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1506 radeon_emit(cs, ds_clear_value.stencil);
1507 radeon_emit(cs, fui(ds_clear_value.depth));
1508
1509 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1510 * only needed when clearing Z to 0.0.
1511 */
1512 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1513 ds_clear_value.depth == 0.0) {
1514 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1515
1516 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1517 layout, false);
1518 }
1519
1520 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1521 }
1522
1523 /**
1524 * Set the clear depth/stencil values to the image's metadata.
1525 */
1526 static void
1527 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1528 struct radv_image *image,
1529 VkClearDepthStencilValue ds_clear_value,
1530 VkImageAspectFlags aspects)
1531 {
1532 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1533 uint64_t va = radv_buffer_get_va(image->bo);
1534 unsigned reg_offset = 0, reg_count = 0;
1535
1536 va += image->offset + image->clear_value_offset;
1537
1538 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1539 ++reg_count;
1540 } else {
1541 ++reg_offset;
1542 va += 4;
1543 }
1544 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1545 ++reg_count;
1546
1547 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
1548 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1549 S_370_WR_CONFIRM(1) |
1550 S_370_ENGINE_SEL(V_370_PFP));
1551 radeon_emit(cs, va);
1552 radeon_emit(cs, va >> 32);
1553 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1554 radeon_emit(cs, ds_clear_value.stencil);
1555 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1556 radeon_emit(cs, fui(ds_clear_value.depth));
1557 }
1558
1559 /**
1560 * Update the TC-compat metadata value for this image.
1561 */
1562 static void
1563 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1564 struct radv_image *image,
1565 uint32_t value)
1566 {
1567 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1568 uint64_t va = radv_buffer_get_va(image->bo);
1569 va += image->offset + image->tc_compat_zrange_offset;
1570
1571 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1572 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1573 S_370_WR_CONFIRM(1) |
1574 S_370_ENGINE_SEL(V_370_PFP));
1575 radeon_emit(cs, va);
1576 radeon_emit(cs, va >> 32);
1577 radeon_emit(cs, value);
1578 }
1579
1580 static void
1581 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1582 struct radv_image *image,
1583 VkClearDepthStencilValue ds_clear_value)
1584 {
1585 uint32_t cond_val;
1586
1587 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1588 * depth clear value is 0.0f.
1589 */
1590 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1591
1592 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1593 }
1594
1595 /**
1596 * Update the clear depth/stencil values for this image.
1597 */
1598 void
1599 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1600 struct radv_image *image,
1601 VkClearDepthStencilValue ds_clear_value,
1602 VkImageAspectFlags aspects)
1603 {
1604 assert(radv_image_has_htile(image));
1605
1606 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1607
1608 if (radv_image_is_tc_compat_htile(image) &&
1609 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1610 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1611 ds_clear_value);
1612 }
1613
1614 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1615 aspects);
1616 }
1617
1618 /**
1619 * Load the clear depth/stencil values from the image's metadata.
1620 */
1621 static void
1622 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1623 struct radv_image *image)
1624 {
1625 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1626 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1627 uint64_t va = radv_buffer_get_va(image->bo);
1628 unsigned reg_offset = 0, reg_count = 0;
1629
1630 va += image->offset + image->clear_value_offset;
1631
1632 if (!radv_image_has_htile(image))
1633 return;
1634
1635 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1636 ++reg_count;
1637 } else {
1638 ++reg_offset;
1639 va += 4;
1640 }
1641 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1642 ++reg_count;
1643
1644 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1645
1646 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1647 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1648 radeon_emit(cs, va);
1649 radeon_emit(cs, va >> 32);
1650 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1651 radeon_emit(cs, reg_count);
1652 } else {
1653 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1654 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1655 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1656 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1657 radeon_emit(cs, va);
1658 radeon_emit(cs, va >> 32);
1659 radeon_emit(cs, reg >> 2);
1660 radeon_emit(cs, 0);
1661
1662 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1663 radeon_emit(cs, 0);
1664 }
1665 }
1666
1667 /*
1668 * With DCC some colors don't require CMASK elimination before being
1669 * used as a texture. This sets a predicate value to determine if the
1670 * cmask eliminate is required.
1671 */
1672 void
1673 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1674 struct radv_image *image,
1675 const VkImageSubresourceRange *range, bool value)
1676 {
1677 uint64_t pred_val = value;
1678 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1679 uint32_t level_count = radv_get_levelCount(image, range);
1680 uint32_t count = 2 * level_count;
1681
1682 assert(radv_dcc_enabled(image, range->baseMipLevel));
1683
1684 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1685 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1686 S_370_WR_CONFIRM(1) |
1687 S_370_ENGINE_SEL(V_370_PFP));
1688 radeon_emit(cmd_buffer->cs, va);
1689 radeon_emit(cmd_buffer->cs, va >> 32);
1690
1691 for (uint32_t l = 0; l < level_count; l++) {
1692 radeon_emit(cmd_buffer->cs, pred_val);
1693 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1694 }
1695 }
1696
1697 /**
1698 * Update the DCC predicate to reflect the compression state.
1699 */
1700 void
1701 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1702 struct radv_image *image,
1703 const VkImageSubresourceRange *range, bool value)
1704 {
1705 uint64_t pred_val = value;
1706 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1707 uint32_t level_count = radv_get_levelCount(image, range);
1708 uint32_t count = 2 * level_count;
1709
1710 assert(radv_dcc_enabled(image, range->baseMipLevel));
1711
1712 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1713 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1714 S_370_WR_CONFIRM(1) |
1715 S_370_ENGINE_SEL(V_370_PFP));
1716 radeon_emit(cmd_buffer->cs, va);
1717 radeon_emit(cmd_buffer->cs, va >> 32);
1718
1719 for (uint32_t l = 0; l < level_count; l++) {
1720 radeon_emit(cmd_buffer->cs, pred_val);
1721 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1722 }
1723 }
1724
1725 /**
1726 * Update the fast clear color values if the image is bound as a color buffer.
1727 */
1728 static void
1729 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1730 struct radv_image *image,
1731 int cb_idx,
1732 uint32_t color_values[2])
1733 {
1734 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1735 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1736 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1737 struct radv_attachment_info *att;
1738 uint32_t att_idx;
1739
1740 if (!framebuffer || !subpass)
1741 return;
1742
1743 att_idx = subpass->color_attachments[cb_idx].attachment;
1744 if (att_idx == VK_ATTACHMENT_UNUSED)
1745 return;
1746
1747 att = &framebuffer->attachments[att_idx];
1748 if (att->attachment->image != image)
1749 return;
1750
1751 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1752 radeon_emit(cs, color_values[0]);
1753 radeon_emit(cs, color_values[1]);
1754
1755 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1756 }
1757
1758 /**
1759 * Set the clear color values to the image's metadata.
1760 */
1761 static void
1762 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1763 struct radv_image *image,
1764 const VkImageSubresourceRange *range,
1765 uint32_t color_values[2])
1766 {
1767 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1768 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1769 uint32_t level_count = radv_get_levelCount(image, range);
1770 uint32_t count = 2 * level_count;
1771
1772 assert(radv_image_has_cmask(image) ||
1773 radv_dcc_enabled(image, range->baseMipLevel));
1774
1775 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1776 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1777 S_370_WR_CONFIRM(1) |
1778 S_370_ENGINE_SEL(V_370_PFP));
1779 radeon_emit(cs, va);
1780 radeon_emit(cs, va >> 32);
1781
1782 for (uint32_t l = 0; l < level_count; l++) {
1783 radeon_emit(cs, color_values[0]);
1784 radeon_emit(cs, color_values[1]);
1785 }
1786 }
1787
1788 /**
1789 * Update the clear color values for this image.
1790 */
1791 void
1792 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1793 const struct radv_image_view *iview,
1794 int cb_idx,
1795 uint32_t color_values[2])
1796 {
1797 struct radv_image *image = iview->image;
1798 VkImageSubresourceRange range = {
1799 .aspectMask = iview->aspect_mask,
1800 .baseMipLevel = iview->base_mip,
1801 .levelCount = iview->level_count,
1802 .baseArrayLayer = iview->base_layer,
1803 .layerCount = iview->layer_count,
1804 };
1805
1806 assert(radv_image_has_cmask(image) ||
1807 radv_dcc_enabled(image, iview->base_mip));
1808
1809 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1810
1811 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1812 color_values);
1813 }
1814
1815 /**
1816 * Load the clear color values from the image's metadata.
1817 */
1818 static void
1819 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1820 struct radv_image_view *iview,
1821 int cb_idx)
1822 {
1823 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1824 struct radv_image *image = iview->image;
1825 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1826
1827 if (!radv_image_has_cmask(image) &&
1828 !radv_dcc_enabled(image, iview->base_mip))
1829 return;
1830
1831 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1832
1833 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1834 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1835 radeon_emit(cs, va);
1836 radeon_emit(cs, va >> 32);
1837 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1838 radeon_emit(cs, 2);
1839 } else {
1840 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1841 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1842 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1843 COPY_DATA_COUNT_SEL);
1844 radeon_emit(cs, va);
1845 radeon_emit(cs, va >> 32);
1846 radeon_emit(cs, reg >> 2);
1847 radeon_emit(cs, 0);
1848
1849 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1850 radeon_emit(cs, 0);
1851 }
1852 }
1853
1854 static void
1855 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1856 {
1857 int i;
1858 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1859 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1860
1861 /* this may happen for inherited secondary recording */
1862 if (!framebuffer)
1863 return;
1864
1865 for (i = 0; i < 8; ++i) {
1866 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1867 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1868 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1869 continue;
1870 }
1871
1872 int idx = subpass->color_attachments[i].attachment;
1873 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1874 struct radv_image_view *iview = att->attachment;
1875 VkImageLayout layout = subpass->color_attachments[i].layout;
1876
1877 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1878
1879 assert(att->attachment->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1880 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1881 radv_emit_fb_color_state(cmd_buffer, i, att, iview, layout);
1882
1883 radv_load_color_clear_metadata(cmd_buffer, iview, i);
1884 }
1885
1886 if (subpass->depth_stencil_attachment) {
1887 int idx = subpass->depth_stencil_attachment->attachment;
1888 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1889 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1890 struct radv_image *image = att->attachment->image;
1891 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1892 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1893 cmd_buffer->queue_family_index,
1894 cmd_buffer->queue_family_index);
1895 /* We currently don't support writing decompressed HTILE */
1896 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1897 radv_layout_is_htile_compressed(image, layout, queue_mask));
1898
1899 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1900
1901 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1902 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1903 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1904 }
1905 radv_load_ds_clear_metadata(cmd_buffer, image);
1906 } else {
1907 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
1908 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1909 else
1910 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1911
1912 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1913 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1914 }
1915 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1916 S_028208_BR_X(framebuffer->width) |
1917 S_028208_BR_Y(framebuffer->height));
1918
1919 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
1920 bool disable_constant_encode =
1921 cmd_buffer->device->physical_device->has_dcc_constant_encode;
1922 enum chip_class chip_class =
1923 cmd_buffer->device->physical_device->rad_info.chip_class;
1924 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
1925
1926 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1927 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
1928 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
1929 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
1930 }
1931
1932 if (cmd_buffer->device->dfsm_allowed) {
1933 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1934 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1935 }
1936
1937 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1938 }
1939
1940 static void
1941 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1942 {
1943 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1944 struct radv_cmd_state *state = &cmd_buffer->state;
1945
1946 if (state->index_type != state->last_index_type) {
1947 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1948 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
1949 cs, R_03090C_VGT_INDEX_TYPE,
1950 2, state->index_type);
1951 } else {
1952 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1953 radeon_emit(cs, state->index_type);
1954 }
1955
1956 state->last_index_type = state->index_type;
1957 }
1958
1959 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1960 radeon_emit(cs, state->index_va);
1961 radeon_emit(cs, state->index_va >> 32);
1962
1963 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1964 radeon_emit(cs, state->max_index_count);
1965
1966 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1967 }
1968
1969 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1970 {
1971 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1972 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1973 uint32_t pa_sc_mode_cntl_1 =
1974 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1975 uint32_t db_count_control;
1976
1977 if(!cmd_buffer->state.active_occlusion_queries) {
1978 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1979 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1980 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1981 has_perfect_queries) {
1982 /* Re-enable out-of-order rasterization if the
1983 * bound pipeline supports it and if it's has
1984 * been disabled before starting any perfect
1985 * occlusion queries.
1986 */
1987 radeon_set_context_reg(cmd_buffer->cs,
1988 R_028A4C_PA_SC_MODE_CNTL_1,
1989 pa_sc_mode_cntl_1);
1990 }
1991 }
1992 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1993 } else {
1994 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1995 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1996 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
1997
1998 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1999 db_count_control =
2000 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2001 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2002 S_028004_SAMPLE_RATE(sample_rate) |
2003 S_028004_ZPASS_ENABLE(1) |
2004 S_028004_SLICE_EVEN_ENABLE(1) |
2005 S_028004_SLICE_ODD_ENABLE(1);
2006
2007 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2008 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2009 has_perfect_queries) {
2010 /* If the bound pipeline has enabled
2011 * out-of-order rasterization, we should
2012 * disable it before starting any perfect
2013 * occlusion queries.
2014 */
2015 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2016
2017 radeon_set_context_reg(cmd_buffer->cs,
2018 R_028A4C_PA_SC_MODE_CNTL_1,
2019 pa_sc_mode_cntl_1);
2020 }
2021 } else {
2022 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2023 S_028004_SAMPLE_RATE(sample_rate);
2024 }
2025 }
2026
2027 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2028
2029 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2030 }
2031
2032 static void
2033 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2034 {
2035 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2036
2037 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2038 radv_emit_viewport(cmd_buffer);
2039
2040 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2041 !cmd_buffer->device->physical_device->has_scissor_bug)
2042 radv_emit_scissor(cmd_buffer);
2043
2044 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2045 radv_emit_line_width(cmd_buffer);
2046
2047 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2048 radv_emit_blend_constants(cmd_buffer);
2049
2050 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2051 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2052 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2053 radv_emit_stencil(cmd_buffer);
2054
2055 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2056 radv_emit_depth_bounds(cmd_buffer);
2057
2058 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2059 radv_emit_depth_bias(cmd_buffer);
2060
2061 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2062 radv_emit_discard_rectangle(cmd_buffer);
2063
2064 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2065 radv_emit_sample_locations(cmd_buffer);
2066
2067 cmd_buffer->state.dirty &= ~states;
2068 }
2069
2070 static void
2071 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2072 VkPipelineBindPoint bind_point)
2073 {
2074 struct radv_descriptor_state *descriptors_state =
2075 radv_get_descriptors_state(cmd_buffer, bind_point);
2076 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2077 unsigned bo_offset;
2078
2079 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2080 set->mapped_ptr,
2081 &bo_offset))
2082 return;
2083
2084 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2085 set->va += bo_offset;
2086 }
2087
2088 static void
2089 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2090 VkPipelineBindPoint bind_point)
2091 {
2092 struct radv_descriptor_state *descriptors_state =
2093 radv_get_descriptors_state(cmd_buffer, bind_point);
2094 uint32_t size = MAX_SETS * 4;
2095 uint32_t offset;
2096 void *ptr;
2097
2098 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2099 256, &offset, &ptr))
2100 return;
2101
2102 for (unsigned i = 0; i < MAX_SETS; i++) {
2103 uint32_t *uptr = ((uint32_t *)ptr) + i;
2104 uint64_t set_va = 0;
2105 struct radv_descriptor_set *set = descriptors_state->sets[i];
2106 if (descriptors_state->valid & (1u << i))
2107 set_va = set->va;
2108 uptr[0] = set_va & 0xffffffff;
2109 }
2110
2111 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2112 va += offset;
2113
2114 if (cmd_buffer->state.pipeline) {
2115 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2116 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2117 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2118
2119 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2120 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2121 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2122
2123 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2124 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2125 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2126
2127 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2128 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2129 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2130
2131 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2132 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2133 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2134 }
2135
2136 if (cmd_buffer->state.compute_pipeline)
2137 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2138 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2139 }
2140
2141 static void
2142 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2143 VkShaderStageFlags stages)
2144 {
2145 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2146 VK_PIPELINE_BIND_POINT_COMPUTE :
2147 VK_PIPELINE_BIND_POINT_GRAPHICS;
2148 struct radv_descriptor_state *descriptors_state =
2149 radv_get_descriptors_state(cmd_buffer, bind_point);
2150 struct radv_cmd_state *state = &cmd_buffer->state;
2151 bool flush_indirect_descriptors;
2152
2153 if (!descriptors_state->dirty)
2154 return;
2155
2156 if (descriptors_state->push_dirty)
2157 radv_flush_push_descriptors(cmd_buffer, bind_point);
2158
2159 flush_indirect_descriptors =
2160 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2161 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2162 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2163 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2164
2165 if (flush_indirect_descriptors)
2166 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2167
2168 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2169 cmd_buffer->cs,
2170 MAX_SETS * MESA_SHADER_STAGES * 4);
2171
2172 if (cmd_buffer->state.pipeline) {
2173 radv_foreach_stage(stage, stages) {
2174 if (!cmd_buffer->state.pipeline->shaders[stage])
2175 continue;
2176
2177 radv_emit_descriptor_pointers(cmd_buffer,
2178 cmd_buffer->state.pipeline,
2179 descriptors_state, stage);
2180 }
2181 }
2182
2183 if (cmd_buffer->state.compute_pipeline &&
2184 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2185 radv_emit_descriptor_pointers(cmd_buffer,
2186 cmd_buffer->state.compute_pipeline,
2187 descriptors_state,
2188 MESA_SHADER_COMPUTE);
2189 }
2190
2191 descriptors_state->dirty = 0;
2192 descriptors_state->push_dirty = false;
2193
2194 assert(cmd_buffer->cs->cdw <= cdw_max);
2195
2196 if (unlikely(cmd_buffer->device->trace_bo))
2197 radv_save_descriptors(cmd_buffer, bind_point);
2198 }
2199
2200 static void
2201 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2202 VkShaderStageFlags stages)
2203 {
2204 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2205 ? cmd_buffer->state.compute_pipeline
2206 : cmd_buffer->state.pipeline;
2207 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2208 VK_PIPELINE_BIND_POINT_COMPUTE :
2209 VK_PIPELINE_BIND_POINT_GRAPHICS;
2210 struct radv_descriptor_state *descriptors_state =
2211 radv_get_descriptors_state(cmd_buffer, bind_point);
2212 struct radv_pipeline_layout *layout = pipeline->layout;
2213 struct radv_shader_variant *shader, *prev_shader;
2214 bool need_push_constants = false;
2215 unsigned offset;
2216 void *ptr;
2217 uint64_t va;
2218
2219 stages &= cmd_buffer->push_constant_stages;
2220 if (!stages ||
2221 (!layout->push_constant_size && !layout->dynamic_offset_count))
2222 return;
2223
2224 radv_foreach_stage(stage, stages) {
2225 if (!pipeline->shaders[stage])
2226 continue;
2227
2228 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
2229 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
2230
2231 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
2232 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
2233
2234 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2235 AC_UD_INLINE_PUSH_CONSTANTS,
2236 count,
2237 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2238 }
2239
2240 if (need_push_constants) {
2241 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2242 16 * layout->dynamic_offset_count,
2243 256, &offset, &ptr))
2244 return;
2245
2246 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2247 memcpy((char*)ptr + layout->push_constant_size,
2248 descriptors_state->dynamic_buffers,
2249 16 * layout->dynamic_offset_count);
2250
2251 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2252 va += offset;
2253
2254 MAYBE_UNUSED unsigned cdw_max =
2255 radeon_check_space(cmd_buffer->device->ws,
2256 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2257
2258 prev_shader = NULL;
2259 radv_foreach_stage(stage, stages) {
2260 shader = radv_get_shader(pipeline, stage);
2261
2262 /* Avoid redundantly emitting the address for merged stages. */
2263 if (shader && shader != prev_shader) {
2264 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2265 AC_UD_PUSH_CONSTANTS, va);
2266
2267 prev_shader = shader;
2268 }
2269 }
2270 assert(cmd_buffer->cs->cdw <= cdw_max);
2271 }
2272
2273 cmd_buffer->push_constant_stages &= ~stages;
2274 }
2275
2276 static void
2277 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2278 bool pipeline_is_dirty)
2279 {
2280 if ((pipeline_is_dirty ||
2281 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2282 cmd_buffer->state.pipeline->num_vertex_bindings &&
2283 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
2284 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
2285 unsigned vb_offset;
2286 void *vb_ptr;
2287 uint32_t i = 0;
2288 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2289 uint64_t va;
2290
2291 /* allocate some descriptor state for vertex buffers */
2292 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2293 &vb_offset, &vb_ptr))
2294 return;
2295
2296 for (i = 0; i < count; i++) {
2297 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2298 uint32_t offset;
2299 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2300 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2301
2302 if (!buffer)
2303 continue;
2304
2305 va = radv_buffer_get_va(buffer->bo);
2306
2307 offset = cmd_buffer->vertex_bindings[i].offset;
2308 va += offset + buffer->offset;
2309 desc[0] = va;
2310 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2311 if (cmd_buffer->device->physical_device->rad_info.chip_class <= GFX7 && stride)
2312 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2313 else
2314 desc[2] = buffer->size - offset;
2315 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2316 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2317 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2318 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2319
2320 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2321 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2322 S_008F0C_OOB_SELECT(1) |
2323 S_008F0C_RESOURCE_LEVEL(1);
2324 } else {
2325 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2326 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2327 }
2328 }
2329
2330 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2331 va += vb_offset;
2332
2333 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2334 AC_UD_VS_VERTEX_BUFFERS, va);
2335
2336 cmd_buffer->state.vb_va = va;
2337 cmd_buffer->state.vb_size = count * 16;
2338 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2339 }
2340 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2341 }
2342
2343 static void
2344 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2345 {
2346 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2347 struct radv_userdata_info *loc;
2348 uint32_t base_reg;
2349
2350 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2351 if (!radv_get_shader(pipeline, stage))
2352 continue;
2353
2354 loc = radv_lookup_user_sgpr(pipeline, stage,
2355 AC_UD_STREAMOUT_BUFFERS);
2356 if (loc->sgpr_idx == -1)
2357 continue;
2358
2359 base_reg = pipeline->user_data_0[stage];
2360
2361 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2362 base_reg + loc->sgpr_idx * 4, va, false);
2363 }
2364
2365 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2366 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2367 if (loc->sgpr_idx != -1) {
2368 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2369
2370 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2371 base_reg + loc->sgpr_idx * 4, va, false);
2372 }
2373 }
2374 }
2375
2376 static void
2377 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2378 {
2379 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2380 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2381 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2382 unsigned so_offset;
2383 void *so_ptr;
2384 uint64_t va;
2385
2386 /* Allocate some descriptor state for streamout buffers. */
2387 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2388 MAX_SO_BUFFERS * 16, 256,
2389 &so_offset, &so_ptr))
2390 return;
2391
2392 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2393 struct radv_buffer *buffer = sb[i].buffer;
2394 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2395
2396 if (!(so->enabled_mask & (1 << i)))
2397 continue;
2398
2399 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2400
2401 va += sb[i].offset;
2402
2403 /* Set the descriptor.
2404 *
2405 * On GFX8, the format must be non-INVALID, otherwise
2406 * the buffer will be considered not bound and store
2407 * instructions will be no-ops.
2408 */
2409 desc[0] = va;
2410 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2411 desc[2] = 0xffffffff;
2412 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2413 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2414 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2415 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2416 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2417 }
2418
2419 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2420 va += so_offset;
2421
2422 radv_emit_streamout_buffers(cmd_buffer, va);
2423 }
2424
2425 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2426 }
2427
2428 static void
2429 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2430 {
2431 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2432 radv_flush_streamout_descriptors(cmd_buffer);
2433 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2434 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2435 }
2436
2437 struct radv_draw_info {
2438 /**
2439 * Number of vertices.
2440 */
2441 uint32_t count;
2442
2443 /**
2444 * Index of the first vertex.
2445 */
2446 int32_t vertex_offset;
2447
2448 /**
2449 * First instance id.
2450 */
2451 uint32_t first_instance;
2452
2453 /**
2454 * Number of instances.
2455 */
2456 uint32_t instance_count;
2457
2458 /**
2459 * First index (indexed draws only).
2460 */
2461 uint32_t first_index;
2462
2463 /**
2464 * Whether it's an indexed draw.
2465 */
2466 bool indexed;
2467
2468 /**
2469 * Indirect draw parameters resource.
2470 */
2471 struct radv_buffer *indirect;
2472 uint64_t indirect_offset;
2473 uint32_t stride;
2474
2475 /**
2476 * Draw count parameters resource.
2477 */
2478 struct radv_buffer *count_buffer;
2479 uint64_t count_buffer_offset;
2480
2481 /**
2482 * Stream output parameters resource.
2483 */
2484 struct radv_buffer *strmout_buffer;
2485 uint64_t strmout_buffer_offset;
2486 };
2487
2488 static void
2489 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2490 bool instanced_draw, bool indirect_draw,
2491 bool count_from_stream_output,
2492 uint32_t draw_vertex_count)
2493 {
2494 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2495 struct radv_cmd_state *state = &cmd_buffer->state;
2496 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2497 unsigned ia_multi_vgt_param;
2498
2499 ia_multi_vgt_param =
2500 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2501 indirect_draw,
2502 count_from_stream_output,
2503 draw_vertex_count);
2504
2505 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2506 if (info->chip_class >= GFX9) {
2507 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2508 cs,
2509 R_030960_IA_MULTI_VGT_PARAM,
2510 4, ia_multi_vgt_param);
2511 } else if (info->chip_class >= GFX7) {
2512 radeon_set_context_reg_idx(cs,
2513 R_028AA8_IA_MULTI_VGT_PARAM,
2514 1, ia_multi_vgt_param);
2515 } else {
2516 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2517 ia_multi_vgt_param);
2518 }
2519 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2520 }
2521 }
2522
2523 static void
2524 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2525 const struct radv_draw_info *draw_info)
2526 {
2527 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2528 struct radv_cmd_state *state = &cmd_buffer->state;
2529 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2530 int32_t primitive_reset_en;
2531
2532 /* Draw state. */
2533 if (info->chip_class < GFX10) {
2534 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2535 draw_info->indirect,
2536 !!draw_info->strmout_buffer,
2537 draw_info->indirect ? 0 : draw_info->count);
2538 }
2539
2540 /* Primitive restart. */
2541 primitive_reset_en =
2542 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2543
2544 if (primitive_reset_en != state->last_primitive_reset_en) {
2545 state->last_primitive_reset_en = primitive_reset_en;
2546 if (info->chip_class >= GFX9) {
2547 radeon_set_uconfig_reg(cs,
2548 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2549 primitive_reset_en);
2550 } else {
2551 radeon_set_context_reg(cs,
2552 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2553 primitive_reset_en);
2554 }
2555 }
2556
2557 if (primitive_reset_en) {
2558 uint32_t primitive_reset_index =
2559 state->index_type ? 0xffffffffu : 0xffffu;
2560
2561 if (primitive_reset_index != state->last_primitive_reset_index) {
2562 radeon_set_context_reg(cs,
2563 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2564 primitive_reset_index);
2565 state->last_primitive_reset_index = primitive_reset_index;
2566 }
2567 }
2568
2569 if (draw_info->strmout_buffer) {
2570 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2571
2572 va += draw_info->strmout_buffer->offset +
2573 draw_info->strmout_buffer_offset;
2574
2575 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2576 draw_info->stride);
2577
2578 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2579 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2580 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2581 COPY_DATA_WR_CONFIRM);
2582 radeon_emit(cs, va);
2583 radeon_emit(cs, va >> 32);
2584 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2585 radeon_emit(cs, 0); /* unused */
2586
2587 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2588 }
2589 }
2590
2591 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2592 VkPipelineStageFlags src_stage_mask)
2593 {
2594 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2595 VK_PIPELINE_STAGE_TRANSFER_BIT |
2596 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2597 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2598 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2599 }
2600
2601 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2602 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2603 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2604 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2605 VK_PIPELINE_STAGE_TRANSFER_BIT |
2606 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2607 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2608 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2609 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2610 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2611 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2612 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2613 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2614 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2615 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2616 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2617 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2618 }
2619 }
2620
2621 static enum radv_cmd_flush_bits
2622 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2623 VkAccessFlags src_flags,
2624 struct radv_image *image)
2625 {
2626 bool flush_CB_meta = true, flush_DB_meta = true;
2627 enum radv_cmd_flush_bits flush_bits = 0;
2628 uint32_t b;
2629
2630 if (image) {
2631 if (!radv_image_has_CB_metadata(image))
2632 flush_CB_meta = false;
2633 if (!radv_image_has_htile(image))
2634 flush_DB_meta = false;
2635 }
2636
2637 for_each_bit(b, src_flags) {
2638 switch ((VkAccessFlagBits)(1 << b)) {
2639 case VK_ACCESS_SHADER_WRITE_BIT:
2640 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2641 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2642 flush_bits |= RADV_CMD_FLAG_WB_L2;
2643 break;
2644 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2645 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2646 if (flush_CB_meta)
2647 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2648 break;
2649 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2650 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2651 if (flush_DB_meta)
2652 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2653 break;
2654 case VK_ACCESS_TRANSFER_WRITE_BIT:
2655 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2656 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2657 RADV_CMD_FLAG_INV_L2;
2658
2659 if (flush_CB_meta)
2660 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2661 if (flush_DB_meta)
2662 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2663 break;
2664 default:
2665 break;
2666 }
2667 }
2668 return flush_bits;
2669 }
2670
2671 static enum radv_cmd_flush_bits
2672 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2673 VkAccessFlags dst_flags,
2674 struct radv_image *image)
2675 {
2676 bool flush_CB_meta = true, flush_DB_meta = true;
2677 enum radv_cmd_flush_bits flush_bits = 0;
2678 bool flush_CB = true, flush_DB = true;
2679 bool image_is_coherent = false;
2680 uint32_t b;
2681
2682 if (image) {
2683 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2684 flush_CB = false;
2685 flush_DB = false;
2686 }
2687
2688 if (!radv_image_has_CB_metadata(image))
2689 flush_CB_meta = false;
2690 if (!radv_image_has_htile(image))
2691 flush_DB_meta = false;
2692
2693 /* TODO: implement shader coherent for GFX10 */
2694
2695 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2696 if (image->info.samples == 1 &&
2697 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2698 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2699 !vk_format_is_stencil(image->vk_format)) {
2700 /* Single-sample color and single-sample depth
2701 * (not stencil) are coherent with shaders on
2702 * GFX9.
2703 */
2704 image_is_coherent = true;
2705 }
2706 }
2707 }
2708
2709 for_each_bit(b, dst_flags) {
2710 switch ((VkAccessFlagBits)(1 << b)) {
2711 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2712 case VK_ACCESS_INDEX_READ_BIT:
2713 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2714 break;
2715 case VK_ACCESS_UNIFORM_READ_BIT:
2716 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2717 break;
2718 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2719 case VK_ACCESS_TRANSFER_READ_BIT:
2720 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2721 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2722 RADV_CMD_FLAG_INV_L2;
2723 break;
2724 case VK_ACCESS_SHADER_READ_BIT:
2725 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2726
2727 if (!image_is_coherent)
2728 flush_bits |= RADV_CMD_FLAG_INV_L2;
2729 break;
2730 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2731 if (flush_CB)
2732 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2733 if (flush_CB_meta)
2734 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2735 break;
2736 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2737 if (flush_DB)
2738 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2739 if (flush_DB_meta)
2740 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2741 break;
2742 default:
2743 break;
2744 }
2745 }
2746 return flush_bits;
2747 }
2748
2749 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2750 const struct radv_subpass_barrier *barrier)
2751 {
2752 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2753 NULL);
2754 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2755 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2756 NULL);
2757 }
2758
2759 uint32_t
2760 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2761 {
2762 struct radv_cmd_state *state = &cmd_buffer->state;
2763 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2764
2765 /* The id of this subpass shouldn't exceed the number of subpasses in
2766 * this render pass minus 1.
2767 */
2768 assert(subpass_id < state->pass->subpass_count);
2769 return subpass_id;
2770 }
2771
2772 static struct radv_sample_locations_state *
2773 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2774 uint32_t att_idx,
2775 bool begin_subpass)
2776 {
2777 struct radv_cmd_state *state = &cmd_buffer->state;
2778 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2779 struct radv_image_view *view = state->framebuffer->attachments[att_idx].attachment;
2780
2781 if (view->image->info.samples == 1)
2782 return NULL;
2783
2784 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2785 /* Return the initial sample locations if this is the initial
2786 * layout transition of the given subpass attachemnt.
2787 */
2788 if (state->attachments[att_idx].sample_location.count > 0)
2789 return &state->attachments[att_idx].sample_location;
2790 } else {
2791 /* Otherwise return the subpass sample locations if defined. */
2792 if (state->subpass_sample_locs) {
2793 /* Because the driver sets the current subpass before
2794 * initial layout transitions, we should use the sample
2795 * locations from the previous subpass to avoid an
2796 * off-by-one problem. Otherwise, use the sample
2797 * locations for the current subpass for final layout
2798 * transitions.
2799 */
2800 if (begin_subpass)
2801 subpass_id--;
2802
2803 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2804 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2805 return &state->subpass_sample_locs[i].sample_location;
2806 }
2807 }
2808 }
2809
2810 return NULL;
2811 }
2812
2813 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2814 struct radv_subpass_attachment att,
2815 bool begin_subpass)
2816 {
2817 unsigned idx = att.attachment;
2818 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2819 struct radv_sample_locations_state *sample_locs;
2820 VkImageSubresourceRange range;
2821 range.aspectMask = 0;
2822 range.baseMipLevel = view->base_mip;
2823 range.levelCount = 1;
2824 range.baseArrayLayer = view->base_layer;
2825 range.layerCount = cmd_buffer->state.framebuffer->layers;
2826
2827 if (cmd_buffer->state.subpass->view_mask) {
2828 /* If the current subpass uses multiview, the driver might have
2829 * performed a fast color/depth clear to the whole image
2830 * (including all layers). To make sure the driver will
2831 * decompress the image correctly (if needed), we have to
2832 * account for the "real" number of layers. If the view mask is
2833 * sparse, this will decompress more layers than needed.
2834 */
2835 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2836 }
2837
2838 /* Get the subpass sample locations for the given attachment, if NULL
2839 * is returned the driver will use the default HW locations.
2840 */
2841 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2842 begin_subpass);
2843
2844 radv_handle_image_transition(cmd_buffer,
2845 view->image,
2846 cmd_buffer->state.attachments[idx].current_layout,
2847 att.layout, 0, 0, &range, sample_locs);
2848
2849 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2850
2851
2852 }
2853
2854 void
2855 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2856 const struct radv_subpass *subpass)
2857 {
2858 cmd_buffer->state.subpass = subpass;
2859
2860 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2861 }
2862
2863 static VkResult
2864 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2865 struct radv_render_pass *pass,
2866 const VkRenderPassBeginInfo *info)
2867 {
2868 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
2869 vk_find_struct_const(info->pNext,
2870 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
2871 struct radv_cmd_state *state = &cmd_buffer->state;
2872 struct radv_framebuffer *framebuffer = state->framebuffer;
2873
2874 if (!sample_locs) {
2875 state->subpass_sample_locs = NULL;
2876 return VK_SUCCESS;
2877 }
2878
2879 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
2880 const VkAttachmentSampleLocationsEXT *att_sample_locs =
2881 &sample_locs->pAttachmentInitialSampleLocations[i];
2882 uint32_t att_idx = att_sample_locs->attachmentIndex;
2883 struct radv_attachment_info *att = &framebuffer->attachments[att_idx];
2884 struct radv_image *image = att->attachment->image;
2885
2886 assert(vk_format_is_depth_or_stencil(image->vk_format));
2887
2888 /* From the Vulkan spec 1.1.108:
2889 *
2890 * "If the image referenced by the framebuffer attachment at
2891 * index attachmentIndex was not created with
2892 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
2893 * then the values specified in sampleLocationsInfo are
2894 * ignored."
2895 */
2896 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
2897 continue;
2898
2899 const VkSampleLocationsInfoEXT *sample_locs_info =
2900 &att_sample_locs->sampleLocationsInfo;
2901
2902 state->attachments[att_idx].sample_location.per_pixel =
2903 sample_locs_info->sampleLocationsPerPixel;
2904 state->attachments[att_idx].sample_location.grid_size =
2905 sample_locs_info->sampleLocationGridSize;
2906 state->attachments[att_idx].sample_location.count =
2907 sample_locs_info->sampleLocationsCount;
2908 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
2909 sample_locs_info->pSampleLocations,
2910 sample_locs_info->sampleLocationsCount);
2911 }
2912
2913 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
2914 sample_locs->postSubpassSampleLocationsCount *
2915 sizeof(state->subpass_sample_locs[0]),
2916 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2917 if (state->subpass_sample_locs == NULL) {
2918 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2919 return cmd_buffer->record_result;
2920 }
2921
2922 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
2923
2924 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
2925 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
2926 &sample_locs->pPostSubpassSampleLocations[i];
2927 const VkSampleLocationsInfoEXT *sample_locs_info =
2928 &subpass_sample_locs_info->sampleLocationsInfo;
2929
2930 state->subpass_sample_locs[i].subpass_idx =
2931 subpass_sample_locs_info->subpassIndex;
2932 state->subpass_sample_locs[i].sample_location.per_pixel =
2933 sample_locs_info->sampleLocationsPerPixel;
2934 state->subpass_sample_locs[i].sample_location.grid_size =
2935 sample_locs_info->sampleLocationGridSize;
2936 state->subpass_sample_locs[i].sample_location.count =
2937 sample_locs_info->sampleLocationsCount;
2938 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
2939 sample_locs_info->pSampleLocations,
2940 sample_locs_info->sampleLocationsCount);
2941 }
2942
2943 return VK_SUCCESS;
2944 }
2945
2946 static VkResult
2947 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2948 struct radv_render_pass *pass,
2949 const VkRenderPassBeginInfo *info)
2950 {
2951 struct radv_cmd_state *state = &cmd_buffer->state;
2952
2953 if (pass->attachment_count == 0) {
2954 state->attachments = NULL;
2955 return VK_SUCCESS;
2956 }
2957
2958 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2959 pass->attachment_count *
2960 sizeof(state->attachments[0]),
2961 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2962 if (state->attachments == NULL) {
2963 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2964 return cmd_buffer->record_result;
2965 }
2966
2967 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2968 struct radv_render_pass_attachment *att = &pass->attachments[i];
2969 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2970 VkImageAspectFlags clear_aspects = 0;
2971
2972 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2973 /* color attachment */
2974 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2975 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2976 }
2977 } else {
2978 /* depthstencil attachment */
2979 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2980 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2981 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2982 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2983 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2984 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2985 }
2986 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2987 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2988 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2989 }
2990 }
2991
2992 state->attachments[i].pending_clear_aspects = clear_aspects;
2993 state->attachments[i].cleared_views = 0;
2994 if (clear_aspects && info) {
2995 assert(info->clearValueCount > i);
2996 state->attachments[i].clear_value = info->pClearValues[i];
2997 }
2998
2999 state->attachments[i].current_layout = att->initial_layout;
3000 state->attachments[i].sample_location.count = 0;
3001 }
3002
3003 return VK_SUCCESS;
3004 }
3005
3006 VkResult radv_AllocateCommandBuffers(
3007 VkDevice _device,
3008 const VkCommandBufferAllocateInfo *pAllocateInfo,
3009 VkCommandBuffer *pCommandBuffers)
3010 {
3011 RADV_FROM_HANDLE(radv_device, device, _device);
3012 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3013
3014 VkResult result = VK_SUCCESS;
3015 uint32_t i;
3016
3017 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3018
3019 if (!list_empty(&pool->free_cmd_buffers)) {
3020 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3021
3022 list_del(&cmd_buffer->pool_link);
3023 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3024
3025 result = radv_reset_cmd_buffer(cmd_buffer);
3026 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3027 cmd_buffer->level = pAllocateInfo->level;
3028
3029 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3030 } else {
3031 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3032 &pCommandBuffers[i]);
3033 }
3034 if (result != VK_SUCCESS)
3035 break;
3036 }
3037
3038 if (result != VK_SUCCESS) {
3039 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3040 i, pCommandBuffers);
3041
3042 /* From the Vulkan 1.0.66 spec:
3043 *
3044 * "vkAllocateCommandBuffers can be used to create multiple
3045 * command buffers. If the creation of any of those command
3046 * buffers fails, the implementation must destroy all
3047 * successfully created command buffer objects from this
3048 * command, set all entries of the pCommandBuffers array to
3049 * NULL and return the error."
3050 */
3051 memset(pCommandBuffers, 0,
3052 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3053 }
3054
3055 return result;
3056 }
3057
3058 void radv_FreeCommandBuffers(
3059 VkDevice device,
3060 VkCommandPool commandPool,
3061 uint32_t commandBufferCount,
3062 const VkCommandBuffer *pCommandBuffers)
3063 {
3064 for (uint32_t i = 0; i < commandBufferCount; i++) {
3065 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3066
3067 if (cmd_buffer) {
3068 if (cmd_buffer->pool) {
3069 list_del(&cmd_buffer->pool_link);
3070 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3071 } else
3072 radv_cmd_buffer_destroy(cmd_buffer);
3073
3074 }
3075 }
3076 }
3077
3078 VkResult radv_ResetCommandBuffer(
3079 VkCommandBuffer commandBuffer,
3080 VkCommandBufferResetFlags flags)
3081 {
3082 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3083 return radv_reset_cmd_buffer(cmd_buffer);
3084 }
3085
3086 VkResult radv_BeginCommandBuffer(
3087 VkCommandBuffer commandBuffer,
3088 const VkCommandBufferBeginInfo *pBeginInfo)
3089 {
3090 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3091 VkResult result = VK_SUCCESS;
3092
3093 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3094 /* If the command buffer has already been resetted with
3095 * vkResetCommandBuffer, no need to do it again.
3096 */
3097 result = radv_reset_cmd_buffer(cmd_buffer);
3098 if (result != VK_SUCCESS)
3099 return result;
3100 }
3101
3102 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3103 cmd_buffer->state.last_primitive_reset_en = -1;
3104 cmd_buffer->state.last_index_type = -1;
3105 cmd_buffer->state.last_num_instances = -1;
3106 cmd_buffer->state.last_vertex_offset = -1;
3107 cmd_buffer->state.last_first_instance = -1;
3108 cmd_buffer->state.predication_type = -1;
3109 cmd_buffer->usage_flags = pBeginInfo->flags;
3110
3111 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3112 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3113 assert(pBeginInfo->pInheritanceInfo);
3114 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3115 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3116
3117 struct radv_subpass *subpass =
3118 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3119
3120 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3121 if (result != VK_SUCCESS)
3122 return result;
3123
3124 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3125 }
3126
3127 if (unlikely(cmd_buffer->device->trace_bo)) {
3128 struct radv_device *device = cmd_buffer->device;
3129
3130 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3131 device->trace_bo);
3132
3133 radv_cmd_buffer_trace_emit(cmd_buffer);
3134 }
3135
3136 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3137
3138 return result;
3139 }
3140
3141 void radv_CmdBindVertexBuffers(
3142 VkCommandBuffer commandBuffer,
3143 uint32_t firstBinding,
3144 uint32_t bindingCount,
3145 const VkBuffer* pBuffers,
3146 const VkDeviceSize* pOffsets)
3147 {
3148 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3149 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3150 bool changed = false;
3151
3152 /* We have to defer setting up vertex buffer since we need the buffer
3153 * stride from the pipeline. */
3154
3155 assert(firstBinding + bindingCount <= MAX_VBS);
3156 for (uint32_t i = 0; i < bindingCount; i++) {
3157 uint32_t idx = firstBinding + i;
3158
3159 if (!changed &&
3160 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3161 vb[idx].offset != pOffsets[i])) {
3162 changed = true;
3163 }
3164
3165 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3166 vb[idx].offset = pOffsets[i];
3167
3168 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3169 vb[idx].buffer->bo);
3170 }
3171
3172 if (!changed) {
3173 /* No state changes. */
3174 return;
3175 }
3176
3177 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3178 }
3179
3180 void radv_CmdBindIndexBuffer(
3181 VkCommandBuffer commandBuffer,
3182 VkBuffer buffer,
3183 VkDeviceSize offset,
3184 VkIndexType indexType)
3185 {
3186 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3187 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3188
3189 if (cmd_buffer->state.index_buffer == index_buffer &&
3190 cmd_buffer->state.index_offset == offset &&
3191 cmd_buffer->state.index_type == indexType) {
3192 /* No state changes. */
3193 return;
3194 }
3195
3196 cmd_buffer->state.index_buffer = index_buffer;
3197 cmd_buffer->state.index_offset = offset;
3198 cmd_buffer->state.index_type = indexType; /* vk matches hw */
3199 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3200 cmd_buffer->state.index_va += index_buffer->offset + offset;
3201
3202 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
3203 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
3204 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3205 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3206 }
3207
3208
3209 static void
3210 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3211 VkPipelineBindPoint bind_point,
3212 struct radv_descriptor_set *set, unsigned idx)
3213 {
3214 struct radeon_winsys *ws = cmd_buffer->device->ws;
3215
3216 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3217
3218 assert(set);
3219 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3220
3221 if (!cmd_buffer->device->use_global_bo_list) {
3222 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3223 if (set->descriptors[j])
3224 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3225 }
3226
3227 if(set->bo)
3228 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3229 }
3230
3231 void radv_CmdBindDescriptorSets(
3232 VkCommandBuffer commandBuffer,
3233 VkPipelineBindPoint pipelineBindPoint,
3234 VkPipelineLayout _layout,
3235 uint32_t firstSet,
3236 uint32_t descriptorSetCount,
3237 const VkDescriptorSet* pDescriptorSets,
3238 uint32_t dynamicOffsetCount,
3239 const uint32_t* pDynamicOffsets)
3240 {
3241 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3242 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3243 unsigned dyn_idx = 0;
3244
3245 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3246 struct radv_descriptor_state *descriptors_state =
3247 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3248
3249 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3250 unsigned idx = i + firstSet;
3251 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3252 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3253
3254 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3255 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3256 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3257 assert(dyn_idx < dynamicOffsetCount);
3258
3259 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3260 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3261 dst[0] = va;
3262 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3263 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3264 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3265 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3266 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3267 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3268
3269 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3270 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3271 S_008F0C_OOB_SELECT(3) |
3272 S_008F0C_RESOURCE_LEVEL(1);
3273 } else {
3274 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3275 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3276 }
3277
3278 cmd_buffer->push_constant_stages |=
3279 set->layout->dynamic_shader_stages;
3280 }
3281 }
3282 }
3283
3284 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3285 struct radv_descriptor_set *set,
3286 struct radv_descriptor_set_layout *layout,
3287 VkPipelineBindPoint bind_point)
3288 {
3289 struct radv_descriptor_state *descriptors_state =
3290 radv_get_descriptors_state(cmd_buffer, bind_point);
3291 set->size = layout->size;
3292 set->layout = layout;
3293
3294 if (descriptors_state->push_set.capacity < set->size) {
3295 size_t new_size = MAX2(set->size, 1024);
3296 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3297 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3298
3299 free(set->mapped_ptr);
3300 set->mapped_ptr = malloc(new_size);
3301
3302 if (!set->mapped_ptr) {
3303 descriptors_state->push_set.capacity = 0;
3304 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3305 return false;
3306 }
3307
3308 descriptors_state->push_set.capacity = new_size;
3309 }
3310
3311 return true;
3312 }
3313
3314 void radv_meta_push_descriptor_set(
3315 struct radv_cmd_buffer* cmd_buffer,
3316 VkPipelineBindPoint pipelineBindPoint,
3317 VkPipelineLayout _layout,
3318 uint32_t set,
3319 uint32_t descriptorWriteCount,
3320 const VkWriteDescriptorSet* pDescriptorWrites)
3321 {
3322 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3323 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3324 unsigned bo_offset;
3325
3326 assert(set == 0);
3327 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3328
3329 push_set->size = layout->set[set].layout->size;
3330 push_set->layout = layout->set[set].layout;
3331
3332 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3333 &bo_offset,
3334 (void**) &push_set->mapped_ptr))
3335 return;
3336
3337 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3338 push_set->va += bo_offset;
3339
3340 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3341 radv_descriptor_set_to_handle(push_set),
3342 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3343
3344 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3345 }
3346
3347 void radv_CmdPushDescriptorSetKHR(
3348 VkCommandBuffer commandBuffer,
3349 VkPipelineBindPoint pipelineBindPoint,
3350 VkPipelineLayout _layout,
3351 uint32_t set,
3352 uint32_t descriptorWriteCount,
3353 const VkWriteDescriptorSet* pDescriptorWrites)
3354 {
3355 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3356 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3357 struct radv_descriptor_state *descriptors_state =
3358 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3359 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3360
3361 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3362
3363 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3364 layout->set[set].layout,
3365 pipelineBindPoint))
3366 return;
3367
3368 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3369 * because it is invalid, according to Vulkan spec.
3370 */
3371 for (int i = 0; i < descriptorWriteCount; i++) {
3372 MAYBE_UNUSED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3373 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3374 }
3375
3376 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3377 radv_descriptor_set_to_handle(push_set),
3378 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3379
3380 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3381 descriptors_state->push_dirty = true;
3382 }
3383
3384 void radv_CmdPushDescriptorSetWithTemplateKHR(
3385 VkCommandBuffer commandBuffer,
3386 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3387 VkPipelineLayout _layout,
3388 uint32_t set,
3389 const void* pData)
3390 {
3391 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3392 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3393 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3394 struct radv_descriptor_state *descriptors_state =
3395 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3396 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3397
3398 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3399
3400 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3401 layout->set[set].layout,
3402 templ->bind_point))
3403 return;
3404
3405 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3406 descriptorUpdateTemplate, pData);
3407
3408 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3409 descriptors_state->push_dirty = true;
3410 }
3411
3412 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3413 VkPipelineLayout layout,
3414 VkShaderStageFlags stageFlags,
3415 uint32_t offset,
3416 uint32_t size,
3417 const void* pValues)
3418 {
3419 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3420 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3421 cmd_buffer->push_constant_stages |= stageFlags;
3422 }
3423
3424 VkResult radv_EndCommandBuffer(
3425 VkCommandBuffer commandBuffer)
3426 {
3427 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3428
3429 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3430 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3431 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3432
3433 /* Make sure to sync all pending active queries at the end of
3434 * command buffer.
3435 */
3436 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3437
3438 si_emit_cache_flush(cmd_buffer);
3439 }
3440
3441 /* Make sure CP DMA is idle at the end of IBs because the kernel
3442 * doesn't wait for it.
3443 */
3444 si_cp_dma_wait_for_idle(cmd_buffer);
3445
3446 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3447 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3448
3449 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3450 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3451
3452 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3453
3454 return cmd_buffer->record_result;
3455 }
3456
3457 static void
3458 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3459 {
3460 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3461
3462 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3463 return;
3464
3465 assert(!pipeline->ctx_cs.cdw);
3466
3467 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3468
3469 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3470 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3471
3472 cmd_buffer->compute_scratch_size_needed =
3473 MAX2(cmd_buffer->compute_scratch_size_needed,
3474 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
3475
3476 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3477 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3478
3479 if (unlikely(cmd_buffer->device->trace_bo))
3480 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3481 }
3482
3483 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3484 VkPipelineBindPoint bind_point)
3485 {
3486 struct radv_descriptor_state *descriptors_state =
3487 radv_get_descriptors_state(cmd_buffer, bind_point);
3488
3489 descriptors_state->dirty |= descriptors_state->valid;
3490 }
3491
3492 void radv_CmdBindPipeline(
3493 VkCommandBuffer commandBuffer,
3494 VkPipelineBindPoint pipelineBindPoint,
3495 VkPipeline _pipeline)
3496 {
3497 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3498 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3499
3500 switch (pipelineBindPoint) {
3501 case VK_PIPELINE_BIND_POINT_COMPUTE:
3502 if (cmd_buffer->state.compute_pipeline == pipeline)
3503 return;
3504 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3505
3506 cmd_buffer->state.compute_pipeline = pipeline;
3507 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3508 break;
3509 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3510 if (cmd_buffer->state.pipeline == pipeline)
3511 return;
3512 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3513
3514 cmd_buffer->state.pipeline = pipeline;
3515 if (!pipeline)
3516 break;
3517
3518 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3519 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3520
3521 /* the new vertex shader might not have the same user regs */
3522 cmd_buffer->state.last_first_instance = -1;
3523 cmd_buffer->state.last_vertex_offset = -1;
3524
3525 /* Prefetch all pipeline shaders at first draw time. */
3526 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3527
3528 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3529 radv_bind_streamout_state(cmd_buffer, pipeline);
3530
3531 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3532 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3533 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3534 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3535
3536 if (radv_pipeline_has_tess(pipeline))
3537 cmd_buffer->tess_rings_needed = true;
3538 break;
3539 default:
3540 assert(!"invalid bind point");
3541 break;
3542 }
3543 }
3544
3545 void radv_CmdSetViewport(
3546 VkCommandBuffer commandBuffer,
3547 uint32_t firstViewport,
3548 uint32_t viewportCount,
3549 const VkViewport* pViewports)
3550 {
3551 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3552 struct radv_cmd_state *state = &cmd_buffer->state;
3553 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3554
3555 assert(firstViewport < MAX_VIEWPORTS);
3556 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3557
3558 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3559 pViewports, viewportCount * sizeof(*pViewports))) {
3560 return;
3561 }
3562
3563 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3564 viewportCount * sizeof(*pViewports));
3565
3566 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3567 }
3568
3569 void radv_CmdSetScissor(
3570 VkCommandBuffer commandBuffer,
3571 uint32_t firstScissor,
3572 uint32_t scissorCount,
3573 const VkRect2D* pScissors)
3574 {
3575 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3576 struct radv_cmd_state *state = &cmd_buffer->state;
3577 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3578
3579 assert(firstScissor < MAX_SCISSORS);
3580 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3581
3582 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3583 scissorCount * sizeof(*pScissors))) {
3584 return;
3585 }
3586
3587 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3588 scissorCount * sizeof(*pScissors));
3589
3590 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3591 }
3592
3593 void radv_CmdSetLineWidth(
3594 VkCommandBuffer commandBuffer,
3595 float lineWidth)
3596 {
3597 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3598
3599 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3600 return;
3601
3602 cmd_buffer->state.dynamic.line_width = lineWidth;
3603 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3604 }
3605
3606 void radv_CmdSetDepthBias(
3607 VkCommandBuffer commandBuffer,
3608 float depthBiasConstantFactor,
3609 float depthBiasClamp,
3610 float depthBiasSlopeFactor)
3611 {
3612 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3613 struct radv_cmd_state *state = &cmd_buffer->state;
3614
3615 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3616 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3617 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3618 return;
3619 }
3620
3621 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3622 state->dynamic.depth_bias.clamp = depthBiasClamp;
3623 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3624
3625 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3626 }
3627
3628 void radv_CmdSetBlendConstants(
3629 VkCommandBuffer commandBuffer,
3630 const float blendConstants[4])
3631 {
3632 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3633 struct radv_cmd_state *state = &cmd_buffer->state;
3634
3635 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3636 return;
3637
3638 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3639
3640 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3641 }
3642
3643 void radv_CmdSetDepthBounds(
3644 VkCommandBuffer commandBuffer,
3645 float minDepthBounds,
3646 float maxDepthBounds)
3647 {
3648 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3649 struct radv_cmd_state *state = &cmd_buffer->state;
3650
3651 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3652 state->dynamic.depth_bounds.max == maxDepthBounds) {
3653 return;
3654 }
3655
3656 state->dynamic.depth_bounds.min = minDepthBounds;
3657 state->dynamic.depth_bounds.max = maxDepthBounds;
3658
3659 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3660 }
3661
3662 void radv_CmdSetStencilCompareMask(
3663 VkCommandBuffer commandBuffer,
3664 VkStencilFaceFlags faceMask,
3665 uint32_t compareMask)
3666 {
3667 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3668 struct radv_cmd_state *state = &cmd_buffer->state;
3669 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3670 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3671
3672 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3673 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3674 return;
3675 }
3676
3677 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3678 state->dynamic.stencil_compare_mask.front = compareMask;
3679 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3680 state->dynamic.stencil_compare_mask.back = compareMask;
3681
3682 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3683 }
3684
3685 void radv_CmdSetStencilWriteMask(
3686 VkCommandBuffer commandBuffer,
3687 VkStencilFaceFlags faceMask,
3688 uint32_t writeMask)
3689 {
3690 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3691 struct radv_cmd_state *state = &cmd_buffer->state;
3692 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3693 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3694
3695 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3696 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3697 return;
3698 }
3699
3700 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3701 state->dynamic.stencil_write_mask.front = writeMask;
3702 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3703 state->dynamic.stencil_write_mask.back = writeMask;
3704
3705 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3706 }
3707
3708 void radv_CmdSetStencilReference(
3709 VkCommandBuffer commandBuffer,
3710 VkStencilFaceFlags faceMask,
3711 uint32_t reference)
3712 {
3713 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3714 struct radv_cmd_state *state = &cmd_buffer->state;
3715 bool front_same = state->dynamic.stencil_reference.front == reference;
3716 bool back_same = state->dynamic.stencil_reference.back == reference;
3717
3718 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3719 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3720 return;
3721 }
3722
3723 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3724 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3725 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3726 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3727
3728 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3729 }
3730
3731 void radv_CmdSetDiscardRectangleEXT(
3732 VkCommandBuffer commandBuffer,
3733 uint32_t firstDiscardRectangle,
3734 uint32_t discardRectangleCount,
3735 const VkRect2D* pDiscardRectangles)
3736 {
3737 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3738 struct radv_cmd_state *state = &cmd_buffer->state;
3739 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3740
3741 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3742 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3743
3744 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3745 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3746 return;
3747 }
3748
3749 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3750 pDiscardRectangles, discardRectangleCount);
3751
3752 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3753 }
3754
3755 void radv_CmdSetSampleLocationsEXT(
3756 VkCommandBuffer commandBuffer,
3757 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3758 {
3759 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3760 struct radv_cmd_state *state = &cmd_buffer->state;
3761
3762 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3763
3764 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3765 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3766 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3767 typed_memcpy(&state->dynamic.sample_location.locations[0],
3768 pSampleLocationsInfo->pSampleLocations,
3769 pSampleLocationsInfo->sampleLocationsCount);
3770
3771 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3772 }
3773
3774 void radv_CmdExecuteCommands(
3775 VkCommandBuffer commandBuffer,
3776 uint32_t commandBufferCount,
3777 const VkCommandBuffer* pCmdBuffers)
3778 {
3779 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3780
3781 assert(commandBufferCount > 0);
3782
3783 /* Emit pending flushes on primary prior to executing secondary */
3784 si_emit_cache_flush(primary);
3785
3786 for (uint32_t i = 0; i < commandBufferCount; i++) {
3787 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3788
3789 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3790 secondary->scratch_size_needed);
3791 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3792 secondary->compute_scratch_size_needed);
3793
3794 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3795 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3796 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3797 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3798 if (secondary->tess_rings_needed)
3799 primary->tess_rings_needed = true;
3800 if (secondary->sample_positions_needed)
3801 primary->sample_positions_needed = true;
3802
3803 if (!secondary->state.framebuffer &&
3804 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
3805 /* Emit the framebuffer state from primary if secondary
3806 * has been recorded without a framebuffer, otherwise
3807 * fast color/depth clears can't work.
3808 */
3809 radv_emit_framebuffer_state(primary);
3810 }
3811
3812 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3813
3814
3815 /* When the secondary command buffer is compute only we don't
3816 * need to re-emit the current graphics pipeline.
3817 */
3818 if (secondary->state.emitted_pipeline) {
3819 primary->state.emitted_pipeline =
3820 secondary->state.emitted_pipeline;
3821 }
3822
3823 /* When the secondary command buffer is graphics only we don't
3824 * need to re-emit the current compute pipeline.
3825 */
3826 if (secondary->state.emitted_compute_pipeline) {
3827 primary->state.emitted_compute_pipeline =
3828 secondary->state.emitted_compute_pipeline;
3829 }
3830
3831 /* Only re-emit the draw packets when needed. */
3832 if (secondary->state.last_primitive_reset_en != -1) {
3833 primary->state.last_primitive_reset_en =
3834 secondary->state.last_primitive_reset_en;
3835 }
3836
3837 if (secondary->state.last_primitive_reset_index) {
3838 primary->state.last_primitive_reset_index =
3839 secondary->state.last_primitive_reset_index;
3840 }
3841
3842 if (secondary->state.last_ia_multi_vgt_param) {
3843 primary->state.last_ia_multi_vgt_param =
3844 secondary->state.last_ia_multi_vgt_param;
3845 }
3846
3847 primary->state.last_first_instance = secondary->state.last_first_instance;
3848 primary->state.last_num_instances = secondary->state.last_num_instances;
3849 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3850
3851 if (secondary->state.last_index_type != -1) {
3852 primary->state.last_index_type =
3853 secondary->state.last_index_type;
3854 }
3855 }
3856
3857 /* After executing commands from secondary buffers we have to dirty
3858 * some states.
3859 */
3860 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3861 RADV_CMD_DIRTY_INDEX_BUFFER |
3862 RADV_CMD_DIRTY_DYNAMIC_ALL;
3863 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3864 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3865 }
3866
3867 VkResult radv_CreateCommandPool(
3868 VkDevice _device,
3869 const VkCommandPoolCreateInfo* pCreateInfo,
3870 const VkAllocationCallbacks* pAllocator,
3871 VkCommandPool* pCmdPool)
3872 {
3873 RADV_FROM_HANDLE(radv_device, device, _device);
3874 struct radv_cmd_pool *pool;
3875
3876 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3877 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3878 if (pool == NULL)
3879 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3880
3881 if (pAllocator)
3882 pool->alloc = *pAllocator;
3883 else
3884 pool->alloc = device->alloc;
3885
3886 list_inithead(&pool->cmd_buffers);
3887 list_inithead(&pool->free_cmd_buffers);
3888
3889 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3890
3891 *pCmdPool = radv_cmd_pool_to_handle(pool);
3892
3893 return VK_SUCCESS;
3894
3895 }
3896
3897 void radv_DestroyCommandPool(
3898 VkDevice _device,
3899 VkCommandPool commandPool,
3900 const VkAllocationCallbacks* pAllocator)
3901 {
3902 RADV_FROM_HANDLE(radv_device, device, _device);
3903 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3904
3905 if (!pool)
3906 return;
3907
3908 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3909 &pool->cmd_buffers, pool_link) {
3910 radv_cmd_buffer_destroy(cmd_buffer);
3911 }
3912
3913 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3914 &pool->free_cmd_buffers, pool_link) {
3915 radv_cmd_buffer_destroy(cmd_buffer);
3916 }
3917
3918 vk_free2(&device->alloc, pAllocator, pool);
3919 }
3920
3921 VkResult radv_ResetCommandPool(
3922 VkDevice device,
3923 VkCommandPool commandPool,
3924 VkCommandPoolResetFlags flags)
3925 {
3926 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3927 VkResult result;
3928
3929 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3930 &pool->cmd_buffers, pool_link) {
3931 result = radv_reset_cmd_buffer(cmd_buffer);
3932 if (result != VK_SUCCESS)
3933 return result;
3934 }
3935
3936 return VK_SUCCESS;
3937 }
3938
3939 void radv_TrimCommandPool(
3940 VkDevice device,
3941 VkCommandPool commandPool,
3942 VkCommandPoolTrimFlags flags)
3943 {
3944 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3945
3946 if (!pool)
3947 return;
3948
3949 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3950 &pool->free_cmd_buffers, pool_link) {
3951 radv_cmd_buffer_destroy(cmd_buffer);
3952 }
3953 }
3954
3955 static void
3956 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
3957 uint32_t subpass_id)
3958 {
3959 struct radv_cmd_state *state = &cmd_buffer->state;
3960 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
3961
3962 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3963 cmd_buffer->cs, 4096);
3964
3965 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
3966
3967 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3968
3969 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3970 const uint32_t a = subpass->attachments[i].attachment;
3971 if (a == VK_ATTACHMENT_UNUSED)
3972 continue;
3973
3974 radv_handle_subpass_image_transition(cmd_buffer,
3975 subpass->attachments[i],
3976 true);
3977 }
3978
3979 radv_cmd_buffer_clear_subpass(cmd_buffer);
3980
3981 assert(cmd_buffer->cs->cdw <= cdw_max);
3982 }
3983
3984 static void
3985 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
3986 {
3987 struct radv_cmd_state *state = &cmd_buffer->state;
3988 const struct radv_subpass *subpass = state->subpass;
3989 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3990
3991 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3992
3993 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3994 const uint32_t a = subpass->attachments[i].attachment;
3995 if (a == VK_ATTACHMENT_UNUSED)
3996 continue;
3997
3998 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
3999 continue;
4000
4001 VkImageLayout layout = state->pass->attachments[a].final_layout;
4002 struct radv_subpass_attachment att = { a, layout };
4003 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4004 }
4005 }
4006
4007 void radv_CmdBeginRenderPass(
4008 VkCommandBuffer commandBuffer,
4009 const VkRenderPassBeginInfo* pRenderPassBegin,
4010 VkSubpassContents contents)
4011 {
4012 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4013 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4014 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4015 VkResult result;
4016
4017 cmd_buffer->state.framebuffer = framebuffer;
4018 cmd_buffer->state.pass = pass;
4019 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4020
4021 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4022 if (result != VK_SUCCESS)
4023 return;
4024
4025 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4026 if (result != VK_SUCCESS)
4027 return;
4028
4029 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4030 }
4031
4032 void radv_CmdBeginRenderPass2KHR(
4033 VkCommandBuffer commandBuffer,
4034 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4035 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
4036 {
4037 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4038 pSubpassBeginInfo->contents);
4039 }
4040
4041 void radv_CmdNextSubpass(
4042 VkCommandBuffer commandBuffer,
4043 VkSubpassContents contents)
4044 {
4045 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4046
4047 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4048 radv_cmd_buffer_end_subpass(cmd_buffer);
4049 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4050 }
4051
4052 void radv_CmdNextSubpass2KHR(
4053 VkCommandBuffer commandBuffer,
4054 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
4055 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4056 {
4057 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4058 }
4059
4060 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4061 {
4062 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4063 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4064 if (!radv_get_shader(pipeline, stage))
4065 continue;
4066
4067 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4068 if (loc->sgpr_idx == -1)
4069 continue;
4070 uint32_t base_reg = pipeline->user_data_0[stage];
4071 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4072
4073 }
4074 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4075 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4076 if (loc->sgpr_idx != -1) {
4077 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4078 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4079 }
4080 }
4081 }
4082
4083 static void
4084 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4085 uint32_t vertex_count,
4086 bool use_opaque)
4087 {
4088 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4089 radeon_emit(cmd_buffer->cs, vertex_count);
4090 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4091 S_0287F0_USE_OPAQUE(use_opaque));
4092 }
4093
4094 static void
4095 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4096 uint64_t index_va,
4097 uint32_t index_count)
4098 {
4099 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4100 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4101 radeon_emit(cmd_buffer->cs, index_va);
4102 radeon_emit(cmd_buffer->cs, index_va >> 32);
4103 radeon_emit(cmd_buffer->cs, index_count);
4104 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4105 }
4106
4107 static void
4108 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4109 bool indexed,
4110 uint32_t draw_count,
4111 uint64_t count_va,
4112 uint32_t stride)
4113 {
4114 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4115 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4116 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4117 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
4118 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4119 bool predicating = cmd_buffer->state.predicating;
4120 assert(base_reg);
4121
4122 /* just reset draw state for vertex data */
4123 cmd_buffer->state.last_first_instance = -1;
4124 cmd_buffer->state.last_num_instances = -1;
4125 cmd_buffer->state.last_vertex_offset = -1;
4126
4127 if (draw_count == 1 && !count_va && !draw_id_enable) {
4128 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4129 PKT3_DRAW_INDIRECT, 3, predicating));
4130 radeon_emit(cs, 0);
4131 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4132 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4133 radeon_emit(cs, di_src_sel);
4134 } else {
4135 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4136 PKT3_DRAW_INDIRECT_MULTI,
4137 8, predicating));
4138 radeon_emit(cs, 0);
4139 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4140 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4141 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4142 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4143 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4144 radeon_emit(cs, draw_count); /* count */
4145 radeon_emit(cs, count_va); /* count_addr */
4146 radeon_emit(cs, count_va >> 32);
4147 radeon_emit(cs, stride); /* stride */
4148 radeon_emit(cs, di_src_sel);
4149 }
4150 }
4151
4152 static void
4153 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4154 const struct radv_draw_info *info)
4155 {
4156 struct radv_cmd_state *state = &cmd_buffer->state;
4157 struct radeon_winsys *ws = cmd_buffer->device->ws;
4158 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4159
4160 if (info->indirect) {
4161 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4162 uint64_t count_va = 0;
4163
4164 va += info->indirect->offset + info->indirect_offset;
4165
4166 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4167
4168 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4169 radeon_emit(cs, 1);
4170 radeon_emit(cs, va);
4171 radeon_emit(cs, va >> 32);
4172
4173 if (info->count_buffer) {
4174 count_va = radv_buffer_get_va(info->count_buffer->bo);
4175 count_va += info->count_buffer->offset +
4176 info->count_buffer_offset;
4177
4178 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4179 }
4180
4181 if (!state->subpass->view_mask) {
4182 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4183 info->indexed,
4184 info->count,
4185 count_va,
4186 info->stride);
4187 } else {
4188 unsigned i;
4189 for_each_bit(i, state->subpass->view_mask) {
4190 radv_emit_view_index(cmd_buffer, i);
4191
4192 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4193 info->indexed,
4194 info->count,
4195 count_va,
4196 info->stride);
4197 }
4198 }
4199 } else {
4200 assert(state->pipeline->graphics.vtx_base_sgpr);
4201
4202 if (info->vertex_offset != state->last_vertex_offset ||
4203 info->first_instance != state->last_first_instance) {
4204 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4205 state->pipeline->graphics.vtx_emit_num);
4206
4207 radeon_emit(cs, info->vertex_offset);
4208 radeon_emit(cs, info->first_instance);
4209 if (state->pipeline->graphics.vtx_emit_num == 3)
4210 radeon_emit(cs, 0);
4211 state->last_first_instance = info->first_instance;
4212 state->last_vertex_offset = info->vertex_offset;
4213 }
4214
4215 if (state->last_num_instances != info->instance_count) {
4216 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4217 radeon_emit(cs, info->instance_count);
4218 state->last_num_instances = info->instance_count;
4219 }
4220
4221 if (info->indexed) {
4222 int index_size = state->index_type ? 4 : 2;
4223 uint64_t index_va;
4224
4225 index_va = state->index_va;
4226 index_va += info->first_index * index_size;
4227
4228 if (!state->subpass->view_mask) {
4229 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4230 index_va,
4231 info->count);
4232 } else {
4233 unsigned i;
4234 for_each_bit(i, state->subpass->view_mask) {
4235 radv_emit_view_index(cmd_buffer, i);
4236
4237 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4238 index_va,
4239 info->count);
4240 }
4241 }
4242 } else {
4243 if (!state->subpass->view_mask) {
4244 radv_cs_emit_draw_packet(cmd_buffer,
4245 info->count,
4246 !!info->strmout_buffer);
4247 } else {
4248 unsigned i;
4249 for_each_bit(i, state->subpass->view_mask) {
4250 radv_emit_view_index(cmd_buffer, i);
4251
4252 radv_cs_emit_draw_packet(cmd_buffer,
4253 info->count,
4254 !!info->strmout_buffer);
4255 }
4256 }
4257 }
4258 }
4259 }
4260
4261 /*
4262 * Vega and raven have a bug which triggers if there are multiple context
4263 * register contexts active at the same time with different scissor values.
4264 *
4265 * There are two possible workarounds:
4266 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4267 * there is only ever 1 active set of scissor values at the same time.
4268 *
4269 * 2) Whenever the hardware switches contexts we have to set the scissor
4270 * registers again even if it is a noop. That way the new context gets
4271 * the correct scissor values.
4272 *
4273 * This implements option 2. radv_need_late_scissor_emission needs to
4274 * return true on affected HW if radv_emit_all_graphics_states sets
4275 * any context registers.
4276 */
4277 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4278 const struct radv_draw_info *info)
4279 {
4280 struct radv_cmd_state *state = &cmd_buffer->state;
4281
4282 if (!cmd_buffer->device->physical_device->has_scissor_bug)
4283 return false;
4284
4285 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4286 return true;
4287
4288 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4289
4290 /* Index, vertex and streamout buffers don't change context regs, and
4291 * pipeline is already handled.
4292 */
4293 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4294 RADV_CMD_DIRTY_VERTEX_BUFFER |
4295 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4296 RADV_CMD_DIRTY_PIPELINE);
4297
4298 if (cmd_buffer->state.dirty & used_states)
4299 return true;
4300
4301 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4302 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
4303 return true;
4304
4305 return false;
4306 }
4307
4308 static void
4309 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4310 const struct radv_draw_info *info)
4311 {
4312 bool late_scissor_emission;
4313
4314 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4315 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4316 radv_emit_rbplus_state(cmd_buffer);
4317
4318 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4319 radv_emit_graphics_pipeline(cmd_buffer);
4320
4321 /* This should be before the cmd_buffer->state.dirty is cleared
4322 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4323 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4324 late_scissor_emission =
4325 radv_need_late_scissor_emission(cmd_buffer, info);
4326
4327 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4328 radv_emit_framebuffer_state(cmd_buffer);
4329
4330 if (info->indexed) {
4331 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4332 radv_emit_index_buffer(cmd_buffer);
4333 } else {
4334 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4335 * so the state must be re-emitted before the next indexed
4336 * draw.
4337 */
4338 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4339 cmd_buffer->state.last_index_type = -1;
4340 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4341 }
4342 }
4343
4344 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4345
4346 radv_emit_draw_registers(cmd_buffer, info);
4347
4348 if (late_scissor_emission)
4349 radv_emit_scissor(cmd_buffer);
4350 }
4351
4352 static void
4353 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4354 const struct radv_draw_info *info)
4355 {
4356 struct radeon_info *rad_info =
4357 &cmd_buffer->device->physical_device->rad_info;
4358 bool has_prefetch =
4359 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4360 bool pipeline_is_dirty =
4361 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4362 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4363
4364 MAYBE_UNUSED unsigned cdw_max =
4365 radeon_check_space(cmd_buffer->device->ws,
4366 cmd_buffer->cs, 4096);
4367
4368 if (likely(!info->indirect)) {
4369 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4370 * no workaround for indirect draws, but we can at least skip
4371 * direct draws.
4372 */
4373 if (unlikely(!info->instance_count))
4374 return;
4375
4376 /* Handle count == 0. */
4377 if (unlikely(!info->count && !info->strmout_buffer))
4378 return;
4379 }
4380
4381 /* Use optimal packet order based on whether we need to sync the
4382 * pipeline.
4383 */
4384 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4385 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4386 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4387 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4388 /* If we have to wait for idle, set all states first, so that
4389 * all SET packets are processed in parallel with previous draw
4390 * calls. Then upload descriptors, set shader pointers, and
4391 * draw, and prefetch at the end. This ensures that the time
4392 * the CUs are idle is very short. (there are only SET_SH
4393 * packets between the wait and the draw)
4394 */
4395 radv_emit_all_graphics_states(cmd_buffer, info);
4396 si_emit_cache_flush(cmd_buffer);
4397 /* <-- CUs are idle here --> */
4398
4399 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4400
4401 radv_emit_draw_packets(cmd_buffer, info);
4402 /* <-- CUs are busy here --> */
4403
4404 /* Start prefetches after the draw has been started. Both will
4405 * run in parallel, but starting the draw first is more
4406 * important.
4407 */
4408 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4409 radv_emit_prefetch_L2(cmd_buffer,
4410 cmd_buffer->state.pipeline, false);
4411 }
4412 } else {
4413 /* If we don't wait for idle, start prefetches first, then set
4414 * states, and draw at the end.
4415 */
4416 si_emit_cache_flush(cmd_buffer);
4417
4418 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4419 /* Only prefetch the vertex shader and VBO descriptors
4420 * in order to start the draw as soon as possible.
4421 */
4422 radv_emit_prefetch_L2(cmd_buffer,
4423 cmd_buffer->state.pipeline, true);
4424 }
4425
4426 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4427
4428 radv_emit_all_graphics_states(cmd_buffer, info);
4429 radv_emit_draw_packets(cmd_buffer, info);
4430
4431 /* Prefetch the remaining shaders after the draw has been
4432 * started.
4433 */
4434 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4435 radv_emit_prefetch_L2(cmd_buffer,
4436 cmd_buffer->state.pipeline, false);
4437 }
4438 }
4439
4440 /* Workaround for a VGT hang when streamout is enabled.
4441 * It must be done after drawing.
4442 */
4443 if (cmd_buffer->state.streamout.streamout_enabled &&
4444 (rad_info->family == CHIP_HAWAII ||
4445 rad_info->family == CHIP_TONGA ||
4446 rad_info->family == CHIP_FIJI)) {
4447 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4448 }
4449
4450 assert(cmd_buffer->cs->cdw <= cdw_max);
4451 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4452 }
4453
4454 void radv_CmdDraw(
4455 VkCommandBuffer commandBuffer,
4456 uint32_t vertexCount,
4457 uint32_t instanceCount,
4458 uint32_t firstVertex,
4459 uint32_t firstInstance)
4460 {
4461 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4462 struct radv_draw_info info = {};
4463
4464 info.count = vertexCount;
4465 info.instance_count = instanceCount;
4466 info.first_instance = firstInstance;
4467 info.vertex_offset = firstVertex;
4468
4469 radv_draw(cmd_buffer, &info);
4470 }
4471
4472 void radv_CmdDrawIndexed(
4473 VkCommandBuffer commandBuffer,
4474 uint32_t indexCount,
4475 uint32_t instanceCount,
4476 uint32_t firstIndex,
4477 int32_t vertexOffset,
4478 uint32_t firstInstance)
4479 {
4480 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4481 struct radv_draw_info info = {};
4482
4483 info.indexed = true;
4484 info.count = indexCount;
4485 info.instance_count = instanceCount;
4486 info.first_index = firstIndex;
4487 info.vertex_offset = vertexOffset;
4488 info.first_instance = firstInstance;
4489
4490 radv_draw(cmd_buffer, &info);
4491 }
4492
4493 void radv_CmdDrawIndirect(
4494 VkCommandBuffer commandBuffer,
4495 VkBuffer _buffer,
4496 VkDeviceSize offset,
4497 uint32_t drawCount,
4498 uint32_t stride)
4499 {
4500 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4501 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4502 struct radv_draw_info info = {};
4503
4504 info.count = drawCount;
4505 info.indirect = buffer;
4506 info.indirect_offset = offset;
4507 info.stride = stride;
4508
4509 radv_draw(cmd_buffer, &info);
4510 }
4511
4512 void radv_CmdDrawIndexedIndirect(
4513 VkCommandBuffer commandBuffer,
4514 VkBuffer _buffer,
4515 VkDeviceSize offset,
4516 uint32_t drawCount,
4517 uint32_t stride)
4518 {
4519 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4520 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4521 struct radv_draw_info info = {};
4522
4523 info.indexed = true;
4524 info.count = drawCount;
4525 info.indirect = buffer;
4526 info.indirect_offset = offset;
4527 info.stride = stride;
4528
4529 radv_draw(cmd_buffer, &info);
4530 }
4531
4532 void radv_CmdDrawIndirectCountKHR(
4533 VkCommandBuffer commandBuffer,
4534 VkBuffer _buffer,
4535 VkDeviceSize offset,
4536 VkBuffer _countBuffer,
4537 VkDeviceSize countBufferOffset,
4538 uint32_t maxDrawCount,
4539 uint32_t stride)
4540 {
4541 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4542 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4543 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4544 struct radv_draw_info info = {};
4545
4546 info.count = maxDrawCount;
4547 info.indirect = buffer;
4548 info.indirect_offset = offset;
4549 info.count_buffer = count_buffer;
4550 info.count_buffer_offset = countBufferOffset;
4551 info.stride = stride;
4552
4553 radv_draw(cmd_buffer, &info);
4554 }
4555
4556 void radv_CmdDrawIndexedIndirectCountKHR(
4557 VkCommandBuffer commandBuffer,
4558 VkBuffer _buffer,
4559 VkDeviceSize offset,
4560 VkBuffer _countBuffer,
4561 VkDeviceSize countBufferOffset,
4562 uint32_t maxDrawCount,
4563 uint32_t stride)
4564 {
4565 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4566 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4567 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4568 struct radv_draw_info info = {};
4569
4570 info.indexed = true;
4571 info.count = maxDrawCount;
4572 info.indirect = buffer;
4573 info.indirect_offset = offset;
4574 info.count_buffer = count_buffer;
4575 info.count_buffer_offset = countBufferOffset;
4576 info.stride = stride;
4577
4578 radv_draw(cmd_buffer, &info);
4579 }
4580
4581 struct radv_dispatch_info {
4582 /**
4583 * Determine the layout of the grid (in block units) to be used.
4584 */
4585 uint32_t blocks[3];
4586
4587 /**
4588 * A starting offset for the grid. If unaligned is set, the offset
4589 * must still be aligned.
4590 */
4591 uint32_t offsets[3];
4592 /**
4593 * Whether it's an unaligned compute dispatch.
4594 */
4595 bool unaligned;
4596
4597 /**
4598 * Indirect compute parameters resource.
4599 */
4600 struct radv_buffer *indirect;
4601 uint64_t indirect_offset;
4602 };
4603
4604 static void
4605 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4606 const struct radv_dispatch_info *info)
4607 {
4608 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4609 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4610 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4611 struct radeon_winsys *ws = cmd_buffer->device->ws;
4612 bool predicating = cmd_buffer->state.predicating;
4613 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4614 struct radv_userdata_info *loc;
4615
4616 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4617 AC_UD_CS_GRID_SIZE);
4618
4619 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4620
4621 if (info->indirect) {
4622 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4623
4624 va += info->indirect->offset + info->indirect_offset;
4625
4626 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4627
4628 if (loc->sgpr_idx != -1) {
4629 for (unsigned i = 0; i < 3; ++i) {
4630 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4631 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4632 COPY_DATA_DST_SEL(COPY_DATA_REG));
4633 radeon_emit(cs, (va + 4 * i));
4634 radeon_emit(cs, (va + 4 * i) >> 32);
4635 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4636 + loc->sgpr_idx * 4) >> 2) + i);
4637 radeon_emit(cs, 0);
4638 }
4639 }
4640
4641 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4642 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4643 PKT3_SHADER_TYPE_S(1));
4644 radeon_emit(cs, va);
4645 radeon_emit(cs, va >> 32);
4646 radeon_emit(cs, dispatch_initiator);
4647 } else {
4648 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4649 PKT3_SHADER_TYPE_S(1));
4650 radeon_emit(cs, 1);
4651 radeon_emit(cs, va);
4652 radeon_emit(cs, va >> 32);
4653
4654 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4655 PKT3_SHADER_TYPE_S(1));
4656 radeon_emit(cs, 0);
4657 radeon_emit(cs, dispatch_initiator);
4658 }
4659 } else {
4660 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4661 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4662
4663 if (info->unaligned) {
4664 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4665 unsigned remainder[3];
4666
4667 /* If aligned, these should be an entire block size,
4668 * not 0.
4669 */
4670 remainder[0] = blocks[0] + cs_block_size[0] -
4671 align_u32_npot(blocks[0], cs_block_size[0]);
4672 remainder[1] = blocks[1] + cs_block_size[1] -
4673 align_u32_npot(blocks[1], cs_block_size[1]);
4674 remainder[2] = blocks[2] + cs_block_size[2] -
4675 align_u32_npot(blocks[2], cs_block_size[2]);
4676
4677 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4678 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4679 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4680
4681 for(unsigned i = 0; i < 3; ++i) {
4682 assert(offsets[i] % cs_block_size[i] == 0);
4683 offsets[i] /= cs_block_size[i];
4684 }
4685
4686 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4687 radeon_emit(cs,
4688 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4689 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4690 radeon_emit(cs,
4691 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4692 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4693 radeon_emit(cs,
4694 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4695 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4696
4697 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4698 }
4699
4700 if (loc->sgpr_idx != -1) {
4701 assert(loc->num_sgprs == 3);
4702
4703 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4704 loc->sgpr_idx * 4, 3);
4705 radeon_emit(cs, blocks[0]);
4706 radeon_emit(cs, blocks[1]);
4707 radeon_emit(cs, blocks[2]);
4708 }
4709
4710 if (offsets[0] || offsets[1] || offsets[2]) {
4711 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4712 radeon_emit(cs, offsets[0]);
4713 radeon_emit(cs, offsets[1]);
4714 radeon_emit(cs, offsets[2]);
4715
4716 /* The blocks in the packet are not counts but end values. */
4717 for (unsigned i = 0; i < 3; ++i)
4718 blocks[i] += offsets[i];
4719 } else {
4720 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4721 }
4722
4723 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4724 PKT3_SHADER_TYPE_S(1));
4725 radeon_emit(cs, blocks[0]);
4726 radeon_emit(cs, blocks[1]);
4727 radeon_emit(cs, blocks[2]);
4728 radeon_emit(cs, dispatch_initiator);
4729 }
4730
4731 assert(cmd_buffer->cs->cdw <= cdw_max);
4732 }
4733
4734 static void
4735 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4736 {
4737 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4738 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4739 }
4740
4741 static void
4742 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4743 const struct radv_dispatch_info *info)
4744 {
4745 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4746 bool has_prefetch =
4747 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4748 bool pipeline_is_dirty = pipeline &&
4749 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4750
4751 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4752 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4753 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4754 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4755 /* If we have to wait for idle, set all states first, so that
4756 * all SET packets are processed in parallel with previous draw
4757 * calls. Then upload descriptors, set shader pointers, and
4758 * dispatch, and prefetch at the end. This ensures that the
4759 * time the CUs are idle is very short. (there are only SET_SH
4760 * packets between the wait and the draw)
4761 */
4762 radv_emit_compute_pipeline(cmd_buffer);
4763 si_emit_cache_flush(cmd_buffer);
4764 /* <-- CUs are idle here --> */
4765
4766 radv_upload_compute_shader_descriptors(cmd_buffer);
4767
4768 radv_emit_dispatch_packets(cmd_buffer, info);
4769 /* <-- CUs are busy here --> */
4770
4771 /* Start prefetches after the dispatch has been started. Both
4772 * will run in parallel, but starting the dispatch first is
4773 * more important.
4774 */
4775 if (has_prefetch && pipeline_is_dirty) {
4776 radv_emit_shader_prefetch(cmd_buffer,
4777 pipeline->shaders[MESA_SHADER_COMPUTE]);
4778 }
4779 } else {
4780 /* If we don't wait for idle, start prefetches first, then set
4781 * states, and dispatch at the end.
4782 */
4783 si_emit_cache_flush(cmd_buffer);
4784
4785 if (has_prefetch && pipeline_is_dirty) {
4786 radv_emit_shader_prefetch(cmd_buffer,
4787 pipeline->shaders[MESA_SHADER_COMPUTE]);
4788 }
4789
4790 radv_upload_compute_shader_descriptors(cmd_buffer);
4791
4792 radv_emit_compute_pipeline(cmd_buffer);
4793 radv_emit_dispatch_packets(cmd_buffer, info);
4794 }
4795
4796 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4797 }
4798
4799 void radv_CmdDispatchBase(
4800 VkCommandBuffer commandBuffer,
4801 uint32_t base_x,
4802 uint32_t base_y,
4803 uint32_t base_z,
4804 uint32_t x,
4805 uint32_t y,
4806 uint32_t z)
4807 {
4808 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4809 struct radv_dispatch_info info = {};
4810
4811 info.blocks[0] = x;
4812 info.blocks[1] = y;
4813 info.blocks[2] = z;
4814
4815 info.offsets[0] = base_x;
4816 info.offsets[1] = base_y;
4817 info.offsets[2] = base_z;
4818 radv_dispatch(cmd_buffer, &info);
4819 }
4820
4821 void radv_CmdDispatch(
4822 VkCommandBuffer commandBuffer,
4823 uint32_t x,
4824 uint32_t y,
4825 uint32_t z)
4826 {
4827 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4828 }
4829
4830 void radv_CmdDispatchIndirect(
4831 VkCommandBuffer commandBuffer,
4832 VkBuffer _buffer,
4833 VkDeviceSize offset)
4834 {
4835 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4836 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4837 struct radv_dispatch_info info = {};
4838
4839 info.indirect = buffer;
4840 info.indirect_offset = offset;
4841
4842 radv_dispatch(cmd_buffer, &info);
4843 }
4844
4845 void radv_unaligned_dispatch(
4846 struct radv_cmd_buffer *cmd_buffer,
4847 uint32_t x,
4848 uint32_t y,
4849 uint32_t z)
4850 {
4851 struct radv_dispatch_info info = {};
4852
4853 info.blocks[0] = x;
4854 info.blocks[1] = y;
4855 info.blocks[2] = z;
4856 info.unaligned = 1;
4857
4858 radv_dispatch(cmd_buffer, &info);
4859 }
4860
4861 void radv_CmdEndRenderPass(
4862 VkCommandBuffer commandBuffer)
4863 {
4864 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4865
4866 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4867
4868 radv_cmd_buffer_end_subpass(cmd_buffer);
4869
4870 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4871 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
4872
4873 cmd_buffer->state.pass = NULL;
4874 cmd_buffer->state.subpass = NULL;
4875 cmd_buffer->state.attachments = NULL;
4876 cmd_buffer->state.framebuffer = NULL;
4877 cmd_buffer->state.subpass_sample_locs = NULL;
4878 }
4879
4880 void radv_CmdEndRenderPass2KHR(
4881 VkCommandBuffer commandBuffer,
4882 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4883 {
4884 radv_CmdEndRenderPass(commandBuffer);
4885 }
4886
4887 /*
4888 * For HTILE we have the following interesting clear words:
4889 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4890 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4891 * 0xfffffff0: Clear depth to 1.0
4892 * 0x00000000: Clear depth to 0.0
4893 */
4894 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4895 struct radv_image *image,
4896 const VkImageSubresourceRange *range,
4897 uint32_t clear_word)
4898 {
4899 assert(range->baseMipLevel == 0);
4900 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4901 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4902 struct radv_cmd_state *state = &cmd_buffer->state;
4903 VkClearDepthStencilValue value = {};
4904
4905 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4906 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4907
4908 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
4909
4910 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4911
4912 if (vk_format_is_stencil(image->vk_format))
4913 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4914
4915 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4916
4917 if (radv_image_is_tc_compat_htile(image)) {
4918 /* Initialize the TC-compat metada value to 0 because by
4919 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4920 * need have to conditionally update its value when performing
4921 * a fast depth clear.
4922 */
4923 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4924 }
4925 }
4926
4927 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4928 struct radv_image *image,
4929 VkImageLayout src_layout,
4930 VkImageLayout dst_layout,
4931 unsigned src_queue_mask,
4932 unsigned dst_queue_mask,
4933 const VkImageSubresourceRange *range,
4934 struct radv_sample_locations_state *sample_locs)
4935 {
4936 if (!radv_image_has_htile(image))
4937 return;
4938
4939 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4940 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4941
4942 if (radv_layout_is_htile_compressed(image, dst_layout,
4943 dst_queue_mask)) {
4944 clear_value = 0;
4945 }
4946
4947 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4948 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4949 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4950 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4951 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4952 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4953 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4954 VkImageSubresourceRange local_range = *range;
4955 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4956 local_range.baseMipLevel = 0;
4957 local_range.levelCount = 1;
4958
4959 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4960 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4961
4962 radv_decompress_depth_image_inplace(cmd_buffer, image,
4963 &local_range, sample_locs);
4964
4965 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4966 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4967 }
4968 }
4969
4970 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4971 struct radv_image *image,
4972 const VkImageSubresourceRange *range,
4973 uint32_t value)
4974 {
4975 struct radv_cmd_state *state = &cmd_buffer->state;
4976
4977 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4978 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4979
4980 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
4981
4982 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4983 }
4984
4985 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4986 struct radv_image *image,
4987 const VkImageSubresourceRange *range)
4988 {
4989 struct radv_cmd_state *state = &cmd_buffer->state;
4990 static const uint32_t fmask_clear_values[4] = {
4991 0x00000000,
4992 0x02020202,
4993 0xE4E4E4E4,
4994 0x76543210
4995 };
4996 uint32_t log2_samples = util_logbase2(image->info.samples);
4997 uint32_t value = fmask_clear_values[log2_samples];
4998
4999 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5000 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5001
5002 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5003
5004 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5005 }
5006
5007 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5008 struct radv_image *image,
5009 const VkImageSubresourceRange *range, uint32_t value)
5010 {
5011 struct radv_cmd_state *state = &cmd_buffer->state;
5012 unsigned size = 0;
5013
5014 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5015 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5016
5017 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5018
5019 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5020 /* When DCC is enabled with mipmaps, some levels might not
5021 * support fast clears and we have to initialize them as "fully
5022 * expanded".
5023 */
5024 /* Compute the size of all fast clearable DCC levels. */
5025 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5026 struct legacy_surf_level *surf_level =
5027 &image->planes[0].surface.u.legacy.level[i];
5028 unsigned dcc_fast_clear_size =
5029 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5030
5031 if (!dcc_fast_clear_size)
5032 break;
5033
5034 size = surf_level->dcc_offset + dcc_fast_clear_size;
5035 }
5036
5037 /* Initialize the mipmap levels without DCC. */
5038 if (size != image->planes[0].surface.dcc_size) {
5039 state->flush_bits |=
5040 radv_fill_buffer(cmd_buffer, image->bo,
5041 image->offset + image->dcc_offset + size,
5042 image->planes[0].surface.dcc_size - size,
5043 0xffffffff);
5044 }
5045 }
5046
5047 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5048 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5049 }
5050
5051 /**
5052 * Initialize DCC/FMASK/CMASK metadata for a color image.
5053 */
5054 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5055 struct radv_image *image,
5056 VkImageLayout src_layout,
5057 VkImageLayout dst_layout,
5058 unsigned src_queue_mask,
5059 unsigned dst_queue_mask,
5060 const VkImageSubresourceRange *range)
5061 {
5062 if (radv_image_has_cmask(image)) {
5063 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5064
5065 /* TODO: clarify this. */
5066 if (radv_image_has_fmask(image)) {
5067 value = 0xccccccccu;
5068 }
5069
5070 radv_initialise_cmask(cmd_buffer, image, range, value);
5071 }
5072
5073 if (radv_image_has_fmask(image)) {
5074 radv_initialize_fmask(cmd_buffer, image, range);
5075 }
5076
5077 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5078 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5079 bool need_decompress_pass = false;
5080
5081 if (radv_layout_dcc_compressed(image, dst_layout,
5082 dst_queue_mask)) {
5083 value = 0x20202020u;
5084 need_decompress_pass = true;
5085 }
5086
5087 radv_initialize_dcc(cmd_buffer, image, range, value);
5088
5089 radv_update_fce_metadata(cmd_buffer, image, range,
5090 need_decompress_pass);
5091 }
5092
5093 if (radv_image_has_cmask(image) ||
5094 radv_dcc_enabled(image, range->baseMipLevel)) {
5095 uint32_t color_values[2] = {};
5096 radv_set_color_clear_metadata(cmd_buffer, image, range,
5097 color_values);
5098 }
5099 }
5100
5101 /**
5102 * Handle color image transitions for DCC/FMASK/CMASK.
5103 */
5104 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5105 struct radv_image *image,
5106 VkImageLayout src_layout,
5107 VkImageLayout dst_layout,
5108 unsigned src_queue_mask,
5109 unsigned dst_queue_mask,
5110 const VkImageSubresourceRange *range)
5111 {
5112 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5113 radv_init_color_image_metadata(cmd_buffer, image,
5114 src_layout, dst_layout,
5115 src_queue_mask, dst_queue_mask,
5116 range);
5117 return;
5118 }
5119
5120 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5121 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5122 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5123 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
5124 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
5125 radv_decompress_dcc(cmd_buffer, image, range);
5126 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5127 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5128 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5129 }
5130 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5131 bool fce_eliminate = false, fmask_expand = false;
5132
5133 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5134 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5135 fce_eliminate = true;
5136 }
5137
5138 if (radv_image_has_fmask(image)) {
5139 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5140 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5141 /* A FMASK decompress is required before doing
5142 * a MSAA decompress using FMASK.
5143 */
5144 fmask_expand = true;
5145 }
5146 }
5147
5148 if (fce_eliminate || fmask_expand)
5149 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5150
5151 if (fmask_expand)
5152 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5153 }
5154 }
5155
5156 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5157 struct radv_image *image,
5158 VkImageLayout src_layout,
5159 VkImageLayout dst_layout,
5160 uint32_t src_family,
5161 uint32_t dst_family,
5162 const VkImageSubresourceRange *range,
5163 struct radv_sample_locations_state *sample_locs)
5164 {
5165 if (image->exclusive && src_family != dst_family) {
5166 /* This is an acquire or a release operation and there will be
5167 * a corresponding release/acquire. Do the transition in the
5168 * most flexible queue. */
5169
5170 assert(src_family == cmd_buffer->queue_family_index ||
5171 dst_family == cmd_buffer->queue_family_index);
5172
5173 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5174 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5175 return;
5176
5177 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5178 return;
5179
5180 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5181 (src_family == RADV_QUEUE_GENERAL ||
5182 dst_family == RADV_QUEUE_GENERAL))
5183 return;
5184 }
5185
5186 if (src_layout == dst_layout)
5187 return;
5188
5189 unsigned src_queue_mask =
5190 radv_image_queue_family_mask(image, src_family,
5191 cmd_buffer->queue_family_index);
5192 unsigned dst_queue_mask =
5193 radv_image_queue_family_mask(image, dst_family,
5194 cmd_buffer->queue_family_index);
5195
5196 if (vk_format_is_depth(image->vk_format)) {
5197 radv_handle_depth_image_transition(cmd_buffer, image,
5198 src_layout, dst_layout,
5199 src_queue_mask, dst_queue_mask,
5200 range, sample_locs);
5201 } else {
5202 radv_handle_color_image_transition(cmd_buffer, image,
5203 src_layout, dst_layout,
5204 src_queue_mask, dst_queue_mask,
5205 range);
5206 }
5207 }
5208
5209 struct radv_barrier_info {
5210 uint32_t eventCount;
5211 const VkEvent *pEvents;
5212 VkPipelineStageFlags srcStageMask;
5213 VkPipelineStageFlags dstStageMask;
5214 };
5215
5216 static void
5217 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5218 uint32_t memoryBarrierCount,
5219 const VkMemoryBarrier *pMemoryBarriers,
5220 uint32_t bufferMemoryBarrierCount,
5221 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5222 uint32_t imageMemoryBarrierCount,
5223 const VkImageMemoryBarrier *pImageMemoryBarriers,
5224 const struct radv_barrier_info *info)
5225 {
5226 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5227 enum radv_cmd_flush_bits src_flush_bits = 0;
5228 enum radv_cmd_flush_bits dst_flush_bits = 0;
5229
5230 for (unsigned i = 0; i < info->eventCount; ++i) {
5231 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5232 uint64_t va = radv_buffer_get_va(event->bo);
5233
5234 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5235
5236 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5237
5238 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5239 assert(cmd_buffer->cs->cdw <= cdw_max);
5240 }
5241
5242 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5243 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5244 NULL);
5245 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5246 NULL);
5247 }
5248
5249 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5250 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5251 NULL);
5252 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5253 NULL);
5254 }
5255
5256 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5257 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5258
5259 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5260 image);
5261 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5262 image);
5263 }
5264
5265 /* The Vulkan spec 1.1.98 says:
5266 *
5267 * "An execution dependency with only
5268 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5269 * will only prevent that stage from executing in subsequently
5270 * submitted commands. As this stage does not perform any actual
5271 * execution, this is not observable - in effect, it does not delay
5272 * processing of subsequent commands. Similarly an execution dependency
5273 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5274 * will effectively not wait for any prior commands to complete."
5275 */
5276 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5277 radv_stage_flush(cmd_buffer, info->srcStageMask);
5278 cmd_buffer->state.flush_bits |= src_flush_bits;
5279
5280 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5281 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5282
5283 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5284 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5285 SAMPLE_LOCATIONS_INFO_EXT);
5286 struct radv_sample_locations_state sample_locations = {};
5287
5288 if (sample_locs_info) {
5289 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5290 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5291 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5292 sample_locations.count = sample_locs_info->sampleLocationsCount;
5293 typed_memcpy(&sample_locations.locations[0],
5294 sample_locs_info->pSampleLocations,
5295 sample_locs_info->sampleLocationsCount);
5296 }
5297
5298 radv_handle_image_transition(cmd_buffer, image,
5299 pImageMemoryBarriers[i].oldLayout,
5300 pImageMemoryBarriers[i].newLayout,
5301 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5302 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5303 &pImageMemoryBarriers[i].subresourceRange,
5304 sample_locs_info ? &sample_locations : NULL);
5305 }
5306
5307 /* Make sure CP DMA is idle because the driver might have performed a
5308 * DMA operation for copying or filling buffers/images.
5309 */
5310 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5311 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5312 si_cp_dma_wait_for_idle(cmd_buffer);
5313
5314 cmd_buffer->state.flush_bits |= dst_flush_bits;
5315 }
5316
5317 void radv_CmdPipelineBarrier(
5318 VkCommandBuffer commandBuffer,
5319 VkPipelineStageFlags srcStageMask,
5320 VkPipelineStageFlags destStageMask,
5321 VkBool32 byRegion,
5322 uint32_t memoryBarrierCount,
5323 const VkMemoryBarrier* pMemoryBarriers,
5324 uint32_t bufferMemoryBarrierCount,
5325 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5326 uint32_t imageMemoryBarrierCount,
5327 const VkImageMemoryBarrier* pImageMemoryBarriers)
5328 {
5329 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5330 struct radv_barrier_info info;
5331
5332 info.eventCount = 0;
5333 info.pEvents = NULL;
5334 info.srcStageMask = srcStageMask;
5335 info.dstStageMask = destStageMask;
5336
5337 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5338 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5339 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5340 }
5341
5342
5343 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5344 struct radv_event *event,
5345 VkPipelineStageFlags stageMask,
5346 unsigned value)
5347 {
5348 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5349 uint64_t va = radv_buffer_get_va(event->bo);
5350
5351 si_emit_cache_flush(cmd_buffer);
5352
5353 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5354
5355 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5356
5357 /* Flags that only require a top-of-pipe event. */
5358 VkPipelineStageFlags top_of_pipe_flags =
5359 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5360
5361 /* Flags that only require a post-index-fetch event. */
5362 VkPipelineStageFlags post_index_fetch_flags =
5363 top_of_pipe_flags |
5364 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5365 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5366
5367 /* Make sure CP DMA is idle because the driver might have performed a
5368 * DMA operation for copying or filling buffers/images.
5369 */
5370 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5371 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5372 si_cp_dma_wait_for_idle(cmd_buffer);
5373
5374 /* TODO: Emit EOS events for syncing PS/CS stages. */
5375
5376 if (!(stageMask & ~top_of_pipe_flags)) {
5377 /* Just need to sync the PFP engine. */
5378 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5379 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5380 S_370_WR_CONFIRM(1) |
5381 S_370_ENGINE_SEL(V_370_PFP));
5382 radeon_emit(cs, va);
5383 radeon_emit(cs, va >> 32);
5384 radeon_emit(cs, value);
5385 } else if (!(stageMask & ~post_index_fetch_flags)) {
5386 /* Sync ME because PFP reads index and indirect buffers. */
5387 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5388 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5389 S_370_WR_CONFIRM(1) |
5390 S_370_ENGINE_SEL(V_370_ME));
5391 radeon_emit(cs, va);
5392 radeon_emit(cs, va >> 32);
5393 radeon_emit(cs, value);
5394 } else {
5395 /* Otherwise, sync all prior GPU work using an EOP event. */
5396 si_cs_emit_write_event_eop(cs,
5397 cmd_buffer->device->physical_device->rad_info.chip_class,
5398 radv_cmd_buffer_uses_mec(cmd_buffer),
5399 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5400 EOP_DST_SEL_MEM,
5401 EOP_DATA_SEL_VALUE_32BIT, va, value,
5402 cmd_buffer->gfx9_eop_bug_va);
5403 }
5404
5405 assert(cmd_buffer->cs->cdw <= cdw_max);
5406 }
5407
5408 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5409 VkEvent _event,
5410 VkPipelineStageFlags stageMask)
5411 {
5412 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5413 RADV_FROM_HANDLE(radv_event, event, _event);
5414
5415 write_event(cmd_buffer, event, stageMask, 1);
5416 }
5417
5418 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5419 VkEvent _event,
5420 VkPipelineStageFlags stageMask)
5421 {
5422 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5423 RADV_FROM_HANDLE(radv_event, event, _event);
5424
5425 write_event(cmd_buffer, event, stageMask, 0);
5426 }
5427
5428 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5429 uint32_t eventCount,
5430 const VkEvent* pEvents,
5431 VkPipelineStageFlags srcStageMask,
5432 VkPipelineStageFlags dstStageMask,
5433 uint32_t memoryBarrierCount,
5434 const VkMemoryBarrier* pMemoryBarriers,
5435 uint32_t bufferMemoryBarrierCount,
5436 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5437 uint32_t imageMemoryBarrierCount,
5438 const VkImageMemoryBarrier* pImageMemoryBarriers)
5439 {
5440 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5441 struct radv_barrier_info info;
5442
5443 info.eventCount = eventCount;
5444 info.pEvents = pEvents;
5445 info.srcStageMask = 0;
5446
5447 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5448 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5449 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5450 }
5451
5452
5453 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5454 uint32_t deviceMask)
5455 {
5456 /* No-op */
5457 }
5458
5459 /* VK_EXT_conditional_rendering */
5460 void radv_CmdBeginConditionalRenderingEXT(
5461 VkCommandBuffer commandBuffer,
5462 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5463 {
5464 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5465 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5466 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5467 bool draw_visible = true;
5468 uint64_t pred_value = 0;
5469 uint64_t va, new_va;
5470 unsigned pred_offset;
5471
5472 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5473
5474 /* By default, if the 32-bit value at offset in buffer memory is zero,
5475 * then the rendering commands are discarded, otherwise they are
5476 * executed as normal. If the inverted flag is set, all commands are
5477 * discarded if the value is non zero.
5478 */
5479 if (pConditionalRenderingBegin->flags &
5480 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5481 draw_visible = false;
5482 }
5483
5484 si_emit_cache_flush(cmd_buffer);
5485
5486 /* From the Vulkan spec 1.1.107:
5487 *
5488 * "If the 32-bit value at offset in buffer memory is zero, then the
5489 * rendering commands are discarded, otherwise they are executed as
5490 * normal. If the value of the predicate in buffer memory changes while
5491 * conditional rendering is active, the rendering commands may be
5492 * discarded in an implementation-dependent way. Some implementations
5493 * may latch the value of the predicate upon beginning conditional
5494 * rendering while others may read it before every rendering command."
5495 *
5496 * But, the AMD hardware treats the predicate as a 64-bit value which
5497 * means we need a workaround in the driver. Luckily, it's not required
5498 * to support if the value changes when predication is active.
5499 *
5500 * The workaround is as follows:
5501 * 1) allocate a 64-value in the upload BO and initialize it to 0
5502 * 2) copy the 32-bit predicate value to the upload BO
5503 * 3) use the new allocated VA address for predication
5504 *
5505 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5506 * in ME (+ sync PFP) instead of PFP.
5507 */
5508 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5509
5510 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5511
5512 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5513 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5514 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5515 COPY_DATA_WR_CONFIRM);
5516 radeon_emit(cs, va);
5517 radeon_emit(cs, va >> 32);
5518 radeon_emit(cs, new_va);
5519 radeon_emit(cs, new_va >> 32);
5520
5521 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5522 radeon_emit(cs, 0);
5523
5524 /* Enable predication for this command buffer. */
5525 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5526 cmd_buffer->state.predicating = true;
5527
5528 /* Store conditional rendering user info. */
5529 cmd_buffer->state.predication_type = draw_visible;
5530 cmd_buffer->state.predication_va = new_va;
5531 }
5532
5533 void radv_CmdEndConditionalRenderingEXT(
5534 VkCommandBuffer commandBuffer)
5535 {
5536 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5537
5538 /* Disable predication for this command buffer. */
5539 si_emit_set_predication_state(cmd_buffer, false, 0);
5540 cmd_buffer->state.predicating = false;
5541
5542 /* Reset conditional rendering user info. */
5543 cmd_buffer->state.predication_type = -1;
5544 cmd_buffer->state.predication_va = 0;
5545 }
5546
5547 /* VK_EXT_transform_feedback */
5548 void radv_CmdBindTransformFeedbackBuffersEXT(
5549 VkCommandBuffer commandBuffer,
5550 uint32_t firstBinding,
5551 uint32_t bindingCount,
5552 const VkBuffer* pBuffers,
5553 const VkDeviceSize* pOffsets,
5554 const VkDeviceSize* pSizes)
5555 {
5556 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5557 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5558 uint8_t enabled_mask = 0;
5559
5560 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5561 for (uint32_t i = 0; i < bindingCount; i++) {
5562 uint32_t idx = firstBinding + i;
5563
5564 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5565 sb[idx].offset = pOffsets[i];
5566 sb[idx].size = pSizes[i];
5567
5568 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5569 sb[idx].buffer->bo);
5570
5571 enabled_mask |= 1 << idx;
5572 }
5573
5574 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5575
5576 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5577 }
5578
5579 static void
5580 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5581 {
5582 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5583 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5584
5585 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5586 radeon_emit(cs,
5587 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5588 S_028B94_RAST_STREAM(0) |
5589 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5590 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5591 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5592 radeon_emit(cs, so->hw_enabled_mask &
5593 so->enabled_stream_buffers_mask);
5594
5595 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5596 }
5597
5598 static void
5599 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5600 {
5601 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5602 bool old_streamout_enabled = so->streamout_enabled;
5603 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5604
5605 so->streamout_enabled = enable;
5606
5607 so->hw_enabled_mask = so->enabled_mask |
5608 (so->enabled_mask << 4) |
5609 (so->enabled_mask << 8) |
5610 (so->enabled_mask << 12);
5611
5612 if ((old_streamout_enabled != so->streamout_enabled) ||
5613 (old_hw_enabled_mask != so->hw_enabled_mask))
5614 radv_emit_streamout_enable(cmd_buffer);
5615 }
5616
5617 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5618 {
5619 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5620 unsigned reg_strmout_cntl;
5621
5622 /* The register is at different places on different ASICs. */
5623 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5624 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5625 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5626 } else {
5627 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5628 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5629 }
5630
5631 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5632 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5633
5634 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5635 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5636 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5637 radeon_emit(cs, 0);
5638 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5639 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5640 radeon_emit(cs, 4); /* poll interval */
5641 }
5642
5643 static void
5644 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5645 uint32_t firstCounterBuffer,
5646 uint32_t counterBufferCount,
5647 const VkBuffer *pCounterBuffers,
5648 const VkDeviceSize *pCounterBufferOffsets)
5649
5650 {
5651 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5652 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5653 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5654 uint32_t i;
5655
5656 radv_flush_vgt_streamout(cmd_buffer);
5657
5658 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5659 for_each_bit(i, so->enabled_mask) {
5660 int32_t counter_buffer_idx = i - firstCounterBuffer;
5661 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5662 counter_buffer_idx = -1;
5663
5664 /* AMD GCN binds streamout buffers as shader resources.
5665 * VGT only counts primitives and tells the shader through
5666 * SGPRs what to do.
5667 */
5668 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5669 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5670 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5671
5672 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5673
5674 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5675 /* The array of counter buffers is optional. */
5676 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5677 uint64_t va = radv_buffer_get_va(buffer->bo);
5678
5679 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5680
5681 /* Append */
5682 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5683 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5684 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5685 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5686 radeon_emit(cs, 0); /* unused */
5687 radeon_emit(cs, 0); /* unused */
5688 radeon_emit(cs, va); /* src address lo */
5689 radeon_emit(cs, va >> 32); /* src address hi */
5690
5691 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5692 } else {
5693 /* Start from the beginning. */
5694 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5695 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5696 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5697 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5698 radeon_emit(cs, 0); /* unused */
5699 radeon_emit(cs, 0); /* unused */
5700 radeon_emit(cs, 0); /* unused */
5701 radeon_emit(cs, 0); /* unused */
5702 }
5703 }
5704
5705 radv_set_streamout_enable(cmd_buffer, true);
5706 }
5707
5708 void radv_CmdBeginTransformFeedbackEXT(
5709 VkCommandBuffer commandBuffer,
5710 uint32_t firstCounterBuffer,
5711 uint32_t counterBufferCount,
5712 const VkBuffer* pCounterBuffers,
5713 const VkDeviceSize* pCounterBufferOffsets)
5714 {
5715 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5716
5717 radv_emit_streamout_begin(cmd_buffer,
5718 firstCounterBuffer, counterBufferCount,
5719 pCounterBuffers, pCounterBufferOffsets);
5720 }
5721
5722 static void
5723 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
5724 uint32_t firstCounterBuffer,
5725 uint32_t counterBufferCount,
5726 const VkBuffer *pCounterBuffers,
5727 const VkDeviceSize *pCounterBufferOffsets)
5728 {
5729 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5730 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5731 uint32_t i;
5732
5733 radv_flush_vgt_streamout(cmd_buffer);
5734
5735 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5736 for_each_bit(i, so->enabled_mask) {
5737 int32_t counter_buffer_idx = i - firstCounterBuffer;
5738 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5739 counter_buffer_idx = -1;
5740
5741 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5742 /* The array of counters buffer is optional. */
5743 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5744 uint64_t va = radv_buffer_get_va(buffer->bo);
5745
5746 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5747
5748 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5749 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5750 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5751 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5752 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5753 radeon_emit(cs, va); /* dst address lo */
5754 radeon_emit(cs, va >> 32); /* dst address hi */
5755 radeon_emit(cs, 0); /* unused */
5756 radeon_emit(cs, 0); /* unused */
5757
5758 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5759 }
5760
5761 /* Deactivate transform feedback by zeroing the buffer size.
5762 * The counters (primitives generated, primitives emitted) may
5763 * be enabled even if there is not buffer bound. This ensures
5764 * that the primitives-emitted query won't increment.
5765 */
5766 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5767
5768 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5769 }
5770
5771 radv_set_streamout_enable(cmd_buffer, false);
5772 }
5773
5774 void radv_CmdEndTransformFeedbackEXT(
5775 VkCommandBuffer commandBuffer,
5776 uint32_t firstCounterBuffer,
5777 uint32_t counterBufferCount,
5778 const VkBuffer* pCounterBuffers,
5779 const VkDeviceSize* pCounterBufferOffsets)
5780 {
5781 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5782
5783 radv_emit_streamout_end(cmd_buffer,
5784 firstCounterBuffer, counterBufferCount,
5785 pCounterBuffers, pCounterBufferOffsets);
5786 }
5787
5788 void radv_CmdDrawIndirectByteCountEXT(
5789 VkCommandBuffer commandBuffer,
5790 uint32_t instanceCount,
5791 uint32_t firstInstance,
5792 VkBuffer _counterBuffer,
5793 VkDeviceSize counterBufferOffset,
5794 uint32_t counterOffset,
5795 uint32_t vertexStride)
5796 {
5797 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5798 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5799 struct radv_draw_info info = {};
5800
5801 info.instance_count = instanceCount;
5802 info.first_instance = firstInstance;
5803 info.strmout_buffer = counterBuffer;
5804 info.strmout_buffer_offset = counterBufferOffset;
5805 info.stride = vertexStride;
5806
5807 radv_draw(cmd_buffer, &info);
5808 }
5809
5810 /* VK_AMD_buffer_marker */
5811 void radv_CmdWriteBufferMarkerAMD(
5812 VkCommandBuffer commandBuffer,
5813 VkPipelineStageFlagBits pipelineStage,
5814 VkBuffer dstBuffer,
5815 VkDeviceSize dstOffset,
5816 uint32_t marker)
5817 {
5818 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5819 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
5820 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5821 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
5822
5823 si_emit_cache_flush(cmd_buffer);
5824
5825 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
5826 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5827 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
5828 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5829 COPY_DATA_WR_CONFIRM);
5830 radeon_emit(cs, marker);
5831 radeon_emit(cs, 0);
5832 radeon_emit(cs, va);
5833 radeon_emit(cs, va >> 32);
5834 } else {
5835 si_cs_emit_write_event_eop(cs,
5836 cmd_buffer->device->physical_device->rad_info.chip_class,
5837 radv_cmd_buffer_uses_mec(cmd_buffer),
5838 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5839 EOP_DST_SEL_MEM,
5840 EOP_DATA_SEL_VALUE_32BIT,
5841 va, marker,
5842 cmd_buffer->gfx9_eop_bug_va);
5843 }
5844 }