2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
41 RADV_PREFETCH_VBO_DESCRIPTORS
= (1 << 0),
42 RADV_PREFETCH_VS
= (1 << 1),
43 RADV_PREFETCH_TCS
= (1 << 2),
44 RADV_PREFETCH_TES
= (1 << 3),
45 RADV_PREFETCH_GS
= (1 << 4),
46 RADV_PREFETCH_PS
= (1 << 5),
47 RADV_PREFETCH_SHADERS
= (RADV_PREFETCH_VS
|
54 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
55 struct radv_image
*image
,
56 VkImageLayout src_layout
,
57 VkImageLayout dst_layout
,
60 const VkImageSubresourceRange
*range
);
62 const struct radv_dynamic_state default_dynamic_state
= {
75 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
80 .stencil_compare_mask
= {
84 .stencil_write_mask
= {
88 .stencil_reference
= {
95 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
96 const struct radv_dynamic_state
*src
)
98 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
99 uint32_t copy_mask
= src
->mask
;
100 uint32_t dest_mask
= 0;
102 /* Make sure to copy the number of viewports/scissors because they can
103 * only be specified at pipeline creation time.
105 dest
->viewport
.count
= src
->viewport
.count
;
106 dest
->scissor
.count
= src
->scissor
.count
;
107 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
109 if (copy_mask
& RADV_DYNAMIC_VIEWPORT
) {
110 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
111 src
->viewport
.count
* sizeof(VkViewport
))) {
112 typed_memcpy(dest
->viewport
.viewports
,
113 src
->viewport
.viewports
,
114 src
->viewport
.count
);
115 dest_mask
|= RADV_DYNAMIC_VIEWPORT
;
119 if (copy_mask
& RADV_DYNAMIC_SCISSOR
) {
120 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
121 src
->scissor
.count
* sizeof(VkRect2D
))) {
122 typed_memcpy(dest
->scissor
.scissors
,
123 src
->scissor
.scissors
, src
->scissor
.count
);
124 dest_mask
|= RADV_DYNAMIC_SCISSOR
;
128 if (copy_mask
& RADV_DYNAMIC_LINE_WIDTH
) {
129 if (dest
->line_width
!= src
->line_width
) {
130 dest
->line_width
= src
->line_width
;
131 dest_mask
|= RADV_DYNAMIC_LINE_WIDTH
;
135 if (copy_mask
& RADV_DYNAMIC_DEPTH_BIAS
) {
136 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
137 sizeof(src
->depth_bias
))) {
138 dest
->depth_bias
= src
->depth_bias
;
139 dest_mask
|= RADV_DYNAMIC_DEPTH_BIAS
;
143 if (copy_mask
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
144 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
145 sizeof(src
->blend_constants
))) {
146 typed_memcpy(dest
->blend_constants
,
147 src
->blend_constants
, 4);
148 dest_mask
|= RADV_DYNAMIC_BLEND_CONSTANTS
;
152 if (copy_mask
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
153 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
154 sizeof(src
->depth_bounds
))) {
155 dest
->depth_bounds
= src
->depth_bounds
;
156 dest_mask
|= RADV_DYNAMIC_DEPTH_BOUNDS
;
160 if (copy_mask
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
161 if (memcmp(&dest
->stencil_compare_mask
,
162 &src
->stencil_compare_mask
,
163 sizeof(src
->stencil_compare_mask
))) {
164 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
165 dest_mask
|= RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
169 if (copy_mask
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
170 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
171 sizeof(src
->stencil_write_mask
))) {
172 dest
->stencil_write_mask
= src
->stencil_write_mask
;
173 dest_mask
|= RADV_DYNAMIC_STENCIL_WRITE_MASK
;
177 if (copy_mask
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
178 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
179 sizeof(src
->stencil_reference
))) {
180 dest
->stencil_reference
= src
->stencil_reference
;
181 dest_mask
|= RADV_DYNAMIC_STENCIL_REFERENCE
;
185 if (copy_mask
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
186 if (memcmp(&dest
->discard_rectangle
.rectangles
, &src
->discard_rectangle
.rectangles
,
187 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
188 typed_memcpy(dest
->discard_rectangle
.rectangles
,
189 src
->discard_rectangle
.rectangles
,
190 src
->discard_rectangle
.count
);
191 dest_mask
|= RADV_DYNAMIC_DISCARD_RECTANGLE
;
195 cmd_buffer
->state
.dirty
|= dest_mask
;
199 radv_bind_streamout_state(struct radv_cmd_buffer
*cmd_buffer
,
200 struct radv_pipeline
*pipeline
)
202 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
203 struct radv_shader_info
*info
;
205 if (!pipeline
->streamout_shader
)
208 info
= &pipeline
->streamout_shader
->info
.info
;
209 for (int i
= 0; i
< MAX_SO_BUFFERS
; i
++)
210 so
->stride_in_dw
[i
] = info
->so
.strides
[i
];
212 so
->enabled_stream_buffers_mask
= info
->so
.enabled_stream_buffers_mask
;
215 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
217 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
218 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
221 enum ring_type
radv_queue_family_to_ring(int f
) {
223 case RADV_QUEUE_GENERAL
:
225 case RADV_QUEUE_COMPUTE
:
227 case RADV_QUEUE_TRANSFER
:
230 unreachable("Unknown queue family");
234 static VkResult
radv_create_cmd_buffer(
235 struct radv_device
* device
,
236 struct radv_cmd_pool
* pool
,
237 VkCommandBufferLevel level
,
238 VkCommandBuffer
* pCommandBuffer
)
240 struct radv_cmd_buffer
*cmd_buffer
;
242 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
243 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
244 if (cmd_buffer
== NULL
)
245 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
247 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
248 cmd_buffer
->device
= device
;
249 cmd_buffer
->pool
= pool
;
250 cmd_buffer
->level
= level
;
253 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
254 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
257 /* Init the pool_link so we can safely call list_del when we destroy
260 list_inithead(&cmd_buffer
->pool_link
);
261 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
264 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
266 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
267 if (!cmd_buffer
->cs
) {
268 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
269 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
272 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
274 list_inithead(&cmd_buffer
->upload
.list
);
280 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
282 list_del(&cmd_buffer
->pool_link
);
284 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
285 &cmd_buffer
->upload
.list
, list
) {
286 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
291 if (cmd_buffer
->upload
.upload_bo
)
292 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
293 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
295 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
296 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
298 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
302 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
305 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
307 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
308 &cmd_buffer
->upload
.list
, list
) {
309 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
314 cmd_buffer
->push_constant_stages
= 0;
315 cmd_buffer
->scratch_size_needed
= 0;
316 cmd_buffer
->compute_scratch_size_needed
= 0;
317 cmd_buffer
->esgs_ring_size_needed
= 0;
318 cmd_buffer
->gsvs_ring_size_needed
= 0;
319 cmd_buffer
->tess_rings_needed
= false;
320 cmd_buffer
->sample_positions_needed
= false;
322 if (cmd_buffer
->upload
.upload_bo
)
323 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
324 cmd_buffer
->upload
.upload_bo
);
325 cmd_buffer
->upload
.offset
= 0;
327 cmd_buffer
->record_result
= VK_SUCCESS
;
329 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
330 cmd_buffer
->descriptors
[i
].dirty
= 0;
331 cmd_buffer
->descriptors
[i
].valid
= 0;
332 cmd_buffer
->descriptors
[i
].push_dirty
= false;
335 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
336 unsigned num_db
= cmd_buffer
->device
->physical_device
->rad_info
.num_render_backends
;
337 unsigned eop_bug_offset
;
340 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 0,
341 &cmd_buffer
->gfx9_fence_offset
,
343 cmd_buffer
->gfx9_fence_bo
= cmd_buffer
->upload
.upload_bo
;
345 /* Allocate a buffer for the EOP bug on GFX9. */
346 radv_cmd_buffer_upload_alloc(cmd_buffer
, 16 * num_db
, 0,
347 &eop_bug_offset
, &fence_ptr
);
348 cmd_buffer
->gfx9_eop_bug_va
=
349 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
350 cmd_buffer
->gfx9_eop_bug_va
+= eop_bug_offset
;
353 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_INITIAL
;
355 return cmd_buffer
->record_result
;
359 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
363 struct radeon_winsys_bo
*bo
;
364 struct radv_cmd_buffer_upload
*upload
;
365 struct radv_device
*device
= cmd_buffer
->device
;
367 new_size
= MAX2(min_needed
, 16 * 1024);
368 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
370 bo
= device
->ws
->buffer_create(device
->ws
,
373 RADEON_FLAG_CPU_ACCESS
|
374 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
378 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
382 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, bo
);
383 if (cmd_buffer
->upload
.upload_bo
) {
384 upload
= malloc(sizeof(*upload
));
387 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
388 device
->ws
->buffer_destroy(bo
);
392 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
393 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
396 cmd_buffer
->upload
.upload_bo
= bo
;
397 cmd_buffer
->upload
.size
= new_size
;
398 cmd_buffer
->upload
.offset
= 0;
399 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
401 if (!cmd_buffer
->upload
.map
) {
402 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
410 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
413 unsigned *out_offset
,
416 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
417 if (offset
+ size
> cmd_buffer
->upload
.size
) {
418 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
423 *out_offset
= offset
;
424 *ptr
= cmd_buffer
->upload
.map
+ offset
;
426 cmd_buffer
->upload
.offset
= offset
+ size
;
431 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
432 unsigned size
, unsigned alignment
,
433 const void *data
, unsigned *out_offset
)
437 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
438 out_offset
, (void **)&ptr
))
442 memcpy(ptr
, data
, size
);
448 radv_emit_write_data_packet(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
449 unsigned count
, const uint32_t *data
)
451 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
453 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4 + count
);
455 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
456 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
457 S_370_WR_CONFIRM(1) |
458 S_370_ENGINE_SEL(V_370_ME
));
460 radeon_emit(cs
, va
>> 32);
461 radeon_emit_array(cs
, data
, count
);
464 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
466 struct radv_device
*device
= cmd_buffer
->device
;
467 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
470 va
= radv_buffer_get_va(device
->trace_bo
);
471 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
474 ++cmd_buffer
->state
.trace_id
;
475 radv_emit_write_data_packet(cmd_buffer
, va
, 1,
476 &cmd_buffer
->state
.trace_id
);
478 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 2);
480 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
481 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
485 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
,
486 enum radv_cmd_flush_bits flags
)
488 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
489 uint32_t *ptr
= NULL
;
492 assert(flags
& (RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
493 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
));
495 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
496 va
= radv_buffer_get_va(cmd_buffer
->gfx9_fence_bo
) +
497 cmd_buffer
->gfx9_fence_offset
;
498 ptr
= &cmd_buffer
->gfx9_fence_idx
;
501 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 4);
503 /* Force wait for graphics or compute engines to be idle. */
504 si_cs_emit_cache_flush(cmd_buffer
->cs
,
505 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
507 radv_cmd_buffer_uses_mec(cmd_buffer
),
508 flags
, cmd_buffer
->gfx9_eop_bug_va
);
511 if (unlikely(cmd_buffer
->device
->trace_bo
))
512 radv_cmd_buffer_trace_emit(cmd_buffer
);
516 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
517 struct radv_pipeline
*pipeline
, enum ring_type ring
)
519 struct radv_device
*device
= cmd_buffer
->device
;
523 va
= radv_buffer_get_va(device
->trace_bo
);
533 assert(!"invalid ring type");
536 data
[0] = (uintptr_t)pipeline
;
537 data
[1] = (uintptr_t)pipeline
>> 32;
539 radv_emit_write_data_packet(cmd_buffer
, va
, 2, data
);
542 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
543 VkPipelineBindPoint bind_point
,
544 struct radv_descriptor_set
*set
,
547 struct radv_descriptor_state
*descriptors_state
=
548 radv_get_descriptors_state(cmd_buffer
, bind_point
);
550 descriptors_state
->sets
[idx
] = set
;
552 descriptors_state
->valid
|= (1u << idx
); /* active descriptors */
553 descriptors_state
->dirty
|= (1u << idx
);
557 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
558 VkPipelineBindPoint bind_point
)
560 struct radv_descriptor_state
*descriptors_state
=
561 radv_get_descriptors_state(cmd_buffer
, bind_point
);
562 struct radv_device
*device
= cmd_buffer
->device
;
563 uint32_t data
[MAX_SETS
* 2] = {};
566 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
568 for_each_bit(i
, descriptors_state
->valid
) {
569 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
570 data
[i
* 2] = (uintptr_t)set
;
571 data
[i
* 2 + 1] = (uintptr_t)set
>> 32;
574 radv_emit_write_data_packet(cmd_buffer
, va
, MAX_SETS
* 2, data
);
577 struct radv_userdata_info
*
578 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
579 gl_shader_stage stage
,
582 struct radv_shader_variant
*shader
= radv_get_shader(pipeline
, stage
);
583 return &shader
->info
.user_sgprs_locs
.shader_data
[idx
];
587 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
588 struct radv_pipeline
*pipeline
,
589 gl_shader_stage stage
,
590 int idx
, uint64_t va
)
592 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
593 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
594 if (loc
->sgpr_idx
== -1)
597 assert(loc
->num_sgprs
== 1);
598 assert(!loc
->indirect
);
600 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
601 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
605 radv_emit_descriptor_pointers(struct radv_cmd_buffer
*cmd_buffer
,
606 struct radv_pipeline
*pipeline
,
607 struct radv_descriptor_state
*descriptors_state
,
608 gl_shader_stage stage
)
610 struct radv_device
*device
= cmd_buffer
->device
;
611 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
612 uint32_t sh_base
= pipeline
->user_data_0
[stage
];
613 struct radv_userdata_locations
*locs
=
614 &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
;
615 unsigned mask
= locs
->descriptor_sets_enabled
;
617 mask
&= descriptors_state
->dirty
& descriptors_state
->valid
;
622 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
624 struct radv_userdata_info
*loc
= &locs
->descriptor_sets
[start
];
625 unsigned sh_offset
= sh_base
+ loc
->sgpr_idx
* 4;
627 radv_emit_shader_pointer_head(cs
, sh_offset
, count
, true);
628 for (int i
= 0; i
< count
; i
++) {
629 struct radv_descriptor_set
*set
=
630 descriptors_state
->sets
[start
+ i
];
632 radv_emit_shader_pointer_body(device
, cs
, set
->va
, true);
638 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
639 struct radv_pipeline
*pipeline
)
641 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
642 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
643 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
645 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
)
646 cmd_buffer
->sample_positions_needed
= true;
648 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
651 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
652 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
653 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
655 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
657 radv_cayman_emit_msaa_sample_locs(cmd_buffer
->cs
, num_samples
);
659 /* GFX9: Flush DFSM when the AA mode changes. */
660 if (cmd_buffer
->device
->dfsm_allowed
) {
661 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
662 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
667 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
668 struct radv_shader_variant
*shader
)
675 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
677 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
681 radv_emit_prefetch_L2(struct radv_cmd_buffer
*cmd_buffer
,
682 struct radv_pipeline
*pipeline
,
683 bool vertex_stage_only
)
685 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
686 uint32_t mask
= state
->prefetch_L2_mask
;
688 if (vertex_stage_only
) {
689 /* Fast prefetch path for starting draws as soon as possible.
691 mask
= state
->prefetch_L2_mask
& (RADV_PREFETCH_VS
|
692 RADV_PREFETCH_VBO_DESCRIPTORS
);
695 if (mask
& RADV_PREFETCH_VS
)
696 radv_emit_shader_prefetch(cmd_buffer
,
697 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
699 if (mask
& RADV_PREFETCH_VBO_DESCRIPTORS
)
700 si_cp_dma_prefetch(cmd_buffer
, state
->vb_va
, state
->vb_size
);
702 if (mask
& RADV_PREFETCH_TCS
)
703 radv_emit_shader_prefetch(cmd_buffer
,
704 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
706 if (mask
& RADV_PREFETCH_TES
)
707 radv_emit_shader_prefetch(cmd_buffer
,
708 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
710 if (mask
& RADV_PREFETCH_GS
) {
711 radv_emit_shader_prefetch(cmd_buffer
,
712 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
713 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
716 if (mask
& RADV_PREFETCH_PS
)
717 radv_emit_shader_prefetch(cmd_buffer
,
718 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
720 state
->prefetch_L2_mask
&= ~mask
;
724 radv_emit_rbplus_state(struct radv_cmd_buffer
*cmd_buffer
)
726 if (!cmd_buffer
->device
->physical_device
->rbplus_allowed
)
729 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
730 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
731 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
733 unsigned sx_ps_downconvert
= 0;
734 unsigned sx_blend_opt_epsilon
= 0;
735 unsigned sx_blend_opt_control
= 0;
737 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
738 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
739 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
740 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
744 int idx
= subpass
->color_attachments
[i
].attachment
;
745 struct radv_color_buffer_info
*cb
= &framebuffer
->attachments
[idx
].cb
;
747 unsigned format
= G_028C70_FORMAT(cb
->cb_color_info
);
748 unsigned swap
= G_028C70_COMP_SWAP(cb
->cb_color_info
);
749 uint32_t spi_format
= (pipeline
->graphics
.col_format
>> (i
* 4)) & 0xf;
750 uint32_t colormask
= (pipeline
->graphics
.cb_target_mask
>> (i
* 4)) & 0xf;
752 bool has_alpha
, has_rgb
;
754 /* Set if RGB and A are present. */
755 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(cb
->cb_color_attrib
);
757 if (format
== V_028C70_COLOR_8
||
758 format
== V_028C70_COLOR_16
||
759 format
== V_028C70_COLOR_32
)
760 has_rgb
= !has_alpha
;
764 /* Check the colormask and export format. */
765 if (!(colormask
& 0x7))
767 if (!(colormask
& 0x8))
770 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
775 /* Disable value checking for disabled channels. */
777 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
779 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
781 /* Enable down-conversion for 32bpp and smaller formats. */
783 case V_028C70_COLOR_8
:
784 case V_028C70_COLOR_8_8
:
785 case V_028C70_COLOR_8_8_8_8
:
786 /* For 1 and 2-channel formats, use the superset thereof. */
787 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
788 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
789 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
790 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
791 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
795 case V_028C70_COLOR_5_6_5
:
796 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
797 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
798 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
802 case V_028C70_COLOR_1_5_5_5
:
803 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
804 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
805 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
809 case V_028C70_COLOR_4_4_4_4
:
810 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
811 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
812 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
816 case V_028C70_COLOR_32
:
817 if (swap
== V_028C70_SWAP_STD
&&
818 spi_format
== V_028714_SPI_SHADER_32_R
)
819 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
820 else if (swap
== V_028C70_SWAP_ALT_REV
&&
821 spi_format
== V_028714_SPI_SHADER_32_AR
)
822 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
825 case V_028C70_COLOR_16
:
826 case V_028C70_COLOR_16_16
:
827 /* For 1-channel formats, use the superset thereof. */
828 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
829 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
830 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
831 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
832 if (swap
== V_028C70_SWAP_STD
||
833 swap
== V_028C70_SWAP_STD_REV
)
834 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
836 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
840 case V_028C70_COLOR_10_11_11
:
841 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
842 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
843 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
847 case V_028C70_COLOR_2_10_10_10
:
848 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
849 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
850 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
856 for (unsigned i
= subpass
->color_count
; i
< 8; ++i
) {
857 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
858 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
860 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
861 radeon_emit(cmd_buffer
->cs
, sx_ps_downconvert
);
862 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_epsilon
);
863 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_control
);
867 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
869 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
871 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
874 radv_update_multisample_state(cmd_buffer
, pipeline
);
876 cmd_buffer
->scratch_size_needed
=
877 MAX2(cmd_buffer
->scratch_size_needed
,
878 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
880 if (!cmd_buffer
->state
.emitted_pipeline
||
881 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
882 pipeline
->graphics
.can_use_guardband
)
883 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
885 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
887 for (unsigned i
= 0; i
< MESA_SHADER_COMPUTE
; i
++) {
888 if (!pipeline
->shaders
[i
])
891 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
892 pipeline
->shaders
[i
]->bo
);
895 if (radv_pipeline_has_gs(pipeline
))
896 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
897 pipeline
->gs_copy_shader
->bo
);
899 if (unlikely(cmd_buffer
->device
->trace_bo
))
900 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
902 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
904 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
908 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
910 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
911 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
915 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
917 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
919 si_write_scissors(cmd_buffer
->cs
, 0, count
,
920 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
921 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
922 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
926 radv_emit_discard_rectangle(struct radv_cmd_buffer
*cmd_buffer
)
928 if (!cmd_buffer
->state
.dynamic
.discard_rectangle
.count
)
931 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028210_PA_SC_CLIPRECT_0_TL
,
932 cmd_buffer
->state
.dynamic
.discard_rectangle
.count
* 2);
933 for (unsigned i
= 0; i
< cmd_buffer
->state
.dynamic
.discard_rectangle
.count
; ++i
) {
934 VkRect2D rect
= cmd_buffer
->state
.dynamic
.discard_rectangle
.rectangles
[i
];
935 radeon_emit(cmd_buffer
->cs
, S_028210_TL_X(rect
.offset
.x
) | S_028210_TL_Y(rect
.offset
.y
));
936 radeon_emit(cmd_buffer
->cs
, S_028214_BR_X(rect
.offset
.x
+ rect
.extent
.width
) |
937 S_028214_BR_Y(rect
.offset
.y
+ rect
.extent
.height
));
942 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
944 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
946 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
947 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
951 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
953 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
955 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
956 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
960 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
962 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
964 radeon_set_context_reg_seq(cmd_buffer
->cs
,
965 R_028430_DB_STENCILREFMASK
, 2);
966 radeon_emit(cmd_buffer
->cs
,
967 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
968 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
969 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
970 S_028430_STENCILOPVAL(1));
971 radeon_emit(cmd_buffer
->cs
,
972 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
973 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
974 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
975 S_028434_STENCILOPVAL_BF(1));
979 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
981 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
983 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
984 fui(d
->depth_bounds
.min
));
985 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
986 fui(d
->depth_bounds
.max
));
990 radv_emit_depth_bias(struct radv_cmd_buffer
*cmd_buffer
)
992 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
993 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
994 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
997 radeon_set_context_reg_seq(cmd_buffer
->cs
,
998 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
999 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1000 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1001 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1002 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1003 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1007 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1009 struct radv_attachment_info
*att
,
1010 struct radv_image
*image
,
1011 VkImageLayout layout
)
1013 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
1014 struct radv_color_buffer_info
*cb
= &att
->cb
;
1015 uint32_t cb_color_info
= cb
->cb_color_info
;
1017 if (!radv_layout_dcc_compressed(image
, layout
,
1018 radv_image_queue_family_mask(image
,
1019 cmd_buffer
->queue_family_index
,
1020 cmd_buffer
->queue_family_index
))) {
1021 cb_color_info
&= C_028C70_DCC_ENABLE
;
1024 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1025 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1026 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1027 radeon_emit(cmd_buffer
->cs
, S_028C64_BASE_256B(cb
->cb_color_base
>> 32));
1028 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1029 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1030 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1031 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1032 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1033 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1034 radeon_emit(cmd_buffer
->cs
, S_028C80_BASE_256B(cb
->cb_color_cmask
>> 32));
1035 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1036 radeon_emit(cmd_buffer
->cs
, S_028C88_BASE_256B(cb
->cb_color_fmask
>> 32));
1038 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1039 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1040 radeon_emit(cmd_buffer
->cs
, S_028C98_BASE_256B(cb
->cb_dcc_base
>> 32));
1042 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1043 S_0287A0_EPITCH(att
->attachment
->image
->surface
.u
.gfx9
.surf
.epitch
));
1045 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1046 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1047 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1048 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1049 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1050 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1051 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1052 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1053 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1054 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1055 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1056 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1058 if (is_vi
) { /* DCC BASE */
1059 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1063 if (radv_image_has_dcc(image
)) {
1064 /* Drawing with DCC enabled also compresses colorbuffers. */
1065 radv_update_dcc_metadata(cmd_buffer
, image
, true);
1070 radv_update_zrange_precision(struct radv_cmd_buffer
*cmd_buffer
,
1071 struct radv_ds_buffer_info
*ds
,
1072 struct radv_image
*image
, VkImageLayout layout
,
1073 bool requires_cond_exec
)
1075 uint32_t db_z_info
= ds
->db_z_info
;
1076 uint32_t db_z_info_reg
;
1078 if (!radv_image_is_tc_compat_htile(image
))
1081 if (!radv_layout_has_htile(image
, layout
,
1082 radv_image_queue_family_mask(image
,
1083 cmd_buffer
->queue_family_index
,
1084 cmd_buffer
->queue_family_index
))) {
1085 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1088 db_z_info
&= C_028040_ZRANGE_PRECISION
;
1090 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1091 db_z_info_reg
= R_028038_DB_Z_INFO
;
1093 db_z_info_reg
= R_028040_DB_Z_INFO
;
1096 /* When we don't know the last fast clear value we need to emit a
1097 * conditional packet that will eventually skip the following
1098 * SET_CONTEXT_REG packet.
1100 if (requires_cond_exec
) {
1101 uint64_t va
= radv_buffer_get_va(image
->bo
);
1102 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1104 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COND_EXEC
, 3, 0));
1105 radeon_emit(cmd_buffer
->cs
, va
);
1106 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1107 radeon_emit(cmd_buffer
->cs
, 0);
1108 radeon_emit(cmd_buffer
->cs
, 3); /* SET_CONTEXT_REG size */
1111 radeon_set_context_reg(cmd_buffer
->cs
, db_z_info_reg
, db_z_info
);
1115 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1116 struct radv_ds_buffer_info
*ds
,
1117 struct radv_image
*image
,
1118 VkImageLayout layout
)
1120 uint32_t db_z_info
= ds
->db_z_info
;
1121 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1123 if (!radv_layout_has_htile(image
, layout
,
1124 radv_image_queue_family_mask(image
,
1125 cmd_buffer
->queue_family_index
,
1126 cmd_buffer
->queue_family_index
))) {
1127 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1128 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1131 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1132 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1135 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1136 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1137 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1138 radeon_emit(cmd_buffer
->cs
, S_028018_BASE_HI(ds
->db_htile_data_base
>> 32));
1139 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1141 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1142 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1143 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1144 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1145 radeon_emit(cmd_buffer
->cs
, S_028044_BASE_HI(ds
->db_z_read_base
>> 32)); /* DB_Z_READ_BASE_HI */
1146 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1147 radeon_emit(cmd_buffer
->cs
, S_02804C_BASE_HI(ds
->db_stencil_read_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
1148 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1149 radeon_emit(cmd_buffer
->cs
, S_028054_BASE_HI(ds
->db_z_write_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
1150 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1151 radeon_emit(cmd_buffer
->cs
, S_02805C_BASE_HI(ds
->db_stencil_write_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1153 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1154 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1155 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1157 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1159 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1160 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1161 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1162 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1163 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1164 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1165 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1166 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1167 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1168 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1172 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1173 radv_update_zrange_precision(cmd_buffer
, ds
, image
, layout
, true);
1175 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1176 ds
->pa_su_poly_offset_db_fmt_cntl
);
1180 * Update the fast clear depth/stencil values if the image is bound as a
1181 * depth/stencil buffer.
1184 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer
*cmd_buffer
,
1185 struct radv_image
*image
,
1186 VkClearDepthStencilValue ds_clear_value
,
1187 VkImageAspectFlags aspects
)
1189 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1190 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1191 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1192 struct radv_attachment_info
*att
;
1195 if (!framebuffer
|| !subpass
)
1198 att_idx
= subpass
->depth_stencil_attachment
.attachment
;
1199 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1202 att
= &framebuffer
->attachments
[att_idx
];
1203 if (att
->attachment
->image
!= image
)
1206 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
1207 radeon_emit(cs
, ds_clear_value
.stencil
);
1208 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1210 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1211 * only needed when clearing Z to 0.0.
1213 if ((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1214 ds_clear_value
.depth
== 0.0) {
1215 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1217 radv_update_zrange_precision(cmd_buffer
, &att
->ds
, image
,
1223 * Set the clear depth/stencil values to the image's metadata.
1226 radv_set_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1227 struct radv_image
*image
,
1228 VkClearDepthStencilValue ds_clear_value
,
1229 VkImageAspectFlags aspects
)
1231 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1232 uint64_t va
= radv_buffer_get_va(image
->bo
);
1233 unsigned reg_offset
= 0, reg_count
= 0;
1235 va
+= image
->offset
+ image
->clear_value_offset
;
1237 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1243 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1246 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, 0));
1247 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1248 S_370_WR_CONFIRM(1) |
1249 S_370_ENGINE_SEL(V_370_PFP
));
1250 radeon_emit(cs
, va
);
1251 radeon_emit(cs
, va
>> 32);
1252 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1253 radeon_emit(cs
, ds_clear_value
.stencil
);
1254 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1255 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1259 * Update the TC-compat metadata value for this image.
1262 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1263 struct radv_image
*image
,
1266 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1267 uint64_t va
= radv_buffer_get_va(image
->bo
);
1268 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1270 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
1271 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1272 S_370_WR_CONFIRM(1) |
1273 S_370_ENGINE_SEL(V_370_PFP
));
1274 radeon_emit(cs
, va
);
1275 radeon_emit(cs
, va
>> 32);
1276 radeon_emit(cs
, value
);
1280 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1281 struct radv_image
*image
,
1282 VkClearDepthStencilValue ds_clear_value
)
1284 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1285 uint64_t va
= radv_buffer_get_va(image
->bo
);
1286 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1289 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1290 * depth clear value is 0.0f.
1292 cond_val
= ds_clear_value
.depth
== 0.0f
? UINT_MAX
: 0;
1294 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, cond_val
);
1298 * Update the clear depth/stencil values for this image.
1301 radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1302 struct radv_image
*image
,
1303 VkClearDepthStencilValue ds_clear_value
,
1304 VkImageAspectFlags aspects
)
1306 assert(radv_image_has_htile(image
));
1308 radv_set_ds_clear_metadata(cmd_buffer
, image
, ds_clear_value
, aspects
);
1310 if (radv_image_is_tc_compat_htile(image
) &&
1311 (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
1312 radv_update_tc_compat_zrange_metadata(cmd_buffer
, image
,
1316 radv_update_bound_fast_clear_ds(cmd_buffer
, image
, ds_clear_value
,
1321 * Load the clear depth/stencil values from the image's metadata.
1324 radv_load_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1325 struct radv_image
*image
)
1327 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1328 VkImageAspectFlags aspects
= vk_format_aspects(image
->vk_format
);
1329 uint64_t va
= radv_buffer_get_va(image
->bo
);
1330 unsigned reg_offset
= 0, reg_count
= 0;
1332 va
+= image
->offset
+ image
->clear_value_offset
;
1334 if (!radv_image_has_htile(image
))
1337 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1343 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1346 uint32_t reg
= R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
;
1348 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
) {
1349 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, 0));
1350 radeon_emit(cs
, va
);
1351 radeon_emit(cs
, va
>> 32);
1352 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1353 radeon_emit(cs
, reg_count
);
1355 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1356 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1357 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1358 (reg_count
== 2 ? COPY_DATA_COUNT_SEL
: 0));
1359 radeon_emit(cs
, va
);
1360 radeon_emit(cs
, va
>> 32);
1361 radeon_emit(cs
, reg
>> 2);
1364 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1370 * With DCC some colors don't require CMASK elimination before being
1371 * used as a texture. This sets a predicate value to determine if the
1372 * cmask eliminate is required.
1375 radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1376 struct radv_image
*image
, bool value
)
1378 uint64_t pred_val
= value
;
1379 uint64_t va
= radv_buffer_get_va(image
->bo
);
1380 va
+= image
->offset
+ image
->fce_pred_offset
;
1382 assert(radv_image_has_dcc(image
));
1384 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1385 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1386 S_370_WR_CONFIRM(1) |
1387 S_370_ENGINE_SEL(V_370_PFP
));
1388 radeon_emit(cmd_buffer
->cs
, va
);
1389 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1390 radeon_emit(cmd_buffer
->cs
, pred_val
);
1391 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1395 * Update the DCC predicate to reflect the compression state.
1398 radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1399 struct radv_image
*image
, bool value
)
1401 uint64_t pred_val
= value
;
1402 uint64_t va
= radv_buffer_get_va(image
->bo
);
1403 va
+= image
->offset
+ image
->dcc_pred_offset
;
1405 assert(radv_image_has_dcc(image
));
1407 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1408 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1409 S_370_WR_CONFIRM(1) |
1410 S_370_ENGINE_SEL(V_370_PFP
));
1411 radeon_emit(cmd_buffer
->cs
, va
);
1412 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1413 radeon_emit(cmd_buffer
->cs
, pred_val
);
1414 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1418 * Update the fast clear color values if the image is bound as a color buffer.
1421 radv_update_bound_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1422 struct radv_image
*image
,
1424 uint32_t color_values
[2])
1426 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1427 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1428 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1429 struct radv_attachment_info
*att
;
1432 if (!framebuffer
|| !subpass
)
1435 att_idx
= subpass
->color_attachments
[cb_idx
].attachment
;
1436 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1439 att
= &framebuffer
->attachments
[att_idx
];
1440 if (att
->attachment
->image
!= image
)
1443 radeon_set_context_reg_seq(cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c, 2);
1444 radeon_emit(cs
, color_values
[0]);
1445 radeon_emit(cs
, color_values
[1]);
1449 * Set the clear color values to the image's metadata.
1452 radv_set_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1453 struct radv_image
*image
,
1454 uint32_t color_values
[2])
1456 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1457 uint64_t va
= radv_buffer_get_va(image
->bo
);
1459 va
+= image
->offset
+ image
->clear_value_offset
;
1461 assert(radv_image_has_cmask(image
) || radv_image_has_dcc(image
));
1463 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1464 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1465 S_370_WR_CONFIRM(1) |
1466 S_370_ENGINE_SEL(V_370_PFP
));
1467 radeon_emit(cs
, va
);
1468 radeon_emit(cs
, va
>> 32);
1469 radeon_emit(cs
, color_values
[0]);
1470 radeon_emit(cs
, color_values
[1]);
1474 * Update the clear color values for this image.
1477 radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1478 struct radv_image
*image
,
1480 uint32_t color_values
[2])
1482 assert(radv_image_has_cmask(image
) || radv_image_has_dcc(image
));
1484 radv_set_color_clear_metadata(cmd_buffer
, image
, color_values
);
1486 radv_update_bound_fast_clear_color(cmd_buffer
, image
, cb_idx
,
1491 * Load the clear color values from the image's metadata.
1494 radv_load_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1495 struct radv_image
*image
,
1498 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1499 uint64_t va
= radv_buffer_get_va(image
->bo
);
1501 va
+= image
->offset
+ image
->clear_value_offset
;
1503 if (!radv_image_has_cmask(image
) && !radv_image_has_dcc(image
))
1506 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c;
1508 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
) {
1509 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, cmd_buffer
->state
.predicating
));
1510 radeon_emit(cs
, va
);
1511 radeon_emit(cs
, va
>> 32);
1512 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1515 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
1516 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1517 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1518 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1519 COPY_DATA_COUNT_SEL
);
1520 radeon_emit(cs
, va
);
1521 radeon_emit(cs
, va
>> 32);
1522 radeon_emit(cs
, reg
>> 2);
1525 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1531 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1534 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1535 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1536 unsigned num_bpp64_colorbufs
= 0;
1538 /* this may happen for inherited secondary recording */
1542 for (i
= 0; i
< 8; ++i
) {
1543 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1544 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1545 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1549 int idx
= subpass
->color_attachments
[i
].attachment
;
1550 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1551 struct radv_image
*image
= att
->attachment
->image
;
1552 VkImageLayout layout
= subpass
->color_attachments
[i
].layout
;
1554 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
);
1556 assert(att
->attachment
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
);
1557 radv_emit_fb_color_state(cmd_buffer
, i
, att
, image
, layout
);
1559 radv_load_color_clear_metadata(cmd_buffer
, image
, i
);
1561 if (image
->surface
.bpe
>= 8)
1562 num_bpp64_colorbufs
++;
1565 if(subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1566 int idx
= subpass
->depth_stencil_attachment
.attachment
;
1567 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1568 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1569 struct radv_image
*image
= att
->attachment
->image
;
1570 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
);
1571 MAYBE_UNUSED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1572 cmd_buffer
->queue_family_index
,
1573 cmd_buffer
->queue_family_index
);
1574 /* We currently don't support writing decompressed HTILE */
1575 assert(radv_layout_has_htile(image
, layout
, queue_mask
) ==
1576 radv_layout_is_htile_compressed(image
, layout
, queue_mask
));
1578 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
1580 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1581 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1582 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
1584 radv_load_ds_clear_metadata(cmd_buffer
, image
);
1586 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1587 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
1589 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1591 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
1592 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
1594 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1595 S_028208_BR_X(framebuffer
->width
) |
1596 S_028208_BR_Y(framebuffer
->height
));
1598 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
) {
1599 uint8_t watermark
= 4; /* Default value for VI. */
1601 /* For optimal DCC performance. */
1602 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1603 if (num_bpp64_colorbufs
>= 5) {
1610 radeon_set_context_reg(cmd_buffer
->cs
, R_028424_CB_DCC_CONTROL
,
1611 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1612 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
));
1615 if (cmd_buffer
->device
->dfsm_allowed
) {
1616 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1617 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1620 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
1624 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
)
1626 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1627 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1629 if (state
->index_type
!= state
->last_index_type
) {
1630 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1631 radeon_set_uconfig_reg_idx(cs
, R_03090C_VGT_INDEX_TYPE
,
1632 2, state
->index_type
);
1634 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
1635 radeon_emit(cs
, state
->index_type
);
1638 state
->last_index_type
= state
->index_type
;
1641 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
1642 radeon_emit(cs
, state
->index_va
);
1643 radeon_emit(cs
, state
->index_va
>> 32);
1645 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
1646 radeon_emit(cs
, state
->max_index_count
);
1648 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
1651 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
1653 bool has_perfect_queries
= cmd_buffer
->state
.perfect_occlusion_queries_enabled
;
1654 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1655 uint32_t pa_sc_mode_cntl_1
=
1656 pipeline
? pipeline
->graphics
.ms
.pa_sc_mode_cntl_1
: 0;
1657 uint32_t db_count_control
;
1659 if(!cmd_buffer
->state
.active_occlusion_queries
) {
1660 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1661 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
1662 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
1663 has_perfect_queries
) {
1664 /* Re-enable out-of-order rasterization if the
1665 * bound pipeline supports it and if it's has
1666 * been disabled before starting any perfect
1667 * occlusion queries.
1669 radeon_set_context_reg(cmd_buffer
->cs
,
1670 R_028A4C_PA_SC_MODE_CNTL_1
,
1674 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1676 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1677 uint32_t sample_rate
= subpass
? util_logbase2(subpass
->max_sample_count
) : 0;
1679 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1681 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries
) |
1682 S_028004_SAMPLE_RATE(sample_rate
) |
1683 S_028004_ZPASS_ENABLE(1) |
1684 S_028004_SLICE_EVEN_ENABLE(1) |
1685 S_028004_SLICE_ODD_ENABLE(1);
1687 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
1688 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
1689 has_perfect_queries
) {
1690 /* If the bound pipeline has enabled
1691 * out-of-order rasterization, we should
1692 * disable it before starting any perfect
1693 * occlusion queries.
1695 pa_sc_mode_cntl_1
&= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE
;
1697 radeon_set_context_reg(cmd_buffer
->cs
,
1698 R_028A4C_PA_SC_MODE_CNTL_1
,
1702 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1703 S_028004_SAMPLE_RATE(sample_rate
);
1707 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
1711 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
1713 uint32_t states
= cmd_buffer
->state
.dirty
& cmd_buffer
->state
.emitted_pipeline
->graphics
.needed_dynamic_state
;
1715 if (states
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1716 radv_emit_viewport(cmd_buffer
);
1718 if (states
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
1719 !cmd_buffer
->device
->physical_device
->has_scissor_bug
)
1720 radv_emit_scissor(cmd_buffer
);
1722 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
1723 radv_emit_line_width(cmd_buffer
);
1725 if (states
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1726 radv_emit_blend_constants(cmd_buffer
);
1728 if (states
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
1729 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
1730 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
1731 radv_emit_stencil(cmd_buffer
);
1733 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
1734 radv_emit_depth_bounds(cmd_buffer
);
1736 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)
1737 radv_emit_depth_bias(cmd_buffer
);
1739 if (states
& RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
)
1740 radv_emit_discard_rectangle(cmd_buffer
);
1742 cmd_buffer
->state
.dirty
&= ~states
;
1746 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1747 VkPipelineBindPoint bind_point
)
1749 struct radv_descriptor_state
*descriptors_state
=
1750 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1751 struct radv_descriptor_set
*set
= &descriptors_state
->push_set
.set
;
1754 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
1759 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1760 set
->va
+= bo_offset
;
1764 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
,
1765 VkPipelineBindPoint bind_point
)
1767 struct radv_descriptor_state
*descriptors_state
=
1768 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1769 uint32_t size
= MAX_SETS
* 4;
1773 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
1774 256, &offset
, &ptr
))
1777 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
1778 uint32_t *uptr
= ((uint32_t *)ptr
) + i
;
1779 uint64_t set_va
= 0;
1780 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
1781 if (descriptors_state
->valid
& (1u << i
))
1783 uptr
[0] = set_va
& 0xffffffff;
1786 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1789 if (cmd_buffer
->state
.pipeline
) {
1790 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
1791 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1792 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1794 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
1795 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
1796 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1798 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
1799 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
1800 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1802 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1803 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
1804 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1806 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1807 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
1808 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1811 if (cmd_buffer
->state
.compute_pipeline
)
1812 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
1813 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1817 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1818 VkShaderStageFlags stages
)
1820 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
1821 VK_PIPELINE_BIND_POINT_COMPUTE
:
1822 VK_PIPELINE_BIND_POINT_GRAPHICS
;
1823 struct radv_descriptor_state
*descriptors_state
=
1824 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1825 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1826 bool flush_indirect_descriptors
;
1828 if (!descriptors_state
->dirty
)
1831 if (descriptors_state
->push_dirty
)
1832 radv_flush_push_descriptors(cmd_buffer
, bind_point
);
1834 flush_indirect_descriptors
=
1835 (bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
&&
1836 state
->pipeline
&& state
->pipeline
->need_indirect_descriptor_sets
) ||
1837 (bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
&&
1838 state
->compute_pipeline
&& state
->compute_pipeline
->need_indirect_descriptor_sets
);
1840 if (flush_indirect_descriptors
)
1841 radv_flush_indirect_descriptor_sets(cmd_buffer
, bind_point
);
1843 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1845 MAX_SETS
* MESA_SHADER_STAGES
* 4);
1847 if (cmd_buffer
->state
.pipeline
) {
1848 radv_foreach_stage(stage
, stages
) {
1849 if (!cmd_buffer
->state
.pipeline
->shaders
[stage
])
1852 radv_emit_descriptor_pointers(cmd_buffer
,
1853 cmd_buffer
->state
.pipeline
,
1854 descriptors_state
, stage
);
1858 if (cmd_buffer
->state
.compute_pipeline
&&
1859 (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)) {
1860 radv_emit_descriptor_pointers(cmd_buffer
,
1861 cmd_buffer
->state
.compute_pipeline
,
1863 MESA_SHADER_COMPUTE
);
1866 descriptors_state
->dirty
= 0;
1867 descriptors_state
->push_dirty
= false;
1869 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1871 if (unlikely(cmd_buffer
->device
->trace_bo
))
1872 radv_save_descriptors(cmd_buffer
, bind_point
);
1876 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
1877 VkShaderStageFlags stages
)
1879 struct radv_pipeline
*pipeline
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
1880 ? cmd_buffer
->state
.compute_pipeline
1881 : cmd_buffer
->state
.pipeline
;
1882 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
1883 VK_PIPELINE_BIND_POINT_COMPUTE
:
1884 VK_PIPELINE_BIND_POINT_GRAPHICS
;
1885 struct radv_descriptor_state
*descriptors_state
=
1886 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1887 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
1888 struct radv_shader_variant
*shader
, *prev_shader
;
1893 stages
&= cmd_buffer
->push_constant_stages
;
1895 (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
1898 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
1899 16 * layout
->dynamic_offset_count
,
1900 256, &offset
, &ptr
))
1903 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
1904 memcpy((char*)ptr
+ layout
->push_constant_size
,
1905 descriptors_state
->dynamic_buffers
,
1906 16 * layout
->dynamic_offset_count
);
1908 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1911 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1912 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
1915 radv_foreach_stage(stage
, stages
) {
1916 shader
= radv_get_shader(pipeline
, stage
);
1918 /* Avoid redundantly emitting the address for merged stages. */
1919 if (shader
&& shader
!= prev_shader
) {
1920 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
1921 AC_UD_PUSH_CONSTANTS
, va
);
1923 prev_shader
= shader
;
1927 cmd_buffer
->push_constant_stages
&= ~stages
;
1928 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1932 radv_flush_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1933 bool pipeline_is_dirty
)
1935 if ((pipeline_is_dirty
||
1936 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_VERTEX_BUFFER
)) &&
1937 cmd_buffer
->state
.pipeline
->vertex_elements
.count
&&
1938 radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.has_vertex_buffers
) {
1939 struct radv_vertex_elements_info
*velems
= &cmd_buffer
->state
.pipeline
->vertex_elements
;
1943 uint32_t count
= velems
->count
;
1946 /* allocate some descriptor state for vertex buffers */
1947 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
1948 &vb_offset
, &vb_ptr
))
1951 for (i
= 0; i
< count
; i
++) {
1952 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
1954 int vb
= velems
->binding
[i
];
1955 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[vb
].buffer
;
1956 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[vb
];
1958 va
= radv_buffer_get_va(buffer
->bo
);
1960 offset
= cmd_buffer
->vertex_bindings
[vb
].offset
+ velems
->offset
[i
];
1961 va
+= offset
+ buffer
->offset
;
1963 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
1964 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= CIK
&& stride
)
1965 desc
[2] = (buffer
->size
- offset
- velems
->format_size
[i
]) / stride
+ 1;
1967 desc
[2] = buffer
->size
- offset
;
1968 desc
[3] = velems
->rsrc_word3
[i
];
1971 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1974 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1975 AC_UD_VS_VERTEX_BUFFERS
, va
);
1977 cmd_buffer
->state
.vb_va
= va
;
1978 cmd_buffer
->state
.vb_size
= count
* 16;
1979 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_VBO_DESCRIPTORS
;
1981 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_VERTEX_BUFFER
;
1985 radv_emit_streamout_buffers(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
)
1987 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1988 struct radv_userdata_info
*loc
;
1991 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
1992 if (!radv_get_shader(pipeline
, stage
))
1995 loc
= radv_lookup_user_sgpr(pipeline
, stage
,
1996 AC_UD_STREAMOUT_BUFFERS
);
1997 if (loc
->sgpr_idx
== -1)
2000 base_reg
= pipeline
->user_data_0
[stage
];
2002 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2003 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2006 if (pipeline
->gs_copy_shader
) {
2007 loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_STREAMOUT_BUFFERS
];
2008 if (loc
->sgpr_idx
!= -1) {
2009 base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2011 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2012 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2018 radv_flush_streamout_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
2020 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_STREAMOUT_BUFFER
) {
2021 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
2022 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
2027 /* Allocate some descriptor state for streamout buffers. */
2028 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
,
2029 MAX_SO_BUFFERS
* 16, 256,
2030 &so_offset
, &so_ptr
))
2033 for (uint32_t i
= 0; i
< MAX_SO_BUFFERS
; i
++) {
2034 struct radv_buffer
*buffer
= sb
[i
].buffer
;
2035 uint32_t *desc
= &((uint32_t *)so_ptr
)[i
* 4];
2037 if (!(so
->enabled_mask
& (1 << i
)))
2040 va
= radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
2044 /* Set the descriptor.
2046 * On VI, the format must be non-INVALID, otherwise
2047 * the buffer will be considered not bound and store
2048 * instructions will be no-ops.
2051 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2052 desc
[2] = 0xffffffff;
2053 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2054 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2055 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2056 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2057 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2060 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2063 radv_emit_streamout_buffers(cmd_buffer
, va
);
2066 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
2070 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
2072 radv_flush_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
);
2073 radv_flush_streamout_descriptors(cmd_buffer
);
2074 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2075 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2079 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
, bool indexed_draw
,
2080 bool instanced_draw
, bool indirect_draw
,
2081 uint32_t draw_vertex_count
)
2083 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2084 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2085 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2086 uint32_t ia_multi_vgt_param
;
2087 int32_t primitive_reset_en
;
2090 ia_multi_vgt_param
=
2091 si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
,
2092 indirect_draw
, draw_vertex_count
);
2094 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
2095 if (info
->chip_class
>= GFX9
) {
2096 radeon_set_uconfig_reg_idx(cs
,
2097 R_030960_IA_MULTI_VGT_PARAM
,
2098 4, ia_multi_vgt_param
);
2099 } else if (info
->chip_class
>= CIK
) {
2100 radeon_set_context_reg_idx(cs
,
2101 R_028AA8_IA_MULTI_VGT_PARAM
,
2102 1, ia_multi_vgt_param
);
2104 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
2105 ia_multi_vgt_param
);
2107 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
2110 /* Primitive restart. */
2111 primitive_reset_en
=
2112 indexed_draw
&& state
->pipeline
->graphics
.prim_restart_enable
;
2114 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
2115 state
->last_primitive_reset_en
= primitive_reset_en
;
2116 if (info
->chip_class
>= GFX9
) {
2117 radeon_set_uconfig_reg(cs
,
2118 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
2119 primitive_reset_en
);
2121 radeon_set_context_reg(cs
,
2122 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
2123 primitive_reset_en
);
2127 if (primitive_reset_en
) {
2128 uint32_t primitive_reset_index
=
2129 state
->index_type
? 0xffffffffu
: 0xffffu
;
2131 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
2132 radeon_set_context_reg(cs
,
2133 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
2134 primitive_reset_index
);
2135 state
->last_primitive_reset_index
= primitive_reset_index
;
2140 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
2141 VkPipelineStageFlags src_stage_mask
)
2143 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
2144 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2145 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2146 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2147 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
2150 if (src_stage_mask
& (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
2151 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
2152 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
2153 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
2154 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2155 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2156 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
2157 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2158 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
2159 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
2160 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
2161 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
|
2162 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
2163 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
2164 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
2165 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT
)) {
2166 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
2170 static enum radv_cmd_flush_bits
2171 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2172 VkAccessFlags src_flags
,
2173 struct radv_image
*image
)
2175 bool flush_CB_meta
= true, flush_DB_meta
= true;
2176 enum radv_cmd_flush_bits flush_bits
= 0;
2180 if (!radv_image_has_CB_metadata(image
))
2181 flush_CB_meta
= false;
2182 if (!radv_image_has_htile(image
))
2183 flush_DB_meta
= false;
2186 for_each_bit(b
, src_flags
) {
2187 switch ((VkAccessFlagBits
)(1 << b
)) {
2188 case VK_ACCESS_SHADER_WRITE_BIT
:
2189 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
:
2190 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2191 flush_bits
|= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2193 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2194 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2196 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2198 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2199 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2201 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2203 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2204 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2205 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2206 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2209 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2211 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2220 static enum radv_cmd_flush_bits
2221 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2222 VkAccessFlags dst_flags
,
2223 struct radv_image
*image
)
2225 bool flush_CB_meta
= true, flush_DB_meta
= true;
2226 enum radv_cmd_flush_bits flush_bits
= 0;
2227 bool flush_CB
= true, flush_DB
= true;
2228 bool image_is_coherent
= false;
2232 if (!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)) {
2237 if (!radv_image_has_CB_metadata(image
))
2238 flush_CB_meta
= false;
2239 if (!radv_image_has_htile(image
))
2240 flush_DB_meta
= false;
2242 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2243 if (image
->info
.samples
== 1 &&
2244 (image
->usage
& (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
2245 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) &&
2246 !vk_format_is_stencil(image
->vk_format
)) {
2247 /* Single-sample color and single-sample depth
2248 * (not stencil) are coherent with shaders on
2251 image_is_coherent
= true;
2256 for_each_bit(b
, dst_flags
) {
2257 switch ((VkAccessFlagBits
)(1 << b
)) {
2258 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2259 case VK_ACCESS_INDEX_READ_BIT
:
2260 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2262 case VK_ACCESS_UNIFORM_READ_BIT
:
2263 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
| RADV_CMD_FLAG_INV_SMEM_L1
;
2265 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2266 case VK_ACCESS_TRANSFER_READ_BIT
:
2267 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2268 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
|
2269 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2271 case VK_ACCESS_SHADER_READ_BIT
:
2272 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
;
2274 if (!image_is_coherent
)
2275 flush_bits
|= RADV_CMD_FLAG_INV_GLOBAL_L2
;
2277 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
2279 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2281 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2283 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
2285 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2287 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2296 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2297 const struct radv_subpass_barrier
*barrier
)
2299 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
,
2301 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
2302 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
2306 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2307 struct radv_subpass_attachment att
)
2309 unsigned idx
= att
.attachment
;
2310 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
2311 VkImageSubresourceRange range
;
2312 range
.aspectMask
= 0;
2313 range
.baseMipLevel
= view
->base_mip
;
2314 range
.levelCount
= 1;
2315 range
.baseArrayLayer
= view
->base_layer
;
2316 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
2318 if (cmd_buffer
->state
.subpass
&& cmd_buffer
->state
.subpass
->view_mask
) {
2319 /* If the current subpass uses multiview, the driver might have
2320 * performed a fast color/depth clear to the whole image
2321 * (including all layers). To make sure the driver will
2322 * decompress the image correctly (if needed), we have to
2323 * account for the "real" number of layers. If the view mask is
2324 * sparse, this will decompress more layers than needed.
2326 range
.layerCount
= util_last_bit(cmd_buffer
->state
.subpass
->view_mask
);
2329 radv_handle_image_transition(cmd_buffer
,
2331 cmd_buffer
->state
.attachments
[idx
].current_layout
,
2332 att
.layout
, 0, 0, &range
);
2334 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
2340 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
2341 const struct radv_subpass
*subpass
, bool transitions
)
2344 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
2346 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
2347 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
2348 radv_handle_subpass_image_transition(cmd_buffer
,
2349 subpass
->color_attachments
[i
]);
2352 for (unsigned i
= 0; i
< subpass
->input_count
; ++i
) {
2353 radv_handle_subpass_image_transition(cmd_buffer
,
2354 subpass
->input_attachments
[i
]);
2357 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
2358 radv_handle_subpass_image_transition(cmd_buffer
,
2359 subpass
->depth_stencil_attachment
);
2363 cmd_buffer
->state
.subpass
= subpass
;
2365 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
2369 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
2370 struct radv_render_pass
*pass
,
2371 const VkRenderPassBeginInfo
*info
)
2373 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2375 if (pass
->attachment_count
== 0) {
2376 state
->attachments
= NULL
;
2380 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
2381 pass
->attachment_count
*
2382 sizeof(state
->attachments
[0]),
2383 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2384 if (state
->attachments
== NULL
) {
2385 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2386 return cmd_buffer
->record_result
;
2389 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
2390 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
2391 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
2392 VkImageAspectFlags clear_aspects
= 0;
2394 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
2395 /* color attachment */
2396 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2397 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
2400 /* depthstencil attachment */
2401 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
2402 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2403 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
2404 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2405 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
2406 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2408 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2409 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2410 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2414 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
2415 state
->attachments
[i
].cleared_views
= 0;
2416 if (clear_aspects
&& info
) {
2417 assert(info
->clearValueCount
> i
);
2418 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
2421 state
->attachments
[i
].current_layout
= att
->initial_layout
;
2427 VkResult
radv_AllocateCommandBuffers(
2429 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
2430 VkCommandBuffer
*pCommandBuffers
)
2432 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2433 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
2435 VkResult result
= VK_SUCCESS
;
2438 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
2440 if (!list_empty(&pool
->free_cmd_buffers
)) {
2441 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
2443 list_del(&cmd_buffer
->pool_link
);
2444 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
2446 result
= radv_reset_cmd_buffer(cmd_buffer
);
2447 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2448 cmd_buffer
->level
= pAllocateInfo
->level
;
2450 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
2452 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
2453 &pCommandBuffers
[i
]);
2455 if (result
!= VK_SUCCESS
)
2459 if (result
!= VK_SUCCESS
) {
2460 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
2461 i
, pCommandBuffers
);
2463 /* From the Vulkan 1.0.66 spec:
2465 * "vkAllocateCommandBuffers can be used to create multiple
2466 * command buffers. If the creation of any of those command
2467 * buffers fails, the implementation must destroy all
2468 * successfully created command buffer objects from this
2469 * command, set all entries of the pCommandBuffers array to
2470 * NULL and return the error."
2472 memset(pCommandBuffers
, 0,
2473 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
2479 void radv_FreeCommandBuffers(
2481 VkCommandPool commandPool
,
2482 uint32_t commandBufferCount
,
2483 const VkCommandBuffer
*pCommandBuffers
)
2485 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2486 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
2489 if (cmd_buffer
->pool
) {
2490 list_del(&cmd_buffer
->pool_link
);
2491 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
2493 radv_cmd_buffer_destroy(cmd_buffer
);
2499 VkResult
radv_ResetCommandBuffer(
2500 VkCommandBuffer commandBuffer
,
2501 VkCommandBufferResetFlags flags
)
2503 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2504 return radv_reset_cmd_buffer(cmd_buffer
);
2507 VkResult
radv_BeginCommandBuffer(
2508 VkCommandBuffer commandBuffer
,
2509 const VkCommandBufferBeginInfo
*pBeginInfo
)
2511 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2512 VkResult result
= VK_SUCCESS
;
2514 if (cmd_buffer
->status
!= RADV_CMD_BUFFER_STATUS_INITIAL
) {
2515 /* If the command buffer has already been resetted with
2516 * vkResetCommandBuffer, no need to do it again.
2518 result
= radv_reset_cmd_buffer(cmd_buffer
);
2519 if (result
!= VK_SUCCESS
)
2523 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
2524 cmd_buffer
->state
.last_primitive_reset_en
= -1;
2525 cmd_buffer
->state
.last_index_type
= -1;
2526 cmd_buffer
->state
.last_num_instances
= -1;
2527 cmd_buffer
->state
.last_vertex_offset
= -1;
2528 cmd_buffer
->state
.last_first_instance
= -1;
2529 cmd_buffer
->state
.predication_type
= -1;
2530 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
2532 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
2533 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
2534 assert(pBeginInfo
->pInheritanceInfo
);
2535 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
2536 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
2538 struct radv_subpass
*subpass
=
2539 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
2541 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
2542 if (result
!= VK_SUCCESS
)
2545 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
2548 if (unlikely(cmd_buffer
->device
->trace_bo
)) {
2549 struct radv_device
*device
= cmd_buffer
->device
;
2551 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
,
2554 radv_cmd_buffer_trace_emit(cmd_buffer
);
2557 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_RECORDING
;
2562 void radv_CmdBindVertexBuffers(
2563 VkCommandBuffer commandBuffer
,
2564 uint32_t firstBinding
,
2565 uint32_t bindingCount
,
2566 const VkBuffer
* pBuffers
,
2567 const VkDeviceSize
* pOffsets
)
2569 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2570 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
2571 bool changed
= false;
2573 /* We have to defer setting up vertex buffer since we need the buffer
2574 * stride from the pipeline. */
2576 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
2577 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
2578 uint32_t idx
= firstBinding
+ i
;
2581 (vb
[idx
].buffer
!= radv_buffer_from_handle(pBuffers
[i
]) ||
2582 vb
[idx
].offset
!= pOffsets
[i
])) {
2586 vb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
2587 vb
[idx
].offset
= pOffsets
[i
];
2589 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2590 vb
[idx
].buffer
->bo
);
2594 /* No state changes. */
2598 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_VERTEX_BUFFER
;
2601 void radv_CmdBindIndexBuffer(
2602 VkCommandBuffer commandBuffer
,
2604 VkDeviceSize offset
,
2605 VkIndexType indexType
)
2607 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2608 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
2610 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
2611 cmd_buffer
->state
.index_offset
== offset
&&
2612 cmd_buffer
->state
.index_type
== indexType
) {
2613 /* No state changes. */
2617 cmd_buffer
->state
.index_buffer
= index_buffer
;
2618 cmd_buffer
->state
.index_offset
= offset
;
2619 cmd_buffer
->state
.index_type
= indexType
; /* vk matches hw */
2620 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
2621 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
2623 int index_size_shift
= cmd_buffer
->state
.index_type
? 2 : 1;
2624 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) >> index_size_shift
;
2625 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
2626 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, index_buffer
->bo
);
2631 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2632 VkPipelineBindPoint bind_point
,
2633 struct radv_descriptor_set
*set
, unsigned idx
)
2635 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2637 radv_set_descriptor_set(cmd_buffer
, bind_point
, set
, idx
);
2640 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
2642 if (!cmd_buffer
->device
->use_global_bo_list
) {
2643 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
2644 if (set
->descriptors
[j
])
2645 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->descriptors
[j
]);
2649 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->bo
);
2652 void radv_CmdBindDescriptorSets(
2653 VkCommandBuffer commandBuffer
,
2654 VkPipelineBindPoint pipelineBindPoint
,
2655 VkPipelineLayout _layout
,
2657 uint32_t descriptorSetCount
,
2658 const VkDescriptorSet
* pDescriptorSets
,
2659 uint32_t dynamicOffsetCount
,
2660 const uint32_t* pDynamicOffsets
)
2662 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2663 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2664 unsigned dyn_idx
= 0;
2666 const bool no_dynamic_bounds
= cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
2667 struct radv_descriptor_state
*descriptors_state
=
2668 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
2670 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
2671 unsigned idx
= i
+ firstSet
;
2672 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
2673 radv_bind_descriptor_set(cmd_buffer
, pipelineBindPoint
, set
, idx
);
2675 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
2676 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
2677 uint32_t *dst
= descriptors_state
->dynamic_buffers
+ idx
* 4;
2678 assert(dyn_idx
< dynamicOffsetCount
);
2680 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
2681 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
2683 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2684 dst
[2] = no_dynamic_bounds
? 0xffffffffu
: range
->size
;
2685 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2686 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2687 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2688 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2689 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2690 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2691 cmd_buffer
->push_constant_stages
|=
2692 set
->layout
->dynamic_shader_stages
;
2697 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2698 struct radv_descriptor_set
*set
,
2699 struct radv_descriptor_set_layout
*layout
,
2700 VkPipelineBindPoint bind_point
)
2702 struct radv_descriptor_state
*descriptors_state
=
2703 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2704 set
->size
= layout
->size
;
2705 set
->layout
= layout
;
2707 if (descriptors_state
->push_set
.capacity
< set
->size
) {
2708 size_t new_size
= MAX2(set
->size
, 1024);
2709 new_size
= MAX2(new_size
, 2 * descriptors_state
->push_set
.capacity
);
2710 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
2712 free(set
->mapped_ptr
);
2713 set
->mapped_ptr
= malloc(new_size
);
2715 if (!set
->mapped_ptr
) {
2716 descriptors_state
->push_set
.capacity
= 0;
2717 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2721 descriptors_state
->push_set
.capacity
= new_size
;
2727 void radv_meta_push_descriptor_set(
2728 struct radv_cmd_buffer
* cmd_buffer
,
2729 VkPipelineBindPoint pipelineBindPoint
,
2730 VkPipelineLayout _layout
,
2732 uint32_t descriptorWriteCount
,
2733 const VkWriteDescriptorSet
* pDescriptorWrites
)
2735 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2736 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
2740 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2742 push_set
->size
= layout
->set
[set
].layout
->size
;
2743 push_set
->layout
= layout
->set
[set
].layout
;
2745 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
2747 (void**) &push_set
->mapped_ptr
))
2750 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2751 push_set
->va
+= bo_offset
;
2753 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2754 radv_descriptor_set_to_handle(push_set
),
2755 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2757 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
2760 void radv_CmdPushDescriptorSetKHR(
2761 VkCommandBuffer commandBuffer
,
2762 VkPipelineBindPoint pipelineBindPoint
,
2763 VkPipelineLayout _layout
,
2765 uint32_t descriptorWriteCount
,
2766 const VkWriteDescriptorSet
* pDescriptorWrites
)
2768 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2769 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2770 struct radv_descriptor_state
*descriptors_state
=
2771 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
2772 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
2774 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2776 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
2777 layout
->set
[set
].layout
,
2781 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2782 radv_descriptor_set_to_handle(push_set
),
2783 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2785 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
2786 descriptors_state
->push_dirty
= true;
2789 void radv_CmdPushDescriptorSetWithTemplateKHR(
2790 VkCommandBuffer commandBuffer
,
2791 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
2792 VkPipelineLayout _layout
,
2796 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2797 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2798 RADV_FROM_HANDLE(radv_descriptor_update_template
, templ
, descriptorUpdateTemplate
);
2799 struct radv_descriptor_state
*descriptors_state
=
2800 radv_get_descriptors_state(cmd_buffer
, templ
->bind_point
);
2801 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
2803 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2805 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
2806 layout
->set
[set
].layout
,
2810 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
2811 descriptorUpdateTemplate
, pData
);
2813 radv_set_descriptor_set(cmd_buffer
, templ
->bind_point
, push_set
, set
);
2814 descriptors_state
->push_dirty
= true;
2817 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
2818 VkPipelineLayout layout
,
2819 VkShaderStageFlags stageFlags
,
2822 const void* pValues
)
2824 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2825 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
2826 cmd_buffer
->push_constant_stages
|= stageFlags
;
2829 VkResult
radv_EndCommandBuffer(
2830 VkCommandBuffer commandBuffer
)
2832 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2834 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
2835 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== SI
)
2836 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2837 si_emit_cache_flush(cmd_buffer
);
2840 /* Make sure CP DMA is idle at the end of IBs because the kernel
2841 * doesn't wait for it.
2843 si_cp_dma_wait_for_idle(cmd_buffer
);
2845 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
2847 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
2848 return vk_error(cmd_buffer
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2850 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_EXECUTABLE
;
2852 return cmd_buffer
->record_result
;
2856 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
2858 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2860 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
2863 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
2865 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, pipeline
->cs
.cdw
);
2866 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
2868 cmd_buffer
->compute_scratch_size_needed
=
2869 MAX2(cmd_buffer
->compute_scratch_size_needed
,
2870 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
2872 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2873 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->bo
);
2875 if (unlikely(cmd_buffer
->device
->trace_bo
))
2876 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
2879 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
,
2880 VkPipelineBindPoint bind_point
)
2882 struct radv_descriptor_state
*descriptors_state
=
2883 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2885 descriptors_state
->dirty
|= descriptors_state
->valid
;
2888 void radv_CmdBindPipeline(
2889 VkCommandBuffer commandBuffer
,
2890 VkPipelineBindPoint pipelineBindPoint
,
2891 VkPipeline _pipeline
)
2893 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2894 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
2896 switch (pipelineBindPoint
) {
2897 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2898 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
2900 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
2902 cmd_buffer
->state
.compute_pipeline
= pipeline
;
2903 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
2905 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2906 if (cmd_buffer
->state
.pipeline
== pipeline
)
2908 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
2910 cmd_buffer
->state
.pipeline
= pipeline
;
2914 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
2915 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
2917 /* the new vertex shader might not have the same user regs */
2918 cmd_buffer
->state
.last_first_instance
= -1;
2919 cmd_buffer
->state
.last_vertex_offset
= -1;
2921 /* Prefetch all pipeline shaders at first draw time. */
2922 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_SHADERS
;
2924 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
2925 radv_bind_streamout_state(cmd_buffer
, pipeline
);
2927 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
2928 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
2929 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
2930 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
2932 if (radv_pipeline_has_tess(pipeline
))
2933 cmd_buffer
->tess_rings_needed
= true;
2936 assert(!"invalid bind point");
2941 void radv_CmdSetViewport(
2942 VkCommandBuffer commandBuffer
,
2943 uint32_t firstViewport
,
2944 uint32_t viewportCount
,
2945 const VkViewport
* pViewports
)
2947 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2948 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2949 MAYBE_UNUSED
const uint32_t total_count
= firstViewport
+ viewportCount
;
2951 assert(firstViewport
< MAX_VIEWPORTS
);
2952 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
2954 memcpy(state
->dynamic
.viewport
.viewports
+ firstViewport
, pViewports
,
2955 viewportCount
* sizeof(*pViewports
));
2957 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2960 void radv_CmdSetScissor(
2961 VkCommandBuffer commandBuffer
,
2962 uint32_t firstScissor
,
2963 uint32_t scissorCount
,
2964 const VkRect2D
* pScissors
)
2966 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2967 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2968 MAYBE_UNUSED
const uint32_t total_count
= firstScissor
+ scissorCount
;
2970 assert(firstScissor
< MAX_SCISSORS
);
2971 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
2973 memcpy(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
2974 scissorCount
* sizeof(*pScissors
));
2976 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2979 void radv_CmdSetLineWidth(
2980 VkCommandBuffer commandBuffer
,
2983 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2984 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
2985 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2988 void radv_CmdSetDepthBias(
2989 VkCommandBuffer commandBuffer
,
2990 float depthBiasConstantFactor
,
2991 float depthBiasClamp
,
2992 float depthBiasSlopeFactor
)
2994 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2996 cmd_buffer
->state
.dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
2997 cmd_buffer
->state
.dynamic
.depth_bias
.clamp
= depthBiasClamp
;
2998 cmd_buffer
->state
.dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
3000 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
3003 void radv_CmdSetBlendConstants(
3004 VkCommandBuffer commandBuffer
,
3005 const float blendConstants
[4])
3007 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3009 memcpy(cmd_buffer
->state
.dynamic
.blend_constants
,
3010 blendConstants
, sizeof(float) * 4);
3012 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
3015 void radv_CmdSetDepthBounds(
3016 VkCommandBuffer commandBuffer
,
3017 float minDepthBounds
,
3018 float maxDepthBounds
)
3020 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3022 cmd_buffer
->state
.dynamic
.depth_bounds
.min
= minDepthBounds
;
3023 cmd_buffer
->state
.dynamic
.depth_bounds
.max
= maxDepthBounds
;
3025 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
3028 void radv_CmdSetStencilCompareMask(
3029 VkCommandBuffer commandBuffer
,
3030 VkStencilFaceFlags faceMask
,
3031 uint32_t compareMask
)
3033 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3035 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3036 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
3037 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3038 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
3040 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
3043 void radv_CmdSetStencilWriteMask(
3044 VkCommandBuffer commandBuffer
,
3045 VkStencilFaceFlags faceMask
,
3048 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3050 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3051 cmd_buffer
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
3052 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3053 cmd_buffer
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
3055 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
3058 void radv_CmdSetStencilReference(
3059 VkCommandBuffer commandBuffer
,
3060 VkStencilFaceFlags faceMask
,
3063 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3065 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3066 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
3067 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3068 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
3070 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
3073 void radv_CmdSetDiscardRectangleEXT(
3074 VkCommandBuffer commandBuffer
,
3075 uint32_t firstDiscardRectangle
,
3076 uint32_t discardRectangleCount
,
3077 const VkRect2D
* pDiscardRectangles
)
3079 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3080 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3081 MAYBE_UNUSED
const uint32_t total_count
= firstDiscardRectangle
+ discardRectangleCount
;
3083 assert(firstDiscardRectangle
< MAX_DISCARD_RECTANGLES
);
3084 assert(total_count
>= 1 && total_count
<= MAX_DISCARD_RECTANGLES
);
3086 typed_memcpy(&state
->dynamic
.discard_rectangle
.rectangles
[firstDiscardRectangle
],
3087 pDiscardRectangles
, discardRectangleCount
);
3089 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
;
3092 void radv_CmdExecuteCommands(
3093 VkCommandBuffer commandBuffer
,
3094 uint32_t commandBufferCount
,
3095 const VkCommandBuffer
* pCmdBuffers
)
3097 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
3099 assert(commandBufferCount
> 0);
3101 /* Emit pending flushes on primary prior to executing secondary */
3102 si_emit_cache_flush(primary
);
3104 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3105 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
3107 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
3108 secondary
->scratch_size_needed
);
3109 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
3110 secondary
->compute_scratch_size_needed
);
3112 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
3113 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
3114 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
3115 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
3116 if (secondary
->tess_rings_needed
)
3117 primary
->tess_rings_needed
= true;
3118 if (secondary
->sample_positions_needed
)
3119 primary
->sample_positions_needed
= true;
3121 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
3124 /* When the secondary command buffer is compute only we don't
3125 * need to re-emit the current graphics pipeline.
3127 if (secondary
->state
.emitted_pipeline
) {
3128 primary
->state
.emitted_pipeline
=
3129 secondary
->state
.emitted_pipeline
;
3132 /* When the secondary command buffer is graphics only we don't
3133 * need to re-emit the current compute pipeline.
3135 if (secondary
->state
.emitted_compute_pipeline
) {
3136 primary
->state
.emitted_compute_pipeline
=
3137 secondary
->state
.emitted_compute_pipeline
;
3140 /* Only re-emit the draw packets when needed. */
3141 if (secondary
->state
.last_primitive_reset_en
!= -1) {
3142 primary
->state
.last_primitive_reset_en
=
3143 secondary
->state
.last_primitive_reset_en
;
3146 if (secondary
->state
.last_primitive_reset_index
) {
3147 primary
->state
.last_primitive_reset_index
=
3148 secondary
->state
.last_primitive_reset_index
;
3151 if (secondary
->state
.last_ia_multi_vgt_param
) {
3152 primary
->state
.last_ia_multi_vgt_param
=
3153 secondary
->state
.last_ia_multi_vgt_param
;
3156 primary
->state
.last_first_instance
= secondary
->state
.last_first_instance
;
3157 primary
->state
.last_num_instances
= secondary
->state
.last_num_instances
;
3158 primary
->state
.last_vertex_offset
= secondary
->state
.last_vertex_offset
;
3160 if (secondary
->state
.last_index_type
!= -1) {
3161 primary
->state
.last_index_type
=
3162 secondary
->state
.last_index_type
;
3166 /* After executing commands from secondary buffers we have to dirty
3169 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
3170 RADV_CMD_DIRTY_INDEX_BUFFER
|
3171 RADV_CMD_DIRTY_DYNAMIC_ALL
;
3172 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_GRAPHICS
);
3173 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_COMPUTE
);
3176 VkResult
radv_CreateCommandPool(
3178 const VkCommandPoolCreateInfo
* pCreateInfo
,
3179 const VkAllocationCallbacks
* pAllocator
,
3180 VkCommandPool
* pCmdPool
)
3182 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3183 struct radv_cmd_pool
*pool
;
3185 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
3186 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3188 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3191 pool
->alloc
= *pAllocator
;
3193 pool
->alloc
= device
->alloc
;
3195 list_inithead(&pool
->cmd_buffers
);
3196 list_inithead(&pool
->free_cmd_buffers
);
3198 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
3200 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
3206 void radv_DestroyCommandPool(
3208 VkCommandPool commandPool
,
3209 const VkAllocationCallbacks
* pAllocator
)
3211 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3212 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3217 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3218 &pool
->cmd_buffers
, pool_link
) {
3219 radv_cmd_buffer_destroy(cmd_buffer
);
3222 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3223 &pool
->free_cmd_buffers
, pool_link
) {
3224 radv_cmd_buffer_destroy(cmd_buffer
);
3227 vk_free2(&device
->alloc
, pAllocator
, pool
);
3230 VkResult
radv_ResetCommandPool(
3232 VkCommandPool commandPool
,
3233 VkCommandPoolResetFlags flags
)
3235 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3238 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
3239 &pool
->cmd_buffers
, pool_link
) {
3240 result
= radv_reset_cmd_buffer(cmd_buffer
);
3241 if (result
!= VK_SUCCESS
)
3248 void radv_TrimCommandPool(
3250 VkCommandPool commandPool
,
3251 VkCommandPoolTrimFlagsKHR flags
)
3253 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3258 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3259 &pool
->free_cmd_buffers
, pool_link
) {
3260 radv_cmd_buffer_destroy(cmd_buffer
);
3264 void radv_CmdBeginRenderPass(
3265 VkCommandBuffer commandBuffer
,
3266 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3267 VkSubpassContents contents
)
3269 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3270 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3271 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3273 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
3274 cmd_buffer
->cs
, 2048);
3275 MAYBE_UNUSED VkResult result
;
3277 cmd_buffer
->state
.framebuffer
= framebuffer
;
3278 cmd_buffer
->state
.pass
= pass
;
3279 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3281 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
3282 if (result
!= VK_SUCCESS
)
3285 radv_cmd_buffer_set_subpass(cmd_buffer
, pass
->subpasses
, true);
3286 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3288 radv_cmd_buffer_clear_subpass(cmd_buffer
);
3291 void radv_CmdBeginRenderPass2KHR(
3292 VkCommandBuffer commandBuffer
,
3293 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
3294 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
3296 radv_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
3297 pSubpassBeginInfo
->contents
);
3300 void radv_CmdNextSubpass(
3301 VkCommandBuffer commandBuffer
,
3302 VkSubpassContents contents
)
3304 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3306 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3308 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3311 radv_cmd_buffer_set_subpass(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1, true);
3312 radv_cmd_buffer_clear_subpass(cmd_buffer
);
3315 void radv_CmdNextSubpass2KHR(
3316 VkCommandBuffer commandBuffer
,
3317 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
3318 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
3320 radv_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
3323 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
3325 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
3326 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
3327 if (!radv_get_shader(pipeline
, stage
))
3330 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
3331 if (loc
->sgpr_idx
== -1)
3333 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
3334 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3337 if (pipeline
->gs_copy_shader
) {
3338 struct radv_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
3339 if (loc
->sgpr_idx
!= -1) {
3340 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3341 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3347 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3348 uint32_t vertex_count
,
3351 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
3352 radeon_emit(cmd_buffer
->cs
, vertex_count
);
3353 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
3354 S_0287F0_USE_OPAQUE(use_opaque
));
3358 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
3360 uint32_t index_count
)
3362 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, cmd_buffer
->state
.predicating
));
3363 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
3364 radeon_emit(cmd_buffer
->cs
, index_va
);
3365 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
3366 radeon_emit(cmd_buffer
->cs
, index_count
);
3367 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
3371 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3373 uint32_t draw_count
,
3377 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3378 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
3379 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
3380 bool draw_id_enable
= radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.needs_draw_id
;
3381 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
3382 bool predicating
= cmd_buffer
->state
.predicating
;
3385 /* just reset draw state for vertex data */
3386 cmd_buffer
->state
.last_first_instance
= -1;
3387 cmd_buffer
->state
.last_num_instances
= -1;
3388 cmd_buffer
->state
.last_vertex_offset
= -1;
3390 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
3391 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
3392 PKT3_DRAW_INDIRECT
, 3, predicating
));
3394 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3395 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3396 radeon_emit(cs
, di_src_sel
);
3398 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
3399 PKT3_DRAW_INDIRECT_MULTI
,
3402 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3403 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3404 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
3405 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
3406 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
3407 radeon_emit(cs
, draw_count
); /* count */
3408 radeon_emit(cs
, count_va
); /* count_addr */
3409 radeon_emit(cs
, count_va
>> 32);
3410 radeon_emit(cs
, stride
); /* stride */
3411 radeon_emit(cs
, di_src_sel
);
3415 struct radv_draw_info
{
3417 * Number of vertices.
3422 * Index of the first vertex.
3424 int32_t vertex_offset
;
3427 * First instance id.
3429 uint32_t first_instance
;
3432 * Number of instances.
3434 uint32_t instance_count
;
3437 * First index (indexed draws only).
3439 uint32_t first_index
;
3442 * Whether it's an indexed draw.
3447 * Indirect draw parameters resource.
3449 struct radv_buffer
*indirect
;
3450 uint64_t indirect_offset
;
3454 * Draw count parameters resource.
3456 struct radv_buffer
*count_buffer
;
3457 uint64_t count_buffer_offset
;
3460 * Stream output parameters resource.
3462 struct radv_buffer
*strmout_buffer
;
3463 uint64_t strmout_buffer_offset
;
3467 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
3468 const struct radv_draw_info
*info
)
3470 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3471 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3472 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3474 if (info
->strmout_buffer
) {
3475 uint64_t va
= radv_buffer_get_va(info
->strmout_buffer
->bo
);
3477 va
+= info
->strmout_buffer
->offset
+
3478 info
->strmout_buffer_offset
;
3480 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
3483 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
3484 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
3485 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
3486 COPY_DATA_WR_CONFIRM
);
3487 radeon_emit(cs
, va
);
3488 radeon_emit(cs
, va
>> 32);
3489 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
3490 radeon_emit(cs
, 0); /* unused */
3492 radv_cs_add_buffer(ws
, cs
, info
->strmout_buffer
->bo
);
3495 if (info
->indirect
) {
3496 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3497 uint64_t count_va
= 0;
3499 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3501 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
3503 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
3505 radeon_emit(cs
, va
);
3506 radeon_emit(cs
, va
>> 32);
3508 if (info
->count_buffer
) {
3509 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
3510 count_va
+= info
->count_buffer
->offset
+
3511 info
->count_buffer_offset
;
3513 radv_cs_add_buffer(ws
, cs
, info
->count_buffer
->bo
);
3516 if (!state
->subpass
->view_mask
) {
3517 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3524 for_each_bit(i
, state
->subpass
->view_mask
) {
3525 radv_emit_view_index(cmd_buffer
, i
);
3527 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3535 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
3537 if (info
->vertex_offset
!= state
->last_vertex_offset
||
3538 info
->first_instance
!= state
->last_first_instance
) {
3539 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
3540 state
->pipeline
->graphics
.vtx_emit_num
);
3542 radeon_emit(cs
, info
->vertex_offset
);
3543 radeon_emit(cs
, info
->first_instance
);
3544 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
3546 state
->last_first_instance
= info
->first_instance
;
3547 state
->last_vertex_offset
= info
->vertex_offset
;
3550 if (state
->last_num_instances
!= info
->instance_count
) {
3551 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, false));
3552 radeon_emit(cs
, info
->instance_count
);
3553 state
->last_num_instances
= info
->instance_count
;
3556 if (info
->indexed
) {
3557 int index_size
= state
->index_type
? 4 : 2;
3560 index_va
= state
->index_va
;
3561 index_va
+= info
->first_index
* index_size
;
3563 if (!state
->subpass
->view_mask
) {
3564 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3569 for_each_bit(i
, state
->subpass
->view_mask
) {
3570 radv_emit_view_index(cmd_buffer
, i
);
3572 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3578 if (!state
->subpass
->view_mask
) {
3579 radv_cs_emit_draw_packet(cmd_buffer
,
3581 !!info
->strmout_buffer
);
3584 for_each_bit(i
, state
->subpass
->view_mask
) {
3585 radv_emit_view_index(cmd_buffer
, i
);
3587 radv_cs_emit_draw_packet(cmd_buffer
,
3589 !!info
->strmout_buffer
);
3597 * Vega and raven have a bug which triggers if there are multiple context
3598 * register contexts active at the same time with different scissor values.
3600 * There are two possible workarounds:
3601 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3602 * there is only ever 1 active set of scissor values at the same time.
3604 * 2) Whenever the hardware switches contexts we have to set the scissor
3605 * registers again even if it is a noop. That way the new context gets
3606 * the correct scissor values.
3608 * This implements option 2. radv_need_late_scissor_emission needs to
3609 * return true on affected HW if radv_emit_all_graphics_states sets
3610 * any context registers.
3612 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer
*cmd_buffer
,
3615 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3617 if (!cmd_buffer
->device
->physical_device
->has_scissor_bug
)
3620 uint32_t used_states
= cmd_buffer
->state
.pipeline
->graphics
.needed_dynamic_state
| ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
3622 /* Index, vertex and streamout buffers don't change context regs, and
3623 * pipeline is handled later.
3625 used_states
&= ~(RADV_CMD_DIRTY_INDEX_BUFFER
|
3626 RADV_CMD_DIRTY_VERTEX_BUFFER
|
3627 RADV_CMD_DIRTY_STREAMOUT_BUFFER
|
3628 RADV_CMD_DIRTY_PIPELINE
);
3630 /* Assume all state changes except these two can imply context rolls. */
3631 if (cmd_buffer
->state
.dirty
& used_states
)
3634 if (cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
3637 if (indexed_draw
&& state
->pipeline
->graphics
.prim_restart_enable
&&
3638 (state
->index_type
? 0xffffffffu
: 0xffffu
) != state
->last_primitive_reset_index
)
3645 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
3646 const struct radv_draw_info
*info
)
3648 bool late_scissor_emission
= radv_need_late_scissor_emission(cmd_buffer
, info
->indexed
);
3650 if ((cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
) ||
3651 cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
3652 radv_emit_rbplus_state(cmd_buffer
);
3654 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
3655 radv_emit_graphics_pipeline(cmd_buffer
);
3657 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
3658 radv_emit_framebuffer_state(cmd_buffer
);
3660 if (info
->indexed
) {
3661 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
3662 radv_emit_index_buffer(cmd_buffer
);
3664 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3665 * so the state must be re-emitted before the next indexed
3668 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3669 cmd_buffer
->state
.last_index_type
= -1;
3670 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3674 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
3676 radv_emit_draw_registers(cmd_buffer
, info
->indexed
,
3677 info
->instance_count
> 1, info
->indirect
,
3678 info
->indirect
? 0 : info
->count
);
3680 if (late_scissor_emission
)
3681 radv_emit_scissor(cmd_buffer
);
3685 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
3686 const struct radv_draw_info
*info
)
3688 struct radeon_info
*rad_info
=
3689 &cmd_buffer
->device
->physical_device
->rad_info
;
3691 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
3692 bool pipeline_is_dirty
=
3693 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
3694 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
3696 MAYBE_UNUSED
unsigned cdw_max
=
3697 radeon_check_space(cmd_buffer
->device
->ws
,
3698 cmd_buffer
->cs
, 4096);
3700 /* Use optimal packet order based on whether we need to sync the
3703 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3704 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3705 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
3706 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
3707 /* If we have to wait for idle, set all states first, so that
3708 * all SET packets are processed in parallel with previous draw
3709 * calls. Then upload descriptors, set shader pointers, and
3710 * draw, and prefetch at the end. This ensures that the time
3711 * the CUs are idle is very short. (there are only SET_SH
3712 * packets between the wait and the draw)
3714 radv_emit_all_graphics_states(cmd_buffer
, info
);
3715 si_emit_cache_flush(cmd_buffer
);
3716 /* <-- CUs are idle here --> */
3718 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
3720 radv_emit_draw_packets(cmd_buffer
, info
);
3721 /* <-- CUs are busy here --> */
3723 /* Start prefetches after the draw has been started. Both will
3724 * run in parallel, but starting the draw first is more
3727 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
3728 radv_emit_prefetch_L2(cmd_buffer
,
3729 cmd_buffer
->state
.pipeline
, false);
3732 /* If we don't wait for idle, start prefetches first, then set
3733 * states, and draw at the end.
3735 si_emit_cache_flush(cmd_buffer
);
3737 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
3738 /* Only prefetch the vertex shader and VBO descriptors
3739 * in order to start the draw as soon as possible.
3741 radv_emit_prefetch_L2(cmd_buffer
,
3742 cmd_buffer
->state
.pipeline
, true);
3745 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
3747 radv_emit_all_graphics_states(cmd_buffer
, info
);
3748 radv_emit_draw_packets(cmd_buffer
, info
);
3750 /* Prefetch the remaining shaders after the draw has been
3753 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
3754 radv_emit_prefetch_L2(cmd_buffer
,
3755 cmd_buffer
->state
.pipeline
, false);
3759 /* Workaround for a VGT hang when streamout is enabled.
3760 * It must be done after drawing.
3762 if (cmd_buffer
->state
.streamout
.streamout_enabled
&&
3763 (rad_info
->family
== CHIP_HAWAII
||
3764 rad_info
->family
== CHIP_TONGA
||
3765 rad_info
->family
== CHIP_FIJI
)) {
3766 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
;
3769 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3770 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_PS_PARTIAL_FLUSH
);
3774 VkCommandBuffer commandBuffer
,
3775 uint32_t vertexCount
,
3776 uint32_t instanceCount
,
3777 uint32_t firstVertex
,
3778 uint32_t firstInstance
)
3780 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3781 struct radv_draw_info info
= {};
3783 info
.count
= vertexCount
;
3784 info
.instance_count
= instanceCount
;
3785 info
.first_instance
= firstInstance
;
3786 info
.vertex_offset
= firstVertex
;
3788 radv_draw(cmd_buffer
, &info
);
3791 void radv_CmdDrawIndexed(
3792 VkCommandBuffer commandBuffer
,
3793 uint32_t indexCount
,
3794 uint32_t instanceCount
,
3795 uint32_t firstIndex
,
3796 int32_t vertexOffset
,
3797 uint32_t firstInstance
)
3799 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3800 struct radv_draw_info info
= {};
3802 info
.indexed
= true;
3803 info
.count
= indexCount
;
3804 info
.instance_count
= instanceCount
;
3805 info
.first_index
= firstIndex
;
3806 info
.vertex_offset
= vertexOffset
;
3807 info
.first_instance
= firstInstance
;
3809 radv_draw(cmd_buffer
, &info
);
3812 void radv_CmdDrawIndirect(
3813 VkCommandBuffer commandBuffer
,
3815 VkDeviceSize offset
,
3819 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3820 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3821 struct radv_draw_info info
= {};
3823 info
.count
= drawCount
;
3824 info
.indirect
= buffer
;
3825 info
.indirect_offset
= offset
;
3826 info
.stride
= stride
;
3828 radv_draw(cmd_buffer
, &info
);
3831 void radv_CmdDrawIndexedIndirect(
3832 VkCommandBuffer commandBuffer
,
3834 VkDeviceSize offset
,
3838 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3839 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3840 struct radv_draw_info info
= {};
3842 info
.indexed
= true;
3843 info
.count
= drawCount
;
3844 info
.indirect
= buffer
;
3845 info
.indirect_offset
= offset
;
3846 info
.stride
= stride
;
3848 radv_draw(cmd_buffer
, &info
);
3851 void radv_CmdDrawIndirectCountAMD(
3852 VkCommandBuffer commandBuffer
,
3854 VkDeviceSize offset
,
3855 VkBuffer _countBuffer
,
3856 VkDeviceSize countBufferOffset
,
3857 uint32_t maxDrawCount
,
3860 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3861 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3862 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3863 struct radv_draw_info info
= {};
3865 info
.count
= maxDrawCount
;
3866 info
.indirect
= buffer
;
3867 info
.indirect_offset
= offset
;
3868 info
.count_buffer
= count_buffer
;
3869 info
.count_buffer_offset
= countBufferOffset
;
3870 info
.stride
= stride
;
3872 radv_draw(cmd_buffer
, &info
);
3875 void radv_CmdDrawIndexedIndirectCountAMD(
3876 VkCommandBuffer commandBuffer
,
3878 VkDeviceSize offset
,
3879 VkBuffer _countBuffer
,
3880 VkDeviceSize countBufferOffset
,
3881 uint32_t maxDrawCount
,
3884 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3885 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3886 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3887 struct radv_draw_info info
= {};
3889 info
.indexed
= true;
3890 info
.count
= maxDrawCount
;
3891 info
.indirect
= buffer
;
3892 info
.indirect_offset
= offset
;
3893 info
.count_buffer
= count_buffer
;
3894 info
.count_buffer_offset
= countBufferOffset
;
3895 info
.stride
= stride
;
3897 radv_draw(cmd_buffer
, &info
);
3900 void radv_CmdDrawIndirectCountKHR(
3901 VkCommandBuffer commandBuffer
,
3903 VkDeviceSize offset
,
3904 VkBuffer _countBuffer
,
3905 VkDeviceSize countBufferOffset
,
3906 uint32_t maxDrawCount
,
3909 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3910 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3911 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3912 struct radv_draw_info info
= {};
3914 info
.count
= maxDrawCount
;
3915 info
.indirect
= buffer
;
3916 info
.indirect_offset
= offset
;
3917 info
.count_buffer
= count_buffer
;
3918 info
.count_buffer_offset
= countBufferOffset
;
3919 info
.stride
= stride
;
3921 radv_draw(cmd_buffer
, &info
);
3924 void radv_CmdDrawIndexedIndirectCountKHR(
3925 VkCommandBuffer commandBuffer
,
3927 VkDeviceSize offset
,
3928 VkBuffer _countBuffer
,
3929 VkDeviceSize countBufferOffset
,
3930 uint32_t maxDrawCount
,
3933 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3934 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3935 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3936 struct radv_draw_info info
= {};
3938 info
.indexed
= true;
3939 info
.count
= maxDrawCount
;
3940 info
.indirect
= buffer
;
3941 info
.indirect_offset
= offset
;
3942 info
.count_buffer
= count_buffer
;
3943 info
.count_buffer_offset
= countBufferOffset
;
3944 info
.stride
= stride
;
3946 radv_draw(cmd_buffer
, &info
);
3949 struct radv_dispatch_info
{
3951 * Determine the layout of the grid (in block units) to be used.
3956 * A starting offset for the grid. If unaligned is set, the offset
3957 * must still be aligned.
3959 uint32_t offsets
[3];
3961 * Whether it's an unaligned compute dispatch.
3966 * Indirect compute parameters resource.
3968 struct radv_buffer
*indirect
;
3969 uint64_t indirect_offset
;
3973 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
3974 const struct radv_dispatch_info
*info
)
3976 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3977 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
3978 unsigned dispatch_initiator
= cmd_buffer
->device
->dispatch_initiator
;
3979 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3980 bool predicating
= cmd_buffer
->state
.predicating
;
3981 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3982 struct radv_userdata_info
*loc
;
3984 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
3985 AC_UD_CS_GRID_SIZE
);
3987 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
3989 if (info
->indirect
) {
3990 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3992 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3994 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
3996 if (loc
->sgpr_idx
!= -1) {
3997 for (unsigned i
= 0; i
< 3; ++i
) {
3998 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
3999 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
4000 COPY_DATA_DST_SEL(COPY_DATA_REG
));
4001 radeon_emit(cs
, (va
+ 4 * i
));
4002 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
4003 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
4004 + loc
->sgpr_idx
* 4) >> 2) + i
);
4009 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
4010 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, predicating
) |
4011 PKT3_SHADER_TYPE_S(1));
4012 radeon_emit(cs
, va
);
4013 radeon_emit(cs
, va
>> 32);
4014 radeon_emit(cs
, dispatch_initiator
);
4016 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
4017 PKT3_SHADER_TYPE_S(1));
4019 radeon_emit(cs
, va
);
4020 radeon_emit(cs
, va
>> 32);
4022 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, predicating
) |
4023 PKT3_SHADER_TYPE_S(1));
4025 radeon_emit(cs
, dispatch_initiator
);
4028 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
4029 unsigned offsets
[3] = { info
->offsets
[0], info
->offsets
[1], info
->offsets
[2] };
4031 if (info
->unaligned
) {
4032 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
4033 unsigned remainder
[3];
4035 /* If aligned, these should be an entire block size,
4038 remainder
[0] = blocks
[0] + cs_block_size
[0] -
4039 align_u32_npot(blocks
[0], cs_block_size
[0]);
4040 remainder
[1] = blocks
[1] + cs_block_size
[1] -
4041 align_u32_npot(blocks
[1], cs_block_size
[1]);
4042 remainder
[2] = blocks
[2] + cs_block_size
[2] -
4043 align_u32_npot(blocks
[2], cs_block_size
[2]);
4045 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
4046 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
4047 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
4049 for(unsigned i
= 0; i
< 3; ++i
) {
4050 assert(offsets
[i
] % cs_block_size
[i
] == 0);
4051 offsets
[i
] /= cs_block_size
[i
];
4054 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
4056 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
4057 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
4059 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
4060 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
4062 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
4063 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
4065 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
4068 if (loc
->sgpr_idx
!= -1) {
4069 assert(!loc
->indirect
);
4070 assert(loc
->num_sgprs
== 3);
4072 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
4073 loc
->sgpr_idx
* 4, 3);
4074 radeon_emit(cs
, blocks
[0]);
4075 radeon_emit(cs
, blocks
[1]);
4076 radeon_emit(cs
, blocks
[2]);
4079 if (offsets
[0] || offsets
[1] || offsets
[2]) {
4080 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
4081 radeon_emit(cs
, offsets
[0]);
4082 radeon_emit(cs
, offsets
[1]);
4083 radeon_emit(cs
, offsets
[2]);
4085 /* The blocks in the packet are not counts but end values. */
4086 for (unsigned i
= 0; i
< 3; ++i
)
4087 blocks
[i
] += offsets
[i
];
4089 dispatch_initiator
|= S_00B800_FORCE_START_AT_000(1);
4092 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, predicating
) |
4093 PKT3_SHADER_TYPE_S(1));
4094 radeon_emit(cs
, blocks
[0]);
4095 radeon_emit(cs
, blocks
[1]);
4096 radeon_emit(cs
, blocks
[2]);
4097 radeon_emit(cs
, dispatch_initiator
);
4100 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4104 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
4106 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4107 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4111 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
4112 const struct radv_dispatch_info
*info
)
4114 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4116 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
4117 bool pipeline_is_dirty
= pipeline
&&
4118 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
4120 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4121 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4122 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4123 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4124 /* If we have to wait for idle, set all states first, so that
4125 * all SET packets are processed in parallel with previous draw
4126 * calls. Then upload descriptors, set shader pointers, and
4127 * dispatch, and prefetch at the end. This ensures that the
4128 * time the CUs are idle is very short. (there are only SET_SH
4129 * packets between the wait and the draw)
4131 radv_emit_compute_pipeline(cmd_buffer
);
4132 si_emit_cache_flush(cmd_buffer
);
4133 /* <-- CUs are idle here --> */
4135 radv_upload_compute_shader_descriptors(cmd_buffer
);
4137 radv_emit_dispatch_packets(cmd_buffer
, info
);
4138 /* <-- CUs are busy here --> */
4140 /* Start prefetches after the dispatch has been started. Both
4141 * will run in parallel, but starting the dispatch first is
4144 if (has_prefetch
&& pipeline_is_dirty
) {
4145 radv_emit_shader_prefetch(cmd_buffer
,
4146 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4149 /* If we don't wait for idle, start prefetches first, then set
4150 * states, and dispatch at the end.
4152 si_emit_cache_flush(cmd_buffer
);
4154 if (has_prefetch
&& pipeline_is_dirty
) {
4155 radv_emit_shader_prefetch(cmd_buffer
,
4156 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4159 radv_upload_compute_shader_descriptors(cmd_buffer
);
4161 radv_emit_compute_pipeline(cmd_buffer
);
4162 radv_emit_dispatch_packets(cmd_buffer
, info
);
4165 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_CS_PARTIAL_FLUSH
);
4168 void radv_CmdDispatchBase(
4169 VkCommandBuffer commandBuffer
,
4177 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4178 struct radv_dispatch_info info
= {};
4184 info
.offsets
[0] = base_x
;
4185 info
.offsets
[1] = base_y
;
4186 info
.offsets
[2] = base_z
;
4187 radv_dispatch(cmd_buffer
, &info
);
4190 void radv_CmdDispatch(
4191 VkCommandBuffer commandBuffer
,
4196 radv_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
4199 void radv_CmdDispatchIndirect(
4200 VkCommandBuffer commandBuffer
,
4202 VkDeviceSize offset
)
4204 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4205 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4206 struct radv_dispatch_info info
= {};
4208 info
.indirect
= buffer
;
4209 info
.indirect_offset
= offset
;
4211 radv_dispatch(cmd_buffer
, &info
);
4214 void radv_unaligned_dispatch(
4215 struct radv_cmd_buffer
*cmd_buffer
,
4220 struct radv_dispatch_info info
= {};
4227 radv_dispatch(cmd_buffer
, &info
);
4230 void radv_CmdEndRenderPass(
4231 VkCommandBuffer commandBuffer
)
4233 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4235 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
4237 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
4239 for (unsigned i
= 0; i
< cmd_buffer
->state
.framebuffer
->attachment_count
; ++i
) {
4240 VkImageLayout layout
= cmd_buffer
->state
.pass
->attachments
[i
].final_layout
;
4241 radv_handle_subpass_image_transition(cmd_buffer
,
4242 (struct radv_subpass_attachment
){i
, layout
});
4245 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
4247 cmd_buffer
->state
.pass
= NULL
;
4248 cmd_buffer
->state
.subpass
= NULL
;
4249 cmd_buffer
->state
.attachments
= NULL
;
4250 cmd_buffer
->state
.framebuffer
= NULL
;
4253 void radv_CmdEndRenderPass2KHR(
4254 VkCommandBuffer commandBuffer
,
4255 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4257 radv_CmdEndRenderPass(commandBuffer
);
4261 * For HTILE we have the following interesting clear words:
4262 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4263 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4264 * 0xfffffff0: Clear depth to 1.0
4265 * 0x00000000: Clear depth to 0.0
4267 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
4268 struct radv_image
*image
,
4269 const VkImageSubresourceRange
*range
,
4270 uint32_t clear_word
)
4272 assert(range
->baseMipLevel
== 0);
4273 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
4274 unsigned layer_count
= radv_get_layerCount(image
, range
);
4275 uint64_t size
= image
->surface
.htile_slice_size
* layer_count
;
4276 VkImageAspectFlags aspects
= VK_IMAGE_ASPECT_DEPTH_BIT
;
4277 uint64_t offset
= image
->offset
+ image
->htile_offset
+
4278 image
->surface
.htile_slice_size
* range
->baseArrayLayer
;
4279 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4280 VkClearDepthStencilValue value
= {};
4282 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4283 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4285 state
->flush_bits
|= radv_fill_buffer(cmd_buffer
, image
->bo
, offset
,
4288 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4290 if (vk_format_is_stencil(image
->vk_format
))
4291 aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
4293 radv_set_ds_clear_metadata(cmd_buffer
, image
, value
, aspects
);
4295 if (radv_image_is_tc_compat_htile(image
)) {
4296 /* Initialize the TC-compat metada value to 0 because by
4297 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4298 * need have to conditionally update its value when performing
4299 * a fast depth clear.
4301 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, 0);
4305 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4306 struct radv_image
*image
,
4307 VkImageLayout src_layout
,
4308 VkImageLayout dst_layout
,
4309 unsigned src_queue_mask
,
4310 unsigned dst_queue_mask
,
4311 const VkImageSubresourceRange
*range
)
4313 if (!radv_image_has_htile(image
))
4316 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
&&
4317 radv_layout_has_htile(image
, dst_layout
, dst_queue_mask
)) {
4318 /* TODO: merge with the clear if applicable */
4319 radv_initialize_htile(cmd_buffer
, image
, range
, 0);
4320 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
4321 radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
4322 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
4323 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
4324 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
4325 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
4326 VkImageSubresourceRange local_range
= *range
;
4327 local_range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
4328 local_range
.baseMipLevel
= 0;
4329 local_range
.levelCount
= 1;
4331 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4332 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4334 radv_decompress_depth_image_inplace(cmd_buffer
, image
, &local_range
);
4336 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4337 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4341 static void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
4342 struct radv_image
*image
, uint32_t value
)
4344 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4346 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4347 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4349 state
->flush_bits
|= radv_clear_cmask(cmd_buffer
, image
, value
);
4351 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4354 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
4355 struct radv_image
*image
)
4357 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4358 static const uint32_t fmask_clear_values
[4] = {
4364 uint32_t log2_samples
= util_logbase2(image
->info
.samples
);
4365 uint32_t value
= fmask_clear_values
[log2_samples
];
4367 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4368 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4370 state
->flush_bits
|= radv_clear_fmask(cmd_buffer
, image
, value
);
4372 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4375 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
4376 struct radv_image
*image
, uint32_t value
)
4378 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4380 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4381 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4383 state
->flush_bits
|= radv_clear_dcc(cmd_buffer
, image
, value
);
4385 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4386 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4390 * Initialize DCC/FMASK/CMASK metadata for a color image.
4392 static void radv_init_color_image_metadata(struct radv_cmd_buffer
*cmd_buffer
,
4393 struct radv_image
*image
,
4394 VkImageLayout src_layout
,
4395 VkImageLayout dst_layout
,
4396 unsigned src_queue_mask
,
4397 unsigned dst_queue_mask
)
4399 if (radv_image_has_cmask(image
)) {
4400 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
4402 /* TODO: clarify this. */
4403 if (radv_image_has_fmask(image
)) {
4404 value
= 0xccccccccu
;
4407 radv_initialise_cmask(cmd_buffer
, image
, value
);
4410 if (radv_image_has_fmask(image
)) {
4411 radv_initialize_fmask(cmd_buffer
, image
);
4414 if (radv_image_has_dcc(image
)) {
4415 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
4416 bool need_decompress_pass
= false;
4418 if (radv_layout_dcc_compressed(image
, dst_layout
,
4420 value
= 0x20202020u
;
4421 need_decompress_pass
= true;
4424 radv_initialize_dcc(cmd_buffer
, image
, value
);
4426 radv_update_fce_metadata(cmd_buffer
, image
,
4427 need_decompress_pass
);
4430 if (radv_image_has_cmask(image
) || radv_image_has_dcc(image
)) {
4431 uint32_t color_values
[2] = {};
4432 radv_set_color_clear_metadata(cmd_buffer
, image
, color_values
);
4437 * Handle color image transitions for DCC/FMASK/CMASK.
4439 static void radv_handle_color_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4440 struct radv_image
*image
,
4441 VkImageLayout src_layout
,
4442 VkImageLayout dst_layout
,
4443 unsigned src_queue_mask
,
4444 unsigned dst_queue_mask
,
4445 const VkImageSubresourceRange
*range
)
4447 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
4448 radv_init_color_image_metadata(cmd_buffer
, image
,
4449 src_layout
, dst_layout
,
4450 src_queue_mask
, dst_queue_mask
);
4454 if (radv_image_has_dcc(image
)) {
4455 if (src_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
4456 radv_initialize_dcc(cmd_buffer
, image
, 0xffffffffu
);
4457 } else if (radv_layout_dcc_compressed(image
, src_layout
, src_queue_mask
) &&
4458 !radv_layout_dcc_compressed(image
, dst_layout
, dst_queue_mask
)) {
4459 radv_decompress_dcc(cmd_buffer
, image
, range
);
4460 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
4461 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
4462 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
4464 } else if (radv_image_has_cmask(image
) || radv_image_has_fmask(image
)) {
4465 if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
4466 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
4467 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
4472 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4473 struct radv_image
*image
,
4474 VkImageLayout src_layout
,
4475 VkImageLayout dst_layout
,
4476 uint32_t src_family
,
4477 uint32_t dst_family
,
4478 const VkImageSubresourceRange
*range
)
4480 if (image
->exclusive
&& src_family
!= dst_family
) {
4481 /* This is an acquire or a release operation and there will be
4482 * a corresponding release/acquire. Do the transition in the
4483 * most flexible queue. */
4485 assert(src_family
== cmd_buffer
->queue_family_index
||
4486 dst_family
== cmd_buffer
->queue_family_index
);
4488 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
4491 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
4492 (src_family
== RADV_QUEUE_GENERAL
||
4493 dst_family
== RADV_QUEUE_GENERAL
))
4497 unsigned src_queue_mask
=
4498 radv_image_queue_family_mask(image
, src_family
,
4499 cmd_buffer
->queue_family_index
);
4500 unsigned dst_queue_mask
=
4501 radv_image_queue_family_mask(image
, dst_family
,
4502 cmd_buffer
->queue_family_index
);
4504 if (vk_format_is_depth(image
->vk_format
)) {
4505 radv_handle_depth_image_transition(cmd_buffer
, image
,
4506 src_layout
, dst_layout
,
4507 src_queue_mask
, dst_queue_mask
,
4510 radv_handle_color_image_transition(cmd_buffer
, image
,
4511 src_layout
, dst_layout
,
4512 src_queue_mask
, dst_queue_mask
,
4517 struct radv_barrier_info
{
4518 uint32_t eventCount
;
4519 const VkEvent
*pEvents
;
4520 VkPipelineStageFlags srcStageMask
;
4524 radv_barrier(struct radv_cmd_buffer
*cmd_buffer
,
4525 uint32_t memoryBarrierCount
,
4526 const VkMemoryBarrier
*pMemoryBarriers
,
4527 uint32_t bufferMemoryBarrierCount
,
4528 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
4529 uint32_t imageMemoryBarrierCount
,
4530 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
4531 const struct radv_barrier_info
*info
)
4533 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4534 enum radv_cmd_flush_bits src_flush_bits
= 0;
4535 enum radv_cmd_flush_bits dst_flush_bits
= 0;
4537 for (unsigned i
= 0; i
< info
->eventCount
; ++i
) {
4538 RADV_FROM_HANDLE(radv_event
, event
, info
->pEvents
[i
]);
4539 uint64_t va
= radv_buffer_get_va(event
->bo
);
4541 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
4543 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
4545 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, va
, 1, 0xffffffff);
4546 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4549 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
4550 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
,
4552 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
4556 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
4557 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
,
4559 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
4563 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
4564 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
4566 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
,
4568 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
4572 radv_stage_flush(cmd_buffer
, info
->srcStageMask
);
4573 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
4575 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
4576 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
4577 radv_handle_image_transition(cmd_buffer
, image
,
4578 pImageMemoryBarriers
[i
].oldLayout
,
4579 pImageMemoryBarriers
[i
].newLayout
,
4580 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
4581 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
4582 &pImageMemoryBarriers
[i
].subresourceRange
);
4585 /* Make sure CP DMA is idle because the driver might have performed a
4586 * DMA operation for copying or filling buffers/images.
4588 if (info
->srcStageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
4589 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
4590 si_cp_dma_wait_for_idle(cmd_buffer
);
4592 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
4595 void radv_CmdPipelineBarrier(
4596 VkCommandBuffer commandBuffer
,
4597 VkPipelineStageFlags srcStageMask
,
4598 VkPipelineStageFlags destStageMask
,
4600 uint32_t memoryBarrierCount
,
4601 const VkMemoryBarrier
* pMemoryBarriers
,
4602 uint32_t bufferMemoryBarrierCount
,
4603 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4604 uint32_t imageMemoryBarrierCount
,
4605 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4607 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4608 struct radv_barrier_info info
;
4610 info
.eventCount
= 0;
4611 info
.pEvents
= NULL
;
4612 info
.srcStageMask
= srcStageMask
;
4614 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
4615 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
4616 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
4620 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
4621 struct radv_event
*event
,
4622 VkPipelineStageFlags stageMask
,
4625 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4626 uint64_t va
= radv_buffer_get_va(event
->bo
);
4628 si_emit_cache_flush(cmd_buffer
);
4630 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
4632 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 18);
4634 /* Flags that only require a top-of-pipe event. */
4635 VkPipelineStageFlags top_of_pipe_flags
=
4636 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
;
4638 /* Flags that only require a post-index-fetch event. */
4639 VkPipelineStageFlags post_index_fetch_flags
=
4641 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
4642 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
;
4644 /* Make sure CP DMA is idle because the driver might have performed a
4645 * DMA operation for copying or filling buffers/images.
4647 if (stageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
4648 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
4649 si_cp_dma_wait_for_idle(cmd_buffer
);
4651 /* TODO: Emit EOS events for syncing PS/CS stages. */
4653 if (!(stageMask
& ~top_of_pipe_flags
)) {
4654 /* Just need to sync the PFP engine. */
4655 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
4656 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
4657 S_370_WR_CONFIRM(1) |
4658 S_370_ENGINE_SEL(V_370_PFP
));
4659 radeon_emit(cs
, va
);
4660 radeon_emit(cs
, va
>> 32);
4661 radeon_emit(cs
, value
);
4662 } else if (!(stageMask
& ~post_index_fetch_flags
)) {
4663 /* Sync ME because PFP reads index and indirect buffers. */
4664 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
4665 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
4666 S_370_WR_CONFIRM(1) |
4667 S_370_ENGINE_SEL(V_370_ME
));
4668 radeon_emit(cs
, va
);
4669 radeon_emit(cs
, va
>> 32);
4670 radeon_emit(cs
, value
);
4672 /* Otherwise, sync all prior GPU work using an EOP event. */
4673 si_cs_emit_write_event_eop(cs
,
4674 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
4675 radv_cmd_buffer_uses_mec(cmd_buffer
),
4676 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
4677 EOP_DATA_SEL_VALUE_32BIT
, va
, 2, value
,
4678 cmd_buffer
->gfx9_eop_bug_va
);
4681 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4684 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
4686 VkPipelineStageFlags stageMask
)
4688 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4689 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4691 write_event(cmd_buffer
, event
, stageMask
, 1);
4694 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
4696 VkPipelineStageFlags stageMask
)
4698 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4699 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4701 write_event(cmd_buffer
, event
, stageMask
, 0);
4704 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
4705 uint32_t eventCount
,
4706 const VkEvent
* pEvents
,
4707 VkPipelineStageFlags srcStageMask
,
4708 VkPipelineStageFlags dstStageMask
,
4709 uint32_t memoryBarrierCount
,
4710 const VkMemoryBarrier
* pMemoryBarriers
,
4711 uint32_t bufferMemoryBarrierCount
,
4712 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4713 uint32_t imageMemoryBarrierCount
,
4714 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4716 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4717 struct radv_barrier_info info
;
4719 info
.eventCount
= eventCount
;
4720 info
.pEvents
= pEvents
;
4721 info
.srcStageMask
= 0;
4723 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
4724 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
4725 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
4729 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer
,
4730 uint32_t deviceMask
)
4735 /* VK_EXT_conditional_rendering */
4736 void radv_CmdBeginConditionalRenderingEXT(
4737 VkCommandBuffer commandBuffer
,
4738 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
4740 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4741 RADV_FROM_HANDLE(radv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
4742 bool draw_visible
= true;
4745 va
= radv_buffer_get_va(buffer
->bo
) + pConditionalRenderingBegin
->offset
;
4747 /* By default, if the 32-bit value at offset in buffer memory is zero,
4748 * then the rendering commands are discarded, otherwise they are
4749 * executed as normal. If the inverted flag is set, all commands are
4750 * discarded if the value is non zero.
4752 if (pConditionalRenderingBegin
->flags
&
4753 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
) {
4754 draw_visible
= false;
4757 /* Enable predication for this command buffer. */
4758 si_emit_set_predication_state(cmd_buffer
, draw_visible
, va
);
4759 cmd_buffer
->state
.predicating
= true;
4761 /* Store conditional rendering user info. */
4762 cmd_buffer
->state
.predication_type
= draw_visible
;
4763 cmd_buffer
->state
.predication_va
= va
;
4766 void radv_CmdEndConditionalRenderingEXT(
4767 VkCommandBuffer commandBuffer
)
4769 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4771 /* Disable predication for this command buffer. */
4772 si_emit_set_predication_state(cmd_buffer
, false, 0);
4773 cmd_buffer
->state
.predicating
= false;
4775 /* Reset conditional rendering user info. */
4776 cmd_buffer
->state
.predication_type
= -1;
4777 cmd_buffer
->state
.predication_va
= 0;
4780 /* VK_EXT_transform_feedback */
4781 void radv_CmdBindTransformFeedbackBuffersEXT(
4782 VkCommandBuffer commandBuffer
,
4783 uint32_t firstBinding
,
4784 uint32_t bindingCount
,
4785 const VkBuffer
* pBuffers
,
4786 const VkDeviceSize
* pOffsets
,
4787 const VkDeviceSize
* pSizes
)
4789 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4790 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
4791 uint8_t enabled_mask
= 0;
4793 assert(firstBinding
+ bindingCount
<= MAX_SO_BUFFERS
);
4794 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
4795 uint32_t idx
= firstBinding
+ i
;
4797 sb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
4798 sb
[idx
].offset
= pOffsets
[i
];
4799 sb
[idx
].size
= pSizes
[i
];
4801 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
4802 sb
[idx
].buffer
->bo
);
4804 enabled_mask
|= 1 << idx
;
4807 cmd_buffer
->state
.streamout
.enabled_mask
= enabled_mask
;
4809 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
4813 radv_emit_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
)
4815 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
4816 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4818 radeon_set_context_reg_seq(cs
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
4820 S_028B94_STREAMOUT_0_EN(so
->streamout_enabled
) |
4821 S_028B94_RAST_STREAM(0) |
4822 S_028B94_STREAMOUT_1_EN(so
->streamout_enabled
) |
4823 S_028B94_STREAMOUT_2_EN(so
->streamout_enabled
) |
4824 S_028B94_STREAMOUT_3_EN(so
->streamout_enabled
));
4825 radeon_emit(cs
, so
->hw_enabled_mask
&
4826 so
->enabled_stream_buffers_mask
);
4830 radv_set_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
, bool enable
)
4832 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
4833 bool old_streamout_enabled
= so
->streamout_enabled
;
4834 uint32_t old_hw_enabled_mask
= so
->hw_enabled_mask
;
4836 so
->streamout_enabled
= enable
;
4838 so
->hw_enabled_mask
= so
->enabled_mask
|
4839 (so
->enabled_mask
<< 4) |
4840 (so
->enabled_mask
<< 8) |
4841 (so
->enabled_mask
<< 12);
4843 if ((old_streamout_enabled
!= so
->streamout_enabled
) ||
4844 (old_hw_enabled_mask
!= so
->hw_enabled_mask
))
4845 radv_emit_streamout_enable(cmd_buffer
);
4848 static void radv_flush_vgt_streamout(struct radv_cmd_buffer
*cmd_buffer
)
4850 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4851 unsigned reg_strmout_cntl
;
4853 /* The register is at different places on different ASICs. */
4854 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
4855 reg_strmout_cntl
= R_0300FC_CP_STRMOUT_CNTL
;
4856 radeon_set_uconfig_reg(cs
, reg_strmout_cntl
, 0);
4858 reg_strmout_cntl
= R_0084FC_CP_STRMOUT_CNTL
;
4859 radeon_set_config_reg(cs
, reg_strmout_cntl
, 0);
4862 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4863 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH
) | EVENT_INDEX(0));
4865 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
4866 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
); /* wait until the register is equal to the reference value */
4867 radeon_emit(cs
, reg_strmout_cntl
>> 2); /* register */
4869 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
4870 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
4871 radeon_emit(cs
, 4); /* poll interval */
4874 void radv_CmdBeginTransformFeedbackEXT(
4875 VkCommandBuffer commandBuffer
,
4876 uint32_t firstCounterBuffer
,
4877 uint32_t counterBufferCount
,
4878 const VkBuffer
* pCounterBuffers
,
4879 const VkDeviceSize
* pCounterBufferOffsets
)
4881 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4882 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
4883 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
4884 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4887 radv_flush_vgt_streamout(cmd_buffer
);
4889 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
4890 for_each_bit(i
, so
->enabled_mask
) {
4891 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
4892 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
4893 counter_buffer_idx
= -1;
4895 /* SI binds streamout buffers as shader resources.
4896 * VGT only counts primitives and tells the shader through
4899 radeon_set_context_reg_seq(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 2);
4900 radeon_emit(cs
, sb
[i
].size
>> 2); /* BUFFER_SIZE (in DW) */
4901 radeon_emit(cs
, so
->stride_in_dw
[i
]); /* VTX_STRIDE (in DW) */
4903 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
4904 /* The array of counter buffers is optional. */
4905 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
4906 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
4908 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
4911 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
4912 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
4913 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4914 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM
)); /* control */
4915 radeon_emit(cs
, 0); /* unused */
4916 radeon_emit(cs
, 0); /* unused */
4917 radeon_emit(cs
, va
); /* src address lo */
4918 radeon_emit(cs
, va
>> 32); /* src address hi */
4920 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
4922 /* Start from the beginning. */
4923 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
4924 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
4925 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4926 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET
)); /* control */
4927 radeon_emit(cs
, 0); /* unused */
4928 radeon_emit(cs
, 0); /* unused */
4929 radeon_emit(cs
, 0); /* unused */
4930 radeon_emit(cs
, 0); /* unused */
4934 radv_set_streamout_enable(cmd_buffer
, true);
4937 void radv_CmdEndTransformFeedbackEXT(
4938 VkCommandBuffer commandBuffer
,
4939 uint32_t firstCounterBuffer
,
4940 uint32_t counterBufferCount
,
4941 const VkBuffer
* pCounterBuffers
,
4942 const VkDeviceSize
* pCounterBufferOffsets
)
4944 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4945 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
4946 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4949 radv_flush_vgt_streamout(cmd_buffer
);
4951 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
4952 for_each_bit(i
, so
->enabled_mask
) {
4953 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
4954 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
4955 counter_buffer_idx
= -1;
4957 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
4958 /* The array of counters buffer is optional. */
4959 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
4960 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
4962 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
4964 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
4965 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
4966 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4967 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE
) |
4968 STRMOUT_STORE_BUFFER_FILLED_SIZE
); /* control */
4969 radeon_emit(cs
, va
); /* dst address lo */
4970 radeon_emit(cs
, va
>> 32); /* dst address hi */
4971 radeon_emit(cs
, 0); /* unused */
4972 radeon_emit(cs
, 0); /* unused */
4974 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
4977 /* Deactivate transform feedback by zeroing the buffer size.
4978 * The counters (primitives generated, primitives emitted) may
4979 * be enabled even if there is not buffer bound. This ensures
4980 * that the primitives-emitted query won't increment.
4982 radeon_set_context_reg(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 0);
4985 radv_set_streamout_enable(cmd_buffer
, false);
4988 void radv_CmdDrawIndirectByteCountEXT(
4989 VkCommandBuffer commandBuffer
,
4990 uint32_t instanceCount
,
4991 uint32_t firstInstance
,
4992 VkBuffer _counterBuffer
,
4993 VkDeviceSize counterBufferOffset
,
4994 uint32_t counterOffset
,
4995 uint32_t vertexStride
)
4997 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4998 RADV_FROM_HANDLE(radv_buffer
, counterBuffer
, _counterBuffer
);
4999 struct radv_draw_info info
= {};
5001 info
.instance_count
= instanceCount
;
5002 info
.first_instance
= firstInstance
;
5003 info
.strmout_buffer
= counterBuffer
;
5004 info
.strmout_buffer_offset
= counterBufferOffset
;
5005 info
.stride
= vertexStride
;
5007 radv_draw(cmd_buffer
, &info
);