5b93083913b9c81afbe69d0595b9cdd066a557a3
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "dirent.h"
29 #include <errno.h>
30 #include <fcntl.h>
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
36 #include <stdatomic.h>
37 #include <stdbool.h>
38 #include <stddef.h>
39 #include <stdio.h>
40 #include <string.h>
41 #include <sys/prctl.h>
42 #include <sys/wait.h>
43 #include <unistd.h>
44 #include <fcntl.h>
45
46 #include "radv_debug.h"
47 #include "radv_private.h"
48 #include "radv_shader.h"
49 #include "radv_cs.h"
50 #include "util/disk_cache.h"
51 #include "vk_util.h"
52 #include <xf86drm.h>
53 #include <amdgpu.h>
54 #include "drm-uapi/amdgpu_drm.h"
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "winsys/null/radv_null_winsys_public.h"
57 #include "ac_llvm_util.h"
58 #include "vk_format.h"
59 #include "sid.h"
60 #include "git_sha1.h"
61 #include "util/build_id.h"
62 #include "util/debug.h"
63 #include "util/mesa-sha1.h"
64 #include "util/timespec.h"
65 #include "util/u_atomic.h"
66 #include "compiler/glsl_types.h"
67 #include "util/driconf.h"
68
69 static struct radv_timeline_point *
70 radv_timeline_find_point_at_least_locked(struct radv_device *device,
71 struct radv_timeline *timeline,
72 uint64_t p);
73
74 static struct radv_timeline_point *
75 radv_timeline_add_point_locked(struct radv_device *device,
76 struct radv_timeline *timeline,
77 uint64_t p);
78
79 static void
80 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
81 struct list_head *processing_list);
82
83 static
84 void radv_destroy_semaphore_part(struct radv_device *device,
85 struct radv_semaphore_part *part);
86
87 static VkResult
88 radv_create_pthread_cond(pthread_cond_t *cond);
89
90 uint64_t radv_get_current_time(void)
91 {
92 struct timespec tv;
93 clock_gettime(CLOCK_MONOTONIC, &tv);
94 return tv.tv_nsec + tv.tv_sec*1000000000ull;
95 }
96
97 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
98 {
99 uint64_t current_time = radv_get_current_time();
100
101 timeout = MIN2(UINT64_MAX - current_time, timeout);
102
103 return current_time + timeout;
104 }
105
106 static int
107 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
108 {
109 struct mesa_sha1 ctx;
110 unsigned char sha1[20];
111 unsigned ptr_size = sizeof(void*);
112
113 memset(uuid, 0, VK_UUID_SIZE);
114 _mesa_sha1_init(&ctx);
115
116 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
117 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
118 return -1;
119
120 _mesa_sha1_update(&ctx, &family, sizeof(family));
121 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
122 _mesa_sha1_final(&ctx, sha1);
123
124 memcpy(uuid, sha1, VK_UUID_SIZE);
125 return 0;
126 }
127
128 static void
129 radv_get_driver_uuid(void *uuid)
130 {
131 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
132 }
133
134 static void
135 radv_get_device_uuid(struct radeon_info *info, void *uuid)
136 {
137 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
138 }
139
140 static uint64_t
141 radv_get_visible_vram_size(struct radv_physical_device *device)
142 {
143 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
144 }
145
146 static uint64_t
147 radv_get_vram_size(struct radv_physical_device *device)
148 {
149 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
150 }
151
152 static void
153 radv_physical_device_init_mem_types(struct radv_physical_device *device)
154 {
155 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
156 uint64_t vram_size = radv_get_vram_size(device);
157 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
158 device->memory_properties.memoryHeapCount = 0;
159 if (vram_size > 0) {
160 vram_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
162 .size = vram_size,
163 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 if (device->rad_info.gart_size > 0) {
168 gart_index = device->memory_properties.memoryHeapCount++;
169 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
170 .size = device->rad_info.gart_size,
171 .flags = 0,
172 };
173 }
174
175 if (visible_vram_size) {
176 visible_vram_index = device->memory_properties.memoryHeapCount++;
177 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
178 .size = visible_vram_size,
179 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
180 };
181 }
182
183 unsigned type_count = 0;
184
185 if (vram_index >= 0 || visible_vram_index >= 0) {
186 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
187 device->memory_flags[type_count] = RADEON_FLAG_NO_CPU_ACCESS;
188 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
189 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
190 .heapIndex = vram_index >= 0 ? vram_index : visible_vram_index,
191 };
192 }
193
194 if (gart_index >= 0) {
195 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
196 device->memory_flags[type_count] = RADEON_FLAG_GTT_WC | RADEON_FLAG_CPU_ACCESS;
197 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
198 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
199 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
200 .heapIndex = gart_index,
201 };
202 }
203 if (visible_vram_index >= 0) {
204 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
205 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
206 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
207 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
208 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
209 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
210 .heapIndex = visible_vram_index,
211 };
212 }
213
214 if (gart_index >= 0) {
215 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
216 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
217 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
218 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
219 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
220 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
221 .heapIndex = gart_index,
222 };
223 }
224 device->memory_properties.memoryTypeCount = type_count;
225
226 if (device->rad_info.has_l2_uncached) {
227 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
228 VkMemoryType mem_type = device->memory_properties.memoryTypes[i];
229
230 if ((mem_type.propertyFlags & (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
231 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)) ||
232 mem_type.propertyFlags == VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) {
233
234 VkMemoryPropertyFlags property_flags = mem_type.propertyFlags |
235 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD |
236 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD;
237
238 device->memory_domains[type_count] = device->memory_domains[i];
239 device->memory_flags[type_count] = device->memory_flags[i] | RADEON_FLAG_VA_UNCACHED;
240 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
241 .propertyFlags = property_flags,
242 .heapIndex = mem_type.heapIndex,
243 };
244 }
245 }
246 device->memory_properties.memoryTypeCount = type_count;
247 }
248 }
249
250 static const char *
251 radv_get_compiler_string(struct radv_physical_device *pdevice)
252 {
253 if (!pdevice->use_llvm) {
254 /* Some games like SotTR apply shader workarounds if the LLVM
255 * version is too old or if the LLVM version string is
256 * missing. This gives 2-5% performance with SotTR and ACO.
257 */
258 if (driQueryOptionb(&pdevice->instance->dri_options,
259 "radv_report_llvm9_version_string")) {
260 return "ACO/LLVM 9.0.1";
261 }
262
263 return "ACO";
264 }
265
266 return "LLVM " MESA_LLVM_VERSION_STRING;
267 }
268
269 static VkResult
270 radv_physical_device_try_create(struct radv_instance *instance,
271 drmDevicePtr drm_device,
272 struct radv_physical_device **device_out)
273 {
274 VkResult result;
275 int fd = -1;
276 int master_fd = -1;
277
278 if (drm_device) {
279 const char *path = drm_device->nodes[DRM_NODE_RENDER];
280 drmVersionPtr version;
281
282 fd = open(path, O_RDWR | O_CLOEXEC);
283 if (fd < 0) {
284 if (instance->debug_flags & RADV_DEBUG_STARTUP)
285 radv_logi("Could not open device '%s'", path);
286
287 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
288 }
289
290 version = drmGetVersion(fd);
291 if (!version) {
292 close(fd);
293
294 if (instance->debug_flags & RADV_DEBUG_STARTUP)
295 radv_logi("Could not get the kernel driver version for device '%s'", path);
296
297 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
298 "failed to get version %s: %m", path);
299 }
300
301 if (strcmp(version->name, "amdgpu")) {
302 drmFreeVersion(version);
303 close(fd);
304
305 if (instance->debug_flags & RADV_DEBUG_STARTUP)
306 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
307
308 return VK_ERROR_INCOMPATIBLE_DRIVER;
309 }
310 drmFreeVersion(version);
311
312 if (instance->debug_flags & RADV_DEBUG_STARTUP)
313 radv_logi("Found compatible device '%s'.", path);
314 }
315
316 struct radv_physical_device *device =
317 vk_zalloc2(&instance->alloc, NULL, sizeof(*device), 8,
318 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
319 if (!device) {
320 result = vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
321 goto fail_fd;
322 }
323
324 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
325 device->instance = instance;
326
327 if (drm_device) {
328 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
329 instance->perftest_flags);
330 } else {
331 device->ws = radv_null_winsys_create();
332 }
333
334 if (!device->ws) {
335 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
336 "failed to initialize winsys");
337 goto fail_alloc;
338 }
339
340 if (drm_device && instance->enabled_extensions.KHR_display) {
341 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
342 if (master_fd >= 0) {
343 uint32_t accel_working = 0;
344 struct drm_amdgpu_info request = {
345 .return_pointer = (uintptr_t)&accel_working,
346 .return_size = sizeof(accel_working),
347 .query = AMDGPU_INFO_ACCEL_WORKING
348 };
349
350 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
351 close(master_fd);
352 master_fd = -1;
353 }
354 }
355 }
356
357 device->master_fd = master_fd;
358 device->local_fd = fd;
359 device->ws->query_info(device->ws, &device->rad_info);
360
361 device->use_llvm = instance->debug_flags & RADV_DEBUG_LLVM;
362
363 snprintf(device->name, sizeof(device->name),
364 "AMD RADV %s (%s)",
365 device->rad_info.name, radv_get_compiler_string(device));
366
367 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
368 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
369 "cannot generate UUID");
370 goto fail_wsi;
371 }
372
373 /* These flags affect shader compilation. */
374 uint64_t shader_env_flags = (device->use_llvm ? 0 : 0x2);
375
376 /* The gpu id is already embedded in the uuid so we just pass "radv"
377 * when creating the cache.
378 */
379 char buf[VK_UUID_SIZE * 2 + 1];
380 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
381 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
382
383 if (device->rad_info.chip_class < GFX8 || !device->use_llvm)
384 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
385
386 radv_get_driver_uuid(&device->driver_uuid);
387 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
388
389 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
390 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
391
392 device->dcc_msaa_allowed =
393 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
394
395 device->use_ngg = device->rad_info.chip_class >= GFX10 &&
396 device->rad_info.family != CHIP_NAVI14 &&
397 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
398
399 /* TODO: Implement NGG GS with ACO. */
400 device->use_ngg_gs = device->use_ngg && device->use_llvm;
401 device->use_ngg_streamout = false;
402
403 /* Determine the number of threads per wave for all stages. */
404 device->cs_wave_size = 64;
405 device->ps_wave_size = 64;
406 device->ge_wave_size = 64;
407
408 if (device->rad_info.chip_class >= GFX10) {
409 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
410 device->cs_wave_size = 32;
411
412 /* For pixel shaders, wave64 is recommanded. */
413 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
414 device->ps_wave_size = 32;
415
416 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
417 device->ge_wave_size = 32;
418 }
419
420 radv_physical_device_init_mem_types(device);
421
422 radv_physical_device_get_supported_extensions(device,
423 &device->supported_extensions);
424
425 if (drm_device)
426 device->bus_info = *drm_device->businfo.pci;
427
428 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
429 ac_print_gpu_info(&device->rad_info);
430
431 /* The WSI is structured as a layer on top of the driver, so this has
432 * to be the last part of initialization (at least until we get other
433 * semi-layers).
434 */
435 result = radv_init_wsi(device);
436 if (result != VK_SUCCESS) {
437 vk_error(instance, result);
438 goto fail_disk_cache;
439 }
440
441 *device_out = device;
442
443 return VK_SUCCESS;
444
445 fail_disk_cache:
446 disk_cache_destroy(device->disk_cache);
447 fail_wsi:
448 device->ws->destroy(device->ws);
449 fail_alloc:
450 vk_free(&instance->alloc, device);
451 fail_fd:
452 if (fd != -1)
453 close(fd);
454 if (master_fd != -1)
455 close(master_fd);
456 return result;
457 }
458
459 static void
460 radv_physical_device_destroy(struct radv_physical_device *device)
461 {
462 radv_finish_wsi(device);
463 device->ws->destroy(device->ws);
464 disk_cache_destroy(device->disk_cache);
465 close(device->local_fd);
466 if (device->master_fd != -1)
467 close(device->master_fd);
468 vk_free(&device->instance->alloc, device);
469 }
470
471 static void *
472 default_alloc_func(void *pUserData, size_t size, size_t align,
473 VkSystemAllocationScope allocationScope)
474 {
475 return malloc(size);
476 }
477
478 static void *
479 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
480 size_t align, VkSystemAllocationScope allocationScope)
481 {
482 return realloc(pOriginal, size);
483 }
484
485 static void
486 default_free_func(void *pUserData, void *pMemory)
487 {
488 free(pMemory);
489 }
490
491 static const VkAllocationCallbacks default_alloc = {
492 .pUserData = NULL,
493 .pfnAllocation = default_alloc_func,
494 .pfnReallocation = default_realloc_func,
495 .pfnFree = default_free_func,
496 };
497
498 static const struct debug_control radv_debug_options[] = {
499 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
500 {"nodcc", RADV_DEBUG_NO_DCC},
501 {"shaders", RADV_DEBUG_DUMP_SHADERS},
502 {"nocache", RADV_DEBUG_NO_CACHE},
503 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
504 {"nohiz", RADV_DEBUG_NO_HIZ},
505 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
506 {"allbos", RADV_DEBUG_ALL_BOS},
507 {"noibs", RADV_DEBUG_NO_IBS},
508 {"spirv", RADV_DEBUG_DUMP_SPIRV},
509 {"vmfaults", RADV_DEBUG_VM_FAULTS},
510 {"zerovram", RADV_DEBUG_ZERO_VRAM},
511 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
512 {"preoptir", RADV_DEBUG_PREOPTIR},
513 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
514 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
515 {"info", RADV_DEBUG_INFO},
516 {"errors", RADV_DEBUG_ERRORS},
517 {"startup", RADV_DEBUG_STARTUP},
518 {"checkir", RADV_DEBUG_CHECKIR},
519 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
520 {"nobinning", RADV_DEBUG_NOBINNING},
521 {"nongg", RADV_DEBUG_NO_NGG},
522 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
523 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
524 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE},
525 {"llvm", RADV_DEBUG_LLVM},
526 {"forcecompress", RADV_DEBUG_FORCE_COMPRESS},
527 {NULL, 0}
528 };
529
530 const char *
531 radv_get_debug_option_name(int id)
532 {
533 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
534 return radv_debug_options[id].string;
535 }
536
537 static const struct debug_control radv_perftest_options[] = {
538 {"localbos", RADV_PERFTEST_LOCAL_BOS},
539 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
540 {"bolist", RADV_PERFTEST_BO_LIST},
541 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
542 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
543 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
544 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
545 {"dfsm", RADV_PERFTEST_DFSM},
546 {NULL, 0}
547 };
548
549 const char *
550 radv_get_perftest_option_name(int id)
551 {
552 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
553 return radv_perftest_options[id].string;
554 }
555
556 static void
557 radv_handle_per_app_options(struct radv_instance *instance,
558 const VkApplicationInfo *info)
559 {
560 const char *name = info ? info->pApplicationName : NULL;
561 const char *engine_name = info ? info->pEngineName : NULL;
562
563 if (name) {
564 if (!strcmp(name, "DOOM_VFR")) {
565 /* Work around a Doom VFR game bug */
566 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
567 } else if (!strcmp(name, "Fledge")) {
568 /*
569 * Zero VRAM for "The Surge 2"
570 *
571 * This avoid a hang when when rendering any level. Likely
572 * uninitialized data in an indirect draw.
573 */
574 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
575 } else if (!strcmp(name, "No Man's Sky")) {
576 /* Work around a NMS game bug */
577 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
578 } else if (!strcmp(name, "DOOMEternal")) {
579 /* Zero VRAM for Doom Eternal to fix rendering issues. */
580 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
581 } else if (!strcmp(name, "Red Dead Redemption 2")) {
582 /* Work around a RDR2 game bug */
583 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
584 }
585 }
586
587 if (engine_name) {
588 if (!strcmp(engine_name, "vkd3d")) {
589 /* Zero VRAM for all VKD3D (DX12->VK) games to fix
590 * rendering issues.
591 */
592 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
593 } else if (!strcmp(engine_name, "Quantic Dream Engine")) {
594 /* Fix various artifacts in Detroit: Become Human */
595 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM |
596 RADV_DEBUG_DISCARD_TO_DEMOTE;
597 }
598 }
599
600 instance->enable_mrt_output_nan_fixup =
601 driQueryOptionb(&instance->dri_options,
602 "radv_enable_mrt_output_nan_fixup");
603
604 if (driQueryOptionb(&instance->dri_options, "radv_no_dynamic_bounds"))
605 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
606 }
607
608 static const char radv_dri_options_xml[] =
609 DRI_CONF_BEGIN
610 DRI_CONF_SECTION_PERFORMANCE
611 DRI_CONF_ADAPTIVE_SYNC("true")
612 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
613 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
614 DRI_CONF_VK_X11_ENSURE_MIN_IMAGE_COUNT("false")
615 DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING("false")
616 DRI_CONF_RADV_ENABLE_MRT_OUTPUT_NAN_FIXUP("false")
617 DRI_CONF_RADV_NO_DYNAMIC_BOUNDS("false")
618 DRI_CONF_RADV_OVERRIDE_UNIFORM_OFFSET_ALIGNMENT(0)
619 DRI_CONF_SECTION_END
620
621 DRI_CONF_SECTION_DEBUG
622 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
623 DRI_CONF_SECTION_END
624 DRI_CONF_END;
625
626 static void radv_init_dri_options(struct radv_instance *instance)
627 {
628 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
629 driParseConfigFiles(&instance->dri_options,
630 &instance->available_dri_options,
631 0, "radv", NULL,
632 instance->applicationName,
633 instance->applicationVersion,
634 instance->engineName,
635 instance->engineVersion);
636 }
637
638 VkResult radv_CreateInstance(
639 const VkInstanceCreateInfo* pCreateInfo,
640 const VkAllocationCallbacks* pAllocator,
641 VkInstance* pInstance)
642 {
643 struct radv_instance *instance;
644 VkResult result;
645
646 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
647 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
648 if (!instance)
649 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
650
651 vk_object_base_init(NULL, &instance->base, VK_OBJECT_TYPE_INSTANCE);
652
653 if (pAllocator)
654 instance->alloc = *pAllocator;
655 else
656 instance->alloc = default_alloc;
657
658 if (pCreateInfo->pApplicationInfo) {
659 const VkApplicationInfo *app = pCreateInfo->pApplicationInfo;
660
661 instance->applicationName =
662 vk_strdup(&instance->alloc, app->pApplicationName,
663 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
664 instance->applicationVersion = app->applicationVersion;
665
666 instance->engineName =
667 vk_strdup(&instance->alloc, app->pEngineName,
668 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
669 instance->engineVersion = app->engineVersion;
670 instance->apiVersion = app->apiVersion;
671 }
672
673 if (instance->apiVersion == 0)
674 instance->apiVersion = VK_API_VERSION_1_0;
675
676 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
677 radv_debug_options);
678
679 const char *radv_perftest_str = getenv("RADV_PERFTEST");
680 instance->perftest_flags = parse_debug_string(radv_perftest_str,
681 radv_perftest_options);
682
683 if (radv_perftest_str) {
684 /* Output warnings for famous RADV_PERFTEST options that no
685 * longer exist or are deprecated.
686 */
687 if (strstr(radv_perftest_str, "aco")) {
688 fprintf(stderr, "*******************************************************************************\n");
689 fprintf(stderr, "* WARNING: Unknown option RADV_PERFTEST='aco'. ACO is enabled by default now. *\n");
690 fprintf(stderr, "*******************************************************************************\n");
691 }
692 if (strstr(radv_perftest_str, "llvm")) {
693 fprintf(stderr, "*********************************************************************************\n");
694 fprintf(stderr, "* WARNING: Unknown option 'RADV_PERFTEST=llvm'. Did you mean 'RADV_DEBUG=llvm'? *\n");
695 fprintf(stderr, "*********************************************************************************\n");
696 abort();
697 }
698 }
699
700 if (instance->debug_flags & RADV_DEBUG_STARTUP)
701 radv_logi("Created an instance");
702
703 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
704 int idx;
705 for (idx = 0; idx < RADV_INSTANCE_EXTENSION_COUNT; idx++) {
706 if (!strcmp(pCreateInfo->ppEnabledExtensionNames[i],
707 radv_instance_extensions[idx].extensionName))
708 break;
709 }
710
711 if (idx >= RADV_INSTANCE_EXTENSION_COUNT ||
712 !radv_instance_extensions_supported.extensions[idx]) {
713 vk_object_base_finish(&instance->base);
714 vk_free2(&default_alloc, pAllocator, instance);
715 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
716 }
717
718 instance->enabled_extensions.extensions[idx] = true;
719 }
720
721 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
722
723 for (unsigned i = 0; i < ARRAY_SIZE(instance->dispatch.entrypoints); i++) {
724 /* Vulkan requires that entrypoints for extensions which have
725 * not been enabled must not be advertised.
726 */
727 if (!unchecked &&
728 !radv_instance_entrypoint_is_enabled(i, instance->apiVersion,
729 &instance->enabled_extensions)) {
730 instance->dispatch.entrypoints[i] = NULL;
731 } else {
732 instance->dispatch.entrypoints[i] =
733 radv_instance_dispatch_table.entrypoints[i];
734 }
735 }
736
737 for (unsigned i = 0; i < ARRAY_SIZE(instance->physical_device_dispatch.entrypoints); i++) {
738 /* Vulkan requires that entrypoints for extensions which have
739 * not been enabled must not be advertised.
740 */
741 if (!unchecked &&
742 !radv_physical_device_entrypoint_is_enabled(i, instance->apiVersion,
743 &instance->enabled_extensions)) {
744 instance->physical_device_dispatch.entrypoints[i] = NULL;
745 } else {
746 instance->physical_device_dispatch.entrypoints[i] =
747 radv_physical_device_dispatch_table.entrypoints[i];
748 }
749 }
750
751 for (unsigned i = 0; i < ARRAY_SIZE(instance->device_dispatch.entrypoints); i++) {
752 /* Vulkan requires that entrypoints for extensions which have
753 * not been enabled must not be advertised.
754 */
755 if (!unchecked &&
756 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
757 &instance->enabled_extensions, NULL)) {
758 instance->device_dispatch.entrypoints[i] = NULL;
759 } else {
760 instance->device_dispatch.entrypoints[i] =
761 radv_device_dispatch_table.entrypoints[i];
762 }
763 }
764
765 instance->physical_devices_enumerated = false;
766 list_inithead(&instance->physical_devices);
767
768 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
769 if (result != VK_SUCCESS) {
770 vk_object_base_finish(&instance->base);
771 vk_free2(&default_alloc, pAllocator, instance);
772 return vk_error(instance, result);
773 }
774
775 glsl_type_singleton_init_or_ref();
776
777 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
778
779 radv_init_dri_options(instance);
780 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
781
782 *pInstance = radv_instance_to_handle(instance);
783
784 return VK_SUCCESS;
785 }
786
787 void radv_DestroyInstance(
788 VkInstance _instance,
789 const VkAllocationCallbacks* pAllocator)
790 {
791 RADV_FROM_HANDLE(radv_instance, instance, _instance);
792
793 if (!instance)
794 return;
795
796 list_for_each_entry_safe(struct radv_physical_device, pdevice,
797 &instance->physical_devices, link) {
798 radv_physical_device_destroy(pdevice);
799 }
800
801 vk_free(&instance->alloc, instance->engineName);
802 vk_free(&instance->alloc, instance->applicationName);
803
804 VG(VALGRIND_DESTROY_MEMPOOL(instance));
805
806 glsl_type_singleton_decref();
807
808 driDestroyOptionCache(&instance->dri_options);
809 driDestroyOptionInfo(&instance->available_dri_options);
810
811 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
812
813 vk_object_base_finish(&instance->base);
814 vk_free(&instance->alloc, instance);
815 }
816
817 static VkResult
818 radv_enumerate_physical_devices(struct radv_instance *instance)
819 {
820 if (instance->physical_devices_enumerated)
821 return VK_SUCCESS;
822
823 instance->physical_devices_enumerated = true;
824
825 /* TODO: Check for more devices ? */
826 drmDevicePtr devices[8];
827 VkResult result = VK_SUCCESS;
828 int max_devices;
829
830 if (getenv("RADV_FORCE_FAMILY")) {
831 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
832 * device that allows to test the compiler without having an
833 * AMDGPU instance.
834 */
835 struct radv_physical_device *pdevice;
836
837 result = radv_physical_device_try_create(instance, NULL, &pdevice);
838 if (result != VK_SUCCESS)
839 return result;
840
841 list_addtail(&pdevice->link, &instance->physical_devices);
842 return VK_SUCCESS;
843 }
844
845 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
846
847 if (instance->debug_flags & RADV_DEBUG_STARTUP)
848 radv_logi("Found %d drm nodes", max_devices);
849
850 if (max_devices < 1)
851 return vk_error(instance, VK_SUCCESS);
852
853 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
854 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
855 devices[i]->bustype == DRM_BUS_PCI &&
856 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
857
858 struct radv_physical_device *pdevice;
859 result = radv_physical_device_try_create(instance, devices[i],
860 &pdevice);
861 /* Incompatible DRM device, skip. */
862 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
863 result = VK_SUCCESS;
864 continue;
865 }
866
867 /* Error creating the physical device, report the error. */
868 if (result != VK_SUCCESS)
869 break;
870
871 list_addtail(&pdevice->link, &instance->physical_devices);
872 }
873 }
874 drmFreeDevices(devices, max_devices);
875
876 /* If we successfully enumerated any devices, call it success */
877 return result;
878 }
879
880 VkResult radv_EnumeratePhysicalDevices(
881 VkInstance _instance,
882 uint32_t* pPhysicalDeviceCount,
883 VkPhysicalDevice* pPhysicalDevices)
884 {
885 RADV_FROM_HANDLE(radv_instance, instance, _instance);
886 VK_OUTARRAY_MAKE(out, pPhysicalDevices, pPhysicalDeviceCount);
887
888 VkResult result = radv_enumerate_physical_devices(instance);
889 if (result != VK_SUCCESS)
890 return result;
891
892 list_for_each_entry(struct radv_physical_device, pdevice,
893 &instance->physical_devices, link) {
894 vk_outarray_append(&out, i) {
895 *i = radv_physical_device_to_handle(pdevice);
896 }
897 }
898
899 return vk_outarray_status(&out);
900 }
901
902 VkResult radv_EnumeratePhysicalDeviceGroups(
903 VkInstance _instance,
904 uint32_t* pPhysicalDeviceGroupCount,
905 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
906 {
907 RADV_FROM_HANDLE(radv_instance, instance, _instance);
908 VK_OUTARRAY_MAKE(out, pPhysicalDeviceGroupProperties,
909 pPhysicalDeviceGroupCount);
910
911 VkResult result = radv_enumerate_physical_devices(instance);
912 if (result != VK_SUCCESS)
913 return result;
914
915 list_for_each_entry(struct radv_physical_device, pdevice,
916 &instance->physical_devices, link) {
917 vk_outarray_append(&out, p) {
918 p->physicalDeviceCount = 1;
919 memset(p->physicalDevices, 0, sizeof(p->physicalDevices));
920 p->physicalDevices[0] = radv_physical_device_to_handle(pdevice);
921 p->subsetAllocation = false;
922 }
923 }
924
925 return vk_outarray_status(&out);
926 }
927
928 void radv_GetPhysicalDeviceFeatures(
929 VkPhysicalDevice physicalDevice,
930 VkPhysicalDeviceFeatures* pFeatures)
931 {
932 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
933 memset(pFeatures, 0, sizeof(*pFeatures));
934
935 *pFeatures = (VkPhysicalDeviceFeatures) {
936 .robustBufferAccess = true,
937 .fullDrawIndexUint32 = true,
938 .imageCubeArray = true,
939 .independentBlend = true,
940 .geometryShader = true,
941 .tessellationShader = true,
942 .sampleRateShading = true,
943 .dualSrcBlend = true,
944 .logicOp = true,
945 .multiDrawIndirect = true,
946 .drawIndirectFirstInstance = true,
947 .depthClamp = true,
948 .depthBiasClamp = true,
949 .fillModeNonSolid = true,
950 .depthBounds = true,
951 .wideLines = true,
952 .largePoints = true,
953 .alphaToOne = true,
954 .multiViewport = true,
955 .samplerAnisotropy = true,
956 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
957 .textureCompressionASTC_LDR = false,
958 .textureCompressionBC = true,
959 .occlusionQueryPrecise = true,
960 .pipelineStatisticsQuery = true,
961 .vertexPipelineStoresAndAtomics = true,
962 .fragmentStoresAndAtomics = true,
963 .shaderTessellationAndGeometryPointSize = true,
964 .shaderImageGatherExtended = true,
965 .shaderStorageImageExtendedFormats = true,
966 .shaderStorageImageMultisample = true,
967 .shaderUniformBufferArrayDynamicIndexing = true,
968 .shaderSampledImageArrayDynamicIndexing = true,
969 .shaderStorageBufferArrayDynamicIndexing = true,
970 .shaderStorageImageArrayDynamicIndexing = true,
971 .shaderStorageImageReadWithoutFormat = true,
972 .shaderStorageImageWriteWithoutFormat = true,
973 .shaderClipDistance = true,
974 .shaderCullDistance = true,
975 .shaderFloat64 = true,
976 .shaderInt64 = true,
977 .shaderInt16 = true,
978 .sparseBinding = true,
979 .variableMultisampleRate = true,
980 .shaderResourceMinLod = true,
981 .inheritedQueries = true,
982 };
983 }
984
985 static void
986 radv_get_physical_device_features_1_1(struct radv_physical_device *pdevice,
987 VkPhysicalDeviceVulkan11Features *f)
988 {
989 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES);
990
991 f->storageBuffer16BitAccess = true;
992 f->uniformAndStorageBuffer16BitAccess = true;
993 f->storagePushConstant16 = true;
994 f->storageInputOutput16 = pdevice->rad_info.has_packed_math_16bit && (LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm);
995 f->multiview = true;
996 f->multiviewGeometryShader = true;
997 f->multiviewTessellationShader = true;
998 f->variablePointersStorageBuffer = true;
999 f->variablePointers = true;
1000 f->protectedMemory = false;
1001 f->samplerYcbcrConversion = true;
1002 f->shaderDrawParameters = true;
1003 }
1004
1005 static void
1006 radv_get_physical_device_features_1_2(struct radv_physical_device *pdevice,
1007 VkPhysicalDeviceVulkan12Features *f)
1008 {
1009 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES);
1010
1011 f->samplerMirrorClampToEdge = true;
1012 f->drawIndirectCount = true;
1013 f->storageBuffer8BitAccess = true;
1014 f->uniformAndStorageBuffer8BitAccess = true;
1015 f->storagePushConstant8 = true;
1016 f->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1017 f->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1018 f->shaderFloat16 = pdevice->rad_info.has_packed_math_16bit;
1019 f->shaderInt8 = true;
1020
1021 f->descriptorIndexing = true;
1022 f->shaderInputAttachmentArrayDynamicIndexing = true;
1023 f->shaderUniformTexelBufferArrayDynamicIndexing = true;
1024 f->shaderStorageTexelBufferArrayDynamicIndexing = true;
1025 f->shaderUniformBufferArrayNonUniformIndexing = true;
1026 f->shaderSampledImageArrayNonUniformIndexing = true;
1027 f->shaderStorageBufferArrayNonUniformIndexing = true;
1028 f->shaderStorageImageArrayNonUniformIndexing = true;
1029 f->shaderInputAttachmentArrayNonUniformIndexing = true;
1030 f->shaderUniformTexelBufferArrayNonUniformIndexing = true;
1031 f->shaderStorageTexelBufferArrayNonUniformIndexing = true;
1032 f->descriptorBindingUniformBufferUpdateAfterBind = true;
1033 f->descriptorBindingSampledImageUpdateAfterBind = true;
1034 f->descriptorBindingStorageImageUpdateAfterBind = true;
1035 f->descriptorBindingStorageBufferUpdateAfterBind = true;
1036 f->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
1037 f->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
1038 f->descriptorBindingUpdateUnusedWhilePending = true;
1039 f->descriptorBindingPartiallyBound = true;
1040 f->descriptorBindingVariableDescriptorCount = true;
1041 f->runtimeDescriptorArray = true;
1042
1043 f->samplerFilterMinmax = true;
1044 f->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
1045 f->imagelessFramebuffer = true;
1046 f->uniformBufferStandardLayout = true;
1047 f->shaderSubgroupExtendedTypes = true;
1048 f->separateDepthStencilLayouts = true;
1049 f->hostQueryReset = true;
1050 f->timelineSemaphore = pdevice->rad_info.has_syncobj_wait_for_submit;
1051 f->bufferDeviceAddress = true;
1052 f->bufferDeviceAddressCaptureReplay = false;
1053 f->bufferDeviceAddressMultiDevice = false;
1054 f->vulkanMemoryModel = true;
1055 f->vulkanMemoryModelDeviceScope = true;
1056 f->vulkanMemoryModelAvailabilityVisibilityChains = false;
1057 f->shaderOutputViewportIndex = true;
1058 f->shaderOutputLayer = true;
1059 f->subgroupBroadcastDynamicId = true;
1060 }
1061
1062 void radv_GetPhysicalDeviceFeatures2(
1063 VkPhysicalDevice physicalDevice,
1064 VkPhysicalDeviceFeatures2 *pFeatures)
1065 {
1066 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1067 radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1068
1069 VkPhysicalDeviceVulkan11Features core_1_1 = {
1070 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES,
1071 };
1072 radv_get_physical_device_features_1_1(pdevice, &core_1_1);
1073
1074 VkPhysicalDeviceVulkan12Features core_1_2 = {
1075 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES,
1076 };
1077 radv_get_physical_device_features_1_2(pdevice, &core_1_2);
1078
1079 #define CORE_FEATURE(major, minor, feature) \
1080 features->feature = core_##major##_##minor.feature
1081
1082 vk_foreach_struct(ext, pFeatures->pNext) {
1083 switch (ext->sType) {
1084 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
1085 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
1086 CORE_FEATURE(1, 1, variablePointersStorageBuffer);
1087 CORE_FEATURE(1, 1, variablePointers);
1088 break;
1089 }
1090 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
1091 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
1092 CORE_FEATURE(1, 1, multiview);
1093 CORE_FEATURE(1, 1, multiviewGeometryShader);
1094 CORE_FEATURE(1, 1, multiviewTessellationShader);
1095 break;
1096 }
1097 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
1098 VkPhysicalDeviceShaderDrawParametersFeatures *features =
1099 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
1100 CORE_FEATURE(1, 1, shaderDrawParameters);
1101 break;
1102 }
1103 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
1104 VkPhysicalDeviceProtectedMemoryFeatures *features =
1105 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
1106 CORE_FEATURE(1, 1, protectedMemory);
1107 break;
1108 }
1109 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
1110 VkPhysicalDevice16BitStorageFeatures *features =
1111 (VkPhysicalDevice16BitStorageFeatures*)ext;
1112 CORE_FEATURE(1, 1, storageBuffer16BitAccess);
1113 CORE_FEATURE(1, 1, uniformAndStorageBuffer16BitAccess);
1114 CORE_FEATURE(1, 1, storagePushConstant16);
1115 CORE_FEATURE(1, 1, storageInputOutput16);
1116 break;
1117 }
1118 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
1119 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
1120 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
1121 CORE_FEATURE(1, 1, samplerYcbcrConversion);
1122 break;
1123 }
1124 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES: {
1125 VkPhysicalDeviceDescriptorIndexingFeatures *features =
1126 (VkPhysicalDeviceDescriptorIndexingFeatures*)ext;
1127 CORE_FEATURE(1, 2, shaderInputAttachmentArrayDynamicIndexing);
1128 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayDynamicIndexing);
1129 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayDynamicIndexing);
1130 CORE_FEATURE(1, 2, shaderUniformBufferArrayNonUniformIndexing);
1131 CORE_FEATURE(1, 2, shaderSampledImageArrayNonUniformIndexing);
1132 CORE_FEATURE(1, 2, shaderStorageBufferArrayNonUniformIndexing);
1133 CORE_FEATURE(1, 2, shaderStorageImageArrayNonUniformIndexing);
1134 CORE_FEATURE(1, 2, shaderInputAttachmentArrayNonUniformIndexing);
1135 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayNonUniformIndexing);
1136 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayNonUniformIndexing);
1137 CORE_FEATURE(1, 2, descriptorBindingUniformBufferUpdateAfterBind);
1138 CORE_FEATURE(1, 2, descriptorBindingSampledImageUpdateAfterBind);
1139 CORE_FEATURE(1, 2, descriptorBindingStorageImageUpdateAfterBind);
1140 CORE_FEATURE(1, 2, descriptorBindingStorageBufferUpdateAfterBind);
1141 CORE_FEATURE(1, 2, descriptorBindingUniformTexelBufferUpdateAfterBind);
1142 CORE_FEATURE(1, 2, descriptorBindingStorageTexelBufferUpdateAfterBind);
1143 CORE_FEATURE(1, 2, descriptorBindingUpdateUnusedWhilePending);
1144 CORE_FEATURE(1, 2, descriptorBindingPartiallyBound);
1145 CORE_FEATURE(1, 2, descriptorBindingVariableDescriptorCount);
1146 CORE_FEATURE(1, 2, runtimeDescriptorArray);
1147 break;
1148 }
1149 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
1150 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
1151 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
1152 features->conditionalRendering = true;
1153 features->inheritedConditionalRendering = false;
1154 break;
1155 }
1156 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
1157 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
1158 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
1159 features->vertexAttributeInstanceRateDivisor = true;
1160 features->vertexAttributeInstanceRateZeroDivisor = true;
1161 break;
1162 }
1163 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
1164 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
1165 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
1166 features->transformFeedback = true;
1167 features->geometryStreams = !pdevice->use_ngg_streamout;
1168 break;
1169 }
1170 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES: {
1171 VkPhysicalDeviceScalarBlockLayoutFeatures *features =
1172 (VkPhysicalDeviceScalarBlockLayoutFeatures *)ext;
1173 CORE_FEATURE(1, 2, scalarBlockLayout);
1174 break;
1175 }
1176 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
1177 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
1178 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
1179 features->memoryPriority = true;
1180 break;
1181 }
1182 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
1183 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
1184 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
1185 features->bufferDeviceAddress = true;
1186 features->bufferDeviceAddressCaptureReplay = false;
1187 features->bufferDeviceAddressMultiDevice = false;
1188 break;
1189 }
1190 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES: {
1191 VkPhysicalDeviceBufferDeviceAddressFeatures *features =
1192 (VkPhysicalDeviceBufferDeviceAddressFeatures *)ext;
1193 CORE_FEATURE(1, 2, bufferDeviceAddress);
1194 CORE_FEATURE(1, 2, bufferDeviceAddressCaptureReplay);
1195 CORE_FEATURE(1, 2, bufferDeviceAddressMultiDevice);
1196 break;
1197 }
1198 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
1199 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
1200 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
1201 features->depthClipEnable = true;
1202 break;
1203 }
1204 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES: {
1205 VkPhysicalDeviceHostQueryResetFeatures *features =
1206 (VkPhysicalDeviceHostQueryResetFeatures *)ext;
1207 CORE_FEATURE(1, 2, hostQueryReset);
1208 break;
1209 }
1210 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES: {
1211 VkPhysicalDevice8BitStorageFeatures *features =
1212 (VkPhysicalDevice8BitStorageFeatures *)ext;
1213 CORE_FEATURE(1, 2, storageBuffer8BitAccess);
1214 CORE_FEATURE(1, 2, uniformAndStorageBuffer8BitAccess);
1215 CORE_FEATURE(1, 2, storagePushConstant8);
1216 break;
1217 }
1218 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES: {
1219 VkPhysicalDeviceShaderFloat16Int8Features *features =
1220 (VkPhysicalDeviceShaderFloat16Int8Features*)ext;
1221 CORE_FEATURE(1, 2, shaderFloat16);
1222 CORE_FEATURE(1, 2, shaderInt8);
1223 break;
1224 }
1225 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES: {
1226 VkPhysicalDeviceShaderAtomicInt64Features *features =
1227 (VkPhysicalDeviceShaderAtomicInt64Features *)ext;
1228 CORE_FEATURE(1, 2, shaderBufferInt64Atomics);
1229 CORE_FEATURE(1, 2, shaderSharedInt64Atomics);
1230 break;
1231 }
1232 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
1233 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
1234 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
1235 features->shaderDemoteToHelperInvocation = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1236 break;
1237 }
1238 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
1239 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
1240 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
1241
1242 features->inlineUniformBlock = true;
1243 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1244 break;
1245 }
1246 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1247 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1248 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1249 features->computeDerivativeGroupQuads = false;
1250 features->computeDerivativeGroupLinear = true;
1251 break;
1252 }
1253 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1254 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1255 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1256 features->ycbcrImageArrays = true;
1257 break;
1258 }
1259 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES: {
1260 VkPhysicalDeviceUniformBufferStandardLayoutFeatures *features =
1261 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures *)ext;
1262 CORE_FEATURE(1, 2, uniformBufferStandardLayout);
1263 break;
1264 }
1265 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1266 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1267 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1268 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1269 break;
1270 }
1271 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES: {
1272 VkPhysicalDeviceImagelessFramebufferFeatures *features =
1273 (VkPhysicalDeviceImagelessFramebufferFeatures *)ext;
1274 CORE_FEATURE(1, 2, imagelessFramebuffer);
1275 break;
1276 }
1277 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1278 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1279 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1280 features->pipelineExecutableInfo = true;
1281 break;
1282 }
1283 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR: {
1284 VkPhysicalDeviceShaderClockFeaturesKHR *features =
1285 (VkPhysicalDeviceShaderClockFeaturesKHR *)ext;
1286 features->shaderSubgroupClock = true;
1287 features->shaderDeviceClock = pdevice->rad_info.chip_class >= GFX8;
1288 break;
1289 }
1290 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
1291 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
1292 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
1293 features->texelBufferAlignment = true;
1294 break;
1295 }
1296 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES: {
1297 VkPhysicalDeviceTimelineSemaphoreFeatures *features =
1298 (VkPhysicalDeviceTimelineSemaphoreFeatures *) ext;
1299 CORE_FEATURE(1, 2, timelineSemaphore);
1300 break;
1301 }
1302 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT: {
1303 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *features =
1304 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *)ext;
1305 features->subgroupSizeControl = true;
1306 features->computeFullSubgroups = true;
1307 break;
1308 }
1309 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD: {
1310 VkPhysicalDeviceCoherentMemoryFeaturesAMD *features =
1311 (VkPhysicalDeviceCoherentMemoryFeaturesAMD *)ext;
1312 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1313 break;
1314 }
1315 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES: {
1316 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *features =
1317 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *)ext;
1318 CORE_FEATURE(1, 2, shaderSubgroupExtendedTypes);
1319 break;
1320 }
1321 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR: {
1322 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *features =
1323 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *)ext;
1324 CORE_FEATURE(1, 2, separateDepthStencilLayouts);
1325 break;
1326 }
1327 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES: {
1328 radv_get_physical_device_features_1_1(pdevice, (void *)ext);
1329 break;
1330 }
1331 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES: {
1332 radv_get_physical_device_features_1_2(pdevice, (void *)ext);
1333 break;
1334 }
1335 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT: {
1336 VkPhysicalDeviceLineRasterizationFeaturesEXT *features =
1337 (VkPhysicalDeviceLineRasterizationFeaturesEXT *)ext;
1338 features->rectangularLines = false;
1339 features->bresenhamLines = true;
1340 features->smoothLines = false;
1341 features->stippledRectangularLines = false;
1342 features->stippledBresenhamLines = true;
1343 features->stippledSmoothLines = false;
1344 break;
1345 }
1346 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
1347 VkDeviceMemoryOverallocationCreateInfoAMD *features =
1348 (VkDeviceMemoryOverallocationCreateInfoAMD *)ext;
1349 features->overallocationBehavior = true;
1350 break;
1351 }
1352 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_FEATURES_EXT: {
1353 VkPhysicalDeviceRobustness2FeaturesEXT *features =
1354 (VkPhysicalDeviceRobustness2FeaturesEXT *)ext;
1355 features->robustBufferAccess2 = true;
1356 features->robustImageAccess2 = true;
1357 features->nullDescriptor = true;
1358 break;
1359 }
1360 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
1361 VkPhysicalDeviceCustomBorderColorFeaturesEXT *features =
1362 (VkPhysicalDeviceCustomBorderColorFeaturesEXT *)ext;
1363 features->customBorderColors = true;
1364 features->customBorderColorWithoutFormat = true;
1365 break;
1366 }
1367 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PRIVATE_DATA_FEATURES_EXT: {
1368 VkPhysicalDevicePrivateDataFeaturesEXT *features =
1369 (VkPhysicalDevicePrivateDataFeaturesEXT *)ext;
1370 features->privateData = true;
1371 break;
1372 }
1373 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_CREATION_CACHE_CONTROL_FEATURES_EXT: {
1374 VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *features =
1375 (VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *)ext;
1376 features-> pipelineCreationCacheControl = true;
1377 break;
1378 }
1379 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_MEMORY_MODEL_FEATURES_KHR: {
1380 VkPhysicalDeviceVulkanMemoryModelFeaturesKHR *features =
1381 (VkPhysicalDeviceVulkanMemoryModelFeaturesKHR *)ext;
1382 CORE_FEATURE(1, 2, vulkanMemoryModel);
1383 CORE_FEATURE(1, 2, vulkanMemoryModelDeviceScope);
1384 CORE_FEATURE(1, 2, vulkanMemoryModelAvailabilityVisibilityChains);
1385 break;
1386 }
1387 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTENDED_DYNAMIC_STATE_FEATURES_EXT: {
1388 VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *features =
1389 (VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *) ext;
1390 features->extendedDynamicState = true;
1391 break;
1392 }
1393 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_ROBUSTNESS_FEATURES_EXT: {
1394 VkPhysicalDeviceImageRobustnessFeaturesEXT *features =
1395 (VkPhysicalDeviceImageRobustnessFeaturesEXT *)ext;
1396 features->robustImageAccess = true;
1397 break;
1398 }
1399 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_FLOAT_FEATURES_EXT: {
1400 VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *features =
1401 (VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *)ext;
1402 features->shaderBufferFloat32Atomics = true;
1403 features->shaderBufferFloat32AtomicAdd = false;
1404 features->shaderBufferFloat64Atomics = true;
1405 features->shaderBufferFloat64AtomicAdd = false;
1406 features->shaderSharedFloat32Atomics = true;
1407 features->shaderSharedFloat32AtomicAdd = pdevice->rad_info.chip_class >= GFX8 &&
1408 (!pdevice->use_llvm || LLVM_VERSION_MAJOR >= 10);
1409 features->shaderSharedFloat64Atomics = true;
1410 features->shaderSharedFloat64AtomicAdd = false;
1411 features->shaderImageFloat32Atomics = true;
1412 features->shaderImageFloat32AtomicAdd = false;
1413 features->sparseImageFloat32Atomics = false;
1414 features->sparseImageFloat32AtomicAdd = false;
1415 break;
1416 }
1417 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_4444_FORMATS_FEATURES_EXT: {
1418 VkPhysicalDevice4444FormatsFeaturesEXT *features =
1419 (VkPhysicalDevice4444FormatsFeaturesEXT *)ext;
1420 features->formatA4R4G4B4 = true;
1421 features->formatA4B4G4R4 = true;
1422 break;
1423 }
1424 default:
1425 break;
1426 }
1427 }
1428 #undef CORE_FEATURE
1429 }
1430
1431 static size_t
1432 radv_max_descriptor_set_size()
1433 {
1434 /* make sure that the entire descriptor set is addressable with a signed
1435 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1436 * be at most 2 GiB. the combined image & samples object count as one of
1437 * both. This limit is for the pipeline layout, not for the set layout, but
1438 * there is no set limit, so we just set a pipeline limit. I don't think
1439 * any app is going to hit this soon. */
1440 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1441 - MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1442 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1443 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1444 32 /* sampler, largest when combined with image */ +
1445 64 /* sampled image */ +
1446 64 /* storage image */);
1447 }
1448
1449 static uint32_t
1450 radv_uniform_buffer_offset_alignment(const struct radv_physical_device *pdevice)
1451 {
1452 uint32_t uniform_offset_alignment = driQueryOptioni(&pdevice->instance->dri_options,
1453 "radv_override_uniform_offset_alignment");
1454 if (!util_is_power_of_two_or_zero(uniform_offset_alignment)) {
1455 fprintf(stderr, "ERROR: invalid radv_override_uniform_offset_alignment setting %d:"
1456 "not a power of two\n", uniform_offset_alignment);
1457 uniform_offset_alignment = 0;
1458 }
1459
1460 /* Take at least the hardware limit. */
1461 return MAX2(uniform_offset_alignment, 4);
1462 }
1463
1464 void radv_GetPhysicalDeviceProperties(
1465 VkPhysicalDevice physicalDevice,
1466 VkPhysicalDeviceProperties* pProperties)
1467 {
1468 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1469 VkSampleCountFlags sample_counts = 0xf;
1470
1471 size_t max_descriptor_set_size = radv_max_descriptor_set_size();
1472
1473 VkPhysicalDeviceLimits limits = {
1474 .maxImageDimension1D = (1 << 14),
1475 .maxImageDimension2D = (1 << 14),
1476 .maxImageDimension3D = (1 << 11),
1477 .maxImageDimensionCube = (1 << 14),
1478 .maxImageArrayLayers = (1 << 11),
1479 .maxTexelBufferElements = UINT32_MAX,
1480 .maxUniformBufferRange = UINT32_MAX,
1481 .maxStorageBufferRange = UINT32_MAX,
1482 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1483 .maxMemoryAllocationCount = UINT32_MAX,
1484 .maxSamplerAllocationCount = 64 * 1024,
1485 .bufferImageGranularity = 64, /* A cache line */
1486 .sparseAddressSpaceSize = RADV_MAX_MEMORY_ALLOCATION_SIZE, /* buffer max size */
1487 .maxBoundDescriptorSets = MAX_SETS,
1488 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1489 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1490 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1491 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1492 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1493 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1494 .maxPerStageResources = max_descriptor_set_size,
1495 .maxDescriptorSetSamplers = max_descriptor_set_size,
1496 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1497 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1498 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1499 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1500 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1501 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1502 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1503 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1504 .maxVertexInputBindings = MAX_VBS,
1505 .maxVertexInputAttributeOffset = 2047,
1506 .maxVertexInputBindingStride = 2048,
1507 .maxVertexOutputComponents = 128,
1508 .maxTessellationGenerationLevel = 64,
1509 .maxTessellationPatchSize = 32,
1510 .maxTessellationControlPerVertexInputComponents = 128,
1511 .maxTessellationControlPerVertexOutputComponents = 128,
1512 .maxTessellationControlPerPatchOutputComponents = 120,
1513 .maxTessellationControlTotalOutputComponents = 4096,
1514 .maxTessellationEvaluationInputComponents = 128,
1515 .maxTessellationEvaluationOutputComponents = 128,
1516 .maxGeometryShaderInvocations = 127,
1517 .maxGeometryInputComponents = 64,
1518 .maxGeometryOutputComponents = 128,
1519 .maxGeometryOutputVertices = 256,
1520 .maxGeometryTotalOutputComponents = 1024,
1521 .maxFragmentInputComponents = 128,
1522 .maxFragmentOutputAttachments = 8,
1523 .maxFragmentDualSrcAttachments = 1,
1524 .maxFragmentCombinedOutputResources = 8,
1525 .maxComputeSharedMemorySize = 32768,
1526 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1527 .maxComputeWorkGroupInvocations = 1024,
1528 .maxComputeWorkGroupSize = {
1529 1024,
1530 1024,
1531 1024
1532 },
1533 .subPixelPrecisionBits = 8,
1534 .subTexelPrecisionBits = 8,
1535 .mipmapPrecisionBits = 8,
1536 .maxDrawIndexedIndexValue = UINT32_MAX,
1537 .maxDrawIndirectCount = UINT32_MAX,
1538 .maxSamplerLodBias = 16,
1539 .maxSamplerAnisotropy = 16,
1540 .maxViewports = MAX_VIEWPORTS,
1541 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1542 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1543 .viewportSubPixelBits = 8,
1544 .minMemoryMapAlignment = 4096, /* A page */
1545 .minTexelBufferOffsetAlignment = 4,
1546 .minUniformBufferOffsetAlignment = radv_uniform_buffer_offset_alignment(pdevice),
1547 .minStorageBufferOffsetAlignment = 4,
1548 .minTexelOffset = -32,
1549 .maxTexelOffset = 31,
1550 .minTexelGatherOffset = -32,
1551 .maxTexelGatherOffset = 31,
1552 .minInterpolationOffset = -2,
1553 .maxInterpolationOffset = 2,
1554 .subPixelInterpolationOffsetBits = 8,
1555 .maxFramebufferWidth = (1 << 14),
1556 .maxFramebufferHeight = (1 << 14),
1557 .maxFramebufferLayers = (1 << 10),
1558 .framebufferColorSampleCounts = sample_counts,
1559 .framebufferDepthSampleCounts = sample_counts,
1560 .framebufferStencilSampleCounts = sample_counts,
1561 .framebufferNoAttachmentsSampleCounts = sample_counts,
1562 .maxColorAttachments = MAX_RTS,
1563 .sampledImageColorSampleCounts = sample_counts,
1564 .sampledImageIntegerSampleCounts = sample_counts,
1565 .sampledImageDepthSampleCounts = sample_counts,
1566 .sampledImageStencilSampleCounts = sample_counts,
1567 .storageImageSampleCounts = sample_counts,
1568 .maxSampleMaskWords = 1,
1569 .timestampComputeAndGraphics = true,
1570 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1571 .maxClipDistances = 8,
1572 .maxCullDistances = 8,
1573 .maxCombinedClipAndCullDistances = 8,
1574 .discreteQueuePriorities = 2,
1575 .pointSizeRange = { 0.0, 8191.875 },
1576 .lineWidthRange = { 0.0, 8191.875 },
1577 .pointSizeGranularity = (1.0 / 8.0),
1578 .lineWidthGranularity = (1.0 / 8.0),
1579 .strictLines = false, /* FINISHME */
1580 .standardSampleLocations = true,
1581 .optimalBufferCopyOffsetAlignment = 128,
1582 .optimalBufferCopyRowPitchAlignment = 128,
1583 .nonCoherentAtomSize = 64,
1584 };
1585
1586 *pProperties = (VkPhysicalDeviceProperties) {
1587 .apiVersion = radv_physical_device_api_version(pdevice),
1588 .driverVersion = vk_get_driver_version(),
1589 .vendorID = ATI_VENDOR_ID,
1590 .deviceID = pdevice->rad_info.pci_id,
1591 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1592 .limits = limits,
1593 .sparseProperties = {0},
1594 };
1595
1596 strcpy(pProperties->deviceName, pdevice->name);
1597 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1598 }
1599
1600 static void
1601 radv_get_physical_device_properties_1_1(struct radv_physical_device *pdevice,
1602 VkPhysicalDeviceVulkan11Properties *p)
1603 {
1604 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES);
1605
1606 memcpy(p->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1607 memcpy(p->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1608 memset(p->deviceLUID, 0, VK_LUID_SIZE);
1609 /* The LUID is for Windows. */
1610 p->deviceLUIDValid = false;
1611 p->deviceNodeMask = 0;
1612
1613 p->subgroupSize = RADV_SUBGROUP_SIZE;
1614 p->subgroupSupportedStages = VK_SHADER_STAGE_ALL_GRAPHICS |
1615 VK_SHADER_STAGE_COMPUTE_BIT;
1616 p->subgroupSupportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT |
1617 VK_SUBGROUP_FEATURE_VOTE_BIT |
1618 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1619 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1620 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1621 VK_SUBGROUP_FEATURE_QUAD_BIT |
1622 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1623 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1624 p->subgroupQuadOperationsInAllStages = true;
1625
1626 p->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1627 p->maxMultiviewViewCount = MAX_VIEWS;
1628 p->maxMultiviewInstanceIndex = INT_MAX;
1629 p->protectedNoFault = false;
1630 p->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
1631 p->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
1632 }
1633
1634 static void
1635 radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
1636 VkPhysicalDeviceVulkan12Properties *p)
1637 {
1638 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES);
1639
1640 p->driverID = VK_DRIVER_ID_MESA_RADV;
1641 snprintf(p->driverName, VK_MAX_DRIVER_NAME_SIZE, "radv");
1642 snprintf(p->driverInfo, VK_MAX_DRIVER_INFO_SIZE,
1643 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1 " (%s)",
1644 radv_get_compiler_string(pdevice));
1645 p->conformanceVersion = (VkConformanceVersion) {
1646 .major = 1,
1647 .minor = 2,
1648 .subminor = 0,
1649 .patch = 0,
1650 };
1651
1652 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1653 * controlled by the same config register.
1654 */
1655 if (pdevice->rad_info.has_packed_math_16bit) {
1656 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1657 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1658 } else {
1659 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1660 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1661 }
1662
1663 /* With LLVM, do not allow both preserving and flushing denorms because
1664 * different shaders in the same pipeline can have different settings and
1665 * this won't work for merged shaders. To make it work, this requires LLVM
1666 * support for changing the register. The same logic applies for the
1667 * rounding modes because they are configured with the same config
1668 * register.
1669 */
1670 p->shaderDenormFlushToZeroFloat32 = true;
1671 p->shaderDenormPreserveFloat32 = !pdevice->use_llvm;
1672 p->shaderRoundingModeRTEFloat32 = true;
1673 p->shaderRoundingModeRTZFloat32 = !pdevice->use_llvm;
1674 p->shaderSignedZeroInfNanPreserveFloat32 = true;
1675
1676 p->shaderDenormFlushToZeroFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1677 p->shaderDenormPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1678 p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.has_packed_math_16bit;
1679 p->shaderRoundingModeRTZFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1680 p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1681
1682 p->shaderDenormFlushToZeroFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1683 p->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1684 p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
1685 p->shaderRoundingModeRTZFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1686 p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1687
1688 p->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1689 p->shaderUniformBufferArrayNonUniformIndexingNative = false;
1690 p->shaderSampledImageArrayNonUniformIndexingNative = false;
1691 p->shaderStorageBufferArrayNonUniformIndexingNative = false;
1692 p->shaderStorageImageArrayNonUniformIndexingNative = false;
1693 p->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1694 p->robustBufferAccessUpdateAfterBind = false;
1695 p->quadDivergentImplicitLod = false;
1696
1697 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1698 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1699 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1700 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1701 32 /* sampler, largest when combined with image */ +
1702 64 /* sampled image */ +
1703 64 /* storage image */);
1704 p->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1705 p->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1706 p->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1707 p->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1708 p->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1709 p->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1710 p->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1711 p->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1712 p->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1713 p->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1714 p->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1715 p->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1716 p->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1717 p->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1718 p->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1719
1720 /* We support all of the depth resolve modes */
1721 p->supportedDepthResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1722 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1723 VK_RESOLVE_MODE_MIN_BIT_KHR |
1724 VK_RESOLVE_MODE_MAX_BIT_KHR;
1725
1726 /* Average doesn't make sense for stencil so we don't support that */
1727 p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1728 VK_RESOLVE_MODE_MIN_BIT_KHR |
1729 VK_RESOLVE_MODE_MAX_BIT_KHR;
1730
1731 p->independentResolveNone = true;
1732 p->independentResolve = true;
1733
1734 /* GFX6-8 only support single channel min/max filter. */
1735 p->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1736 p->filterMinmaxSingleComponentFormats = true;
1737
1738 p->maxTimelineSemaphoreValueDifference = UINT64_MAX;
1739
1740 p->framebufferIntegerColorSampleCounts = VK_SAMPLE_COUNT_1_BIT;
1741 }
1742
1743 void radv_GetPhysicalDeviceProperties2(
1744 VkPhysicalDevice physicalDevice,
1745 VkPhysicalDeviceProperties2 *pProperties)
1746 {
1747 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1748 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1749
1750 VkPhysicalDeviceVulkan11Properties core_1_1 = {
1751 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES,
1752 };
1753 radv_get_physical_device_properties_1_1(pdevice, &core_1_1);
1754
1755 VkPhysicalDeviceVulkan12Properties core_1_2 = {
1756 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES,
1757 };
1758 radv_get_physical_device_properties_1_2(pdevice, &core_1_2);
1759
1760 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1761 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1762 sizeof(core_##major##_##minor.core_property))
1763
1764 #define CORE_PROPERTY(major, minor, property) \
1765 CORE_RENAMED_PROPERTY(major, minor, property, property)
1766
1767 vk_foreach_struct(ext, pProperties->pNext) {
1768 switch (ext->sType) {
1769 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1770 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1771 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1772 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1773 break;
1774 }
1775 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1776 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1777 CORE_PROPERTY(1, 1, deviceUUID);
1778 CORE_PROPERTY(1, 1, driverUUID);
1779 CORE_PROPERTY(1, 1, deviceLUID);
1780 CORE_PROPERTY(1, 1, deviceLUIDValid);
1781 break;
1782 }
1783 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1784 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1785 CORE_PROPERTY(1, 1, maxMultiviewViewCount);
1786 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex);
1787 break;
1788 }
1789 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1790 VkPhysicalDevicePointClippingProperties *properties =
1791 (VkPhysicalDevicePointClippingProperties*)ext;
1792 CORE_PROPERTY(1, 1, pointClippingBehavior);
1793 break;
1794 }
1795 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1796 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1797 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1798 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1799 break;
1800 }
1801 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1802 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1803 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1804 properties->minImportedHostPointerAlignment = 4096;
1805 break;
1806 }
1807 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1808 VkPhysicalDeviceSubgroupProperties *properties =
1809 (VkPhysicalDeviceSubgroupProperties*)ext;
1810 CORE_PROPERTY(1, 1, subgroupSize);
1811 CORE_RENAMED_PROPERTY(1, 1, supportedStages,
1812 subgroupSupportedStages);
1813 CORE_RENAMED_PROPERTY(1, 1, supportedOperations,
1814 subgroupSupportedOperations);
1815 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages,
1816 subgroupQuadOperationsInAllStages);
1817 break;
1818 }
1819 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1820 VkPhysicalDeviceMaintenance3Properties *properties =
1821 (VkPhysicalDeviceMaintenance3Properties*)ext;
1822 CORE_PROPERTY(1, 1, maxPerSetDescriptors);
1823 CORE_PROPERTY(1, 1, maxMemoryAllocationSize);
1824 break;
1825 }
1826 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES: {
1827 VkPhysicalDeviceSamplerFilterMinmaxProperties *properties =
1828 (VkPhysicalDeviceSamplerFilterMinmaxProperties *)ext;
1829 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping);
1830 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats);
1831 break;
1832 }
1833 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1834 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1835 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1836
1837 /* Shader engines. */
1838 properties->shaderEngineCount =
1839 pdevice->rad_info.max_se;
1840 properties->shaderArraysPerEngineCount =
1841 pdevice->rad_info.max_sh_per_se;
1842 properties->computeUnitsPerShaderArray =
1843 pdevice->rad_info.min_good_cu_per_sa;
1844 properties->simdPerComputeUnit =
1845 pdevice->rad_info.num_simd_per_compute_unit;
1846 properties->wavefrontsPerSimd =
1847 pdevice->rad_info.max_wave64_per_simd;
1848 properties->wavefrontSize = 64;
1849
1850 /* SGPR. */
1851 properties->sgprsPerSimd =
1852 pdevice->rad_info.num_physical_sgprs_per_simd;
1853 properties->minSgprAllocation =
1854 pdevice->rad_info.min_sgpr_alloc;
1855 properties->maxSgprAllocation =
1856 pdevice->rad_info.max_sgpr_alloc;
1857 properties->sgprAllocationGranularity =
1858 pdevice->rad_info.sgpr_alloc_granularity;
1859
1860 /* VGPR. */
1861 properties->vgprsPerSimd =
1862 pdevice->rad_info.num_physical_wave64_vgprs_per_simd;
1863 properties->minVgprAllocation =
1864 pdevice->rad_info.min_wave64_vgpr_alloc;
1865 properties->maxVgprAllocation =
1866 pdevice->rad_info.max_vgpr_alloc;
1867 properties->vgprAllocationGranularity =
1868 pdevice->rad_info.wave64_vgpr_alloc_granularity;
1869 break;
1870 }
1871 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1872 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1873 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1874
1875 properties->shaderCoreFeatures = 0;
1876 properties->activeComputeUnitCount =
1877 pdevice->rad_info.num_good_compute_units;
1878 break;
1879 }
1880 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1881 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1882 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1883 properties->maxVertexAttribDivisor = UINT32_MAX;
1884 break;
1885 }
1886 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES: {
1887 VkPhysicalDeviceDescriptorIndexingProperties *properties =
1888 (VkPhysicalDeviceDescriptorIndexingProperties*)ext;
1889 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools);
1890 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative);
1891 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative);
1892 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative);
1893 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative);
1894 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative);
1895 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind);
1896 CORE_PROPERTY(1, 2, quadDivergentImplicitLod);
1897 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers);
1898 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers);
1899 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers);
1900 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages);
1901 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages);
1902 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments);
1903 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources);
1904 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers);
1905 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers);
1906 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic);
1907 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers);
1908 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic);
1909 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages);
1910 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages);
1911 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments);
1912 break;
1913 }
1914 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1915 VkPhysicalDeviceProtectedMemoryProperties *properties =
1916 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1917 CORE_PROPERTY(1, 1, protectedNoFault);
1918 break;
1919 }
1920 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1921 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1922 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1923 properties->primitiveOverestimationSize = 0;
1924 properties->maxExtraPrimitiveOverestimationSize = 0;
1925 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1926 properties->primitiveUnderestimation = false;
1927 properties->conservativePointAndLineRasterization = false;
1928 properties->degenerateTrianglesRasterized = false;
1929 properties->degenerateLinesRasterized = false;
1930 properties->fullyCoveredFragmentShaderInputVariable = false;
1931 properties->conservativeRasterizationPostDepthCoverage = false;
1932 break;
1933 }
1934 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1935 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1936 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1937 properties->pciDomain = pdevice->bus_info.domain;
1938 properties->pciBus = pdevice->bus_info.bus;
1939 properties->pciDevice = pdevice->bus_info.dev;
1940 properties->pciFunction = pdevice->bus_info.func;
1941 break;
1942 }
1943 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES: {
1944 VkPhysicalDeviceDriverProperties *properties =
1945 (VkPhysicalDeviceDriverProperties *) ext;
1946 CORE_PROPERTY(1, 2, driverID);
1947 CORE_PROPERTY(1, 2, driverName);
1948 CORE_PROPERTY(1, 2, driverInfo);
1949 CORE_PROPERTY(1, 2, conformanceVersion);
1950 break;
1951 }
1952 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1953 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1954 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1955 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1956 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1957 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1958 properties->maxTransformFeedbackStreamDataSize = 512;
1959 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1960 properties->maxTransformFeedbackBufferDataStride = 512;
1961 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1962 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1963 properties->transformFeedbackRasterizationStreamSelect = false;
1964 properties->transformFeedbackDraw = true;
1965 break;
1966 }
1967 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1968 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1969 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1970
1971 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1972 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1973 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1974 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1975 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1976 break;
1977 }
1978 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1979 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1980 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1981 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1982 VK_SAMPLE_COUNT_4_BIT |
1983 VK_SAMPLE_COUNT_8_BIT;
1984 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1985 properties->sampleLocationCoordinateRange[0] = 0.0f;
1986 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1987 properties->sampleLocationSubPixelBits = 4;
1988 properties->variableSampleLocations = false;
1989 break;
1990 }
1991 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES: {
1992 VkPhysicalDeviceDepthStencilResolveProperties *properties =
1993 (VkPhysicalDeviceDepthStencilResolveProperties *)ext;
1994 CORE_PROPERTY(1, 2, supportedDepthResolveModes);
1995 CORE_PROPERTY(1, 2, supportedStencilResolveModes);
1996 CORE_PROPERTY(1, 2, independentResolveNone);
1997 CORE_PROPERTY(1, 2, independentResolve);
1998 break;
1999 }
2000 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
2001 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *properties =
2002 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *)ext;
2003 properties->storageTexelBufferOffsetAlignmentBytes = 4;
2004 properties->storageTexelBufferOffsetSingleTexelAlignment = true;
2005 properties->uniformTexelBufferOffsetAlignmentBytes = 4;
2006 properties->uniformTexelBufferOffsetSingleTexelAlignment = true;
2007 break;
2008 }
2009 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES : {
2010 VkPhysicalDeviceFloatControlsProperties *properties =
2011 (VkPhysicalDeviceFloatControlsProperties *)ext;
2012 CORE_PROPERTY(1, 2, denormBehaviorIndependence);
2013 CORE_PROPERTY(1, 2, roundingModeIndependence);
2014 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16);
2015 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16);
2016 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16);
2017 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16);
2018 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16);
2019 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32);
2020 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32);
2021 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32);
2022 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32);
2023 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32);
2024 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64);
2025 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64);
2026 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64);
2027 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64);
2028 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64);
2029 break;
2030 }
2031 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES: {
2032 VkPhysicalDeviceTimelineSemaphoreProperties *properties =
2033 (VkPhysicalDeviceTimelineSemaphoreProperties *) ext;
2034 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference);
2035 break;
2036 }
2037 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT: {
2038 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *props =
2039 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *)ext;
2040 props->minSubgroupSize = 64;
2041 props->maxSubgroupSize = 64;
2042 props->maxComputeWorkgroupSubgroups = UINT32_MAX;
2043 props->requiredSubgroupSizeStages = 0;
2044
2045 if (pdevice->rad_info.chip_class >= GFX10) {
2046 /* Only GFX10+ supports wave32. */
2047 props->minSubgroupSize = 32;
2048 props->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT;
2049 }
2050 break;
2051 }
2052 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES:
2053 radv_get_physical_device_properties_1_1(pdevice, (void *)ext);
2054 break;
2055 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES:
2056 radv_get_physical_device_properties_1_2(pdevice, (void *)ext);
2057 break;
2058 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT: {
2059 VkPhysicalDeviceLineRasterizationPropertiesEXT *props =
2060 (VkPhysicalDeviceLineRasterizationPropertiesEXT *)ext;
2061 props->lineSubPixelPrecisionBits = 4;
2062 break;
2063 }
2064 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_PROPERTIES_EXT: {
2065 VkPhysicalDeviceRobustness2PropertiesEXT *properties =
2066 (VkPhysicalDeviceRobustness2PropertiesEXT *)ext;
2067 properties->robustStorageBufferAccessSizeAlignment = 4;
2068 properties->robustUniformBufferAccessSizeAlignment = 4;
2069 break;
2070 }
2071 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_PROPERTIES_EXT: {
2072 VkPhysicalDeviceCustomBorderColorPropertiesEXT *props =
2073 (VkPhysicalDeviceCustomBorderColorPropertiesEXT *)ext;
2074 props->maxCustomBorderColorSamplers = RADV_BORDER_COLOR_COUNT;
2075 break;
2076 }
2077 default:
2078 break;
2079 }
2080 }
2081 }
2082
2083 static void radv_get_physical_device_queue_family_properties(
2084 struct radv_physical_device* pdevice,
2085 uint32_t* pCount,
2086 VkQueueFamilyProperties** pQueueFamilyProperties)
2087 {
2088 int num_queue_families = 1;
2089 int idx;
2090 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2091 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
2092 num_queue_families++;
2093
2094 if (pQueueFamilyProperties == NULL) {
2095 *pCount = num_queue_families;
2096 return;
2097 }
2098
2099 if (!*pCount)
2100 return;
2101
2102 idx = 0;
2103 if (*pCount >= 1) {
2104 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2105 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
2106 VK_QUEUE_COMPUTE_BIT |
2107 VK_QUEUE_TRANSFER_BIT |
2108 VK_QUEUE_SPARSE_BINDING_BIT,
2109 .queueCount = 1,
2110 .timestampValidBits = 64,
2111 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2112 };
2113 idx++;
2114 }
2115
2116 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2117 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
2118 if (*pCount > idx) {
2119 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2120 .queueFlags = VK_QUEUE_COMPUTE_BIT |
2121 VK_QUEUE_TRANSFER_BIT |
2122 VK_QUEUE_SPARSE_BINDING_BIT,
2123 .queueCount = pdevice->rad_info.num_rings[RING_COMPUTE],
2124 .timestampValidBits = 64,
2125 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2126 };
2127 idx++;
2128 }
2129 }
2130 *pCount = idx;
2131 }
2132
2133 void radv_GetPhysicalDeviceQueueFamilyProperties(
2134 VkPhysicalDevice physicalDevice,
2135 uint32_t* pCount,
2136 VkQueueFamilyProperties* pQueueFamilyProperties)
2137 {
2138 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2139 if (!pQueueFamilyProperties) {
2140 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2141 return;
2142 }
2143 VkQueueFamilyProperties *properties[] = {
2144 pQueueFamilyProperties + 0,
2145 pQueueFamilyProperties + 1,
2146 pQueueFamilyProperties + 2,
2147 };
2148 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2149 assert(*pCount <= 3);
2150 }
2151
2152 void radv_GetPhysicalDeviceQueueFamilyProperties2(
2153 VkPhysicalDevice physicalDevice,
2154 uint32_t* pCount,
2155 VkQueueFamilyProperties2 *pQueueFamilyProperties)
2156 {
2157 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2158 if (!pQueueFamilyProperties) {
2159 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2160 return;
2161 }
2162 VkQueueFamilyProperties *properties[] = {
2163 &pQueueFamilyProperties[0].queueFamilyProperties,
2164 &pQueueFamilyProperties[1].queueFamilyProperties,
2165 &pQueueFamilyProperties[2].queueFamilyProperties,
2166 };
2167 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2168 assert(*pCount <= 3);
2169 }
2170
2171 void radv_GetPhysicalDeviceMemoryProperties(
2172 VkPhysicalDevice physicalDevice,
2173 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
2174 {
2175 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2176
2177 *pMemoryProperties = physical_device->memory_properties;
2178 }
2179
2180 static void
2181 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
2182 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
2183 {
2184 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2185 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
2186 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
2187 uint64_t vram_size = radv_get_vram_size(device);
2188 uint64_t gtt_size = device->rad_info.gart_size;
2189 uint64_t heap_budget, heap_usage;
2190
2191 /* For all memory heaps, the computation of budget is as follow:
2192 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2193 *
2194 * The Vulkan spec 1.1.97 says that the budget should include any
2195 * currently allocated device memory.
2196 *
2197 * Note that the application heap usages are not really accurate (eg.
2198 * in presence of shared buffers).
2199 */
2200 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
2201 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
2202
2203 if ((device->memory_domains[i] & RADEON_DOMAIN_VRAM) && (device->memory_flags[i] & RADEON_FLAG_NO_CPU_ACCESS)) {
2204 heap_usage = device->ws->query_value(device->ws,
2205 RADEON_ALLOCATED_VRAM);
2206
2207 heap_budget = vram_size -
2208 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
2209 heap_usage;
2210
2211 memoryBudget->heapBudget[heap_index] = heap_budget;
2212 memoryBudget->heapUsage[heap_index] = heap_usage;
2213 } else if (device->memory_domains[i] & RADEON_DOMAIN_VRAM) {
2214 heap_usage = device->ws->query_value(device->ws,
2215 RADEON_ALLOCATED_VRAM_VIS);
2216
2217 heap_budget = visible_vram_size -
2218 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
2219 heap_usage;
2220
2221 memoryBudget->heapBudget[heap_index] = heap_budget;
2222 memoryBudget->heapUsage[heap_index] = heap_usage;
2223 } else {
2224 assert(device->memory_domains[i] & RADEON_DOMAIN_GTT);
2225
2226 heap_usage = device->ws->query_value(device->ws,
2227 RADEON_ALLOCATED_GTT);
2228
2229 heap_budget = gtt_size -
2230 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
2231 heap_usage;
2232
2233 memoryBudget->heapBudget[heap_index] = heap_budget;
2234 memoryBudget->heapUsage[heap_index] = heap_usage;
2235 }
2236 }
2237
2238 /* The heapBudget and heapUsage values must be zero for array elements
2239 * greater than or equal to
2240 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2241 */
2242 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
2243 memoryBudget->heapBudget[i] = 0;
2244 memoryBudget->heapUsage[i] = 0;
2245 }
2246 }
2247
2248 void radv_GetPhysicalDeviceMemoryProperties2(
2249 VkPhysicalDevice physicalDevice,
2250 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
2251 {
2252 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
2253 &pMemoryProperties->memoryProperties);
2254
2255 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
2256 vk_find_struct(pMemoryProperties->pNext,
2257 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
2258 if (memory_budget)
2259 radv_get_memory_budget_properties(physicalDevice, memory_budget);
2260 }
2261
2262 VkResult radv_GetMemoryHostPointerPropertiesEXT(
2263 VkDevice _device,
2264 VkExternalMemoryHandleTypeFlagBits handleType,
2265 const void *pHostPointer,
2266 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
2267 {
2268 RADV_FROM_HANDLE(radv_device, device, _device);
2269
2270 switch (handleType)
2271 {
2272 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
2273 const struct radv_physical_device *physical_device = device->physical_device;
2274 uint32_t memoryTypeBits = 0;
2275 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
2276 if (physical_device->memory_domains[i] == RADEON_DOMAIN_GTT &&
2277 !(physical_device->memory_flags[i] & RADEON_FLAG_GTT_WC)) {
2278 memoryTypeBits = (1 << i);
2279 break;
2280 }
2281 }
2282 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
2283 return VK_SUCCESS;
2284 }
2285 default:
2286 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
2287 }
2288 }
2289
2290 static enum radeon_ctx_priority
2291 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
2292 {
2293 /* Default to MEDIUM when a specific global priority isn't requested */
2294 if (!pObj)
2295 return RADEON_CTX_PRIORITY_MEDIUM;
2296
2297 switch(pObj->globalPriority) {
2298 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
2299 return RADEON_CTX_PRIORITY_REALTIME;
2300 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
2301 return RADEON_CTX_PRIORITY_HIGH;
2302 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
2303 return RADEON_CTX_PRIORITY_MEDIUM;
2304 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
2305 return RADEON_CTX_PRIORITY_LOW;
2306 default:
2307 unreachable("Illegal global priority value");
2308 return RADEON_CTX_PRIORITY_INVALID;
2309 }
2310 }
2311
2312 static int
2313 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
2314 uint32_t queue_family_index, int idx,
2315 VkDeviceQueueCreateFlags flags,
2316 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
2317 {
2318 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2319 queue->device = device;
2320 queue->queue_family_index = queue_family_index;
2321 queue->queue_idx = idx;
2322 queue->priority = radv_get_queue_global_priority(global_priority);
2323 queue->flags = flags;
2324 queue->hw_ctx = NULL;
2325
2326 VkResult result = device->ws->ctx_create(device->ws, queue->priority, &queue->hw_ctx);
2327 if (result != VK_SUCCESS)
2328 return vk_error(device->instance, result);
2329
2330 list_inithead(&queue->pending_submissions);
2331 pthread_mutex_init(&queue->pending_mutex, NULL);
2332
2333 pthread_mutex_init(&queue->thread_mutex, NULL);
2334 queue->thread_submission = NULL;
2335 queue->thread_running = queue->thread_exit = false;
2336 result = radv_create_pthread_cond(&queue->thread_cond);
2337 if (result != VK_SUCCESS)
2338 return vk_error(device->instance, result);
2339
2340 return VK_SUCCESS;
2341 }
2342
2343 static void
2344 radv_queue_finish(struct radv_queue *queue)
2345 {
2346 if (queue->thread_running) {
2347 p_atomic_set(&queue->thread_exit, true);
2348 pthread_cond_broadcast(&queue->thread_cond);
2349 pthread_join(queue->submission_thread, NULL);
2350 }
2351 pthread_cond_destroy(&queue->thread_cond);
2352 pthread_mutex_destroy(&queue->pending_mutex);
2353 pthread_mutex_destroy(&queue->thread_mutex);
2354
2355 if (queue->hw_ctx)
2356 queue->device->ws->ctx_destroy(queue->hw_ctx);
2357
2358 if (queue->initial_full_flush_preamble_cs)
2359 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2360 if (queue->initial_preamble_cs)
2361 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2362 if (queue->continue_preamble_cs)
2363 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2364 if (queue->descriptor_bo)
2365 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2366 if (queue->scratch_bo)
2367 queue->device->ws->buffer_destroy(queue->scratch_bo);
2368 if (queue->esgs_ring_bo)
2369 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2370 if (queue->gsvs_ring_bo)
2371 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2372 if (queue->tess_rings_bo)
2373 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
2374 if (queue->gds_bo)
2375 queue->device->ws->buffer_destroy(queue->gds_bo);
2376 if (queue->gds_oa_bo)
2377 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
2378 if (queue->compute_scratch_bo)
2379 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2380 }
2381
2382 static void
2383 radv_bo_list_init(struct radv_bo_list *bo_list)
2384 {
2385 pthread_mutex_init(&bo_list->mutex, NULL);
2386 bo_list->list.count = bo_list->capacity = 0;
2387 bo_list->list.bos = NULL;
2388 }
2389
2390 static void
2391 radv_bo_list_finish(struct radv_bo_list *bo_list)
2392 {
2393 free(bo_list->list.bos);
2394 pthread_mutex_destroy(&bo_list->mutex);
2395 }
2396
2397 VkResult radv_bo_list_add(struct radv_device *device,
2398 struct radeon_winsys_bo *bo)
2399 {
2400 struct radv_bo_list *bo_list = &device->bo_list;
2401
2402 if (bo->is_local)
2403 return VK_SUCCESS;
2404
2405 if (unlikely(!device->use_global_bo_list))
2406 return VK_SUCCESS;
2407
2408 pthread_mutex_lock(&bo_list->mutex);
2409 if (bo_list->list.count == bo_list->capacity) {
2410 unsigned capacity = MAX2(4, bo_list->capacity * 2);
2411 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
2412
2413 if (!data) {
2414 pthread_mutex_unlock(&bo_list->mutex);
2415 return VK_ERROR_OUT_OF_HOST_MEMORY;
2416 }
2417
2418 bo_list->list.bos = (struct radeon_winsys_bo**)data;
2419 bo_list->capacity = capacity;
2420 }
2421
2422 bo_list->list.bos[bo_list->list.count++] = bo;
2423 pthread_mutex_unlock(&bo_list->mutex);
2424 return VK_SUCCESS;
2425 }
2426
2427 void radv_bo_list_remove(struct radv_device *device,
2428 struct radeon_winsys_bo *bo)
2429 {
2430 struct radv_bo_list *bo_list = &device->bo_list;
2431
2432 if (bo->is_local)
2433 return;
2434
2435 if (unlikely(!device->use_global_bo_list))
2436 return;
2437
2438 pthread_mutex_lock(&bo_list->mutex);
2439 /* Loop the list backwards so we find the most recently added
2440 * memory first. */
2441 for(unsigned i = bo_list->list.count; i-- > 0;) {
2442 if (bo_list->list.bos[i] == bo) {
2443 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
2444 --bo_list->list.count;
2445 break;
2446 }
2447 }
2448 pthread_mutex_unlock(&bo_list->mutex);
2449 }
2450
2451 static void
2452 radv_device_init_gs_info(struct radv_device *device)
2453 {
2454 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
2455 device->physical_device->rad_info.family);
2456 }
2457
2458 static int radv_get_device_extension_index(const char *name)
2459 {
2460 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
2461 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
2462 return i;
2463 }
2464 return -1;
2465 }
2466
2467 static int
2468 radv_get_int_debug_option(const char *name, int default_value)
2469 {
2470 const char *str;
2471 int result;
2472
2473 str = getenv(name);
2474 if (!str) {
2475 result = default_value;
2476 } else {
2477 char *endptr;
2478
2479 result = strtol(str, &endptr, 0);
2480 if (str == endptr) {
2481 /* No digits founs. */
2482 result = default_value;
2483 }
2484 }
2485
2486 return result;
2487 }
2488
2489 static void
2490 radv_device_init_dispatch(struct radv_device *device)
2491 {
2492 const struct radv_instance *instance = device->physical_device->instance;
2493 const struct radv_device_dispatch_table *dispatch_table_layer = NULL;
2494 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
2495 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2496
2497 if (radv_thread_trace >= 0) {
2498 /* Use device entrypoints from the SQTT layer if enabled. */
2499 dispatch_table_layer = &sqtt_device_dispatch_table;
2500 }
2501
2502 for (unsigned i = 0; i < ARRAY_SIZE(device->dispatch.entrypoints); i++) {
2503 /* Vulkan requires that entrypoints for extensions which have not been
2504 * enabled must not be advertised.
2505 */
2506 if (!unchecked &&
2507 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
2508 &instance->enabled_extensions,
2509 &device->enabled_extensions)) {
2510 device->dispatch.entrypoints[i] = NULL;
2511 } else if (dispatch_table_layer &&
2512 dispatch_table_layer->entrypoints[i]) {
2513 device->dispatch.entrypoints[i] =
2514 dispatch_table_layer->entrypoints[i];
2515 } else {
2516 device->dispatch.entrypoints[i] =
2517 radv_device_dispatch_table.entrypoints[i];
2518 }
2519 }
2520 }
2521
2522 static VkResult
2523 radv_create_pthread_cond(pthread_cond_t *cond)
2524 {
2525 pthread_condattr_t condattr;
2526 if (pthread_condattr_init(&condattr)) {
2527 return VK_ERROR_INITIALIZATION_FAILED;
2528 }
2529
2530 if (pthread_condattr_setclock(&condattr, CLOCK_MONOTONIC)) {
2531 pthread_condattr_destroy(&condattr);
2532 return VK_ERROR_INITIALIZATION_FAILED;
2533 }
2534 if (pthread_cond_init(cond, &condattr)) {
2535 pthread_condattr_destroy(&condattr);
2536 return VK_ERROR_INITIALIZATION_FAILED;
2537 }
2538 pthread_condattr_destroy(&condattr);
2539 return VK_SUCCESS;
2540 }
2541
2542 static VkResult
2543 check_physical_device_features(VkPhysicalDevice physicalDevice,
2544 const VkPhysicalDeviceFeatures *features)
2545 {
2546 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2547 VkPhysicalDeviceFeatures supported_features;
2548 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
2549 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
2550 VkBool32 *enabled_feature = (VkBool32 *)features;
2551 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
2552 for (uint32_t i = 0; i < num_features; i++) {
2553 if (enabled_feature[i] && !supported_feature[i])
2554 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
2555 }
2556
2557 return VK_SUCCESS;
2558 }
2559
2560 static VkResult radv_device_init_border_color(struct radv_device *device)
2561 {
2562 device->border_color_data.bo =
2563 device->ws->buffer_create(device->ws,
2564 RADV_BORDER_COLOR_BUFFER_SIZE,
2565 4096,
2566 RADEON_DOMAIN_VRAM,
2567 RADEON_FLAG_CPU_ACCESS |
2568 RADEON_FLAG_READ_ONLY |
2569 RADEON_FLAG_NO_INTERPROCESS_SHARING,
2570 RADV_BO_PRIORITY_SHADER);
2571
2572 if (device->border_color_data.bo == NULL)
2573 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2574
2575 device->border_color_data.colors_gpu_ptr =
2576 device->ws->buffer_map(device->border_color_data.bo);
2577 if (!device->border_color_data.colors_gpu_ptr)
2578 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2579 pthread_mutex_init(&device->border_color_data.mutex, NULL);
2580
2581 return VK_SUCCESS;
2582 }
2583
2584 static void radv_device_finish_border_color(struct radv_device *device)
2585 {
2586 if (device->border_color_data.bo) {
2587 device->ws->buffer_destroy(device->border_color_data.bo);
2588
2589 pthread_mutex_destroy(&device->border_color_data.mutex);
2590 }
2591 }
2592
2593 VkResult
2594 _radv_device_set_lost(struct radv_device *device,
2595 const char *file, int line,
2596 const char *msg, ...)
2597 {
2598 VkResult err;
2599 va_list ap;
2600
2601 p_atomic_inc(&device->lost);
2602
2603 va_start(ap, msg);
2604 err = __vk_errorv(device->physical_device->instance, device,
2605 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT,
2606 VK_ERROR_DEVICE_LOST, file, line, msg, ap);
2607 va_end(ap);
2608
2609 return err;
2610 }
2611
2612 VkResult radv_CreateDevice(
2613 VkPhysicalDevice physicalDevice,
2614 const VkDeviceCreateInfo* pCreateInfo,
2615 const VkAllocationCallbacks* pAllocator,
2616 VkDevice* pDevice)
2617 {
2618 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2619 VkResult result;
2620 struct radv_device *device;
2621
2622 bool keep_shader_info = false;
2623 bool robust_buffer_access = false;
2624 bool overallocation_disallowed = false;
2625 bool custom_border_colors = false;
2626
2627 /* Check enabled features */
2628 if (pCreateInfo->pEnabledFeatures) {
2629 result = check_physical_device_features(physicalDevice,
2630 pCreateInfo->pEnabledFeatures);
2631 if (result != VK_SUCCESS)
2632 return result;
2633
2634 if (pCreateInfo->pEnabledFeatures->robustBufferAccess)
2635 robust_buffer_access = true;
2636 }
2637
2638 vk_foreach_struct_const(ext, pCreateInfo->pNext) {
2639 switch (ext->sType) {
2640 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2: {
2641 const VkPhysicalDeviceFeatures2 *features = (const void *)ext;
2642 result = check_physical_device_features(physicalDevice,
2643 &features->features);
2644 if (result != VK_SUCCESS)
2645 return result;
2646
2647 if (features->features.robustBufferAccess)
2648 robust_buffer_access = true;
2649 break;
2650 }
2651 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
2652 const VkDeviceMemoryOverallocationCreateInfoAMD *overallocation = (const void *)ext;
2653 if (overallocation->overallocationBehavior == VK_MEMORY_OVERALLOCATION_BEHAVIOR_DISALLOWED_AMD)
2654 overallocation_disallowed = true;
2655 break;
2656 }
2657 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
2658 const VkPhysicalDeviceCustomBorderColorFeaturesEXT *border_color_features = (const void *)ext;
2659 custom_border_colors = border_color_features->customBorderColors;
2660 break;
2661 }
2662 default:
2663 break;
2664 }
2665 }
2666
2667 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
2668 sizeof(*device), 8,
2669 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2670 if (!device)
2671 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2672
2673 vk_device_init(&device->vk, pCreateInfo,
2674 &physical_device->instance->alloc, pAllocator);
2675
2676 device->instance = physical_device->instance;
2677 device->physical_device = physical_device;
2678
2679 device->ws = physical_device->ws;
2680
2681 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
2682 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
2683 int index = radv_get_device_extension_index(ext_name);
2684 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
2685 vk_free(&device->vk.alloc, device);
2686 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
2687 }
2688
2689 device->enabled_extensions.extensions[index] = true;
2690 }
2691
2692 radv_device_init_dispatch(device);
2693
2694 keep_shader_info = device->enabled_extensions.AMD_shader_info;
2695
2696 /* With update after bind we can't attach bo's to the command buffer
2697 * from the descriptor set anymore, so we have to use a global BO list.
2698 */
2699 device->use_global_bo_list =
2700 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
2701 device->enabled_extensions.EXT_descriptor_indexing ||
2702 device->enabled_extensions.EXT_buffer_device_address ||
2703 device->enabled_extensions.KHR_buffer_device_address;
2704
2705 device->robust_buffer_access = robust_buffer_access;
2706
2707 mtx_init(&device->shader_slab_mutex, mtx_plain);
2708 list_inithead(&device->shader_slabs);
2709
2710 device->overallocation_disallowed = overallocation_disallowed;
2711 mtx_init(&device->overallocation_mutex, mtx_plain);
2712
2713 radv_bo_list_init(&device->bo_list);
2714
2715 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
2716 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
2717 uint32_t qfi = queue_create->queueFamilyIndex;
2718 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
2719 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
2720
2721 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
2722
2723 device->queues[qfi] = vk_alloc(&device->vk.alloc,
2724 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2725 if (!device->queues[qfi]) {
2726 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2727 goto fail;
2728 }
2729
2730 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
2731
2732 device->queue_count[qfi] = queue_create->queueCount;
2733
2734 for (unsigned q = 0; q < queue_create->queueCount; q++) {
2735 result = radv_queue_init(device, &device->queues[qfi][q],
2736 qfi, q, queue_create->flags,
2737 global_priority);
2738 if (result != VK_SUCCESS)
2739 goto fail;
2740 }
2741 }
2742
2743 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
2744 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
2745
2746 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2747 device->dfsm_allowed = device->pbb_allowed &&
2748 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
2749
2750 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
2751
2752 /* The maximum number of scratch waves. Scratch space isn't divided
2753 * evenly between CUs. The number is only a function of the number of CUs.
2754 * We can decrease the constant to decrease the scratch buffer size.
2755 *
2756 * sctx->scratch_waves must be >= the maximum possible size of
2757 * 1 threadgroup, so that the hw doesn't hang from being unable
2758 * to start any.
2759 *
2760 * The recommended value is 4 per CU at most. Higher numbers don't
2761 * bring much benefit, but they still occupy chip resources (think
2762 * async compute). I've seen ~2% performance difference between 4 and 32.
2763 */
2764 uint32_t max_threads_per_block = 2048;
2765 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
2766 max_threads_per_block / 64);
2767
2768 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
2769
2770 if (device->physical_device->rad_info.chip_class >= GFX7) {
2771 /* If the KMD allows it (there is a KMD hw register for it),
2772 * allow launching waves out-of-order.
2773 */
2774 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
2775 }
2776
2777 radv_device_init_gs_info(device);
2778
2779 device->tess_offchip_block_dw_size =
2780 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2781
2782 if (getenv("RADV_TRACE_FILE")) {
2783 const char *filename = getenv("RADV_TRACE_FILE");
2784
2785 keep_shader_info = true;
2786
2787 if (!radv_init_trace(device))
2788 goto fail;
2789
2790 fprintf(stderr, "*****************************************************************************\n");
2791 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2792 fprintf(stderr, "*****************************************************************************\n");
2793
2794 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2795 radv_dump_enabled_options(device, stderr);
2796 }
2797
2798 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2799 if (radv_thread_trace >= 0) {
2800 fprintf(stderr, "*************************************************\n");
2801 fprintf(stderr, "* WARNING: Thread trace support is experimental *\n");
2802 fprintf(stderr, "*************************************************\n");
2803
2804 if (device->physical_device->rad_info.chip_class < GFX8) {
2805 fprintf(stderr, "GPU hardware not supported: refer to "
2806 "the RGP documentation for the list of "
2807 "supported GPUs!\n");
2808 abort();
2809 }
2810
2811 /* Default buffer size set to 1MB per SE. */
2812 device->thread_trace_buffer_size =
2813 radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024);
2814 device->thread_trace_start_frame = radv_thread_trace;
2815
2816 if (!radv_thread_trace_init(device))
2817 goto fail;
2818 }
2819
2820 device->keep_shader_info = keep_shader_info;
2821 result = radv_device_init_meta(device);
2822 if (result != VK_SUCCESS)
2823 goto fail;
2824
2825 radv_device_init_msaa(device);
2826
2827 /* If the border color extension is enabled, let's create the buffer we need. */
2828 if (custom_border_colors) {
2829 result = radv_device_init_border_color(device);
2830 if (result != VK_SUCCESS)
2831 goto fail;
2832 }
2833
2834 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2835 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2836 if (!device->empty_cs[family])
2837 goto fail;
2838
2839 switch (family) {
2840 case RADV_QUEUE_GENERAL:
2841 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2842 radeon_emit(device->empty_cs[family], CC0_UPDATE_LOAD_ENABLES(1));
2843 radeon_emit(device->empty_cs[family], CC1_UPDATE_SHADOW_ENABLES(1));
2844 break;
2845 case RADV_QUEUE_COMPUTE:
2846 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2847 radeon_emit(device->empty_cs[family], 0);
2848 break;
2849 }
2850
2851 result = device->ws->cs_finalize(device->empty_cs[family]);
2852 if (result != VK_SUCCESS)
2853 goto fail;
2854 }
2855
2856 if (device->physical_device->rad_info.chip_class >= GFX7)
2857 cik_create_gfx_config(device);
2858
2859 VkPipelineCacheCreateInfo ci;
2860 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2861 ci.pNext = NULL;
2862 ci.flags = 0;
2863 ci.pInitialData = NULL;
2864 ci.initialDataSize = 0;
2865 VkPipelineCache pc;
2866 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2867 &ci, NULL, &pc);
2868 if (result != VK_SUCCESS)
2869 goto fail_meta;
2870
2871 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2872
2873 result = radv_create_pthread_cond(&device->timeline_cond);
2874 if (result != VK_SUCCESS)
2875 goto fail_mem_cache;
2876
2877 device->force_aniso =
2878 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2879 if (device->force_aniso >= 0) {
2880 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2881 1 << util_logbase2(device->force_aniso));
2882 }
2883
2884 *pDevice = radv_device_to_handle(device);
2885 return VK_SUCCESS;
2886
2887 fail_mem_cache:
2888 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2889 fail_meta:
2890 radv_device_finish_meta(device);
2891 fail:
2892 radv_bo_list_finish(&device->bo_list);
2893
2894 radv_thread_trace_finish(device);
2895
2896 if (device->trace_bo)
2897 device->ws->buffer_destroy(device->trace_bo);
2898
2899 if (device->gfx_init)
2900 device->ws->buffer_destroy(device->gfx_init);
2901
2902 radv_device_finish_border_color(device);
2903
2904 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2905 for (unsigned q = 0; q < device->queue_count[i]; q++)
2906 radv_queue_finish(&device->queues[i][q]);
2907 if (device->queue_count[i])
2908 vk_free(&device->vk.alloc, device->queues[i]);
2909 }
2910
2911 vk_free(&device->vk.alloc, device);
2912 return result;
2913 }
2914
2915 void radv_DestroyDevice(
2916 VkDevice _device,
2917 const VkAllocationCallbacks* pAllocator)
2918 {
2919 RADV_FROM_HANDLE(radv_device, device, _device);
2920
2921 if (!device)
2922 return;
2923
2924 if (device->trace_bo)
2925 device->ws->buffer_destroy(device->trace_bo);
2926
2927 if (device->gfx_init)
2928 device->ws->buffer_destroy(device->gfx_init);
2929
2930 radv_device_finish_border_color(device);
2931
2932 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2933 for (unsigned q = 0; q < device->queue_count[i]; q++)
2934 radv_queue_finish(&device->queues[i][q]);
2935 if (device->queue_count[i])
2936 vk_free(&device->vk.alloc, device->queues[i]);
2937 if (device->empty_cs[i])
2938 device->ws->cs_destroy(device->empty_cs[i]);
2939 }
2940 radv_device_finish_meta(device);
2941
2942 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2943 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2944
2945 radv_destroy_shader_slabs(device);
2946
2947 pthread_cond_destroy(&device->timeline_cond);
2948 radv_bo_list_finish(&device->bo_list);
2949
2950 radv_thread_trace_finish(device);
2951
2952 vk_free(&device->vk.alloc, device);
2953 }
2954
2955 VkResult radv_EnumerateInstanceLayerProperties(
2956 uint32_t* pPropertyCount,
2957 VkLayerProperties* pProperties)
2958 {
2959 if (pProperties == NULL) {
2960 *pPropertyCount = 0;
2961 return VK_SUCCESS;
2962 }
2963
2964 /* None supported at this time */
2965 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2966 }
2967
2968 VkResult radv_EnumerateDeviceLayerProperties(
2969 VkPhysicalDevice physicalDevice,
2970 uint32_t* pPropertyCount,
2971 VkLayerProperties* pProperties)
2972 {
2973 if (pProperties == NULL) {
2974 *pPropertyCount = 0;
2975 return VK_SUCCESS;
2976 }
2977
2978 /* None supported at this time */
2979 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2980 }
2981
2982 void radv_GetDeviceQueue2(
2983 VkDevice _device,
2984 const VkDeviceQueueInfo2* pQueueInfo,
2985 VkQueue* pQueue)
2986 {
2987 RADV_FROM_HANDLE(radv_device, device, _device);
2988 struct radv_queue *queue;
2989
2990 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2991 if (pQueueInfo->flags != queue->flags) {
2992 /* From the Vulkan 1.1.70 spec:
2993 *
2994 * "The queue returned by vkGetDeviceQueue2 must have the same
2995 * flags value from this structure as that used at device
2996 * creation time in a VkDeviceQueueCreateInfo instance. If no
2997 * matching flags were specified at device creation time then
2998 * pQueue will return VK_NULL_HANDLE."
2999 */
3000 *pQueue = VK_NULL_HANDLE;
3001 return;
3002 }
3003
3004 *pQueue = radv_queue_to_handle(queue);
3005 }
3006
3007 void radv_GetDeviceQueue(
3008 VkDevice _device,
3009 uint32_t queueFamilyIndex,
3010 uint32_t queueIndex,
3011 VkQueue* pQueue)
3012 {
3013 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
3014 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
3015 .queueFamilyIndex = queueFamilyIndex,
3016 .queueIndex = queueIndex
3017 };
3018
3019 radv_GetDeviceQueue2(_device, &info, pQueue);
3020 }
3021
3022 static void
3023 fill_geom_tess_rings(struct radv_queue *queue,
3024 uint32_t *map,
3025 bool add_sample_positions,
3026 uint32_t esgs_ring_size,
3027 struct radeon_winsys_bo *esgs_ring_bo,
3028 uint32_t gsvs_ring_size,
3029 struct radeon_winsys_bo *gsvs_ring_bo,
3030 uint32_t tess_factor_ring_size,
3031 uint32_t tess_offchip_ring_offset,
3032 uint32_t tess_offchip_ring_size,
3033 struct radeon_winsys_bo *tess_rings_bo)
3034 {
3035 uint32_t *desc = &map[4];
3036
3037 if (esgs_ring_bo) {
3038 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
3039
3040 /* stride 0, num records - size, add tid, swizzle, elsize4,
3041 index stride 64 */
3042 desc[0] = esgs_va;
3043 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
3044 S_008F04_SWIZZLE_ENABLE(true);
3045 desc[2] = esgs_ring_size;
3046 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3047 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3048 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3049 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3050 S_008F0C_INDEX_STRIDE(3) |
3051 S_008F0C_ADD_TID_ENABLE(1);
3052
3053 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3054 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3055 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3056 S_008F0C_RESOURCE_LEVEL(1);
3057 } else {
3058 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3059 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3060 S_008F0C_ELEMENT_SIZE(1);
3061 }
3062
3063 /* GS entry for ES->GS ring */
3064 /* stride 0, num records - size, elsize0,
3065 index stride 0 */
3066 desc[4] = esgs_va;
3067 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
3068 desc[6] = esgs_ring_size;
3069 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3070 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3071 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3072 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3073
3074 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3075 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3076 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3077 S_008F0C_RESOURCE_LEVEL(1);
3078 } else {
3079 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3080 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3081 }
3082 }
3083
3084 desc += 8;
3085
3086 if (gsvs_ring_bo) {
3087 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
3088
3089 /* VS entry for GS->VS ring */
3090 /* stride 0, num records - size, elsize0,
3091 index stride 0 */
3092 desc[0] = gsvs_va;
3093 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
3094 desc[2] = gsvs_ring_size;
3095 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3096 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3097 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3098 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3099
3100 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3101 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3102 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3103 S_008F0C_RESOURCE_LEVEL(1);
3104 } else {
3105 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3106 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3107 }
3108
3109 /* stride gsvs_itemsize, num records 64
3110 elsize 4, index stride 16 */
3111 /* shader will patch stride and desc[2] */
3112 desc[4] = gsvs_va;
3113 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
3114 S_008F04_SWIZZLE_ENABLE(1);
3115 desc[6] = 0;
3116 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3117 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3118 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3119 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3120 S_008F0C_INDEX_STRIDE(1) |
3121 S_008F0C_ADD_TID_ENABLE(true);
3122
3123 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3124 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3125 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3126 S_008F0C_RESOURCE_LEVEL(1);
3127 } else {
3128 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3129 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3130 S_008F0C_ELEMENT_SIZE(1);
3131 }
3132
3133 }
3134
3135 desc += 8;
3136
3137 if (tess_rings_bo) {
3138 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
3139 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
3140
3141 desc[0] = tess_va;
3142 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
3143 desc[2] = tess_factor_ring_size;
3144 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3145 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3146 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3147 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3148
3149 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3150 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3151 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3152 S_008F0C_RESOURCE_LEVEL(1);
3153 } else {
3154 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3155 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3156 }
3157
3158 desc[4] = tess_offchip_va;
3159 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
3160 desc[6] = tess_offchip_ring_size;
3161 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3162 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3163 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3164 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3165
3166 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3167 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3168 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3169 S_008F0C_RESOURCE_LEVEL(1);
3170 } else {
3171 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3172 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3173 }
3174 }
3175
3176 desc += 8;
3177
3178 if (add_sample_positions) {
3179 /* add sample positions after all rings */
3180 memcpy(desc, queue->device->sample_locations_1x, 8);
3181 desc += 2;
3182 memcpy(desc, queue->device->sample_locations_2x, 16);
3183 desc += 4;
3184 memcpy(desc, queue->device->sample_locations_4x, 32);
3185 desc += 8;
3186 memcpy(desc, queue->device->sample_locations_8x, 64);
3187 }
3188 }
3189
3190 static unsigned
3191 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
3192 {
3193 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
3194 device->physical_device->rad_info.family != CHIP_CARRIZO &&
3195 device->physical_device->rad_info.family != CHIP_STONEY;
3196 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
3197 unsigned max_offchip_buffers;
3198 unsigned offchip_granularity;
3199 unsigned hs_offchip_param;
3200
3201 /*
3202 * Per RadeonSI:
3203 * This must be one less than the maximum number due to a hw limitation.
3204 * Various hardware bugs need thGFX7
3205 *
3206 * Per AMDVLK:
3207 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3208 * Gfx7 should limit max_offchip_buffers to 508
3209 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3210 *
3211 * Follow AMDVLK here.
3212 */
3213 if (device->physical_device->rad_info.chip_class >= GFX10) {
3214 max_offchip_buffers_per_se = 256;
3215 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
3216 device->physical_device->rad_info.chip_class == GFX7 ||
3217 device->physical_device->rad_info.chip_class == GFX6)
3218 --max_offchip_buffers_per_se;
3219
3220 max_offchip_buffers = max_offchip_buffers_per_se *
3221 device->physical_device->rad_info.max_se;
3222
3223 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3224 * around by setting 4K granularity.
3225 */
3226 if (device->tess_offchip_block_dw_size == 4096) {
3227 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
3228 offchip_granularity = V_03093C_X_4K_DWORDS;
3229 } else {
3230 assert(device->tess_offchip_block_dw_size == 8192);
3231 offchip_granularity = V_03093C_X_8K_DWORDS;
3232 }
3233
3234 switch (device->physical_device->rad_info.chip_class) {
3235 case GFX6:
3236 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
3237 break;
3238 case GFX7:
3239 case GFX8:
3240 case GFX9:
3241 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
3242 break;
3243 case GFX10:
3244 break;
3245 default:
3246 break;
3247 }
3248
3249 *max_offchip_buffers_p = max_offchip_buffers;
3250 if (device->physical_device->rad_info.chip_class >= GFX10_3) {
3251 hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers - 1) |
3252 S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity);
3253 } else if (device->physical_device->rad_info.chip_class >= GFX7) {
3254 if (device->physical_device->rad_info.chip_class >= GFX8)
3255 --max_offchip_buffers;
3256 hs_offchip_param =
3257 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
3258 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
3259 } else {
3260 hs_offchip_param =
3261 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
3262 }
3263 return hs_offchip_param;
3264 }
3265
3266 static void
3267 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3268 struct radeon_winsys_bo *esgs_ring_bo,
3269 uint32_t esgs_ring_size,
3270 struct radeon_winsys_bo *gsvs_ring_bo,
3271 uint32_t gsvs_ring_size)
3272 {
3273 if (!esgs_ring_bo && !gsvs_ring_bo)
3274 return;
3275
3276 if (esgs_ring_bo)
3277 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
3278
3279 if (gsvs_ring_bo)
3280 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
3281
3282 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3283 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
3284 radeon_emit(cs, esgs_ring_size >> 8);
3285 radeon_emit(cs, gsvs_ring_size >> 8);
3286 } else {
3287 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
3288 radeon_emit(cs, esgs_ring_size >> 8);
3289 radeon_emit(cs, gsvs_ring_size >> 8);
3290 }
3291 }
3292
3293 static void
3294 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3295 unsigned hs_offchip_param, unsigned tf_ring_size,
3296 struct radeon_winsys_bo *tess_rings_bo)
3297 {
3298 uint64_t tf_va;
3299
3300 if (!tess_rings_bo)
3301 return;
3302
3303 tf_va = radv_buffer_get_va(tess_rings_bo);
3304
3305 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
3306
3307 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3308 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
3309 S_030938_SIZE(tf_ring_size / 4));
3310 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
3311 tf_va >> 8);
3312
3313 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3314 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3315 S_030984_BASE_HI(tf_va >> 40));
3316 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3317 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
3318 S_030944_BASE_HI(tf_va >> 40));
3319 }
3320 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
3321 hs_offchip_param);
3322 } else {
3323 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
3324 S_008988_SIZE(tf_ring_size / 4));
3325 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
3326 tf_va >> 8);
3327 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3328 hs_offchip_param);
3329 }
3330 }
3331
3332 static void
3333 radv_emit_graphics_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3334 uint32_t size_per_wave, uint32_t waves,
3335 struct radeon_winsys_bo *scratch_bo)
3336 {
3337 if (queue->queue_family_index != RADV_QUEUE_GENERAL)
3338 return;
3339
3340 if (!scratch_bo)
3341 return;
3342
3343 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3344
3345 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3346 S_0286E8_WAVES(waves) |
3347 S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3348 }
3349
3350 static void
3351 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3352 uint32_t size_per_wave, uint32_t waves,
3353 struct radeon_winsys_bo *compute_scratch_bo)
3354 {
3355 uint64_t scratch_va;
3356
3357 if (!compute_scratch_bo)
3358 return;
3359
3360 scratch_va = radv_buffer_get_va(compute_scratch_bo);
3361
3362 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
3363
3364 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
3365 radeon_emit(cs, scratch_va);
3366 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3367 S_008F04_SWIZZLE_ENABLE(1));
3368
3369 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
3370 S_00B860_WAVES(waves) |
3371 S_00B860_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3372 }
3373
3374 static void
3375 radv_emit_global_shader_pointers(struct radv_queue *queue,
3376 struct radeon_cmdbuf *cs,
3377 struct radeon_winsys_bo *descriptor_bo)
3378 {
3379 uint64_t va;
3380
3381 if (!descriptor_bo)
3382 return;
3383
3384 va = radv_buffer_get_va(descriptor_bo);
3385
3386 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
3387
3388 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3389 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3390 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3391 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3392 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3393
3394 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3395 radv_emit_shader_pointer(queue->device, cs, regs[i],
3396 va, true);
3397 }
3398 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3399 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3400 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3401 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3402 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3403
3404 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3405 radv_emit_shader_pointer(queue->device, cs, regs[i],
3406 va, true);
3407 }
3408 } else {
3409 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3410 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3411 R_00B230_SPI_SHADER_USER_DATA_GS_0,
3412 R_00B330_SPI_SHADER_USER_DATA_ES_0,
3413 R_00B430_SPI_SHADER_USER_DATA_HS_0,
3414 R_00B530_SPI_SHADER_USER_DATA_LS_0};
3415
3416 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3417 radv_emit_shader_pointer(queue->device, cs, regs[i],
3418 va, true);
3419 }
3420 }
3421 }
3422
3423 static void
3424 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3425 {
3426 struct radv_device *device = queue->device;
3427
3428 if (device->gfx_init) {
3429 uint64_t va = radv_buffer_get_va(device->gfx_init);
3430
3431 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
3432 radeon_emit(cs, va);
3433 radeon_emit(cs, va >> 32);
3434 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
3435
3436 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
3437 } else {
3438 si_emit_graphics(device, cs);
3439 }
3440 }
3441
3442 static void
3443 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3444 {
3445 si_emit_compute(queue->device, cs);
3446 }
3447
3448 static VkResult
3449 radv_get_preamble_cs(struct radv_queue *queue,
3450 uint32_t scratch_size_per_wave,
3451 uint32_t scratch_waves,
3452 uint32_t compute_scratch_size_per_wave,
3453 uint32_t compute_scratch_waves,
3454 uint32_t esgs_ring_size,
3455 uint32_t gsvs_ring_size,
3456 bool needs_tess_rings,
3457 bool needs_gds,
3458 bool needs_gds_oa,
3459 bool needs_sample_positions,
3460 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
3461 struct radeon_cmdbuf **initial_preamble_cs,
3462 struct radeon_cmdbuf **continue_preamble_cs)
3463 {
3464 struct radeon_winsys_bo *scratch_bo = NULL;
3465 struct radeon_winsys_bo *descriptor_bo = NULL;
3466 struct radeon_winsys_bo *compute_scratch_bo = NULL;
3467 struct radeon_winsys_bo *esgs_ring_bo = NULL;
3468 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
3469 struct radeon_winsys_bo *tess_rings_bo = NULL;
3470 struct radeon_winsys_bo *gds_bo = NULL;
3471 struct radeon_winsys_bo *gds_oa_bo = NULL;
3472 struct radeon_cmdbuf *dest_cs[3] = {0};</