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radv: clean up fill_geom_tess_rings()
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
52
53 static int
54 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
55 {
56 struct mesa_sha1 ctx;
57 unsigned char sha1[20];
58 unsigned ptr_size = sizeof(void*);
59
60 memset(uuid, 0, VK_UUID_SIZE);
61 _mesa_sha1_init(&ctx);
62
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
65 return -1;
66
67 _mesa_sha1_update(&ctx, &family, sizeof(family));
68 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
69 _mesa_sha1_final(&ctx, sha1);
70
71 memcpy(uuid, sha1, VK_UUID_SIZE);
72 return 0;
73 }
74
75 static void
76 radv_get_driver_uuid(void *uuid)
77 {
78 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
79 }
80
81 static void
82 radv_get_device_uuid(struct radeon_info *info, void *uuid)
83 {
84 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
85 }
86
87 static void
88 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
89 {
90 const char *chip_string;
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
103 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
110 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 case CHIP_NAVI10: chip_string = "AMD RADV NAVI10"; break;
117 case CHIP_NAVI12: chip_string = "AMD RADV NAVI12"; break;
118 case CHIP_NAVI14: chip_string = "AMD RADV NAVI14"; break;
119 default: chip_string = "AMD RADV unknown"; break;
120 }
121
122 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_NAVI10)
222 device->rad_info.chip_class = GFX10;
223 else if (i >= CHIP_VEGA10)
224 device->rad_info.chip_class = GFX9;
225 else if (i >= CHIP_TONGA)
226 device->rad_info.chip_class = GFX8;
227 else if (i >= CHIP_BONAIRE)
228 device->rad_info.chip_class = GFX7;
229 else
230 device->rad_info.chip_class = GFX6;
231
232 return;
233 }
234 }
235
236 fprintf(stderr, "radv: Unknown family: %s\n", family);
237 exit(1);
238 }
239
240 static VkResult
241 radv_physical_device_init(struct radv_physical_device *device,
242 struct radv_instance *instance,
243 drmDevicePtr drm_device)
244 {
245 const char *path = drm_device->nodes[DRM_NODE_RENDER];
246 VkResult result;
247 drmVersionPtr version;
248 int fd;
249 int master_fd = -1;
250
251 fd = open(path, O_RDWR | O_CLOEXEC);
252 if (fd < 0) {
253 if (instance->debug_flags & RADV_DEBUG_STARTUP)
254 radv_logi("Could not open device '%s'", path);
255
256 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
257 }
258
259 version = drmGetVersion(fd);
260 if (!version) {
261 close(fd);
262
263 if (instance->debug_flags & RADV_DEBUG_STARTUP)
264 radv_logi("Could not get the kernel driver version for device '%s'", path);
265
266 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
267 "failed to get version %s: %m", path);
268 }
269
270 if (strcmp(version->name, "amdgpu")) {
271 drmFreeVersion(version);
272 close(fd);
273
274 if (instance->debug_flags & RADV_DEBUG_STARTUP)
275 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
276
277 return VK_ERROR_INCOMPATIBLE_DRIVER;
278 }
279 drmFreeVersion(version);
280
281 if (instance->debug_flags & RADV_DEBUG_STARTUP)
282 radv_logi("Found compatible device '%s'.", path);
283
284 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
285 device->instance = instance;
286
287 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
288 instance->perftest_flags);
289 if (!device->ws) {
290 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
291 goto fail;
292 }
293
294 if (instance->enabled_extensions.KHR_display) {
295 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
296 if (master_fd >= 0) {
297 uint32_t accel_working = 0;
298 struct drm_amdgpu_info request = {
299 .return_pointer = (uintptr_t)&accel_working,
300 .return_size = sizeof(accel_working),
301 .query = AMDGPU_INFO_ACCEL_WORKING
302 };
303
304 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
305 close(master_fd);
306 master_fd = -1;
307 }
308 }
309 }
310
311 device->master_fd = master_fd;
312 device->local_fd = fd;
313 device->ws->query_info(device->ws, &device->rad_info);
314
315 radv_handle_env_var_force_family(device);
316
317 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
318
319 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
320 device->ws->destroy(device->ws);
321 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
322 "cannot generate UUID");
323 goto fail;
324 }
325
326 /* These flags affect shader compilation. */
327 uint64_t shader_env_flags =
328 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
329 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
330
331 /* The gpu id is already embedded in the uuid so we just pass "radv"
332 * when creating the cache.
333 */
334 char buf[VK_UUID_SIZE * 2 + 1];
335 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
336 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
337
338 if (device->rad_info.chip_class < GFX8 ||
339 device->rad_info.chip_class > GFX9)
340 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
341
342 radv_get_driver_uuid(&device->driver_uuid);
343 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
344
345 if (device->rad_info.family == CHIP_STONEY ||
346 device->rad_info.chip_class >= GFX9) {
347 device->has_rbplus = true;
348 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
349 device->rad_info.family == CHIP_VEGA12 ||
350 device->rad_info.family == CHIP_RAVEN ||
351 device->rad_info.family == CHIP_RAVEN2;
352 }
353
354 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
355 * on GFX6.
356 */
357 device->has_clear_state = device->rad_info.chip_class >= GFX7 &&
358 device->rad_info.chip_class <= GFX9;
359
360 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
361
362 /* Vega10/Raven need a special workaround for a hardware bug. */
363 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
364 device->rad_info.family == CHIP_RAVEN;
365
366 device->has_tc_compat_zrange_bug = device->rad_info.chip_class < GFX10;
367
368 /* Out-of-order primitive rasterization. */
369 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
370 device->rad_info.max_se >= 2;
371 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
372 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
373
374 device->dcc_msaa_allowed =
375 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
376
377 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
378 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
379 (device->rad_info.chip_class >= GFX8 &&
380 device->rad_info.me_fw_feature >= 41);
381
382 device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2 ||
383 device->rad_info.chip_class >= GFX10;
384
385 device->use_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
386
387 radv_physical_device_init_mem_types(device);
388 radv_fill_device_extension_table(device, &device->supported_extensions);
389
390 device->bus_info = *drm_device->businfo.pci;
391
392 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
393 ac_print_gpu_info(&device->rad_info);
394
395 /* The WSI is structured as a layer on top of the driver, so this has
396 * to be the last part of initialization (at least until we get other
397 * semi-layers).
398 */
399 result = radv_init_wsi(device);
400 if (result != VK_SUCCESS) {
401 device->ws->destroy(device->ws);
402 vk_error(instance, result);
403 goto fail;
404 }
405
406 return VK_SUCCESS;
407
408 fail:
409 close(fd);
410 if (master_fd != -1)
411 close(master_fd);
412 return result;
413 }
414
415 static void
416 radv_physical_device_finish(struct radv_physical_device *device)
417 {
418 radv_finish_wsi(device);
419 device->ws->destroy(device->ws);
420 disk_cache_destroy(device->disk_cache);
421 close(device->local_fd);
422 if (device->master_fd != -1)
423 close(device->master_fd);
424 }
425
426 static void *
427 default_alloc_func(void *pUserData, size_t size, size_t align,
428 VkSystemAllocationScope allocationScope)
429 {
430 return malloc(size);
431 }
432
433 static void *
434 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
435 size_t align, VkSystemAllocationScope allocationScope)
436 {
437 return realloc(pOriginal, size);
438 }
439
440 static void
441 default_free_func(void *pUserData, void *pMemory)
442 {
443 free(pMemory);
444 }
445
446 static const VkAllocationCallbacks default_alloc = {
447 .pUserData = NULL,
448 .pfnAllocation = default_alloc_func,
449 .pfnReallocation = default_realloc_func,
450 .pfnFree = default_free_func,
451 };
452
453 static const struct debug_control radv_debug_options[] = {
454 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
455 {"nodcc", RADV_DEBUG_NO_DCC},
456 {"shaders", RADV_DEBUG_DUMP_SHADERS},
457 {"nocache", RADV_DEBUG_NO_CACHE},
458 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
459 {"nohiz", RADV_DEBUG_NO_HIZ},
460 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
461 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
462 {"allbos", RADV_DEBUG_ALL_BOS},
463 {"noibs", RADV_DEBUG_NO_IBS},
464 {"spirv", RADV_DEBUG_DUMP_SPIRV},
465 {"vmfaults", RADV_DEBUG_VM_FAULTS},
466 {"zerovram", RADV_DEBUG_ZERO_VRAM},
467 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
468 {"nosisched", RADV_DEBUG_NO_SISCHED},
469 {"preoptir", RADV_DEBUG_PREOPTIR},
470 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
471 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
472 {"info", RADV_DEBUG_INFO},
473 {"errors", RADV_DEBUG_ERRORS},
474 {"startup", RADV_DEBUG_STARTUP},
475 {"checkir", RADV_DEBUG_CHECKIR},
476 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
477 {"nobinning", RADV_DEBUG_NOBINNING},
478 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
479 {"nongg", RADV_DEBUG_NO_NGG},
480 {NULL, 0}
481 };
482
483 const char *
484 radv_get_debug_option_name(int id)
485 {
486 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
487 return radv_debug_options[id].string;
488 }
489
490 static const struct debug_control radv_perftest_options[] = {
491 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
492 {"sisched", RADV_PERFTEST_SISCHED},
493 {"localbos", RADV_PERFTEST_LOCAL_BOS},
494 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
495 {"bolist", RADV_PERFTEST_BO_LIST},
496 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
497 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
498 {NULL, 0}
499 };
500
501 const char *
502 radv_get_perftest_option_name(int id)
503 {
504 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
505 return radv_perftest_options[id].string;
506 }
507
508 static void
509 radv_handle_per_app_options(struct radv_instance *instance,
510 const VkApplicationInfo *info)
511 {
512 const char *name = info ? info->pApplicationName : NULL;
513
514 if (!name)
515 return;
516
517 if (!strcmp(name, "Talos - Linux - 32bit") ||
518 !strcmp(name, "Talos - Linux - 64bit")) {
519 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
520 /* Force enable LLVM sisched for Talos because it looks
521 * safe and it gives few more FPS.
522 */
523 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
524 }
525 } else if (!strcmp(name, "DOOM_VFR")) {
526 /* Work around a Doom VFR game bug */
527 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
528 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
529 /* Workaround for a WaW hazard when LLVM moves/merges
530 * load/store memory operations.
531 * See https://reviews.llvm.org/D61313
532 */
533 if (HAVE_LLVM < 0x900)
534 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
535 }
536 }
537
538 static int radv_get_instance_extension_index(const char *name)
539 {
540 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
541 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
542 return i;
543 }
544 return -1;
545 }
546
547 static const char radv_dri_options_xml[] =
548 DRI_CONF_BEGIN
549 DRI_CONF_SECTION_QUALITY
550 DRI_CONF_ADAPTIVE_SYNC("true")
551 DRI_CONF_SECTION_END
552 DRI_CONF_END;
553
554 static void radv_init_dri_options(struct radv_instance *instance)
555 {
556 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
557 driParseConfigFiles(&instance->dri_options,
558 &instance->available_dri_options,
559 0, "radv", NULL);
560 }
561
562 VkResult radv_CreateInstance(
563 const VkInstanceCreateInfo* pCreateInfo,
564 const VkAllocationCallbacks* pAllocator,
565 VkInstance* pInstance)
566 {
567 struct radv_instance *instance;
568 VkResult result;
569
570 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
571
572 uint32_t client_version;
573 if (pCreateInfo->pApplicationInfo &&
574 pCreateInfo->pApplicationInfo->apiVersion != 0) {
575 client_version = pCreateInfo->pApplicationInfo->apiVersion;
576 } else {
577 client_version = VK_API_VERSION_1_0;
578 }
579
580 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
581 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
582 if (!instance)
583 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
584
585 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
586
587 if (pAllocator)
588 instance->alloc = *pAllocator;
589 else
590 instance->alloc = default_alloc;
591
592 instance->apiVersion = client_version;
593 instance->physicalDeviceCount = -1;
594
595 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
596 radv_debug_options);
597
598 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
599 radv_perftest_options);
600
601
602 if (instance->debug_flags & RADV_DEBUG_STARTUP)
603 radv_logi("Created an instance");
604
605 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
606 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
607 int index = radv_get_instance_extension_index(ext_name);
608
609 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
610 vk_free2(&default_alloc, pAllocator, instance);
611 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
612 }
613
614 instance->enabled_extensions.extensions[index] = true;
615 }
616
617 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
618 if (result != VK_SUCCESS) {
619 vk_free2(&default_alloc, pAllocator, instance);
620 return vk_error(instance, result);
621 }
622
623 _mesa_locale_init();
624 glsl_type_singleton_init_or_ref();
625
626 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
627
628 radv_init_dri_options(instance);
629 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
630
631 *pInstance = radv_instance_to_handle(instance);
632
633 return VK_SUCCESS;
634 }
635
636 void radv_DestroyInstance(
637 VkInstance _instance,
638 const VkAllocationCallbacks* pAllocator)
639 {
640 RADV_FROM_HANDLE(radv_instance, instance, _instance);
641
642 if (!instance)
643 return;
644
645 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
646 radv_physical_device_finish(instance->physicalDevices + i);
647 }
648
649 VG(VALGRIND_DESTROY_MEMPOOL(instance));
650
651 glsl_type_singleton_decref();
652 _mesa_locale_fini();
653
654 driDestroyOptionCache(&instance->dri_options);
655 driDestroyOptionInfo(&instance->available_dri_options);
656
657 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
658
659 vk_free(&instance->alloc, instance);
660 }
661
662 static VkResult
663 radv_enumerate_devices(struct radv_instance *instance)
664 {
665 /* TODO: Check for more devices ? */
666 drmDevicePtr devices[8];
667 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
668 int max_devices;
669
670 instance->physicalDeviceCount = 0;
671
672 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
673
674 if (instance->debug_flags & RADV_DEBUG_STARTUP)
675 radv_logi("Found %d drm nodes", max_devices);
676
677 if (max_devices < 1)
678 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
679
680 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
681 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
682 devices[i]->bustype == DRM_BUS_PCI &&
683 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
684
685 result = radv_physical_device_init(instance->physicalDevices +
686 instance->physicalDeviceCount,
687 instance,
688 devices[i]);
689 if (result == VK_SUCCESS)
690 ++instance->physicalDeviceCount;
691 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
692 break;
693 }
694 }
695 drmFreeDevices(devices, max_devices);
696
697 return result;
698 }
699
700 VkResult radv_EnumeratePhysicalDevices(
701 VkInstance _instance,
702 uint32_t* pPhysicalDeviceCount,
703 VkPhysicalDevice* pPhysicalDevices)
704 {
705 RADV_FROM_HANDLE(radv_instance, instance, _instance);
706 VkResult result;
707
708 if (instance->physicalDeviceCount < 0) {
709 result = radv_enumerate_devices(instance);
710 if (result != VK_SUCCESS &&
711 result != VK_ERROR_INCOMPATIBLE_DRIVER)
712 return result;
713 }
714
715 if (!pPhysicalDevices) {
716 *pPhysicalDeviceCount = instance->physicalDeviceCount;
717 } else {
718 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
719 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
720 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
721 }
722
723 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
724 : VK_SUCCESS;
725 }
726
727 VkResult radv_EnumeratePhysicalDeviceGroups(
728 VkInstance _instance,
729 uint32_t* pPhysicalDeviceGroupCount,
730 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
731 {
732 RADV_FROM_HANDLE(radv_instance, instance, _instance);
733 VkResult result;
734
735 if (instance->physicalDeviceCount < 0) {
736 result = radv_enumerate_devices(instance);
737 if (result != VK_SUCCESS &&
738 result != VK_ERROR_INCOMPATIBLE_DRIVER)
739 return result;
740 }
741
742 if (!pPhysicalDeviceGroupProperties) {
743 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
744 } else {
745 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
746 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
747 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
748 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
749 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
750 }
751 }
752 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
753 : VK_SUCCESS;
754 }
755
756 void radv_GetPhysicalDeviceFeatures(
757 VkPhysicalDevice physicalDevice,
758 VkPhysicalDeviceFeatures* pFeatures)
759 {
760 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
761 memset(pFeatures, 0, sizeof(*pFeatures));
762
763 *pFeatures = (VkPhysicalDeviceFeatures) {
764 .robustBufferAccess = true,
765 .fullDrawIndexUint32 = true,
766 .imageCubeArray = true,
767 .independentBlend = true,
768 .geometryShader = true,
769 .tessellationShader = true,
770 .sampleRateShading = true,
771 .dualSrcBlend = true,
772 .logicOp = true,
773 .multiDrawIndirect = true,
774 .drawIndirectFirstInstance = true,
775 .depthClamp = true,
776 .depthBiasClamp = true,
777 .fillModeNonSolid = true,
778 .depthBounds = true,
779 .wideLines = true,
780 .largePoints = true,
781 .alphaToOne = true,
782 .multiViewport = true,
783 .samplerAnisotropy = true,
784 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
785 .textureCompressionASTC_LDR = false,
786 .textureCompressionBC = true,
787 .occlusionQueryPrecise = true,
788 .pipelineStatisticsQuery = true,
789 .vertexPipelineStoresAndAtomics = true,
790 .fragmentStoresAndAtomics = true,
791 .shaderTessellationAndGeometryPointSize = true,
792 .shaderImageGatherExtended = true,
793 .shaderStorageImageExtendedFormats = true,
794 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
795 .shaderUniformBufferArrayDynamicIndexing = true,
796 .shaderSampledImageArrayDynamicIndexing = true,
797 .shaderStorageBufferArrayDynamicIndexing = true,
798 .shaderStorageImageArrayDynamicIndexing = true,
799 .shaderStorageImageReadWithoutFormat = true,
800 .shaderStorageImageWriteWithoutFormat = true,
801 .shaderClipDistance = true,
802 .shaderCullDistance = true,
803 .shaderFloat64 = true,
804 .shaderInt64 = true,
805 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
806 .sparseBinding = true,
807 .variableMultisampleRate = true,
808 .inheritedQueries = true,
809 };
810 }
811
812 void radv_GetPhysicalDeviceFeatures2(
813 VkPhysicalDevice physicalDevice,
814 VkPhysicalDeviceFeatures2 *pFeatures)
815 {
816 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
817 vk_foreach_struct(ext, pFeatures->pNext) {
818 switch (ext->sType) {
819 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
820 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
821 features->variablePointersStorageBuffer = true;
822 features->variablePointers = true;
823 break;
824 }
825 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
826 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
827 features->multiview = true;
828 features->multiviewGeometryShader = true;
829 features->multiviewTessellationShader = true;
830 break;
831 }
832 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
833 VkPhysicalDeviceShaderDrawParametersFeatures *features =
834 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
835 features->shaderDrawParameters = true;
836 break;
837 }
838 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
839 VkPhysicalDeviceProtectedMemoryFeatures *features =
840 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
841 features->protectedMemory = false;
842 break;
843 }
844 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
845 VkPhysicalDevice16BitStorageFeatures *features =
846 (VkPhysicalDevice16BitStorageFeatures*)ext;
847 bool enabled = pdevice->rad_info.chip_class >= GFX8;
848 features->storageBuffer16BitAccess = enabled;
849 features->uniformAndStorageBuffer16BitAccess = enabled;
850 features->storagePushConstant16 = enabled;
851 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
852 break;
853 }
854 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
855 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
856 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
857 features->samplerYcbcrConversion = true;
858 break;
859 }
860 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
861 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
862 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
863 features->shaderInputAttachmentArrayDynamicIndexing = true;
864 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
865 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
866 features->shaderUniformBufferArrayNonUniformIndexing = true;
867 features->shaderSampledImageArrayNonUniformIndexing = true;
868 features->shaderStorageBufferArrayNonUniformIndexing = true;
869 features->shaderStorageImageArrayNonUniformIndexing = true;
870 features->shaderInputAttachmentArrayNonUniformIndexing = true;
871 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
872 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
873 features->descriptorBindingUniformBufferUpdateAfterBind = true;
874 features->descriptorBindingSampledImageUpdateAfterBind = true;
875 features->descriptorBindingStorageImageUpdateAfterBind = true;
876 features->descriptorBindingStorageBufferUpdateAfterBind = true;
877 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
878 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
879 features->descriptorBindingUpdateUnusedWhilePending = true;
880 features->descriptorBindingPartiallyBound = true;
881 features->descriptorBindingVariableDescriptorCount = true;
882 features->runtimeDescriptorArray = true;
883 break;
884 }
885 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
886 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
887 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
888 features->conditionalRendering = true;
889 features->inheritedConditionalRendering = false;
890 break;
891 }
892 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
893 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
894 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
895 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
896 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
897 break;
898 }
899 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
900 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
901 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
902 features->transformFeedback = true;
903 features->geometryStreams = true;
904 break;
905 }
906 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
907 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
908 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
909 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
910 break;
911 }
912 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
913 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
914 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
915 features->memoryPriority = VK_TRUE;
916 break;
917 }
918 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
919 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
920 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
921 features->bufferDeviceAddress = true;
922 features->bufferDeviceAddressCaptureReplay = false;
923 features->bufferDeviceAddressMultiDevice = false;
924 break;
925 }
926 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
927 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
928 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
929 features->depthClipEnable = true;
930 break;
931 }
932 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
933 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
934 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
935 features->hostQueryReset = true;
936 break;
937 }
938 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
939 VkPhysicalDevice8BitStorageFeaturesKHR *features =
940 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
941 bool enabled = pdevice->rad_info.chip_class >= GFX8;
942 features->storageBuffer8BitAccess = enabled;
943 features->uniformAndStorageBuffer8BitAccess = enabled;
944 features->storagePushConstant8 = enabled;
945 break;
946 }
947 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
948 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
949 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
950 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
951 features->shaderInt8 = true;
952 break;
953 }
954 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
955 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
956 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
957 /* TODO: Enable this once the driver supports 64-bit
958 * compare&swap atomic operations.
959 */
960 features->shaderBufferInt64Atomics = false;
961 features->shaderSharedInt64Atomics = false;
962 break;
963 }
964 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
965 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
966 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
967
968 features->inlineUniformBlock = true;
969 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
970 break;
971 }
972 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
973 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
974 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
975 features->computeDerivativeGroupQuads = false;
976 features->computeDerivativeGroupLinear = true;
977 break;
978 }
979 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
980 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
981 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
982 features->ycbcrImageArrays = true;
983 break;
984 }
985 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
986 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
987 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
988 features->uniformBufferStandardLayout = true;
989 break;
990 }
991 default:
992 break;
993 }
994 }
995 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
996 }
997
998 void radv_GetPhysicalDeviceProperties(
999 VkPhysicalDevice physicalDevice,
1000 VkPhysicalDeviceProperties* pProperties)
1001 {
1002 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1003 VkSampleCountFlags sample_counts = 0xf;
1004
1005 /* make sure that the entire descriptor set is addressable with a signed
1006 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1007 * be at most 2 GiB. the combined image & samples object count as one of
1008 * both. This limit is for the pipeline layout, not for the set layout, but
1009 * there is no set limit, so we just set a pipeline limit. I don't think
1010 * any app is going to hit this soon. */
1011 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1012 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1013 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1014 32 /* sampler, largest when combined with image */ +
1015 64 /* sampled image */ +
1016 64 /* storage image */);
1017
1018 VkPhysicalDeviceLimits limits = {
1019 .maxImageDimension1D = (1 << 14),
1020 .maxImageDimension2D = (1 << 14),
1021 .maxImageDimension3D = (1 << 11),
1022 .maxImageDimensionCube = (1 << 14),
1023 .maxImageArrayLayers = (1 << 11),
1024 .maxTexelBufferElements = 128 * 1024 * 1024,
1025 .maxUniformBufferRange = UINT32_MAX,
1026 .maxStorageBufferRange = UINT32_MAX,
1027 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1028 .maxMemoryAllocationCount = UINT32_MAX,
1029 .maxSamplerAllocationCount = 64 * 1024,
1030 .bufferImageGranularity = 64, /* A cache line */
1031 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1032 .maxBoundDescriptorSets = MAX_SETS,
1033 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1034 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1035 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1036 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1037 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1038 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1039 .maxPerStageResources = max_descriptor_set_size,
1040 .maxDescriptorSetSamplers = max_descriptor_set_size,
1041 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1042 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1043 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1044 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1045 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1046 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1047 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1048 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1049 .maxVertexInputBindings = MAX_VBS,
1050 .maxVertexInputAttributeOffset = 2047,
1051 .maxVertexInputBindingStride = 2048,
1052 .maxVertexOutputComponents = 128,
1053 .maxTessellationGenerationLevel = 64,
1054 .maxTessellationPatchSize = 32,
1055 .maxTessellationControlPerVertexInputComponents = 128,
1056 .maxTessellationControlPerVertexOutputComponents = 128,
1057 .maxTessellationControlPerPatchOutputComponents = 120,
1058 .maxTessellationControlTotalOutputComponents = 4096,
1059 .maxTessellationEvaluationInputComponents = 128,
1060 .maxTessellationEvaluationOutputComponents = 128,
1061 .maxGeometryShaderInvocations = 127,
1062 .maxGeometryInputComponents = 64,
1063 .maxGeometryOutputComponents = 128,
1064 .maxGeometryOutputVertices = 256,
1065 .maxGeometryTotalOutputComponents = 1024,
1066 .maxFragmentInputComponents = 128,
1067 .maxFragmentOutputAttachments = 8,
1068 .maxFragmentDualSrcAttachments = 1,
1069 .maxFragmentCombinedOutputResources = 8,
1070 .maxComputeSharedMemorySize = 32768,
1071 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1072 .maxComputeWorkGroupInvocations = 2048,
1073 .maxComputeWorkGroupSize = {
1074 2048,
1075 2048,
1076 2048
1077 },
1078 .subPixelPrecisionBits = 8,
1079 .subTexelPrecisionBits = 8,
1080 .mipmapPrecisionBits = 8,
1081 .maxDrawIndexedIndexValue = UINT32_MAX,
1082 .maxDrawIndirectCount = UINT32_MAX,
1083 .maxSamplerLodBias = 16,
1084 .maxSamplerAnisotropy = 16,
1085 .maxViewports = MAX_VIEWPORTS,
1086 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1087 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1088 .viewportSubPixelBits = 8,
1089 .minMemoryMapAlignment = 4096, /* A page */
1090 .minTexelBufferOffsetAlignment = 1,
1091 .minUniformBufferOffsetAlignment = 4,
1092 .minStorageBufferOffsetAlignment = 4,
1093 .minTexelOffset = -32,
1094 .maxTexelOffset = 31,
1095 .minTexelGatherOffset = -32,
1096 .maxTexelGatherOffset = 31,
1097 .minInterpolationOffset = -2,
1098 .maxInterpolationOffset = 2,
1099 .subPixelInterpolationOffsetBits = 8,
1100 .maxFramebufferWidth = (1 << 14),
1101 .maxFramebufferHeight = (1 << 14),
1102 .maxFramebufferLayers = (1 << 10),
1103 .framebufferColorSampleCounts = sample_counts,
1104 .framebufferDepthSampleCounts = sample_counts,
1105 .framebufferStencilSampleCounts = sample_counts,
1106 .framebufferNoAttachmentsSampleCounts = sample_counts,
1107 .maxColorAttachments = MAX_RTS,
1108 .sampledImageColorSampleCounts = sample_counts,
1109 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1110 .sampledImageDepthSampleCounts = sample_counts,
1111 .sampledImageStencilSampleCounts = sample_counts,
1112 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1113 .maxSampleMaskWords = 1,
1114 .timestampComputeAndGraphics = true,
1115 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1116 .maxClipDistances = 8,
1117 .maxCullDistances = 8,
1118 .maxCombinedClipAndCullDistances = 8,
1119 .discreteQueuePriorities = 2,
1120 .pointSizeRange = { 0.0, 8192.0 },
1121 .lineWidthRange = { 0.0, 7.9921875 },
1122 .pointSizeGranularity = (1.0 / 8.0),
1123 .lineWidthGranularity = (1.0 / 128.0),
1124 .strictLines = false, /* FINISHME */
1125 .standardSampleLocations = true,
1126 .optimalBufferCopyOffsetAlignment = 128,
1127 .optimalBufferCopyRowPitchAlignment = 128,
1128 .nonCoherentAtomSize = 64,
1129 };
1130
1131 *pProperties = (VkPhysicalDeviceProperties) {
1132 .apiVersion = radv_physical_device_api_version(pdevice),
1133 .driverVersion = vk_get_driver_version(),
1134 .vendorID = ATI_VENDOR_ID,
1135 .deviceID = pdevice->rad_info.pci_id,
1136 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1137 .limits = limits,
1138 .sparseProperties = {0},
1139 };
1140
1141 strcpy(pProperties->deviceName, pdevice->name);
1142 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1143 }
1144
1145 void radv_GetPhysicalDeviceProperties2(
1146 VkPhysicalDevice physicalDevice,
1147 VkPhysicalDeviceProperties2 *pProperties)
1148 {
1149 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1150 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1151
1152 vk_foreach_struct(ext, pProperties->pNext) {
1153 switch (ext->sType) {
1154 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1155 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1156 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1157 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1158 break;
1159 }
1160 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1161 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1162 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1163 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1164 properties->deviceLUIDValid = false;
1165 break;
1166 }
1167 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1168 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1169 properties->maxMultiviewViewCount = MAX_VIEWS;
1170 properties->maxMultiviewInstanceIndex = INT_MAX;
1171 break;
1172 }
1173 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1174 VkPhysicalDevicePointClippingProperties *properties =
1175 (VkPhysicalDevicePointClippingProperties*)ext;
1176 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1177 break;
1178 }
1179 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1180 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1181 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1182 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1183 break;
1184 }
1185 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1186 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1187 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1188 properties->minImportedHostPointerAlignment = 4096;
1189 break;
1190 }
1191 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1192 VkPhysicalDeviceSubgroupProperties *properties =
1193 (VkPhysicalDeviceSubgroupProperties*)ext;
1194 properties->subgroupSize = 64;
1195 properties->supportedStages = VK_SHADER_STAGE_ALL;
1196 properties->supportedOperations =
1197 VK_SUBGROUP_FEATURE_BASIC_BIT |
1198 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1199 VK_SUBGROUP_FEATURE_QUAD_BIT |
1200 VK_SUBGROUP_FEATURE_VOTE_BIT;
1201 if (pdevice->rad_info.chip_class >= GFX8) {
1202 properties->supportedOperations |=
1203 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1204 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1205 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1206 }
1207 properties->quadOperationsInAllStages = true;
1208 break;
1209 }
1210 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1211 VkPhysicalDeviceMaintenance3Properties *properties =
1212 (VkPhysicalDeviceMaintenance3Properties*)ext;
1213 /* Make sure everything is addressable by a signed 32-bit int, and
1214 * our largest descriptors are 96 bytes. */
1215 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1216 /* Our buffer size fields allow only this much */
1217 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1218 break;
1219 }
1220 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1221 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1222 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1223 /* GFX6-8 only support single channel min/max filter. */
1224 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1225 properties->filterMinmaxSingleComponentFormats = true;
1226 break;
1227 }
1228 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1229 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1230 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1231
1232 /* Shader engines. */
1233 properties->shaderEngineCount =
1234 pdevice->rad_info.max_se;
1235 properties->shaderArraysPerEngineCount =
1236 pdevice->rad_info.max_sh_per_se;
1237 properties->computeUnitsPerShaderArray =
1238 pdevice->rad_info.num_good_cu_per_sh;
1239 properties->simdPerComputeUnit = 4;
1240 properties->wavefrontsPerSimd =
1241 pdevice->rad_info.family == CHIP_TONGA ||
1242 pdevice->rad_info.family == CHIP_ICELAND ||
1243 pdevice->rad_info.family == CHIP_POLARIS10 ||
1244 pdevice->rad_info.family == CHIP_POLARIS11 ||
1245 pdevice->rad_info.family == CHIP_POLARIS12 ||
1246 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1247 properties->wavefrontSize = 64;
1248
1249 /* SGPR. */
1250 properties->sgprsPerSimd =
1251 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1252 properties->minSgprAllocation =
1253 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1254 properties->maxSgprAllocation =
1255 pdevice->rad_info.family == CHIP_TONGA ||
1256 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1257 properties->sgprAllocationGranularity =
1258 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1259
1260 /* VGPR. */
1261 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1262 properties->minVgprAllocation = 4;
1263 properties->maxVgprAllocation = 256;
1264 properties->vgprAllocationGranularity = 4;
1265 break;
1266 }
1267 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1268 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1269 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1270 properties->maxVertexAttribDivisor = UINT32_MAX;
1271 break;
1272 }
1273 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1274 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1275 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1276 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1277 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1278 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1279 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1280 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1281 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1282 properties->robustBufferAccessUpdateAfterBind = false;
1283 properties->quadDivergentImplicitLod = false;
1284
1285 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1286 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1287 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1288 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1289 32 /* sampler, largest when combined with image */ +
1290 64 /* sampled image */ +
1291 64 /* storage image */);
1292 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1293 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1294 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1295 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1296 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1297 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1298 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1299 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1300 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1301 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1302 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1303 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1304 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1305 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1306 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1307 break;
1308 }
1309 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1310 VkPhysicalDeviceProtectedMemoryProperties *properties =
1311 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1312 properties->protectedNoFault = false;
1313 break;
1314 }
1315 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1316 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1317 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1318 properties->primitiveOverestimationSize = 0;
1319 properties->maxExtraPrimitiveOverestimationSize = 0;
1320 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1321 properties->primitiveUnderestimation = VK_FALSE;
1322 properties->conservativePointAndLineRasterization = VK_FALSE;
1323 properties->degenerateTrianglesRasterized = VK_FALSE;
1324 properties->degenerateLinesRasterized = VK_FALSE;
1325 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1326 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1327 break;
1328 }
1329 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1330 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1331 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1332 properties->pciDomain = pdevice->bus_info.domain;
1333 properties->pciBus = pdevice->bus_info.bus;
1334 properties->pciDevice = pdevice->bus_info.dev;
1335 properties->pciFunction = pdevice->bus_info.func;
1336 break;
1337 }
1338 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1339 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1340 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1341
1342 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1343 snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE_KHR, "radv");
1344 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1345 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1346 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1347
1348 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1349 .major = 1,
1350 .minor = 1,
1351 .subminor = 2,
1352 .patch = 0,
1353 };
1354 break;
1355 }
1356 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1357 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1358 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1359 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1360 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1361 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1362 properties->maxTransformFeedbackStreamDataSize = 512;
1363 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1364 properties->maxTransformFeedbackBufferDataStride = 512;
1365 properties->transformFeedbackQueries = true;
1366 properties->transformFeedbackStreamsLinesTriangles = true;
1367 properties->transformFeedbackRasterizationStreamSelect = false;
1368 properties->transformFeedbackDraw = true;
1369 break;
1370 }
1371 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1372 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1373 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1374
1375 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1376 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1377 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1378 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1379 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1380 break;
1381 }
1382 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1383 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1384 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1385 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1386 VK_SAMPLE_COUNT_4_BIT |
1387 VK_SAMPLE_COUNT_8_BIT;
1388 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1389 properties->sampleLocationCoordinateRange[0] = 0.0f;
1390 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1391 properties->sampleLocationSubPixelBits = 4;
1392 properties->variableSampleLocations = VK_FALSE;
1393 break;
1394 }
1395 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1396 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1397 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1398
1399 /* We support all of the depth resolve modes */
1400 properties->supportedDepthResolveModes =
1401 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1402 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1403 VK_RESOLVE_MODE_MIN_BIT_KHR |
1404 VK_RESOLVE_MODE_MAX_BIT_KHR;
1405
1406 /* Average doesn't make sense for stencil so we don't support that */
1407 properties->supportedStencilResolveModes =
1408 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1409 VK_RESOLVE_MODE_MIN_BIT_KHR |
1410 VK_RESOLVE_MODE_MAX_BIT_KHR;
1411
1412 properties->independentResolveNone = VK_TRUE;
1413 properties->independentResolve = VK_TRUE;
1414 break;
1415 }
1416 default:
1417 break;
1418 }
1419 }
1420 }
1421
1422 static void radv_get_physical_device_queue_family_properties(
1423 struct radv_physical_device* pdevice,
1424 uint32_t* pCount,
1425 VkQueueFamilyProperties** pQueueFamilyProperties)
1426 {
1427 int num_queue_families = 1;
1428 int idx;
1429 if (pdevice->rad_info.num_compute_rings > 0 &&
1430 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1431 num_queue_families++;
1432
1433 if (pQueueFamilyProperties == NULL) {
1434 *pCount = num_queue_families;
1435 return;
1436 }
1437
1438 if (!*pCount)
1439 return;
1440
1441 idx = 0;
1442 if (*pCount >= 1) {
1443 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1444 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1445 VK_QUEUE_COMPUTE_BIT |
1446 VK_QUEUE_TRANSFER_BIT |
1447 VK_QUEUE_SPARSE_BINDING_BIT,
1448 .queueCount = 1,
1449 .timestampValidBits = 64,
1450 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1451 };
1452 idx++;
1453 }
1454
1455 if (pdevice->rad_info.num_compute_rings > 0 &&
1456 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1457 if (*pCount > idx) {
1458 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1459 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1460 VK_QUEUE_TRANSFER_BIT |
1461 VK_QUEUE_SPARSE_BINDING_BIT,
1462 .queueCount = pdevice->rad_info.num_compute_rings,
1463 .timestampValidBits = 64,
1464 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1465 };
1466 idx++;
1467 }
1468 }
1469 *pCount = idx;
1470 }
1471
1472 void radv_GetPhysicalDeviceQueueFamilyProperties(
1473 VkPhysicalDevice physicalDevice,
1474 uint32_t* pCount,
1475 VkQueueFamilyProperties* pQueueFamilyProperties)
1476 {
1477 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1478 if (!pQueueFamilyProperties) {
1479 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1480 return;
1481 }
1482 VkQueueFamilyProperties *properties[] = {
1483 pQueueFamilyProperties + 0,
1484 pQueueFamilyProperties + 1,
1485 pQueueFamilyProperties + 2,
1486 };
1487 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1488 assert(*pCount <= 3);
1489 }
1490
1491 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1492 VkPhysicalDevice physicalDevice,
1493 uint32_t* pCount,
1494 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1495 {
1496 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1497 if (!pQueueFamilyProperties) {
1498 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1499 return;
1500 }
1501 VkQueueFamilyProperties *properties[] = {
1502 &pQueueFamilyProperties[0].queueFamilyProperties,
1503 &pQueueFamilyProperties[1].queueFamilyProperties,
1504 &pQueueFamilyProperties[2].queueFamilyProperties,
1505 };
1506 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1507 assert(*pCount <= 3);
1508 }
1509
1510 void radv_GetPhysicalDeviceMemoryProperties(
1511 VkPhysicalDevice physicalDevice,
1512 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1513 {
1514 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1515
1516 *pMemoryProperties = physical_device->memory_properties;
1517 }
1518
1519 static void
1520 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1521 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1522 {
1523 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1524 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1525 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1526 uint64_t vram_size = radv_get_vram_size(device);
1527 uint64_t gtt_size = device->rad_info.gart_size;
1528 uint64_t heap_budget, heap_usage;
1529
1530 /* For all memory heaps, the computation of budget is as follow:
1531 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1532 *
1533 * The Vulkan spec 1.1.97 says that the budget should include any
1534 * currently allocated device memory.
1535 *
1536 * Note that the application heap usages are not really accurate (eg.
1537 * in presence of shared buffers).
1538 */
1539 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1540 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1541
1542 switch (device->mem_type_indices[i]) {
1543 case RADV_MEM_TYPE_VRAM:
1544 heap_usage = device->ws->query_value(device->ws,
1545 RADEON_ALLOCATED_VRAM);
1546
1547 heap_budget = vram_size -
1548 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1549 heap_usage;
1550
1551 memoryBudget->heapBudget[heap_index] = heap_budget;
1552 memoryBudget->heapUsage[heap_index] = heap_usage;
1553 break;
1554 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1555 heap_usage = device->ws->query_value(device->ws,
1556 RADEON_ALLOCATED_VRAM_VIS);
1557
1558 heap_budget = visible_vram_size -
1559 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1560 heap_usage;
1561
1562 memoryBudget->heapBudget[heap_index] = heap_budget;
1563 memoryBudget->heapUsage[heap_index] = heap_usage;
1564 break;
1565 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1566 heap_usage = device->ws->query_value(device->ws,
1567 RADEON_ALLOCATED_GTT);
1568
1569 heap_budget = gtt_size -
1570 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1571 heap_usage;
1572
1573 memoryBudget->heapBudget[heap_index] = heap_budget;
1574 memoryBudget->heapUsage[heap_index] = heap_usage;
1575 break;
1576 default:
1577 break;
1578 }
1579 }
1580
1581 /* The heapBudget and heapUsage values must be zero for array elements
1582 * greater than or equal to
1583 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1584 */
1585 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1586 memoryBudget->heapBudget[i] = 0;
1587 memoryBudget->heapUsage[i] = 0;
1588 }
1589 }
1590
1591 void radv_GetPhysicalDeviceMemoryProperties2(
1592 VkPhysicalDevice physicalDevice,
1593 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1594 {
1595 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1596 &pMemoryProperties->memoryProperties);
1597
1598 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1599 vk_find_struct(pMemoryProperties->pNext,
1600 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1601 if (memory_budget)
1602 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1603 }
1604
1605 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1606 VkDevice _device,
1607 VkExternalMemoryHandleTypeFlagBits handleType,
1608 const void *pHostPointer,
1609 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1610 {
1611 RADV_FROM_HANDLE(radv_device, device, _device);
1612
1613 switch (handleType)
1614 {
1615 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1616 const struct radv_physical_device *physical_device = device->physical_device;
1617 uint32_t memoryTypeBits = 0;
1618 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1619 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1620 memoryTypeBits = (1 << i);
1621 break;
1622 }
1623 }
1624 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1625 return VK_SUCCESS;
1626 }
1627 default:
1628 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1629 }
1630 }
1631
1632 static enum radeon_ctx_priority
1633 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1634 {
1635 /* Default to MEDIUM when a specific global priority isn't requested */
1636 if (!pObj)
1637 return RADEON_CTX_PRIORITY_MEDIUM;
1638
1639 switch(pObj->globalPriority) {
1640 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1641 return RADEON_CTX_PRIORITY_REALTIME;
1642 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1643 return RADEON_CTX_PRIORITY_HIGH;
1644 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1645 return RADEON_CTX_PRIORITY_MEDIUM;
1646 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1647 return RADEON_CTX_PRIORITY_LOW;
1648 default:
1649 unreachable("Illegal global priority value");
1650 return RADEON_CTX_PRIORITY_INVALID;
1651 }
1652 }
1653
1654 static int
1655 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1656 uint32_t queue_family_index, int idx,
1657 VkDeviceQueueCreateFlags flags,
1658 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1659 {
1660 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1661 queue->device = device;
1662 queue->queue_family_index = queue_family_index;
1663 queue->queue_idx = idx;
1664 queue->priority = radv_get_queue_global_priority(global_priority);
1665 queue->flags = flags;
1666
1667 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1668 if (!queue->hw_ctx)
1669 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1670
1671 return VK_SUCCESS;
1672 }
1673
1674 static void
1675 radv_queue_finish(struct radv_queue *queue)
1676 {
1677 if (queue->hw_ctx)
1678 queue->device->ws->ctx_destroy(queue->hw_ctx);
1679
1680 if (queue->initial_full_flush_preamble_cs)
1681 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1682 if (queue->initial_preamble_cs)
1683 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1684 if (queue->continue_preamble_cs)
1685 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1686 if (queue->descriptor_bo)
1687 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1688 if (queue->scratch_bo)
1689 queue->device->ws->buffer_destroy(queue->scratch_bo);
1690 if (queue->esgs_ring_bo)
1691 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1692 if (queue->gsvs_ring_bo)
1693 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1694 if (queue->tess_rings_bo)
1695 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1696 if (queue->compute_scratch_bo)
1697 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1698 }
1699
1700 static void
1701 radv_bo_list_init(struct radv_bo_list *bo_list)
1702 {
1703 pthread_mutex_init(&bo_list->mutex, NULL);
1704 bo_list->list.count = bo_list->capacity = 0;
1705 bo_list->list.bos = NULL;
1706 }
1707
1708 static void
1709 radv_bo_list_finish(struct radv_bo_list *bo_list)
1710 {
1711 free(bo_list->list.bos);
1712 pthread_mutex_destroy(&bo_list->mutex);
1713 }
1714
1715 static VkResult radv_bo_list_add(struct radv_device *device,
1716 struct radeon_winsys_bo *bo)
1717 {
1718 struct radv_bo_list *bo_list = &device->bo_list;
1719
1720 if (bo->is_local)
1721 return VK_SUCCESS;
1722
1723 if (unlikely(!device->use_global_bo_list))
1724 return VK_SUCCESS;
1725
1726 pthread_mutex_lock(&bo_list->mutex);
1727 if (bo_list->list.count == bo_list->capacity) {
1728 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1729 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1730
1731 if (!data) {
1732 pthread_mutex_unlock(&bo_list->mutex);
1733 return VK_ERROR_OUT_OF_HOST_MEMORY;
1734 }
1735
1736 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1737 bo_list->capacity = capacity;
1738 }
1739
1740 bo_list->list.bos[bo_list->list.count++] = bo;
1741 pthread_mutex_unlock(&bo_list->mutex);
1742 return VK_SUCCESS;
1743 }
1744
1745 static void radv_bo_list_remove(struct radv_device *device,
1746 struct radeon_winsys_bo *bo)
1747 {
1748 struct radv_bo_list *bo_list = &device->bo_list;
1749
1750 if (bo->is_local)
1751 return;
1752
1753 if (unlikely(!device->use_global_bo_list))
1754 return;
1755
1756 pthread_mutex_lock(&bo_list->mutex);
1757 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1758 if (bo_list->list.bos[i] == bo) {
1759 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1760 --bo_list->list.count;
1761 break;
1762 }
1763 }
1764 pthread_mutex_unlock(&bo_list->mutex);
1765 }
1766
1767 static void
1768 radv_device_init_gs_info(struct radv_device *device)
1769 {
1770 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1771 device->physical_device->rad_info.family);
1772 }
1773
1774 static int radv_get_device_extension_index(const char *name)
1775 {
1776 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1777 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1778 return i;
1779 }
1780 return -1;
1781 }
1782
1783 static int
1784 radv_get_int_debug_option(const char *name, int default_value)
1785 {
1786 const char *str;
1787 int result;
1788
1789 str = getenv(name);
1790 if (!str) {
1791 result = default_value;
1792 } else {
1793 char *endptr;
1794
1795 result = strtol(str, &endptr, 0);
1796 if (str == endptr) {
1797 /* No digits founs. */
1798 result = default_value;
1799 }
1800 }
1801
1802 return result;
1803 }
1804
1805 VkResult radv_CreateDevice(
1806 VkPhysicalDevice physicalDevice,
1807 const VkDeviceCreateInfo* pCreateInfo,
1808 const VkAllocationCallbacks* pAllocator,
1809 VkDevice* pDevice)
1810 {
1811 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1812 VkResult result;
1813 struct radv_device *device;
1814
1815 bool keep_shader_info = false;
1816
1817 /* Check enabled features */
1818 if (pCreateInfo->pEnabledFeatures) {
1819 VkPhysicalDeviceFeatures supported_features;
1820 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1821 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1822 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1823 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1824 for (uint32_t i = 0; i < num_features; i++) {
1825 if (enabled_feature[i] && !supported_feature[i])
1826 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1827 }
1828 }
1829
1830 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1831 sizeof(*device), 8,
1832 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1833 if (!device)
1834 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1835
1836 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1837 device->instance = physical_device->instance;
1838 device->physical_device = physical_device;
1839
1840 device->ws = physical_device->ws;
1841 if (pAllocator)
1842 device->alloc = *pAllocator;
1843 else
1844 device->alloc = physical_device->instance->alloc;
1845
1846 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1847 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1848 int index = radv_get_device_extension_index(ext_name);
1849 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1850 vk_free(&device->alloc, device);
1851 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1852 }
1853
1854 device->enabled_extensions.extensions[index] = true;
1855 }
1856
1857 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1858
1859 /* With update after bind we can't attach bo's to the command buffer
1860 * from the descriptor set anymore, so we have to use a global BO list.
1861 */
1862 device->use_global_bo_list =
1863 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1864 device->enabled_extensions.EXT_descriptor_indexing ||
1865 device->enabled_extensions.EXT_buffer_device_address;
1866
1867 mtx_init(&device->shader_slab_mutex, mtx_plain);
1868 list_inithead(&device->shader_slabs);
1869
1870 radv_bo_list_init(&device->bo_list);
1871
1872 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1873 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1874 uint32_t qfi = queue_create->queueFamilyIndex;
1875 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1876 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1877
1878 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1879
1880 device->queues[qfi] = vk_alloc(&device->alloc,
1881 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1882 if (!device->queues[qfi]) {
1883 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1884 goto fail;
1885 }
1886
1887 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1888
1889 device->queue_count[qfi] = queue_create->queueCount;
1890
1891 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1892 result = radv_queue_init(device, &device->queues[qfi][q],
1893 qfi, q, queue_create->flags,
1894 global_priority);
1895 if (result != VK_SUCCESS)
1896 goto fail;
1897 }
1898 }
1899
1900 /* TODO: Enable binning for GFX10. */
1901 device->pbb_allowed = device->physical_device->rad_info.chip_class == GFX9 &&
1902 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1903
1904 /* Disabled and not implemented for now. */
1905 device->dfsm_allowed = device->pbb_allowed &&
1906 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1907 device->physical_device->rad_info.family == CHIP_RAVEN2);
1908
1909 #ifdef ANDROID
1910 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1911 #endif
1912
1913 /* The maximum number of scratch waves. Scratch space isn't divided
1914 * evenly between CUs. The number is only a function of the number of CUs.
1915 * We can decrease the constant to decrease the scratch buffer size.
1916 *
1917 * sctx->scratch_waves must be >= the maximum possible size of
1918 * 1 threadgroup, so that the hw doesn't hang from being unable
1919 * to start any.
1920 *
1921 * The recommended value is 4 per CU at most. Higher numbers don't
1922 * bring much benefit, but they still occupy chip resources (think
1923 * async compute). I've seen ~2% performance difference between 4 and 32.
1924 */
1925 uint32_t max_threads_per_block = 2048;
1926 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1927 max_threads_per_block / 64);
1928
1929 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1930
1931 if (device->physical_device->rad_info.chip_class >= GFX7) {
1932 /* If the KMD allows it (there is a KMD hw register for it),
1933 * allow launching waves out-of-order.
1934 */
1935 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1936 }
1937
1938 radv_device_init_gs_info(device);
1939
1940 device->tess_offchip_block_dw_size =
1941 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1942 device->has_distributed_tess =
1943 device->physical_device->rad_info.chip_class >= GFX8 &&
1944 device->physical_device->rad_info.max_se >= 2;
1945
1946 if (getenv("RADV_TRACE_FILE")) {
1947 const char *filename = getenv("RADV_TRACE_FILE");
1948
1949 keep_shader_info = true;
1950
1951 if (!radv_init_trace(device))
1952 goto fail;
1953
1954 fprintf(stderr, "*****************************************************************************\n");
1955 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1956 fprintf(stderr, "*****************************************************************************\n");
1957
1958 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1959 radv_dump_enabled_options(device, stderr);
1960 }
1961
1962 device->keep_shader_info = keep_shader_info;
1963
1964 result = radv_device_init_meta(device);
1965 if (result != VK_SUCCESS)
1966 goto fail;
1967
1968 radv_device_init_msaa(device);
1969
1970 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1971 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1972 switch (family) {
1973 case RADV_QUEUE_GENERAL:
1974 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1975 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1976 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1977 break;
1978 case RADV_QUEUE_COMPUTE:
1979 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1980 radeon_emit(device->empty_cs[family], 0);
1981 break;
1982 }
1983 device->ws->cs_finalize(device->empty_cs[family]);
1984 }
1985
1986 if (device->physical_device->rad_info.chip_class >= GFX7)
1987 cik_create_gfx_config(device);
1988
1989 VkPipelineCacheCreateInfo ci;
1990 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1991 ci.pNext = NULL;
1992 ci.flags = 0;
1993 ci.pInitialData = NULL;
1994 ci.initialDataSize = 0;
1995 VkPipelineCache pc;
1996 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1997 &ci, NULL, &pc);
1998 if (result != VK_SUCCESS)
1999 goto fail_meta;
2000
2001 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2002
2003 device->force_aniso =
2004 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2005 if (device->force_aniso >= 0) {
2006 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2007 1 << util_logbase2(device->force_aniso));
2008 }
2009
2010 *pDevice = radv_device_to_handle(device);
2011 return VK_SUCCESS;
2012
2013 fail_meta:
2014 radv_device_finish_meta(device);
2015 fail:
2016 radv_bo_list_finish(&device->bo_list);
2017
2018 if (device->trace_bo)
2019 device->ws->buffer_destroy(device->trace_bo);
2020
2021 if (device->gfx_init)
2022 device->ws->buffer_destroy(device->gfx_init);
2023
2024 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2025 for (unsigned q = 0; q < device->queue_count[i]; q++)
2026 radv_queue_finish(&device->queues[i][q]);
2027 if (device->queue_count[i])
2028 vk_free(&device->alloc, device->queues[i]);
2029 }
2030
2031 vk_free(&device->alloc, device);
2032 return result;
2033 }
2034
2035 void radv_DestroyDevice(
2036 VkDevice _device,
2037 const VkAllocationCallbacks* pAllocator)
2038 {
2039 RADV_FROM_HANDLE(radv_device, device, _device);
2040
2041 if (!device)
2042 return;
2043
2044 if (device->trace_bo)
2045 device->ws->buffer_destroy(device->trace_bo);
2046
2047 if (device->gfx_init)
2048 device->ws->buffer_destroy(device->gfx_init);
2049
2050 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2051 for (unsigned q = 0; q < device->queue_count[i]; q++)
2052 radv_queue_finish(&device->queues[i][q]);
2053 if (device->queue_count[i])
2054 vk_free(&device->alloc, device->queues[i]);
2055 if (device->empty_cs[i])
2056 device->ws->cs_destroy(device->empty_cs[i]);
2057 }
2058 radv_device_finish_meta(device);
2059
2060 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2061 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2062
2063 radv_destroy_shader_slabs(device);
2064
2065 radv_bo_list_finish(&device->bo_list);
2066 vk_free(&device->alloc, device);
2067 }
2068
2069 VkResult radv_EnumerateInstanceLayerProperties(
2070 uint32_t* pPropertyCount,
2071 VkLayerProperties* pProperties)
2072 {
2073 if (pProperties == NULL) {
2074 *pPropertyCount = 0;
2075 return VK_SUCCESS;
2076 }
2077
2078 /* None supported at this time */
2079 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2080 }
2081
2082 VkResult radv_EnumerateDeviceLayerProperties(
2083 VkPhysicalDevice physicalDevice,
2084 uint32_t* pPropertyCount,
2085 VkLayerProperties* pProperties)
2086 {
2087 if (pProperties == NULL) {
2088 *pPropertyCount = 0;
2089 return VK_SUCCESS;
2090 }
2091
2092 /* None supported at this time */
2093 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2094 }
2095
2096 void radv_GetDeviceQueue2(
2097 VkDevice _device,
2098 const VkDeviceQueueInfo2* pQueueInfo,
2099 VkQueue* pQueue)
2100 {
2101 RADV_FROM_HANDLE(radv_device, device, _device);
2102 struct radv_queue *queue;
2103
2104 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2105 if (pQueueInfo->flags != queue->flags) {
2106 /* From the Vulkan 1.1.70 spec:
2107 *
2108 * "The queue returned by vkGetDeviceQueue2 must have the same
2109 * flags value from this structure as that used at device
2110 * creation time in a VkDeviceQueueCreateInfo instance. If no
2111 * matching flags were specified at device creation time then
2112 * pQueue will return VK_NULL_HANDLE."
2113 */
2114 *pQueue = VK_NULL_HANDLE;
2115 return;
2116 }
2117
2118 *pQueue = radv_queue_to_handle(queue);
2119 }
2120
2121 void radv_GetDeviceQueue(
2122 VkDevice _device,
2123 uint32_t queueFamilyIndex,
2124 uint32_t queueIndex,
2125 VkQueue* pQueue)
2126 {
2127 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2128 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2129 .queueFamilyIndex = queueFamilyIndex,
2130 .queueIndex = queueIndex
2131 };
2132
2133 radv_GetDeviceQueue2(_device, &info, pQueue);
2134 }
2135
2136 static void
2137 fill_geom_tess_rings(struct radv_queue *queue,
2138 uint32_t *map,
2139 bool add_sample_positions,
2140 uint32_t esgs_ring_size,
2141 struct radeon_winsys_bo *esgs_ring_bo,
2142 uint32_t gsvs_ring_size,
2143 struct radeon_winsys_bo *gsvs_ring_bo,
2144 uint32_t tess_factor_ring_size,
2145 uint32_t tess_offchip_ring_offset,
2146 uint32_t tess_offchip_ring_size,
2147 struct radeon_winsys_bo *tess_rings_bo)
2148 {
2149 uint32_t *desc = &map[4];
2150
2151 if (esgs_ring_bo) {
2152 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2153
2154 /* stride 0, num records - size, add tid, swizzle, elsize4,
2155 index stride 64 */
2156 desc[0] = esgs_va;
2157 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2158 S_008F04_SWIZZLE_ENABLE(true);
2159 desc[2] = esgs_ring_size;
2160 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2161 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2162 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2163 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2164 S_008F0C_ELEMENT_SIZE(1) |
2165 S_008F0C_INDEX_STRIDE(3) |
2166 S_008F0C_ADD_TID_ENABLE(1);
2167
2168 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2169 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2170 S_008F0C_OOB_SELECT(2) |
2171 S_008F0C_RESOURCE_LEVEL(1);
2172 } else {
2173 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2174 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2175 }
2176
2177 /* GS entry for ES->GS ring */
2178 /* stride 0, num records - size, elsize0,
2179 index stride 0 */
2180 desc[4] = esgs_va;
2181 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
2182 desc[6] = esgs_ring_size;
2183 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2184 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2185 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2186 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2187
2188 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2189 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2190 S_008F0C_OOB_SELECT(2) |
2191 S_008F0C_RESOURCE_LEVEL(1);
2192 } else {
2193 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2194 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2195 }
2196 }
2197
2198 desc += 8;
2199
2200 if (gsvs_ring_bo) {
2201 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2202
2203 /* VS entry for GS->VS ring */
2204 /* stride 0, num records - size, elsize0,
2205 index stride 0 */
2206 desc[0] = gsvs_va;
2207 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
2208 desc[2] = gsvs_ring_size;
2209 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2210 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2211 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2212 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2213
2214 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2215 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2216 S_008F0C_OOB_SELECT(2) |
2217 S_008F0C_RESOURCE_LEVEL(1);
2218 } else {
2219 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2220 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2221 }
2222
2223 /* stride gsvs_itemsize, num records 64
2224 elsize 4, index stride 16 */
2225 /* shader will patch stride and desc[2] */
2226 desc[4] = gsvs_va;
2227 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
2228 S_008F04_SWIZZLE_ENABLE(1);
2229 desc[6] = 0;
2230 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2231 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2232 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2233 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2234 S_008F0C_ELEMENT_SIZE(1) |
2235 S_008F0C_INDEX_STRIDE(1) |
2236 S_008F0C_ADD_TID_ENABLE(true);
2237
2238 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2239 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2240 S_008F0C_OOB_SELECT(2) |
2241 S_008F0C_RESOURCE_LEVEL(1);
2242 } else {
2243 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2244 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2245 }
2246
2247 }
2248
2249 desc += 8;
2250
2251 if (tess_rings_bo) {
2252 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2253 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2254
2255 desc[0] = tess_va;
2256 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
2257 desc[2] = tess_factor_ring_size;
2258 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2259 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2260 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2261 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2262
2263 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2264 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2265 S_008F0C_OOB_SELECT(3) |
2266 S_008F0C_RESOURCE_LEVEL(1);
2267 } else {
2268 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2269 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2270 }
2271
2272 desc[4] = tess_offchip_va;
2273 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
2274 desc[6] = tess_offchip_ring_size;
2275 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2276 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2277 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2278 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2279
2280 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2281 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2282 S_008F0C_OOB_SELECT(3) |
2283 S_008F0C_RESOURCE_LEVEL(1);
2284 } else {
2285 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2286 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2287 }
2288 }
2289
2290 desc += 8;
2291
2292 if (add_sample_positions) {
2293 /* add sample positions after all rings */
2294 memcpy(desc, queue->device->sample_locations_1x, 8);
2295 desc += 2;
2296 memcpy(desc, queue->device->sample_locations_2x, 16);
2297 desc += 4;
2298 memcpy(desc, queue->device->sample_locations_4x, 32);
2299 desc += 8;
2300 memcpy(desc, queue->device->sample_locations_8x, 64);
2301 }
2302 }
2303
2304 static unsigned
2305 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2306 {
2307 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2308 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2309 device->physical_device->rad_info.family != CHIP_STONEY;
2310 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2311 unsigned max_offchip_buffers;
2312 unsigned offchip_granularity;
2313 unsigned hs_offchip_param;
2314
2315 /*
2316 * Per RadeonSI:
2317 * This must be one less than the maximum number due to a hw limitation.
2318 * Various hardware bugs need thGFX7
2319 *
2320 * Per AMDVLK:
2321 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2322 * Gfx7 should limit max_offchip_buffers to 508
2323 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2324 *
2325 * Follow AMDVLK here.
2326 */
2327 if (device->physical_device->rad_info.chip_class >= GFX10) {
2328 max_offchip_buffers_per_se = 256;
2329 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2330 device->physical_device->rad_info.chip_class == GFX7 ||
2331 device->physical_device->rad_info.chip_class == GFX6)
2332 --max_offchip_buffers_per_se;
2333
2334 max_offchip_buffers = max_offchip_buffers_per_se *
2335 device->physical_device->rad_info.max_se;
2336
2337 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2338 * around by setting 4K granularity.
2339 */
2340 if (device->tess_offchip_block_dw_size == 4096) {
2341 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2342 offchip_granularity = V_03093C_X_4K_DWORDS;
2343 } else {
2344 assert(device->tess_offchip_block_dw_size == 8192);
2345 offchip_granularity = V_03093C_X_8K_DWORDS;
2346 }
2347
2348 switch (device->physical_device->rad_info.chip_class) {
2349 case GFX6:
2350 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2351 break;
2352 case GFX7:
2353 case GFX8:
2354 case GFX9:
2355 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2356 break;
2357 case GFX10:
2358 break;
2359 default:
2360 break;
2361 }
2362
2363 *max_offchip_buffers_p = max_offchip_buffers;
2364 if (device->physical_device->rad_info.chip_class >= GFX7) {
2365 if (device->physical_device->rad_info.chip_class >= GFX8)
2366 --max_offchip_buffers;
2367 hs_offchip_param =
2368 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2369 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2370 } else {
2371 hs_offchip_param =
2372 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2373 }
2374 return hs_offchip_param;
2375 }
2376
2377 static void
2378 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2379 struct radeon_winsys_bo *esgs_ring_bo,
2380 uint32_t esgs_ring_size,
2381 struct radeon_winsys_bo *gsvs_ring_bo,
2382 uint32_t gsvs_ring_size)
2383 {
2384 if (!esgs_ring_bo && !gsvs_ring_bo)
2385 return;
2386
2387 if (esgs_ring_bo)
2388 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2389
2390 if (gsvs_ring_bo)
2391 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2392
2393 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2394 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2395 radeon_emit(cs, esgs_ring_size >> 8);
2396 radeon_emit(cs, gsvs_ring_size >> 8);
2397 } else {
2398 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2399 radeon_emit(cs, esgs_ring_size >> 8);
2400 radeon_emit(cs, gsvs_ring_size >> 8);
2401 }
2402 }
2403
2404 static void
2405 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2406 unsigned hs_offchip_param, unsigned tf_ring_size,
2407 struct radeon_winsys_bo *tess_rings_bo)
2408 {
2409 uint64_t tf_va;
2410
2411 if (!tess_rings_bo)
2412 return;
2413
2414 tf_va = radv_buffer_get_va(tess_rings_bo);
2415
2416 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2417
2418 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2419 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2420 S_030938_SIZE(tf_ring_size / 4));
2421 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2422 tf_va >> 8);
2423
2424 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2425 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2426 S_030984_BASE_HI(tf_va >> 40));
2427 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2428 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2429 S_030944_BASE_HI(tf_va >> 40));
2430 }
2431 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2432 hs_offchip_param);
2433 } else {
2434 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2435 S_008988_SIZE(tf_ring_size / 4));
2436 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2437 tf_va >> 8);
2438 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2439 hs_offchip_param);
2440 }
2441 }
2442
2443 static void
2444 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2445 struct radeon_winsys_bo *compute_scratch_bo)
2446 {
2447 uint64_t scratch_va;
2448
2449 if (!compute_scratch_bo)
2450 return;
2451
2452 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2453
2454 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2455
2456 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2457 radeon_emit(cs, scratch_va);
2458 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2459 S_008F04_SWIZZLE_ENABLE(1));
2460 }
2461
2462 static void
2463 radv_emit_global_shader_pointers(struct radv_queue *queue,
2464 struct radeon_cmdbuf *cs,
2465 struct radeon_winsys_bo *descriptor_bo)
2466 {
2467 uint64_t va;
2468
2469 if (!descriptor_bo)
2470 return;
2471
2472 va = radv_buffer_get_va(descriptor_bo);
2473
2474 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2475
2476 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2477 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2478 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2479 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2480 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2481
2482 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2483 radv_emit_shader_pointer(queue->device, cs, regs[i],
2484 va, true);
2485 }
2486 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2487 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2488 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2489 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2490 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2491
2492 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2493 radv_emit_shader_pointer(queue->device, cs, regs[i],
2494 va, true);
2495 }
2496 } else {
2497 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2498 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2499 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2500 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2501 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2502 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2503
2504 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2505 radv_emit_shader_pointer(queue->device, cs, regs[i],
2506 va, true);
2507 }
2508 }
2509 }
2510
2511 static void
2512 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2513 {
2514 struct radv_device *device = queue->device;
2515
2516 if (device->gfx_init) {
2517 uint64_t va = radv_buffer_get_va(device->gfx_init);
2518
2519 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2520 radeon_emit(cs, va);
2521 radeon_emit(cs, va >> 32);
2522 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2523
2524 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2525 } else {
2526 struct radv_physical_device *physical_device = device->physical_device;
2527 si_emit_graphics(physical_device, cs);
2528 }
2529 }
2530
2531 static void
2532 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2533 {
2534 struct radv_physical_device *physical_device = queue->device->physical_device;
2535 si_emit_compute(physical_device, cs);
2536 }
2537
2538 static VkResult
2539 radv_get_preamble_cs(struct radv_queue *queue,
2540 uint32_t scratch_size,
2541 uint32_t compute_scratch_size,
2542 uint32_t esgs_ring_size,
2543 uint32_t gsvs_ring_size,
2544 bool needs_tess_rings,
2545 bool needs_sample_positions,
2546 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2547 struct radeon_cmdbuf **initial_preamble_cs,
2548 struct radeon_cmdbuf **continue_preamble_cs)
2549 {
2550 struct radeon_winsys_bo *scratch_bo = NULL;
2551 struct radeon_winsys_bo *descriptor_bo = NULL;
2552 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2553 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2554 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2555 struct radeon_winsys_bo *tess_rings_bo = NULL;
2556 struct radeon_cmdbuf *dest_cs[3] = {0};
2557 bool add_tess_rings = false, add_sample_positions = false;
2558 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2559 unsigned max_offchip_buffers;
2560 unsigned hs_offchip_param = 0;
2561 unsigned tess_offchip_ring_offset;
2562 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2563 if (!queue->has_tess_rings) {
2564 if (needs_tess_rings)
2565 add_tess_rings = true;
2566 }
2567 if (!queue->has_sample_positions) {
2568 if (needs_sample_positions)
2569 add_sample_positions = true;
2570 }
2571 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2572 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2573 &max_offchip_buffers);
2574 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2575 tess_offchip_ring_size = max_offchip_buffers *
2576 queue->device->tess_offchip_block_dw_size * 4;
2577
2578 if (scratch_size <= queue->scratch_size &&
2579 compute_scratch_size <= queue->compute_scratch_size &&
2580 esgs_ring_size <= queue->esgs_ring_size &&
2581 gsvs_ring_size <= queue->gsvs_ring_size &&
2582 !add_tess_rings && !add_sample_positions &&
2583 queue->initial_preamble_cs) {
2584 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2585 *initial_preamble_cs = queue->initial_preamble_cs;
2586 *continue_preamble_cs = queue->continue_preamble_cs;
2587 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2588 *continue_preamble_cs = NULL;
2589 return VK_SUCCESS;
2590 }
2591
2592 if (scratch_size > queue->scratch_size) {
2593 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2594 scratch_size,
2595 4096,
2596 RADEON_DOMAIN_VRAM,
2597 ring_bo_flags,
2598 RADV_BO_PRIORITY_SCRATCH);
2599 if (!scratch_bo)
2600 goto fail;
2601 } else
2602 scratch_bo = queue->scratch_bo;
2603
2604 if (compute_scratch_size > queue->compute_scratch_size) {
2605 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2606 compute_scratch_size,
2607 4096,
2608 RADEON_DOMAIN_VRAM,
2609 ring_bo_flags,
2610 RADV_BO_PRIORITY_SCRATCH);
2611 if (!compute_scratch_bo)
2612 goto fail;
2613
2614 } else
2615 compute_scratch_bo = queue->compute_scratch_bo;
2616
2617 if (esgs_ring_size > queue->esgs_ring_size) {
2618 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2619 esgs_ring_size,
2620 4096,
2621 RADEON_DOMAIN_VRAM,
2622 ring_bo_flags,
2623 RADV_BO_PRIORITY_SCRATCH);
2624 if (!esgs_ring_bo)
2625 goto fail;
2626 } else {
2627 esgs_ring_bo = queue->esgs_ring_bo;
2628 esgs_ring_size = queue->esgs_ring_size;
2629 }
2630
2631 if (gsvs_ring_size > queue->gsvs_ring_size) {
2632 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2633 gsvs_ring_size,
2634 4096,
2635 RADEON_DOMAIN_VRAM,
2636 ring_bo_flags,
2637 RADV_BO_PRIORITY_SCRATCH);
2638 if (!gsvs_ring_bo)
2639 goto fail;
2640 } else {
2641 gsvs_ring_bo = queue->gsvs_ring_bo;
2642 gsvs_ring_size = queue->gsvs_ring_size;
2643 }
2644
2645 if (add_tess_rings) {
2646 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2647 tess_offchip_ring_offset + tess_offchip_ring_size,
2648 256,
2649 RADEON_DOMAIN_VRAM,
2650 ring_bo_flags,
2651 RADV_BO_PRIORITY_SCRATCH);
2652 if (!tess_rings_bo)
2653 goto fail;
2654 } else {
2655 tess_rings_bo = queue->tess_rings_bo;
2656 }
2657
2658 if (scratch_bo != queue->scratch_bo ||
2659 esgs_ring_bo != queue->esgs_ring_bo ||
2660 gsvs_ring_bo != queue->gsvs_ring_bo ||
2661 tess_rings_bo != queue->tess_rings_bo ||
2662 add_sample_positions) {
2663 uint32_t size = 0;
2664 if (gsvs_ring_bo || esgs_ring_bo ||
2665 tess_rings_bo || add_sample_positions) {
2666 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2667 if (add_sample_positions)
2668 size += 128; /* 64+32+16+8 = 120 bytes */
2669 }
2670 else if (scratch_bo)
2671 size = 8; /* 2 dword */
2672
2673 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2674 size,
2675 4096,
2676 RADEON_DOMAIN_VRAM,
2677 RADEON_FLAG_CPU_ACCESS |
2678 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2679 RADEON_FLAG_READ_ONLY,
2680 RADV_BO_PRIORITY_DESCRIPTOR);
2681 if (!descriptor_bo)
2682 goto fail;
2683 } else
2684 descriptor_bo = queue->descriptor_bo;
2685
2686 if (descriptor_bo != queue->descriptor_bo) {
2687 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2688
2689 if (scratch_bo) {
2690 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2691 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2692 S_008F04_SWIZZLE_ENABLE(1);
2693 map[0] = scratch_va;
2694 map[1] = rsrc1;
2695 }
2696
2697 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2698 fill_geom_tess_rings(queue, map, add_sample_positions,
2699 esgs_ring_size, esgs_ring_bo,
2700 gsvs_ring_size, gsvs_ring_bo,
2701 tess_factor_ring_size,
2702 tess_offchip_ring_offset,
2703 tess_offchip_ring_size,
2704 tess_rings_bo);
2705
2706 queue->device->ws->buffer_unmap(descriptor_bo);
2707 }
2708
2709 for(int i = 0; i < 3; ++i) {
2710 struct radeon_cmdbuf *cs = NULL;
2711 cs = queue->device->ws->cs_create(queue->device->ws,
2712 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2713 if (!cs)
2714 goto fail;
2715
2716 dest_cs[i] = cs;
2717
2718 if (scratch_bo)
2719 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2720
2721 /* Emit initial configuration. */
2722 switch (queue->queue_family_index) {
2723 case RADV_QUEUE_GENERAL:
2724 radv_init_graphics_state(cs, queue);
2725 break;
2726 case RADV_QUEUE_COMPUTE:
2727 radv_init_compute_state(cs, queue);
2728 break;
2729 case RADV_QUEUE_TRANSFER:
2730 break;
2731 }
2732
2733 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2734 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2735 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2736
2737 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2738 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2739 }
2740
2741 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2742 gsvs_ring_bo, gsvs_ring_size);
2743 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2744 tess_factor_ring_size, tess_rings_bo);
2745 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2746 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2747
2748 if (i == 0) {
2749 si_cs_emit_cache_flush(cs,
2750 queue->device->physical_device->rad_info.chip_class,
2751 NULL, 0,
2752 queue->queue_family_index == RING_COMPUTE &&
2753 queue->device->physical_device->rad_info.chip_class >= GFX7,
2754 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2755 RADV_CMD_FLAG_INV_ICACHE |
2756 RADV_CMD_FLAG_INV_SCACHE |
2757 RADV_CMD_FLAG_INV_VCACHE |
2758 RADV_CMD_FLAG_INV_L2 |
2759 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2760 } else if (i == 1) {
2761 si_cs_emit_cache_flush(cs,
2762 queue->device->physical_device->rad_info.chip_class,
2763 NULL, 0,
2764 queue->queue_family_index == RING_COMPUTE &&
2765 queue->device->physical_device->rad_info.chip_class >= GFX7,
2766 RADV_CMD_FLAG_INV_ICACHE |
2767 RADV_CMD_FLAG_INV_SCACHE |
2768 RADV_CMD_FLAG_INV_VCACHE |
2769 RADV_CMD_FLAG_INV_L2 |
2770 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2771 }
2772
2773 if (!queue->device->ws->cs_finalize(cs))
2774 goto fail;
2775 }
2776
2777 if (queue->initial_full_flush_preamble_cs)
2778 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2779
2780 if (queue->initial_preamble_cs)
2781 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2782
2783 if (queue->continue_preamble_cs)
2784 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2785
2786 queue->initial_full_flush_preamble_cs = dest_cs[0];
2787 queue->initial_preamble_cs = dest_cs[1];
2788 queue->continue_preamble_cs = dest_cs[2];
2789
2790 if (scratch_bo != queue->scratch_bo) {
2791 if (queue->scratch_bo)
2792 queue->device->ws->buffer_destroy(queue->scratch_bo);
2793 queue->scratch_bo = scratch_bo;
2794 queue->scratch_size = scratch_size;
2795 }
2796
2797 if (compute_scratch_bo != queue->compute_scratch_bo) {
2798 if (queue->compute_scratch_bo)
2799 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2800 queue->compute_scratch_bo = compute_scratch_bo;
2801 queue->compute_scratch_size = compute_scratch_size;
2802 }
2803
2804 if (esgs_ring_bo != queue->esgs_ring_bo) {
2805 if (queue->esgs_ring_bo)
2806 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2807 queue->esgs_ring_bo = esgs_ring_bo;
2808 queue->esgs_ring_size = esgs_ring_size;
2809 }
2810
2811 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2812 if (queue->gsvs_ring_bo)
2813 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2814 queue->gsvs_ring_bo = gsvs_ring_bo;
2815 queue->gsvs_ring_size = gsvs_ring_size;
2816 }
2817
2818 if (tess_rings_bo != queue->tess_rings_bo) {
2819 queue->tess_rings_bo = tess_rings_bo;
2820 queue->has_tess_rings = true;
2821 }
2822
2823 if (descriptor_bo != queue->descriptor_bo) {
2824 if (queue->descriptor_bo)
2825 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2826
2827 queue->descriptor_bo = descriptor_bo;
2828 }
2829
2830 if (add_sample_positions)
2831 queue->has_sample_positions = true;
2832
2833 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2834 *initial_preamble_cs = queue->initial_preamble_cs;
2835 *continue_preamble_cs = queue->continue_preamble_cs;
2836 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2837 *continue_preamble_cs = NULL;
2838 return VK_SUCCESS;
2839 fail:
2840 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2841 if (dest_cs[i])
2842 queue->device->ws->cs_destroy(dest_cs[i]);
2843 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2844 queue->device->ws->buffer_destroy(descriptor_bo);
2845 if (scratch_bo && scratch_bo != queue->scratch_bo)
2846 queue->device->ws->buffer_destroy(scratch_bo);
2847 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2848 queue->device->ws->buffer_destroy(compute_scratch_bo);
2849 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2850 queue->device->ws->buffer_destroy(esgs_ring_bo);
2851 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2852 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2853 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2854 queue->device->ws->buffer_destroy(tess_rings_bo);
2855 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2856 }
2857
2858 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2859 struct radv_winsys_sem_counts *counts,
2860 int num_sems,
2861 const VkSemaphore *sems,
2862 VkFence _fence,
2863 bool reset_temp)
2864 {
2865 int syncobj_idx = 0, sem_idx = 0;
2866
2867 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2868 return VK_SUCCESS;
2869
2870 for (uint32_t i = 0; i < num_sems; i++) {
2871 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2872
2873 if (sem->temp_syncobj || sem->syncobj)
2874 counts->syncobj_count++;
2875 else
2876 counts->sem_count++;
2877 }
2878
2879 if (_fence != VK_NULL_HANDLE) {
2880 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2881 if (fence->temp_syncobj || fence->syncobj)
2882 counts->syncobj_count++;
2883 }
2884
2885 if (counts->syncobj_count) {
2886 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2887 if (!counts->syncobj)
2888 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2889 }
2890
2891 if (counts->sem_count) {
2892 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2893 if (!counts->sem) {
2894 free(counts->syncobj);
2895 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2896 }
2897 }
2898
2899 for (uint32_t i = 0; i < num_sems; i++) {
2900 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2901
2902 if (sem->temp_syncobj) {
2903 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2904 }
2905 else if (sem->syncobj)
2906 counts->syncobj[syncobj_idx++] = sem->syncobj;
2907 else {
2908 assert(sem->sem);
2909 counts->sem[sem_idx++] = sem->sem;
2910 }
2911 }
2912
2913 if (_fence != VK_NULL_HANDLE) {
2914 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2915 if (fence->temp_syncobj)
2916 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2917 else if (fence->syncobj)
2918 counts->syncobj[syncobj_idx++] = fence->syncobj;
2919 }
2920
2921 return VK_SUCCESS;
2922 }
2923
2924 static void
2925 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2926 {
2927 free(sem_info->wait.syncobj);
2928 free(sem_info->wait.sem);
2929 free(sem_info->signal.syncobj);
2930 free(sem_info->signal.sem);
2931 }
2932
2933
2934 static void radv_free_temp_syncobjs(struct radv_device *device,
2935 int num_sems,
2936 const VkSemaphore *sems)
2937 {
2938 for (uint32_t i = 0; i < num_sems; i++) {
2939 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2940
2941 if (sem->temp_syncobj) {
2942 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2943 sem->temp_syncobj = 0;
2944 }
2945 }
2946 }
2947
2948 static VkResult
2949 radv_alloc_sem_info(struct radv_instance *instance,
2950 struct radv_winsys_sem_info *sem_info,
2951 int num_wait_sems,
2952 const VkSemaphore *wait_sems,
2953 int num_signal_sems,
2954 const VkSemaphore *signal_sems,
2955 VkFence fence)
2956 {
2957 VkResult ret;
2958 memset(sem_info, 0, sizeof(*sem_info));
2959
2960 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2961 if (ret)
2962 return ret;
2963 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2964 if (ret)
2965 radv_free_sem_info(sem_info);
2966
2967 /* caller can override these */
2968 sem_info->cs_emit_wait = true;
2969 sem_info->cs_emit_signal = true;
2970 return ret;
2971 }
2972
2973 /* Signals fence as soon as all the work currently put on queue is done. */
2974 static VkResult radv_signal_fence(struct radv_queue *queue,
2975 struct radv_fence *fence)
2976 {
2977 int ret;
2978 VkResult result;
2979 struct radv_winsys_sem_info sem_info;
2980
2981 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2982 radv_fence_to_handle(fence));
2983 if (result != VK_SUCCESS)
2984 return result;
2985
2986 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2987 &queue->device->empty_cs[queue->queue_family_index],
2988 1, NULL, NULL, &sem_info, NULL,
2989 false, fence->fence);
2990 radv_free_sem_info(&sem_info);
2991
2992 if (ret)
2993 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2994
2995 return VK_SUCCESS;
2996 }
2997
2998 VkResult radv_QueueSubmit(
2999 VkQueue _queue,
3000 uint32_t submitCount,
3001 const VkSubmitInfo* pSubmits,
3002 VkFence _fence)
3003 {
3004 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3005 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3006 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3007 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
3008 int ret;
3009 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
3010 uint32_t scratch_size = 0;
3011 uint32_t compute_scratch_size = 0;
3012 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
3013 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
3014 VkResult result;
3015 bool fence_emitted = false;
3016 bool tess_rings_needed = false;
3017 bool sample_positions_needed = false;
3018
3019 /* Do this first so failing to allocate scratch buffers can't result in
3020 * partially executed submissions. */
3021 for (uint32_t i = 0; i < submitCount; i++) {
3022 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3023 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3024 pSubmits[i].pCommandBuffers[j]);
3025
3026 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
3027 compute_scratch_size = MAX2(compute_scratch_size,
3028 cmd_buffer->compute_scratch_size_needed);
3029 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
3030 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
3031 tess_rings_needed |= cmd_buffer->tess_rings_needed;
3032 sample_positions_needed |= cmd_buffer->sample_positions_needed;
3033 }
3034 }
3035
3036 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
3037 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
3038 sample_positions_needed, &initial_flush_preamble_cs,
3039 &initial_preamble_cs, &continue_preamble_cs);
3040 if (result != VK_SUCCESS)
3041 return result;
3042
3043 for (uint32_t i = 0; i < submitCount; i++) {
3044 struct radeon_cmdbuf **cs_array;
3045 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
3046 bool can_patch = true;
3047 uint32_t advance;
3048 struct radv_winsys_sem_info sem_info;
3049
3050 result = radv_alloc_sem_info(queue->device->instance,
3051 &sem_info,
3052 pSubmits[i].waitSemaphoreCount,
3053 pSubmits[i].pWaitSemaphores,
3054 pSubmits[i].signalSemaphoreCount,
3055 pSubmits[i].pSignalSemaphores,
3056 _fence);
3057 if (result != VK_SUCCESS)
3058 return result;
3059
3060 if (!pSubmits[i].commandBufferCount) {
3061 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3062 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3063 &queue->device->empty_cs[queue->queue_family_index],
3064 1, NULL, NULL,
3065 &sem_info, NULL,
3066 false, base_fence);
3067 if (ret) {
3068 radv_loge("failed to submit CS %d\n", i);
3069 abort();
3070 }
3071 fence_emitted = true;
3072 }
3073 radv_free_sem_info(&sem_info);
3074 continue;
3075 }
3076
3077 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3078 (pSubmits[i].commandBufferCount));
3079
3080 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3081 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3082 pSubmits[i].pCommandBuffers[j]);
3083 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3084
3085 cs_array[j] = cmd_buffer->cs;
3086 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3087 can_patch = false;
3088
3089 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3090 }
3091
3092 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3093 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3094 const struct radv_winsys_bo_list *bo_list = NULL;
3095
3096 advance = MIN2(max_cs_submission,
3097 pSubmits[i].commandBufferCount - j);
3098
3099 if (queue->device->trace_bo)
3100 *queue->device->trace_id_ptr = 0;
3101
3102 sem_info.cs_emit_wait = j == 0;
3103 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3104
3105 if (unlikely(queue->device->use_global_bo_list)) {
3106 pthread_mutex_lock(&queue->device->bo_list.mutex);
3107 bo_list = &queue->device->bo_list.list;
3108 }
3109
3110 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3111 advance, initial_preamble, continue_preamble_cs,
3112 &sem_info, bo_list,
3113 can_patch, base_fence);
3114
3115 if (unlikely(queue->device->use_global_bo_list))
3116 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3117
3118 if (ret) {
3119 radv_loge("failed to submit CS %d\n", i);
3120 abort();
3121 }
3122 fence_emitted = true;
3123 if (queue->device->trace_bo) {
3124 radv_check_gpu_hangs(queue, cs_array[j]);
3125 }
3126 }
3127
3128 radv_free_temp_syncobjs(queue->device,
3129 pSubmits[i].waitSemaphoreCount,
3130 pSubmits[i].pWaitSemaphores);
3131 radv_free_sem_info(&sem_info);
3132 free(cs_array);
3133 }
3134
3135 if (fence) {
3136 if (!fence_emitted) {
3137 result = radv_signal_fence(queue, fence);
3138 if (result != VK_SUCCESS)
3139 return result;
3140 }
3141 }
3142
3143 return VK_SUCCESS;
3144 }
3145
3146 VkResult radv_QueueWaitIdle(
3147 VkQueue _queue)
3148 {
3149 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3150
3151 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3152 radv_queue_family_to_ring(queue->queue_family_index),
3153 queue->queue_idx);
3154 return VK_SUCCESS;
3155 }
3156
3157 VkResult radv_DeviceWaitIdle(
3158 VkDevice _device)
3159 {
3160 RADV_FROM_HANDLE(radv_device, device, _device);
3161
3162 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3163 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3164 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3165 }
3166 }
3167 return VK_SUCCESS;
3168 }
3169
3170 VkResult radv_EnumerateInstanceExtensionProperties(
3171 const char* pLayerName,
3172 uint32_t* pPropertyCount,
3173 VkExtensionProperties* pProperties)
3174 {
3175 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3176
3177 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3178 if (radv_supported_instance_extensions.extensions[i]) {
3179 vk_outarray_append(&out, prop) {
3180 *prop = radv_instance_extensions[i];
3181 }
3182 }
3183 }
3184
3185 return vk_outarray_status(&out);
3186 }
3187
3188 VkResult radv_EnumerateDeviceExtensionProperties(
3189 VkPhysicalDevice physicalDevice,
3190 const char* pLayerName,
3191 uint32_t* pPropertyCount,
3192 VkExtensionProperties* pProperties)
3193 {
3194 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3195 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3196
3197 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3198 if (device->supported_extensions.extensions[i]) {
3199 vk_outarray_append(&out, prop) {
3200 *prop = radv_device_extensions[i];
3201 }
3202 }
3203 }
3204
3205 return vk_outarray_status(&out);
3206 }
3207
3208 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3209 VkInstance _instance,
3210 const char* pName)
3211 {
3212 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3213
3214 return radv_lookup_entrypoint_checked(pName,
3215 instance ? instance->apiVersion : 0,
3216 instance ? &instance->enabled_extensions : NULL,
3217 NULL);
3218 }
3219
3220 /* The loader wants us to expose a second GetInstanceProcAddr function
3221 * to work around certain LD_PRELOAD issues seen in apps.
3222 */
3223 PUBLIC
3224 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3225 VkInstance instance,
3226 const char* pName);
3227
3228 PUBLIC
3229 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3230 VkInstance instance,
3231 const char* pName)
3232 {
3233 return radv_GetInstanceProcAddr(instance, pName);
3234 }
3235
3236 PUBLIC
3237 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3238 VkInstance _instance,
3239 const char* pName);
3240
3241 PUBLIC
3242 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3243 VkInstance _instance,
3244 const char* pName)
3245 {
3246 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3247
3248 return radv_lookup_physical_device_entrypoint_checked(pName,
3249 instance ? instance->apiVersion : 0,
3250 instance ? &instance->enabled_extensions : NULL);
3251 }
3252
3253 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3254 VkDevice _device,
3255 const char* pName)
3256 {
3257 RADV_FROM_HANDLE(radv_device, device, _device);
3258
3259 return radv_lookup_entrypoint_checked(pName,
3260 device->instance->apiVersion,
3261 &device->instance->enabled_extensions,
3262 &device->enabled_extensions);
3263 }
3264
3265 bool radv_get_memory_fd(struct radv_device *device,
3266 struct radv_device_memory *memory,
3267 int *pFD)
3268 {
3269 struct radeon_bo_metadata metadata;
3270
3271 if (memory->image) {
3272 radv_init_metadata(device, memory->image, &metadata);
3273 device->ws->buffer_set_metadata(memory->bo, &metadata);
3274 }
3275
3276 return device->ws->buffer_get_fd(device->ws, memory->bo,
3277 pFD);
3278 }
3279
3280 static VkResult radv_alloc_memory(struct radv_device *device,
3281 const VkMemoryAllocateInfo* pAllocateInfo,
3282 const VkAllocationCallbacks* pAllocator,
3283 VkDeviceMemory* pMem)
3284 {
3285 struct radv_device_memory *mem;
3286 VkResult result;
3287 enum radeon_bo_domain domain;
3288 uint32_t flags = 0;
3289 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3290
3291 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3292
3293 if (pAllocateInfo->allocationSize == 0) {
3294 /* Apparently, this is allowed */
3295 *pMem = VK_NULL_HANDLE;
3296 return VK_SUCCESS;
3297 }
3298
3299 const VkImportMemoryFdInfoKHR *import_info =
3300 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3301 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3302 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3303 const VkExportMemoryAllocateInfo *export_info =
3304 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3305 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3306 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3307
3308 const struct wsi_memory_allocate_info *wsi_info =
3309 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3310
3311 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3312 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3313 if (mem == NULL)
3314 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3315
3316 if (wsi_info && wsi_info->implicit_sync)
3317 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3318
3319 if (dedicate_info) {
3320 mem->image = radv_image_from_handle(dedicate_info->image);
3321 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3322 } else {
3323 mem->image = NULL;
3324 mem->buffer = NULL;
3325 }
3326
3327 float priority_float = 0.5;
3328 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3329 vk_find_struct_const(pAllocateInfo->pNext,
3330 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3331 if (priority_ext)
3332 priority_float = priority_ext->priority;
3333
3334 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3335 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3336
3337 mem->user_ptr = NULL;
3338
3339 if (import_info) {
3340 assert(import_info->handleType ==
3341 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3342 import_info->handleType ==
3343 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3344 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3345 priority, NULL, NULL);
3346 if (!mem->bo) {
3347 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3348 goto fail;
3349 } else {
3350 close(import_info->fd);
3351 }
3352 } else if (host_ptr_info) {
3353 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3354 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3355 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3356 pAllocateInfo->allocationSize,
3357 priority);
3358 if (!mem->bo) {
3359 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3360 goto fail;
3361 } else {
3362 mem->user_ptr = host_ptr_info->pHostPointer;
3363 }
3364 } else {
3365 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3366 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3367 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3368 domain = RADEON_DOMAIN_GTT;
3369 else
3370 domain = RADEON_DOMAIN_VRAM;
3371
3372 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3373 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3374 else
3375 flags |= RADEON_FLAG_CPU_ACCESS;
3376
3377 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3378 flags |= RADEON_FLAG_GTT_WC;
3379
3380 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3381 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3382 if (device->use_global_bo_list) {
3383 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3384 }
3385 }
3386
3387 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3388 domain, flags, priority);
3389
3390 if (!mem->bo) {
3391 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3392 goto fail;
3393 }
3394 mem->type_index = mem_type_index;
3395 }
3396
3397 result = radv_bo_list_add(device, mem->bo);
3398 if (result != VK_SUCCESS)
3399 goto fail_bo;
3400
3401 *pMem = radv_device_memory_to_handle(mem);
3402
3403 return VK_SUCCESS;
3404
3405 fail_bo:
3406 device->ws->buffer_destroy(mem->bo);
3407 fail:
3408 vk_free2(&device->alloc, pAllocator, mem);
3409
3410 return result;
3411 }
3412
3413 VkResult radv_AllocateMemory(
3414 VkDevice _device,
3415 const VkMemoryAllocateInfo* pAllocateInfo,
3416 const VkAllocationCallbacks* pAllocator,
3417 VkDeviceMemory* pMem)
3418 {
3419 RADV_FROM_HANDLE(radv_device, device, _device);
3420 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3421 }
3422
3423 void radv_FreeMemory(
3424 VkDevice _device,
3425 VkDeviceMemory _mem,
3426 const VkAllocationCallbacks* pAllocator)
3427 {
3428 RADV_FROM_HANDLE(radv_device, device, _device);
3429 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3430
3431 if (mem == NULL)
3432 return;
3433
3434 radv_bo_list_remove(device, mem->bo);
3435 device->ws->buffer_destroy(mem->bo);
3436 mem->bo = NULL;
3437
3438 vk_free2(&device->alloc, pAllocator, mem);
3439 }
3440
3441 VkResult radv_MapMemory(
3442 VkDevice _device,
3443 VkDeviceMemory _memory,
3444 VkDeviceSize offset,
3445 VkDeviceSize size,
3446 VkMemoryMapFlags flags,
3447 void** ppData)
3448 {
3449 RADV_FROM_HANDLE(radv_device, device, _device);
3450 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3451
3452 if (mem == NULL) {
3453 *ppData = NULL;
3454 return VK_SUCCESS;
3455 }
3456
3457 if (mem->user_ptr)
3458 *ppData = mem->user_ptr;
3459 else
3460 *ppData = device->ws->buffer_map(mem->bo);
3461
3462 if (*ppData) {
3463 *ppData += offset;
3464 return VK_SUCCESS;
3465 }
3466
3467 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3468 }
3469
3470 void radv_UnmapMemory(
3471 VkDevice _device,
3472 VkDeviceMemory _memory)
3473 {
3474 RADV_FROM_HANDLE(radv_device, device, _device);
3475 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3476
3477 if (mem == NULL)
3478 return;
3479
3480 if (mem->user_ptr == NULL)
3481 device->ws->buffer_unmap(mem->bo);
3482 }
3483
3484 VkResult radv_FlushMappedMemoryRanges(
3485 VkDevice _device,
3486 uint32_t memoryRangeCount,
3487 const VkMappedMemoryRange* pMemoryRanges)
3488 {
3489 return VK_SUCCESS;
3490 }
3491
3492 VkResult radv_InvalidateMappedMemoryRanges(
3493 VkDevice _device,
3494 uint32_t memoryRangeCount,
3495 const VkMappedMemoryRange* pMemoryRanges)
3496 {
3497 return VK_SUCCESS;
3498 }
3499
3500 void radv_GetBufferMemoryRequirements(
3501 VkDevice _device,
3502 VkBuffer _buffer,
3503 VkMemoryRequirements* pMemoryRequirements)
3504 {
3505 RADV_FROM_HANDLE(radv_device, device, _device);
3506 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3507
3508 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3509
3510 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3511 pMemoryRequirements->alignment = 4096;
3512 else
3513 pMemoryRequirements->alignment = 16;
3514
3515 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3516 }
3517
3518 void radv_GetBufferMemoryRequirements2(
3519 VkDevice device,
3520 const VkBufferMemoryRequirementsInfo2 *pInfo,
3521 VkMemoryRequirements2 *pMemoryRequirements)
3522 {
3523 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3524 &pMemoryRequirements->memoryRequirements);
3525 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3526 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3527 switch (ext->sType) {
3528 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3529 VkMemoryDedicatedRequirements *req =
3530 (VkMemoryDedicatedRequirements *) ext;
3531 req->requiresDedicatedAllocation = buffer->shareable;
3532 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3533 break;
3534 }
3535 default:
3536 break;
3537 }
3538 }
3539 }
3540
3541 void radv_GetImageMemoryRequirements(
3542 VkDevice _device,
3543 VkImage _image,
3544 VkMemoryRequirements* pMemoryRequirements)
3545 {
3546 RADV_FROM_HANDLE(radv_device, device, _device);
3547 RADV_FROM_HANDLE(radv_image, image, _image);
3548
3549 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3550
3551 pMemoryRequirements->size = image->size;
3552 pMemoryRequirements->alignment = image->alignment;
3553 }
3554
3555 void radv_GetImageMemoryRequirements2(
3556 VkDevice device,
3557 const VkImageMemoryRequirementsInfo2 *pInfo,
3558 VkMemoryRequirements2 *pMemoryRequirements)
3559 {
3560 radv_GetImageMemoryRequirements(device, pInfo->image,
3561 &pMemoryRequirements->memoryRequirements);
3562
3563 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3564
3565 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3566 switch (ext->sType) {
3567 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3568 VkMemoryDedicatedRequirements *req =
3569 (VkMemoryDedicatedRequirements *) ext;
3570 req->requiresDedicatedAllocation = image->shareable;
3571 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3572 break;
3573 }
3574 default:
3575 break;
3576 }
3577 }
3578 }
3579
3580 void radv_GetImageSparseMemoryRequirements(
3581 VkDevice device,
3582 VkImage image,
3583 uint32_t* pSparseMemoryRequirementCount,
3584 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3585 {
3586 stub();
3587 }
3588
3589 void radv_GetImageSparseMemoryRequirements2(
3590 VkDevice device,
3591 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3592 uint32_t* pSparseMemoryRequirementCount,
3593 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3594 {
3595 stub();
3596 }
3597
3598 void radv_GetDeviceMemoryCommitment(
3599 VkDevice device,
3600 VkDeviceMemory memory,
3601 VkDeviceSize* pCommittedMemoryInBytes)
3602 {
3603 *pCommittedMemoryInBytes = 0;
3604 }
3605
3606 VkResult radv_BindBufferMemory2(VkDevice device,
3607 uint32_t bindInfoCount,
3608 const VkBindBufferMemoryInfo *pBindInfos)
3609 {
3610 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3611 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3612 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3613
3614 if (mem) {
3615 buffer->bo = mem->bo;
3616 buffer->offset = pBindInfos[i].memoryOffset;
3617 } else {
3618 buffer->bo = NULL;
3619 }
3620 }
3621 return VK_SUCCESS;
3622 }
3623
3624 VkResult radv_BindBufferMemory(
3625 VkDevice device,
3626 VkBuffer buffer,
3627 VkDeviceMemory memory,
3628 VkDeviceSize memoryOffset)
3629 {
3630 const VkBindBufferMemoryInfo info = {
3631 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3632 .buffer = buffer,
3633 .memory = memory,
3634 .memoryOffset = memoryOffset
3635 };
3636
3637 return radv_BindBufferMemory2(device, 1, &info);
3638 }
3639
3640 VkResult radv_BindImageMemory2(VkDevice device,
3641 uint32_t bindInfoCount,
3642 const VkBindImageMemoryInfo *pBindInfos)
3643 {
3644 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3645 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3646 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3647
3648 if (mem) {
3649 image->bo = mem->bo;
3650 image->offset = pBindInfos[i].memoryOffset;
3651 } else {
3652 image->bo = NULL;
3653 image->offset = 0;
3654 }
3655 }
3656 return VK_SUCCESS;
3657 }
3658
3659
3660 VkResult radv_BindImageMemory(
3661 VkDevice device,
3662 VkImage image,
3663 VkDeviceMemory memory,
3664 VkDeviceSize memoryOffset)
3665 {
3666 const VkBindImageMemoryInfo info = {
3667 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3668 .image = image,
3669 .memory = memory,
3670 .memoryOffset = memoryOffset
3671 };
3672
3673 return radv_BindImageMemory2(device, 1, &info);
3674 }
3675
3676
3677 static void
3678 radv_sparse_buffer_bind_memory(struct radv_device *device,
3679 const VkSparseBufferMemoryBindInfo *bind)
3680 {
3681 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3682
3683 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3684 struct radv_device_memory *mem = NULL;
3685
3686 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3687 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3688
3689 device->ws->buffer_virtual_bind(buffer->bo,
3690 bind->pBinds[i].resourceOffset,
3691 bind->pBinds[i].size,
3692 mem ? mem->bo : NULL,
3693 bind->pBinds[i].memoryOffset);
3694 }
3695 }
3696
3697 static void
3698 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3699 const VkSparseImageOpaqueMemoryBindInfo *bind)
3700 {
3701 RADV_FROM_HANDLE(radv_image, image, bind->image);
3702
3703 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3704 struct radv_device_memory *mem = NULL;
3705
3706 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3707 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3708
3709 device->ws->buffer_virtual_bind(image->bo,
3710 bind->pBinds[i].resourceOffset,
3711 bind->pBinds[i].size,
3712 mem ? mem->bo : NULL,
3713 bind->pBinds[i].memoryOffset);
3714 }
3715 }
3716
3717 VkResult radv_QueueBindSparse(
3718 VkQueue _queue,
3719 uint32_t bindInfoCount,
3720 const VkBindSparseInfo* pBindInfo,
3721 VkFence _fence)
3722 {
3723 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3724 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3725 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3726 bool fence_emitted = false;
3727 VkResult result;
3728 int ret;
3729
3730 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3731 struct radv_winsys_sem_info sem_info;
3732 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3733 radv_sparse_buffer_bind_memory(queue->device,
3734 pBindInfo[i].pBufferBinds + j);
3735 }
3736
3737 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3738 radv_sparse_image_opaque_bind_memory(queue->device,
3739 pBindInfo[i].pImageOpaqueBinds + j);
3740 }
3741
3742 VkResult result;
3743 result = radv_alloc_sem_info(queue->device->instance,
3744 &sem_info,
3745 pBindInfo[i].waitSemaphoreCount,
3746 pBindInfo[i].pWaitSemaphores,
3747 pBindInfo[i].signalSemaphoreCount,
3748 pBindInfo[i].pSignalSemaphores,
3749 _fence);
3750 if (result != VK_SUCCESS)
3751 return result;
3752
3753 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3754 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3755 &queue->device->empty_cs[queue->queue_family_index],
3756 1, NULL, NULL,
3757 &sem_info, NULL,
3758 false, base_fence);
3759 if (ret) {
3760 radv_loge("failed to submit CS %d\n", i);
3761 abort();
3762 }
3763
3764 fence_emitted = true;
3765 }
3766
3767 radv_free_sem_info(&sem_info);
3768
3769 }
3770
3771 if (fence) {
3772 if (!fence_emitted) {
3773 result = radv_signal_fence(queue, fence);
3774 if (result != VK_SUCCESS)
3775 return result;
3776 }
3777 }
3778
3779 return VK_SUCCESS;
3780 }
3781
3782 VkResult radv_CreateFence(
3783 VkDevice _device,
3784 const VkFenceCreateInfo* pCreateInfo,
3785 const VkAllocationCallbacks* pAllocator,
3786 VkFence* pFence)
3787 {
3788 RADV_FROM_HANDLE(radv_device, device, _device);
3789 const VkExportFenceCreateInfo *export =
3790 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3791 VkExternalFenceHandleTypeFlags handleTypes =
3792 export ? export->handleTypes : 0;
3793
3794 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3795 sizeof(*fence), 8,
3796 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3797
3798 if (!fence)
3799 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3800
3801 fence->fence_wsi = NULL;
3802 fence->temp_syncobj = 0;
3803 if (device->always_use_syncobj || handleTypes) {
3804 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3805 if (ret) {
3806 vk_free2(&device->alloc, pAllocator, fence);
3807 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3808 }
3809 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3810 device->ws->signal_syncobj(device->ws, fence->syncobj);
3811 }
3812 fence->fence = NULL;
3813 } else {
3814 fence->fence = device->ws->create_fence();
3815 if (!fence->fence) {
3816 vk_free2(&device->alloc, pAllocator, fence);
3817 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3818 }
3819 fence->syncobj = 0;
3820 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3821 device->ws->signal_fence(fence->fence);
3822 }
3823
3824 *pFence = radv_fence_to_handle(fence);
3825
3826 return VK_SUCCESS;
3827 }
3828
3829 void radv_DestroyFence(
3830 VkDevice _device,
3831 VkFence _fence,
3832 const VkAllocationCallbacks* pAllocator)
3833 {
3834 RADV_FROM_HANDLE(radv_device, device, _device);
3835 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3836
3837 if (!fence)
3838 return;
3839
3840 if (fence->temp_syncobj)
3841 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3842 if (fence->syncobj)
3843 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3844 if (fence->fence)
3845 device->ws->destroy_fence(fence->fence);
3846 if (fence->fence_wsi)
3847 fence->fence_wsi->destroy(fence->fence_wsi);
3848 vk_free2(&device->alloc, pAllocator, fence);
3849 }
3850
3851
3852 uint64_t radv_get_current_time(void)
3853 {
3854 struct timespec tv;
3855 clock_gettime(CLOCK_MONOTONIC, &tv);
3856 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3857 }
3858
3859 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3860 {
3861 uint64_t current_time = radv_get_current_time();
3862
3863 timeout = MIN2(UINT64_MAX - current_time, timeout);
3864
3865 return current_time + timeout;
3866 }
3867
3868
3869 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3870 uint32_t fenceCount, const VkFence *pFences)
3871 {
3872 for (uint32_t i = 0; i < fenceCount; ++i) {
3873 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3874 if (fence->fence == NULL || fence->syncobj ||
3875 fence->temp_syncobj || fence->fence_wsi ||
3876 (!device->ws->is_fence_waitable(fence->fence)))
3877 return false;
3878 }
3879 return true;
3880 }
3881
3882 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3883 {
3884 for (uint32_t i = 0; i < fenceCount; ++i) {
3885 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3886 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3887 return false;
3888 }
3889 return true;
3890 }
3891
3892 VkResult radv_WaitForFences(
3893 VkDevice _device,
3894 uint32_t fenceCount,
3895 const VkFence* pFences,
3896 VkBool32 waitAll,
3897 uint64_t timeout)
3898 {
3899 RADV_FROM_HANDLE(radv_device, device, _device);
3900 timeout = radv_get_absolute_timeout(timeout);
3901
3902 if (device->always_use_syncobj &&
3903 radv_all_fences_syncobj(fenceCount, pFences))
3904 {
3905 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3906 if (!handles)
3907 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3908
3909 for (uint32_t i = 0; i < fenceCount; ++i) {
3910 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3911 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3912 }
3913
3914 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3915
3916 free(handles);
3917 return success ? VK_SUCCESS : VK_TIMEOUT;
3918 }
3919
3920 if (!waitAll && fenceCount > 1) {
3921 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3922 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3923 uint32_t wait_count = 0;
3924 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3925 if (!fences)
3926 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3927
3928 for (uint32_t i = 0; i < fenceCount; ++i) {
3929 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3930
3931 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3932 free(fences);
3933 return VK_SUCCESS;
3934 }
3935
3936 fences[wait_count++] = fence->fence;
3937 }
3938
3939 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3940 waitAll, timeout - radv_get_current_time());
3941
3942 free(fences);
3943 return success ? VK_SUCCESS : VK_TIMEOUT;
3944 }
3945
3946 while(radv_get_current_time() <= timeout) {
3947 for (uint32_t i = 0; i < fenceCount; ++i) {
3948 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3949 return VK_SUCCESS;
3950 }
3951 }
3952 return VK_TIMEOUT;
3953 }
3954
3955 for (uint32_t i = 0; i < fenceCount; ++i) {
3956 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3957 bool expired = false;
3958
3959 if (fence->temp_syncobj) {
3960 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3961 return VK_TIMEOUT;
3962 continue;
3963 }
3964
3965 if (fence->syncobj) {
3966 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3967 return VK_TIMEOUT;
3968 continue;
3969 }
3970
3971 if (fence->fence) {
3972 if (!device->ws->is_fence_waitable(fence->fence)) {
3973 while(!device->ws->is_fence_waitable(fence->fence) &&
3974 radv_get_current_time() <= timeout)
3975 /* Do nothing */;
3976 }
3977
3978 expired = device->ws->fence_wait(device->ws,
3979 fence->fence,
3980 true, timeout);
3981 if (!expired)
3982 return VK_TIMEOUT;
3983 }
3984
3985 if (fence->fence_wsi) {
3986 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3987 if (result != VK_SUCCESS)
3988 return result;
3989 }
3990 }
3991
3992 return VK_SUCCESS;
3993 }
3994
3995 VkResult radv_ResetFences(VkDevice _device,
3996 uint32_t fenceCount,
3997 const VkFence *pFences)
3998 {
3999 RADV_FROM_HANDLE(radv_device, device, _device);
4000
4001 for (unsigned i = 0; i < fenceCount; ++i) {
4002 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4003 if (fence->fence)
4004 device->ws->reset_fence(fence->fence);
4005
4006 /* Per spec, we first restore the permanent payload, and then reset, so
4007 * having a temp syncobj should not skip resetting the permanent syncobj. */
4008 if (fence->temp_syncobj) {
4009 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
4010 fence->temp_syncobj = 0;
4011 }
4012
4013 if (fence->syncobj) {
4014 device->ws->reset_syncobj(device->ws, fence->syncobj);
4015 }
4016 }
4017
4018 return VK_SUCCESS;
4019 }
4020
4021 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
4022 {
4023 RADV_FROM_HANDLE(radv_device, device, _device);
4024 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4025
4026 if (fence->temp_syncobj) {
4027 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
4028 return success ? VK_SUCCESS : VK_NOT_READY;
4029 }
4030
4031 if (fence->syncobj) {
4032 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
4033 return success ? VK_SUCCESS : VK_NOT_READY;
4034 }
4035
4036 if (fence->fence) {
4037 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
4038 return VK_NOT_READY;
4039 }
4040 if (fence->fence_wsi) {
4041 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
4042
4043 if (result != VK_SUCCESS) {
4044 if (result == VK_TIMEOUT)
4045 return VK_NOT_READY;
4046 return result;
4047 }
4048 }
4049 return VK_SUCCESS;
4050 }
4051
4052
4053 // Queue semaphore functions
4054
4055 VkResult radv_CreateSemaphore(
4056 VkDevice _device,
4057 const VkSemaphoreCreateInfo* pCreateInfo,
4058 const VkAllocationCallbacks* pAllocator,
4059 VkSemaphore* pSemaphore)
4060 {
4061 RADV_FROM_HANDLE(radv_device, device, _device);
4062 const VkExportSemaphoreCreateInfo *export =
4063 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4064 VkExternalSemaphoreHandleTypeFlags handleTypes =
4065 export ? export->handleTypes : 0;
4066
4067 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4068 sizeof(*sem), 8,
4069 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4070 if (!sem)
4071 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4072
4073 sem->temp_syncobj = 0;
4074 /* create a syncobject if we are going to export this semaphore */
4075 if (device->always_use_syncobj || handleTypes) {
4076 assert (device->physical_device->rad_info.has_syncobj);
4077 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4078 if (ret) {
4079 vk_free2(&device->alloc, pAllocator, sem);
4080 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4081 }
4082 sem->sem = NULL;
4083 } else {
4084 sem->sem = device->ws->create_sem(device->ws);
4085 if (!sem->sem) {
4086 vk_free2(&device->alloc, pAllocator, sem);
4087 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4088 }
4089 sem->syncobj = 0;
4090 }
4091
4092 *pSemaphore = radv_semaphore_to_handle(sem);
4093 return VK_SUCCESS;
4094 }
4095
4096 void radv_DestroySemaphore(
4097 VkDevice _device,
4098 VkSemaphore _semaphore,
4099 const VkAllocationCallbacks* pAllocator)
4100 {
4101 RADV_FROM_HANDLE(radv_device, device, _device);
4102 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4103 if (!_semaphore)
4104 return;
4105
4106 if (sem->syncobj)
4107 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4108 else
4109 device->ws->destroy_sem(sem->sem);
4110 vk_free2(&device->alloc, pAllocator, sem);
4111 }
4112
4113 VkResult radv_CreateEvent(
4114 VkDevice _device,
4115 const VkEventCreateInfo* pCreateInfo,
4116 const VkAllocationCallbacks* pAllocator,
4117 VkEvent* pEvent)
4118 {
4119 RADV_FROM_HANDLE(radv_device, device, _device);
4120 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4121 sizeof(*event), 8,
4122 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4123
4124 if (!event)
4125 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4126
4127 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4128 RADEON_DOMAIN_GTT,
4129 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4130 RADV_BO_PRIORITY_FENCE);
4131 if (!event->bo) {
4132 vk_free2(&device->alloc, pAllocator, event);
4133 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4134 }
4135
4136 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4137
4138 *pEvent = radv_event_to_handle(event);
4139
4140 return VK_SUCCESS;
4141 }
4142
4143 void radv_DestroyEvent(
4144 VkDevice _device,
4145 VkEvent _event,
4146 const VkAllocationCallbacks* pAllocator)
4147 {
4148 RADV_FROM_HANDLE(radv_device, device, _device);
4149 RADV_FROM_HANDLE(radv_event, event, _event);
4150
4151 if (!event)
4152 return;
4153 device->ws->buffer_destroy(event->bo);
4154 vk_free2(&device->alloc, pAllocator, event);
4155 }
4156
4157 VkResult radv_GetEventStatus(
4158 VkDevice _device,
4159 VkEvent _event)
4160 {
4161 RADV_FROM_HANDLE(radv_event, event, _event);
4162
4163 if (*event->map == 1)
4164 return VK_EVENT_SET;
4165 return VK_EVENT_RESET;
4166 }
4167
4168 VkResult radv_SetEvent(
4169 VkDevice _device,
4170 VkEvent _event)
4171 {
4172 RADV_FROM_HANDLE(radv_event, event, _event);
4173 *event->map = 1;
4174
4175 return VK_SUCCESS;
4176 }
4177
4178 VkResult radv_ResetEvent(
4179 VkDevice _device,
4180 VkEvent _event)
4181 {
4182 RADV_FROM_HANDLE(radv_event, event, _event);
4183 *event->map = 0;
4184
4185 return VK_SUCCESS;
4186 }
4187
4188 VkResult radv_CreateBuffer(
4189 VkDevice _device,
4190 const VkBufferCreateInfo* pCreateInfo,
4191 const VkAllocationCallbacks* pAllocator,
4192 VkBuffer* pBuffer)
4193 {
4194 RADV_FROM_HANDLE(radv_device, device, _device);
4195 struct radv_buffer *buffer;
4196
4197 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4198
4199 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4200 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4201 if (buffer == NULL)
4202 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4203
4204 buffer->size = pCreateInfo->size;
4205 buffer->usage = pCreateInfo->usage;
4206 buffer->bo = NULL;
4207 buffer->offset = 0;
4208 buffer->flags = pCreateInfo->flags;
4209
4210 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4211 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4212
4213 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4214 buffer->bo = device->ws->buffer_create(device->ws,
4215 align64(buffer->size, 4096),
4216 4096, 0, RADEON_FLAG_VIRTUAL,
4217 RADV_BO_PRIORITY_VIRTUAL);
4218 if (!buffer->bo) {
4219 vk_free2(&device->alloc, pAllocator, buffer);
4220 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4221 }
4222 }
4223
4224 *pBuffer = radv_buffer_to_handle(buffer);
4225
4226 return VK_SUCCESS;
4227 }
4228
4229 void radv_DestroyBuffer(
4230 VkDevice _device,
4231 VkBuffer _buffer,
4232 const VkAllocationCallbacks* pAllocator)
4233 {
4234 RADV_FROM_HANDLE(radv_device, device, _device);
4235 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4236
4237 if (!buffer)
4238 return;
4239
4240 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4241 device->ws->buffer_destroy(buffer->bo);
4242
4243 vk_free2(&device->alloc, pAllocator, buffer);
4244 }
4245
4246 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4247 VkDevice device,
4248 const VkBufferDeviceAddressInfoEXT* pInfo)
4249 {
4250 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4251 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4252 }
4253
4254
4255 static inline unsigned
4256 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4257 {
4258 if (stencil)
4259 return plane->surface.u.legacy.stencil_tiling_index[level];
4260 else
4261 return plane->surface.u.legacy.tiling_index[level];
4262 }
4263
4264 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4265 {
4266 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4267 }
4268
4269 static uint32_t
4270 radv_init_dcc_control_reg(struct radv_device *device,
4271 struct radv_image_view *iview)
4272 {
4273 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4274 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4275 unsigned max_compressed_block_size;
4276 unsigned independent_128b_blocks;
4277 unsigned independent_64b_blocks;
4278
4279 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4280 return 0;
4281
4282 if (!device->physical_device->rad_info.has_dedicated_vram) {
4283 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4284 * dGPU and 64 for APU because all of our APUs to date use
4285 * DIMMs which have a request granularity size of 64B while all
4286 * other chips have a 32B request size.
4287 */
4288 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4289 }
4290
4291 if (device->physical_device->rad_info.chip_class >= GFX10) {
4292 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4293 independent_64b_blocks = 0;
4294 independent_128b_blocks = 1;
4295 } else {
4296 independent_128b_blocks = 0;
4297
4298 if (iview->image->info.samples > 1) {
4299 if (iview->image->planes[0].surface.bpe == 1)
4300 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4301 else if (iview->image->planes[0].surface.bpe == 2)
4302 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4303 }
4304
4305 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4306 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4307 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4308 /* If this DCC image is potentially going to be used in texture
4309 * fetches, we need some special settings.
4310 */
4311 independent_64b_blocks = 1;
4312 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4313 } else {
4314 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4315 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4316 * big as possible for better compression state.
4317 */
4318 independent_64b_blocks = 0;
4319 max_compressed_block_size = max_uncompressed_block_size;
4320 }
4321 }
4322
4323 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4324 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4325 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4326 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4327 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4328 }
4329
4330 static void
4331 radv_initialise_color_surface(struct radv_device *device,
4332 struct radv_color_buffer_info *cb,
4333 struct radv_image_view *iview)
4334 {
4335 const struct vk_format_description *desc;
4336 unsigned ntype, format, swap, endian;
4337 unsigned blend_clamp = 0, blend_bypass = 0;
4338 uint64_t va;
4339 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4340 const struct radeon_surf *surf = &plane->surface;
4341
4342 desc = vk_format_description(iview->vk_format);
4343
4344 memset(cb, 0, sizeof(*cb));
4345
4346 /* Intensity is implemented as Red, so treat it that way. */
4347 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4348
4349 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4350
4351 cb->cb_color_base = va >> 8;
4352
4353 if (device->physical_device->rad_info.chip_class >= GFX9) {
4354 struct gfx9_surf_meta_flags meta;
4355 if (iview->image->dcc_offset)
4356 meta = surf->u.gfx9.dcc;
4357 else
4358 meta = surf->u.gfx9.cmask;
4359
4360 if (device->physical_device->rad_info.chip_class >= GFX10) {
4361 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4362 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4363 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4364 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4365 } else {
4366 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4367 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4368 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4369 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4370 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4371 }
4372
4373 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4374 cb->cb_color_base |= surf->tile_swizzle;
4375 } else {
4376 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4377 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4378
4379 cb->cb_color_base += level_info->offset >> 8;
4380 if (level_info->mode == RADEON_SURF_MODE_2D)
4381 cb->cb_color_base |= surf->tile_swizzle;
4382
4383 pitch_tile_max = level_info->nblk_x / 8 - 1;
4384 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4385 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4386
4387 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4388 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4389 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4390
4391 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4392
4393 if (radv_image_has_fmask(iview->image)) {
4394 if (device->physical_device->rad_info.chip_class >= GFX7)
4395 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4396 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4397 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4398 } else {
4399 /* This must be set for fast clear to work without FMASK. */
4400 if (device->physical_device->rad_info.chip_class >= GFX7)
4401 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4402 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4403 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4404 }
4405 }
4406
4407 /* CMASK variables */
4408 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4409 va += iview->image->cmask.offset;
4410 cb->cb_color_cmask = va >> 8;
4411
4412 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4413 va += iview->image->dcc_offset;
4414
4415 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4416 device->physical_device->rad_info.chip_class <= GFX8)
4417 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4418
4419 unsigned dcc_tile_swizzle = surf->tile_swizzle;
4420 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
4421
4422 cb->cb_dcc_base = va >> 8;
4423 cb->cb_dcc_base |= dcc_tile_swizzle;
4424
4425 /* GFX10 field has the same base shift as the GFX6 field. */
4426 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4427 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4428 S_028C6C_SLICE_MAX_GFX10(max_slice);
4429
4430 if (iview->image->info.samples > 1) {
4431 unsigned log_samples = util_logbase2(iview->image->info.samples);
4432
4433 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4434 S_028C74_NUM_FRAGMENTS(log_samples);
4435 }
4436
4437 if (radv_image_has_fmask(iview->image)) {
4438 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4439 cb->cb_color_fmask = va >> 8;
4440 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4441 } else {
4442 cb->cb_color_fmask = cb->cb_color_base;
4443 }
4444
4445 ntype = radv_translate_color_numformat(iview->vk_format,
4446 desc,
4447 vk_format_get_first_non_void_channel(iview->vk_format));
4448 format = radv_translate_colorformat(iview->vk_format);
4449 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4450 radv_finishme("Illegal color\n");
4451 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4452 endian = radv_colorformat_endian_swap(format);
4453
4454 /* blend clamp should be set for all NORM/SRGB types */
4455 if (ntype == V_028C70_NUMBER_UNORM ||
4456 ntype == V_028C70_NUMBER_SNORM ||
4457 ntype == V_028C70_NUMBER_SRGB)
4458 blend_clamp = 1;
4459
4460 /* set blend bypass according to docs if SINT/UINT or
4461 8/24 COLOR variants */
4462 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4463 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4464 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4465 blend_clamp = 0;
4466 blend_bypass = 1;
4467 }
4468 #if 0
4469 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4470 (format == V_028C70_COLOR_8 ||
4471 format == V_028C70_COLOR_8_8 ||
4472 format == V_028C70_COLOR_8_8_8_8))
4473 ->color_is_int8 = true;
4474 #endif
4475 cb->cb_color_info = S_028C70_FORMAT(format) |
4476 S_028C70_COMP_SWAP(swap) |
4477 S_028C70_BLEND_CLAMP(blend_clamp) |
4478 S_028C70_BLEND_BYPASS(blend_bypass) |
4479 S_028C70_SIMPLE_FLOAT(1) |
4480 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4481 ntype != V_028C70_NUMBER_SNORM &&
4482 ntype != V_028C70_NUMBER_SRGB &&
4483 format != V_028C70_COLOR_8_24 &&
4484 format != V_028C70_COLOR_24_8) |
4485 S_028C70_NUMBER_TYPE(ntype) |
4486 S_028C70_ENDIAN(endian);
4487 if (radv_image_has_fmask(iview->image)) {
4488 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4489 if (device->physical_device->rad_info.chip_class == GFX6) {
4490 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4491 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4492 }
4493
4494 if (radv_image_is_tc_compat_cmask(iview->image)) {
4495 /* Allow the texture block to read FMASK directly
4496 * without decompressing it. This bit must be cleared
4497 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4498 * otherwise the operation doesn't happen.
4499 */
4500 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4501
4502 /* Set CMASK into a tiling format that allows the
4503 * texture block to read it.
4504 */
4505 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4506 }
4507 }
4508
4509 if (radv_image_has_cmask(iview->image) &&
4510 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4511 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4512
4513 if (radv_dcc_enabled(iview->image, iview->base_mip))
4514 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4515
4516 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4517
4518 /* This must be set for fast clear to work without FMASK. */
4519 if (!radv_image_has_fmask(iview->image) &&
4520 device->physical_device->rad_info.chip_class == GFX6) {
4521 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4522 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4523 }
4524
4525 if (device->physical_device->rad_info.chip_class >= GFX9) {
4526 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4527
4528 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4529 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4530 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4531 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4532
4533 if (device->physical_device->rad_info.chip_class >= GFX10) {
4534 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4535
4536 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4537 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4538 S_028EE0_RESOURCE_LEVEL(1);
4539 } else {
4540 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4541 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4542 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4543 }
4544
4545 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4546 S_028C68_MIP0_HEIGHT(height - 1) |
4547 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4548 }
4549 }
4550
4551 static unsigned
4552 radv_calc_decompress_on_z_planes(struct radv_device *device,
4553 struct radv_image_view *iview)
4554 {
4555 unsigned max_zplanes = 0;
4556
4557 assert(radv_image_is_tc_compat_htile(iview->image));
4558
4559 if (device->physical_device->rad_info.chip_class >= GFX9) {
4560 /* Default value for 32-bit depth surfaces. */
4561 max_zplanes = 4;
4562
4563 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4564 iview->image->info.samples > 1)
4565 max_zplanes = 2;
4566
4567 max_zplanes = max_zplanes + 1;
4568 } else {
4569 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4570 /* Do not enable Z plane compression for 16-bit depth
4571 * surfaces because isn't supported on GFX8. Only
4572 * 32-bit depth surfaces are supported by the hardware.
4573 * This allows to maintain shader compatibility and to
4574 * reduce the number of depth decompressions.
4575 */
4576 max_zplanes = 1;
4577 } else {
4578 if (iview->image->info.samples <= 1)
4579 max_zplanes = 5;
4580 else if (iview->image->info.samples <= 4)
4581 max_zplanes = 3;
4582 else
4583 max_zplanes = 2;
4584 }
4585 }
4586
4587 return max_zplanes;
4588 }
4589
4590 static void
4591 radv_initialise_ds_surface(struct radv_device *device,
4592 struct radv_ds_buffer_info *ds,
4593 struct radv_image_view *iview)
4594 {
4595 unsigned level = iview->base_mip;
4596 unsigned format, stencil_format;
4597 uint64_t va, s_offs, z_offs;
4598 bool stencil_only = false;
4599 const struct radv_image_plane *plane = &iview->image->planes[0];
4600 const struct radeon_surf *surf = &plane->surface;
4601
4602 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4603
4604 memset(ds, 0, sizeof(*ds));
4605 switch (iview->image->vk_format) {
4606 case VK_FORMAT_D24_UNORM_S8_UINT:
4607 case VK_FORMAT_X8_D24_UNORM_PACK32:
4608 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4609 ds->offset_scale = 2.0f;
4610 break;
4611 case VK_FORMAT_D16_UNORM:
4612 case VK_FORMAT_D16_UNORM_S8_UINT:
4613 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4614 ds->offset_scale = 4.0f;
4615 break;
4616 case VK_FORMAT_D32_SFLOAT:
4617 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4618 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4619 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4620 ds->offset_scale = 1.0f;
4621 break;
4622 case VK_FORMAT_S8_UINT:
4623 stencil_only = true;
4624 break;
4625 default:
4626 break;
4627 }
4628
4629 format = radv_translate_dbformat(iview->image->vk_format);
4630 stencil_format = surf->has_stencil ?
4631 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4632
4633 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4634 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4635 S_028008_SLICE_MAX(max_slice);
4636 if (device->physical_device->rad_info.chip_class >= GFX10) {
4637 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4638 S_028008_SLICE_MAX_HI(max_slice >> 11);
4639 }
4640
4641 ds->db_htile_data_base = 0;
4642 ds->db_htile_surface = 0;
4643
4644 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4645 s_offs = z_offs = va;
4646
4647 if (device->physical_device->rad_info.chip_class >= GFX9) {
4648 assert(surf->u.gfx9.surf_offset == 0);
4649 s_offs += surf->u.gfx9.stencil_offset;
4650
4651 ds->db_z_info = S_028038_FORMAT(format) |
4652 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4653 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4654 S_028038_MAXMIP(iview->image->info.levels - 1) |
4655 S_028038_ZRANGE_PRECISION(1);
4656 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4657 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4658
4659 if (device->physical_device->rad_info.chip_class == GFX9) {
4660 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4661 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4662 }
4663
4664 ds->db_depth_view |= S_028008_MIPID(level);
4665 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4666 S_02801C_Y_MAX(iview->image->info.height - 1);
4667
4668 if (radv_htile_enabled(iview->image, level)) {
4669 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4670
4671 if (radv_image_is_tc_compat_htile(iview->image)) {
4672 unsigned max_zplanes =
4673 radv_calc_decompress_on_z_planes(device, iview);
4674
4675 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4676
4677 if (device->physical_device->rad_info.chip_class >= GFX10) {
4678 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4679 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4680 } else {
4681 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4682 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4683 }
4684 }
4685
4686 if (!surf->has_stencil)
4687 /* Use all of the htile_buffer for depth if there's no stencil. */
4688 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4689 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4690 iview->image->htile_offset;
4691 ds->db_htile_data_base = va >> 8;
4692 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4693 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4694
4695 if (device->physical_device->rad_info.chip_class == GFX9) {
4696 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4697 }
4698 }
4699 } else {
4700 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4701
4702 if (stencil_only)
4703 level_info = &surf->u.legacy.stencil_level[level];
4704
4705 z_offs += surf->u.legacy.level[level].offset;
4706 s_offs += surf->u.legacy.stencil_level[level].offset;
4707
4708 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4709 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4710 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4711
4712 if (iview->image->info.samples > 1)
4713 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4714
4715 if (device->physical_device->rad_info.chip_class >= GFX7) {
4716 struct radeon_info *info = &device->physical_device->rad_info;
4717 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4718 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4719 unsigned macro_index = surf->u.legacy.macro_tile_index;
4720 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4721 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4722 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4723
4724 if (stencil_only)
4725 tile_mode = stencil_tile_mode;
4726
4727 ds->db_depth_info |=
4728 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4729 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4730 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4731 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4732 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4733 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4734 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4735 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4736 } else {
4737 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4738 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4739 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4740 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4741 if (stencil_only)
4742 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4743 }
4744
4745 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4746 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4747 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4748
4749 if (radv_htile_enabled(iview->image, level)) {
4750 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4751
4752 if (!surf->has_stencil &&
4753 !radv_image_is_tc_compat_htile(iview->image))
4754 /* Use all of the htile_buffer for depth if there's no stencil. */
4755 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4756
4757 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4758 iview->image->htile_offset;
4759 ds->db_htile_data_base = va >> 8;
4760 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4761
4762 if (radv_image_is_tc_compat_htile(iview->image)) {
4763 unsigned max_zplanes =
4764 radv_calc_decompress_on_z_planes(device, iview);
4765
4766 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4767 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4768 }
4769 }
4770 }
4771
4772 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4773 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4774 }
4775
4776 VkResult radv_CreateFramebuffer(
4777 VkDevice _device,
4778 const VkFramebufferCreateInfo* pCreateInfo,
4779 const VkAllocationCallbacks* pAllocator,
4780 VkFramebuffer* pFramebuffer)
4781 {
4782 RADV_FROM_HANDLE(radv_device, device, _device);
4783 struct radv_framebuffer *framebuffer;
4784
4785 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4786
4787 size_t size = sizeof(*framebuffer) +
4788 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4789 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4790 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4791 if (framebuffer == NULL)
4792 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4793
4794 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4795 framebuffer->width = pCreateInfo->width;
4796 framebuffer->height = pCreateInfo->height;
4797 framebuffer->layers = pCreateInfo->layers;
4798 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4799 VkImageView _iview = pCreateInfo->pAttachments[i];
4800 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4801 framebuffer->attachments[i].attachment = iview;
4802 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4803 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4804 } else {
4805 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4806 }
4807 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4808 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4809 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4810 }
4811
4812 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4813 return VK_SUCCESS;
4814 }
4815
4816 void radv_DestroyFramebuffer(
4817 VkDevice _device,
4818 VkFramebuffer _fb,
4819 const VkAllocationCallbacks* pAllocator)
4820 {
4821 RADV_FROM_HANDLE(radv_device, device, _device);
4822 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4823
4824 if (!fb)
4825 return;
4826 vk_free2(&device->alloc, pAllocator, fb);
4827 }
4828
4829 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4830 {
4831 switch (address_mode) {
4832 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4833 return V_008F30_SQ_TEX_WRAP;
4834 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4835 return V_008F30_SQ_TEX_MIRROR;
4836 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4837 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4838 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4839 return V_008F30_SQ_TEX_CLAMP_BORDER;
4840 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4841 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4842 default:
4843 unreachable("illegal tex wrap mode");
4844 break;
4845 }
4846 }
4847
4848 static unsigned
4849 radv_tex_compare(VkCompareOp op)
4850 {
4851 switch (op) {
4852 case VK_COMPARE_OP_NEVER:
4853 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4854 case VK_COMPARE_OP_LESS:
4855 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4856 case VK_COMPARE_OP_EQUAL:
4857 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4858 case VK_COMPARE_OP_LESS_OR_EQUAL:
4859 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4860 case VK_COMPARE_OP_GREATER:
4861 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4862 case VK_COMPARE_OP_NOT_EQUAL:
4863 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4864 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4865 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4866 case VK_COMPARE_OP_ALWAYS:
4867 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4868 default:
4869 unreachable("illegal compare mode");
4870 break;
4871 }
4872 }
4873
4874 static unsigned
4875 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4876 {
4877 switch (filter) {
4878 case VK_FILTER_NEAREST:
4879 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4880 V_008F38_SQ_TEX_XY_FILTER_POINT);
4881 case VK_FILTER_LINEAR:
4882 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4883 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4884 case VK_FILTER_CUBIC_IMG:
4885 default:
4886 fprintf(stderr, "illegal texture filter");
4887 return 0;
4888 }
4889 }
4890
4891 static unsigned
4892 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4893 {
4894 switch (mode) {
4895 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4896 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4897 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4898 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4899 default:
4900 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4901 }
4902 }
4903
4904 static unsigned
4905 radv_tex_bordercolor(VkBorderColor bcolor)
4906 {
4907 switch (bcolor) {
4908 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4909 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4910 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4911 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4912 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4913 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4914 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4915 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4916 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4917 default:
4918 break;
4919 }
4920 return 0;
4921 }
4922
4923 static unsigned
4924 radv_tex_aniso_filter(unsigned filter)
4925 {
4926 if (filter < 2)
4927 return 0;
4928 if (filter < 4)
4929 return 1;
4930 if (filter < 8)
4931 return 2;
4932 if (filter < 16)
4933 return 3;
4934 return 4;
4935 }
4936
4937 static unsigned
4938 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4939 {
4940 switch (mode) {
4941 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4942 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4943 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4944 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4945 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4946 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4947 default:
4948 break;
4949 }
4950 return 0;
4951 }
4952
4953 static uint32_t
4954 radv_get_max_anisotropy(struct radv_device *device,
4955 const VkSamplerCreateInfo *pCreateInfo)
4956 {
4957 if (device->force_aniso >= 0)
4958 return device->force_aniso;
4959
4960 if (pCreateInfo->anisotropyEnable &&
4961 pCreateInfo->maxAnisotropy > 1.0f)
4962 return (uint32_t)pCreateInfo->maxAnisotropy;
4963
4964 return 0;
4965 }
4966
4967 static void
4968 radv_init_sampler(struct radv_device *device,
4969 struct radv_sampler *sampler,
4970 const VkSamplerCreateInfo *pCreateInfo)
4971 {
4972 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4973 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4974 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
4975 device->physical_device->rad_info.chip_class == GFX9;
4976 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4977
4978 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4979 vk_find_struct_const(pCreateInfo->pNext,
4980 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4981 if (sampler_reduction)
4982 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4983
4984 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4985 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4986 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4987 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4988 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4989 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4990 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4991 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4992 S_008F30_DISABLE_CUBE_WRAP(0) |
4993 S_008F30_COMPAT_MODE(compat_mode) |
4994 S_008F30_FILTER_MODE(filter_mode));
4995 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4996 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4997 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4998 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4999 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
5000 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
5001 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
5002 S_008F38_MIP_POINT_PRECLAMP(0));
5003 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5004 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
5005
5006 if (device->physical_device->rad_info.chip_class >= GFX10) {
5007 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5008 } else {
5009 sampler->state[2] |=
5010 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
5011 S_008F38_FILTER_PREC_FIX(1) |
5012 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
5013 }
5014 }
5015
5016 VkResult radv_CreateSampler(
5017 VkDevice _device,
5018 const VkSamplerCreateInfo* pCreateInfo,
5019 const VkAllocationCallbacks* pAllocator,
5020 VkSampler* pSampler)
5021 {
5022 RADV_FROM_HANDLE(radv_device, device, _device);
5023 struct radv_sampler *sampler;
5024
5025 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
5026 vk_find_struct_const(pCreateInfo->pNext,
5027 SAMPLER_YCBCR_CONVERSION_INFO);
5028
5029 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
5030
5031 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
5032 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5033 if (!sampler)
5034 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5035
5036 radv_init_sampler(device, sampler, pCreateInfo);
5037
5038 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
5039 *pSampler = radv_sampler_to_handle(sampler);
5040
5041 return VK_SUCCESS;
5042 }
5043
5044 void radv_DestroySampler(
5045 VkDevice _device,
5046 VkSampler _sampler,
5047 const VkAllocationCallbacks* pAllocator)
5048 {
5049 RADV_FROM_HANDLE(radv_device, device, _device);
5050 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
5051
5052 if (!sampler)
5053 return;
5054 vk_free2(&device->alloc, pAllocator, sampler);
5055 }
5056
5057 /* vk_icd.h does not declare this function, so we declare it here to
5058 * suppress Wmissing-prototypes.
5059 */
5060 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5061 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5062
5063 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5064 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5065 {
5066 /* For the full details on loader interface versioning, see
5067 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5068 * What follows is a condensed summary, to help you navigate the large and
5069 * confusing official doc.
5070 *
5071 * - Loader interface v0 is incompatible with later versions. We don't
5072 * support it.
5073 *
5074 * - In loader interface v1:
5075 * - The first ICD entrypoint called by the loader is
5076 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5077 * entrypoint.
5078 * - The ICD must statically expose no other Vulkan symbol unless it is
5079 * linked with -Bsymbolic.
5080 * - Each dispatchable Vulkan handle created by the ICD must be
5081 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5082 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5083 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5084 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5085 * such loader-managed surfaces.
5086 *
5087 * - Loader interface v2 differs from v1 in:
5088 * - The first ICD entrypoint called by the loader is
5089 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5090 * statically expose this entrypoint.
5091 *
5092 * - Loader interface v3 differs from v2 in:
5093 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5094 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5095 * because the loader no longer does so.
5096 */
5097 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5098 return VK_SUCCESS;
5099 }
5100
5101 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5102 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5103 int *pFD)
5104 {
5105 RADV_FROM_HANDLE(radv_device, device, _device);
5106 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5107
5108 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5109
5110 /* At the moment, we support only the below handle types. */
5111 assert(pGetFdInfo->handleType ==
5112 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5113 pGetFdInfo->handleType ==
5114 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5115
5116 bool ret = radv_get_memory_fd(device, memory, pFD);
5117 if (ret == false)
5118 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5119 return VK_SUCCESS;
5120 }
5121
5122 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5123 VkExternalMemoryHandleTypeFlagBits handleType,
5124 int fd,
5125 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5126 {
5127 RADV_FROM_HANDLE(radv_device, device, _device);
5128
5129 switch (handleType) {
5130 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5131 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5132 return VK_SUCCESS;
5133
5134 default:
5135 /* The valid usage section for this function says:
5136 *
5137 * "handleType must not be one of the handle types defined as
5138 * opaque."
5139 *
5140 * So opaque handle types fall into the default "unsupported" case.
5141 */
5142 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5143 }
5144 }
5145
5146 static VkResult radv_import_opaque_fd(struct radv_device *device,
5147 int fd,
5148 uint32_t *syncobj)
5149 {
5150 uint32_t syncobj_handle = 0;
5151 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5152 if (ret != 0)
5153 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5154
5155 if (*syncobj)
5156 device->ws->destroy_syncobj(device->ws, *syncobj);
5157
5158 *syncobj = syncobj_handle;
5159 close(fd);
5160
5161 return VK_SUCCESS;
5162 }
5163
5164 static VkResult radv_import_sync_fd(struct radv_device *device,
5165 int fd,
5166 uint32_t *syncobj)
5167 {
5168 /* If we create a syncobj we do it locally so that if we have an error, we don't
5169 * leave a syncobj in an undetermined state in the fence. */
5170 uint32_t syncobj_handle = *syncobj;
5171 if (!syncobj_handle) {
5172 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5173 if (ret) {
5174 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5175 }
5176 }
5177
5178 if (fd == -1) {
5179 device->ws->signal_syncobj(device->ws, syncobj_handle);
5180 } else {
5181 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5182 if (ret != 0)
5183 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5184 }
5185
5186 *syncobj = syncobj_handle;
5187 if (fd != -1)
5188 close(fd);
5189
5190 return VK_SUCCESS;
5191 }
5192
5193 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5194 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5195 {
5196 RADV_FROM_HANDLE(radv_device, device, _device);
5197 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5198 uint32_t *syncobj_dst = NULL;
5199
5200 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5201 syncobj_dst = &sem->temp_syncobj;
5202 } else {
5203 syncobj_dst = &sem->syncobj;
5204 }
5205
5206 switch(pImportSemaphoreFdInfo->handleType) {
5207 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5208 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5209 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5210 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5211 default:
5212 unreachable("Unhandled semaphore handle type");
5213 }
5214 }
5215
5216 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5217 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5218 int *pFd)
5219 {
5220 RADV_FROM_HANDLE(radv_device, device, _device);
5221 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5222 int ret;
5223 uint32_t syncobj_handle;
5224
5225 if (sem->temp_syncobj)
5226 syncobj_handle = sem->temp_syncobj;
5227 else
5228 syncobj_handle = sem->syncobj;
5229
5230 switch(pGetFdInfo->handleType) {
5231 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5232 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5233 break;
5234 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5235 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5236 if (!ret) {
5237 if (sem->temp_syncobj) {
5238 close (sem->temp_syncobj);
5239 sem->temp_syncobj = 0;
5240 } else {
5241 device->ws->reset_syncobj(device->ws, syncobj_handle);
5242 }
5243 }
5244 break;
5245 default:
5246 unreachable("Unhandled semaphore handle type");
5247 }
5248
5249 if (ret)
5250 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5251 return VK_SUCCESS;
5252 }
5253
5254 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5255 VkPhysicalDevice physicalDevice,
5256 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5257 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5258 {
5259 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5260
5261 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5262 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5263 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5264 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5265 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5266 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5267 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5268 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5269 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5270 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5271 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5272 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5273 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5274 } else {
5275 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5276 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5277 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5278 }
5279 }
5280
5281 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5282 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5283 {
5284 RADV_FROM_HANDLE(radv_device, device, _device);
5285 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5286 uint32_t *syncobj_dst = NULL;
5287
5288
5289 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5290 syncobj_dst = &fence->temp_syncobj;
5291 } else {
5292 syncobj_dst = &fence->syncobj;
5293 }
5294
5295 switch(pImportFenceFdInfo->handleType) {
5296 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5297 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5298 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5299 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5300 default:
5301 unreachable("Unhandled fence handle type");
5302 }
5303 }
5304
5305 VkResult radv_GetFenceFdKHR(VkDevice _device,
5306 const VkFenceGetFdInfoKHR *pGetFdInfo,
5307 int *pFd)
5308 {
5309 RADV_FROM_HANDLE(radv_device, device, _device);
5310 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5311 int ret;
5312 uint32_t syncobj_handle;
5313
5314 if (fence->temp_syncobj)
5315 syncobj_handle = fence->temp_syncobj;
5316 else
5317 syncobj_handle = fence->syncobj;
5318
5319 switch(pGetFdInfo->handleType) {
5320 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5321 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5322 break;
5323 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5324 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5325 if (!ret) {
5326 if (fence->temp_syncobj) {
5327 close (fence->temp_syncobj);
5328 fence->temp_syncobj = 0;
5329 } else {
5330 device->ws->reset_syncobj(device->ws, syncobj_handle);
5331 }
5332 }
5333 break;
5334 default:
5335 unreachable("Unhandled fence handle type");
5336 }
5337
5338 if (ret)
5339 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5340 return VK_SUCCESS;
5341 }
5342
5343 void radv_GetPhysicalDeviceExternalFenceProperties(
5344 VkPhysicalDevice physicalDevice,
5345 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5346 VkExternalFenceProperties *pExternalFenceProperties)
5347 {
5348 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5349
5350 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5351 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5352 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5353 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5354 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5355 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5356 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5357 } else {
5358 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5359 pExternalFenceProperties->compatibleHandleTypes = 0;
5360 pExternalFenceProperties->externalFenceFeatures = 0;
5361 }
5362 }
5363
5364 VkResult
5365 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5366 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5367 const VkAllocationCallbacks* pAllocator,
5368 VkDebugReportCallbackEXT* pCallback)
5369 {
5370 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5371 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5372 pCreateInfo, pAllocator, &instance->alloc,
5373 pCallback);
5374 }
5375
5376 void
5377 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5378 VkDebugReportCallbackEXT _callback,
5379 const VkAllocationCallbacks* pAllocator)
5380 {
5381 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5382 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5383 _callback, pAllocator, &instance->alloc);
5384 }
5385
5386 void
5387 radv_DebugReportMessageEXT(VkInstance _instance,
5388 VkDebugReportFlagsEXT flags,
5389 VkDebugReportObjectTypeEXT objectType,
5390 uint64_t object,
5391 size_t location,
5392 int32_t messageCode,
5393 const char* pLayerPrefix,
5394 const char* pMessage)
5395 {
5396 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5397 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5398 object, location, messageCode, pLayerPrefix, pMessage);
5399 }
5400
5401 void
5402 radv_GetDeviceGroupPeerMemoryFeatures(
5403 VkDevice device,
5404 uint32_t heapIndex,
5405 uint32_t localDeviceIndex,
5406 uint32_t remoteDeviceIndex,
5407 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5408 {
5409 assert(localDeviceIndex == remoteDeviceIndex);
5410
5411 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5412 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5413 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5414 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5415 }
5416
5417 static const VkTimeDomainEXT radv_time_domains[] = {
5418 VK_TIME_DOMAIN_DEVICE_EXT,
5419 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5420 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5421 };
5422
5423 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5424 VkPhysicalDevice physicalDevice,
5425 uint32_t *pTimeDomainCount,
5426 VkTimeDomainEXT *pTimeDomains)
5427 {
5428 int d;
5429 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5430
5431 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5432 vk_outarray_append(&out, i) {
5433 *i = radv_time_domains[d];
5434 }
5435 }
5436
5437 return vk_outarray_status(&out);
5438 }
5439
5440 static uint64_t
5441 radv_clock_gettime(clockid_t clock_id)
5442 {
5443 struct timespec current;
5444 int ret;
5445
5446 ret = clock_gettime(clock_id, &current);
5447 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5448 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5449 if (ret < 0)
5450 return 0;
5451
5452 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5453 }
5454
5455 VkResult radv_GetCalibratedTimestampsEXT(
5456 VkDevice _device,
5457 uint32_t timestampCount,
5458 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5459 uint64_t *pTimestamps,
5460 uint64_t *pMaxDeviation)
5461 {
5462 RADV_FROM_HANDLE(radv_device, device, _device);
5463 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5464 int d;
5465 uint64_t begin, end;
5466 uint64_t max_clock_period = 0;
5467
5468 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5469
5470 for (d = 0; d < timestampCount; d++) {
5471 switch (pTimestampInfos[d].timeDomain) {
5472 case VK_TIME_DOMAIN_DEVICE_EXT:
5473 pTimestamps[d] = device->ws->query_value(device->ws,
5474 RADEON_TIMESTAMP);
5475 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5476 max_clock_period = MAX2(max_clock_period, device_period);
5477 break;
5478 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5479 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5480 max_clock_period = MAX2(max_clock_period, 1);
5481 break;
5482
5483 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5484 pTimestamps[d] = begin;
5485 break;
5486 default:
5487 pTimestamps[d] = 0;
5488 break;
5489 }
5490 }
5491
5492 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5493
5494 /*
5495 * The maximum deviation is the sum of the interval over which we
5496 * perform the sampling and the maximum period of any sampled
5497 * clock. That's because the maximum skew between any two sampled
5498 * clock edges is when the sampled clock with the largest period is
5499 * sampled at the end of that period but right at the beginning of the
5500 * sampling interval and some other clock is sampled right at the
5501 * begining of its sampling period and right at the end of the
5502 * sampling interval. Let's assume the GPU has the longest clock
5503 * period and that the application is sampling GPU and monotonic:
5504 *
5505 * s e
5506 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5507 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5508 *
5509 * g
5510 * 0 1 2 3
5511 * GPU -----_____-----_____-----_____-----_____
5512 *
5513 * m
5514 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5515 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5516 *
5517 * Interval <----------------->
5518 * Deviation <-------------------------->
5519 *
5520 * s = read(raw) 2
5521 * g = read(GPU) 1
5522 * m = read(monotonic) 2
5523 * e = read(raw) b
5524 *
5525 * We round the sample interval up by one tick to cover sampling error
5526 * in the interval clock
5527 */
5528
5529 uint64_t sample_interval = end - begin + 1;
5530
5531 *pMaxDeviation = sample_interval + max_clock_period;
5532
5533 return VK_SUCCESS;
5534 }
5535
5536 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5537 VkPhysicalDevice physicalDevice,
5538 VkSampleCountFlagBits samples,
5539 VkMultisamplePropertiesEXT* pMultisampleProperties)
5540 {
5541 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5542 VK_SAMPLE_COUNT_4_BIT |
5543 VK_SAMPLE_COUNT_8_BIT)) {
5544 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5545 } else {
5546 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5547 }
5548 }