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amd/common: use generated register header
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
52
53 static int
54 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
55 {
56 struct mesa_sha1 ctx;
57 unsigned char sha1[20];
58 unsigned ptr_size = sizeof(void*);
59
60 memset(uuid, 0, VK_UUID_SIZE);
61 _mesa_sha1_init(&ctx);
62
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
65 return -1;
66
67 _mesa_sha1_update(&ctx, &family, sizeof(family));
68 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
69 _mesa_sha1_final(&ctx, sha1);
70
71 memcpy(uuid, sha1, VK_UUID_SIZE);
72 return 0;
73 }
74
75 static void
76 radv_get_driver_uuid(void *uuid)
77 {
78 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
79 }
80
81 static void
82 radv_get_device_uuid(struct radeon_info *info, void *uuid)
83 {
84 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
85 }
86
87 static void
88 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
89 {
90 const char *chip_string;
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
103 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
110 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 default: chip_string = "AMD RADV unknown"; break;
117 }
118
119 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
120 }
121
122 static uint64_t
123 radv_get_visible_vram_size(struct radv_physical_device *device)
124 {
125 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
126 }
127
128 static uint64_t
129 radv_get_vram_size(struct radv_physical_device *device)
130 {
131 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
132 }
133
134 static void
135 radv_physical_device_init_mem_types(struct radv_physical_device *device)
136 {
137 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
138 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
139 uint64_t vram_size = radv_get_vram_size(device);
140 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
141 device->memory_properties.memoryHeapCount = 0;
142 if (vram_size > 0) {
143 vram_index = device->memory_properties.memoryHeapCount++;
144 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
145 .size = vram_size,
146 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
147 };
148 }
149 if (visible_vram_size) {
150 visible_vram_index = device->memory_properties.memoryHeapCount++;
151 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
152 .size = visible_vram_size,
153 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
154 };
155 }
156 if (device->rad_info.gart_size > 0) {
157 gart_index = device->memory_properties.memoryHeapCount++;
158 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
159 .size = device->rad_info.gart_size,
160 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
161 };
162 }
163
164 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
165 unsigned type_count = 0;
166 if (vram_index >= 0) {
167 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
170 .heapIndex = vram_index,
171 };
172 }
173 if (gart_index >= 0) {
174 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
175 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
176 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
177 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
178 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
179 .heapIndex = gart_index,
180 };
181 }
182 if (visible_vram_index >= 0) {
183 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
184 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
185 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
186 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
187 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
188 .heapIndex = visible_vram_index,
189 };
190 }
191 if (gart_index >= 0) {
192 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
193 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
194 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
195 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
196 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
197 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
198 .heapIndex = gart_index,
199 };
200 }
201 device->memory_properties.memoryTypeCount = type_count;
202 }
203
204 static void
205 radv_handle_env_var_force_family(struct radv_physical_device *device)
206 {
207 const char *family = getenv("RADV_FORCE_FAMILY");
208 unsigned i;
209
210 if (!family)
211 return;
212
213 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
214 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
215 /* Override family and chip_class. */
216 device->rad_info.family = i;
217
218 if (i >= CHIP_VEGA10)
219 device->rad_info.chip_class = GFX9;
220 else if (i >= CHIP_TONGA)
221 device->rad_info.chip_class = GFX8;
222 else if (i >= CHIP_BONAIRE)
223 device->rad_info.chip_class = GFX7;
224 else
225 device->rad_info.chip_class = GFX6;
226
227 return;
228 }
229 }
230
231 fprintf(stderr, "radv: Unknown family: %s\n", family);
232 exit(1);
233 }
234
235 static VkResult
236 radv_physical_device_init(struct radv_physical_device *device,
237 struct radv_instance *instance,
238 drmDevicePtr drm_device)
239 {
240 const char *path = drm_device->nodes[DRM_NODE_RENDER];
241 VkResult result;
242 drmVersionPtr version;
243 int fd;
244 int master_fd = -1;
245
246 fd = open(path, O_RDWR | O_CLOEXEC);
247 if (fd < 0) {
248 if (instance->debug_flags & RADV_DEBUG_STARTUP)
249 radv_logi("Could not open device '%s'", path);
250
251 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
252 }
253
254 version = drmGetVersion(fd);
255 if (!version) {
256 close(fd);
257
258 if (instance->debug_flags & RADV_DEBUG_STARTUP)
259 radv_logi("Could not get the kernel driver version for device '%s'", path);
260
261 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
262 "failed to get version %s: %m", path);
263 }
264
265 if (strcmp(version->name, "amdgpu")) {
266 drmFreeVersion(version);
267 close(fd);
268
269 if (instance->debug_flags & RADV_DEBUG_STARTUP)
270 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
271
272 return VK_ERROR_INCOMPATIBLE_DRIVER;
273 }
274 drmFreeVersion(version);
275
276 if (instance->debug_flags & RADV_DEBUG_STARTUP)
277 radv_logi("Found compatible device '%s'.", path);
278
279 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
280 device->instance = instance;
281
282 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
283 instance->perftest_flags);
284 if (!device->ws) {
285 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
286 goto fail;
287 }
288
289 if (instance->enabled_extensions.KHR_display) {
290 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
291 if (master_fd >= 0) {
292 uint32_t accel_working = 0;
293 struct drm_amdgpu_info request = {
294 .return_pointer = (uintptr_t)&accel_working,
295 .return_size = sizeof(accel_working),
296 .query = AMDGPU_INFO_ACCEL_WORKING
297 };
298
299 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
300 close(master_fd);
301 master_fd = -1;
302 }
303 }
304 }
305
306 device->master_fd = master_fd;
307 device->local_fd = fd;
308 device->ws->query_info(device->ws, &device->rad_info);
309
310 radv_handle_env_var_force_family(device);
311
312 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
313
314 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
315 device->ws->destroy(device->ws);
316 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
317 "cannot generate UUID");
318 goto fail;
319 }
320
321 /* These flags affect shader compilation. */
322 uint64_t shader_env_flags =
323 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
324 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
325
326 /* The gpu id is already embedded in the uuid so we just pass "radv"
327 * when creating the cache.
328 */
329 char buf[VK_UUID_SIZE * 2 + 1];
330 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
331 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
332
333 if (device->rad_info.chip_class < GFX8 ||
334 device->rad_info.chip_class > GFX9)
335 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
336
337 radv_get_driver_uuid(&device->driver_uuid);
338 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
339
340 if (device->rad_info.family == CHIP_STONEY ||
341 device->rad_info.chip_class >= GFX9) {
342 device->has_rbplus = true;
343 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
344 device->rad_info.family == CHIP_VEGA12 ||
345 device->rad_info.family == CHIP_RAVEN ||
346 device->rad_info.family == CHIP_RAVEN2;
347 }
348
349 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
350 * on GFX6.
351 */
352 device->has_clear_state = device->rad_info.chip_class >= GFX7;
353
354 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
355
356 /* Vega10/Raven need a special workaround for a hardware bug. */
357 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
358 device->rad_info.family == CHIP_RAVEN;
359
360 /* Out-of-order primitive rasterization. */
361 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
362 device->rad_info.max_se >= 2;
363 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
364 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
365
366 device->dcc_msaa_allowed =
367 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
368
369 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
370 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
371 (device->rad_info.chip_class >= GFX8 &&
372 device->rad_info.me_fw_feature >= 41);
373
374 radv_physical_device_init_mem_types(device);
375 radv_fill_device_extension_table(device, &device->supported_extensions);
376
377 device->bus_info = *drm_device->businfo.pci;
378
379 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
380 ac_print_gpu_info(&device->rad_info);
381
382 /* The WSI is structured as a layer on top of the driver, so this has
383 * to be the last part of initialization (at least until we get other
384 * semi-layers).
385 */
386 result = radv_init_wsi(device);
387 if (result != VK_SUCCESS) {
388 device->ws->destroy(device->ws);
389 vk_error(instance, result);
390 goto fail;
391 }
392
393 return VK_SUCCESS;
394
395 fail:
396 close(fd);
397 if (master_fd != -1)
398 close(master_fd);
399 return result;
400 }
401
402 static void
403 radv_physical_device_finish(struct radv_physical_device *device)
404 {
405 radv_finish_wsi(device);
406 device->ws->destroy(device->ws);
407 disk_cache_destroy(device->disk_cache);
408 close(device->local_fd);
409 if (device->master_fd != -1)
410 close(device->master_fd);
411 }
412
413 static void *
414 default_alloc_func(void *pUserData, size_t size, size_t align,
415 VkSystemAllocationScope allocationScope)
416 {
417 return malloc(size);
418 }
419
420 static void *
421 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
422 size_t align, VkSystemAllocationScope allocationScope)
423 {
424 return realloc(pOriginal, size);
425 }
426
427 static void
428 default_free_func(void *pUserData, void *pMemory)
429 {
430 free(pMemory);
431 }
432
433 static const VkAllocationCallbacks default_alloc = {
434 .pUserData = NULL,
435 .pfnAllocation = default_alloc_func,
436 .pfnReallocation = default_realloc_func,
437 .pfnFree = default_free_func,
438 };
439
440 static const struct debug_control radv_debug_options[] = {
441 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
442 {"nodcc", RADV_DEBUG_NO_DCC},
443 {"shaders", RADV_DEBUG_DUMP_SHADERS},
444 {"nocache", RADV_DEBUG_NO_CACHE},
445 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
446 {"nohiz", RADV_DEBUG_NO_HIZ},
447 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
448 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
449 {"allbos", RADV_DEBUG_ALL_BOS},
450 {"noibs", RADV_DEBUG_NO_IBS},
451 {"spirv", RADV_DEBUG_DUMP_SPIRV},
452 {"vmfaults", RADV_DEBUG_VM_FAULTS},
453 {"zerovram", RADV_DEBUG_ZERO_VRAM},
454 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
455 {"nosisched", RADV_DEBUG_NO_SISCHED},
456 {"preoptir", RADV_DEBUG_PREOPTIR},
457 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
458 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
459 {"info", RADV_DEBUG_INFO},
460 {"errors", RADV_DEBUG_ERRORS},
461 {"startup", RADV_DEBUG_STARTUP},
462 {"checkir", RADV_DEBUG_CHECKIR},
463 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
464 {"nobinning", RADV_DEBUG_NOBINNING},
465 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
466 {NULL, 0}
467 };
468
469 const char *
470 radv_get_debug_option_name(int id)
471 {
472 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
473 return radv_debug_options[id].string;
474 }
475
476 static const struct debug_control radv_perftest_options[] = {
477 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
478 {"sisched", RADV_PERFTEST_SISCHED},
479 {"localbos", RADV_PERFTEST_LOCAL_BOS},
480 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
481 {"bolist", RADV_PERFTEST_BO_LIST},
482 {NULL, 0}
483 };
484
485 const char *
486 radv_get_perftest_option_name(int id)
487 {
488 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
489 return radv_perftest_options[id].string;
490 }
491
492 static void
493 radv_handle_per_app_options(struct radv_instance *instance,
494 const VkApplicationInfo *info)
495 {
496 const char *name = info ? info->pApplicationName : NULL;
497
498 if (!name)
499 return;
500
501 if (!strcmp(name, "Talos - Linux - 32bit") ||
502 !strcmp(name, "Talos - Linux - 64bit")) {
503 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
504 /* Force enable LLVM sisched for Talos because it looks
505 * safe and it gives few more FPS.
506 */
507 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
508 }
509 } else if (!strcmp(name, "DOOM_VFR")) {
510 /* Work around a Doom VFR game bug */
511 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
512 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
513 /* Workaround for a WaW hazard when LLVM moves/merges
514 * load/store memory operations.
515 * See https://reviews.llvm.org/D61313
516 */
517 if (HAVE_LLVM < 0x900)
518 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
519 }
520 }
521
522 static int radv_get_instance_extension_index(const char *name)
523 {
524 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
525 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
526 return i;
527 }
528 return -1;
529 }
530
531 static const char radv_dri_options_xml[] =
532 DRI_CONF_BEGIN
533 DRI_CONF_SECTION_QUALITY
534 DRI_CONF_ADAPTIVE_SYNC("true")
535 DRI_CONF_SECTION_END
536 DRI_CONF_END;
537
538 static void radv_init_dri_options(struct radv_instance *instance)
539 {
540 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
541 driParseConfigFiles(&instance->dri_options,
542 &instance->available_dri_options,
543 0, "radv", NULL);
544 }
545
546 VkResult radv_CreateInstance(
547 const VkInstanceCreateInfo* pCreateInfo,
548 const VkAllocationCallbacks* pAllocator,
549 VkInstance* pInstance)
550 {
551 struct radv_instance *instance;
552 VkResult result;
553
554 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
555
556 uint32_t client_version;
557 if (pCreateInfo->pApplicationInfo &&
558 pCreateInfo->pApplicationInfo->apiVersion != 0) {
559 client_version = pCreateInfo->pApplicationInfo->apiVersion;
560 } else {
561 client_version = VK_API_VERSION_1_0;
562 }
563
564 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
565 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
566 if (!instance)
567 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
568
569 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
570
571 if (pAllocator)
572 instance->alloc = *pAllocator;
573 else
574 instance->alloc = default_alloc;
575
576 instance->apiVersion = client_version;
577 instance->physicalDeviceCount = -1;
578
579 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
580 radv_debug_options);
581
582 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
583 radv_perftest_options);
584
585
586 if (instance->debug_flags & RADV_DEBUG_STARTUP)
587 radv_logi("Created an instance");
588
589 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
590 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
591 int index = radv_get_instance_extension_index(ext_name);
592
593 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
594 vk_free2(&default_alloc, pAllocator, instance);
595 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
596 }
597
598 instance->enabled_extensions.extensions[index] = true;
599 }
600
601 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
602 if (result != VK_SUCCESS) {
603 vk_free2(&default_alloc, pAllocator, instance);
604 return vk_error(instance, result);
605 }
606
607 _mesa_locale_init();
608 glsl_type_singleton_init_or_ref();
609
610 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
611
612 radv_init_dri_options(instance);
613 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
614
615 *pInstance = radv_instance_to_handle(instance);
616
617 return VK_SUCCESS;
618 }
619
620 void radv_DestroyInstance(
621 VkInstance _instance,
622 const VkAllocationCallbacks* pAllocator)
623 {
624 RADV_FROM_HANDLE(radv_instance, instance, _instance);
625
626 if (!instance)
627 return;
628
629 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
630 radv_physical_device_finish(instance->physicalDevices + i);
631 }
632
633 VG(VALGRIND_DESTROY_MEMPOOL(instance));
634
635 glsl_type_singleton_decref();
636 _mesa_locale_fini();
637
638 driDestroyOptionCache(&instance->dri_options);
639 driDestroyOptionInfo(&instance->available_dri_options);
640
641 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
642
643 vk_free(&instance->alloc, instance);
644 }
645
646 static VkResult
647 radv_enumerate_devices(struct radv_instance *instance)
648 {
649 /* TODO: Check for more devices ? */
650 drmDevicePtr devices[8];
651 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
652 int max_devices;
653
654 instance->physicalDeviceCount = 0;
655
656 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
657
658 if (instance->debug_flags & RADV_DEBUG_STARTUP)
659 radv_logi("Found %d drm nodes", max_devices);
660
661 if (max_devices < 1)
662 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
663
664 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
665 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
666 devices[i]->bustype == DRM_BUS_PCI &&
667 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
668
669 result = radv_physical_device_init(instance->physicalDevices +
670 instance->physicalDeviceCount,
671 instance,
672 devices[i]);
673 if (result == VK_SUCCESS)
674 ++instance->physicalDeviceCount;
675 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
676 break;
677 }
678 }
679 drmFreeDevices(devices, max_devices);
680
681 return result;
682 }
683
684 VkResult radv_EnumeratePhysicalDevices(
685 VkInstance _instance,
686 uint32_t* pPhysicalDeviceCount,
687 VkPhysicalDevice* pPhysicalDevices)
688 {
689 RADV_FROM_HANDLE(radv_instance, instance, _instance);
690 VkResult result;
691
692 if (instance->physicalDeviceCount < 0) {
693 result = radv_enumerate_devices(instance);
694 if (result != VK_SUCCESS &&
695 result != VK_ERROR_INCOMPATIBLE_DRIVER)
696 return result;
697 }
698
699 if (!pPhysicalDevices) {
700 *pPhysicalDeviceCount = instance->physicalDeviceCount;
701 } else {
702 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
703 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
704 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
705 }
706
707 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
708 : VK_SUCCESS;
709 }
710
711 VkResult radv_EnumeratePhysicalDeviceGroups(
712 VkInstance _instance,
713 uint32_t* pPhysicalDeviceGroupCount,
714 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
715 {
716 RADV_FROM_HANDLE(radv_instance, instance, _instance);
717 VkResult result;
718
719 if (instance->physicalDeviceCount < 0) {
720 result = radv_enumerate_devices(instance);
721 if (result != VK_SUCCESS &&
722 result != VK_ERROR_INCOMPATIBLE_DRIVER)
723 return result;
724 }
725
726 if (!pPhysicalDeviceGroupProperties) {
727 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
728 } else {
729 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
730 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
731 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
732 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
733 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
734 }
735 }
736 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
737 : VK_SUCCESS;
738 }
739
740 void radv_GetPhysicalDeviceFeatures(
741 VkPhysicalDevice physicalDevice,
742 VkPhysicalDeviceFeatures* pFeatures)
743 {
744 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
745 memset(pFeatures, 0, sizeof(*pFeatures));
746
747 *pFeatures = (VkPhysicalDeviceFeatures) {
748 .robustBufferAccess = true,
749 .fullDrawIndexUint32 = true,
750 .imageCubeArray = true,
751 .independentBlend = true,
752 .geometryShader = true,
753 .tessellationShader = true,
754 .sampleRateShading = true,
755 .dualSrcBlend = true,
756 .logicOp = true,
757 .multiDrawIndirect = true,
758 .drawIndirectFirstInstance = true,
759 .depthClamp = true,
760 .depthBiasClamp = true,
761 .fillModeNonSolid = true,
762 .depthBounds = true,
763 .wideLines = true,
764 .largePoints = true,
765 .alphaToOne = true,
766 .multiViewport = true,
767 .samplerAnisotropy = true,
768 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
769 .textureCompressionASTC_LDR = false,
770 .textureCompressionBC = true,
771 .occlusionQueryPrecise = true,
772 .pipelineStatisticsQuery = true,
773 .vertexPipelineStoresAndAtomics = true,
774 .fragmentStoresAndAtomics = true,
775 .shaderTessellationAndGeometryPointSize = true,
776 .shaderImageGatherExtended = true,
777 .shaderStorageImageExtendedFormats = true,
778 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
779 .shaderUniformBufferArrayDynamicIndexing = true,
780 .shaderSampledImageArrayDynamicIndexing = true,
781 .shaderStorageBufferArrayDynamicIndexing = true,
782 .shaderStorageImageArrayDynamicIndexing = true,
783 .shaderStorageImageReadWithoutFormat = true,
784 .shaderStorageImageWriteWithoutFormat = true,
785 .shaderClipDistance = true,
786 .shaderCullDistance = true,
787 .shaderFloat64 = true,
788 .shaderInt64 = true,
789 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
790 .sparseBinding = true,
791 .variableMultisampleRate = true,
792 .inheritedQueries = true,
793 };
794 }
795
796 void radv_GetPhysicalDeviceFeatures2(
797 VkPhysicalDevice physicalDevice,
798 VkPhysicalDeviceFeatures2 *pFeatures)
799 {
800 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
801 vk_foreach_struct(ext, pFeatures->pNext) {
802 switch (ext->sType) {
803 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
804 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
805 features->variablePointersStorageBuffer = true;
806 features->variablePointers = true;
807 break;
808 }
809 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
810 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
811 features->multiview = true;
812 features->multiviewGeometryShader = true;
813 features->multiviewTessellationShader = true;
814 break;
815 }
816 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
817 VkPhysicalDeviceShaderDrawParametersFeatures *features =
818 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
819 features->shaderDrawParameters = true;
820 break;
821 }
822 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
823 VkPhysicalDeviceProtectedMemoryFeatures *features =
824 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
825 features->protectedMemory = false;
826 break;
827 }
828 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
829 VkPhysicalDevice16BitStorageFeatures *features =
830 (VkPhysicalDevice16BitStorageFeatures*)ext;
831 bool enabled = pdevice->rad_info.chip_class >= GFX8;
832 features->storageBuffer16BitAccess = enabled;
833 features->uniformAndStorageBuffer16BitAccess = enabled;
834 features->storagePushConstant16 = enabled;
835 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
836 break;
837 }
838 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
839 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
840 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
841 features->samplerYcbcrConversion = true;
842 break;
843 }
844 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
845 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
846 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
847 features->shaderInputAttachmentArrayDynamicIndexing = true;
848 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
849 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
850 features->shaderUniformBufferArrayNonUniformIndexing = true;
851 features->shaderSampledImageArrayNonUniformIndexing = true;
852 features->shaderStorageBufferArrayNonUniformIndexing = true;
853 features->shaderStorageImageArrayNonUniformIndexing = true;
854 features->shaderInputAttachmentArrayNonUniformIndexing = true;
855 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
856 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
857 features->descriptorBindingUniformBufferUpdateAfterBind = true;
858 features->descriptorBindingSampledImageUpdateAfterBind = true;
859 features->descriptorBindingStorageImageUpdateAfterBind = true;
860 features->descriptorBindingStorageBufferUpdateAfterBind = true;
861 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
862 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
863 features->descriptorBindingUpdateUnusedWhilePending = true;
864 features->descriptorBindingPartiallyBound = true;
865 features->descriptorBindingVariableDescriptorCount = true;
866 features->runtimeDescriptorArray = true;
867 break;
868 }
869 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
870 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
871 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
872 features->conditionalRendering = true;
873 features->inheritedConditionalRendering = false;
874 break;
875 }
876 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
877 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
878 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
879 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
880 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
881 break;
882 }
883 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
884 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
885 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
886 features->transformFeedback = true;
887 features->geometryStreams = true;
888 break;
889 }
890 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
891 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
892 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
893 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
894 break;
895 }
896 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
897 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
898 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
899 features->memoryPriority = VK_TRUE;
900 break;
901 }
902 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
903 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
904 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
905 features->bufferDeviceAddress = true;
906 features->bufferDeviceAddressCaptureReplay = false;
907 features->bufferDeviceAddressMultiDevice = false;
908 break;
909 }
910 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
911 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
912 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
913 features->depthClipEnable = true;
914 break;
915 }
916 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
917 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
918 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
919 features->hostQueryReset = true;
920 break;
921 }
922 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
923 VkPhysicalDevice8BitStorageFeaturesKHR *features =
924 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
925 bool enabled = pdevice->rad_info.chip_class >= GFX8;
926 features->storageBuffer8BitAccess = enabled;
927 features->uniformAndStorageBuffer8BitAccess = enabled;
928 features->storagePushConstant8 = enabled;
929 break;
930 }
931 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
932 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
933 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
934 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
935 features->shaderInt8 = true;
936 break;
937 }
938 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
939 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
940 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
941 /* TODO: Enable this once the driver supports 64-bit
942 * compare&swap atomic operations.
943 */
944 features->shaderBufferInt64Atomics = false;
945 features->shaderSharedInt64Atomics = false;
946 break;
947 }
948 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
949 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
950 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
951
952 features->inlineUniformBlock = true;
953 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
954 break;
955 }
956 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
957 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
958 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
959 features->computeDerivativeGroupQuads = false;
960 features->computeDerivativeGroupLinear = true;
961 break;
962 }
963 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
964 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
965 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
966 features->ycbcrImageArrays = true;
967 break;
968 }
969 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
970 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
971 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
972 features->uniformBufferStandardLayout = true;
973 break;
974 }
975 default:
976 break;
977 }
978 }
979 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
980 }
981
982 void radv_GetPhysicalDeviceProperties(
983 VkPhysicalDevice physicalDevice,
984 VkPhysicalDeviceProperties* pProperties)
985 {
986 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
987 VkSampleCountFlags sample_counts = 0xf;
988
989 /* make sure that the entire descriptor set is addressable with a signed
990 * 32-bit int. So the sum of all limits scaled by descriptor size has to
991 * be at most 2 GiB. the combined image & samples object count as one of
992 * both. This limit is for the pipeline layout, not for the set layout, but
993 * there is no set limit, so we just set a pipeline limit. I don't think
994 * any app is going to hit this soon. */
995 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
996 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
997 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
998 32 /* sampler, largest when combined with image */ +
999 64 /* sampled image */ +
1000 64 /* storage image */);
1001
1002 VkPhysicalDeviceLimits limits = {
1003 .maxImageDimension1D = (1 << 14),
1004 .maxImageDimension2D = (1 << 14),
1005 .maxImageDimension3D = (1 << 11),
1006 .maxImageDimensionCube = (1 << 14),
1007 .maxImageArrayLayers = (1 << 11),
1008 .maxTexelBufferElements = 128 * 1024 * 1024,
1009 .maxUniformBufferRange = UINT32_MAX,
1010 .maxStorageBufferRange = UINT32_MAX,
1011 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1012 .maxMemoryAllocationCount = UINT32_MAX,
1013 .maxSamplerAllocationCount = 64 * 1024,
1014 .bufferImageGranularity = 64, /* A cache line */
1015 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1016 .maxBoundDescriptorSets = MAX_SETS,
1017 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1018 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1019 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1020 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1021 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1022 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1023 .maxPerStageResources = max_descriptor_set_size,
1024 .maxDescriptorSetSamplers = max_descriptor_set_size,
1025 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1026 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1027 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1028 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1029 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1030 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1031 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1032 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1033 .maxVertexInputBindings = MAX_VBS,
1034 .maxVertexInputAttributeOffset = 2047,
1035 .maxVertexInputBindingStride = 2048,
1036 .maxVertexOutputComponents = 128,
1037 .maxTessellationGenerationLevel = 64,
1038 .maxTessellationPatchSize = 32,
1039 .maxTessellationControlPerVertexInputComponents = 128,
1040 .maxTessellationControlPerVertexOutputComponents = 128,
1041 .maxTessellationControlPerPatchOutputComponents = 120,
1042 .maxTessellationControlTotalOutputComponents = 4096,
1043 .maxTessellationEvaluationInputComponents = 128,
1044 .maxTessellationEvaluationOutputComponents = 128,
1045 .maxGeometryShaderInvocations = 127,
1046 .maxGeometryInputComponents = 64,
1047 .maxGeometryOutputComponents = 128,
1048 .maxGeometryOutputVertices = 256,
1049 .maxGeometryTotalOutputComponents = 1024,
1050 .maxFragmentInputComponents = 128,
1051 .maxFragmentOutputAttachments = 8,
1052 .maxFragmentDualSrcAttachments = 1,
1053 .maxFragmentCombinedOutputResources = 8,
1054 .maxComputeSharedMemorySize = 32768,
1055 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1056 .maxComputeWorkGroupInvocations = 2048,
1057 .maxComputeWorkGroupSize = {
1058 2048,
1059 2048,
1060 2048
1061 },
1062 .subPixelPrecisionBits = 8,
1063 .subTexelPrecisionBits = 8,
1064 .mipmapPrecisionBits = 8,
1065 .maxDrawIndexedIndexValue = UINT32_MAX,
1066 .maxDrawIndirectCount = UINT32_MAX,
1067 .maxSamplerLodBias = 16,
1068 .maxSamplerAnisotropy = 16,
1069 .maxViewports = MAX_VIEWPORTS,
1070 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1071 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1072 .viewportSubPixelBits = 8,
1073 .minMemoryMapAlignment = 4096, /* A page */
1074 .minTexelBufferOffsetAlignment = 1,
1075 .minUniformBufferOffsetAlignment = 4,
1076 .minStorageBufferOffsetAlignment = 4,
1077 .minTexelOffset = -32,
1078 .maxTexelOffset = 31,
1079 .minTexelGatherOffset = -32,
1080 .maxTexelGatherOffset = 31,
1081 .minInterpolationOffset = -2,
1082 .maxInterpolationOffset = 2,
1083 .subPixelInterpolationOffsetBits = 8,
1084 .maxFramebufferWidth = (1 << 14),
1085 .maxFramebufferHeight = (1 << 14),
1086 .maxFramebufferLayers = (1 << 10),
1087 .framebufferColorSampleCounts = sample_counts,
1088 .framebufferDepthSampleCounts = sample_counts,
1089 .framebufferStencilSampleCounts = sample_counts,
1090 .framebufferNoAttachmentsSampleCounts = sample_counts,
1091 .maxColorAttachments = MAX_RTS,
1092 .sampledImageColorSampleCounts = sample_counts,
1093 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1094 .sampledImageDepthSampleCounts = sample_counts,
1095 .sampledImageStencilSampleCounts = sample_counts,
1096 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1097 .maxSampleMaskWords = 1,
1098 .timestampComputeAndGraphics = true,
1099 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1100 .maxClipDistances = 8,
1101 .maxCullDistances = 8,
1102 .maxCombinedClipAndCullDistances = 8,
1103 .discreteQueuePriorities = 2,
1104 .pointSizeRange = { 0.0, 8192.0 },
1105 .lineWidthRange = { 0.0, 7.9921875 },
1106 .pointSizeGranularity = (1.0 / 8.0),
1107 .lineWidthGranularity = (1.0 / 128.0),
1108 .strictLines = false, /* FINISHME */
1109 .standardSampleLocations = true,
1110 .optimalBufferCopyOffsetAlignment = 128,
1111 .optimalBufferCopyRowPitchAlignment = 128,
1112 .nonCoherentAtomSize = 64,
1113 };
1114
1115 *pProperties = (VkPhysicalDeviceProperties) {
1116 .apiVersion = radv_physical_device_api_version(pdevice),
1117 .driverVersion = vk_get_driver_version(),
1118 .vendorID = ATI_VENDOR_ID,
1119 .deviceID = pdevice->rad_info.pci_id,
1120 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1121 .limits = limits,
1122 .sparseProperties = {0},
1123 };
1124
1125 strcpy(pProperties->deviceName, pdevice->name);
1126 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1127 }
1128
1129 void radv_GetPhysicalDeviceProperties2(
1130 VkPhysicalDevice physicalDevice,
1131 VkPhysicalDeviceProperties2 *pProperties)
1132 {
1133 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1134 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1135
1136 vk_foreach_struct(ext, pProperties->pNext) {
1137 switch (ext->sType) {
1138 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1139 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1140 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1141 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1142 break;
1143 }
1144 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1145 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1146 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1147 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1148 properties->deviceLUIDValid = false;
1149 break;
1150 }
1151 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1152 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1153 properties->maxMultiviewViewCount = MAX_VIEWS;
1154 properties->maxMultiviewInstanceIndex = INT_MAX;
1155 break;
1156 }
1157 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1158 VkPhysicalDevicePointClippingProperties *properties =
1159 (VkPhysicalDevicePointClippingProperties*)ext;
1160 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1161 break;
1162 }
1163 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1164 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1165 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1166 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1167 break;
1168 }
1169 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1170 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1171 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1172 properties->minImportedHostPointerAlignment = 4096;
1173 break;
1174 }
1175 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1176 VkPhysicalDeviceSubgroupProperties *properties =
1177 (VkPhysicalDeviceSubgroupProperties*)ext;
1178 properties->subgroupSize = 64;
1179 properties->supportedStages = VK_SHADER_STAGE_ALL;
1180 properties->supportedOperations =
1181 VK_SUBGROUP_FEATURE_BASIC_BIT |
1182 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1183 VK_SUBGROUP_FEATURE_QUAD_BIT |
1184 VK_SUBGROUP_FEATURE_VOTE_BIT;
1185 if (pdevice->rad_info.chip_class >= GFX8) {
1186 properties->supportedOperations |=
1187 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1188 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1189 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1190 }
1191 properties->quadOperationsInAllStages = true;
1192 break;
1193 }
1194 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1195 VkPhysicalDeviceMaintenance3Properties *properties =
1196 (VkPhysicalDeviceMaintenance3Properties*)ext;
1197 /* Make sure everything is addressable by a signed 32-bit int, and
1198 * our largest descriptors are 96 bytes. */
1199 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1200 /* Our buffer size fields allow only this much */
1201 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1202 break;
1203 }
1204 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1205 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1206 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1207 /* GFX6-8 only support single channel min/max filter. */
1208 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1209 properties->filterMinmaxSingleComponentFormats = true;
1210 break;
1211 }
1212 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1213 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1214 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1215
1216 /* Shader engines. */
1217 properties->shaderEngineCount =
1218 pdevice->rad_info.max_se;
1219 properties->shaderArraysPerEngineCount =
1220 pdevice->rad_info.max_sh_per_se;
1221 properties->computeUnitsPerShaderArray =
1222 pdevice->rad_info.num_good_cu_per_sh;
1223 properties->simdPerComputeUnit = 4;
1224 properties->wavefrontsPerSimd =
1225 pdevice->rad_info.family == CHIP_TONGA ||
1226 pdevice->rad_info.family == CHIP_ICELAND ||
1227 pdevice->rad_info.family == CHIP_POLARIS10 ||
1228 pdevice->rad_info.family == CHIP_POLARIS11 ||
1229 pdevice->rad_info.family == CHIP_POLARIS12 ||
1230 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1231 properties->wavefrontSize = 64;
1232
1233 /* SGPR. */
1234 properties->sgprsPerSimd =
1235 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1236 properties->minSgprAllocation =
1237 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1238 properties->maxSgprAllocation =
1239 pdevice->rad_info.family == CHIP_TONGA ||
1240 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1241 properties->sgprAllocationGranularity =
1242 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1243
1244 /* VGPR. */
1245 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1246 properties->minVgprAllocation = 4;
1247 properties->maxVgprAllocation = 256;
1248 properties->vgprAllocationGranularity = 4;
1249 break;
1250 }
1251 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1252 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1253 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1254 properties->maxVertexAttribDivisor = UINT32_MAX;
1255 break;
1256 }
1257 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1258 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1259 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1260 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1261 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1262 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1263 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1264 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1265 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1266 properties->robustBufferAccessUpdateAfterBind = false;
1267 properties->quadDivergentImplicitLod = false;
1268
1269 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1270 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1271 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1272 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1273 32 /* sampler, largest when combined with image */ +
1274 64 /* sampled image */ +
1275 64 /* storage image */);
1276 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1277 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1278 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1279 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1280 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1281 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1282 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1283 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1284 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1285 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1286 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1287 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1288 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1289 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1290 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1291 break;
1292 }
1293 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1294 VkPhysicalDeviceProtectedMemoryProperties *properties =
1295 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1296 properties->protectedNoFault = false;
1297 break;
1298 }
1299 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1300 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1301 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1302 properties->primitiveOverestimationSize = 0;
1303 properties->maxExtraPrimitiveOverestimationSize = 0;
1304 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1305 properties->primitiveUnderestimation = VK_FALSE;
1306 properties->conservativePointAndLineRasterization = VK_FALSE;
1307 properties->degenerateTrianglesRasterized = VK_FALSE;
1308 properties->degenerateLinesRasterized = VK_FALSE;
1309 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1310 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1311 break;
1312 }
1313 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1314 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1315 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1316 properties->pciDomain = pdevice->bus_info.domain;
1317 properties->pciBus = pdevice->bus_info.bus;
1318 properties->pciDevice = pdevice->bus_info.dev;
1319 properties->pciFunction = pdevice->bus_info.func;
1320 break;
1321 }
1322 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1323 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1324 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1325
1326 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1327 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1328 strcpy(driver_props->driverName, "radv");
1329
1330 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1331 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1332 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1333 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1334
1335 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1336 .major = 1,
1337 .minor = 1,
1338 .subminor = 2,
1339 .patch = 0,
1340 };
1341 break;
1342 }
1343 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1344 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1345 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1346 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1347 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1348 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1349 properties->maxTransformFeedbackStreamDataSize = 512;
1350 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1351 properties->maxTransformFeedbackBufferDataStride = 512;
1352 properties->transformFeedbackQueries = true;
1353 properties->transformFeedbackStreamsLinesTriangles = true;
1354 properties->transformFeedbackRasterizationStreamSelect = false;
1355 properties->transformFeedbackDraw = true;
1356 break;
1357 }
1358 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1359 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1360 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1361
1362 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1363 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1364 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1365 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1366 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1367 break;
1368 }
1369 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1370 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1371 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1372 /* TODO: The ext is currently disabled because the
1373 * driver needs to handle sample locations during
1374 * layout transitions for depth/stencil surfaces and
1375 * HTILE.
1376 */
1377 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_1_BIT;
1378 /*
1379 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1380 VK_SAMPLE_COUNT_4_BIT |
1381 VK_SAMPLE_COUNT_8_BIT;
1382 */
1383 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1384 properties->sampleLocationCoordinateRange[0] = 0.0f;
1385 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1386 properties->sampleLocationSubPixelBits = 4;
1387 properties->variableSampleLocations = VK_FALSE;
1388 break;
1389 }
1390 default:
1391 break;
1392 }
1393 }
1394 }
1395
1396 static void radv_get_physical_device_queue_family_properties(
1397 struct radv_physical_device* pdevice,
1398 uint32_t* pCount,
1399 VkQueueFamilyProperties** pQueueFamilyProperties)
1400 {
1401 int num_queue_families = 1;
1402 int idx;
1403 if (pdevice->rad_info.num_compute_rings > 0 &&
1404 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1405 num_queue_families++;
1406
1407 if (pQueueFamilyProperties == NULL) {
1408 *pCount = num_queue_families;
1409 return;
1410 }
1411
1412 if (!*pCount)
1413 return;
1414
1415 idx = 0;
1416 if (*pCount >= 1) {
1417 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1418 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1419 VK_QUEUE_COMPUTE_BIT |
1420 VK_QUEUE_TRANSFER_BIT |
1421 VK_QUEUE_SPARSE_BINDING_BIT,
1422 .queueCount = 1,
1423 .timestampValidBits = 64,
1424 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1425 };
1426 idx++;
1427 }
1428
1429 if (pdevice->rad_info.num_compute_rings > 0 &&
1430 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1431 if (*pCount > idx) {
1432 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1433 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1434 VK_QUEUE_TRANSFER_BIT |
1435 VK_QUEUE_SPARSE_BINDING_BIT,
1436 .queueCount = pdevice->rad_info.num_compute_rings,
1437 .timestampValidBits = 64,
1438 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1439 };
1440 idx++;
1441 }
1442 }
1443 *pCount = idx;
1444 }
1445
1446 void radv_GetPhysicalDeviceQueueFamilyProperties(
1447 VkPhysicalDevice physicalDevice,
1448 uint32_t* pCount,
1449 VkQueueFamilyProperties* pQueueFamilyProperties)
1450 {
1451 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1452 if (!pQueueFamilyProperties) {
1453 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1454 return;
1455 }
1456 VkQueueFamilyProperties *properties[] = {
1457 pQueueFamilyProperties + 0,
1458 pQueueFamilyProperties + 1,
1459 pQueueFamilyProperties + 2,
1460 };
1461 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1462 assert(*pCount <= 3);
1463 }
1464
1465 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1466 VkPhysicalDevice physicalDevice,
1467 uint32_t* pCount,
1468 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1469 {
1470 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1471 if (!pQueueFamilyProperties) {
1472 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1473 return;
1474 }
1475 VkQueueFamilyProperties *properties[] = {
1476 &pQueueFamilyProperties[0].queueFamilyProperties,
1477 &pQueueFamilyProperties[1].queueFamilyProperties,
1478 &pQueueFamilyProperties[2].queueFamilyProperties,
1479 };
1480 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1481 assert(*pCount <= 3);
1482 }
1483
1484 void radv_GetPhysicalDeviceMemoryProperties(
1485 VkPhysicalDevice physicalDevice,
1486 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1487 {
1488 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1489
1490 *pMemoryProperties = physical_device->memory_properties;
1491 }
1492
1493 static void
1494 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1495 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1496 {
1497 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1498 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1499 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1500 uint64_t vram_size = radv_get_vram_size(device);
1501 uint64_t gtt_size = device->rad_info.gart_size;
1502 uint64_t heap_budget, heap_usage;
1503
1504 /* For all memory heaps, the computation of budget is as follow:
1505 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1506 *
1507 * The Vulkan spec 1.1.97 says that the budget should include any
1508 * currently allocated device memory.
1509 *
1510 * Note that the application heap usages are not really accurate (eg.
1511 * in presence of shared buffers).
1512 */
1513 if (vram_size) {
1514 heap_usage = device->ws->query_value(device->ws,
1515 RADEON_ALLOCATED_VRAM);
1516
1517 heap_budget = vram_size -
1518 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1519 heap_usage;
1520
1521 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
1522 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
1523 }
1524
1525 if (visible_vram_size) {
1526 heap_usage = device->ws->query_value(device->ws,
1527 RADEON_ALLOCATED_VRAM_VIS);
1528
1529 heap_budget = visible_vram_size -
1530 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1531 heap_usage;
1532
1533 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
1534 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
1535 }
1536
1537 if (gtt_size) {
1538 heap_usage = device->ws->query_value(device->ws,
1539 RADEON_ALLOCATED_GTT);
1540
1541 heap_budget = gtt_size -
1542 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1543 heap_usage;
1544
1545 memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
1546 memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
1547 }
1548
1549 /* The heapBudget and heapUsage values must be zero for array elements
1550 * greater than or equal to
1551 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1552 */
1553 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1554 memoryBudget->heapBudget[i] = 0;
1555 memoryBudget->heapUsage[i] = 0;
1556 }
1557 }
1558
1559 void radv_GetPhysicalDeviceMemoryProperties2(
1560 VkPhysicalDevice physicalDevice,
1561 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1562 {
1563 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1564 &pMemoryProperties->memoryProperties);
1565
1566 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1567 vk_find_struct(pMemoryProperties->pNext,
1568 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1569 if (memory_budget)
1570 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1571 }
1572
1573 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1574 VkDevice _device,
1575 VkExternalMemoryHandleTypeFlagBits handleType,
1576 const void *pHostPointer,
1577 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1578 {
1579 RADV_FROM_HANDLE(radv_device, device, _device);
1580
1581 switch (handleType)
1582 {
1583 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1584 const struct radv_physical_device *physical_device = device->physical_device;
1585 uint32_t memoryTypeBits = 0;
1586 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1587 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1588 memoryTypeBits = (1 << i);
1589 break;
1590 }
1591 }
1592 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1593 return VK_SUCCESS;
1594 }
1595 default:
1596 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1597 }
1598 }
1599
1600 static enum radeon_ctx_priority
1601 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1602 {
1603 /* Default to MEDIUM when a specific global priority isn't requested */
1604 if (!pObj)
1605 return RADEON_CTX_PRIORITY_MEDIUM;
1606
1607 switch(pObj->globalPriority) {
1608 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1609 return RADEON_CTX_PRIORITY_REALTIME;
1610 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1611 return RADEON_CTX_PRIORITY_HIGH;
1612 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1613 return RADEON_CTX_PRIORITY_MEDIUM;
1614 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1615 return RADEON_CTX_PRIORITY_LOW;
1616 default:
1617 unreachable("Illegal global priority value");
1618 return RADEON_CTX_PRIORITY_INVALID;
1619 }
1620 }
1621
1622 static int
1623 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1624 uint32_t queue_family_index, int idx,
1625 VkDeviceQueueCreateFlags flags,
1626 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1627 {
1628 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1629 queue->device = device;
1630 queue->queue_family_index = queue_family_index;
1631 queue->queue_idx = idx;
1632 queue->priority = radv_get_queue_global_priority(global_priority);
1633 queue->flags = flags;
1634
1635 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1636 if (!queue->hw_ctx)
1637 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1638
1639 return VK_SUCCESS;
1640 }
1641
1642 static void
1643 radv_queue_finish(struct radv_queue *queue)
1644 {
1645 if (queue->hw_ctx)
1646 queue->device->ws->ctx_destroy(queue->hw_ctx);
1647
1648 if (queue->initial_full_flush_preamble_cs)
1649 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1650 if (queue->initial_preamble_cs)
1651 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1652 if (queue->continue_preamble_cs)
1653 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1654 if (queue->descriptor_bo)
1655 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1656 if (queue->scratch_bo)
1657 queue->device->ws->buffer_destroy(queue->scratch_bo);
1658 if (queue->esgs_ring_bo)
1659 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1660 if (queue->gsvs_ring_bo)
1661 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1662 if (queue->tess_rings_bo)
1663 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1664 if (queue->compute_scratch_bo)
1665 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1666 }
1667
1668 static void
1669 radv_bo_list_init(struct radv_bo_list *bo_list)
1670 {
1671 pthread_mutex_init(&bo_list->mutex, NULL);
1672 bo_list->list.count = bo_list->capacity = 0;
1673 bo_list->list.bos = NULL;
1674 }
1675
1676 static void
1677 radv_bo_list_finish(struct radv_bo_list *bo_list)
1678 {
1679 free(bo_list->list.bos);
1680 pthread_mutex_destroy(&bo_list->mutex);
1681 }
1682
1683 static VkResult radv_bo_list_add(struct radv_device *device,
1684 struct radeon_winsys_bo *bo)
1685 {
1686 struct radv_bo_list *bo_list = &device->bo_list;
1687
1688 if (bo->is_local)
1689 return VK_SUCCESS;
1690
1691 if (unlikely(!device->use_global_bo_list))
1692 return VK_SUCCESS;
1693
1694 pthread_mutex_lock(&bo_list->mutex);
1695 if (bo_list->list.count == bo_list->capacity) {
1696 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1697 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1698
1699 if (!data) {
1700 pthread_mutex_unlock(&bo_list->mutex);
1701 return VK_ERROR_OUT_OF_HOST_MEMORY;
1702 }
1703
1704 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1705 bo_list->capacity = capacity;
1706 }
1707
1708 bo_list->list.bos[bo_list->list.count++] = bo;
1709 pthread_mutex_unlock(&bo_list->mutex);
1710 return VK_SUCCESS;
1711 }
1712
1713 static void radv_bo_list_remove(struct radv_device *device,
1714 struct radeon_winsys_bo *bo)
1715 {
1716 struct radv_bo_list *bo_list = &device->bo_list;
1717
1718 if (bo->is_local)
1719 return;
1720
1721 if (unlikely(!device->use_global_bo_list))
1722 return;
1723
1724 pthread_mutex_lock(&bo_list->mutex);
1725 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1726 if (bo_list->list.bos[i] == bo) {
1727 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1728 --bo_list->list.count;
1729 break;
1730 }
1731 }
1732 pthread_mutex_unlock(&bo_list->mutex);
1733 }
1734
1735 static void
1736 radv_device_init_gs_info(struct radv_device *device)
1737 {
1738 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1739 device->physical_device->rad_info.family);
1740 }
1741
1742 static int radv_get_device_extension_index(const char *name)
1743 {
1744 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1745 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1746 return i;
1747 }
1748 return -1;
1749 }
1750
1751 static int
1752 radv_get_int_debug_option(const char *name, int default_value)
1753 {
1754 const char *str;
1755 int result;
1756
1757 str = getenv(name);
1758 if (!str) {
1759 result = default_value;
1760 } else {
1761 char *endptr;
1762
1763 result = strtol(str, &endptr, 0);
1764 if (str == endptr) {
1765 /* No digits founs. */
1766 result = default_value;
1767 }
1768 }
1769
1770 return result;
1771 }
1772
1773 VkResult radv_CreateDevice(
1774 VkPhysicalDevice physicalDevice,
1775 const VkDeviceCreateInfo* pCreateInfo,
1776 const VkAllocationCallbacks* pAllocator,
1777 VkDevice* pDevice)
1778 {
1779 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1780 VkResult result;
1781 struct radv_device *device;
1782
1783 bool keep_shader_info = false;
1784
1785 /* Check enabled features */
1786 if (pCreateInfo->pEnabledFeatures) {
1787 VkPhysicalDeviceFeatures supported_features;
1788 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1789 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1790 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1791 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1792 for (uint32_t i = 0; i < num_features; i++) {
1793 if (enabled_feature[i] && !supported_feature[i])
1794 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1795 }
1796 }
1797
1798 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1799 sizeof(*device), 8,
1800 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1801 if (!device)
1802 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1803
1804 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1805 device->instance = physical_device->instance;
1806 device->physical_device = physical_device;
1807
1808 device->ws = physical_device->ws;
1809 if (pAllocator)
1810 device->alloc = *pAllocator;
1811 else
1812 device->alloc = physical_device->instance->alloc;
1813
1814 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1815 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1816 int index = radv_get_device_extension_index(ext_name);
1817 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1818 vk_free(&device->alloc, device);
1819 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1820 }
1821
1822 device->enabled_extensions.extensions[index] = true;
1823 }
1824
1825 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1826
1827 /* With update after bind we can't attach bo's to the command buffer
1828 * from the descriptor set anymore, so we have to use a global BO list.
1829 */
1830 device->use_global_bo_list =
1831 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1832 device->enabled_extensions.EXT_descriptor_indexing ||
1833 device->enabled_extensions.EXT_buffer_device_address;
1834
1835 mtx_init(&device->shader_slab_mutex, mtx_plain);
1836 list_inithead(&device->shader_slabs);
1837
1838 radv_bo_list_init(&device->bo_list);
1839
1840 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1841 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1842 uint32_t qfi = queue_create->queueFamilyIndex;
1843 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1844 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1845
1846 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1847
1848 device->queues[qfi] = vk_alloc(&device->alloc,
1849 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1850 if (!device->queues[qfi]) {
1851 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1852 goto fail;
1853 }
1854
1855 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1856
1857 device->queue_count[qfi] = queue_create->queueCount;
1858
1859 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1860 result = radv_queue_init(device, &device->queues[qfi][q],
1861 qfi, q, queue_create->flags,
1862 global_priority);
1863 if (result != VK_SUCCESS)
1864 goto fail;
1865 }
1866 }
1867
1868 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1869 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1870
1871 /* Disabled and not implemented for now. */
1872 device->dfsm_allowed = device->pbb_allowed &&
1873 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1874 device->physical_device->rad_info.family == CHIP_RAVEN2);
1875
1876 #ifdef ANDROID
1877 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1878 #endif
1879
1880 /* The maximum number of scratch waves. Scratch space isn't divided
1881 * evenly between CUs. The number is only a function of the number of CUs.
1882 * We can decrease the constant to decrease the scratch buffer size.
1883 *
1884 * sctx->scratch_waves must be >= the maximum possible size of
1885 * 1 threadgroup, so that the hw doesn't hang from being unable
1886 * to start any.
1887 *
1888 * The recommended value is 4 per CU at most. Higher numbers don't
1889 * bring much benefit, but they still occupy chip resources (think
1890 * async compute). I've seen ~2% performance difference between 4 and 32.
1891 */
1892 uint32_t max_threads_per_block = 2048;
1893 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1894 max_threads_per_block / 64);
1895
1896 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1897
1898 if (device->physical_device->rad_info.chip_class >= GFX7) {
1899 /* If the KMD allows it (there is a KMD hw register for it),
1900 * allow launching waves out-of-order.
1901 */
1902 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1903 }
1904
1905 radv_device_init_gs_info(device);
1906
1907 device->tess_offchip_block_dw_size =
1908 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1909 device->has_distributed_tess =
1910 device->physical_device->rad_info.chip_class >= GFX8 &&
1911 device->physical_device->rad_info.max_se >= 2;
1912
1913 if (getenv("RADV_TRACE_FILE")) {
1914 const char *filename = getenv("RADV_TRACE_FILE");
1915
1916 keep_shader_info = true;
1917
1918 if (!radv_init_trace(device))
1919 goto fail;
1920
1921 fprintf(stderr, "*****************************************************************************\n");
1922 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1923 fprintf(stderr, "*****************************************************************************\n");
1924
1925 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1926 radv_dump_enabled_options(device, stderr);
1927 }
1928
1929 device->keep_shader_info = keep_shader_info;
1930
1931 result = radv_device_init_meta(device);
1932 if (result != VK_SUCCESS)
1933 goto fail;
1934
1935 radv_device_init_msaa(device);
1936
1937 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1938 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1939 switch (family) {
1940 case RADV_QUEUE_GENERAL:
1941 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1942 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1943 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1944 break;
1945 case RADV_QUEUE_COMPUTE:
1946 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1947 radeon_emit(device->empty_cs[family], 0);
1948 break;
1949 }
1950 device->ws->cs_finalize(device->empty_cs[family]);
1951 }
1952
1953 if (device->physical_device->rad_info.chip_class >= GFX7)
1954 cik_create_gfx_config(device);
1955
1956 VkPipelineCacheCreateInfo ci;
1957 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1958 ci.pNext = NULL;
1959 ci.flags = 0;
1960 ci.pInitialData = NULL;
1961 ci.initialDataSize = 0;
1962 VkPipelineCache pc;
1963 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1964 &ci, NULL, &pc);
1965 if (result != VK_SUCCESS)
1966 goto fail_meta;
1967
1968 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1969
1970 device->force_aniso =
1971 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1972 if (device->force_aniso >= 0) {
1973 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1974 1 << util_logbase2(device->force_aniso));
1975 }
1976
1977 *pDevice = radv_device_to_handle(device);
1978 return VK_SUCCESS;
1979
1980 fail_meta:
1981 radv_device_finish_meta(device);
1982 fail:
1983 radv_bo_list_finish(&device->bo_list);
1984
1985 if (device->trace_bo)
1986 device->ws->buffer_destroy(device->trace_bo);
1987
1988 if (device->gfx_init)
1989 device->ws->buffer_destroy(device->gfx_init);
1990
1991 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1992 for (unsigned q = 0; q < device->queue_count[i]; q++)
1993 radv_queue_finish(&device->queues[i][q]);
1994 if (device->queue_count[i])
1995 vk_free(&device->alloc, device->queues[i]);
1996 }
1997
1998 vk_free(&device->alloc, device);
1999 return result;
2000 }
2001
2002 void radv_DestroyDevice(
2003 VkDevice _device,
2004 const VkAllocationCallbacks* pAllocator)
2005 {
2006 RADV_FROM_HANDLE(radv_device, device, _device);
2007
2008 if (!device)
2009 return;
2010
2011 if (device->trace_bo)
2012 device->ws->buffer_destroy(device->trace_bo);
2013
2014 if (device->gfx_init)
2015 device->ws->buffer_destroy(device->gfx_init);
2016
2017 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2018 for (unsigned q = 0; q < device->queue_count[i]; q++)
2019 radv_queue_finish(&device->queues[i][q]);
2020 if (device->queue_count[i])
2021 vk_free(&device->alloc, device->queues[i]);
2022 if (device->empty_cs[i])
2023 device->ws->cs_destroy(device->empty_cs[i]);
2024 }
2025 radv_device_finish_meta(device);
2026
2027 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2028 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2029
2030 radv_destroy_shader_slabs(device);
2031
2032 radv_bo_list_finish(&device->bo_list);
2033 vk_free(&device->alloc, device);
2034 }
2035
2036 VkResult radv_EnumerateInstanceLayerProperties(
2037 uint32_t* pPropertyCount,
2038 VkLayerProperties* pProperties)
2039 {
2040 if (pProperties == NULL) {
2041 *pPropertyCount = 0;
2042 return VK_SUCCESS;
2043 }
2044
2045 /* None supported at this time */
2046 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2047 }
2048
2049 VkResult radv_EnumerateDeviceLayerProperties(
2050 VkPhysicalDevice physicalDevice,
2051 uint32_t* pPropertyCount,
2052 VkLayerProperties* pProperties)
2053 {
2054 if (pProperties == NULL) {
2055 *pPropertyCount = 0;
2056 return VK_SUCCESS;
2057 }
2058
2059 /* None supported at this time */
2060 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2061 }
2062
2063 void radv_GetDeviceQueue2(
2064 VkDevice _device,
2065 const VkDeviceQueueInfo2* pQueueInfo,
2066 VkQueue* pQueue)
2067 {
2068 RADV_FROM_HANDLE(radv_device, device, _device);
2069 struct radv_queue *queue;
2070
2071 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2072 if (pQueueInfo->flags != queue->flags) {
2073 /* From the Vulkan 1.1.70 spec:
2074 *
2075 * "The queue returned by vkGetDeviceQueue2 must have the same
2076 * flags value from this structure as that used at device
2077 * creation time in a VkDeviceQueueCreateInfo instance. If no
2078 * matching flags were specified at device creation time then
2079 * pQueue will return VK_NULL_HANDLE."
2080 */
2081 *pQueue = VK_NULL_HANDLE;
2082 return;
2083 }
2084
2085 *pQueue = radv_queue_to_handle(queue);
2086 }
2087
2088 void radv_GetDeviceQueue(
2089 VkDevice _device,
2090 uint32_t queueFamilyIndex,
2091 uint32_t queueIndex,
2092 VkQueue* pQueue)
2093 {
2094 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2095 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2096 .queueFamilyIndex = queueFamilyIndex,
2097 .queueIndex = queueIndex
2098 };
2099
2100 radv_GetDeviceQueue2(_device, &info, pQueue);
2101 }
2102
2103 static void
2104 fill_geom_tess_rings(struct radv_queue *queue,
2105 uint32_t *map,
2106 bool add_sample_positions,
2107 uint32_t esgs_ring_size,
2108 struct radeon_winsys_bo *esgs_ring_bo,
2109 uint32_t gsvs_ring_size,
2110 struct radeon_winsys_bo *gsvs_ring_bo,
2111 uint32_t tess_factor_ring_size,
2112 uint32_t tess_offchip_ring_offset,
2113 uint32_t tess_offchip_ring_size,
2114 struct radeon_winsys_bo *tess_rings_bo)
2115 {
2116 uint32_t *desc = &map[4];
2117
2118 if (esgs_ring_bo) {
2119 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2120
2121 /* stride 0, num records - size, add tid, swizzle, elsize4,
2122 index stride 64 */
2123 desc[0] = esgs_va;
2124 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2125 S_008F04_STRIDE(0) |
2126 S_008F04_SWIZZLE_ENABLE(true);
2127 desc[2] = esgs_ring_size;
2128 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2129 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2130 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2131 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2132 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2133 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2134 S_008F0C_ELEMENT_SIZE(1) |
2135 S_008F0C_INDEX_STRIDE(3) |
2136 S_008F0C_ADD_TID_ENABLE(true);
2137
2138 /* GS entry for ES->GS ring */
2139 /* stride 0, num records - size, elsize0,
2140 index stride 0 */
2141 desc[4] = esgs_va;
2142 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2143 S_008F04_STRIDE(0) |
2144 S_008F04_SWIZZLE_ENABLE(false);
2145 desc[6] = esgs_ring_size;
2146 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2147 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2148 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2149 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2150 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2151 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2152 S_008F0C_ELEMENT_SIZE(0) |
2153 S_008F0C_INDEX_STRIDE(0) |
2154 S_008F0C_ADD_TID_ENABLE(false);
2155 }
2156
2157 desc += 8;
2158
2159 if (gsvs_ring_bo) {
2160 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2161
2162 /* VS entry for GS->VS ring */
2163 /* stride 0, num records - size, elsize0,
2164 index stride 0 */
2165 desc[0] = gsvs_va;
2166 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2167 S_008F04_STRIDE(0) |
2168 S_008F04_SWIZZLE_ENABLE(false);
2169 desc[2] = gsvs_ring_size;
2170 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2171 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2172 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2173 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2174 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2175 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2176 S_008F0C_ELEMENT_SIZE(0) |
2177 S_008F0C_INDEX_STRIDE(0) |
2178 S_008F0C_ADD_TID_ENABLE(false);
2179
2180 /* stride gsvs_itemsize, num records 64
2181 elsize 4, index stride 16 */
2182 /* shader will patch stride and desc[2] */
2183 desc[4] = gsvs_va;
2184 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2185 S_008F04_STRIDE(0) |
2186 S_008F04_SWIZZLE_ENABLE(true);
2187 desc[6] = 0;
2188 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2189 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2190 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2191 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2192 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2193 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2194 S_008F0C_ELEMENT_SIZE(1) |
2195 S_008F0C_INDEX_STRIDE(1) |
2196 S_008F0C_ADD_TID_ENABLE(true);
2197 }
2198
2199 desc += 8;
2200
2201 if (tess_rings_bo) {
2202 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2203 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2204
2205 desc[0] = tess_va;
2206 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2207 S_008F04_STRIDE(0) |
2208 S_008F04_SWIZZLE_ENABLE(false);
2209 desc[2] = tess_factor_ring_size;
2210 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2211 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2212 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2213 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2214 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2215 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2216 S_008F0C_ELEMENT_SIZE(0) |
2217 S_008F0C_INDEX_STRIDE(0) |
2218 S_008F0C_ADD_TID_ENABLE(false);
2219
2220 desc[4] = tess_offchip_va;
2221 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2222 S_008F04_STRIDE(0) |
2223 S_008F04_SWIZZLE_ENABLE(false);
2224 desc[6] = tess_offchip_ring_size;
2225 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2226 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2227 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2228 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2229 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2230 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2231 S_008F0C_ELEMENT_SIZE(0) |
2232 S_008F0C_INDEX_STRIDE(0) |
2233 S_008F0C_ADD_TID_ENABLE(false);
2234 }
2235
2236 desc += 8;
2237
2238 if (add_sample_positions) {
2239 /* add sample positions after all rings */
2240 memcpy(desc, queue->device->sample_locations_1x, 8);
2241 desc += 2;
2242 memcpy(desc, queue->device->sample_locations_2x, 16);
2243 desc += 4;
2244 memcpy(desc, queue->device->sample_locations_4x, 32);
2245 desc += 8;
2246 memcpy(desc, queue->device->sample_locations_8x, 64);
2247 }
2248 }
2249
2250 static unsigned
2251 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2252 {
2253 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2254 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2255 device->physical_device->rad_info.family != CHIP_STONEY;
2256 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2257 unsigned max_offchip_buffers;
2258 unsigned offchip_granularity;
2259 unsigned hs_offchip_param;
2260
2261 /*
2262 * Per RadeonSI:
2263 * This must be one less than the maximum number due to a hw limitation.
2264 * Various hardware bugs need thGFX7
2265 *
2266 * Per AMDVLK:
2267 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2268 * Gfx7 should limit max_offchip_buffers to 508
2269 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2270 *
2271 * Follow AMDVLK here.
2272 */
2273 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2274 device->physical_device->rad_info.chip_class == GFX7 ||
2275 device->physical_device->rad_info.chip_class == GFX6)
2276 --max_offchip_buffers_per_se;
2277
2278 max_offchip_buffers = max_offchip_buffers_per_se *
2279 device->physical_device->rad_info.max_se;
2280
2281 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2282 * around by setting 4K granularity.
2283 */
2284 if (device->tess_offchip_block_dw_size == 4096) {
2285 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2286 offchip_granularity = V_03093C_X_4K_DWORDS;
2287 } else {
2288 assert(device->tess_offchip_block_dw_size == 8192);
2289 offchip_granularity = V_03093C_X_8K_DWORDS;
2290 }
2291
2292 switch (device->physical_device->rad_info.chip_class) {
2293 case GFX6:
2294 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2295 break;
2296 case GFX7:
2297 case GFX8:
2298 case GFX9:
2299 default:
2300 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2301 break;
2302 }
2303
2304 *max_offchip_buffers_p = max_offchip_buffers;
2305 if (device->physical_device->rad_info.chip_class >= GFX7) {
2306 if (device->physical_device->rad_info.chip_class >= GFX8)
2307 --max_offchip_buffers;
2308 hs_offchip_param =
2309 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2310 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2311 } else {
2312 hs_offchip_param =
2313 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2314 }
2315 return hs_offchip_param;
2316 }
2317
2318 static void
2319 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2320 struct radeon_winsys_bo *esgs_ring_bo,
2321 uint32_t esgs_ring_size,
2322 struct radeon_winsys_bo *gsvs_ring_bo,
2323 uint32_t gsvs_ring_size)
2324 {
2325 if (!esgs_ring_bo && !gsvs_ring_bo)
2326 return;
2327
2328 if (esgs_ring_bo)
2329 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2330
2331 if (gsvs_ring_bo)
2332 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2333
2334 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2335 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2336 radeon_emit(cs, esgs_ring_size >> 8);
2337 radeon_emit(cs, gsvs_ring_size >> 8);
2338 } else {
2339 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2340 radeon_emit(cs, esgs_ring_size >> 8);
2341 radeon_emit(cs, gsvs_ring_size >> 8);
2342 }
2343 }
2344
2345 static void
2346 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2347 unsigned hs_offchip_param, unsigned tf_ring_size,
2348 struct radeon_winsys_bo *tess_rings_bo)
2349 {
2350 uint64_t tf_va;
2351
2352 if (!tess_rings_bo)
2353 return;
2354
2355 tf_va = radv_buffer_get_va(tess_rings_bo);
2356
2357 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2358
2359 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2360 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2361 S_030938_SIZE(tf_ring_size / 4));
2362 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2363 tf_va >> 8);
2364 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2365 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2366 S_030944_BASE_HI(tf_va >> 40));
2367 }
2368 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2369 hs_offchip_param);
2370 } else {
2371 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2372 S_008988_SIZE(tf_ring_size / 4));
2373 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2374 tf_va >> 8);
2375 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2376 hs_offchip_param);
2377 }
2378 }
2379
2380 static void
2381 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2382 struct radeon_winsys_bo *compute_scratch_bo)
2383 {
2384 uint64_t scratch_va;
2385
2386 if (!compute_scratch_bo)
2387 return;
2388
2389 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2390
2391 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2392
2393 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2394 radeon_emit(cs, scratch_va);
2395 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2396 S_008F04_SWIZZLE_ENABLE(1));
2397 }
2398
2399 static void
2400 radv_emit_global_shader_pointers(struct radv_queue *queue,
2401 struct radeon_cmdbuf *cs,
2402 struct radeon_winsys_bo *descriptor_bo)
2403 {
2404 uint64_t va;
2405
2406 if (!descriptor_bo)
2407 return;
2408
2409 va = radv_buffer_get_va(descriptor_bo);
2410
2411 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2412
2413 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2414 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2415 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2416 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2417 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2418
2419 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2420 radv_emit_shader_pointer(queue->device, cs, regs[i],
2421 va, true);
2422 }
2423 } else {
2424 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2425 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2426 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2427 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2428 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2429 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2430
2431 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2432 radv_emit_shader_pointer(queue->device, cs, regs[i],
2433 va, true);
2434 }
2435 }
2436 }
2437
2438 static void
2439 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2440 {
2441 struct radv_device *device = queue->device;
2442
2443 if (device->gfx_init) {
2444 uint64_t va = radv_buffer_get_va(device->gfx_init);
2445
2446 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2447 radeon_emit(cs, va);
2448 radeon_emit(cs, va >> 32);
2449 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2450
2451 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2452 } else {
2453 struct radv_physical_device *physical_device = device->physical_device;
2454 si_emit_graphics(physical_device, cs);
2455 }
2456 }
2457
2458 static void
2459 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2460 {
2461 struct radv_physical_device *physical_device = queue->device->physical_device;
2462 si_emit_compute(physical_device, cs);
2463 }
2464
2465 static VkResult
2466 radv_get_preamble_cs(struct radv_queue *queue,
2467 uint32_t scratch_size,
2468 uint32_t compute_scratch_size,
2469 uint32_t esgs_ring_size,
2470 uint32_t gsvs_ring_size,
2471 bool needs_tess_rings,
2472 bool needs_sample_positions,
2473 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2474 struct radeon_cmdbuf **initial_preamble_cs,
2475 struct radeon_cmdbuf **continue_preamble_cs)
2476 {
2477 struct radeon_winsys_bo *scratch_bo = NULL;
2478 struct radeon_winsys_bo *descriptor_bo = NULL;
2479 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2480 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2481 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2482 struct radeon_winsys_bo *tess_rings_bo = NULL;
2483 struct radeon_cmdbuf *dest_cs[3] = {0};
2484 bool add_tess_rings = false, add_sample_positions = false;
2485 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2486 unsigned max_offchip_buffers;
2487 unsigned hs_offchip_param = 0;
2488 unsigned tess_offchip_ring_offset;
2489 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2490 if (!queue->has_tess_rings) {
2491 if (needs_tess_rings)
2492 add_tess_rings = true;
2493 }
2494 if (!queue->has_sample_positions) {
2495 if (needs_sample_positions)
2496 add_sample_positions = true;
2497 }
2498 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2499 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2500 &max_offchip_buffers);
2501 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2502 tess_offchip_ring_size = max_offchip_buffers *
2503 queue->device->tess_offchip_block_dw_size * 4;
2504
2505 if (scratch_size <= queue->scratch_size &&
2506 compute_scratch_size <= queue->compute_scratch_size &&
2507 esgs_ring_size <= queue->esgs_ring_size &&
2508 gsvs_ring_size <= queue->gsvs_ring_size &&
2509 !add_tess_rings && !add_sample_positions &&
2510 queue->initial_preamble_cs) {
2511 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2512 *initial_preamble_cs = queue->initial_preamble_cs;
2513 *continue_preamble_cs = queue->continue_preamble_cs;
2514 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2515 *continue_preamble_cs = NULL;
2516 return VK_SUCCESS;
2517 }
2518
2519 if (scratch_size > queue->scratch_size) {
2520 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2521 scratch_size,
2522 4096,
2523 RADEON_DOMAIN_VRAM,
2524 ring_bo_flags,
2525 RADV_BO_PRIORITY_SCRATCH);
2526 if (!scratch_bo)
2527 goto fail;
2528 } else
2529 scratch_bo = queue->scratch_bo;
2530
2531 if (compute_scratch_size > queue->compute_scratch_size) {
2532 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2533 compute_scratch_size,
2534 4096,
2535 RADEON_DOMAIN_VRAM,
2536 ring_bo_flags,
2537 RADV_BO_PRIORITY_SCRATCH);
2538 if (!compute_scratch_bo)
2539 goto fail;
2540
2541 } else
2542 compute_scratch_bo = queue->compute_scratch_bo;
2543
2544 if (esgs_ring_size > queue->esgs_ring_size) {
2545 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2546 esgs_ring_size,
2547 4096,
2548 RADEON_DOMAIN_VRAM,
2549 ring_bo_flags,
2550 RADV_BO_PRIORITY_SCRATCH);
2551 if (!esgs_ring_bo)
2552 goto fail;
2553 } else {
2554 esgs_ring_bo = queue->esgs_ring_bo;
2555 esgs_ring_size = queue->esgs_ring_size;
2556 }
2557
2558 if (gsvs_ring_size > queue->gsvs_ring_size) {
2559 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2560 gsvs_ring_size,
2561 4096,
2562 RADEON_DOMAIN_VRAM,
2563 ring_bo_flags,
2564 RADV_BO_PRIORITY_SCRATCH);
2565 if (!gsvs_ring_bo)
2566 goto fail;
2567 } else {
2568 gsvs_ring_bo = queue->gsvs_ring_bo;
2569 gsvs_ring_size = queue->gsvs_ring_size;
2570 }
2571
2572 if (add_tess_rings) {
2573 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2574 tess_offchip_ring_offset + tess_offchip_ring_size,
2575 256,
2576 RADEON_DOMAIN_VRAM,
2577 ring_bo_flags,
2578 RADV_BO_PRIORITY_SCRATCH);
2579 if (!tess_rings_bo)
2580 goto fail;
2581 } else {
2582 tess_rings_bo = queue->tess_rings_bo;
2583 }
2584
2585 if (scratch_bo != queue->scratch_bo ||
2586 esgs_ring_bo != queue->esgs_ring_bo ||
2587 gsvs_ring_bo != queue->gsvs_ring_bo ||
2588 tess_rings_bo != queue->tess_rings_bo ||
2589 add_sample_positions) {
2590 uint32_t size = 0;
2591 if (gsvs_ring_bo || esgs_ring_bo ||
2592 tess_rings_bo || add_sample_positions) {
2593 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2594 if (add_sample_positions)
2595 size += 128; /* 64+32+16+8 = 120 bytes */
2596 }
2597 else if (scratch_bo)
2598 size = 8; /* 2 dword */
2599
2600 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2601 size,
2602 4096,
2603 RADEON_DOMAIN_VRAM,
2604 RADEON_FLAG_CPU_ACCESS |
2605 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2606 RADEON_FLAG_READ_ONLY,
2607 RADV_BO_PRIORITY_DESCRIPTOR);
2608 if (!descriptor_bo)
2609 goto fail;
2610 } else
2611 descriptor_bo = queue->descriptor_bo;
2612
2613 if (descriptor_bo != queue->descriptor_bo) {
2614 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2615
2616 if (scratch_bo) {
2617 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2618 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2619 S_008F04_SWIZZLE_ENABLE(1);
2620 map[0] = scratch_va;
2621 map[1] = rsrc1;
2622 }
2623
2624 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2625 fill_geom_tess_rings(queue, map, add_sample_positions,
2626 esgs_ring_size, esgs_ring_bo,
2627 gsvs_ring_size, gsvs_ring_bo,
2628 tess_factor_ring_size,
2629 tess_offchip_ring_offset,
2630 tess_offchip_ring_size,
2631 tess_rings_bo);
2632
2633 queue->device->ws->buffer_unmap(descriptor_bo);
2634 }
2635
2636 for(int i = 0; i < 3; ++i) {
2637 struct radeon_cmdbuf *cs = NULL;
2638 cs = queue->device->ws->cs_create(queue->device->ws,
2639 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2640 if (!cs)
2641 goto fail;
2642
2643 dest_cs[i] = cs;
2644
2645 if (scratch_bo)
2646 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2647
2648 /* Emit initial configuration. */
2649 switch (queue->queue_family_index) {
2650 case RADV_QUEUE_GENERAL:
2651 radv_init_graphics_state(cs, queue);
2652 break;
2653 case RADV_QUEUE_COMPUTE:
2654 radv_init_compute_state(cs, queue);
2655 break;
2656 case RADV_QUEUE_TRANSFER:
2657 break;
2658 }
2659
2660 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2661 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2662 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2663 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2664 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2665 }
2666
2667 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2668 gsvs_ring_bo, gsvs_ring_size);
2669 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2670 tess_factor_ring_size, tess_rings_bo);
2671 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2672 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2673
2674 if (i == 0) {
2675 si_cs_emit_cache_flush(cs,
2676 queue->device->physical_device->rad_info.chip_class,
2677 NULL, 0,
2678 queue->queue_family_index == RING_COMPUTE &&
2679 queue->device->physical_device->rad_info.chip_class >= GFX7,
2680 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2681 RADV_CMD_FLAG_INV_ICACHE |
2682 RADV_CMD_FLAG_INV_SMEM_L1 |
2683 RADV_CMD_FLAG_INV_VMEM_L1 |
2684 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2685 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2686 } else if (i == 1) {
2687 si_cs_emit_cache_flush(cs,
2688 queue->device->physical_device->rad_info.chip_class,
2689 NULL, 0,
2690 queue->queue_family_index == RING_COMPUTE &&
2691 queue->device->physical_device->rad_info.chip_class >= GFX7,
2692 RADV_CMD_FLAG_INV_ICACHE |
2693 RADV_CMD_FLAG_INV_SMEM_L1 |
2694 RADV_CMD_FLAG_INV_VMEM_L1 |
2695 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2696 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2697 }
2698
2699 if (!queue->device->ws->cs_finalize(cs))
2700 goto fail;
2701 }
2702
2703 if (queue->initial_full_flush_preamble_cs)
2704 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2705
2706 if (queue->initial_preamble_cs)
2707 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2708
2709 if (queue->continue_preamble_cs)
2710 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2711
2712 queue->initial_full_flush_preamble_cs = dest_cs[0];
2713 queue->initial_preamble_cs = dest_cs[1];
2714 queue->continue_preamble_cs = dest_cs[2];
2715
2716 if (scratch_bo != queue->scratch_bo) {
2717 if (queue->scratch_bo)
2718 queue->device->ws->buffer_destroy(queue->scratch_bo);
2719 queue->scratch_bo = scratch_bo;
2720 queue->scratch_size = scratch_size;
2721 }
2722
2723 if (compute_scratch_bo != queue->compute_scratch_bo) {
2724 if (queue->compute_scratch_bo)
2725 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2726 queue->compute_scratch_bo = compute_scratch_bo;
2727 queue->compute_scratch_size = compute_scratch_size;
2728 }
2729
2730 if (esgs_ring_bo != queue->esgs_ring_bo) {
2731 if (queue->esgs_ring_bo)
2732 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2733 queue->esgs_ring_bo = esgs_ring_bo;
2734 queue->esgs_ring_size = esgs_ring_size;
2735 }
2736
2737 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2738 if (queue->gsvs_ring_bo)
2739 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2740 queue->gsvs_ring_bo = gsvs_ring_bo;
2741 queue->gsvs_ring_size = gsvs_ring_size;
2742 }
2743
2744 if (tess_rings_bo != queue->tess_rings_bo) {
2745 queue->tess_rings_bo = tess_rings_bo;
2746 queue->has_tess_rings = true;
2747 }
2748
2749 if (descriptor_bo != queue->descriptor_bo) {
2750 if (queue->descriptor_bo)
2751 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2752
2753 queue->descriptor_bo = descriptor_bo;
2754 }
2755
2756 if (add_sample_positions)
2757 queue->has_sample_positions = true;
2758
2759 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2760 *initial_preamble_cs = queue->initial_preamble_cs;
2761 *continue_preamble_cs = queue->continue_preamble_cs;
2762 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2763 *continue_preamble_cs = NULL;
2764 return VK_SUCCESS;
2765 fail:
2766 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2767 if (dest_cs[i])
2768 queue->device->ws->cs_destroy(dest_cs[i]);
2769 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2770 queue->device->ws->buffer_destroy(descriptor_bo);
2771 if (scratch_bo && scratch_bo != queue->scratch_bo)
2772 queue->device->ws->buffer_destroy(scratch_bo);
2773 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2774 queue->device->ws->buffer_destroy(compute_scratch_bo);
2775 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2776 queue->device->ws->buffer_destroy(esgs_ring_bo);
2777 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2778 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2779 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2780 queue->device->ws->buffer_destroy(tess_rings_bo);
2781 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2782 }
2783
2784 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2785 struct radv_winsys_sem_counts *counts,
2786 int num_sems,
2787 const VkSemaphore *sems,
2788 VkFence _fence,
2789 bool reset_temp)
2790 {
2791 int syncobj_idx = 0, sem_idx = 0;
2792
2793 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2794 return VK_SUCCESS;
2795
2796 for (uint32_t i = 0; i < num_sems; i++) {
2797 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2798
2799 if (sem->temp_syncobj || sem->syncobj)
2800 counts->syncobj_count++;
2801 else
2802 counts->sem_count++;
2803 }
2804
2805 if (_fence != VK_NULL_HANDLE) {
2806 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2807 if (fence->temp_syncobj || fence->syncobj)
2808 counts->syncobj_count++;
2809 }
2810
2811 if (counts->syncobj_count) {
2812 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2813 if (!counts->syncobj)
2814 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2815 }
2816
2817 if (counts->sem_count) {
2818 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2819 if (!counts->sem) {
2820 free(counts->syncobj);
2821 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2822 }
2823 }
2824
2825 for (uint32_t i = 0; i < num_sems; i++) {
2826 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2827
2828 if (sem->temp_syncobj) {
2829 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2830 }
2831 else if (sem->syncobj)
2832 counts->syncobj[syncobj_idx++] = sem->syncobj;
2833 else {
2834 assert(sem->sem);
2835 counts->sem[sem_idx++] = sem->sem;
2836 }
2837 }
2838
2839 if (_fence != VK_NULL_HANDLE) {
2840 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2841 if (fence->temp_syncobj)
2842 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2843 else if (fence->syncobj)
2844 counts->syncobj[syncobj_idx++] = fence->syncobj;
2845 }
2846
2847 return VK_SUCCESS;
2848 }
2849
2850 static void
2851 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2852 {
2853 free(sem_info->wait.syncobj);
2854 free(sem_info->wait.sem);
2855 free(sem_info->signal.syncobj);
2856 free(sem_info->signal.sem);
2857 }
2858
2859
2860 static void radv_free_temp_syncobjs(struct radv_device *device,
2861 int num_sems,
2862 const VkSemaphore *sems)
2863 {
2864 for (uint32_t i = 0; i < num_sems; i++) {
2865 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2866
2867 if (sem->temp_syncobj) {
2868 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2869 sem->temp_syncobj = 0;
2870 }
2871 }
2872 }
2873
2874 static VkResult
2875 radv_alloc_sem_info(struct radv_instance *instance,
2876 struct radv_winsys_sem_info *sem_info,
2877 int num_wait_sems,
2878 const VkSemaphore *wait_sems,
2879 int num_signal_sems,
2880 const VkSemaphore *signal_sems,
2881 VkFence fence)
2882 {
2883 VkResult ret;
2884 memset(sem_info, 0, sizeof(*sem_info));
2885
2886 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2887 if (ret)
2888 return ret;
2889 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2890 if (ret)
2891 radv_free_sem_info(sem_info);
2892
2893 /* caller can override these */
2894 sem_info->cs_emit_wait = true;
2895 sem_info->cs_emit_signal = true;
2896 return ret;
2897 }
2898
2899 /* Signals fence as soon as all the work currently put on queue is done. */
2900 static VkResult radv_signal_fence(struct radv_queue *queue,
2901 struct radv_fence *fence)
2902 {
2903 int ret;
2904 VkResult result;
2905 struct radv_winsys_sem_info sem_info;
2906
2907 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2908 radv_fence_to_handle(fence));
2909 if (result != VK_SUCCESS)
2910 return result;
2911
2912 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2913 &queue->device->empty_cs[queue->queue_family_index],
2914 1, NULL, NULL, &sem_info, NULL,
2915 false, fence->fence);
2916 radv_free_sem_info(&sem_info);
2917
2918 if (ret)
2919 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2920
2921 return VK_SUCCESS;
2922 }
2923
2924 VkResult radv_QueueSubmit(
2925 VkQueue _queue,
2926 uint32_t submitCount,
2927 const VkSubmitInfo* pSubmits,
2928 VkFence _fence)
2929 {
2930 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2931 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2932 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2933 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2934 int ret;
2935 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
2936 uint32_t scratch_size = 0;
2937 uint32_t compute_scratch_size = 0;
2938 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2939 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2940 VkResult result;
2941 bool fence_emitted = false;
2942 bool tess_rings_needed = false;
2943 bool sample_positions_needed = false;
2944
2945 /* Do this first so failing to allocate scratch buffers can't result in
2946 * partially executed submissions. */
2947 for (uint32_t i = 0; i < submitCount; i++) {
2948 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2949 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2950 pSubmits[i].pCommandBuffers[j]);
2951
2952 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2953 compute_scratch_size = MAX2(compute_scratch_size,
2954 cmd_buffer->compute_scratch_size_needed);
2955 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2956 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2957 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2958 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2959 }
2960 }
2961
2962 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2963 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2964 sample_positions_needed, &initial_flush_preamble_cs,
2965 &initial_preamble_cs, &continue_preamble_cs);
2966 if (result != VK_SUCCESS)
2967 return result;
2968
2969 for (uint32_t i = 0; i < submitCount; i++) {
2970 struct radeon_cmdbuf **cs_array;
2971 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2972 bool can_patch = true;
2973 uint32_t advance;
2974 struct radv_winsys_sem_info sem_info;
2975
2976 result = radv_alloc_sem_info(queue->device->instance,
2977 &sem_info,
2978 pSubmits[i].waitSemaphoreCount,
2979 pSubmits[i].pWaitSemaphores,
2980 pSubmits[i].signalSemaphoreCount,
2981 pSubmits[i].pSignalSemaphores,
2982 _fence);
2983 if (result != VK_SUCCESS)
2984 return result;
2985
2986 if (!pSubmits[i].commandBufferCount) {
2987 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2988 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2989 &queue->device->empty_cs[queue->queue_family_index],
2990 1, NULL, NULL,
2991 &sem_info, NULL,
2992 false, base_fence);
2993 if (ret) {
2994 radv_loge("failed to submit CS %d\n", i);
2995 abort();
2996 }
2997 fence_emitted = true;
2998 }
2999 radv_free_sem_info(&sem_info);
3000 continue;
3001 }
3002
3003 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3004 (pSubmits[i].commandBufferCount));
3005
3006 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3007 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3008 pSubmits[i].pCommandBuffers[j]);
3009 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3010
3011 cs_array[j] = cmd_buffer->cs;
3012 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3013 can_patch = false;
3014
3015 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3016 }
3017
3018 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3019 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3020 const struct radv_winsys_bo_list *bo_list = NULL;
3021
3022 advance = MIN2(max_cs_submission,
3023 pSubmits[i].commandBufferCount - j);
3024
3025 if (queue->device->trace_bo)
3026 *queue->device->trace_id_ptr = 0;
3027
3028 sem_info.cs_emit_wait = j == 0;
3029 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3030
3031 if (unlikely(queue->device->use_global_bo_list)) {
3032 pthread_mutex_lock(&queue->device->bo_list.mutex);
3033 bo_list = &queue->device->bo_list.list;
3034 }
3035
3036 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3037 advance, initial_preamble, continue_preamble_cs,
3038 &sem_info, bo_list,
3039 can_patch, base_fence);
3040
3041 if (unlikely(queue->device->use_global_bo_list))
3042 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3043
3044 if (ret) {
3045 radv_loge("failed to submit CS %d\n", i);
3046 abort();
3047 }
3048 fence_emitted = true;
3049 if (queue->device->trace_bo) {
3050 radv_check_gpu_hangs(queue, cs_array[j]);
3051 }
3052 }
3053
3054 radv_free_temp_syncobjs(queue->device,
3055 pSubmits[i].waitSemaphoreCount,
3056 pSubmits[i].pWaitSemaphores);
3057 radv_free_sem_info(&sem_info);
3058 free(cs_array);
3059 }
3060
3061 if (fence) {
3062 if (!fence_emitted) {
3063 result = radv_signal_fence(queue, fence);
3064 if (result != VK_SUCCESS)
3065 return result;
3066 }
3067 }
3068
3069 return VK_SUCCESS;
3070 }
3071
3072 VkResult radv_QueueWaitIdle(
3073 VkQueue _queue)
3074 {
3075 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3076
3077 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3078 radv_queue_family_to_ring(queue->queue_family_index),
3079 queue->queue_idx);
3080 return VK_SUCCESS;
3081 }
3082
3083 VkResult radv_DeviceWaitIdle(
3084 VkDevice _device)
3085 {
3086 RADV_FROM_HANDLE(radv_device, device, _device);
3087
3088 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3089 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3090 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3091 }
3092 }
3093 return VK_SUCCESS;
3094 }
3095
3096 VkResult radv_EnumerateInstanceExtensionProperties(
3097 const char* pLayerName,
3098 uint32_t* pPropertyCount,
3099 VkExtensionProperties* pProperties)
3100 {
3101 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3102
3103 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3104 if (radv_supported_instance_extensions.extensions[i]) {
3105 vk_outarray_append(&out, prop) {
3106 *prop = radv_instance_extensions[i];
3107 }
3108 }
3109 }
3110
3111 return vk_outarray_status(&out);
3112 }
3113
3114 VkResult radv_EnumerateDeviceExtensionProperties(
3115 VkPhysicalDevice physicalDevice,
3116 const char* pLayerName,
3117 uint32_t* pPropertyCount,
3118 VkExtensionProperties* pProperties)
3119 {
3120 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3121 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3122
3123 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3124 if (device->supported_extensions.extensions[i]) {
3125 vk_outarray_append(&out, prop) {
3126 *prop = radv_device_extensions[i];
3127 }
3128 }
3129 }
3130
3131 return vk_outarray_status(&out);
3132 }
3133
3134 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3135 VkInstance _instance,
3136 const char* pName)
3137 {
3138 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3139
3140 return radv_lookup_entrypoint_checked(pName,
3141 instance ? instance->apiVersion : 0,
3142 instance ? &instance->enabled_extensions : NULL,
3143 NULL);
3144 }
3145
3146 /* The loader wants us to expose a second GetInstanceProcAddr function
3147 * to work around certain LD_PRELOAD issues seen in apps.
3148 */
3149 PUBLIC
3150 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3151 VkInstance instance,
3152 const char* pName);
3153
3154 PUBLIC
3155 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3156 VkInstance instance,
3157 const char* pName)
3158 {
3159 return radv_GetInstanceProcAddr(instance, pName);
3160 }
3161
3162 PUBLIC
3163 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3164 VkInstance _instance,
3165 const char* pName);
3166
3167 PUBLIC
3168 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3169 VkInstance _instance,
3170 const char* pName)
3171 {
3172 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3173
3174 return radv_lookup_physical_device_entrypoint_checked(pName,
3175 instance ? instance->apiVersion : 0,
3176 instance ? &instance->enabled_extensions : NULL);
3177 }
3178
3179 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3180 VkDevice _device,
3181 const char* pName)
3182 {
3183 RADV_FROM_HANDLE(radv_device, device, _device);
3184
3185 return radv_lookup_entrypoint_checked(pName,
3186 device->instance->apiVersion,
3187 &device->instance->enabled_extensions,
3188 &device->enabled_extensions);
3189 }
3190
3191 bool radv_get_memory_fd(struct radv_device *device,
3192 struct radv_device_memory *memory,
3193 int *pFD)
3194 {
3195 struct radeon_bo_metadata metadata;
3196
3197 if (memory->image) {
3198 radv_init_metadata(device, memory->image, &metadata);
3199 device->ws->buffer_set_metadata(memory->bo, &metadata);
3200 }
3201
3202 return device->ws->buffer_get_fd(device->ws, memory->bo,
3203 pFD);
3204 }
3205
3206 static VkResult radv_alloc_memory(struct radv_device *device,
3207 const VkMemoryAllocateInfo* pAllocateInfo,
3208 const VkAllocationCallbacks* pAllocator,
3209 VkDeviceMemory* pMem)
3210 {
3211 struct radv_device_memory *mem;
3212 VkResult result;
3213 enum radeon_bo_domain domain;
3214 uint32_t flags = 0;
3215 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3216
3217 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3218
3219 if (pAllocateInfo->allocationSize == 0) {
3220 /* Apparently, this is allowed */
3221 *pMem = VK_NULL_HANDLE;
3222 return VK_SUCCESS;
3223 }
3224
3225 const VkImportMemoryFdInfoKHR *import_info =
3226 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3227 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3228 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3229 const VkExportMemoryAllocateInfo *export_info =
3230 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3231 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3232 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3233
3234 const struct wsi_memory_allocate_info *wsi_info =
3235 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3236
3237 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3238 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3239 if (mem == NULL)
3240 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3241
3242 if (wsi_info && wsi_info->implicit_sync)
3243 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3244
3245 if (dedicate_info) {
3246 mem->image = radv_image_from_handle(dedicate_info->image);
3247 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3248 } else {
3249 mem->image = NULL;
3250 mem->buffer = NULL;
3251 }
3252
3253 float priority_float = 0.5;
3254 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3255 vk_find_struct_const(pAllocateInfo->pNext,
3256 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3257 if (priority_ext)
3258 priority_float = priority_ext->priority;
3259
3260 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3261 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3262
3263 mem->user_ptr = NULL;
3264
3265 if (import_info) {
3266 assert(import_info->handleType ==
3267 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3268 import_info->handleType ==
3269 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3270 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3271 priority, NULL, NULL);
3272 if (!mem->bo) {
3273 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3274 goto fail;
3275 } else {
3276 close(import_info->fd);
3277 }
3278 } else if (host_ptr_info) {
3279 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3280 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3281 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3282 pAllocateInfo->allocationSize,
3283 priority);
3284 if (!mem->bo) {
3285 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3286 goto fail;
3287 } else {
3288 mem->user_ptr = host_ptr_info->pHostPointer;
3289 }
3290 } else {
3291 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3292 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3293 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3294 domain = RADEON_DOMAIN_GTT;
3295 else
3296 domain = RADEON_DOMAIN_VRAM;
3297
3298 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3299 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3300 else
3301 flags |= RADEON_FLAG_CPU_ACCESS;
3302
3303 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3304 flags |= RADEON_FLAG_GTT_WC;
3305
3306 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3307 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3308 if (device->use_global_bo_list) {
3309 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3310 }
3311 }
3312
3313 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3314 domain, flags, priority);
3315
3316 if (!mem->bo) {
3317 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3318 goto fail;
3319 }
3320 mem->type_index = mem_type_index;
3321 }
3322
3323 result = radv_bo_list_add(device, mem->bo);
3324 if (result != VK_SUCCESS)
3325 goto fail_bo;
3326
3327 *pMem = radv_device_memory_to_handle(mem);
3328
3329 return VK_SUCCESS;
3330
3331 fail_bo:
3332 device->ws->buffer_destroy(mem->bo);
3333 fail:
3334 vk_free2(&device->alloc, pAllocator, mem);
3335
3336 return result;
3337 }
3338
3339 VkResult radv_AllocateMemory(
3340 VkDevice _device,
3341 const VkMemoryAllocateInfo* pAllocateInfo,
3342 const VkAllocationCallbacks* pAllocator,
3343 VkDeviceMemory* pMem)
3344 {
3345 RADV_FROM_HANDLE(radv_device, device, _device);
3346 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3347 }
3348
3349 void radv_FreeMemory(
3350 VkDevice _device,
3351 VkDeviceMemory _mem,
3352 const VkAllocationCallbacks* pAllocator)
3353 {
3354 RADV_FROM_HANDLE(radv_device, device, _device);
3355 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3356
3357 if (mem == NULL)
3358 return;
3359
3360 radv_bo_list_remove(device, mem->bo);
3361 device->ws->buffer_destroy(mem->bo);
3362 mem->bo = NULL;
3363
3364 vk_free2(&device->alloc, pAllocator, mem);
3365 }
3366
3367 VkResult radv_MapMemory(
3368 VkDevice _device,
3369 VkDeviceMemory _memory,
3370 VkDeviceSize offset,
3371 VkDeviceSize size,
3372 VkMemoryMapFlags flags,
3373 void** ppData)
3374 {
3375 RADV_FROM_HANDLE(radv_device, device, _device);
3376 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3377
3378 if (mem == NULL) {
3379 *ppData = NULL;
3380 return VK_SUCCESS;
3381 }
3382
3383 if (mem->user_ptr)
3384 *ppData = mem->user_ptr;
3385 else
3386 *ppData = device->ws->buffer_map(mem->bo);
3387
3388 if (*ppData) {
3389 *ppData += offset;
3390 return VK_SUCCESS;
3391 }
3392
3393 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3394 }
3395
3396 void radv_UnmapMemory(
3397 VkDevice _device,
3398 VkDeviceMemory _memory)
3399 {
3400 RADV_FROM_HANDLE(radv_device, device, _device);
3401 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3402
3403 if (mem == NULL)
3404 return;
3405
3406 if (mem->user_ptr == NULL)
3407 device->ws->buffer_unmap(mem->bo);
3408 }
3409
3410 VkResult radv_FlushMappedMemoryRanges(
3411 VkDevice _device,
3412 uint32_t memoryRangeCount,
3413 const VkMappedMemoryRange* pMemoryRanges)
3414 {
3415 return VK_SUCCESS;
3416 }
3417
3418 VkResult radv_InvalidateMappedMemoryRanges(
3419 VkDevice _device,
3420 uint32_t memoryRangeCount,
3421 const VkMappedMemoryRange* pMemoryRanges)
3422 {
3423 return VK_SUCCESS;
3424 }
3425
3426 void radv_GetBufferMemoryRequirements(
3427 VkDevice _device,
3428 VkBuffer _buffer,
3429 VkMemoryRequirements* pMemoryRequirements)
3430 {
3431 RADV_FROM_HANDLE(radv_device, device, _device);
3432 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3433
3434 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3435
3436 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3437 pMemoryRequirements->alignment = 4096;
3438 else
3439 pMemoryRequirements->alignment = 16;
3440
3441 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3442 }
3443
3444 void radv_GetBufferMemoryRequirements2(
3445 VkDevice device,
3446 const VkBufferMemoryRequirementsInfo2 *pInfo,
3447 VkMemoryRequirements2 *pMemoryRequirements)
3448 {
3449 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3450 &pMemoryRequirements->memoryRequirements);
3451 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3452 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3453 switch (ext->sType) {
3454 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3455 VkMemoryDedicatedRequirements *req =
3456 (VkMemoryDedicatedRequirements *) ext;
3457 req->requiresDedicatedAllocation = buffer->shareable;
3458 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3459 break;
3460 }
3461 default:
3462 break;
3463 }
3464 }
3465 }
3466
3467 void radv_GetImageMemoryRequirements(
3468 VkDevice _device,
3469 VkImage _image,
3470 VkMemoryRequirements* pMemoryRequirements)
3471 {
3472 RADV_FROM_HANDLE(radv_device, device, _device);
3473 RADV_FROM_HANDLE(radv_image, image, _image);
3474
3475 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3476
3477 pMemoryRequirements->size = image->size;
3478 pMemoryRequirements->alignment = image->alignment;
3479 }
3480
3481 void radv_GetImageMemoryRequirements2(
3482 VkDevice device,
3483 const VkImageMemoryRequirementsInfo2 *pInfo,
3484 VkMemoryRequirements2 *pMemoryRequirements)
3485 {
3486 radv_GetImageMemoryRequirements(device, pInfo->image,
3487 &pMemoryRequirements->memoryRequirements);
3488
3489 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3490
3491 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3492 switch (ext->sType) {
3493 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3494 VkMemoryDedicatedRequirements *req =
3495 (VkMemoryDedicatedRequirements *) ext;
3496 req->requiresDedicatedAllocation = image->shareable;
3497 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3498 break;
3499 }
3500 default:
3501 break;
3502 }
3503 }
3504 }
3505
3506 void radv_GetImageSparseMemoryRequirements(
3507 VkDevice device,
3508 VkImage image,
3509 uint32_t* pSparseMemoryRequirementCount,
3510 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3511 {
3512 stub();
3513 }
3514
3515 void radv_GetImageSparseMemoryRequirements2(
3516 VkDevice device,
3517 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3518 uint32_t* pSparseMemoryRequirementCount,
3519 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3520 {
3521 stub();
3522 }
3523
3524 void radv_GetDeviceMemoryCommitment(
3525 VkDevice device,
3526 VkDeviceMemory memory,
3527 VkDeviceSize* pCommittedMemoryInBytes)
3528 {
3529 *pCommittedMemoryInBytes = 0;
3530 }
3531
3532 VkResult radv_BindBufferMemory2(VkDevice device,
3533 uint32_t bindInfoCount,
3534 const VkBindBufferMemoryInfo *pBindInfos)
3535 {
3536 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3537 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3538 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3539
3540 if (mem) {
3541 buffer->bo = mem->bo;
3542 buffer->offset = pBindInfos[i].memoryOffset;
3543 } else {
3544 buffer->bo = NULL;
3545 }
3546 }
3547 return VK_SUCCESS;
3548 }
3549
3550 VkResult radv_BindBufferMemory(
3551 VkDevice device,
3552 VkBuffer buffer,
3553 VkDeviceMemory memory,
3554 VkDeviceSize memoryOffset)
3555 {
3556 const VkBindBufferMemoryInfo info = {
3557 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3558 .buffer = buffer,
3559 .memory = memory,
3560 .memoryOffset = memoryOffset
3561 };
3562
3563 return radv_BindBufferMemory2(device, 1, &info);
3564 }
3565
3566 VkResult radv_BindImageMemory2(VkDevice device,
3567 uint32_t bindInfoCount,
3568 const VkBindImageMemoryInfo *pBindInfos)
3569 {
3570 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3571 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3572 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3573
3574 if (mem) {
3575 image->bo = mem->bo;
3576 image->offset = pBindInfos[i].memoryOffset;
3577 } else {
3578 image->bo = NULL;
3579 image->offset = 0;
3580 }
3581 }
3582 return VK_SUCCESS;
3583 }
3584
3585
3586 VkResult radv_BindImageMemory(
3587 VkDevice device,
3588 VkImage image,
3589 VkDeviceMemory memory,
3590 VkDeviceSize memoryOffset)
3591 {
3592 const VkBindImageMemoryInfo info = {
3593 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3594 .image = image,
3595 .memory = memory,
3596 .memoryOffset = memoryOffset
3597 };
3598
3599 return radv_BindImageMemory2(device, 1, &info);
3600 }
3601
3602
3603 static void
3604 radv_sparse_buffer_bind_memory(struct radv_device *device,
3605 const VkSparseBufferMemoryBindInfo *bind)
3606 {
3607 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3608
3609 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3610 struct radv_device_memory *mem = NULL;
3611
3612 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3613 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3614
3615 device->ws->buffer_virtual_bind(buffer->bo,
3616 bind->pBinds[i].resourceOffset,
3617 bind->pBinds[i].size,
3618 mem ? mem->bo : NULL,
3619 bind->pBinds[i].memoryOffset);
3620 }
3621 }
3622
3623 static void
3624 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3625 const VkSparseImageOpaqueMemoryBindInfo *bind)
3626 {
3627 RADV_FROM_HANDLE(radv_image, image, bind->image);
3628
3629 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3630 struct radv_device_memory *mem = NULL;
3631
3632 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3633 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3634
3635 device->ws->buffer_virtual_bind(image->bo,
3636 bind->pBinds[i].resourceOffset,
3637 bind->pBinds[i].size,
3638 mem ? mem->bo : NULL,
3639 bind->pBinds[i].memoryOffset);
3640 }
3641 }
3642
3643 VkResult radv_QueueBindSparse(
3644 VkQueue _queue,
3645 uint32_t bindInfoCount,
3646 const VkBindSparseInfo* pBindInfo,
3647 VkFence _fence)
3648 {
3649 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3650 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3651 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3652 bool fence_emitted = false;
3653 VkResult result;
3654 int ret;
3655
3656 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3657 struct radv_winsys_sem_info sem_info;
3658 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3659 radv_sparse_buffer_bind_memory(queue->device,
3660 pBindInfo[i].pBufferBinds + j);
3661 }
3662
3663 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3664 radv_sparse_image_opaque_bind_memory(queue->device,
3665 pBindInfo[i].pImageOpaqueBinds + j);
3666 }
3667
3668 VkResult result;
3669 result = radv_alloc_sem_info(queue->device->instance,
3670 &sem_info,
3671 pBindInfo[i].waitSemaphoreCount,
3672 pBindInfo[i].pWaitSemaphores,
3673 pBindInfo[i].signalSemaphoreCount,
3674 pBindInfo[i].pSignalSemaphores,
3675 _fence);
3676 if (result != VK_SUCCESS)
3677 return result;
3678
3679 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3680 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3681 &queue->device->empty_cs[queue->queue_family_index],
3682 1, NULL, NULL,
3683 &sem_info, NULL,
3684 false, base_fence);
3685 if (ret) {
3686 radv_loge("failed to submit CS %d\n", i);
3687 abort();
3688 }
3689
3690 fence_emitted = true;
3691 }
3692
3693 radv_free_sem_info(&sem_info);
3694
3695 }
3696
3697 if (fence) {
3698 if (!fence_emitted) {
3699 result = radv_signal_fence(queue, fence);
3700 if (result != VK_SUCCESS)
3701 return result;
3702 }
3703 }
3704
3705 return VK_SUCCESS;
3706 }
3707
3708 VkResult radv_CreateFence(
3709 VkDevice _device,
3710 const VkFenceCreateInfo* pCreateInfo,
3711 const VkAllocationCallbacks* pAllocator,
3712 VkFence* pFence)
3713 {
3714 RADV_FROM_HANDLE(radv_device, device, _device);
3715 const VkExportFenceCreateInfo *export =
3716 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3717 VkExternalFenceHandleTypeFlags handleTypes =
3718 export ? export->handleTypes : 0;
3719
3720 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3721 sizeof(*fence), 8,
3722 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3723
3724 if (!fence)
3725 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3726
3727 fence->fence_wsi = NULL;
3728 fence->temp_syncobj = 0;
3729 if (device->always_use_syncobj || handleTypes) {
3730 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3731 if (ret) {
3732 vk_free2(&device->alloc, pAllocator, fence);
3733 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3734 }
3735 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3736 device->ws->signal_syncobj(device->ws, fence->syncobj);
3737 }
3738 fence->fence = NULL;
3739 } else {
3740 fence->fence = device->ws->create_fence();
3741 if (!fence->fence) {
3742 vk_free2(&device->alloc, pAllocator, fence);
3743 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3744 }
3745 fence->syncobj = 0;
3746 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3747 device->ws->signal_fence(fence->fence);
3748 }
3749
3750 *pFence = radv_fence_to_handle(fence);
3751
3752 return VK_SUCCESS;
3753 }
3754
3755 void radv_DestroyFence(
3756 VkDevice _device,
3757 VkFence _fence,
3758 const VkAllocationCallbacks* pAllocator)
3759 {
3760 RADV_FROM_HANDLE(radv_device, device, _device);
3761 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3762
3763 if (!fence)
3764 return;
3765
3766 if (fence->temp_syncobj)
3767 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3768 if (fence->syncobj)
3769 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3770 if (fence->fence)
3771 device->ws->destroy_fence(fence->fence);
3772 if (fence->fence_wsi)
3773 fence->fence_wsi->destroy(fence->fence_wsi);
3774 vk_free2(&device->alloc, pAllocator, fence);
3775 }
3776
3777
3778 uint64_t radv_get_current_time(void)
3779 {
3780 struct timespec tv;
3781 clock_gettime(CLOCK_MONOTONIC, &tv);
3782 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3783 }
3784
3785 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3786 {
3787 uint64_t current_time = radv_get_current_time();
3788
3789 timeout = MIN2(UINT64_MAX - current_time, timeout);
3790
3791 return current_time + timeout;
3792 }
3793
3794
3795 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3796 uint32_t fenceCount, const VkFence *pFences)
3797 {
3798 for (uint32_t i = 0; i < fenceCount; ++i) {
3799 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3800 if (fence->fence == NULL || fence->syncobj ||
3801 fence->temp_syncobj || fence->fence_wsi ||
3802 (!device->ws->is_fence_waitable(fence->fence)))
3803 return false;
3804 }
3805 return true;
3806 }
3807
3808 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3809 {
3810 for (uint32_t i = 0; i < fenceCount; ++i) {
3811 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3812 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3813 return false;
3814 }
3815 return true;
3816 }
3817
3818 VkResult radv_WaitForFences(
3819 VkDevice _device,
3820 uint32_t fenceCount,
3821 const VkFence* pFences,
3822 VkBool32 waitAll,
3823 uint64_t timeout)
3824 {
3825 RADV_FROM_HANDLE(radv_device, device, _device);
3826 timeout = radv_get_absolute_timeout(timeout);
3827
3828 if (device->always_use_syncobj &&
3829 radv_all_fences_syncobj(fenceCount, pFences))
3830 {
3831 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3832 if (!handles)
3833 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3834
3835 for (uint32_t i = 0; i < fenceCount; ++i) {
3836 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3837 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3838 }
3839
3840 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3841
3842 free(handles);
3843 return success ? VK_SUCCESS : VK_TIMEOUT;
3844 }
3845
3846 if (!waitAll && fenceCount > 1) {
3847 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3848 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3849 uint32_t wait_count = 0;
3850 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3851 if (!fences)
3852 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3853
3854 for (uint32_t i = 0; i < fenceCount; ++i) {
3855 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3856
3857 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3858 free(fences);
3859 return VK_SUCCESS;
3860 }
3861
3862 fences[wait_count++] = fence->fence;
3863 }
3864
3865 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3866 waitAll, timeout - radv_get_current_time());
3867
3868 free(fences);
3869 return success ? VK_SUCCESS : VK_TIMEOUT;
3870 }
3871
3872 while(radv_get_current_time() <= timeout) {
3873 for (uint32_t i = 0; i < fenceCount; ++i) {
3874 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3875 return VK_SUCCESS;
3876 }
3877 }
3878 return VK_TIMEOUT;
3879 }
3880
3881 for (uint32_t i = 0; i < fenceCount; ++i) {
3882 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3883 bool expired = false;
3884
3885 if (fence->temp_syncobj) {
3886 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3887 return VK_TIMEOUT;
3888 continue;
3889 }
3890
3891 if (fence->syncobj) {
3892 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3893 return VK_TIMEOUT;
3894 continue;
3895 }
3896
3897 if (fence->fence) {
3898 if (!device->ws->is_fence_waitable(fence->fence)) {
3899 while(!device->ws->is_fence_waitable(fence->fence) &&
3900 radv_get_current_time() <= timeout)
3901 /* Do nothing */;
3902 }
3903
3904 expired = device->ws->fence_wait(device->ws,
3905 fence->fence,
3906 true, timeout);
3907 if (!expired)
3908 return VK_TIMEOUT;
3909 }
3910
3911 if (fence->fence_wsi) {
3912 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3913 if (result != VK_SUCCESS)
3914 return result;
3915 }
3916 }
3917
3918 return VK_SUCCESS;
3919 }
3920
3921 VkResult radv_ResetFences(VkDevice _device,
3922 uint32_t fenceCount,
3923 const VkFence *pFences)
3924 {
3925 RADV_FROM_HANDLE(radv_device, device, _device);
3926
3927 for (unsigned i = 0; i < fenceCount; ++i) {
3928 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3929 if (fence->fence)
3930 device->ws->reset_fence(fence->fence);
3931
3932 /* Per spec, we first restore the permanent payload, and then reset, so
3933 * having a temp syncobj should not skip resetting the permanent syncobj. */
3934 if (fence->temp_syncobj) {
3935 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3936 fence->temp_syncobj = 0;
3937 }
3938
3939 if (fence->syncobj) {
3940 device->ws->reset_syncobj(device->ws, fence->syncobj);
3941 }
3942 }
3943
3944 return VK_SUCCESS;
3945 }
3946
3947 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3948 {
3949 RADV_FROM_HANDLE(radv_device, device, _device);
3950 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3951
3952 if (fence->temp_syncobj) {
3953 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3954 return success ? VK_SUCCESS : VK_NOT_READY;
3955 }
3956
3957 if (fence->syncobj) {
3958 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3959 return success ? VK_SUCCESS : VK_NOT_READY;
3960 }
3961
3962 if (fence->fence) {
3963 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3964 return VK_NOT_READY;
3965 }
3966 if (fence->fence_wsi) {
3967 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3968
3969 if (result != VK_SUCCESS) {
3970 if (result == VK_TIMEOUT)
3971 return VK_NOT_READY;
3972 return result;
3973 }
3974 }
3975 return VK_SUCCESS;
3976 }
3977
3978
3979 // Queue semaphore functions
3980
3981 VkResult radv_CreateSemaphore(
3982 VkDevice _device,
3983 const VkSemaphoreCreateInfo* pCreateInfo,
3984 const VkAllocationCallbacks* pAllocator,
3985 VkSemaphore* pSemaphore)
3986 {
3987 RADV_FROM_HANDLE(radv_device, device, _device);
3988 const VkExportSemaphoreCreateInfo *export =
3989 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
3990 VkExternalSemaphoreHandleTypeFlags handleTypes =
3991 export ? export->handleTypes : 0;
3992
3993 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3994 sizeof(*sem), 8,
3995 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3996 if (!sem)
3997 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3998
3999 sem->temp_syncobj = 0;
4000 /* create a syncobject if we are going to export this semaphore */
4001 if (device->always_use_syncobj || handleTypes) {
4002 assert (device->physical_device->rad_info.has_syncobj);
4003 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4004 if (ret) {
4005 vk_free2(&device->alloc, pAllocator, sem);
4006 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4007 }
4008 sem->sem = NULL;
4009 } else {
4010 sem->sem = device->ws->create_sem(device->ws);
4011 if (!sem->sem) {
4012 vk_free2(&device->alloc, pAllocator, sem);
4013 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4014 }
4015 sem->syncobj = 0;
4016 }
4017
4018 *pSemaphore = radv_semaphore_to_handle(sem);
4019 return VK_SUCCESS;
4020 }
4021
4022 void radv_DestroySemaphore(
4023 VkDevice _device,
4024 VkSemaphore _semaphore,
4025 const VkAllocationCallbacks* pAllocator)
4026 {
4027 RADV_FROM_HANDLE(radv_device, device, _device);
4028 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4029 if (!_semaphore)
4030 return;
4031
4032 if (sem->syncobj)
4033 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4034 else
4035 device->ws->destroy_sem(sem->sem);
4036 vk_free2(&device->alloc, pAllocator, sem);
4037 }
4038
4039 VkResult radv_CreateEvent(
4040 VkDevice _device,
4041 const VkEventCreateInfo* pCreateInfo,
4042 const VkAllocationCallbacks* pAllocator,
4043 VkEvent* pEvent)
4044 {
4045 RADV_FROM_HANDLE(radv_device, device, _device);
4046 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4047 sizeof(*event), 8,
4048 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4049
4050 if (!event)
4051 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4052
4053 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4054 RADEON_DOMAIN_GTT,
4055 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4056 RADV_BO_PRIORITY_FENCE);
4057 if (!event->bo) {
4058 vk_free2(&device->alloc, pAllocator, event);
4059 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4060 }
4061
4062 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4063
4064 *pEvent = radv_event_to_handle(event);
4065
4066 return VK_SUCCESS;
4067 }
4068
4069 void radv_DestroyEvent(
4070 VkDevice _device,
4071 VkEvent _event,
4072 const VkAllocationCallbacks* pAllocator)
4073 {
4074 RADV_FROM_HANDLE(radv_device, device, _device);
4075 RADV_FROM_HANDLE(radv_event, event, _event);
4076
4077 if (!event)
4078 return;
4079 device->ws->buffer_destroy(event->bo);
4080 vk_free2(&device->alloc, pAllocator, event);
4081 }
4082
4083 VkResult radv_GetEventStatus(
4084 VkDevice _device,
4085 VkEvent _event)
4086 {
4087 RADV_FROM_HANDLE(radv_event, event, _event);
4088
4089 if (*event->map == 1)
4090 return VK_EVENT_SET;
4091 return VK_EVENT_RESET;
4092 }
4093
4094 VkResult radv_SetEvent(
4095 VkDevice _device,
4096 VkEvent _event)
4097 {
4098 RADV_FROM_HANDLE(radv_event, event, _event);
4099 *event->map = 1;
4100
4101 return VK_SUCCESS;
4102 }
4103
4104 VkResult radv_ResetEvent(
4105 VkDevice _device,
4106 VkEvent _event)
4107 {
4108 RADV_FROM_HANDLE(radv_event, event, _event);
4109 *event->map = 0;
4110
4111 return VK_SUCCESS;
4112 }
4113
4114 VkResult radv_CreateBuffer(
4115 VkDevice _device,
4116 const VkBufferCreateInfo* pCreateInfo,
4117 const VkAllocationCallbacks* pAllocator,
4118 VkBuffer* pBuffer)
4119 {
4120 RADV_FROM_HANDLE(radv_device, device, _device);
4121 struct radv_buffer *buffer;
4122
4123 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4124
4125 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4126 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4127 if (buffer == NULL)
4128 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4129
4130 buffer->size = pCreateInfo->size;
4131 buffer->usage = pCreateInfo->usage;
4132 buffer->bo = NULL;
4133 buffer->offset = 0;
4134 buffer->flags = pCreateInfo->flags;
4135
4136 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4137 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4138
4139 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4140 buffer->bo = device->ws->buffer_create(device->ws,
4141 align64(buffer->size, 4096),
4142 4096, 0, RADEON_FLAG_VIRTUAL,
4143 RADV_BO_PRIORITY_VIRTUAL);
4144 if (!buffer->bo) {
4145 vk_free2(&device->alloc, pAllocator, buffer);
4146 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4147 }
4148 }
4149
4150 *pBuffer = radv_buffer_to_handle(buffer);
4151
4152 return VK_SUCCESS;
4153 }
4154
4155 void radv_DestroyBuffer(
4156 VkDevice _device,
4157 VkBuffer _buffer,
4158 const VkAllocationCallbacks* pAllocator)
4159 {
4160 RADV_FROM_HANDLE(radv_device, device, _device);
4161 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4162
4163 if (!buffer)
4164 return;
4165
4166 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4167 device->ws->buffer_destroy(buffer->bo);
4168
4169 vk_free2(&device->alloc, pAllocator, buffer);
4170 }
4171
4172 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4173 VkDevice device,
4174 const VkBufferDeviceAddressInfoEXT* pInfo)
4175 {
4176 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4177 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4178 }
4179
4180
4181 static inline unsigned
4182 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4183 {
4184 if (stencil)
4185 return plane->surface.u.legacy.stencil_tiling_index[level];
4186 else
4187 return plane->surface.u.legacy.tiling_index[level];
4188 }
4189
4190 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4191 {
4192 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4193 }
4194
4195 static uint32_t
4196 radv_init_dcc_control_reg(struct radv_device *device,
4197 struct radv_image_view *iview)
4198 {
4199 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4200 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4201 unsigned max_compressed_block_size;
4202 unsigned independent_64b_blocks;
4203
4204 if (!radv_image_has_dcc(iview->image))
4205 return 0;
4206
4207 if (iview->image->info.samples > 1) {
4208 if (iview->image->planes[0].surface.bpe == 1)
4209 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4210 else if (iview->image->planes[0].surface.bpe == 2)
4211 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4212 }
4213
4214 if (!device->physical_device->rad_info.has_dedicated_vram) {
4215 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4216 * dGPU and 64 for APU because all of our APUs to date use
4217 * DIMMs which have a request granularity size of 64B while all
4218 * other chips have a 32B request size.
4219 */
4220 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4221 }
4222
4223 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4224 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4225 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4226 /* If this DCC image is potentially going to be used in texture
4227 * fetches, we need some special settings.
4228 */
4229 independent_64b_blocks = 1;
4230 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4231 } else {
4232 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4233 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4234 * big as possible for better compression state.
4235 */
4236 independent_64b_blocks = 0;
4237 max_compressed_block_size = max_uncompressed_block_size;
4238 }
4239
4240 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4241 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4242 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4243 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
4244 }
4245
4246 static void
4247 radv_initialise_color_surface(struct radv_device *device,
4248 struct radv_color_buffer_info *cb,
4249 struct radv_image_view *iview)
4250 {
4251 const struct vk_format_description *desc;
4252 unsigned ntype, format, swap, endian;
4253 unsigned blend_clamp = 0, blend_bypass = 0;
4254 uint64_t va;
4255 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4256 const struct radeon_surf *surf = &plane->surface;
4257
4258 desc = vk_format_description(iview->vk_format);
4259
4260 memset(cb, 0, sizeof(*cb));
4261
4262 /* Intensity is implemented as Red, so treat it that way. */
4263 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4264
4265 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4266
4267 cb->cb_color_base = va >> 8;
4268
4269 if (device->physical_device->rad_info.chip_class >= GFX9) {
4270 struct gfx9_surf_meta_flags meta;
4271 if (iview->image->dcc_offset)
4272 meta = surf->u.gfx9.dcc;
4273 else
4274 meta = surf->u.gfx9.cmask;
4275
4276 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4277 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4278 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4279 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4280
4281 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4282 cb->cb_color_base |= surf->tile_swizzle;
4283
4284 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4285 } else {
4286 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4287 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4288
4289 cb->cb_color_base += level_info->offset >> 8;
4290 if (level_info->mode == RADEON_SURF_MODE_2D)
4291 cb->cb_color_base |= surf->tile_swizzle;
4292
4293 pitch_tile_max = level_info->nblk_x / 8 - 1;
4294 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4295 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4296
4297 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4298 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4299 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4300
4301 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4302
4303 if (radv_image_has_fmask(iview->image)) {
4304 if (device->physical_device->rad_info.chip_class >= GFX7)
4305 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4306 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4307 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4308 } else {
4309 /* This must be set for fast clear to work without FMASK. */
4310 if (device->physical_device->rad_info.chip_class >= GFX7)
4311 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4312 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4313 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4314 }
4315 }
4316
4317 /* CMASK variables */
4318 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4319 va += iview->image->cmask.offset;
4320 cb->cb_color_cmask = va >> 8;
4321
4322 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4323 va += iview->image->dcc_offset;
4324 cb->cb_dcc_base = va >> 8;
4325 cb->cb_dcc_base |= surf->tile_swizzle;
4326
4327 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4328 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4329 S_028C6C_SLICE_MAX(max_slice);
4330
4331 if (iview->image->info.samples > 1) {
4332 unsigned log_samples = util_logbase2(iview->image->info.samples);
4333
4334 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4335 S_028C74_NUM_FRAGMENTS(log_samples);
4336 }
4337
4338 if (radv_image_has_fmask(iview->image)) {
4339 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4340 cb->cb_color_fmask = va >> 8;
4341 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4342 } else {
4343 cb->cb_color_fmask = cb->cb_color_base;
4344 }
4345
4346 ntype = radv_translate_color_numformat(iview->vk_format,
4347 desc,
4348 vk_format_get_first_non_void_channel(iview->vk_format));
4349 format = radv_translate_colorformat(iview->vk_format);
4350 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4351 radv_finishme("Illegal color\n");
4352 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4353 endian = radv_colorformat_endian_swap(format);
4354
4355 /* blend clamp should be set for all NORM/SRGB types */
4356 if (ntype == V_028C70_NUMBER_UNORM ||
4357 ntype == V_028C70_NUMBER_SNORM ||
4358 ntype == V_028C70_NUMBER_SRGB)
4359 blend_clamp = 1;
4360
4361 /* set blend bypass according to docs if SINT/UINT or
4362 8/24 COLOR variants */
4363 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4364 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4365 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4366 blend_clamp = 0;
4367 blend_bypass = 1;
4368 }
4369 #if 0
4370 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4371 (format == V_028C70_COLOR_8 ||
4372 format == V_028C70_COLOR_8_8 ||
4373 format == V_028C70_COLOR_8_8_8_8))
4374 ->color_is_int8 = true;
4375 #endif
4376 cb->cb_color_info = S_028C70_FORMAT(format) |
4377 S_028C70_COMP_SWAP(swap) |
4378 S_028C70_BLEND_CLAMP(blend_clamp) |
4379 S_028C70_BLEND_BYPASS(blend_bypass) |
4380 S_028C70_SIMPLE_FLOAT(1) |
4381 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4382 ntype != V_028C70_NUMBER_SNORM &&
4383 ntype != V_028C70_NUMBER_SRGB &&
4384 format != V_028C70_COLOR_8_24 &&
4385 format != V_028C70_COLOR_24_8) |
4386 S_028C70_NUMBER_TYPE(ntype) |
4387 S_028C70_ENDIAN(endian);
4388 if (radv_image_has_fmask(iview->image)) {
4389 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4390 if (device->physical_device->rad_info.chip_class == GFX6) {
4391 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4392 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4393 }
4394 }
4395
4396 if (radv_image_has_cmask(iview->image) &&
4397 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4398 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4399
4400 if (radv_dcc_enabled(iview->image, iview->base_mip))
4401 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4402
4403 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4404
4405 /* This must be set for fast clear to work without FMASK. */
4406 if (!radv_image_has_fmask(iview->image) &&
4407 device->physical_device->rad_info.chip_class == GFX6) {
4408 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4409 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4410 }
4411
4412 if (device->physical_device->rad_info.chip_class >= GFX9) {
4413 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4414
4415 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4416 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4417 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4418 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4419
4420 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4421 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4422 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4423 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4424 S_028C68_MIP0_HEIGHT(height - 1) |
4425 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4426 }
4427 }
4428
4429 static unsigned
4430 radv_calc_decompress_on_z_planes(struct radv_device *device,
4431 struct radv_image_view *iview)
4432 {
4433 unsigned max_zplanes = 0;
4434
4435 assert(radv_image_is_tc_compat_htile(iview->image));
4436
4437 if (device->physical_device->rad_info.chip_class >= GFX9) {
4438 /* Default value for 32-bit depth surfaces. */
4439 max_zplanes = 4;
4440
4441 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4442 iview->image->info.samples > 1)
4443 max_zplanes = 2;
4444
4445 max_zplanes = max_zplanes + 1;
4446 } else {
4447 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4448 /* Do not enable Z plane compression for 16-bit depth
4449 * surfaces because isn't supported on GFX8. Only
4450 * 32-bit depth surfaces are supported by the hardware.
4451 * This allows to maintain shader compatibility and to
4452 * reduce the number of depth decompressions.
4453 */
4454 max_zplanes = 1;
4455 } else {
4456 if (iview->image->info.samples <= 1)
4457 max_zplanes = 5;
4458 else if (iview->image->info.samples <= 4)
4459 max_zplanes = 3;
4460 else
4461 max_zplanes = 2;
4462 }
4463 }
4464
4465 return max_zplanes;
4466 }
4467
4468 static void
4469 radv_initialise_ds_surface(struct radv_device *device,
4470 struct radv_ds_buffer_info *ds,
4471 struct radv_image_view *iview)
4472 {
4473 unsigned level = iview->base_mip;
4474 unsigned format, stencil_format;
4475 uint64_t va, s_offs, z_offs;
4476 bool stencil_only = false;
4477 const struct radv_image_plane *plane = &iview->image->planes[0];
4478 const struct radeon_surf *surf = &plane->surface;
4479
4480 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4481
4482 memset(ds, 0, sizeof(*ds));
4483 switch (iview->image->vk_format) {
4484 case VK_FORMAT_D24_UNORM_S8_UINT:
4485 case VK_FORMAT_X8_D24_UNORM_PACK32:
4486 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4487 ds->offset_scale = 2.0f;
4488 break;
4489 case VK_FORMAT_D16_UNORM:
4490 case VK_FORMAT_D16_UNORM_S8_UINT:
4491 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4492 ds->offset_scale = 4.0f;
4493 break;
4494 case VK_FORMAT_D32_SFLOAT:
4495 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4496 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4497 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4498 ds->offset_scale = 1.0f;
4499 break;
4500 case VK_FORMAT_S8_UINT:
4501 stencil_only = true;
4502 break;
4503 default:
4504 break;
4505 }
4506
4507 format = radv_translate_dbformat(iview->image->vk_format);
4508 stencil_format = surf->has_stencil ?
4509 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4510
4511 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4512 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4513 S_028008_SLICE_MAX(max_slice);
4514
4515 ds->db_htile_data_base = 0;
4516 ds->db_htile_surface = 0;
4517
4518 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4519 s_offs = z_offs = va;
4520
4521 if (device->physical_device->rad_info.chip_class >= GFX9) {
4522 assert(surf->u.gfx9.surf_offset == 0);
4523 s_offs += surf->u.gfx9.stencil_offset;
4524
4525 ds->db_z_info = S_028038_FORMAT(format) |
4526 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4527 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4528 S_028038_MAXMIP(iview->image->info.levels - 1) |
4529 S_028038_ZRANGE_PRECISION(1);
4530 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4531 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4532
4533 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4534 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4535 ds->db_depth_view |= S_028008_MIPID(level);
4536
4537 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4538 S_02801C_Y_MAX(iview->image->info.height - 1);
4539
4540 if (radv_htile_enabled(iview->image, level)) {
4541 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4542
4543 if (radv_image_is_tc_compat_htile(iview->image)) {
4544 unsigned max_zplanes =
4545 radv_calc_decompress_on_z_planes(device, iview);
4546
4547 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4548 S_028038_ITERATE_FLUSH(1);
4549 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4550 }
4551
4552 if (!surf->has_stencil)
4553 /* Use all of the htile_buffer for depth if there's no stencil. */
4554 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4555 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4556 iview->image->htile_offset;
4557 ds->db_htile_data_base = va >> 8;
4558 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4559 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned) |
4560 S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4561 }
4562 } else {
4563 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4564
4565 if (stencil_only)
4566 level_info = &surf->u.legacy.stencil_level[level];
4567
4568 z_offs += surf->u.legacy.level[level].offset;
4569 s_offs += surf->u.legacy.stencil_level[level].offset;
4570
4571 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4572 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4573 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4574
4575 if (iview->image->info.samples > 1)
4576 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4577
4578 if (device->physical_device->rad_info.chip_class >= GFX7) {
4579 struct radeon_info *info = &device->physical_device->rad_info;
4580 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4581 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4582 unsigned macro_index = surf->u.legacy.macro_tile_index;
4583 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4584 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4585 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4586
4587 if (stencil_only)
4588 tile_mode = stencil_tile_mode;
4589
4590 ds->db_depth_info |=
4591 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4592 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4593 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4594 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4595 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4596 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4597 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4598 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4599 } else {
4600 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4601 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4602 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4603 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4604 if (stencil_only)
4605 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4606 }
4607
4608 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4609 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4610 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4611
4612 if (radv_htile_enabled(iview->image, level)) {
4613 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4614
4615 if (!surf->has_stencil &&
4616 !radv_image_is_tc_compat_htile(iview->image))
4617 /* Use all of the htile_buffer for depth if there's no stencil. */
4618 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4619
4620 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4621 iview->image->htile_offset;
4622 ds->db_htile_data_base = va >> 8;
4623 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4624
4625 if (radv_image_is_tc_compat_htile(iview->image)) {
4626 unsigned max_zplanes =
4627 radv_calc_decompress_on_z_planes(device, iview);
4628
4629 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4630 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4631 }
4632 }
4633 }
4634
4635 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4636 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4637 }
4638
4639 VkResult radv_CreateFramebuffer(
4640 VkDevice _device,
4641 const VkFramebufferCreateInfo* pCreateInfo,
4642 const VkAllocationCallbacks* pAllocator,
4643 VkFramebuffer* pFramebuffer)
4644 {
4645 RADV_FROM_HANDLE(radv_device, device, _device);
4646 struct radv_framebuffer *framebuffer;
4647
4648 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4649
4650 size_t size = sizeof(*framebuffer) +
4651 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4652 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4653 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4654 if (framebuffer == NULL)
4655 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4656
4657 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4658 framebuffer->width = pCreateInfo->width;
4659 framebuffer->height = pCreateInfo->height;
4660 framebuffer->layers = pCreateInfo->layers;
4661 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4662 VkImageView _iview = pCreateInfo->pAttachments[i];
4663 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4664 framebuffer->attachments[i].attachment = iview;
4665 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4666 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4667 } else {
4668 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4669 }
4670 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4671 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4672 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4673 }
4674
4675 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4676 return VK_SUCCESS;
4677 }
4678
4679 void radv_DestroyFramebuffer(
4680 VkDevice _device,
4681 VkFramebuffer _fb,
4682 const VkAllocationCallbacks* pAllocator)
4683 {
4684 RADV_FROM_HANDLE(radv_device, device, _device);
4685 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4686
4687 if (!fb)
4688 return;
4689 vk_free2(&device->alloc, pAllocator, fb);
4690 }
4691
4692 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4693 {
4694 switch (address_mode) {
4695 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4696 return V_008F30_SQ_TEX_WRAP;
4697 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4698 return V_008F30_SQ_TEX_MIRROR;
4699 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4700 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4701 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4702 return V_008F30_SQ_TEX_CLAMP_BORDER;
4703 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4704 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4705 default:
4706 unreachable("illegal tex wrap mode");
4707 break;
4708 }
4709 }
4710
4711 static unsigned
4712 radv_tex_compare(VkCompareOp op)
4713 {
4714 switch (op) {
4715 case VK_COMPARE_OP_NEVER:
4716 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4717 case VK_COMPARE_OP_LESS:
4718 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4719 case VK_COMPARE_OP_EQUAL:
4720 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4721 case VK_COMPARE_OP_LESS_OR_EQUAL:
4722 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4723 case VK_COMPARE_OP_GREATER:
4724 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4725 case VK_COMPARE_OP_NOT_EQUAL:
4726 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4727 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4728 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4729 case VK_COMPARE_OP_ALWAYS:
4730 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4731 default:
4732 unreachable("illegal compare mode");
4733 break;
4734 }
4735 }
4736
4737 static unsigned
4738 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4739 {
4740 switch (filter) {
4741 case VK_FILTER_NEAREST:
4742 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4743 V_008F38_SQ_TEX_XY_FILTER_POINT);
4744 case VK_FILTER_LINEAR:
4745 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4746 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4747 case VK_FILTER_CUBIC_IMG:
4748 default:
4749 fprintf(stderr, "illegal texture filter");
4750 return 0;
4751 }
4752 }
4753
4754 static unsigned
4755 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4756 {
4757 switch (mode) {
4758 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4759 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4760 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4761 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4762 default:
4763 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4764 }
4765 }
4766
4767 static unsigned
4768 radv_tex_bordercolor(VkBorderColor bcolor)
4769 {
4770 switch (bcolor) {
4771 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4772 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4773 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4774 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4775 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4776 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4777 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4778 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4779 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4780 default:
4781 break;
4782 }
4783 return 0;
4784 }
4785
4786 static unsigned
4787 radv_tex_aniso_filter(unsigned filter)
4788 {
4789 if (filter < 2)
4790 return 0;
4791 if (filter < 4)
4792 return 1;
4793 if (filter < 8)
4794 return 2;
4795 if (filter < 16)
4796 return 3;
4797 return 4;
4798 }
4799
4800 static unsigned
4801 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4802 {
4803 switch (mode) {
4804 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4805 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4806 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4807 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4808 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4809 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4810 default:
4811 break;
4812 }
4813 return 0;
4814 }
4815
4816 static uint32_t
4817 radv_get_max_anisotropy(struct radv_device *device,
4818 const VkSamplerCreateInfo *pCreateInfo)
4819 {
4820 if (device->force_aniso >= 0)
4821 return device->force_aniso;
4822
4823 if (pCreateInfo->anisotropyEnable &&
4824 pCreateInfo->maxAnisotropy > 1.0f)
4825 return (uint32_t)pCreateInfo->maxAnisotropy;
4826
4827 return 0;
4828 }
4829
4830 static void
4831 radv_init_sampler(struct radv_device *device,
4832 struct radv_sampler *sampler,
4833 const VkSamplerCreateInfo *pCreateInfo)
4834 {
4835 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4836 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4837 bool is_vi = (device->physical_device->rad_info.chip_class >= GFX8);
4838 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4839
4840 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4841 vk_find_struct_const(pCreateInfo->pNext,
4842 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4843 if (sampler_reduction)
4844 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4845
4846 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4847 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4848 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4849 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4850 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4851 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4852 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4853 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4854 S_008F30_DISABLE_CUBE_WRAP(0) |
4855 S_008F30_COMPAT_MODE(is_vi) |
4856 S_008F30_FILTER_MODE(filter_mode));
4857 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4858 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4859 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4860 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4861 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4862 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4863 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4864 S_008F38_MIP_POINT_PRECLAMP(0) |
4865 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
4866 S_008F38_FILTER_PREC_FIX(1) |
4867 S_008F38_ANISO_OVERRIDE(is_vi));
4868 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4869 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4870 }
4871
4872 VkResult radv_CreateSampler(
4873 VkDevice _device,
4874 const VkSamplerCreateInfo* pCreateInfo,
4875 const VkAllocationCallbacks* pAllocator,
4876 VkSampler* pSampler)
4877 {
4878 RADV_FROM_HANDLE(radv_device, device, _device);
4879 struct radv_sampler *sampler;
4880
4881 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
4882 vk_find_struct_const(pCreateInfo->pNext,
4883 SAMPLER_YCBCR_CONVERSION_INFO);
4884
4885 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4886
4887 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4888 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4889 if (!sampler)
4890 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4891
4892 radv_init_sampler(device, sampler, pCreateInfo);
4893
4894 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
4895 *pSampler = radv_sampler_to_handle(sampler);
4896
4897 return VK_SUCCESS;
4898 }
4899
4900 void radv_DestroySampler(
4901 VkDevice _device,
4902 VkSampler _sampler,
4903 const VkAllocationCallbacks* pAllocator)
4904 {
4905 RADV_FROM_HANDLE(radv_device, device, _device);
4906 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4907
4908 if (!sampler)
4909 return;
4910 vk_free2(&device->alloc, pAllocator, sampler);
4911 }
4912
4913 /* vk_icd.h does not declare this function, so we declare it here to
4914 * suppress Wmissing-prototypes.
4915 */
4916 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4917 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4918
4919 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4920 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4921 {
4922 /* For the full details on loader interface versioning, see
4923 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4924 * What follows is a condensed summary, to help you navigate the large and
4925 * confusing official doc.
4926 *
4927 * - Loader interface v0 is incompatible with later versions. We don't
4928 * support it.
4929 *
4930 * - In loader interface v1:
4931 * - The first ICD entrypoint called by the loader is
4932 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4933 * entrypoint.
4934 * - The ICD must statically expose no other Vulkan symbol unless it is
4935 * linked with -Bsymbolic.
4936 * - Each dispatchable Vulkan handle created by the ICD must be
4937 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4938 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4939 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4940 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4941 * such loader-managed surfaces.
4942 *
4943 * - Loader interface v2 differs from v1 in:
4944 * - The first ICD entrypoint called by the loader is
4945 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4946 * statically expose this entrypoint.
4947 *
4948 * - Loader interface v3 differs from v2 in:
4949 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4950 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4951 * because the loader no longer does so.
4952 */
4953 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
4954 return VK_SUCCESS;
4955 }
4956
4957 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4958 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4959 int *pFD)
4960 {
4961 RADV_FROM_HANDLE(radv_device, device, _device);
4962 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4963
4964 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4965
4966 /* At the moment, we support only the below handle types. */
4967 assert(pGetFdInfo->handleType ==
4968 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4969 pGetFdInfo->handleType ==
4970 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4971
4972 bool ret = radv_get_memory_fd(device, memory, pFD);
4973 if (ret == false)
4974 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4975 return VK_SUCCESS;
4976 }
4977
4978 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4979 VkExternalMemoryHandleTypeFlagBits handleType,
4980 int fd,
4981 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4982 {
4983 RADV_FROM_HANDLE(radv_device, device, _device);
4984
4985 switch (handleType) {
4986 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4987 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4988 return VK_SUCCESS;
4989
4990 default:
4991 /* The valid usage section for this function says:
4992 *
4993 * "handleType must not be one of the handle types defined as
4994 * opaque."
4995 *
4996 * So opaque handle types fall into the default "unsupported" case.
4997 */
4998 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4999 }
5000 }
5001
5002 static VkResult radv_import_opaque_fd(struct radv_device *device,
5003 int fd,
5004 uint32_t *syncobj)
5005 {
5006 uint32_t syncobj_handle = 0;
5007 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5008 if (ret != 0)
5009 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5010
5011 if (*syncobj)
5012 device->ws->destroy_syncobj(device->ws, *syncobj);
5013
5014 *syncobj = syncobj_handle;
5015 close(fd);
5016
5017 return VK_SUCCESS;
5018 }
5019
5020 static VkResult radv_import_sync_fd(struct radv_device *device,
5021 int fd,
5022 uint32_t *syncobj)
5023 {
5024 /* If we create a syncobj we do it locally so that if we have an error, we don't
5025 * leave a syncobj in an undetermined state in the fence. */
5026 uint32_t syncobj_handle = *syncobj;
5027 if (!syncobj_handle) {
5028 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5029 if (ret) {
5030 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5031 }
5032 }
5033
5034 if (fd == -1) {
5035 device->ws->signal_syncobj(device->ws, syncobj_handle);
5036 } else {
5037 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5038 if (ret != 0)
5039 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5040 }
5041
5042 *syncobj = syncobj_handle;
5043 if (fd != -1)
5044 close(fd);
5045
5046 return VK_SUCCESS;
5047 }
5048
5049 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5050 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5051 {
5052 RADV_FROM_HANDLE(radv_device, device, _device);
5053 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5054 uint32_t *syncobj_dst = NULL;
5055
5056 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5057 syncobj_dst = &sem->temp_syncobj;
5058 } else {
5059 syncobj_dst = &sem->syncobj;
5060 }
5061
5062 switch(pImportSemaphoreFdInfo->handleType) {
5063 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5064 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5065 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5066 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5067 default:
5068 unreachable("Unhandled semaphore handle type");
5069 }
5070 }
5071
5072 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5073 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5074 int *pFd)
5075 {
5076 RADV_FROM_HANDLE(radv_device, device, _device);
5077 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5078 int ret;
5079 uint32_t syncobj_handle;
5080
5081 if (sem->temp_syncobj)
5082 syncobj_handle = sem->temp_syncobj;
5083 else
5084 syncobj_handle = sem->syncobj;
5085
5086 switch(pGetFdInfo->handleType) {
5087 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5088 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5089 break;
5090 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5091 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5092 if (!ret) {
5093 if (sem->temp_syncobj) {
5094 close (sem->temp_syncobj);
5095 sem->temp_syncobj = 0;
5096 } else {
5097 device->ws->reset_syncobj(device->ws, syncobj_handle);
5098 }
5099 }
5100 break;
5101 default:
5102 unreachable("Unhandled semaphore handle type");
5103 }
5104
5105 if (ret)
5106 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5107 return VK_SUCCESS;
5108 }
5109
5110 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5111 VkPhysicalDevice physicalDevice,
5112 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5113 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5114 {
5115 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5116
5117 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5118 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5119 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5120 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5121 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5122 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5123 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5124 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5125 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5126 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5127 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5128 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5129 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5130 } else {
5131 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5132 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5133 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5134 }
5135 }
5136
5137 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5138 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5139 {
5140 RADV_FROM_HANDLE(radv_device, device, _device);
5141 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5142 uint32_t *syncobj_dst = NULL;
5143
5144
5145 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5146 syncobj_dst = &fence->temp_syncobj;
5147 } else {
5148 syncobj_dst = &fence->syncobj;
5149 }
5150
5151 switch(pImportFenceFdInfo->handleType) {
5152 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5153 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5154 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5155 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5156 default:
5157 unreachable("Unhandled fence handle type");
5158 }
5159 }
5160
5161 VkResult radv_GetFenceFdKHR(VkDevice _device,
5162 const VkFenceGetFdInfoKHR *pGetFdInfo,
5163 int *pFd)
5164 {
5165 RADV_FROM_HANDLE(radv_device, device, _device);
5166 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5167 int ret;
5168 uint32_t syncobj_handle;
5169
5170 if (fence->temp_syncobj)
5171 syncobj_handle = fence->temp_syncobj;
5172 else
5173 syncobj_handle = fence->syncobj;
5174
5175 switch(pGetFdInfo->handleType) {
5176 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5177 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5178 break;
5179 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5180 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5181 if (!ret) {
5182 if (fence->temp_syncobj) {
5183 close (fence->temp_syncobj);
5184 fence->temp_syncobj = 0;
5185 } else {
5186 device->ws->reset_syncobj(device->ws, syncobj_handle);
5187 }
5188 }
5189 break;
5190 default:
5191 unreachable("Unhandled fence handle type");
5192 }
5193
5194 if (ret)
5195 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5196 return VK_SUCCESS;
5197 }
5198
5199 void radv_GetPhysicalDeviceExternalFenceProperties(
5200 VkPhysicalDevice physicalDevice,
5201 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5202 VkExternalFenceProperties *pExternalFenceProperties)
5203 {
5204 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5205
5206 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5207 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5208 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5209 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5210 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5211 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5212 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5213 } else {
5214 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5215 pExternalFenceProperties->compatibleHandleTypes = 0;
5216 pExternalFenceProperties->externalFenceFeatures = 0;
5217 }
5218 }
5219
5220 VkResult
5221 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5222 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5223 const VkAllocationCallbacks* pAllocator,
5224 VkDebugReportCallbackEXT* pCallback)
5225 {
5226 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5227 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5228 pCreateInfo, pAllocator, &instance->alloc,
5229 pCallback);
5230 }
5231
5232 void
5233 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5234 VkDebugReportCallbackEXT _callback,
5235 const VkAllocationCallbacks* pAllocator)
5236 {
5237 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5238 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5239 _callback, pAllocator, &instance->alloc);
5240 }
5241
5242 void
5243 radv_DebugReportMessageEXT(VkInstance _instance,
5244 VkDebugReportFlagsEXT flags,
5245 VkDebugReportObjectTypeEXT objectType,
5246 uint64_t object,
5247 size_t location,
5248 int32_t messageCode,
5249 const char* pLayerPrefix,
5250 const char* pMessage)
5251 {
5252 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5253 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5254 object, location, messageCode, pLayerPrefix, pMessage);
5255 }
5256
5257 void
5258 radv_GetDeviceGroupPeerMemoryFeatures(
5259 VkDevice device,
5260 uint32_t heapIndex,
5261 uint32_t localDeviceIndex,
5262 uint32_t remoteDeviceIndex,
5263 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5264 {
5265 assert(localDeviceIndex == remoteDeviceIndex);
5266
5267 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5268 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5269 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5270 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5271 }
5272
5273 static const VkTimeDomainEXT radv_time_domains[] = {
5274 VK_TIME_DOMAIN_DEVICE_EXT,
5275 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5276 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5277 };
5278
5279 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5280 VkPhysicalDevice physicalDevice,
5281 uint32_t *pTimeDomainCount,
5282 VkTimeDomainEXT *pTimeDomains)
5283 {
5284 int d;
5285 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5286
5287 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5288 vk_outarray_append(&out, i) {
5289 *i = radv_time_domains[d];
5290 }
5291 }
5292
5293 return vk_outarray_status(&out);
5294 }
5295
5296 static uint64_t
5297 radv_clock_gettime(clockid_t clock_id)
5298 {
5299 struct timespec current;
5300 int ret;
5301
5302 ret = clock_gettime(clock_id, &current);
5303 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5304 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5305 if (ret < 0)
5306 return 0;
5307
5308 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5309 }
5310
5311 VkResult radv_GetCalibratedTimestampsEXT(
5312 VkDevice _device,
5313 uint32_t timestampCount,
5314 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5315 uint64_t *pTimestamps,
5316 uint64_t *pMaxDeviation)
5317 {
5318 RADV_FROM_HANDLE(radv_device, device, _device);
5319 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5320 int d;
5321 uint64_t begin, end;
5322 uint64_t max_clock_period = 0;
5323
5324 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5325
5326 for (d = 0; d < timestampCount; d++) {
5327 switch (pTimestampInfos[d].timeDomain) {
5328 case VK_TIME_DOMAIN_DEVICE_EXT:
5329 pTimestamps[d] = device->ws->query_value(device->ws,
5330 RADEON_TIMESTAMP);
5331 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5332 max_clock_period = MAX2(max_clock_period, device_period);
5333 break;
5334 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5335 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5336 max_clock_period = MAX2(max_clock_period, 1);
5337 break;
5338
5339 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5340 pTimestamps[d] = begin;
5341 break;
5342 default:
5343 pTimestamps[d] = 0;
5344 break;
5345 }
5346 }
5347
5348 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5349
5350 /*
5351 * The maximum deviation is the sum of the interval over which we
5352 * perform the sampling and the maximum period of any sampled
5353 * clock. That's because the maximum skew between any two sampled
5354 * clock edges is when the sampled clock with the largest period is
5355 * sampled at the end of that period but right at the beginning of the
5356 * sampling interval and some other clock is sampled right at the
5357 * begining of its sampling period and right at the end of the
5358 * sampling interval. Let's assume the GPU has the longest clock
5359 * period and that the application is sampling GPU and monotonic:
5360 *
5361 * s e
5362 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5363 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5364 *
5365 * g
5366 * 0 1 2 3
5367 * GPU -----_____-----_____-----_____-----_____
5368 *
5369 * m
5370 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5371 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5372 *
5373 * Interval <----------------->
5374 * Deviation <-------------------------->
5375 *
5376 * s = read(raw) 2
5377 * g = read(GPU) 1
5378 * m = read(monotonic) 2
5379 * e = read(raw) b
5380 *
5381 * We round the sample interval up by one tick to cover sampling error
5382 * in the interval clock
5383 */
5384
5385 uint64_t sample_interval = end - begin + 1;
5386
5387 *pMaxDeviation = sample_interval + max_clock_period;
5388
5389 return VK_SUCCESS;
5390 }
5391
5392 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5393 VkPhysicalDevice physicalDevice,
5394 VkSampleCountFlagBits samples,
5395 VkMultisamplePropertiesEXT* pMultisampleProperties)
5396 {
5397 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5398 VK_SAMPLE_COUNT_4_BIT |
5399 VK_SAMPLE_COUNT_8_BIT)) {
5400 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5401 } else {
5402 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5403 }
5404 }