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radv: Implement VK_EXT_discard_rectangles.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "util/debug.h"
48
49 static int
50 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
51 {
52 uint32_t mesa_timestamp, llvm_timestamp;
53 uint16_t f = family;
54 memset(uuid, 0, VK_UUID_SIZE);
55 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
56 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
57 return -1;
58
59 memcpy(uuid, &mesa_timestamp, 4);
60 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
61 memcpy((char*)uuid + 8, &f, 2);
62 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
63 return 0;
64 }
65
66 static void
67 radv_get_driver_uuid(void *uuid)
68 {
69 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
70 }
71
72 static void
73 radv_get_device_uuid(struct radeon_info *info, void *uuid)
74 {
75 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
76 }
77
78 static void
79 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
80 {
81 const char *chip_string;
82 char llvm_string[32] = {};
83
84 switch (family) {
85 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
86 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
87 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
88 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
89 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
90 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
91 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
92 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
93 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
94 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
95 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
96 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
97 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
98 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
99 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
100 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
101 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
102 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
103 case CHIP_VEGA10: chip_string = "AMD RADV VEGA"; break;
104 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
105 default: chip_string = "AMD RADV unknown"; break;
106 }
107
108 if (HAVE_LLVM > 0) {
109 snprintf(llvm_string, sizeof(llvm_string),
110 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
111 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
112 }
113
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = 0,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
162 .heapIndex = gart_index,
163 };
164 }
165 if (visible_vram_index >= 0) {
166 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
167 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
168 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
169 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
170 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
171 .heapIndex = visible_vram_index,
172 };
173 }
174 if (gart_index >= 0) {
175 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
176 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
177 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
178 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
179 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
180 .heapIndex = gart_index,
181 };
182 }
183 device->memory_properties.memoryTypeCount = type_count;
184 }
185
186 static VkResult
187 radv_physical_device_init(struct radv_physical_device *device,
188 struct radv_instance *instance,
189 drmDevicePtr drm_device)
190 {
191 const char *path = drm_device->nodes[DRM_NODE_RENDER];
192 VkResult result;
193 drmVersionPtr version;
194 int fd;
195
196 fd = open(path, O_RDWR | O_CLOEXEC);
197 if (fd < 0)
198 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
199
200 version = drmGetVersion(fd);
201 if (!version) {
202 close(fd);
203 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
204 "failed to get version %s: %m", path);
205 }
206
207 if (strcmp(version->name, "amdgpu")) {
208 drmFreeVersion(version);
209 close(fd);
210 return VK_ERROR_INCOMPATIBLE_DRIVER;
211 }
212 drmFreeVersion(version);
213
214 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
215 device->instance = instance;
216 assert(strlen(path) < ARRAY_SIZE(device->path));
217 strncpy(device->path, path, ARRAY_SIZE(device->path));
218
219 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
220 instance->perftest_flags);
221 if (!device->ws) {
222 result = VK_ERROR_INCOMPATIBLE_DRIVER;
223 goto fail;
224 }
225
226 device->local_fd = fd;
227 device->ws->query_info(device->ws, &device->rad_info);
228
229 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
230
231 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
232 device->ws->destroy(device->ws);
233 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
234 "cannot generate UUID");
235 goto fail;
236 }
237
238 /* These flags affect shader compilation. */
239 uint64_t shader_env_flags =
240 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
241 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
242
243 /* The gpu id is already embeded in the uuid so we just pass "radv"
244 * when creating the cache.
245 */
246 char buf[VK_UUID_SIZE * 2 + 1];
247 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
248 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
249
250 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
251
252 radv_get_driver_uuid(&device->device_uuid);
253 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
254
255 if (device->rad_info.family == CHIP_STONEY ||
256 device->rad_info.chip_class >= GFX9) {
257 device->has_rbplus = true;
258 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
259 }
260
261 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
262 * on SI.
263 */
264 device->has_clear_state = device->rad_info.chip_class >= CIK;
265
266 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
267
268 /* Vega10/Raven need a special workaround for a hardware bug. */
269 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
270 device->rad_info.family == CHIP_RAVEN;
271
272 radv_physical_device_init_mem_types(device);
273
274 result = radv_init_wsi(device);
275 if (result != VK_SUCCESS) {
276 device->ws->destroy(device->ws);
277 goto fail;
278 }
279
280 return VK_SUCCESS;
281
282 fail:
283 close(fd);
284 return result;
285 }
286
287 static void
288 radv_physical_device_finish(struct radv_physical_device *device)
289 {
290 radv_finish_wsi(device);
291 device->ws->destroy(device->ws);
292 disk_cache_destroy(device->disk_cache);
293 close(device->local_fd);
294 }
295
296 static void *
297 default_alloc_func(void *pUserData, size_t size, size_t align,
298 VkSystemAllocationScope allocationScope)
299 {
300 return malloc(size);
301 }
302
303 static void *
304 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
305 size_t align, VkSystemAllocationScope allocationScope)
306 {
307 return realloc(pOriginal, size);
308 }
309
310 static void
311 default_free_func(void *pUserData, void *pMemory)
312 {
313 free(pMemory);
314 }
315
316 static const VkAllocationCallbacks default_alloc = {
317 .pUserData = NULL,
318 .pfnAllocation = default_alloc_func,
319 .pfnReallocation = default_realloc_func,
320 .pfnFree = default_free_func,
321 };
322
323 static const struct debug_control radv_debug_options[] = {
324 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
325 {"nodcc", RADV_DEBUG_NO_DCC},
326 {"shaders", RADV_DEBUG_DUMP_SHADERS},
327 {"nocache", RADV_DEBUG_NO_CACHE},
328 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
329 {"nohiz", RADV_DEBUG_NO_HIZ},
330 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
331 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
332 {"allbos", RADV_DEBUG_ALL_BOS},
333 {"noibs", RADV_DEBUG_NO_IBS},
334 {"spirv", RADV_DEBUG_DUMP_SPIRV},
335 {"vmfaults", RADV_DEBUG_VM_FAULTS},
336 {"zerovram", RADV_DEBUG_ZERO_VRAM},
337 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
338 {"nosisched", RADV_DEBUG_NO_SISCHED},
339 {NULL, 0}
340 };
341
342 const char *
343 radv_get_debug_option_name(int id)
344 {
345 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
346 return radv_debug_options[id].string;
347 }
348
349 static const struct debug_control radv_perftest_options[] = {
350 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
351 {"sisched", RADV_PERFTEST_SISCHED},
352 {"localbos", RADV_PERFTEST_LOCAL_BOS},
353 {"binning", RADV_PERFTEST_BINNING},
354 {NULL, 0}
355 };
356
357 const char *
358 radv_get_perftest_option_name(int id)
359 {
360 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
361 return radv_perftest_options[id].string;
362 }
363
364 static void
365 radv_handle_per_app_options(struct radv_instance *instance,
366 const VkApplicationInfo *info)
367 {
368 const char *name = info ? info->pApplicationName : NULL;
369
370 if (!name)
371 return;
372
373 if (!strcmp(name, "Talos - Linux - 32bit") ||
374 !strcmp(name, "Talos - Linux - 64bit")) {
375 /* Force enable LLVM sisched for Talos because it looks safe
376 * and it gives few more FPS.
377 */
378 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
379 }
380 }
381
382 VkResult radv_CreateInstance(
383 const VkInstanceCreateInfo* pCreateInfo,
384 const VkAllocationCallbacks* pAllocator,
385 VkInstance* pInstance)
386 {
387 struct radv_instance *instance;
388
389 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
390
391 uint32_t client_version;
392 if (pCreateInfo->pApplicationInfo &&
393 pCreateInfo->pApplicationInfo->apiVersion != 0) {
394 client_version = pCreateInfo->pApplicationInfo->apiVersion;
395 } else {
396 client_version = VK_MAKE_VERSION(1, 0, 0);
397 }
398
399 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
400 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
401 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
402 "Client requested version %d.%d.%d",
403 VK_VERSION_MAJOR(client_version),
404 VK_VERSION_MINOR(client_version),
405 VK_VERSION_PATCH(client_version));
406 }
407
408 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
409 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
410 if (!radv_instance_extension_supported(ext_name))
411 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
412 }
413
414 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
415 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
416 if (!instance)
417 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
418
419 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
420
421 if (pAllocator)
422 instance->alloc = *pAllocator;
423 else
424 instance->alloc = default_alloc;
425
426 instance->apiVersion = client_version;
427 instance->physicalDeviceCount = -1;
428
429 _mesa_locale_init();
430
431 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
432
433 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
434 radv_debug_options);
435
436 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
437 radv_perftest_options);
438
439 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
440
441 if (instance->debug_flags & RADV_DEBUG_NO_SISCHED) {
442 /* Disable sisched when the user requests it, this is mostly
443 * useful when the driver force-enable sisched for the given
444 * application.
445 */
446 instance->perftest_flags &= ~RADV_PERFTEST_SISCHED;
447 }
448
449 *pInstance = radv_instance_to_handle(instance);
450
451 return VK_SUCCESS;
452 }
453
454 void radv_DestroyInstance(
455 VkInstance _instance,
456 const VkAllocationCallbacks* pAllocator)
457 {
458 RADV_FROM_HANDLE(radv_instance, instance, _instance);
459
460 if (!instance)
461 return;
462
463 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
464 radv_physical_device_finish(instance->physicalDevices + i);
465 }
466
467 VG(VALGRIND_DESTROY_MEMPOOL(instance));
468
469 _mesa_locale_fini();
470
471 vk_free(&instance->alloc, instance);
472 }
473
474 static VkResult
475 radv_enumerate_devices(struct radv_instance *instance)
476 {
477 /* TODO: Check for more devices ? */
478 drmDevicePtr devices[8];
479 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
480 int max_devices;
481
482 instance->physicalDeviceCount = 0;
483
484 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
485 if (max_devices < 1)
486 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
487
488 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
489 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
490 devices[i]->bustype == DRM_BUS_PCI &&
491 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
492
493 result = radv_physical_device_init(instance->physicalDevices +
494 instance->physicalDeviceCount,
495 instance,
496 devices[i]);
497 if (result == VK_SUCCESS)
498 ++instance->physicalDeviceCount;
499 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
500 break;
501 }
502 }
503 drmFreeDevices(devices, max_devices);
504
505 return result;
506 }
507
508 VkResult radv_EnumeratePhysicalDevices(
509 VkInstance _instance,
510 uint32_t* pPhysicalDeviceCount,
511 VkPhysicalDevice* pPhysicalDevices)
512 {
513 RADV_FROM_HANDLE(radv_instance, instance, _instance);
514 VkResult result;
515
516 if (instance->physicalDeviceCount < 0) {
517 result = radv_enumerate_devices(instance);
518 if (result != VK_SUCCESS &&
519 result != VK_ERROR_INCOMPATIBLE_DRIVER)
520 return result;
521 }
522
523 if (!pPhysicalDevices) {
524 *pPhysicalDeviceCount = instance->physicalDeviceCount;
525 } else {
526 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
527 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
528 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
529 }
530
531 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
532 : VK_SUCCESS;
533 }
534
535 void radv_GetPhysicalDeviceFeatures(
536 VkPhysicalDevice physicalDevice,
537 VkPhysicalDeviceFeatures* pFeatures)
538 {
539 memset(pFeatures, 0, sizeof(*pFeatures));
540
541 *pFeatures = (VkPhysicalDeviceFeatures) {
542 .robustBufferAccess = true,
543 .fullDrawIndexUint32 = true,
544 .imageCubeArray = true,
545 .independentBlend = true,
546 .geometryShader = true,
547 .tessellationShader = true,
548 .sampleRateShading = true,
549 .dualSrcBlend = true,
550 .logicOp = true,
551 .multiDrawIndirect = true,
552 .drawIndirectFirstInstance = true,
553 .depthClamp = true,
554 .depthBiasClamp = true,
555 .fillModeNonSolid = true,
556 .depthBounds = true,
557 .wideLines = true,
558 .largePoints = true,
559 .alphaToOne = true,
560 .multiViewport = true,
561 .samplerAnisotropy = true,
562 .textureCompressionETC2 = false,
563 .textureCompressionASTC_LDR = false,
564 .textureCompressionBC = true,
565 .occlusionQueryPrecise = true,
566 .pipelineStatisticsQuery = true,
567 .vertexPipelineStoresAndAtomics = true,
568 .fragmentStoresAndAtomics = true,
569 .shaderTessellationAndGeometryPointSize = true,
570 .shaderImageGatherExtended = true,
571 .shaderStorageImageExtendedFormats = true,
572 .shaderStorageImageMultisample = false,
573 .shaderUniformBufferArrayDynamicIndexing = true,
574 .shaderSampledImageArrayDynamicIndexing = true,
575 .shaderStorageBufferArrayDynamicIndexing = true,
576 .shaderStorageImageArrayDynamicIndexing = true,
577 .shaderStorageImageReadWithoutFormat = true,
578 .shaderStorageImageWriteWithoutFormat = true,
579 .shaderClipDistance = true,
580 .shaderCullDistance = true,
581 .shaderFloat64 = true,
582 .shaderInt64 = true,
583 .shaderInt16 = false,
584 .sparseBinding = true,
585 .variableMultisampleRate = true,
586 .inheritedQueries = true,
587 };
588 }
589
590 void radv_GetPhysicalDeviceFeatures2KHR(
591 VkPhysicalDevice physicalDevice,
592 VkPhysicalDeviceFeatures2KHR *pFeatures)
593 {
594 vk_foreach_struct(ext, pFeatures->pNext) {
595 switch (ext->sType) {
596 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
597 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
598 features->variablePointersStorageBuffer = true;
599 features->variablePointers = false;
600 break;
601 }
602 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX: {
603 VkPhysicalDeviceMultiviewFeaturesKHX *features = (VkPhysicalDeviceMultiviewFeaturesKHX*)ext;
604 features->multiview = true;
605 features->multiviewGeometryShader = true;
606 features->multiviewTessellationShader = true;
607 break;
608 }
609 default:
610 break;
611 }
612 }
613 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
614 }
615
616 void radv_GetPhysicalDeviceProperties(
617 VkPhysicalDevice physicalDevice,
618 VkPhysicalDeviceProperties* pProperties)
619 {
620 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
621 VkSampleCountFlags sample_counts = 0xf;
622
623 /* make sure that the entire descriptor set is addressable with a signed
624 * 32-bit int. So the sum of all limits scaled by descriptor size has to
625 * be at most 2 GiB. the combined image & samples object count as one of
626 * both. This limit is for the pipeline layout, not for the set layout, but
627 * there is no set limit, so we just set a pipeline limit. I don't think
628 * any app is going to hit this soon. */
629 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
630 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
631 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
632 32 /* sampler, largest when combined with image */ +
633 64 /* sampled image */ +
634 64 /* storage image */);
635
636 VkPhysicalDeviceLimits limits = {
637 .maxImageDimension1D = (1 << 14),
638 .maxImageDimension2D = (1 << 14),
639 .maxImageDimension3D = (1 << 11),
640 .maxImageDimensionCube = (1 << 14),
641 .maxImageArrayLayers = (1 << 11),
642 .maxTexelBufferElements = 128 * 1024 * 1024,
643 .maxUniformBufferRange = UINT32_MAX,
644 .maxStorageBufferRange = UINT32_MAX,
645 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
646 .maxMemoryAllocationCount = UINT32_MAX,
647 .maxSamplerAllocationCount = 64 * 1024,
648 .bufferImageGranularity = 64, /* A cache line */
649 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
650 .maxBoundDescriptorSets = MAX_SETS,
651 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
652 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
653 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
654 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
655 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
656 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
657 .maxPerStageResources = max_descriptor_set_size,
658 .maxDescriptorSetSamplers = max_descriptor_set_size,
659 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
660 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
661 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
662 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
663 .maxDescriptorSetSampledImages = max_descriptor_set_size,
664 .maxDescriptorSetStorageImages = max_descriptor_set_size,
665 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
666 .maxVertexInputAttributes = 32,
667 .maxVertexInputBindings = 32,
668 .maxVertexInputAttributeOffset = 2047,
669 .maxVertexInputBindingStride = 2048,
670 .maxVertexOutputComponents = 128,
671 .maxTessellationGenerationLevel = 64,
672 .maxTessellationPatchSize = 32,
673 .maxTessellationControlPerVertexInputComponents = 128,
674 .maxTessellationControlPerVertexOutputComponents = 128,
675 .maxTessellationControlPerPatchOutputComponents = 120,
676 .maxTessellationControlTotalOutputComponents = 4096,
677 .maxTessellationEvaluationInputComponents = 128,
678 .maxTessellationEvaluationOutputComponents = 128,
679 .maxGeometryShaderInvocations = 127,
680 .maxGeometryInputComponents = 64,
681 .maxGeometryOutputComponents = 128,
682 .maxGeometryOutputVertices = 256,
683 .maxGeometryTotalOutputComponents = 1024,
684 .maxFragmentInputComponents = 128,
685 .maxFragmentOutputAttachments = 8,
686 .maxFragmentDualSrcAttachments = 1,
687 .maxFragmentCombinedOutputResources = 8,
688 .maxComputeSharedMemorySize = 32768,
689 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
690 .maxComputeWorkGroupInvocations = 2048,
691 .maxComputeWorkGroupSize = {
692 2048,
693 2048,
694 2048
695 },
696 .subPixelPrecisionBits = 4 /* FIXME */,
697 .subTexelPrecisionBits = 4 /* FIXME */,
698 .mipmapPrecisionBits = 4 /* FIXME */,
699 .maxDrawIndexedIndexValue = UINT32_MAX,
700 .maxDrawIndirectCount = UINT32_MAX,
701 .maxSamplerLodBias = 16,
702 .maxSamplerAnisotropy = 16,
703 .maxViewports = MAX_VIEWPORTS,
704 .maxViewportDimensions = { (1 << 14), (1 << 14) },
705 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
706 .viewportSubPixelBits = 13, /* We take a float? */
707 .minMemoryMapAlignment = 4096, /* A page */
708 .minTexelBufferOffsetAlignment = 1,
709 .minUniformBufferOffsetAlignment = 4,
710 .minStorageBufferOffsetAlignment = 4,
711 .minTexelOffset = -32,
712 .maxTexelOffset = 31,
713 .minTexelGatherOffset = -32,
714 .maxTexelGatherOffset = 31,
715 .minInterpolationOffset = -2,
716 .maxInterpolationOffset = 2,
717 .subPixelInterpolationOffsetBits = 8,
718 .maxFramebufferWidth = (1 << 14),
719 .maxFramebufferHeight = (1 << 14),
720 .maxFramebufferLayers = (1 << 10),
721 .framebufferColorSampleCounts = sample_counts,
722 .framebufferDepthSampleCounts = sample_counts,
723 .framebufferStencilSampleCounts = sample_counts,
724 .framebufferNoAttachmentsSampleCounts = sample_counts,
725 .maxColorAttachments = MAX_RTS,
726 .sampledImageColorSampleCounts = sample_counts,
727 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
728 .sampledImageDepthSampleCounts = sample_counts,
729 .sampledImageStencilSampleCounts = sample_counts,
730 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
731 .maxSampleMaskWords = 1,
732 .timestampComputeAndGraphics = true,
733 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
734 .maxClipDistances = 8,
735 .maxCullDistances = 8,
736 .maxCombinedClipAndCullDistances = 8,
737 .discreteQueuePriorities = 1,
738 .pointSizeRange = { 0.125, 255.875 },
739 .lineWidthRange = { 0.0, 7.9921875 },
740 .pointSizeGranularity = (1.0 / 8.0),
741 .lineWidthGranularity = (1.0 / 128.0),
742 .strictLines = false, /* FINISHME */
743 .standardSampleLocations = true,
744 .optimalBufferCopyOffsetAlignment = 128,
745 .optimalBufferCopyRowPitchAlignment = 128,
746 .nonCoherentAtomSize = 64,
747 };
748
749 *pProperties = (VkPhysicalDeviceProperties) {
750 .apiVersion = radv_physical_device_api_version(pdevice),
751 .driverVersion = vk_get_driver_version(),
752 .vendorID = ATI_VENDOR_ID,
753 .deviceID = pdevice->rad_info.pci_id,
754 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
755 .limits = limits,
756 .sparseProperties = {0},
757 };
758
759 strcpy(pProperties->deviceName, pdevice->name);
760 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
761 }
762
763 void radv_GetPhysicalDeviceProperties2KHR(
764 VkPhysicalDevice physicalDevice,
765 VkPhysicalDeviceProperties2KHR *pProperties)
766 {
767 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
768 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
769
770 vk_foreach_struct(ext, pProperties->pNext) {
771 switch (ext->sType) {
772 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
773 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
774 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
775 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
776 break;
777 }
778 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
779 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
780 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
781 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
782 properties->deviceLUIDValid = false;
783 break;
784 }
785 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX: {
786 VkPhysicalDeviceMultiviewPropertiesKHX *properties = (VkPhysicalDeviceMultiviewPropertiesKHX*)ext;
787 properties->maxMultiviewViewCount = MAX_VIEWS;
788 properties->maxMultiviewInstanceIndex = INT_MAX;
789 break;
790 }
791 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
792 VkPhysicalDevicePointClippingPropertiesKHR *properties =
793 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
794 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
795 break;
796 }
797 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
798 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
799 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
800 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
801 break;
802 }
803 default:
804 break;
805 }
806 }
807 }
808
809 static void radv_get_physical_device_queue_family_properties(
810 struct radv_physical_device* pdevice,
811 uint32_t* pCount,
812 VkQueueFamilyProperties** pQueueFamilyProperties)
813 {
814 int num_queue_families = 1;
815 int idx;
816 if (pdevice->rad_info.num_compute_rings > 0 &&
817 pdevice->rad_info.chip_class >= CIK &&
818 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
819 num_queue_families++;
820
821 if (pQueueFamilyProperties == NULL) {
822 *pCount = num_queue_families;
823 return;
824 }
825
826 if (!*pCount)
827 return;
828
829 idx = 0;
830 if (*pCount >= 1) {
831 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
832 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
833 VK_QUEUE_COMPUTE_BIT |
834 VK_QUEUE_TRANSFER_BIT |
835 VK_QUEUE_SPARSE_BINDING_BIT,
836 .queueCount = 1,
837 .timestampValidBits = 64,
838 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
839 };
840 idx++;
841 }
842
843 if (pdevice->rad_info.num_compute_rings > 0 &&
844 pdevice->rad_info.chip_class >= CIK &&
845 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
846 if (*pCount > idx) {
847 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
848 .queueFlags = VK_QUEUE_COMPUTE_BIT |
849 VK_QUEUE_TRANSFER_BIT |
850 VK_QUEUE_SPARSE_BINDING_BIT,
851 .queueCount = pdevice->rad_info.num_compute_rings,
852 .timestampValidBits = 64,
853 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
854 };
855 idx++;
856 }
857 }
858 *pCount = idx;
859 }
860
861 void radv_GetPhysicalDeviceQueueFamilyProperties(
862 VkPhysicalDevice physicalDevice,
863 uint32_t* pCount,
864 VkQueueFamilyProperties* pQueueFamilyProperties)
865 {
866 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
867 if (!pQueueFamilyProperties) {
868 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
869 return;
870 }
871 VkQueueFamilyProperties *properties[] = {
872 pQueueFamilyProperties + 0,
873 pQueueFamilyProperties + 1,
874 pQueueFamilyProperties + 2,
875 };
876 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
877 assert(*pCount <= 3);
878 }
879
880 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
881 VkPhysicalDevice physicalDevice,
882 uint32_t* pCount,
883 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
884 {
885 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
886 if (!pQueueFamilyProperties) {
887 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
888 return;
889 }
890 VkQueueFamilyProperties *properties[] = {
891 &pQueueFamilyProperties[0].queueFamilyProperties,
892 &pQueueFamilyProperties[1].queueFamilyProperties,
893 &pQueueFamilyProperties[2].queueFamilyProperties,
894 };
895 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
896 assert(*pCount <= 3);
897 }
898
899 void radv_GetPhysicalDeviceMemoryProperties(
900 VkPhysicalDevice physicalDevice,
901 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
902 {
903 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
904
905 *pMemoryProperties = physical_device->memory_properties;
906 }
907
908 void radv_GetPhysicalDeviceMemoryProperties2KHR(
909 VkPhysicalDevice physicalDevice,
910 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
911 {
912 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
913 &pMemoryProperties->memoryProperties);
914 }
915
916 static enum radeon_ctx_priority
917 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
918 {
919 /* Default to MEDIUM when a specific global priority isn't requested */
920 if (!pObj)
921 return RADEON_CTX_PRIORITY_MEDIUM;
922
923 switch(pObj->globalPriority) {
924 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
925 return RADEON_CTX_PRIORITY_REALTIME;
926 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
927 return RADEON_CTX_PRIORITY_HIGH;
928 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
929 return RADEON_CTX_PRIORITY_MEDIUM;
930 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
931 return RADEON_CTX_PRIORITY_LOW;
932 default:
933 unreachable("Illegal global priority value");
934 return RADEON_CTX_PRIORITY_INVALID;
935 }
936 }
937
938 static int
939 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
940 uint32_t queue_family_index, int idx,
941 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
942 {
943 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
944 queue->device = device;
945 queue->queue_family_index = queue_family_index;
946 queue->queue_idx = idx;
947 queue->priority = radv_get_queue_global_priority(global_priority);
948
949 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
950 if (!queue->hw_ctx)
951 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
952
953 return VK_SUCCESS;
954 }
955
956 static void
957 radv_queue_finish(struct radv_queue *queue)
958 {
959 if (queue->hw_ctx)
960 queue->device->ws->ctx_destroy(queue->hw_ctx);
961
962 if (queue->initial_full_flush_preamble_cs)
963 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
964 if (queue->initial_preamble_cs)
965 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
966 if (queue->continue_preamble_cs)
967 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
968 if (queue->descriptor_bo)
969 queue->device->ws->buffer_destroy(queue->descriptor_bo);
970 if (queue->scratch_bo)
971 queue->device->ws->buffer_destroy(queue->scratch_bo);
972 if (queue->esgs_ring_bo)
973 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
974 if (queue->gsvs_ring_bo)
975 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
976 if (queue->tess_factor_ring_bo)
977 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
978 if (queue->tess_offchip_ring_bo)
979 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
980 if (queue->compute_scratch_bo)
981 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
982 }
983
984 static void
985 radv_device_init_gs_info(struct radv_device *device)
986 {
987 switch (device->physical_device->rad_info.family) {
988 case CHIP_OLAND:
989 case CHIP_HAINAN:
990 case CHIP_KAVERI:
991 case CHIP_KABINI:
992 case CHIP_MULLINS:
993 case CHIP_ICELAND:
994 case CHIP_CARRIZO:
995 case CHIP_STONEY:
996 device->gs_table_depth = 16;
997 return;
998 case CHIP_TAHITI:
999 case CHIP_PITCAIRN:
1000 case CHIP_VERDE:
1001 case CHIP_BONAIRE:
1002 case CHIP_HAWAII:
1003 case CHIP_TONGA:
1004 case CHIP_FIJI:
1005 case CHIP_POLARIS10:
1006 case CHIP_POLARIS11:
1007 case CHIP_POLARIS12:
1008 case CHIP_VEGA10:
1009 case CHIP_RAVEN:
1010 device->gs_table_depth = 32;
1011 return;
1012 default:
1013 unreachable("unknown GPU");
1014 }
1015 }
1016
1017 VkResult radv_CreateDevice(
1018 VkPhysicalDevice physicalDevice,
1019 const VkDeviceCreateInfo* pCreateInfo,
1020 const VkAllocationCallbacks* pAllocator,
1021 VkDevice* pDevice)
1022 {
1023 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1024 VkResult result;
1025 struct radv_device *device;
1026
1027 bool keep_shader_info = false;
1028
1029 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1030 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1031 if (!radv_physical_device_extension_supported(physical_device, ext_name))
1032 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1033
1034 if (strcmp(ext_name, VK_AMD_SHADER_INFO_EXTENSION_NAME) == 0)
1035 keep_shader_info = true;
1036 }
1037
1038 /* Check enabled features */
1039 if (pCreateInfo->pEnabledFeatures) {
1040 VkPhysicalDeviceFeatures supported_features;
1041 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1042 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1043 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1044 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1045 for (uint32_t i = 0; i < num_features; i++) {
1046 if (enabled_feature[i] && !supported_feature[i])
1047 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1048 }
1049 }
1050
1051 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1052 sizeof(*device), 8,
1053 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1054 if (!device)
1055 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1056
1057 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1058 device->instance = physical_device->instance;
1059 device->physical_device = physical_device;
1060
1061 device->ws = physical_device->ws;
1062 if (pAllocator)
1063 device->alloc = *pAllocator;
1064 else
1065 device->alloc = physical_device->instance->alloc;
1066
1067 mtx_init(&device->shader_slab_mutex, mtx_plain);
1068 list_inithead(&device->shader_slabs);
1069
1070 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1071 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1072 uint32_t qfi = queue_create->queueFamilyIndex;
1073 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1074 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1075
1076 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1077
1078 device->queues[qfi] = vk_alloc(&device->alloc,
1079 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1080 if (!device->queues[qfi]) {
1081 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1082 goto fail;
1083 }
1084
1085 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1086
1087 device->queue_count[qfi] = queue_create->queueCount;
1088
1089 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1090 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q, global_priority);
1091 if (result != VK_SUCCESS)
1092 goto fail;
1093 }
1094 }
1095
1096 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1097 (device->instance->perftest_flags & RADV_PERFTEST_BINNING);
1098
1099 /* Disabled and not implemented for now. */
1100 device->dfsm_allowed = device->pbb_allowed && false;
1101
1102
1103 #if HAVE_LLVM < 0x0400
1104 device->llvm_supports_spill = false;
1105 #else
1106 device->llvm_supports_spill = true;
1107 #endif
1108
1109 /* The maximum number of scratch waves. Scratch space isn't divided
1110 * evenly between CUs. The number is only a function of the number of CUs.
1111 * We can decrease the constant to decrease the scratch buffer size.
1112 *
1113 * sctx->scratch_waves must be >= the maximum posible size of
1114 * 1 threadgroup, so that the hw doesn't hang from being unable
1115 * to start any.
1116 *
1117 * The recommended value is 4 per CU at most. Higher numbers don't
1118 * bring much benefit, but they still occupy chip resources (think
1119 * async compute). I've seen ~2% performance difference between 4 and 32.
1120 */
1121 uint32_t max_threads_per_block = 2048;
1122 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1123 max_threads_per_block / 64);
1124
1125 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
1126 S_00B800_FORCE_START_AT_000(1);
1127
1128 if (device->physical_device->rad_info.chip_class >= CIK) {
1129 /* If the KMD allows it (there is a KMD hw register for it),
1130 * allow launching waves out-of-order.
1131 */
1132 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1133 }
1134
1135 radv_device_init_gs_info(device);
1136
1137 device->tess_offchip_block_dw_size =
1138 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1139 device->has_distributed_tess =
1140 device->physical_device->rad_info.chip_class >= VI &&
1141 device->physical_device->rad_info.max_se >= 2;
1142
1143 if (getenv("RADV_TRACE_FILE")) {
1144 keep_shader_info = true;
1145
1146 if (!radv_init_trace(device))
1147 goto fail;
1148 }
1149
1150 device->keep_shader_info = keep_shader_info;
1151
1152 result = radv_device_init_meta(device);
1153 if (result != VK_SUCCESS)
1154 goto fail;
1155
1156 radv_device_init_msaa(device);
1157
1158 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1159 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1160 switch (family) {
1161 case RADV_QUEUE_GENERAL:
1162 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1163 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1164 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1165 break;
1166 case RADV_QUEUE_COMPUTE:
1167 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1168 radeon_emit(device->empty_cs[family], 0);
1169 break;
1170 }
1171 device->ws->cs_finalize(device->empty_cs[family]);
1172 }
1173
1174 if (device->physical_device->rad_info.chip_class >= CIK)
1175 cik_create_gfx_config(device);
1176
1177 VkPipelineCacheCreateInfo ci;
1178 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1179 ci.pNext = NULL;
1180 ci.flags = 0;
1181 ci.pInitialData = NULL;
1182 ci.initialDataSize = 0;
1183 VkPipelineCache pc;
1184 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1185 &ci, NULL, &pc);
1186 if (result != VK_SUCCESS)
1187 goto fail;
1188
1189 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1190
1191 *pDevice = radv_device_to_handle(device);
1192 return VK_SUCCESS;
1193
1194 fail:
1195 if (device->trace_bo)
1196 device->ws->buffer_destroy(device->trace_bo);
1197
1198 if (device->gfx_init)
1199 device->ws->buffer_destroy(device->gfx_init);
1200
1201 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1202 for (unsigned q = 0; q < device->queue_count[i]; q++)
1203 radv_queue_finish(&device->queues[i][q]);
1204 if (device->queue_count[i])
1205 vk_free(&device->alloc, device->queues[i]);
1206 }
1207
1208 vk_free(&device->alloc, device);
1209 return result;
1210 }
1211
1212 void radv_DestroyDevice(
1213 VkDevice _device,
1214 const VkAllocationCallbacks* pAllocator)
1215 {
1216 RADV_FROM_HANDLE(radv_device, device, _device);
1217
1218 if (!device)
1219 return;
1220
1221 if (device->trace_bo)
1222 device->ws->buffer_destroy(device->trace_bo);
1223
1224 if (device->gfx_init)
1225 device->ws->buffer_destroy(device->gfx_init);
1226
1227 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1228 for (unsigned q = 0; q < device->queue_count[i]; q++)
1229 radv_queue_finish(&device->queues[i][q]);
1230 if (device->queue_count[i])
1231 vk_free(&device->alloc, device->queues[i]);
1232 if (device->empty_cs[i])
1233 device->ws->cs_destroy(device->empty_cs[i]);
1234 }
1235 radv_device_finish_meta(device);
1236
1237 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1238 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1239
1240 radv_destroy_shader_slabs(device);
1241
1242 vk_free(&device->alloc, device);
1243 }
1244
1245 VkResult radv_EnumerateInstanceLayerProperties(
1246 uint32_t* pPropertyCount,
1247 VkLayerProperties* pProperties)
1248 {
1249 if (pProperties == NULL) {
1250 *pPropertyCount = 0;
1251 return VK_SUCCESS;
1252 }
1253
1254 /* None supported at this time */
1255 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1256 }
1257
1258 VkResult radv_EnumerateDeviceLayerProperties(
1259 VkPhysicalDevice physicalDevice,
1260 uint32_t* pPropertyCount,
1261 VkLayerProperties* pProperties)
1262 {
1263 if (pProperties == NULL) {
1264 *pPropertyCount = 0;
1265 return VK_SUCCESS;
1266 }
1267
1268 /* None supported at this time */
1269 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1270 }
1271
1272 void radv_GetDeviceQueue(
1273 VkDevice _device,
1274 uint32_t queueFamilyIndex,
1275 uint32_t queueIndex,
1276 VkQueue* pQueue)
1277 {
1278 RADV_FROM_HANDLE(radv_device, device, _device);
1279
1280 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1281 }
1282
1283 static void
1284 fill_geom_tess_rings(struct radv_queue *queue,
1285 uint32_t *map,
1286 bool add_sample_positions,
1287 uint32_t esgs_ring_size,
1288 struct radeon_winsys_bo *esgs_ring_bo,
1289 uint32_t gsvs_ring_size,
1290 struct radeon_winsys_bo *gsvs_ring_bo,
1291 uint32_t tess_factor_ring_size,
1292 struct radeon_winsys_bo *tess_factor_ring_bo,
1293 uint32_t tess_offchip_ring_size,
1294 struct radeon_winsys_bo *tess_offchip_ring_bo)
1295 {
1296 uint64_t esgs_va = 0, gsvs_va = 0;
1297 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1298 uint32_t *desc = &map[4];
1299
1300 if (esgs_ring_bo)
1301 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1302 if (gsvs_ring_bo)
1303 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1304 if (tess_factor_ring_bo)
1305 tess_factor_va = radv_buffer_get_va(tess_factor_ring_bo);
1306 if (tess_offchip_ring_bo)
1307 tess_offchip_va = radv_buffer_get_va(tess_offchip_ring_bo);
1308
1309 /* stride 0, num records - size, add tid, swizzle, elsize4,
1310 index stride 64 */
1311 desc[0] = esgs_va;
1312 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1313 S_008F04_STRIDE(0) |
1314 S_008F04_SWIZZLE_ENABLE(true);
1315 desc[2] = esgs_ring_size;
1316 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1317 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1318 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1319 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1320 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1321 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1322 S_008F0C_ELEMENT_SIZE(1) |
1323 S_008F0C_INDEX_STRIDE(3) |
1324 S_008F0C_ADD_TID_ENABLE(true);
1325
1326 desc += 4;
1327 /* GS entry for ES->GS ring */
1328 /* stride 0, num records - size, elsize0,
1329 index stride 0 */
1330 desc[0] = esgs_va;
1331 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1332 S_008F04_STRIDE(0) |
1333 S_008F04_SWIZZLE_ENABLE(false);
1334 desc[2] = esgs_ring_size;
1335 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1336 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1337 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1338 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1339 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1340 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1341 S_008F0C_ELEMENT_SIZE(0) |
1342 S_008F0C_INDEX_STRIDE(0) |
1343 S_008F0C_ADD_TID_ENABLE(false);
1344
1345 desc += 4;
1346 /* VS entry for GS->VS ring */
1347 /* stride 0, num records - size, elsize0,
1348 index stride 0 */
1349 desc[0] = gsvs_va;
1350 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1351 S_008F04_STRIDE(0) |
1352 S_008F04_SWIZZLE_ENABLE(false);
1353 desc[2] = gsvs_ring_size;
1354 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1355 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1356 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1357 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1358 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1359 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1360 S_008F0C_ELEMENT_SIZE(0) |
1361 S_008F0C_INDEX_STRIDE(0) |
1362 S_008F0C_ADD_TID_ENABLE(false);
1363 desc += 4;
1364
1365 /* stride gsvs_itemsize, num records 64
1366 elsize 4, index stride 16 */
1367 /* shader will patch stride and desc[2] */
1368 desc[0] = gsvs_va;
1369 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1370 S_008F04_STRIDE(0) |
1371 S_008F04_SWIZZLE_ENABLE(true);
1372 desc[2] = 0;
1373 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1374 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1375 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1376 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1377 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1378 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1379 S_008F0C_ELEMENT_SIZE(1) |
1380 S_008F0C_INDEX_STRIDE(1) |
1381 S_008F0C_ADD_TID_ENABLE(true);
1382 desc += 4;
1383
1384 desc[0] = tess_factor_va;
1385 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1386 S_008F04_STRIDE(0) |
1387 S_008F04_SWIZZLE_ENABLE(false);
1388 desc[2] = tess_factor_ring_size;
1389 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1390 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1391 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1392 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1393 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1394 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1395 S_008F0C_ELEMENT_SIZE(0) |
1396 S_008F0C_INDEX_STRIDE(0) |
1397 S_008F0C_ADD_TID_ENABLE(false);
1398 desc += 4;
1399
1400 desc[0] = tess_offchip_va;
1401 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1402 S_008F04_STRIDE(0) |
1403 S_008F04_SWIZZLE_ENABLE(false);
1404 desc[2] = tess_offchip_ring_size;
1405 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1406 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1407 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1408 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1409 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1410 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1411 S_008F0C_ELEMENT_SIZE(0) |
1412 S_008F0C_INDEX_STRIDE(0) |
1413 S_008F0C_ADD_TID_ENABLE(false);
1414 desc += 4;
1415
1416 /* add sample positions after all rings */
1417 memcpy(desc, queue->device->sample_locations_1x, 8);
1418 desc += 2;
1419 memcpy(desc, queue->device->sample_locations_2x, 16);
1420 desc += 4;
1421 memcpy(desc, queue->device->sample_locations_4x, 32);
1422 desc += 8;
1423 memcpy(desc, queue->device->sample_locations_8x, 64);
1424 desc += 16;
1425 memcpy(desc, queue->device->sample_locations_16x, 128);
1426 }
1427
1428 static unsigned
1429 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1430 {
1431 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1432 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1433 device->physical_device->rad_info.family != CHIP_STONEY;
1434 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1435 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1436 device->physical_device->rad_info.max_se;
1437 unsigned offchip_granularity;
1438 unsigned hs_offchip_param;
1439 switch (device->tess_offchip_block_dw_size) {
1440 default:
1441 assert(0);
1442 /* fall through */
1443 case 8192:
1444 offchip_granularity = V_03093C_X_8K_DWORDS;
1445 break;
1446 case 4096:
1447 offchip_granularity = V_03093C_X_4K_DWORDS;
1448 break;
1449 }
1450
1451 switch (device->physical_device->rad_info.chip_class) {
1452 case SI:
1453 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1454 break;
1455 case CIK:
1456 case VI:
1457 case GFX9:
1458 default:
1459 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1460 break;
1461 }
1462
1463 *max_offchip_buffers_p = max_offchip_buffers;
1464 if (device->physical_device->rad_info.chip_class >= CIK) {
1465 if (device->physical_device->rad_info.chip_class >= VI)
1466 --max_offchip_buffers;
1467 hs_offchip_param =
1468 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1469 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1470 } else {
1471 hs_offchip_param =
1472 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1473 }
1474 return hs_offchip_param;
1475 }
1476
1477 static VkResult
1478 radv_get_preamble_cs(struct radv_queue *queue,
1479 uint32_t scratch_size,
1480 uint32_t compute_scratch_size,
1481 uint32_t esgs_ring_size,
1482 uint32_t gsvs_ring_size,
1483 bool needs_tess_rings,
1484 bool needs_sample_positions,
1485 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1486 struct radeon_winsys_cs **initial_preamble_cs,
1487 struct radeon_winsys_cs **continue_preamble_cs)
1488 {
1489 struct radeon_winsys_bo *scratch_bo = NULL;
1490 struct radeon_winsys_bo *descriptor_bo = NULL;
1491 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1492 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1493 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1494 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1495 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1496 struct radeon_winsys_cs *dest_cs[3] = {0};
1497 bool add_tess_rings = false, add_sample_positions = false;
1498 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1499 unsigned max_offchip_buffers;
1500 unsigned hs_offchip_param = 0;
1501 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
1502 if (!queue->has_tess_rings) {
1503 if (needs_tess_rings)
1504 add_tess_rings = true;
1505 }
1506 if (!queue->has_sample_positions) {
1507 if (needs_sample_positions)
1508 add_sample_positions = true;
1509 }
1510 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1511 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1512 &max_offchip_buffers);
1513 tess_offchip_ring_size = max_offchip_buffers *
1514 queue->device->tess_offchip_block_dw_size * 4;
1515
1516 if (scratch_size <= queue->scratch_size &&
1517 compute_scratch_size <= queue->compute_scratch_size &&
1518 esgs_ring_size <= queue->esgs_ring_size &&
1519 gsvs_ring_size <= queue->gsvs_ring_size &&
1520 !add_tess_rings && !add_sample_positions &&
1521 queue->initial_preamble_cs) {
1522 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1523 *initial_preamble_cs = queue->initial_preamble_cs;
1524 *continue_preamble_cs = queue->continue_preamble_cs;
1525 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1526 *continue_preamble_cs = NULL;
1527 return VK_SUCCESS;
1528 }
1529
1530 if (scratch_size > queue->scratch_size) {
1531 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1532 scratch_size,
1533 4096,
1534 RADEON_DOMAIN_VRAM,
1535 ring_bo_flags);
1536 if (!scratch_bo)
1537 goto fail;
1538 } else
1539 scratch_bo = queue->scratch_bo;
1540
1541 if (compute_scratch_size > queue->compute_scratch_size) {
1542 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1543 compute_scratch_size,
1544 4096,
1545 RADEON_DOMAIN_VRAM,
1546 ring_bo_flags);
1547 if (!compute_scratch_bo)
1548 goto fail;
1549
1550 } else
1551 compute_scratch_bo = queue->compute_scratch_bo;
1552
1553 if (esgs_ring_size > queue->esgs_ring_size) {
1554 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1555 esgs_ring_size,
1556 4096,
1557 RADEON_DOMAIN_VRAM,
1558 ring_bo_flags);
1559 if (!esgs_ring_bo)
1560 goto fail;
1561 } else {
1562 esgs_ring_bo = queue->esgs_ring_bo;
1563 esgs_ring_size = queue->esgs_ring_size;
1564 }
1565
1566 if (gsvs_ring_size > queue->gsvs_ring_size) {
1567 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1568 gsvs_ring_size,
1569 4096,
1570 RADEON_DOMAIN_VRAM,
1571 ring_bo_flags);
1572 if (!gsvs_ring_bo)
1573 goto fail;
1574 } else {
1575 gsvs_ring_bo = queue->gsvs_ring_bo;
1576 gsvs_ring_size = queue->gsvs_ring_size;
1577 }
1578
1579 if (add_tess_rings) {
1580 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1581 tess_factor_ring_size,
1582 256,
1583 RADEON_DOMAIN_VRAM,
1584 ring_bo_flags);
1585 if (!tess_factor_ring_bo)
1586 goto fail;
1587 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1588 tess_offchip_ring_size,
1589 256,
1590 RADEON_DOMAIN_VRAM,
1591 ring_bo_flags);
1592 if (!tess_offchip_ring_bo)
1593 goto fail;
1594 } else {
1595 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1596 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1597 }
1598
1599 if (scratch_bo != queue->scratch_bo ||
1600 esgs_ring_bo != queue->esgs_ring_bo ||
1601 gsvs_ring_bo != queue->gsvs_ring_bo ||
1602 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1603 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1604 uint32_t size = 0;
1605 if (gsvs_ring_bo || esgs_ring_bo ||
1606 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1607 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1608 if (add_sample_positions)
1609 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1610 }
1611 else if (scratch_bo)
1612 size = 8; /* 2 dword */
1613
1614 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1615 size,
1616 4096,
1617 RADEON_DOMAIN_VRAM,
1618 RADEON_FLAG_CPU_ACCESS |
1619 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1620 RADEON_FLAG_READ_ONLY);
1621 if (!descriptor_bo)
1622 goto fail;
1623 } else
1624 descriptor_bo = queue->descriptor_bo;
1625
1626 for(int i = 0; i < 3; ++i) {
1627 struct radeon_winsys_cs *cs = NULL;
1628 cs = queue->device->ws->cs_create(queue->device->ws,
1629 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1630 if (!cs)
1631 goto fail;
1632
1633 dest_cs[i] = cs;
1634
1635 if (scratch_bo)
1636 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
1637
1638 if (esgs_ring_bo)
1639 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
1640
1641 if (gsvs_ring_bo)
1642 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
1643
1644 if (tess_factor_ring_bo)
1645 radv_cs_add_buffer(queue->device->ws, cs, tess_factor_ring_bo, 8);
1646
1647 if (tess_offchip_ring_bo)
1648 radv_cs_add_buffer(queue->device->ws, cs, tess_offchip_ring_bo, 8);
1649
1650 if (descriptor_bo)
1651 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
1652
1653 if (descriptor_bo != queue->descriptor_bo) {
1654 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1655
1656 if (scratch_bo) {
1657 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
1658 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1659 S_008F04_SWIZZLE_ENABLE(1);
1660 map[0] = scratch_va;
1661 map[1] = rsrc1;
1662 }
1663
1664 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1665 add_sample_positions)
1666 fill_geom_tess_rings(queue, map, add_sample_positions,
1667 esgs_ring_size, esgs_ring_bo,
1668 gsvs_ring_size, gsvs_ring_bo,
1669 tess_factor_ring_size, tess_factor_ring_bo,
1670 tess_offchip_ring_size, tess_offchip_ring_bo);
1671
1672 queue->device->ws->buffer_unmap(descriptor_bo);
1673 }
1674
1675 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1676 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1677 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1678 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1679 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1680 }
1681
1682 if (esgs_ring_bo || gsvs_ring_bo) {
1683 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1684 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1685 radeon_emit(cs, esgs_ring_size >> 8);
1686 radeon_emit(cs, gsvs_ring_size >> 8);
1687 } else {
1688 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1689 radeon_emit(cs, esgs_ring_size >> 8);
1690 radeon_emit(cs, gsvs_ring_size >> 8);
1691 }
1692 }
1693
1694 if (tess_factor_ring_bo) {
1695 uint64_t tf_va = radv_buffer_get_va(tess_factor_ring_bo);
1696 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1697 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1698 S_030938_SIZE(tess_factor_ring_size / 4));
1699 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1700 tf_va >> 8);
1701 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1702 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1703 tf_va >> 40);
1704 }
1705 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1706 } else {
1707 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1708 S_008988_SIZE(tess_factor_ring_size / 4));
1709 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1710 tf_va >> 8);
1711 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1712 hs_offchip_param);
1713 }
1714 }
1715
1716 if (descriptor_bo) {
1717 uint64_t va = radv_buffer_get_va(descriptor_bo);
1718 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1719 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1720 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1721 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
1722 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
1723
1724 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1725 radeon_set_sh_reg_seq(cs, regs[i], 2);
1726 radeon_emit(cs, va);
1727 radeon_emit(cs, va >> 32);
1728 }
1729 } else {
1730 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1731 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1732 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1733 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1734 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1735 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1736
1737 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1738 radeon_set_sh_reg_seq(cs, regs[i], 2);
1739 radeon_emit(cs, va);
1740 radeon_emit(cs, va >> 32);
1741 }
1742 }
1743 }
1744
1745 if (compute_scratch_bo) {
1746 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
1747 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1748 S_008F04_SWIZZLE_ENABLE(1);
1749
1750 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
1751
1752 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1753 radeon_emit(cs, scratch_va);
1754 radeon_emit(cs, rsrc1);
1755 }
1756
1757 if (i == 0) {
1758 si_cs_emit_cache_flush(cs,
1759 false,
1760 queue->device->physical_device->rad_info.chip_class,
1761 NULL, 0,
1762 queue->queue_family_index == RING_COMPUTE &&
1763 queue->device->physical_device->rad_info.chip_class >= CIK,
1764 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1765 RADV_CMD_FLAG_INV_ICACHE |
1766 RADV_CMD_FLAG_INV_SMEM_L1 |
1767 RADV_CMD_FLAG_INV_VMEM_L1 |
1768 RADV_CMD_FLAG_INV_GLOBAL_L2);
1769 } else if (i == 1) {
1770 si_cs_emit_cache_flush(cs,
1771 false,
1772 queue->device->physical_device->rad_info.chip_class,
1773 NULL, 0,
1774 queue->queue_family_index == RING_COMPUTE &&
1775 queue->device->physical_device->rad_info.chip_class >= CIK,
1776 RADV_CMD_FLAG_INV_ICACHE |
1777 RADV_CMD_FLAG_INV_SMEM_L1 |
1778 RADV_CMD_FLAG_INV_VMEM_L1 |
1779 RADV_CMD_FLAG_INV_GLOBAL_L2);
1780 }
1781
1782 if (!queue->device->ws->cs_finalize(cs))
1783 goto fail;
1784 }
1785
1786 if (queue->initial_full_flush_preamble_cs)
1787 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1788
1789 if (queue->initial_preamble_cs)
1790 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1791
1792 if (queue->continue_preamble_cs)
1793 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1794
1795 queue->initial_full_flush_preamble_cs = dest_cs[0];
1796 queue->initial_preamble_cs = dest_cs[1];
1797 queue->continue_preamble_cs = dest_cs[2];
1798
1799 if (scratch_bo != queue->scratch_bo) {
1800 if (queue->scratch_bo)
1801 queue->device->ws->buffer_destroy(queue->scratch_bo);
1802 queue->scratch_bo = scratch_bo;
1803 queue->scratch_size = scratch_size;
1804 }
1805
1806 if (compute_scratch_bo != queue->compute_scratch_bo) {
1807 if (queue->compute_scratch_bo)
1808 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1809 queue->compute_scratch_bo = compute_scratch_bo;
1810 queue->compute_scratch_size = compute_scratch_size;
1811 }
1812
1813 if (esgs_ring_bo != queue->esgs_ring_bo) {
1814 if (queue->esgs_ring_bo)
1815 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1816 queue->esgs_ring_bo = esgs_ring_bo;
1817 queue->esgs_ring_size = esgs_ring_size;
1818 }
1819
1820 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1821 if (queue->gsvs_ring_bo)
1822 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1823 queue->gsvs_ring_bo = gsvs_ring_bo;
1824 queue->gsvs_ring_size = gsvs_ring_size;
1825 }
1826
1827 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1828 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1829 }
1830
1831 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1832 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1833 queue->has_tess_rings = true;
1834 }
1835
1836 if (descriptor_bo != queue->descriptor_bo) {
1837 if (queue->descriptor_bo)
1838 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1839
1840 queue->descriptor_bo = descriptor_bo;
1841 }
1842
1843 if (add_sample_positions)
1844 queue->has_sample_positions = true;
1845
1846 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1847 *initial_preamble_cs = queue->initial_preamble_cs;
1848 *continue_preamble_cs = queue->continue_preamble_cs;
1849 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1850 *continue_preamble_cs = NULL;
1851 return VK_SUCCESS;
1852 fail:
1853 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1854 if (dest_cs[i])
1855 queue->device->ws->cs_destroy(dest_cs[i]);
1856 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1857 queue->device->ws->buffer_destroy(descriptor_bo);
1858 if (scratch_bo && scratch_bo != queue->scratch_bo)
1859 queue->device->ws->buffer_destroy(scratch_bo);
1860 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1861 queue->device->ws->buffer_destroy(compute_scratch_bo);
1862 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1863 queue->device->ws->buffer_destroy(esgs_ring_bo);
1864 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1865 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1866 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1867 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1868 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1869 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1870 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
1871 }
1872
1873 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1874 int num_sems,
1875 const VkSemaphore *sems,
1876 VkFence _fence,
1877 bool reset_temp)
1878 {
1879 int syncobj_idx = 0, sem_idx = 0;
1880
1881 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
1882 return VK_SUCCESS;
1883
1884 for (uint32_t i = 0; i < num_sems; i++) {
1885 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1886
1887 if (sem->temp_syncobj || sem->syncobj)
1888 counts->syncobj_count++;
1889 else
1890 counts->sem_count++;
1891 }
1892
1893 if (_fence != VK_NULL_HANDLE) {
1894 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1895 if (fence->temp_syncobj || fence->syncobj)
1896 counts->syncobj_count++;
1897 }
1898
1899 if (counts->syncobj_count) {
1900 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1901 if (!counts->syncobj)
1902 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1903 }
1904
1905 if (counts->sem_count) {
1906 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1907 if (!counts->sem) {
1908 free(counts->syncobj);
1909 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1910 }
1911 }
1912
1913 for (uint32_t i = 0; i < num_sems; i++) {
1914 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1915
1916 if (sem->temp_syncobj) {
1917 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1918 }
1919 else if (sem->syncobj)
1920 counts->syncobj[syncobj_idx++] = sem->syncobj;
1921 else {
1922 assert(sem->sem);
1923 counts->sem[sem_idx++] = sem->sem;
1924 }
1925 }
1926
1927 if (_fence != VK_NULL_HANDLE) {
1928 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1929 if (fence->temp_syncobj)
1930 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
1931 else if (fence->syncobj)
1932 counts->syncobj[syncobj_idx++] = fence->syncobj;
1933 }
1934
1935 return VK_SUCCESS;
1936 }
1937
1938 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
1939 {
1940 free(sem_info->wait.syncobj);
1941 free(sem_info->wait.sem);
1942 free(sem_info->signal.syncobj);
1943 free(sem_info->signal.sem);
1944 }
1945
1946
1947 static void radv_free_temp_syncobjs(struct radv_device *device,
1948 int num_sems,
1949 const VkSemaphore *sems)
1950 {
1951 for (uint32_t i = 0; i < num_sems; i++) {
1952 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1953
1954 if (sem->temp_syncobj) {
1955 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
1956 sem->temp_syncobj = 0;
1957 }
1958 }
1959 }
1960
1961 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1962 int num_wait_sems,
1963 const VkSemaphore *wait_sems,
1964 int num_signal_sems,
1965 const VkSemaphore *signal_sems,
1966 VkFence fence)
1967 {
1968 VkResult ret;
1969 memset(sem_info, 0, sizeof(*sem_info));
1970
1971 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
1972 if (ret)
1973 return ret;
1974 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, fence, false);
1975 if (ret)
1976 radv_free_sem_info(sem_info);
1977
1978 /* caller can override these */
1979 sem_info->cs_emit_wait = true;
1980 sem_info->cs_emit_signal = true;
1981 return ret;
1982 }
1983
1984 VkResult radv_QueueSubmit(
1985 VkQueue _queue,
1986 uint32_t submitCount,
1987 const VkSubmitInfo* pSubmits,
1988 VkFence _fence)
1989 {
1990 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1991 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1992 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1993 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1994 int ret;
1995 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1996 uint32_t scratch_size = 0;
1997 uint32_t compute_scratch_size = 0;
1998 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1999 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2000 VkResult result;
2001 bool fence_emitted = false;
2002 bool tess_rings_needed = false;
2003 bool sample_positions_needed = false;
2004
2005 /* Do this first so failing to allocate scratch buffers can't result in
2006 * partially executed submissions. */
2007 for (uint32_t i = 0; i < submitCount; i++) {
2008 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2009 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2010 pSubmits[i].pCommandBuffers[j]);
2011
2012 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2013 compute_scratch_size = MAX2(compute_scratch_size,
2014 cmd_buffer->compute_scratch_size_needed);
2015 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2016 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2017 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2018 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2019 }
2020 }
2021
2022 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2023 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2024 sample_positions_needed, &initial_flush_preamble_cs,
2025 &initial_preamble_cs, &continue_preamble_cs);
2026 if (result != VK_SUCCESS)
2027 return result;
2028
2029 for (uint32_t i = 0; i < submitCount; i++) {
2030 struct radeon_winsys_cs **cs_array;
2031 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2032 bool can_patch = true;
2033 uint32_t advance;
2034 struct radv_winsys_sem_info sem_info;
2035
2036 result = radv_alloc_sem_info(&sem_info,
2037 pSubmits[i].waitSemaphoreCount,
2038 pSubmits[i].pWaitSemaphores,
2039 pSubmits[i].signalSemaphoreCount,
2040 pSubmits[i].pSignalSemaphores,
2041 _fence);
2042 if (result != VK_SUCCESS)
2043 return result;
2044
2045 if (!pSubmits[i].commandBufferCount) {
2046 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2047 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2048 &queue->device->empty_cs[queue->queue_family_index],
2049 1, NULL, NULL,
2050 &sem_info,
2051 false, base_fence);
2052 if (ret) {
2053 radv_loge("failed to submit CS %d\n", i);
2054 abort();
2055 }
2056 fence_emitted = true;
2057 }
2058 radv_free_sem_info(&sem_info);
2059 continue;
2060 }
2061
2062 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2063 (pSubmits[i].commandBufferCount));
2064
2065 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2066 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2067 pSubmits[i].pCommandBuffers[j]);
2068 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2069
2070 cs_array[j] = cmd_buffer->cs;
2071 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2072 can_patch = false;
2073
2074 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2075 }
2076
2077 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2078 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2079 advance = MIN2(max_cs_submission,
2080 pSubmits[i].commandBufferCount - j);
2081
2082 if (queue->device->trace_bo)
2083 *queue->device->trace_id_ptr = 0;
2084
2085 sem_info.cs_emit_wait = j == 0;
2086 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2087
2088 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2089 advance, initial_preamble, continue_preamble_cs,
2090 &sem_info,
2091 can_patch, base_fence);
2092
2093 if (ret) {
2094 radv_loge("failed to submit CS %d\n", i);
2095 abort();
2096 }
2097 fence_emitted = true;
2098 if (queue->device->trace_bo) {
2099 radv_check_gpu_hangs(queue, cs_array[j]);
2100 }
2101 }
2102
2103 radv_free_temp_syncobjs(queue->device,
2104 pSubmits[i].waitSemaphoreCount,
2105 pSubmits[i].pWaitSemaphores);
2106 radv_free_sem_info(&sem_info);
2107 free(cs_array);
2108 }
2109
2110 if (fence) {
2111 if (!fence_emitted) {
2112 struct radv_winsys_sem_info sem_info;
2113
2114 result = radv_alloc_sem_info(&sem_info, 0, NULL, 0, NULL,
2115 _fence);
2116 if (result != VK_SUCCESS)
2117 return result;
2118
2119 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2120 &queue->device->empty_cs[queue->queue_family_index],
2121 1, NULL, NULL, &sem_info,
2122 false, base_fence);
2123 radv_free_sem_info(&sem_info);
2124 }
2125 fence->submitted = true;
2126 }
2127
2128 return VK_SUCCESS;
2129 }
2130
2131 VkResult radv_QueueWaitIdle(
2132 VkQueue _queue)
2133 {
2134 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2135
2136 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2137 radv_queue_family_to_ring(queue->queue_family_index),
2138 queue->queue_idx);
2139 return VK_SUCCESS;
2140 }
2141
2142 VkResult radv_DeviceWaitIdle(
2143 VkDevice _device)
2144 {
2145 RADV_FROM_HANDLE(radv_device, device, _device);
2146
2147 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2148 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2149 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2150 }
2151 }
2152 return VK_SUCCESS;
2153 }
2154
2155 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2156 VkInstance instance,
2157 const char* pName)
2158 {
2159 return radv_lookup_entrypoint(pName);
2160 }
2161
2162 /* The loader wants us to expose a second GetInstanceProcAddr function
2163 * to work around certain LD_PRELOAD issues seen in apps.
2164 */
2165 PUBLIC
2166 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2167 VkInstance instance,
2168 const char* pName);
2169
2170 PUBLIC
2171 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2172 VkInstance instance,
2173 const char* pName)
2174 {
2175 return radv_GetInstanceProcAddr(instance, pName);
2176 }
2177
2178 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2179 VkDevice device,
2180 const char* pName)
2181 {
2182 return radv_lookup_entrypoint(pName);
2183 }
2184
2185 bool radv_get_memory_fd(struct radv_device *device,
2186 struct radv_device_memory *memory,
2187 int *pFD)
2188 {
2189 struct radeon_bo_metadata metadata;
2190
2191 if (memory->image) {
2192 radv_init_metadata(device, memory->image, &metadata);
2193 device->ws->buffer_set_metadata(memory->bo, &metadata);
2194 }
2195
2196 return device->ws->buffer_get_fd(device->ws, memory->bo,
2197 pFD);
2198 }
2199
2200 static VkResult radv_alloc_memory(struct radv_device *device,
2201 const VkMemoryAllocateInfo* pAllocateInfo,
2202 const VkAllocationCallbacks* pAllocator,
2203 VkDeviceMemory* pMem)
2204 {
2205 struct radv_device_memory *mem;
2206 VkResult result;
2207 enum radeon_bo_domain domain;
2208 uint32_t flags = 0;
2209 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2210
2211 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2212
2213 if (pAllocateInfo->allocationSize == 0) {
2214 /* Apparently, this is allowed */
2215 *pMem = VK_NULL_HANDLE;
2216 return VK_SUCCESS;
2217 }
2218
2219 const VkImportMemoryFdInfoKHR *import_info =
2220 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2221 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2222 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2223 const VkExportMemoryAllocateInfoKHR *export_info =
2224 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2225
2226 const struct wsi_memory_allocate_info *wsi_info =
2227 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2228
2229 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2230 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2231 if (mem == NULL)
2232 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2233
2234 if (wsi_info && wsi_info->implicit_sync)
2235 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2236
2237 if (dedicate_info) {
2238 mem->image = radv_image_from_handle(dedicate_info->image);
2239 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2240 } else {
2241 mem->image = NULL;
2242 mem->buffer = NULL;
2243 }
2244
2245 if (import_info) {
2246 assert(import_info->handleType ==
2247 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2248 import_info->handleType ==
2249 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2250 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2251 NULL, NULL);
2252 if (!mem->bo) {
2253 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2254 goto fail;
2255 } else {
2256 close(import_info->fd);
2257 goto out_success;
2258 }
2259 }
2260
2261 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2262 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2263 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2264 domain = RADEON_DOMAIN_GTT;
2265 else
2266 domain = RADEON_DOMAIN_VRAM;
2267
2268 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2269 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2270 else
2271 flags |= RADEON_FLAG_CPU_ACCESS;
2272
2273 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2274 flags |= RADEON_FLAG_GTT_WC;
2275
2276 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2277 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2278
2279 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2280 domain, flags);
2281
2282 if (!mem->bo) {
2283 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2284 goto fail;
2285 }
2286 mem->type_index = mem_type_index;
2287 out_success:
2288 *pMem = radv_device_memory_to_handle(mem);
2289
2290 return VK_SUCCESS;
2291
2292 fail:
2293 vk_free2(&device->alloc, pAllocator, mem);
2294
2295 return result;
2296 }
2297
2298 VkResult radv_AllocateMemory(
2299 VkDevice _device,
2300 const VkMemoryAllocateInfo* pAllocateInfo,
2301 const VkAllocationCallbacks* pAllocator,
2302 VkDeviceMemory* pMem)
2303 {
2304 RADV_FROM_HANDLE(radv_device, device, _device);
2305 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2306 }
2307
2308 void radv_FreeMemory(
2309 VkDevice _device,
2310 VkDeviceMemory _mem,
2311 const VkAllocationCallbacks* pAllocator)
2312 {
2313 RADV_FROM_HANDLE(radv_device, device, _device);
2314 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2315
2316 if (mem == NULL)
2317 return;
2318
2319 device->ws->buffer_destroy(mem->bo);
2320 mem->bo = NULL;
2321
2322 vk_free2(&device->alloc, pAllocator, mem);
2323 }
2324
2325 VkResult radv_MapMemory(
2326 VkDevice _device,
2327 VkDeviceMemory _memory,
2328 VkDeviceSize offset,
2329 VkDeviceSize size,
2330 VkMemoryMapFlags flags,
2331 void** ppData)
2332 {
2333 RADV_FROM_HANDLE(radv_device, device, _device);
2334 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2335
2336 if (mem == NULL) {
2337 *ppData = NULL;
2338 return VK_SUCCESS;
2339 }
2340
2341 *ppData = device->ws->buffer_map(mem->bo);
2342 if (*ppData) {
2343 *ppData += offset;
2344 return VK_SUCCESS;
2345 }
2346
2347 return vk_error(VK_ERROR_MEMORY_MAP_FAILED);
2348 }
2349
2350 void radv_UnmapMemory(
2351 VkDevice _device,
2352 VkDeviceMemory _memory)
2353 {
2354 RADV_FROM_HANDLE(radv_device, device, _device);
2355 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2356
2357 if (mem == NULL)
2358 return;
2359
2360 device->ws->buffer_unmap(mem->bo);
2361 }
2362
2363 VkResult radv_FlushMappedMemoryRanges(
2364 VkDevice _device,
2365 uint32_t memoryRangeCount,
2366 const VkMappedMemoryRange* pMemoryRanges)
2367 {
2368 return VK_SUCCESS;
2369 }
2370
2371 VkResult radv_InvalidateMappedMemoryRanges(
2372 VkDevice _device,
2373 uint32_t memoryRangeCount,
2374 const VkMappedMemoryRange* pMemoryRanges)
2375 {
2376 return VK_SUCCESS;
2377 }
2378
2379 void radv_GetBufferMemoryRequirements(
2380 VkDevice _device,
2381 VkBuffer _buffer,
2382 VkMemoryRequirements* pMemoryRequirements)
2383 {
2384 RADV_FROM_HANDLE(radv_device, device, _device);
2385 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2386
2387 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2388
2389 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2390 pMemoryRequirements->alignment = 4096;
2391 else
2392 pMemoryRequirements->alignment = 16;
2393
2394 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2395 }
2396
2397 void radv_GetBufferMemoryRequirements2KHR(
2398 VkDevice device,
2399 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2400 VkMemoryRequirements2KHR* pMemoryRequirements)
2401 {
2402 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2403 &pMemoryRequirements->memoryRequirements);
2404 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2405 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2406 switch (ext->sType) {
2407 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2408 VkMemoryDedicatedRequirementsKHR *req =
2409 (VkMemoryDedicatedRequirementsKHR *) ext;
2410 req->requiresDedicatedAllocation = buffer->shareable;
2411 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2412 break;
2413 }
2414 default:
2415 break;
2416 }
2417 }
2418 }
2419
2420 void radv_GetImageMemoryRequirements(
2421 VkDevice _device,
2422 VkImage _image,
2423 VkMemoryRequirements* pMemoryRequirements)
2424 {
2425 RADV_FROM_HANDLE(radv_device, device, _device);
2426 RADV_FROM_HANDLE(radv_image, image, _image);
2427
2428 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2429
2430 pMemoryRequirements->size = image->size;
2431 pMemoryRequirements->alignment = image->alignment;
2432 }
2433
2434 void radv_GetImageMemoryRequirements2KHR(
2435 VkDevice device,
2436 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2437 VkMemoryRequirements2KHR* pMemoryRequirements)
2438 {
2439 radv_GetImageMemoryRequirements(device, pInfo->image,
2440 &pMemoryRequirements->memoryRequirements);
2441
2442 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2443
2444 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2445 switch (ext->sType) {
2446 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2447 VkMemoryDedicatedRequirementsKHR *req =
2448 (VkMemoryDedicatedRequirementsKHR *) ext;
2449 req->requiresDedicatedAllocation = image->shareable;
2450 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2451 break;
2452 }
2453 default:
2454 break;
2455 }
2456 }
2457 }
2458
2459 void radv_GetImageSparseMemoryRequirements(
2460 VkDevice device,
2461 VkImage image,
2462 uint32_t* pSparseMemoryRequirementCount,
2463 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2464 {
2465 stub();
2466 }
2467
2468 void radv_GetImageSparseMemoryRequirements2KHR(
2469 VkDevice device,
2470 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2471 uint32_t* pSparseMemoryRequirementCount,
2472 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2473 {
2474 stub();
2475 }
2476
2477 void radv_GetDeviceMemoryCommitment(
2478 VkDevice device,
2479 VkDeviceMemory memory,
2480 VkDeviceSize* pCommittedMemoryInBytes)
2481 {
2482 *pCommittedMemoryInBytes = 0;
2483 }
2484
2485 VkResult radv_BindBufferMemory2KHR(VkDevice device,
2486 uint32_t bindInfoCount,
2487 const VkBindBufferMemoryInfoKHR *pBindInfos)
2488 {
2489 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2490 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2491 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2492
2493 if (mem) {
2494 buffer->bo = mem->bo;
2495 buffer->offset = pBindInfos[i].memoryOffset;
2496 } else {
2497 buffer->bo = NULL;
2498 }
2499 }
2500 return VK_SUCCESS;
2501 }
2502
2503 VkResult radv_BindBufferMemory(
2504 VkDevice device,
2505 VkBuffer buffer,
2506 VkDeviceMemory memory,
2507 VkDeviceSize memoryOffset)
2508 {
2509 const VkBindBufferMemoryInfoKHR info = {
2510 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2511 .buffer = buffer,
2512 .memory = memory,
2513 .memoryOffset = memoryOffset
2514 };
2515
2516 return radv_BindBufferMemory2KHR(device, 1, &info);
2517 }
2518
2519 VkResult radv_BindImageMemory2KHR(VkDevice device,
2520 uint32_t bindInfoCount,
2521 const VkBindImageMemoryInfoKHR *pBindInfos)
2522 {
2523 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2524 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2525 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2526
2527 if (mem) {
2528 image->bo = mem->bo;
2529 image->offset = pBindInfos[i].memoryOffset;
2530 } else {
2531 image->bo = NULL;
2532 image->offset = 0;
2533 }
2534 }
2535 return VK_SUCCESS;
2536 }
2537
2538
2539 VkResult radv_BindImageMemory(
2540 VkDevice device,
2541 VkImage image,
2542 VkDeviceMemory memory,
2543 VkDeviceSize memoryOffset)
2544 {
2545 const VkBindImageMemoryInfoKHR info = {
2546 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2547 .image = image,
2548 .memory = memory,
2549 .memoryOffset = memoryOffset
2550 };
2551
2552 return radv_BindImageMemory2KHR(device, 1, &info);
2553 }
2554
2555
2556 static void
2557 radv_sparse_buffer_bind_memory(struct radv_device *device,
2558 const VkSparseBufferMemoryBindInfo *bind)
2559 {
2560 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2561
2562 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2563 struct radv_device_memory *mem = NULL;
2564
2565 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2566 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2567
2568 device->ws->buffer_virtual_bind(buffer->bo,
2569 bind->pBinds[i].resourceOffset,
2570 bind->pBinds[i].size,
2571 mem ? mem->bo : NULL,
2572 bind->pBinds[i].memoryOffset);
2573 }
2574 }
2575
2576 static void
2577 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2578 const VkSparseImageOpaqueMemoryBindInfo *bind)
2579 {
2580 RADV_FROM_HANDLE(radv_image, image, bind->image);
2581
2582 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2583 struct radv_device_memory *mem = NULL;
2584
2585 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2586 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2587
2588 device->ws->buffer_virtual_bind(image->bo,
2589 bind->pBinds[i].resourceOffset,
2590 bind->pBinds[i].size,
2591 mem ? mem->bo : NULL,
2592 bind->pBinds[i].memoryOffset);
2593 }
2594 }
2595
2596 VkResult radv_QueueBindSparse(
2597 VkQueue _queue,
2598 uint32_t bindInfoCount,
2599 const VkBindSparseInfo* pBindInfo,
2600 VkFence _fence)
2601 {
2602 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2603 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2604 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2605 bool fence_emitted = false;
2606
2607 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2608 struct radv_winsys_sem_info sem_info;
2609 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2610 radv_sparse_buffer_bind_memory(queue->device,
2611 pBindInfo[i].pBufferBinds + j);
2612 }
2613
2614 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2615 radv_sparse_image_opaque_bind_memory(queue->device,
2616 pBindInfo[i].pImageOpaqueBinds + j);
2617 }
2618
2619 VkResult result;
2620 result = radv_alloc_sem_info(&sem_info,
2621 pBindInfo[i].waitSemaphoreCount,
2622 pBindInfo[i].pWaitSemaphores,
2623 pBindInfo[i].signalSemaphoreCount,
2624 pBindInfo[i].pSignalSemaphores,
2625 _fence);
2626 if (result != VK_SUCCESS)
2627 return result;
2628
2629 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2630 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2631 &queue->device->empty_cs[queue->queue_family_index],
2632 1, NULL, NULL,
2633 &sem_info,
2634 false, base_fence);
2635 fence_emitted = true;
2636 if (fence)
2637 fence->submitted = true;
2638 }
2639
2640 radv_free_sem_info(&sem_info);
2641
2642 }
2643
2644 if (fence && !fence_emitted) {
2645 fence->signalled = true;
2646 }
2647
2648 return VK_SUCCESS;
2649 }
2650
2651 VkResult radv_CreateFence(
2652 VkDevice _device,
2653 const VkFenceCreateInfo* pCreateInfo,
2654 const VkAllocationCallbacks* pAllocator,
2655 VkFence* pFence)
2656 {
2657 RADV_FROM_HANDLE(radv_device, device, _device);
2658 const VkExportFenceCreateInfoKHR *export =
2659 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
2660 VkExternalFenceHandleTypeFlagsKHR handleTypes =
2661 export ? export->handleTypes : 0;
2662
2663 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2664 sizeof(*fence), 8,
2665 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2666
2667 if (!fence)
2668 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2669
2670 fence->submitted = false;
2671 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2672 fence->temp_syncobj = 0;
2673 if (handleTypes) {
2674 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
2675 if (ret) {
2676 vk_free2(&device->alloc, pAllocator, fence);
2677 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2678 }
2679 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
2680 device->ws->signal_syncobj(device->ws, fence->syncobj);
2681 }
2682 fence->fence = NULL;
2683 } else {
2684 fence->fence = device->ws->create_fence();
2685 if (!fence->fence) {
2686 vk_free2(&device->alloc, pAllocator, fence);
2687 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2688 }
2689 fence->syncobj = 0;
2690 }
2691
2692 *pFence = radv_fence_to_handle(fence);
2693
2694 return VK_SUCCESS;
2695 }
2696
2697 void radv_DestroyFence(
2698 VkDevice _device,
2699 VkFence _fence,
2700 const VkAllocationCallbacks* pAllocator)
2701 {
2702 RADV_FROM_HANDLE(radv_device, device, _device);
2703 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2704
2705 if (!fence)
2706 return;
2707
2708 if (fence->temp_syncobj)
2709 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
2710 if (fence->syncobj)
2711 device->ws->destroy_syncobj(device->ws, fence->syncobj);
2712 if (fence->fence)
2713 device->ws->destroy_fence(fence->fence);
2714 vk_free2(&device->alloc, pAllocator, fence);
2715 }
2716
2717 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2718 {
2719 uint64_t current_time;
2720 struct timespec tv;
2721
2722 clock_gettime(CLOCK_MONOTONIC, &tv);
2723 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2724
2725 timeout = MIN2(UINT64_MAX - current_time, timeout);
2726
2727 return current_time + timeout;
2728 }
2729
2730 VkResult radv_WaitForFences(
2731 VkDevice _device,
2732 uint32_t fenceCount,
2733 const VkFence* pFences,
2734 VkBool32 waitAll,
2735 uint64_t timeout)
2736 {
2737 RADV_FROM_HANDLE(radv_device, device, _device);
2738 timeout = radv_get_absolute_timeout(timeout);
2739
2740 if (!waitAll && fenceCount > 1) {
2741 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2742 }
2743
2744 for (uint32_t i = 0; i < fenceCount; ++i) {
2745 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2746 bool expired = false;
2747
2748 if (fence->temp_syncobj) {
2749 if (!device->ws->wait_syncobj(device->ws, fence->temp_syncobj, timeout))
2750 return VK_TIMEOUT;
2751 continue;
2752 }
2753
2754 if (fence->syncobj) {
2755 if (!device->ws->wait_syncobj(device->ws, fence->syncobj, timeout))
2756 return VK_TIMEOUT;
2757 continue;
2758 }
2759
2760 if (fence->signalled)
2761 continue;
2762
2763 if (!fence->submitted)
2764 return VK_TIMEOUT;
2765
2766 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2767 if (!expired)
2768 return VK_TIMEOUT;
2769
2770 fence->signalled = true;
2771 }
2772
2773 return VK_SUCCESS;
2774 }
2775
2776 VkResult radv_ResetFences(VkDevice _device,
2777 uint32_t fenceCount,
2778 const VkFence *pFences)
2779 {
2780 RADV_FROM_HANDLE(radv_device, device, _device);
2781
2782 for (unsigned i = 0; i < fenceCount; ++i) {
2783 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2784 fence->submitted = fence->signalled = false;
2785
2786 /* Per spec, we first restore the permanent payload, and then reset, so
2787 * having a temp syncobj should not skip resetting the permanent syncobj. */
2788 if (fence->temp_syncobj) {
2789 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
2790 fence->temp_syncobj = 0;
2791 }
2792
2793 if (fence->syncobj) {
2794 device->ws->reset_syncobj(device->ws, fence->syncobj);
2795 }
2796 }
2797
2798 return VK_SUCCESS;
2799 }
2800
2801 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2802 {
2803 RADV_FROM_HANDLE(radv_device, device, _device);
2804 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2805
2806 if (fence->temp_syncobj) {
2807 bool success = device->ws->wait_syncobj(device->ws, fence->temp_syncobj, 0);
2808 return success ? VK_SUCCESS : VK_NOT_READY;
2809 }
2810
2811 if (fence->syncobj) {
2812 bool success = device->ws->wait_syncobj(device->ws, fence->syncobj, 0);
2813 return success ? VK_SUCCESS : VK_NOT_READY;
2814 }
2815
2816 if (fence->signalled)
2817 return VK_SUCCESS;
2818 if (!fence->submitted)
2819 return VK_NOT_READY;
2820 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2821 return VK_NOT_READY;
2822
2823 return VK_SUCCESS;
2824 }
2825
2826
2827 // Queue semaphore functions
2828
2829 VkResult radv_CreateSemaphore(
2830 VkDevice _device,
2831 const VkSemaphoreCreateInfo* pCreateInfo,
2832 const VkAllocationCallbacks* pAllocator,
2833 VkSemaphore* pSemaphore)
2834 {
2835 RADV_FROM_HANDLE(radv_device, device, _device);
2836 const VkExportSemaphoreCreateInfoKHR *export =
2837 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2838 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2839 export ? export->handleTypes : 0;
2840
2841 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2842 sizeof(*sem), 8,
2843 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2844 if (!sem)
2845 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2846
2847 sem->temp_syncobj = 0;
2848 /* create a syncobject if we are going to export this semaphore */
2849 if (handleTypes) {
2850 assert (device->physical_device->rad_info.has_syncobj);
2851 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2852 if (ret) {
2853 vk_free2(&device->alloc, pAllocator, sem);
2854 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2855 }
2856 sem->sem = NULL;
2857 } else {
2858 sem->sem = device->ws->create_sem(device->ws);
2859 if (!sem->sem) {
2860 vk_free2(&device->alloc, pAllocator, sem);
2861 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2862 }
2863 sem->syncobj = 0;
2864 }
2865
2866 *pSemaphore = radv_semaphore_to_handle(sem);
2867 return VK_SUCCESS;
2868 }
2869
2870 void radv_DestroySemaphore(
2871 VkDevice _device,
2872 VkSemaphore _semaphore,
2873 const VkAllocationCallbacks* pAllocator)
2874 {
2875 RADV_FROM_HANDLE(radv_device, device, _device);
2876 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2877 if (!_semaphore)
2878 return;
2879
2880 if (sem->syncobj)
2881 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2882 else
2883 device->ws->destroy_sem(sem->sem);
2884 vk_free2(&device->alloc, pAllocator, sem);
2885 }
2886
2887 VkResult radv_CreateEvent(
2888 VkDevice _device,
2889 const VkEventCreateInfo* pCreateInfo,
2890 const VkAllocationCallbacks* pAllocator,
2891 VkEvent* pEvent)
2892 {
2893 RADV_FROM_HANDLE(radv_device, device, _device);
2894 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2895 sizeof(*event), 8,
2896 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2897
2898 if (!event)
2899 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2900
2901 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2902 RADEON_DOMAIN_GTT,
2903 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
2904 if (!event->bo) {
2905 vk_free2(&device->alloc, pAllocator, event);
2906 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2907 }
2908
2909 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2910
2911 *pEvent = radv_event_to_handle(event);
2912
2913 return VK_SUCCESS;
2914 }
2915
2916 void radv_DestroyEvent(
2917 VkDevice _device,
2918 VkEvent _event,
2919 const VkAllocationCallbacks* pAllocator)
2920 {
2921 RADV_FROM_HANDLE(radv_device, device, _device);
2922 RADV_FROM_HANDLE(radv_event, event, _event);
2923
2924 if (!event)
2925 return;
2926 device->ws->buffer_destroy(event->bo);
2927 vk_free2(&device->alloc, pAllocator, event);
2928 }
2929
2930 VkResult radv_GetEventStatus(
2931 VkDevice _device,
2932 VkEvent _event)
2933 {
2934 RADV_FROM_HANDLE(radv_event, event, _event);
2935
2936 if (*event->map == 1)
2937 return VK_EVENT_SET;
2938 return VK_EVENT_RESET;
2939 }
2940
2941 VkResult radv_SetEvent(
2942 VkDevice _device,
2943 VkEvent _event)
2944 {
2945 RADV_FROM_HANDLE(radv_event, event, _event);
2946 *event->map = 1;
2947
2948 return VK_SUCCESS;
2949 }
2950
2951 VkResult radv_ResetEvent(
2952 VkDevice _device,
2953 VkEvent _event)
2954 {
2955 RADV_FROM_HANDLE(radv_event, event, _event);
2956 *event->map = 0;
2957
2958 return VK_SUCCESS;
2959 }
2960
2961 VkResult radv_CreateBuffer(
2962 VkDevice _device,
2963 const VkBufferCreateInfo* pCreateInfo,
2964 const VkAllocationCallbacks* pAllocator,
2965 VkBuffer* pBuffer)
2966 {
2967 RADV_FROM_HANDLE(radv_device, device, _device);
2968 struct radv_buffer *buffer;
2969
2970 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2971
2972 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2973 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2974 if (buffer == NULL)
2975 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2976
2977 buffer->size = pCreateInfo->size;
2978 buffer->usage = pCreateInfo->usage;
2979 buffer->bo = NULL;
2980 buffer->offset = 0;
2981 buffer->flags = pCreateInfo->flags;
2982
2983 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
2984 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
2985
2986 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2987 buffer->bo = device->ws->buffer_create(device->ws,
2988 align64(buffer->size, 4096),
2989 4096, 0, RADEON_FLAG_VIRTUAL);
2990 if (!buffer->bo) {
2991 vk_free2(&device->alloc, pAllocator, buffer);
2992 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2993 }
2994 }
2995
2996 *pBuffer = radv_buffer_to_handle(buffer);
2997
2998 return VK_SUCCESS;
2999 }
3000
3001 void radv_DestroyBuffer(
3002 VkDevice _device,
3003 VkBuffer _buffer,
3004 const VkAllocationCallbacks* pAllocator)
3005 {
3006 RADV_FROM_HANDLE(radv_device, device, _device);
3007 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3008
3009 if (!buffer)
3010 return;
3011
3012 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3013 device->ws->buffer_destroy(buffer->bo);
3014
3015 vk_free2(&device->alloc, pAllocator, buffer);
3016 }
3017
3018 static inline unsigned
3019 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3020 {
3021 if (stencil)
3022 return image->surface.u.legacy.stencil_tiling_index[level];
3023 else
3024 return image->surface.u.legacy.tiling_index[level];
3025 }
3026
3027 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3028 {
3029 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3030 }
3031
3032 static void
3033 radv_initialise_color_surface(struct radv_device *device,
3034 struct radv_color_buffer_info *cb,
3035 struct radv_image_view *iview)
3036 {
3037 const struct vk_format_description *desc;
3038 unsigned ntype, format, swap, endian;
3039 unsigned blend_clamp = 0, blend_bypass = 0;
3040 uint64_t va;
3041 const struct radeon_surf *surf = &iview->image->surface;
3042
3043 desc = vk_format_description(iview->vk_format);
3044
3045 memset(cb, 0, sizeof(*cb));
3046
3047 /* Intensity is implemented as Red, so treat it that way. */
3048 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3049
3050 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3051
3052 cb->cb_color_base = va >> 8;
3053
3054 if (device->physical_device->rad_info.chip_class >= GFX9) {
3055 struct gfx9_surf_meta_flags meta;
3056 if (iview->image->dcc_offset)
3057 meta = iview->image->surface.u.gfx9.dcc;
3058 else
3059 meta = iview->image->surface.u.gfx9.cmask;
3060
3061 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3062 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3063 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3064 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3065
3066 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3067 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3068 } else {
3069 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3070 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3071
3072 cb->cb_color_base += level_info->offset >> 8;
3073 if (level_info->mode == RADEON_SURF_MODE_2D)
3074 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3075
3076 pitch_tile_max = level_info->nblk_x / 8 - 1;
3077 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3078 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3079
3080 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3081 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3082 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3083
3084 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3085
3086 if (iview->image->fmask.size) {
3087 if (device->physical_device->rad_info.chip_class >= CIK)
3088 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3089 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3090 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3091 } else {
3092 /* This must be set for fast clear to work without FMASK. */
3093 if (device->physical_device->rad_info.chip_class >= CIK)
3094 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3095 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3096 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3097 }
3098 }
3099
3100 /* CMASK variables */
3101 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3102 va += iview->image->cmask.offset;
3103 cb->cb_color_cmask = va >> 8;
3104
3105 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3106 va += iview->image->dcc_offset;
3107 cb->cb_dcc_base = va >> 8;
3108 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3109
3110 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3111 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3112 S_028C6C_SLICE_MAX(max_slice);
3113
3114 if (iview->image->info.samples > 1) {
3115 unsigned log_samples = util_logbase2(iview->image->info.samples);
3116
3117 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3118 S_028C74_NUM_FRAGMENTS(log_samples);
3119 }
3120
3121 if (iview->image->fmask.size) {
3122 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3123 cb->cb_color_fmask = va >> 8;
3124 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3125 } else {
3126 cb->cb_color_fmask = cb->cb_color_base;
3127 }
3128
3129 ntype = radv_translate_color_numformat(iview->vk_format,
3130 desc,
3131 vk_format_get_first_non_void_channel(iview->vk_format));
3132 format = radv_translate_colorformat(iview->vk_format);
3133 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3134 radv_finishme("Illegal color\n");
3135 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3136 endian = radv_colorformat_endian_swap(format);
3137
3138 /* blend clamp should be set for all NORM/SRGB types */
3139 if (ntype == V_028C70_NUMBER_UNORM ||
3140 ntype == V_028C70_NUMBER_SNORM ||
3141 ntype == V_028C70_NUMBER_SRGB)
3142 blend_clamp = 1;
3143
3144 /* set blend bypass according to docs if SINT/UINT or
3145 8/24 COLOR variants */
3146 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3147 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3148 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3149 blend_clamp = 0;
3150 blend_bypass = 1;
3151 }
3152 #if 0
3153 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3154 (format == V_028C70_COLOR_8 ||
3155 format == V_028C70_COLOR_8_8 ||
3156 format == V_028C70_COLOR_8_8_8_8))
3157 ->color_is_int8 = true;
3158 #endif
3159 cb->cb_color_info = S_028C70_FORMAT(format) |
3160 S_028C70_COMP_SWAP(swap) |
3161 S_028C70_BLEND_CLAMP(blend_clamp) |
3162 S_028C70_BLEND_BYPASS(blend_bypass) |
3163 S_028C70_SIMPLE_FLOAT(1) |
3164 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3165 ntype != V_028C70_NUMBER_SNORM &&
3166 ntype != V_028C70_NUMBER_SRGB &&
3167 format != V_028C70_COLOR_8_24 &&
3168 format != V_028C70_COLOR_24_8) |
3169 S_028C70_NUMBER_TYPE(ntype) |
3170 S_028C70_ENDIAN(endian);
3171 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
3172 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3173 if (device->physical_device->rad_info.chip_class == SI) {
3174 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3175 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3176 }
3177 }
3178
3179 if (iview->image->cmask.size &&
3180 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3181 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3182
3183 if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
3184 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3185
3186 if (device->physical_device->rad_info.chip_class >= VI) {
3187 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3188 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3189 unsigned independent_64b_blocks = 0;
3190 unsigned max_compressed_block_size;
3191
3192 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
3193 64 for APU because all of our APUs to date use DIMMs which have
3194 a request granularity size of 64B while all other chips have a
3195 32B request size */
3196 if (!device->physical_device->rad_info.has_dedicated_vram)
3197 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3198
3199 if (iview->image->info.samples > 1) {
3200 if (iview->image->surface.bpe == 1)
3201 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3202 else if (iview->image->surface.bpe == 2)
3203 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3204 }
3205
3206 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3207 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3208 independent_64b_blocks = 1;
3209 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3210 } else
3211 max_compressed_block_size = max_uncompressed_block_size;
3212
3213 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3214 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3215 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3216 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3217 }
3218
3219 /* This must be set for fast clear to work without FMASK. */
3220 if (!iview->image->fmask.size &&
3221 device->physical_device->rad_info.chip_class == SI) {
3222 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3223 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3224 }
3225
3226 if (device->physical_device->rad_info.chip_class >= GFX9) {
3227 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3228 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3229
3230 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3231 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3232 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3233 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3234 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3235 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3236 }
3237 }
3238
3239 static void
3240 radv_initialise_ds_surface(struct radv_device *device,
3241 struct radv_ds_buffer_info *ds,
3242 struct radv_image_view *iview)
3243 {
3244 unsigned level = iview->base_mip;
3245 unsigned format, stencil_format;
3246 uint64_t va, s_offs, z_offs;
3247 bool stencil_only = false;
3248 memset(ds, 0, sizeof(*ds));
3249 switch (iview->image->vk_format) {
3250 case VK_FORMAT_D24_UNORM_S8_UINT:
3251 case VK_FORMAT_X8_D24_UNORM_PACK32:
3252 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3253 ds->offset_scale = 2.0f;
3254 break;
3255 case VK_FORMAT_D16_UNORM:
3256 case VK_FORMAT_D16_UNORM_S8_UINT:
3257 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3258 ds->offset_scale = 4.0f;
3259 break;
3260 case VK_FORMAT_D32_SFLOAT:
3261 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3262 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3263 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3264 ds->offset_scale = 1.0f;
3265 break;
3266 case VK_FORMAT_S8_UINT:
3267 stencil_only = true;
3268 break;
3269 default:
3270 break;
3271 }
3272
3273 format = radv_translate_dbformat(iview->image->vk_format);
3274 stencil_format = iview->image->surface.has_stencil ?
3275 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3276
3277 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3278 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3279 S_028008_SLICE_MAX(max_slice);
3280
3281 ds->db_htile_data_base = 0;
3282 ds->db_htile_surface = 0;
3283
3284 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3285 s_offs = z_offs = va;
3286
3287 if (device->physical_device->rad_info.chip_class >= GFX9) {
3288 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3289 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3290
3291 ds->db_z_info = S_028038_FORMAT(format) |
3292 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3293 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3294 S_028038_MAXMIP(iview->image->info.levels - 1);
3295 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3296 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3297
3298 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3299 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3300 ds->db_depth_view |= S_028008_MIPID(level);
3301
3302 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3303 S_02801C_Y_MAX(iview->image->info.height - 1);
3304
3305 if (radv_htile_enabled(iview->image, level)) {
3306 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3307
3308 if (iview->image->tc_compatible_htile) {
3309 unsigned max_zplanes = 4;
3310
3311 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3312 iview->image->info.samples > 1)
3313 max_zplanes = 2;
3314
3315 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
3316 S_028038_ITERATE_FLUSH(1);
3317 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3318 }
3319
3320 if (!iview->image->surface.has_stencil)
3321 /* Use all of the htile_buffer for depth if there's no stencil. */
3322 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3323 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3324 iview->image->htile_offset;
3325 ds->db_htile_data_base = va >> 8;
3326 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3327 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3328 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3329 }
3330 } else {
3331 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3332
3333 if (stencil_only)
3334 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3335
3336 z_offs += iview->image->surface.u.legacy.level[level].offset;
3337 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3338
3339 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!iview->image->tc_compatible_htile);
3340 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3341 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3342
3343 if (iview->image->info.samples > 1)
3344 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3345
3346 if (device->physical_device->rad_info.chip_class >= CIK) {
3347 struct radeon_info *info = &device->physical_device->rad_info;
3348 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3349 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3350 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3351 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3352 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3353 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3354
3355 if (stencil_only)
3356 tile_mode = stencil_tile_mode;
3357
3358 ds->db_depth_info |=
3359 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3360 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3361 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3362 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3363 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3364 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3365 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3366 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3367 } else {
3368 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3369 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3370 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3371 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3372 if (stencil_only)
3373 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3374 }
3375
3376 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3377 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3378 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3379
3380 if (radv_htile_enabled(iview->image, level)) {
3381 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3382
3383 if (!iview->image->surface.has_stencil &&
3384 !iview->image->tc_compatible_htile)
3385 /* Use all of the htile_buffer for depth if there's no stencil. */
3386 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3387
3388 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3389 iview->image->htile_offset;
3390 ds->db_htile_data_base = va >> 8;
3391 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3392
3393 if (iview->image->tc_compatible_htile) {
3394 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3395
3396 if (iview->image->info.samples <= 1)
3397 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3398 else if (iview->image->info.samples <= 4)
3399 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3400 else
3401 ds->db_z_info|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3402 }
3403 }
3404 }
3405
3406 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3407 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3408 }
3409
3410 VkResult radv_CreateFramebuffer(
3411 VkDevice _device,
3412 const VkFramebufferCreateInfo* pCreateInfo,
3413 const VkAllocationCallbacks* pAllocator,
3414 VkFramebuffer* pFramebuffer)
3415 {
3416 RADV_FROM_HANDLE(radv_device, device, _device);
3417 struct radv_framebuffer *framebuffer;
3418
3419 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3420
3421 size_t size = sizeof(*framebuffer) +
3422 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3423 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3424 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3425 if (framebuffer == NULL)
3426 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3427
3428 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3429 framebuffer->width = pCreateInfo->width;
3430 framebuffer->height = pCreateInfo->height;
3431 framebuffer->layers = pCreateInfo->layers;
3432 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3433 VkImageView _iview = pCreateInfo->pAttachments[i];
3434 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3435 framebuffer->attachments[i].attachment = iview;
3436 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3437 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3438 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3439 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3440 }
3441 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3442 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3443 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
3444 }
3445
3446 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3447 return VK_SUCCESS;
3448 }
3449
3450 void radv_DestroyFramebuffer(
3451 VkDevice _device,
3452 VkFramebuffer _fb,
3453 const VkAllocationCallbacks* pAllocator)
3454 {
3455 RADV_FROM_HANDLE(radv_device, device, _device);
3456 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3457
3458 if (!fb)
3459 return;
3460 vk_free2(&device->alloc, pAllocator, fb);
3461 }
3462
3463 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3464 {
3465 switch (address_mode) {
3466 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3467 return V_008F30_SQ_TEX_WRAP;
3468 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3469 return V_008F30_SQ_TEX_MIRROR;
3470 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3471 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3472 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3473 return V_008F30_SQ_TEX_CLAMP_BORDER;
3474 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3475 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3476 default:
3477 unreachable("illegal tex wrap mode");
3478 break;
3479 }
3480 }
3481
3482 static unsigned
3483 radv_tex_compare(VkCompareOp op)
3484 {
3485 switch (op) {
3486 case VK_COMPARE_OP_NEVER:
3487 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3488 case VK_COMPARE_OP_LESS:
3489 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3490 case VK_COMPARE_OP_EQUAL:
3491 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3492 case VK_COMPARE_OP_LESS_OR_EQUAL:
3493 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3494 case VK_COMPARE_OP_GREATER:
3495 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3496 case VK_COMPARE_OP_NOT_EQUAL:
3497 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3498 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3499 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3500 case VK_COMPARE_OP_ALWAYS:
3501 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3502 default:
3503 unreachable("illegal compare mode");
3504 break;
3505 }
3506 }
3507
3508 static unsigned
3509 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3510 {
3511 switch (filter) {
3512 case VK_FILTER_NEAREST:
3513 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3514 V_008F38_SQ_TEX_XY_FILTER_POINT);
3515 case VK_FILTER_LINEAR:
3516 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3517 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3518 case VK_FILTER_CUBIC_IMG:
3519 default:
3520 fprintf(stderr, "illegal texture filter");
3521 return 0;
3522 }
3523 }
3524
3525 static unsigned
3526 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3527 {
3528 switch (mode) {
3529 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3530 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3531 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3532 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3533 default:
3534 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3535 }
3536 }
3537
3538 static unsigned
3539 radv_tex_bordercolor(VkBorderColor bcolor)
3540 {
3541 switch (bcolor) {
3542 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3543 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3544 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3545 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3546 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3547 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3548 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3549 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3550 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3551 default:
3552 break;
3553 }
3554 return 0;
3555 }
3556
3557 static unsigned
3558 radv_tex_aniso_filter(unsigned filter)
3559 {
3560 if (filter < 2)
3561 return 0;
3562 if (filter < 4)
3563 return 1;
3564 if (filter < 8)
3565 return 2;
3566 if (filter < 16)
3567 return 3;
3568 return 4;
3569 }
3570
3571 static void
3572 radv_init_sampler(struct radv_device *device,
3573 struct radv_sampler *sampler,
3574 const VkSamplerCreateInfo *pCreateInfo)
3575 {
3576 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3577 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3578 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3579 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3580
3581 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3582 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3583 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3584 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3585 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3586 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3587 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3588 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3589 S_008F30_DISABLE_CUBE_WRAP(0) |
3590 S_008F30_COMPAT_MODE(is_vi));
3591 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3592 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3593 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3594 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3595 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3596 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3597 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3598 S_008F38_MIP_POINT_PRECLAMP(0) |
3599 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
3600 S_008F38_FILTER_PREC_FIX(1) |
3601 S_008F38_ANISO_OVERRIDE(is_vi));
3602 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3603 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3604 }
3605
3606 VkResult radv_CreateSampler(
3607 VkDevice _device,
3608 const VkSamplerCreateInfo* pCreateInfo,
3609 const VkAllocationCallbacks* pAllocator,
3610 VkSampler* pSampler)
3611 {
3612 RADV_FROM_HANDLE(radv_device, device, _device);
3613 struct radv_sampler *sampler;
3614
3615 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3616
3617 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3618 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3619 if (!sampler)
3620 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3621
3622 radv_init_sampler(device, sampler, pCreateInfo);
3623 *pSampler = radv_sampler_to_handle(sampler);
3624
3625 return VK_SUCCESS;
3626 }
3627
3628 void radv_DestroySampler(
3629 VkDevice _device,
3630 VkSampler _sampler,
3631 const VkAllocationCallbacks* pAllocator)
3632 {
3633 RADV_FROM_HANDLE(radv_device, device, _device);
3634 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3635
3636 if (!sampler)
3637 return;
3638 vk_free2(&device->alloc, pAllocator, sampler);
3639 }
3640
3641 /* vk_icd.h does not declare this function, so we declare it here to
3642 * suppress Wmissing-prototypes.
3643 */
3644 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3645 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3646
3647 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3648 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3649 {
3650 /* For the full details on loader interface versioning, see
3651 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3652 * What follows is a condensed summary, to help you navigate the large and
3653 * confusing official doc.
3654 *
3655 * - Loader interface v0 is incompatible with later versions. We don't
3656 * support it.
3657 *
3658 * - In loader interface v1:
3659 * - The first ICD entrypoint called by the loader is
3660 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3661 * entrypoint.
3662 * - The ICD must statically expose no other Vulkan symbol unless it is
3663 * linked with -Bsymbolic.
3664 * - Each dispatchable Vulkan handle created by the ICD must be
3665 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3666 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3667 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3668 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3669 * such loader-managed surfaces.
3670 *
3671 * - Loader interface v2 differs from v1 in:
3672 * - The first ICD entrypoint called by the loader is
3673 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3674 * statically expose this entrypoint.
3675 *
3676 * - Loader interface v3 differs from v2 in:
3677 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3678 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3679 * because the loader no longer does so.
3680 */
3681 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3682 return VK_SUCCESS;
3683 }
3684
3685 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3686 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3687 int *pFD)
3688 {
3689 RADV_FROM_HANDLE(radv_device, device, _device);
3690 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3691
3692 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3693
3694 /* At the moment, we support only the below handle types. */
3695 assert(pGetFdInfo->handleType ==
3696 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3697 pGetFdInfo->handleType ==
3698 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3699
3700 bool ret = radv_get_memory_fd(device, memory, pFD);
3701 if (ret == false)
3702 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3703 return VK_SUCCESS;
3704 }
3705
3706 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3707 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3708 int fd,
3709 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3710 {
3711 switch (handleType) {
3712 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
3713 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
3714 return VK_SUCCESS;
3715
3716 default:
3717 /* The valid usage section for this function says:
3718 *
3719 * "handleType must not be one of the handle types defined as
3720 * opaque."
3721 *
3722 * So opaque handle types fall into the default "unsupported" case.
3723 */
3724 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3725 }
3726 }
3727
3728 static VkResult radv_import_opaque_fd(struct radv_device *device,
3729 int fd,
3730 uint32_t *syncobj)
3731 {
3732 uint32_t syncobj_handle = 0;
3733 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
3734 if (ret != 0)
3735 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3736
3737 if (*syncobj)
3738 device->ws->destroy_syncobj(device->ws, *syncobj);
3739
3740 *syncobj = syncobj_handle;
3741 close(fd);
3742
3743 return VK_SUCCESS;
3744 }
3745
3746 static VkResult radv_import_sync_fd(struct radv_device *device,
3747 int fd,
3748 uint32_t *syncobj)
3749 {
3750 /* If we create a syncobj we do it locally so that if we have an error, we don't
3751 * leave a syncobj in an undetermined state in the fence. */
3752 uint32_t syncobj_handle = *syncobj;
3753 if (!syncobj_handle) {
3754 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
3755 if (ret) {
3756 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3757 }
3758 }
3759
3760 if (fd == -1) {
3761 device->ws->signal_syncobj(device->ws, syncobj_handle);
3762 } else {
3763 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
3764 if (ret != 0)
3765 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3766 }
3767
3768 *syncobj = syncobj_handle;
3769 if (fd != -1)
3770 close(fd);
3771
3772 return VK_SUCCESS;
3773 }
3774
3775 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3776 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3777 {
3778 RADV_FROM_HANDLE(radv_device, device, _device);
3779 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3780 uint32_t *syncobj_dst = NULL;
3781
3782 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3783 syncobj_dst = &sem->temp_syncobj;
3784 } else {
3785 syncobj_dst = &sem->syncobj;
3786 }
3787
3788 switch(pImportSemaphoreFdInfo->handleType) {
3789 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3790 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
3791 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3792 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
3793 default:
3794 unreachable("Unhandled semaphore handle type");
3795 }
3796 }
3797
3798 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3799 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3800 int *pFd)
3801 {
3802 RADV_FROM_HANDLE(radv_device, device, _device);
3803 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3804 int ret;
3805 uint32_t syncobj_handle;
3806
3807 if (sem->temp_syncobj)
3808 syncobj_handle = sem->temp_syncobj;
3809 else
3810 syncobj_handle = sem->syncobj;
3811
3812 switch(pGetFdInfo->handleType) {
3813 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3814 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3815 break;
3816 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3817 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
3818 break;
3819 default:
3820 unreachable("Unhandled semaphore handle type");
3821 }
3822
3823 if (ret)
3824 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3825 return VK_SUCCESS;
3826 }
3827
3828 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3829 VkPhysicalDevice physicalDevice,
3830 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3831 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3832 {
3833 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
3834
3835 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
3836 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
3837 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3838 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
3839 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3840 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3841 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3842 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3843 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3844 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3845 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3846 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3847 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3848 } else {
3849 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3850 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3851 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3852 }
3853 }
3854
3855 VkResult radv_ImportFenceFdKHR(VkDevice _device,
3856 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
3857 {
3858 RADV_FROM_HANDLE(radv_device, device, _device);
3859 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
3860 uint32_t *syncobj_dst = NULL;
3861
3862
3863 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
3864 syncobj_dst = &fence->temp_syncobj;
3865 } else {
3866 syncobj_dst = &fence->syncobj;
3867 }
3868
3869 switch(pImportFenceFdInfo->handleType) {
3870 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3871 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
3872 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3873 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
3874 default:
3875 unreachable("Unhandled fence handle type");
3876 }
3877 }
3878
3879 VkResult radv_GetFenceFdKHR(VkDevice _device,
3880 const VkFenceGetFdInfoKHR *pGetFdInfo,
3881 int *pFd)
3882 {
3883 RADV_FROM_HANDLE(radv_device, device, _device);
3884 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
3885 int ret;
3886 uint32_t syncobj_handle;
3887
3888 if (fence->temp_syncobj)
3889 syncobj_handle = fence->temp_syncobj;
3890 else
3891 syncobj_handle = fence->syncobj;
3892
3893 switch(pGetFdInfo->handleType) {
3894 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3895 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3896 break;
3897 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3898 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
3899 break;
3900 default:
3901 unreachable("Unhandled fence handle type");
3902 }
3903
3904 if (ret)
3905 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3906 return VK_SUCCESS;
3907 }
3908
3909 void radv_GetPhysicalDeviceExternalFencePropertiesKHR(
3910 VkPhysicalDevice physicalDevice,
3911 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
3912 VkExternalFencePropertiesKHR* pExternalFenceProperties)
3913 {
3914 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
3915
3916 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
3917 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3918 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
3919 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3920 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3921 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
3922 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3923 } else {
3924 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
3925 pExternalFenceProperties->compatibleHandleTypes = 0;
3926 pExternalFenceProperties->externalFenceFeatures = 0;
3927 }
3928 }