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dda535d553822d4468f9bb6c1dda5f55e2c2c24e
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "dirent.h"
29 #include <errno.h>
30 #include <fcntl.h>
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
36 #include <stdatomic.h>
37 #include <stdbool.h>
38 #include <stddef.h>
39 #include <stdio.h>
40 #include <string.h>
41 #include <sys/prctl.h>
42 #include <sys/wait.h>
43 #include <unistd.h>
44 #include <fcntl.h>
45
46 #include "radv_debug.h"
47 #include "radv_private.h"
48 #include "radv_shader.h"
49 #include "radv_cs.h"
50 #include "util/disk_cache.h"
51 #include "vk_util.h"
52 #include <xf86drm.h>
53 #include <amdgpu.h>
54 #include "drm-uapi/amdgpu_drm.h"
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "winsys/null/radv_null_winsys_public.h"
57 #include "ac_llvm_util.h"
58 #include "vk_format.h"
59 #include "sid.h"
60 #include "git_sha1.h"
61 #include "util/build_id.h"
62 #include "util/debug.h"
63 #include "util/mesa-sha1.h"
64 #include "util/timespec.h"
65 #include "util/u_atomic.h"
66 #include "compiler/glsl_types.h"
67 #include "util/driconf.h"
68
69 static struct radv_timeline_point *
70 radv_timeline_find_point_at_least_locked(struct radv_device *device,
71 struct radv_timeline *timeline,
72 uint64_t p);
73
74 static struct radv_timeline_point *
75 radv_timeline_add_point_locked(struct radv_device *device,
76 struct radv_timeline *timeline,
77 uint64_t p);
78
79 static void
80 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
81 struct list_head *processing_list);
82
83 static
84 void radv_destroy_semaphore_part(struct radv_device *device,
85 struct radv_semaphore_part *part);
86
87 static VkResult
88 radv_create_pthread_cond(pthread_cond_t *cond);
89
90 uint64_t radv_get_current_time(void)
91 {
92 struct timespec tv;
93 clock_gettime(CLOCK_MONOTONIC, &tv);
94 return tv.tv_nsec + tv.tv_sec*1000000000ull;
95 }
96
97 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
98 {
99 uint64_t current_time = radv_get_current_time();
100
101 timeout = MIN2(UINT64_MAX - current_time, timeout);
102
103 return current_time + timeout;
104 }
105
106 static int
107 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
108 {
109 struct mesa_sha1 ctx;
110 unsigned char sha1[20];
111 unsigned ptr_size = sizeof(void*);
112
113 memset(uuid, 0, VK_UUID_SIZE);
114 _mesa_sha1_init(&ctx);
115
116 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
117 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
118 return -1;
119
120 _mesa_sha1_update(&ctx, &family, sizeof(family));
121 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
122 _mesa_sha1_final(&ctx, sha1);
123
124 memcpy(uuid, sha1, VK_UUID_SIZE);
125 return 0;
126 }
127
128 static void
129 radv_get_driver_uuid(void *uuid)
130 {
131 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
132 }
133
134 static void
135 radv_get_device_uuid(struct radeon_info *info, void *uuid)
136 {
137 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
138 }
139
140 static uint64_t
141 radv_get_visible_vram_size(struct radv_physical_device *device)
142 {
143 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
144 }
145
146 static uint64_t
147 radv_get_vram_size(struct radv_physical_device *device)
148 {
149 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
150 }
151
152 static void
153 radv_physical_device_init_mem_types(struct radv_physical_device *device)
154 {
155 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
156 uint64_t vram_size = radv_get_vram_size(device);
157 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
158 device->memory_properties.memoryHeapCount = 0;
159 if (vram_size > 0) {
160 vram_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
162 .size = vram_size,
163 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 if (device->rad_info.gart_size > 0) {
168 gart_index = device->memory_properties.memoryHeapCount++;
169 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
170 .size = device->rad_info.gart_size,
171 .flags = 0,
172 };
173 }
174
175 if (visible_vram_size) {
176 visible_vram_index = device->memory_properties.memoryHeapCount++;
177 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
178 .size = visible_vram_size,
179 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
180 };
181 }
182
183 unsigned type_count = 0;
184
185 if (vram_index >= 0 || visible_vram_index >= 0) {
186 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
187 device->memory_flags[type_count] = RADEON_FLAG_NO_CPU_ACCESS;
188 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
189 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
190 .heapIndex = vram_index >= 0 ? vram_index : visible_vram_index,
191 };
192 }
193
194 if (gart_index >= 0) {
195 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
196 device->memory_flags[type_count] = RADEON_FLAG_GTT_WC | RADEON_FLAG_CPU_ACCESS;
197 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
198 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
199 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
200 .heapIndex = gart_index,
201 };
202 }
203 if (visible_vram_index >= 0) {
204 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
205 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
206 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
207 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
208 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
209 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
210 .heapIndex = visible_vram_index,
211 };
212 }
213
214 if (gart_index >= 0) {
215 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
216 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
217 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
218 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
219 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
220 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
221 .heapIndex = gart_index,
222 };
223 }
224 device->memory_properties.memoryTypeCount = type_count;
225
226 if (device->rad_info.has_l2_uncached) {
227 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
228 VkMemoryType mem_type = device->memory_properties.memoryTypes[i];
229
230 if ((mem_type.propertyFlags & (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
231 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)) ||
232 mem_type.propertyFlags == VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) {
233
234 VkMemoryPropertyFlags property_flags = mem_type.propertyFlags |
235 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD |
236 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD;
237
238 device->memory_domains[type_count] = device->memory_domains[i];
239 device->memory_flags[type_count] = device->memory_flags[i] | RADEON_FLAG_VA_UNCACHED;
240 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
241 .propertyFlags = property_flags,
242 .heapIndex = mem_type.heapIndex,
243 };
244 }
245 }
246 device->memory_properties.memoryTypeCount = type_count;
247 }
248 }
249
250 static const char *
251 radv_get_compiler_string(struct radv_physical_device *pdevice)
252 {
253 if (!pdevice->use_llvm) {
254 /* Some games like SotTR apply shader workarounds if the LLVM
255 * version is too old or if the LLVM version string is
256 * missing. This gives 2-5% performance with SotTR and ACO.
257 */
258 if (driQueryOptionb(&pdevice->instance->dri_options,
259 "radv_report_llvm9_version_string")) {
260 return "ACO/LLVM 9.0.1";
261 }
262
263 return "ACO";
264 }
265
266 return "LLVM " MESA_LLVM_VERSION_STRING;
267 }
268
269 static VkResult
270 radv_physical_device_try_create(struct radv_instance *instance,
271 drmDevicePtr drm_device,
272 struct radv_physical_device **device_out)
273 {
274 VkResult result;
275 int fd = -1;
276 int master_fd = -1;
277
278 if (drm_device) {
279 const char *path = drm_device->nodes[DRM_NODE_RENDER];
280 drmVersionPtr version;
281
282 fd = open(path, O_RDWR | O_CLOEXEC);
283 if (fd < 0) {
284 if (instance->debug_flags & RADV_DEBUG_STARTUP)
285 radv_logi("Could not open device '%s'", path);
286
287 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
288 }
289
290 version = drmGetVersion(fd);
291 if (!version) {
292 close(fd);
293
294 if (instance->debug_flags & RADV_DEBUG_STARTUP)
295 radv_logi("Could not get the kernel driver version for device '%s'", path);
296
297 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
298 "failed to get version %s: %m", path);
299 }
300
301 if (strcmp(version->name, "amdgpu")) {
302 drmFreeVersion(version);
303 close(fd);
304
305 if (instance->debug_flags & RADV_DEBUG_STARTUP)
306 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
307
308 return VK_ERROR_INCOMPATIBLE_DRIVER;
309 }
310 drmFreeVersion(version);
311
312 if (instance->debug_flags & RADV_DEBUG_STARTUP)
313 radv_logi("Found compatible device '%s'.", path);
314 }
315
316 struct radv_physical_device *device =
317 vk_zalloc2(&instance->alloc, NULL, sizeof(*device), 8,
318 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
319 if (!device) {
320 result = vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
321 goto fail_fd;
322 }
323
324 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
325 device->instance = instance;
326
327 if (drm_device) {
328 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
329 instance->perftest_flags);
330 } else {
331 device->ws = radv_null_winsys_create();
332 }
333
334 if (!device->ws) {
335 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
336 "failed to initialize winsys");
337 goto fail_alloc;
338 }
339
340 if (drm_device && instance->enabled_extensions.KHR_display) {
341 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
342 if (master_fd >= 0) {
343 uint32_t accel_working = 0;
344 struct drm_amdgpu_info request = {
345 .return_pointer = (uintptr_t)&accel_working,
346 .return_size = sizeof(accel_working),
347 .query = AMDGPU_INFO_ACCEL_WORKING
348 };
349
350 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
351 close(master_fd);
352 master_fd = -1;
353 }
354 }
355 }
356
357 device->master_fd = master_fd;
358 device->local_fd = fd;
359 device->ws->query_info(device->ws, &device->rad_info);
360
361 device->use_llvm = instance->debug_flags & RADV_DEBUG_LLVM;
362
363 snprintf(device->name, sizeof(device->name),
364 "AMD RADV %s (%s)",
365 device->rad_info.name, radv_get_compiler_string(device));
366
367 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
368 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
369 "cannot generate UUID");
370 goto fail_wsi;
371 }
372
373 /* These flags affect shader compilation. */
374 uint64_t shader_env_flags = (device->use_llvm ? 0 : 0x2);
375
376 /* The gpu id is already embedded in the uuid so we just pass "radv"
377 * when creating the cache.
378 */
379 char buf[VK_UUID_SIZE * 2 + 1];
380 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
381 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
382
383 if (device->rad_info.chip_class < GFX8 || !device->use_llvm)
384 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
385
386 radv_get_driver_uuid(&device->driver_uuid);
387 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
388
389 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
390 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
391
392 device->dcc_msaa_allowed =
393 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
394
395 device->use_ngg = device->rad_info.chip_class >= GFX10 &&
396 device->rad_info.family != CHIP_NAVI14 &&
397 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
398
399 /* TODO: Implement NGG GS with ACO. */
400 device->use_ngg_gs = device->use_ngg && device->use_llvm;
401 device->use_ngg_streamout = false;
402
403 /* Determine the number of threads per wave for all stages. */
404 device->cs_wave_size = 64;
405 device->ps_wave_size = 64;
406 device->ge_wave_size = 64;
407
408 if (device->rad_info.chip_class >= GFX10) {
409 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
410 device->cs_wave_size = 32;
411
412 /* For pixel shaders, wave64 is recommanded. */
413 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
414 device->ps_wave_size = 32;
415
416 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
417 device->ge_wave_size = 32;
418 }
419
420 radv_physical_device_init_mem_types(device);
421
422 radv_physical_device_get_supported_extensions(device,
423 &device->supported_extensions);
424
425 if (drm_device)
426 device->bus_info = *drm_device->businfo.pci;
427
428 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
429 ac_print_gpu_info(&device->rad_info);
430
431 /* The WSI is structured as a layer on top of the driver, so this has
432 * to be the last part of initialization (at least until we get other
433 * semi-layers).
434 */
435 result = radv_init_wsi(device);
436 if (result != VK_SUCCESS) {
437 vk_error(instance, result);
438 goto fail_disk_cache;
439 }
440
441 *device_out = device;
442
443 return VK_SUCCESS;
444
445 fail_disk_cache:
446 disk_cache_destroy(device->disk_cache);
447 fail_wsi:
448 device->ws->destroy(device->ws);
449 fail_alloc:
450 vk_free(&instance->alloc, device);
451 fail_fd:
452 if (fd != -1)
453 close(fd);
454 if (master_fd != -1)
455 close(master_fd);
456 return result;
457 }
458
459 static void
460 radv_physical_device_destroy(struct radv_physical_device *device)
461 {
462 radv_finish_wsi(device);
463 device->ws->destroy(device->ws);
464 disk_cache_destroy(device->disk_cache);
465 close(device->local_fd);
466 if (device->master_fd != -1)
467 close(device->master_fd);
468 vk_free(&device->instance->alloc, device);
469 }
470
471 static void *
472 default_alloc_func(void *pUserData, size_t size, size_t align,
473 VkSystemAllocationScope allocationScope)
474 {
475 return malloc(size);
476 }
477
478 static void *
479 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
480 size_t align, VkSystemAllocationScope allocationScope)
481 {
482 return realloc(pOriginal, size);
483 }
484
485 static void
486 default_free_func(void *pUserData, void *pMemory)
487 {
488 free(pMemory);
489 }
490
491 static const VkAllocationCallbacks default_alloc = {
492 .pUserData = NULL,
493 .pfnAllocation = default_alloc_func,
494 .pfnReallocation = default_realloc_func,
495 .pfnFree = default_free_func,
496 };
497
498 static const struct debug_control radv_debug_options[] = {
499 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
500 {"nodcc", RADV_DEBUG_NO_DCC},
501 {"shaders", RADV_DEBUG_DUMP_SHADERS},
502 {"nocache", RADV_DEBUG_NO_CACHE},
503 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
504 {"nohiz", RADV_DEBUG_NO_HIZ},
505 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
506 {"allbos", RADV_DEBUG_ALL_BOS},
507 {"noibs", RADV_DEBUG_NO_IBS},
508 {"spirv", RADV_DEBUG_DUMP_SPIRV},
509 {"vmfaults", RADV_DEBUG_VM_FAULTS},
510 {"zerovram", RADV_DEBUG_ZERO_VRAM},
511 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
512 {"preoptir", RADV_DEBUG_PREOPTIR},
513 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
514 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
515 {"info", RADV_DEBUG_INFO},
516 {"errors", RADV_DEBUG_ERRORS},
517 {"startup", RADV_DEBUG_STARTUP},
518 {"checkir", RADV_DEBUG_CHECKIR},
519 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
520 {"nobinning", RADV_DEBUG_NOBINNING},
521 {"nongg", RADV_DEBUG_NO_NGG},
522 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
523 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
524 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE},
525 {"llvm", RADV_DEBUG_LLVM},
526 {"forcecompress", RADV_DEBUG_FORCE_COMPRESS},
527 {NULL, 0}
528 };
529
530 const char *
531 radv_get_debug_option_name(int id)
532 {
533 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
534 return radv_debug_options[id].string;
535 }
536
537 static const struct debug_control radv_perftest_options[] = {
538 {"localbos", RADV_PERFTEST_LOCAL_BOS},
539 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
540 {"bolist", RADV_PERFTEST_BO_LIST},
541 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
542 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
543 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
544 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
545 {"dfsm", RADV_PERFTEST_DFSM},
546 {NULL, 0}
547 };
548
549 const char *
550 radv_get_perftest_option_name(int id)
551 {
552 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
553 return radv_perftest_options[id].string;
554 }
555
556 static void
557 radv_handle_per_app_options(struct radv_instance *instance,
558 const VkApplicationInfo *info)
559 {
560 const char *name = info ? info->pApplicationName : NULL;
561 const char *engine_name = info ? info->pEngineName : NULL;
562
563 if (name) {
564 if (!strcmp(name, "DOOM_VFR")) {
565 /* Work around a Doom VFR game bug */
566 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
567 } else if (!strcmp(name, "Fledge")) {
568 /*
569 * Zero VRAM for "The Surge 2"
570 *
571 * This avoid a hang when when rendering any level. Likely
572 * uninitialized data in an indirect draw.
573 */
574 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
575 } else if (!strcmp(name, "No Man's Sky")) {
576 /* Work around a NMS game bug */
577 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
578 } else if (!strcmp(name, "DOOMEternal")) {
579 /* Zero VRAM for Doom Eternal to fix rendering issues. */
580 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
581 } else if (!strcmp(name, "Red Dead Redemption 2")) {
582 /* Work around a RDR2 game bug */
583 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
584 }
585 }
586
587 if (engine_name) {
588 if (!strcmp(engine_name, "vkd3d")) {
589 /* Zero VRAM for all VKD3D (DX12->VK) games to fix
590 * rendering issues.
591 */
592 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
593 } else if (!strcmp(engine_name, "Quantic Dream Engine")) {
594 /* Fix various artifacts in Detroit: Become Human */
595 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM |
596 RADV_DEBUG_DISCARD_TO_DEMOTE;
597 }
598 }
599
600 instance->enable_mrt_output_nan_fixup =
601 driQueryOptionb(&instance->dri_options,
602 "radv_enable_mrt_output_nan_fixup");
603
604 if (driQueryOptionb(&instance->dri_options, "radv_no_dynamic_bounds"))
605 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
606 }
607
608 static const char radv_dri_options_xml[] =
609 DRI_CONF_BEGIN
610 DRI_CONF_SECTION_PERFORMANCE
611 DRI_CONF_ADAPTIVE_SYNC("true")
612 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
613 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
614 DRI_CONF_VK_X11_ENSURE_MIN_IMAGE_COUNT("false")
615 DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING("false")
616 DRI_CONF_RADV_ENABLE_MRT_OUTPUT_NAN_FIXUP("false")
617 DRI_CONF_RADV_NO_DYNAMIC_BOUNDS("false")
618 DRI_CONF_RADV_OVERRIDE_UNIFORM_OFFSET_ALIGNMENT(0)
619 DRI_CONF_SECTION_END
620
621 DRI_CONF_SECTION_DEBUG
622 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
623 DRI_CONF_SECTION_END
624 DRI_CONF_END;
625
626 static void radv_init_dri_options(struct radv_instance *instance)
627 {
628 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
629 driParseConfigFiles(&instance->dri_options,
630 &instance->available_dri_options,
631 0, "radv", NULL,
632 instance->applicationName,
633 instance->applicationVersion,
634 instance->engineName,
635 instance->engineVersion);
636 }
637
638 VkResult radv_CreateInstance(
639 const VkInstanceCreateInfo* pCreateInfo,
640 const VkAllocationCallbacks* pAllocator,
641 VkInstance* pInstance)
642 {
643 struct radv_instance *instance;
644 VkResult result;
645
646 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
647 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
648 if (!instance)
649 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
650
651 vk_object_base_init(NULL, &instance->base, VK_OBJECT_TYPE_INSTANCE);
652
653 if (pAllocator)
654 instance->alloc = *pAllocator;
655 else
656 instance->alloc = default_alloc;
657
658 if (pCreateInfo->pApplicationInfo) {
659 const VkApplicationInfo *app = pCreateInfo->pApplicationInfo;
660
661 instance->applicationName =
662 vk_strdup(&instance->alloc, app->pApplicationName,
663 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
664 instance->applicationVersion = app->applicationVersion;
665
666 instance->engineName =
667 vk_strdup(&instance->alloc, app->pEngineName,
668 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
669 instance->engineVersion = app->engineVersion;
670 instance->apiVersion = app->apiVersion;
671 }
672
673 if (instance->apiVersion == 0)
674 instance->apiVersion = VK_API_VERSION_1_0;
675
676 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
677 radv_debug_options);
678
679 const char *radv_perftest_str = getenv("RADV_PERFTEST");
680 instance->perftest_flags = parse_debug_string(radv_perftest_str,
681 radv_perftest_options);
682
683 if (radv_perftest_str) {
684 /* Output warnings for famous RADV_PERFTEST options that no
685 * longer exist or are deprecated.
686 */
687 if (strstr(radv_perftest_str, "aco")) {
688 fprintf(stderr, "*******************************************************************************\n");
689 fprintf(stderr, "* WARNING: Unknown option RADV_PERFTEST='aco'. ACO is enabled by default now. *\n");
690 fprintf(stderr, "*******************************************************************************\n");
691 }
692 if (strstr(radv_perftest_str, "llvm")) {
693 fprintf(stderr, "*********************************************************************************\n");
694 fprintf(stderr, "* WARNING: Unknown option 'RADV_PERFTEST=llvm'. Did you mean 'RADV_DEBUG=llvm'? *\n");
695 fprintf(stderr, "*********************************************************************************\n");
696 abort();
697 }
698 }
699
700 if (instance->debug_flags & RADV_DEBUG_STARTUP)
701 radv_logi("Created an instance");
702
703 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
704 int idx;
705 for (idx = 0; idx < RADV_INSTANCE_EXTENSION_COUNT; idx++) {
706 if (!strcmp(pCreateInfo->ppEnabledExtensionNames[i],
707 radv_instance_extensions[idx].extensionName))
708 break;
709 }
710
711 if (idx >= RADV_INSTANCE_EXTENSION_COUNT ||
712 !radv_instance_extensions_supported.extensions[idx]) {
713 vk_object_base_finish(&instance->base);
714 vk_free2(&default_alloc, pAllocator, instance);
715 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
716 }
717
718 instance->enabled_extensions.extensions[idx] = true;
719 }
720
721 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
722
723 for (unsigned i = 0; i < ARRAY_SIZE(instance->dispatch.entrypoints); i++) {
724 /* Vulkan requires that entrypoints for extensions which have
725 * not been enabled must not be advertised.
726 */
727 if (!unchecked &&
728 !radv_instance_entrypoint_is_enabled(i, instance->apiVersion,
729 &instance->enabled_extensions)) {
730 instance->dispatch.entrypoints[i] = NULL;
731 } else {
732 instance->dispatch.entrypoints[i] =
733 radv_instance_dispatch_table.entrypoints[i];
734 }
735 }
736
737 for (unsigned i = 0; i < ARRAY_SIZE(instance->physical_device_dispatch.entrypoints); i++) {
738 /* Vulkan requires that entrypoints for extensions which have
739 * not been enabled must not be advertised.
740 */
741 if (!unchecked &&
742 !radv_physical_device_entrypoint_is_enabled(i, instance->apiVersion,
743 &instance->enabled_extensions)) {
744 instance->physical_device_dispatch.entrypoints[i] = NULL;
745 } else {
746 instance->physical_device_dispatch.entrypoints[i] =
747 radv_physical_device_dispatch_table.entrypoints[i];
748 }
749 }
750
751 for (unsigned i = 0; i < ARRAY_SIZE(instance->device_dispatch.entrypoints); i++) {
752 /* Vulkan requires that entrypoints for extensions which have
753 * not been enabled must not be advertised.
754 */
755 if (!unchecked &&
756 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
757 &instance->enabled_extensions, NULL)) {
758 instance->device_dispatch.entrypoints[i] = NULL;
759 } else {
760 instance->device_dispatch.entrypoints[i] =
761 radv_device_dispatch_table.entrypoints[i];
762 }
763 }
764
765 instance->physical_devices_enumerated = false;
766 list_inithead(&instance->physical_devices);
767
768 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
769 if (result != VK_SUCCESS) {
770 vk_object_base_finish(&instance->base);
771 vk_free2(&default_alloc, pAllocator, instance);
772 return vk_error(instance, result);
773 }
774
775 glsl_type_singleton_init_or_ref();
776
777 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
778
779 radv_init_dri_options(instance);
780 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
781
782 *pInstance = radv_instance_to_handle(instance);
783
784 return VK_SUCCESS;
785 }
786
787 void radv_DestroyInstance(
788 VkInstance _instance,
789 const VkAllocationCallbacks* pAllocator)
790 {
791 RADV_FROM_HANDLE(radv_instance, instance, _instance);
792
793 if (!instance)
794 return;
795
796 list_for_each_entry_safe(struct radv_physical_device, pdevice,
797 &instance->physical_devices, link) {
798 radv_physical_device_destroy(pdevice);
799 }
800
801 vk_free(&instance->alloc, instance->engineName);
802 vk_free(&instance->alloc, instance->applicationName);
803
804 VG(VALGRIND_DESTROY_MEMPOOL(instance));
805
806 glsl_type_singleton_decref();
807
808 driDestroyOptionCache(&instance->dri_options);
809 driDestroyOptionInfo(&instance->available_dri_options);
810
811 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
812
813 vk_object_base_finish(&instance->base);
814 vk_free(&instance->alloc, instance);
815 }
816
817 static VkResult
818 radv_enumerate_physical_devices(struct radv_instance *instance)
819 {
820 if (instance->physical_devices_enumerated)
821 return VK_SUCCESS;
822
823 instance->physical_devices_enumerated = true;
824
825 /* TODO: Check for more devices ? */
826 drmDevicePtr devices[8];
827 VkResult result = VK_SUCCESS;
828 int max_devices;
829
830 if (getenv("RADV_FORCE_FAMILY")) {
831 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
832 * device that allows to test the compiler without having an
833 * AMDGPU instance.
834 */
835 struct radv_physical_device *pdevice;
836
837 result = radv_physical_device_try_create(instance, NULL, &pdevice);
838 if (result != VK_SUCCESS)
839 return result;
840
841 list_addtail(&pdevice->link, &instance->physical_devices);
842 return VK_SUCCESS;
843 }
844
845 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
846
847 if (instance->debug_flags & RADV_DEBUG_STARTUP)
848 radv_logi("Found %d drm nodes", max_devices);
849
850 if (max_devices < 1)
851 return vk_error(instance, VK_SUCCESS);
852
853 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
854 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
855 devices[i]->bustype == DRM_BUS_PCI &&
856 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
857
858 struct radv_physical_device *pdevice;
859 result = radv_physical_device_try_create(instance, devices[i],
860 &pdevice);
861 /* Incompatible DRM device, skip. */
862 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
863 result = VK_SUCCESS;
864 continue;
865 }
866
867 /* Error creating the physical device, report the error. */
868 if (result != VK_SUCCESS)
869 break;
870
871 list_addtail(&pdevice->link, &instance->physical_devices);
872 }
873 }
874 drmFreeDevices(devices, max_devices);
875
876 /* If we successfully enumerated any devices, call it success */
877 return result;
878 }
879
880 VkResult radv_EnumeratePhysicalDevices(
881 VkInstance _instance,
882 uint32_t* pPhysicalDeviceCount,
883 VkPhysicalDevice* pPhysicalDevices)
884 {
885 RADV_FROM_HANDLE(radv_instance, instance, _instance);
886 VK_OUTARRAY_MAKE(out, pPhysicalDevices, pPhysicalDeviceCount);
887
888 VkResult result = radv_enumerate_physical_devices(instance);
889 if (result != VK_SUCCESS)
890 return result;
891
892 list_for_each_entry(struct radv_physical_device, pdevice,
893 &instance->physical_devices, link) {
894 vk_outarray_append(&out, i) {
895 *i = radv_physical_device_to_handle(pdevice);
896 }
897 }
898
899 return vk_outarray_status(&out);
900 }
901
902 VkResult radv_EnumeratePhysicalDeviceGroups(
903 VkInstance _instance,
904 uint32_t* pPhysicalDeviceGroupCount,
905 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
906 {
907 RADV_FROM_HANDLE(radv_instance, instance, _instance);
908 VK_OUTARRAY_MAKE(out, pPhysicalDeviceGroupProperties,
909 pPhysicalDeviceGroupCount);
910
911 VkResult result = radv_enumerate_physical_devices(instance);
912 if (result != VK_SUCCESS)
913 return result;
914
915 list_for_each_entry(struct radv_physical_device, pdevice,
916 &instance->physical_devices, link) {
917 vk_outarray_append(&out, p) {
918 p->physicalDeviceCount = 1;
919 memset(p->physicalDevices, 0, sizeof(p->physicalDevices));
920 p->physicalDevices[0] = radv_physical_device_to_handle(pdevice);
921 p->subsetAllocation = false;
922 }
923 }
924
925 return vk_outarray_status(&out);
926 }
927
928 void radv_GetPhysicalDeviceFeatures(
929 VkPhysicalDevice physicalDevice,
930 VkPhysicalDeviceFeatures* pFeatures)
931 {
932 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
933 memset(pFeatures, 0, sizeof(*pFeatures));
934
935 *pFeatures = (VkPhysicalDeviceFeatures) {
936 .robustBufferAccess = true,
937 .fullDrawIndexUint32 = true,
938 .imageCubeArray = true,
939 .independentBlend = true,
940 .geometryShader = true,
941 .tessellationShader = true,
942 .sampleRateShading = true,
943 .dualSrcBlend = true,
944 .logicOp = true,
945 .multiDrawIndirect = true,
946 .drawIndirectFirstInstance = true,
947 .depthClamp = true,
948 .depthBiasClamp = true,
949 .fillModeNonSolid = true,
950 .depthBounds = true,
951 .wideLines = true,
952 .largePoints = true,
953 .alphaToOne = true,
954 .multiViewport = true,
955 .samplerAnisotropy = true,
956 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
957 .textureCompressionASTC_LDR = false,
958 .textureCompressionBC = true,
959 .occlusionQueryPrecise = true,
960 .pipelineStatisticsQuery = true,
961 .vertexPipelineStoresAndAtomics = true,
962 .fragmentStoresAndAtomics = true,
963 .shaderTessellationAndGeometryPointSize = true,
964 .shaderImageGatherExtended = true,
965 .shaderStorageImageExtendedFormats = true,
966 .shaderStorageImageMultisample = true,
967 .shaderUniformBufferArrayDynamicIndexing = true,
968 .shaderSampledImageArrayDynamicIndexing = true,
969 .shaderStorageBufferArrayDynamicIndexing = true,
970 .shaderStorageImageArrayDynamicIndexing = true,
971 .shaderStorageImageReadWithoutFormat = true,
972 .shaderStorageImageWriteWithoutFormat = true,
973 .shaderClipDistance = true,
974 .shaderCullDistance = true,
975 .shaderFloat64 = true,
976 .shaderInt64 = true,
977 .shaderInt16 = true,
978 .sparseBinding = true,
979 .variableMultisampleRate = true,
980 .shaderResourceMinLod = true,
981 .inheritedQueries = true,
982 };
983 }
984
985 static void
986 radv_get_physical_device_features_1_1(struct radv_physical_device *pdevice,
987 VkPhysicalDeviceVulkan11Features *f)
988 {
989 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES);
990
991 f->storageBuffer16BitAccess = true;
992 f->uniformAndStorageBuffer16BitAccess = true;
993 f->storagePushConstant16 = true;
994 f->storageInputOutput16 = pdevice->rad_info.has_packed_math_16bit && (LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm);
995 f->multiview = true;
996 f->multiviewGeometryShader = true;
997 f->multiviewTessellationShader = true;
998 f->variablePointersStorageBuffer = true;
999 f->variablePointers = true;
1000 f->protectedMemory = false;
1001 f->samplerYcbcrConversion = true;
1002 f->shaderDrawParameters = true;
1003 }
1004
1005 static void
1006 radv_get_physical_device_features_1_2(struct radv_physical_device *pdevice,
1007 VkPhysicalDeviceVulkan12Features *f)
1008 {
1009 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES);
1010
1011 f->samplerMirrorClampToEdge = true;
1012 f->drawIndirectCount = true;
1013 f->storageBuffer8BitAccess = true;
1014 f->uniformAndStorageBuffer8BitAccess = true;
1015 f->storagePushConstant8 = true;
1016 f->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1017 f->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1018 f->shaderFloat16 = pdevice->rad_info.has_packed_math_16bit;
1019 f->shaderInt8 = true;
1020
1021 f->descriptorIndexing = true;
1022 f->shaderInputAttachmentArrayDynamicIndexing = true;
1023 f->shaderUniformTexelBufferArrayDynamicIndexing = true;
1024 f->shaderStorageTexelBufferArrayDynamicIndexing = true;
1025 f->shaderUniformBufferArrayNonUniformIndexing = true;
1026 f->shaderSampledImageArrayNonUniformIndexing = true;
1027 f->shaderStorageBufferArrayNonUniformIndexing = true;
1028 f->shaderStorageImageArrayNonUniformIndexing = true;
1029 f->shaderInputAttachmentArrayNonUniformIndexing = true;
1030 f->shaderUniformTexelBufferArrayNonUniformIndexing = true;
1031 f->shaderStorageTexelBufferArrayNonUniformIndexing = true;
1032 f->descriptorBindingUniformBufferUpdateAfterBind = true;
1033 f->descriptorBindingSampledImageUpdateAfterBind = true;
1034 f->descriptorBindingStorageImageUpdateAfterBind = true;
1035 f->descriptorBindingStorageBufferUpdateAfterBind = true;
1036 f->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
1037 f->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
1038 f->descriptorBindingUpdateUnusedWhilePending = true;
1039 f->descriptorBindingPartiallyBound = true;
1040 f->descriptorBindingVariableDescriptorCount = true;
1041 f->runtimeDescriptorArray = true;
1042
1043 f->samplerFilterMinmax = true;
1044 f->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
1045 f->imagelessFramebuffer = true;
1046 f->uniformBufferStandardLayout = true;
1047 f->shaderSubgroupExtendedTypes = true;
1048 f->separateDepthStencilLayouts = true;
1049 f->hostQueryReset = true;
1050 f->timelineSemaphore = pdevice->rad_info.has_syncobj_wait_for_submit;
1051 f->bufferDeviceAddress = true;
1052 f->bufferDeviceAddressCaptureReplay = false;
1053 f->bufferDeviceAddressMultiDevice = false;
1054 f->vulkanMemoryModel = true;
1055 f->vulkanMemoryModelDeviceScope = true;
1056 f->vulkanMemoryModelAvailabilityVisibilityChains = false;
1057 f->shaderOutputViewportIndex = true;
1058 f->shaderOutputLayer = true;
1059 f->subgroupBroadcastDynamicId = true;
1060 }
1061
1062 void radv_GetPhysicalDeviceFeatures2(
1063 VkPhysicalDevice physicalDevice,
1064 VkPhysicalDeviceFeatures2 *pFeatures)
1065 {
1066 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1067 radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1068
1069 VkPhysicalDeviceVulkan11Features core_1_1 = {
1070 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES,
1071 };
1072 radv_get_physical_device_features_1_1(pdevice, &core_1_1);
1073
1074 VkPhysicalDeviceVulkan12Features core_1_2 = {
1075 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES,
1076 };
1077 radv_get_physical_device_features_1_2(pdevice, &core_1_2);
1078
1079 #define CORE_FEATURE(major, minor, feature) \
1080 features->feature = core_##major##_##minor.feature
1081
1082 vk_foreach_struct(ext, pFeatures->pNext) {
1083 switch (ext->sType) {
1084 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
1085 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
1086 CORE_FEATURE(1, 1, variablePointersStorageBuffer);
1087 CORE_FEATURE(1, 1, variablePointers);
1088 break;
1089 }
1090 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
1091 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
1092 CORE_FEATURE(1, 1, multiview);
1093 CORE_FEATURE(1, 1, multiviewGeometryShader);
1094 CORE_FEATURE(1, 1, multiviewTessellationShader);
1095 break;
1096 }
1097 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
1098 VkPhysicalDeviceShaderDrawParametersFeatures *features =
1099 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
1100 CORE_FEATURE(1, 1, shaderDrawParameters);
1101 break;
1102 }
1103 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
1104 VkPhysicalDeviceProtectedMemoryFeatures *features =
1105 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
1106 CORE_FEATURE(1, 1, protectedMemory);
1107 break;
1108 }
1109 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
1110 VkPhysicalDevice16BitStorageFeatures *features =
1111 (VkPhysicalDevice16BitStorageFeatures*)ext;
1112 CORE_FEATURE(1, 1, storageBuffer16BitAccess);
1113 CORE_FEATURE(1, 1, uniformAndStorageBuffer16BitAccess);
1114 CORE_FEATURE(1, 1, storagePushConstant16);
1115 CORE_FEATURE(1, 1, storageInputOutput16);
1116 break;
1117 }
1118 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
1119 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
1120 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
1121 CORE_FEATURE(1, 1, samplerYcbcrConversion);
1122 break;
1123 }
1124 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES: {
1125 VkPhysicalDeviceDescriptorIndexingFeatures *features =
1126 (VkPhysicalDeviceDescriptorIndexingFeatures*)ext;
1127 CORE_FEATURE(1, 2, shaderInputAttachmentArrayDynamicIndexing);
1128 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayDynamicIndexing);
1129 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayDynamicIndexing);
1130 CORE_FEATURE(1, 2, shaderUniformBufferArrayNonUniformIndexing);
1131 CORE_FEATURE(1, 2, shaderSampledImageArrayNonUniformIndexing);
1132 CORE_FEATURE(1, 2, shaderStorageBufferArrayNonUniformIndexing);
1133 CORE_FEATURE(1, 2, shaderStorageImageArrayNonUniformIndexing);
1134 CORE_FEATURE(1, 2, shaderInputAttachmentArrayNonUniformIndexing);
1135 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayNonUniformIndexing);
1136 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayNonUniformIndexing);
1137 CORE_FEATURE(1, 2, descriptorBindingUniformBufferUpdateAfterBind);
1138 CORE_FEATURE(1, 2, descriptorBindingSampledImageUpdateAfterBind);
1139 CORE_FEATURE(1, 2, descriptorBindingStorageImageUpdateAfterBind);
1140 CORE_FEATURE(1, 2, descriptorBindingStorageBufferUpdateAfterBind);
1141 CORE_FEATURE(1, 2, descriptorBindingUniformTexelBufferUpdateAfterBind);
1142 CORE_FEATURE(1, 2, descriptorBindingStorageTexelBufferUpdateAfterBind);
1143 CORE_FEATURE(1, 2, descriptorBindingUpdateUnusedWhilePending);
1144 CORE_FEATURE(1, 2, descriptorBindingPartiallyBound);
1145 CORE_FEATURE(1, 2, descriptorBindingVariableDescriptorCount);
1146 CORE_FEATURE(1, 2, runtimeDescriptorArray);
1147 break;
1148 }
1149 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
1150 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
1151 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
1152 features->conditionalRendering = true;
1153 features->inheritedConditionalRendering = false;
1154 break;
1155 }
1156 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
1157 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
1158 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
1159 features->vertexAttributeInstanceRateDivisor = true;
1160 features->vertexAttributeInstanceRateZeroDivisor = true;
1161 break;
1162 }
1163 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
1164 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
1165 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
1166 features->transformFeedback = true;
1167 features->geometryStreams = !pdevice->use_ngg_streamout;
1168 break;
1169 }
1170 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES: {
1171 VkPhysicalDeviceScalarBlockLayoutFeatures *features =
1172 (VkPhysicalDeviceScalarBlockLayoutFeatures *)ext;
1173 CORE_FEATURE(1, 2, scalarBlockLayout);
1174 break;
1175 }
1176 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
1177 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
1178 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
1179 features->memoryPriority = true;
1180 break;
1181 }
1182 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
1183 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
1184 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
1185 features->bufferDeviceAddress = true;
1186 features->bufferDeviceAddressCaptureReplay = false;
1187 features->bufferDeviceAddressMultiDevice = false;
1188 break;
1189 }
1190 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES: {
1191 VkPhysicalDeviceBufferDeviceAddressFeatures *features =
1192 (VkPhysicalDeviceBufferDeviceAddressFeatures *)ext;
1193 CORE_FEATURE(1, 2, bufferDeviceAddress);
1194 CORE_FEATURE(1, 2, bufferDeviceAddressCaptureReplay);
1195 CORE_FEATURE(1, 2, bufferDeviceAddressMultiDevice);
1196 break;
1197 }
1198 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
1199 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
1200 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
1201 features->depthClipEnable = true;
1202 break;
1203 }
1204 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES: {
1205 VkPhysicalDeviceHostQueryResetFeatures *features =
1206 (VkPhysicalDeviceHostQueryResetFeatures *)ext;
1207 CORE_FEATURE(1, 2, hostQueryReset);
1208 break;
1209 }
1210 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES: {
1211 VkPhysicalDevice8BitStorageFeatures *features =
1212 (VkPhysicalDevice8BitStorageFeatures *)ext;
1213 CORE_FEATURE(1, 2, storageBuffer8BitAccess);
1214 CORE_FEATURE(1, 2, uniformAndStorageBuffer8BitAccess);
1215 CORE_FEATURE(1, 2, storagePushConstant8);
1216 break;
1217 }
1218 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES: {
1219 VkPhysicalDeviceShaderFloat16Int8Features *features =
1220 (VkPhysicalDeviceShaderFloat16Int8Features*)ext;
1221 CORE_FEATURE(1, 2, shaderFloat16);
1222 CORE_FEATURE(1, 2, shaderInt8);
1223 break;
1224 }
1225 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES: {
1226 VkPhysicalDeviceShaderAtomicInt64Features *features =
1227 (VkPhysicalDeviceShaderAtomicInt64Features *)ext;
1228 CORE_FEATURE(1, 2, shaderBufferInt64Atomics);
1229 CORE_FEATURE(1, 2, shaderSharedInt64Atomics);
1230 break;
1231 }
1232 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
1233 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
1234 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
1235 features->shaderDemoteToHelperInvocation = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1236 break;
1237 }
1238 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
1239 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
1240 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
1241
1242 features->inlineUniformBlock = true;
1243 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1244 break;
1245 }
1246 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1247 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1248 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1249 features->computeDerivativeGroupQuads = false;
1250 features->computeDerivativeGroupLinear = true;
1251 break;
1252 }
1253 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1254 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1255 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1256 features->ycbcrImageArrays = true;
1257 break;
1258 }
1259 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES: {
1260 VkPhysicalDeviceUniformBufferStandardLayoutFeatures *features =
1261 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures *)ext;
1262 CORE_FEATURE(1, 2, uniformBufferStandardLayout);
1263 break;
1264 }
1265 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1266 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1267 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1268 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1269 break;
1270 }
1271 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES: {
1272 VkPhysicalDeviceImagelessFramebufferFeatures *features =
1273 (VkPhysicalDeviceImagelessFramebufferFeatures *)ext;
1274 CORE_FEATURE(1, 2, imagelessFramebuffer);
1275 break;
1276 }
1277 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1278 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1279 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1280 features->pipelineExecutableInfo = true;
1281 break;
1282 }
1283 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR: {
1284 VkPhysicalDeviceShaderClockFeaturesKHR *features =
1285 (VkPhysicalDeviceShaderClockFeaturesKHR *)ext;
1286 features->shaderSubgroupClock = true;
1287 features->shaderDeviceClock = pdevice->rad_info.chip_class >= GFX8;
1288 break;
1289 }
1290 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
1291 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
1292 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
1293 features->texelBufferAlignment = true;
1294 break;
1295 }
1296 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES: {
1297 VkPhysicalDeviceTimelineSemaphoreFeatures *features =
1298 (VkPhysicalDeviceTimelineSemaphoreFeatures *) ext;
1299 CORE_FEATURE(1, 2, timelineSemaphore);
1300 break;
1301 }
1302 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT: {
1303 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *features =
1304 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *)ext;
1305 features->subgroupSizeControl = true;
1306 features->computeFullSubgroups = true;
1307 break;
1308 }
1309 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD: {
1310 VkPhysicalDeviceCoherentMemoryFeaturesAMD *features =
1311 (VkPhysicalDeviceCoherentMemoryFeaturesAMD *)ext;
1312 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1313 break;
1314 }
1315 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES: {
1316 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *features =
1317 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *)ext;
1318 CORE_FEATURE(1, 2, shaderSubgroupExtendedTypes);
1319 break;
1320 }
1321 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR: {
1322 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *features =
1323 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *)ext;
1324 CORE_FEATURE(1, 2, separateDepthStencilLayouts);
1325 break;
1326 }
1327 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES: {
1328 radv_get_physical_device_features_1_1(pdevice, (void *)ext);
1329 break;
1330 }
1331 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES: {
1332 radv_get_physical_device_features_1_2(pdevice, (void *)ext);
1333 break;
1334 }
1335 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT: {
1336 VkPhysicalDeviceLineRasterizationFeaturesEXT *features =
1337 (VkPhysicalDeviceLineRasterizationFeaturesEXT *)ext;
1338 features->rectangularLines = false;
1339 features->bresenhamLines = true;
1340 features->smoothLines = false;
1341 features->stippledRectangularLines = false;
1342 features->stippledBresenhamLines = true;
1343 features->stippledSmoothLines = false;
1344 break;
1345 }
1346 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
1347 VkDeviceMemoryOverallocationCreateInfoAMD *features =
1348 (VkDeviceMemoryOverallocationCreateInfoAMD *)ext;
1349 features->overallocationBehavior = true;
1350 break;
1351 }
1352 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_FEATURES_EXT: {
1353 VkPhysicalDeviceRobustness2FeaturesEXT *features =
1354 (VkPhysicalDeviceRobustness2FeaturesEXT *)ext;
1355 features->robustBufferAccess2 = true;
1356 features->robustImageAccess2 = true;
1357 features->nullDescriptor = true;
1358 break;
1359 }
1360 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
1361 VkPhysicalDeviceCustomBorderColorFeaturesEXT *features =
1362 (VkPhysicalDeviceCustomBorderColorFeaturesEXT *)ext;
1363 features->customBorderColors = true;
1364 features->customBorderColorWithoutFormat = true;
1365 break;
1366 }
1367 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PRIVATE_DATA_FEATURES_EXT: {
1368 VkPhysicalDevicePrivateDataFeaturesEXT *features =
1369 (VkPhysicalDevicePrivateDataFeaturesEXT *)ext;
1370 features->privateData = true;
1371 break;
1372 }
1373 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_CREATION_CACHE_CONTROL_FEATURES_EXT: {
1374 VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *features =
1375 (VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *)ext;
1376 features-> pipelineCreationCacheControl = true;
1377 break;
1378 }
1379 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_MEMORY_MODEL_FEATURES_KHR: {
1380 VkPhysicalDeviceVulkanMemoryModelFeaturesKHR *features =
1381 (VkPhysicalDeviceVulkanMemoryModelFeaturesKHR *)ext;
1382 CORE_FEATURE(1, 2, vulkanMemoryModel);
1383 CORE_FEATURE(1, 2, vulkanMemoryModelDeviceScope);
1384 CORE_FEATURE(1, 2, vulkanMemoryModelAvailabilityVisibilityChains);
1385 break;
1386 }
1387 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTENDED_DYNAMIC_STATE_FEATURES_EXT: {
1388 VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *features =
1389 (VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *) ext;
1390 features->extendedDynamicState = true;
1391 break;
1392 }
1393 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_ROBUSTNESS_FEATURES_EXT: {
1394 VkPhysicalDeviceImageRobustnessFeaturesEXT *features =
1395 (VkPhysicalDeviceImageRobustnessFeaturesEXT *)ext;
1396 features->robustImageAccess = true;
1397 break;
1398 }
1399 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_FLOAT_FEATURES_EXT: {
1400 VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *features =
1401 (VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *)ext;
1402 features->shaderBufferFloat32Atomics = true;
1403 features->shaderBufferFloat32AtomicAdd = false;
1404 features->shaderBufferFloat64Atomics = true;
1405 features->shaderBufferFloat64AtomicAdd = false;
1406 features->shaderSharedFloat32Atomics = true;
1407 features->shaderSharedFloat32AtomicAdd = pdevice->rad_info.chip_class >= GFX8 &&
1408 (!pdevice->use_llvm || LLVM_VERSION_MAJOR >= 10);
1409 features->shaderSharedFloat64Atomics = true;
1410 features->shaderSharedFloat64AtomicAdd = false;
1411 features->shaderImageFloat32Atomics = true;
1412 features->shaderImageFloat32AtomicAdd = false;
1413 features->sparseImageFloat32Atomics = false;
1414 features->sparseImageFloat32AtomicAdd = false;
1415 break;
1416 }
1417 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_4444_FORMATS_FEATURES_EXT: {
1418 VkPhysicalDevice4444FormatsFeaturesEXT *features =
1419 (VkPhysicalDevice4444FormatsFeaturesEXT *)ext;
1420 features->formatA4R4G4B4 = true;
1421 features->formatA4B4G4R4 = true;
1422 break;
1423 }
1424 default:
1425 break;
1426 }
1427 }
1428 #undef CORE_FEATURE
1429 }
1430
1431 static size_t
1432 radv_max_descriptor_set_size()
1433 {
1434 /* make sure that the entire descriptor set is addressable with a signed
1435 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1436 * be at most 2 GiB. the combined image & samples object count as one of
1437 * both. This limit is for the pipeline layout, not for the set layout, but
1438 * there is no set limit, so we just set a pipeline limit. I don't think
1439 * any app is going to hit this soon. */
1440 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1441 - MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1442 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1443 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1444 32 /* sampler, largest when combined with image */ +
1445 64 /* sampled image */ +
1446 64 /* storage image */);
1447 }
1448
1449 static uint32_t
1450 radv_uniform_buffer_offset_alignment(const struct radv_physical_device *pdevice)
1451 {
1452 uint32_t uniform_offset_alignment = driQueryOptioni(&pdevice->instance->dri_options,
1453 "radv_override_uniform_offset_alignment");
1454 if (!util_is_power_of_two_or_zero(uniform_offset_alignment)) {
1455 fprintf(stderr, "ERROR: invalid radv_override_uniform_offset_alignment setting %d:"
1456 "not a power of two\n", uniform_offset_alignment);
1457 uniform_offset_alignment = 0;
1458 }
1459
1460 /* Take at least the hardware limit. */
1461 return MAX2(uniform_offset_alignment, 4);
1462 }
1463
1464 void radv_GetPhysicalDeviceProperties(
1465 VkPhysicalDevice physicalDevice,
1466 VkPhysicalDeviceProperties* pProperties)
1467 {
1468 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1469 VkSampleCountFlags sample_counts = 0xf;
1470
1471 size_t max_descriptor_set_size = radv_max_descriptor_set_size();
1472
1473 VkPhysicalDeviceLimits limits = {
1474 .maxImageDimension1D = (1 << 14),
1475 .maxImageDimension2D = (1 << 14),
1476 .maxImageDimension3D = (1 << 11),
1477 .maxImageDimensionCube = (1 << 14),
1478 .maxImageArrayLayers = (1 << 11),
1479 .maxTexelBufferElements = UINT32_MAX,
1480 .maxUniformBufferRange = UINT32_MAX,
1481 .maxStorageBufferRange = UINT32_MAX,
1482 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1483 .maxMemoryAllocationCount = UINT32_MAX,
1484 .maxSamplerAllocationCount = 64 * 1024,
1485 .bufferImageGranularity = 64, /* A cache line */
1486 .sparseAddressSpaceSize = RADV_MAX_MEMORY_ALLOCATION_SIZE, /* buffer max size */
1487 .maxBoundDescriptorSets = MAX_SETS,
1488 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1489 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1490 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1491 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1492 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1493 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1494 .maxPerStageResources = max_descriptor_set_size,
1495 .maxDescriptorSetSamplers = max_descriptor_set_size,
1496 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1497 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1498 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1499 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1500 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1501 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1502 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1503 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1504 .maxVertexInputBindings = MAX_VBS,
1505 .maxVertexInputAttributeOffset = 2047,
1506 .maxVertexInputBindingStride = 2048,
1507 .maxVertexOutputComponents = 128,
1508 .maxTessellationGenerationLevel = 64,
1509 .maxTessellationPatchSize = 32,
1510 .maxTessellationControlPerVertexInputComponents = 128,
1511 .maxTessellationControlPerVertexOutputComponents = 128,
1512 .maxTessellationControlPerPatchOutputComponents = 120,
1513 .maxTessellationControlTotalOutputComponents = 4096,
1514 .maxTessellationEvaluationInputComponents = 128,
1515 .maxTessellationEvaluationOutputComponents = 128,
1516 .maxGeometryShaderInvocations = 127,
1517 .maxGeometryInputComponents = 64,
1518 .maxGeometryOutputComponents = 128,
1519 .maxGeometryOutputVertices = 256,
1520 .maxGeometryTotalOutputComponents = 1024,
1521 .maxFragmentInputComponents = 128,
1522 .maxFragmentOutputAttachments = 8,
1523 .maxFragmentDualSrcAttachments = 1,
1524 .maxFragmentCombinedOutputResources = 8,
1525 .maxComputeSharedMemorySize = 32768,
1526 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1527 .maxComputeWorkGroupInvocations = 1024,
1528 .maxComputeWorkGroupSize = {
1529 1024,
1530 1024,
1531 1024
1532 },
1533 .subPixelPrecisionBits = 8,
1534 .subTexelPrecisionBits = 8,
1535 .mipmapPrecisionBits = 8,
1536 .maxDrawIndexedIndexValue = UINT32_MAX,
1537 .maxDrawIndirectCount = UINT32_MAX,
1538 .maxSamplerLodBias = 16,
1539 .maxSamplerAnisotropy = 16,
1540 .maxViewports = MAX_VIEWPORTS,
1541 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1542 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1543 .viewportSubPixelBits = 8,
1544 .minMemoryMapAlignment = 4096, /* A page */
1545 .minTexelBufferOffsetAlignment = 4,
1546 .minUniformBufferOffsetAlignment = radv_uniform_buffer_offset_alignment(pdevice),
1547 .minStorageBufferOffsetAlignment = 4,
1548 .minTexelOffset = -32,
1549 .maxTexelOffset = 31,
1550 .minTexelGatherOffset = -32,
1551 .maxTexelGatherOffset = 31,
1552 .minInterpolationOffset = -2,
1553 .maxInterpolationOffset = 2,
1554 .subPixelInterpolationOffsetBits = 8,
1555 .maxFramebufferWidth = (1 << 14),
1556 .maxFramebufferHeight = (1 << 14),
1557 .maxFramebufferLayers = (1 << 10),
1558 .framebufferColorSampleCounts = sample_counts,
1559 .framebufferDepthSampleCounts = sample_counts,
1560 .framebufferStencilSampleCounts = sample_counts,
1561 .framebufferNoAttachmentsSampleCounts = sample_counts,
1562 .maxColorAttachments = MAX_RTS,
1563 .sampledImageColorSampleCounts = sample_counts,
1564 .sampledImageIntegerSampleCounts = sample_counts,
1565 .sampledImageDepthSampleCounts = sample_counts,
1566 .sampledImageStencilSampleCounts = sample_counts,
1567 .storageImageSampleCounts = sample_counts,
1568 .maxSampleMaskWords = 1,
1569 .timestampComputeAndGraphics = true,
1570 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1571 .maxClipDistances = 8,
1572 .maxCullDistances = 8,
1573 .maxCombinedClipAndCullDistances = 8,
1574 .discreteQueuePriorities = 2,
1575 .pointSizeRange = { 0.0, 8191.875 },
1576 .lineWidthRange = { 0.0, 8191.875 },
1577 .pointSizeGranularity = (1.0 / 8.0),
1578 .lineWidthGranularity = (1.0 / 8.0),
1579 .strictLines = false, /* FINISHME */
1580 .standardSampleLocations = true,
1581 .optimalBufferCopyOffsetAlignment = 128,
1582 .optimalBufferCopyRowPitchAlignment = 128,
1583 .nonCoherentAtomSize = 64,
1584 };
1585
1586 *pProperties = (VkPhysicalDeviceProperties) {
1587 .apiVersion = radv_physical_device_api_version(pdevice),
1588 .driverVersion = vk_get_driver_version(),
1589 .vendorID = ATI_VENDOR_ID,
1590 .deviceID = pdevice->rad_info.pci_id,
1591 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1592 .limits = limits,
1593 .sparseProperties = {0},
1594 };
1595
1596 strcpy(pProperties->deviceName, pdevice->name);
1597 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1598 }
1599
1600 static void
1601 radv_get_physical_device_properties_1_1(struct radv_physical_device *pdevice,
1602 VkPhysicalDeviceVulkan11Properties *p)
1603 {
1604 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES);
1605
1606 memcpy(p->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1607 memcpy(p->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1608 memset(p->deviceLUID, 0, VK_LUID_SIZE);
1609 /* The LUID is for Windows. */
1610 p->deviceLUIDValid = false;
1611 p->deviceNodeMask = 0;
1612
1613 p->subgroupSize = RADV_SUBGROUP_SIZE;
1614 p->subgroupSupportedStages = VK_SHADER_STAGE_ALL_GRAPHICS |
1615 VK_SHADER_STAGE_COMPUTE_BIT;
1616 p->subgroupSupportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT |
1617 VK_SUBGROUP_FEATURE_VOTE_BIT |
1618 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1619 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1620 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1621 VK_SUBGROUP_FEATURE_QUAD_BIT |
1622 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1623 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1624 p->subgroupQuadOperationsInAllStages = true;
1625
1626 p->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1627 p->maxMultiviewViewCount = MAX_VIEWS;
1628 p->maxMultiviewInstanceIndex = INT_MAX;
1629 p->protectedNoFault = false;
1630 p->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
1631 p->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
1632 }
1633
1634 static void
1635 radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
1636 VkPhysicalDeviceVulkan12Properties *p)
1637 {
1638 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES);
1639
1640 p->driverID = VK_DRIVER_ID_MESA_RADV;
1641 snprintf(p->driverName, VK_MAX_DRIVER_NAME_SIZE, "radv");
1642 snprintf(p->driverInfo, VK_MAX_DRIVER_INFO_SIZE,
1643 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1 " (%s)",
1644 radv_get_compiler_string(pdevice));
1645 p->conformanceVersion = (VkConformanceVersion) {
1646 .major = 1,
1647 .minor = 2,
1648 .subminor = 0,
1649 .patch = 0,
1650 };
1651
1652 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1653 * controlled by the same config register.
1654 */
1655 if (pdevice->rad_info.has_packed_math_16bit) {
1656 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1657 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1658 } else {
1659 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1660 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1661 }
1662
1663 /* With LLVM, do not allow both preserving and flushing denorms because
1664 * different shaders in the same pipeline can have different settings and
1665 * this won't work for merged shaders. To make it work, this requires LLVM
1666 * support for changing the register. The same logic applies for the
1667 * rounding modes because they are configured with the same config
1668 * register.
1669 */
1670 p->shaderDenormFlushToZeroFloat32 = true;
1671 p->shaderDenormPreserveFloat32 = !pdevice->use_llvm;
1672 p->shaderRoundingModeRTEFloat32 = true;
1673 p->shaderRoundingModeRTZFloat32 = !pdevice->use_llvm;
1674 p->shaderSignedZeroInfNanPreserveFloat32 = true;
1675
1676 p->shaderDenormFlushToZeroFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1677 p->shaderDenormPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1678 p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.has_packed_math_16bit;
1679 p->shaderRoundingModeRTZFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1680 p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1681
1682 p->shaderDenormFlushToZeroFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1683 p->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1684 p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
1685 p->shaderRoundingModeRTZFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1686 p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1687
1688 p->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1689 p->shaderUniformBufferArrayNonUniformIndexingNative = false;
1690 p->shaderSampledImageArrayNonUniformIndexingNative = false;
1691 p->shaderStorageBufferArrayNonUniformIndexingNative = false;
1692 p->shaderStorageImageArrayNonUniformIndexingNative = false;
1693 p->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1694 p->robustBufferAccessUpdateAfterBind = false;
1695 p->quadDivergentImplicitLod = false;
1696
1697 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1698 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1699 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1700 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1701 32 /* sampler, largest when combined with image */ +
1702 64 /* sampled image */ +
1703 64 /* storage image */);
1704 p->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1705 p->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1706 p->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1707 p->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1708 p->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1709 p->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1710 p->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1711 p->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1712 p->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1713 p->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1714 p->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1715 p->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1716 p->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1717 p->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1718 p->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1719
1720 /* We support all of the depth resolve modes */
1721 p->supportedDepthResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1722 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1723 VK_RESOLVE_MODE_MIN_BIT_KHR |
1724 VK_RESOLVE_MODE_MAX_BIT_KHR;
1725
1726 /* Average doesn't make sense for stencil so we don't support that */
1727 p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1728 VK_RESOLVE_MODE_MIN_BIT_KHR |
1729 VK_RESOLVE_MODE_MAX_BIT_KHR;
1730
1731 p->independentResolveNone = true;
1732 p->independentResolve = true;
1733
1734 /* GFX6-8 only support single channel min/max filter. */
1735 p->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1736 p->filterMinmaxSingleComponentFormats = true;
1737
1738 p->maxTimelineSemaphoreValueDifference = UINT64_MAX;
1739
1740 p->framebufferIntegerColorSampleCounts = VK_SAMPLE_COUNT_1_BIT;
1741 }
1742
1743 void radv_GetPhysicalDeviceProperties2(
1744 VkPhysicalDevice physicalDevice,
1745 VkPhysicalDeviceProperties2 *pProperties)
1746 {
1747 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1748 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1749
1750 VkPhysicalDeviceVulkan11Properties core_1_1 = {
1751 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES,
1752 };
1753 radv_get_physical_device_properties_1_1(pdevice, &core_1_1);
1754
1755 VkPhysicalDeviceVulkan12Properties core_1_2 = {
1756 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES,
1757 };
1758 radv_get_physical_device_properties_1_2(pdevice, &core_1_2);
1759
1760 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1761 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1762 sizeof(core_##major##_##minor.core_property))
1763
1764 #define CORE_PROPERTY(major, minor, property) \
1765 CORE_RENAMED_PROPERTY(major, minor, property, property)
1766
1767 vk_foreach_struct(ext, pProperties->pNext) {
1768 switch (ext->sType) {
1769 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1770 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1771 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1772 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1773 break;
1774 }
1775 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1776 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1777 CORE_PROPERTY(1, 1, deviceUUID);
1778 CORE_PROPERTY(1, 1, driverUUID);
1779 CORE_PROPERTY(1, 1, deviceLUID);
1780 CORE_PROPERTY(1, 1, deviceLUIDValid);
1781 break;
1782 }
1783 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1784 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1785 CORE_PROPERTY(1, 1, maxMultiviewViewCount);
1786 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex);
1787 break;
1788 }
1789 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1790 VkPhysicalDevicePointClippingProperties *properties =
1791 (VkPhysicalDevicePointClippingProperties*)ext;
1792 CORE_PROPERTY(1, 1, pointClippingBehavior);
1793 break;
1794 }
1795 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1796 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1797 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1798 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1799 break;
1800 }
1801 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1802 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1803 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1804 properties->minImportedHostPointerAlignment = 4096;
1805 break;
1806 }
1807 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1808 VkPhysicalDeviceSubgroupProperties *properties =
1809 (VkPhysicalDeviceSubgroupProperties*)ext;
1810 CORE_PROPERTY(1, 1, subgroupSize);
1811 CORE_RENAMED_PROPERTY(1, 1, supportedStages,
1812 subgroupSupportedStages);
1813 CORE_RENAMED_PROPERTY(1, 1, supportedOperations,
1814 subgroupSupportedOperations);
1815 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages,
1816 subgroupQuadOperationsInAllStages);
1817 break;
1818 }
1819 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1820 VkPhysicalDeviceMaintenance3Properties *properties =
1821 (VkPhysicalDeviceMaintenance3Properties*)ext;
1822 CORE_PROPERTY(1, 1, maxPerSetDescriptors);
1823 CORE_PROPERTY(1, 1, maxMemoryAllocationSize);
1824 break;
1825 }
1826 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES: {
1827 VkPhysicalDeviceSamplerFilterMinmaxProperties *properties =
1828 (VkPhysicalDeviceSamplerFilterMinmaxProperties *)ext;
1829 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping);
1830 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats);
1831 break;
1832 }
1833 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1834 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1835 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1836
1837 /* Shader engines. */
1838 properties->shaderEngineCount =
1839 pdevice->rad_info.max_se;
1840 properties->shaderArraysPerEngineCount =
1841 pdevice->rad_info.max_sh_per_se;
1842 properties->computeUnitsPerShaderArray =
1843 pdevice->rad_info.min_good_cu_per_sa;
1844 properties->simdPerComputeUnit =
1845 pdevice->rad_info.num_simd_per_compute_unit;
1846 properties->wavefrontsPerSimd =
1847 pdevice->rad_info.max_wave64_per_simd;
1848 properties->wavefrontSize = 64;
1849
1850 /* SGPR. */
1851 properties->sgprsPerSimd =
1852 pdevice->rad_info.num_physical_sgprs_per_simd;
1853 properties->minSgprAllocation =
1854 pdevice->rad_info.min_sgpr_alloc;
1855 properties->maxSgprAllocation =
1856 pdevice->rad_info.max_sgpr_alloc;
1857 properties->sgprAllocationGranularity =
1858 pdevice->rad_info.sgpr_alloc_granularity;
1859
1860 /* VGPR. */
1861 properties->vgprsPerSimd =
1862 pdevice->rad_info.num_physical_wave64_vgprs_per_simd;
1863 properties->minVgprAllocation =
1864 pdevice->rad_info.min_wave64_vgpr_alloc;
1865 properties->maxVgprAllocation =
1866 pdevice->rad_info.max_vgpr_alloc;
1867 properties->vgprAllocationGranularity =
1868 pdevice->rad_info.wave64_vgpr_alloc_granularity;
1869 break;
1870 }
1871 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1872 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1873 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1874
1875 properties->shaderCoreFeatures = 0;
1876 properties->activeComputeUnitCount =
1877 pdevice->rad_info.num_good_compute_units;
1878 break;
1879 }
1880 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1881 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1882 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1883 properties->maxVertexAttribDivisor = UINT32_MAX;
1884 break;
1885 }
1886 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES: {
1887 VkPhysicalDeviceDescriptorIndexingProperties *properties =
1888 (VkPhysicalDeviceDescriptorIndexingProperties*)ext;
1889 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools);
1890 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative);
1891 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative);
1892 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative);
1893 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative);
1894 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative);
1895 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind);
1896 CORE_PROPERTY(1, 2, quadDivergentImplicitLod);
1897 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers);
1898 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers);
1899 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers);
1900 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages);
1901 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages);
1902 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments);
1903 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources);
1904 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers);
1905 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers);
1906 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic);
1907 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers);
1908 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic);
1909 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages);
1910 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages);
1911 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments);
1912 break;
1913 }
1914 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1915 VkPhysicalDeviceProtectedMemoryProperties *properties =
1916 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1917 CORE_PROPERTY(1, 1, protectedNoFault);
1918 break;
1919 }
1920 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1921 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1922 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1923 properties->primitiveOverestimationSize = 0;
1924 properties->maxExtraPrimitiveOverestimationSize = 0;
1925 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1926 properties->primitiveUnderestimation = false;
1927 properties->conservativePointAndLineRasterization = false;
1928 properties->degenerateTrianglesRasterized = false;
1929 properties->degenerateLinesRasterized = false;
1930 properties->fullyCoveredFragmentShaderInputVariable = false;
1931 properties->conservativeRasterizationPostDepthCoverage = false;
1932 break;
1933 }
1934 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1935 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1936 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1937 properties->pciDomain = pdevice->bus_info.domain;
1938 properties->pciBus = pdevice->bus_info.bus;
1939 properties->pciDevice = pdevice->bus_info.dev;
1940 properties->pciFunction = pdevice->bus_info.func;
1941 break;
1942 }
1943 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES: {
1944 VkPhysicalDeviceDriverProperties *properties =
1945 (VkPhysicalDeviceDriverProperties *) ext;
1946 CORE_PROPERTY(1, 2, driverID);
1947 CORE_PROPERTY(1, 2, driverName);
1948 CORE_PROPERTY(1, 2, driverInfo);
1949 CORE_PROPERTY(1, 2, conformanceVersion);
1950 break;
1951 }
1952 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1953 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1954 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1955 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1956 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1957 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1958 properties->maxTransformFeedbackStreamDataSize = 512;
1959 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1960 properties->maxTransformFeedbackBufferDataStride = 512;
1961 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1962 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1963 properties->transformFeedbackRasterizationStreamSelect = false;
1964 properties->transformFeedbackDraw = true;
1965 break;
1966 }
1967 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1968 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1969 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1970
1971 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1972 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1973 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1974 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1975 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1976 break;
1977 }
1978 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1979 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1980 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1981 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1982 VK_SAMPLE_COUNT_4_BIT |
1983 VK_SAMPLE_COUNT_8_BIT;
1984 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1985 properties->sampleLocationCoordinateRange[0] = 0.0f;
1986 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1987 properties->sampleLocationSubPixelBits = 4;
1988 properties->variableSampleLocations = false;
1989 break;
1990 }
1991 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES: {
1992 VkPhysicalDeviceDepthStencilResolveProperties *properties =
1993 (VkPhysicalDeviceDepthStencilResolveProperties *)ext;
1994 CORE_PROPERTY(1, 2, supportedDepthResolveModes);
1995 CORE_PROPERTY(1, 2, supportedStencilResolveModes);
1996 CORE_PROPERTY(1, 2, independentResolveNone);
1997 CORE_PROPERTY(1, 2, independentResolve);
1998 break;
1999 }
2000 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
2001 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *properties =
2002 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *)ext;
2003 properties->storageTexelBufferOffsetAlignmentBytes = 4;
2004 properties->storageTexelBufferOffsetSingleTexelAlignment = true;
2005 properties->uniformTexelBufferOffsetAlignmentBytes = 4;
2006 properties->uniformTexelBufferOffsetSingleTexelAlignment = true;
2007 break;
2008 }
2009 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES : {
2010 VkPhysicalDeviceFloatControlsProperties *properties =
2011 (VkPhysicalDeviceFloatControlsProperties *)ext;
2012 CORE_PROPERTY(1, 2, denormBehaviorIndependence);
2013 CORE_PROPERTY(1, 2, roundingModeIndependence);
2014 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16);
2015 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16);
2016 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16);
2017 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16);
2018 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16);
2019 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32);
2020 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32);
2021 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32);
2022 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32);
2023 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32);
2024 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64);
2025 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64);
2026 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64);
2027 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64);
2028 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64);
2029 break;
2030 }
2031 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES: {
2032 VkPhysicalDeviceTimelineSemaphoreProperties *properties =
2033 (VkPhysicalDeviceTimelineSemaphoreProperties *) ext;
2034 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference);
2035 break;
2036 }
2037 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT: {
2038 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *props =
2039 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *)ext;
2040 props->minSubgroupSize = 64;
2041 props->maxSubgroupSize = 64;
2042 props->maxComputeWorkgroupSubgroups = UINT32_MAX;
2043 props->requiredSubgroupSizeStages = 0;
2044
2045 if (pdevice->rad_info.chip_class >= GFX10) {
2046 /* Only GFX10+ supports wave32. */
2047 props->minSubgroupSize = 32;
2048 props->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT;
2049 }
2050 break;
2051 }
2052 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES:
2053 radv_get_physical_device_properties_1_1(pdevice, (void *)ext);
2054 break;
2055 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES:
2056 radv_get_physical_device_properties_1_2(pdevice, (void *)ext);
2057 break;
2058 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT: {
2059 VkPhysicalDeviceLineRasterizationPropertiesEXT *props =
2060 (VkPhysicalDeviceLineRasterizationPropertiesEXT *)ext;
2061 props->lineSubPixelPrecisionBits = 4;
2062 break;
2063 }
2064 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_PROPERTIES_EXT: {
2065 VkPhysicalDeviceRobustness2PropertiesEXT *properties =
2066 (VkPhysicalDeviceRobustness2PropertiesEXT *)ext;
2067 properties->robustStorageBufferAccessSizeAlignment = 4;
2068 properties->robustUniformBufferAccessSizeAlignment = 4;
2069 break;
2070 }
2071 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_PROPERTIES_EXT: {
2072 VkPhysicalDeviceCustomBorderColorPropertiesEXT *props =
2073 (VkPhysicalDeviceCustomBorderColorPropertiesEXT *)ext;
2074 props->maxCustomBorderColorSamplers = RADV_BORDER_COLOR_COUNT;
2075 break;
2076 }
2077 default:
2078 break;
2079 }
2080 }
2081 }
2082
2083 static void radv_get_physical_device_queue_family_properties(
2084 struct radv_physical_device* pdevice,
2085 uint32_t* pCount,
2086 VkQueueFamilyProperties** pQueueFamilyProperties)
2087 {
2088 int num_queue_families = 1;
2089 int idx;
2090 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2091 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
2092 num_queue_families++;
2093
2094 if (pQueueFamilyProperties == NULL) {
2095 *pCount = num_queue_families;
2096 return;
2097 }
2098
2099 if (!*pCount)
2100 return;
2101
2102 idx = 0;
2103 if (*pCount >= 1) {
2104 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2105 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
2106 VK_QUEUE_COMPUTE_BIT |
2107 VK_QUEUE_TRANSFER_BIT |
2108 VK_QUEUE_SPARSE_BINDING_BIT,
2109 .queueCount = 1,
2110 .timestampValidBits = 64,
2111 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2112 };
2113 idx++;
2114 }
2115
2116 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2117 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
2118 if (*pCount > idx) {
2119 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2120 .queueFlags = VK_QUEUE_COMPUTE_BIT |
2121 VK_QUEUE_TRANSFER_BIT |
2122 VK_QUEUE_SPARSE_BINDING_BIT,
2123 .queueCount = pdevice->rad_info.num_rings[RING_COMPUTE],
2124 .timestampValidBits = 64,
2125 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2126 };
2127 idx++;
2128 }
2129 }
2130 *pCount = idx;
2131 }
2132
2133 void radv_GetPhysicalDeviceQueueFamilyProperties(
2134 VkPhysicalDevice physicalDevice,
2135 uint32_t* pCount,
2136 VkQueueFamilyProperties* pQueueFamilyProperties)
2137 {
2138 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2139 if (!pQueueFamilyProperties) {
2140 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2141 return;
2142 }
2143 VkQueueFamilyProperties *properties[] = {
2144 pQueueFamilyProperties + 0,
2145 pQueueFamilyProperties + 1,
2146 pQueueFamilyProperties + 2,
2147 };
2148 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2149 assert(*pCount <= 3);
2150 }
2151
2152 void radv_GetPhysicalDeviceQueueFamilyProperties2(
2153 VkPhysicalDevice physicalDevice,
2154 uint32_t* pCount,
2155 VkQueueFamilyProperties2 *pQueueFamilyProperties)
2156 {
2157 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2158 if (!pQueueFamilyProperties) {
2159 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2160 return;
2161 }
2162 VkQueueFamilyProperties *properties[] = {
2163 &pQueueFamilyProperties[0].queueFamilyProperties,
2164 &pQueueFamilyProperties[1].queueFamilyProperties,
2165 &pQueueFamilyProperties[2].queueFamilyProperties,
2166 };
2167 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2168 assert(*pCount <= 3);
2169 }
2170
2171 void radv_GetPhysicalDeviceMemoryProperties(
2172 VkPhysicalDevice physicalDevice,
2173 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
2174 {
2175 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2176
2177 *pMemoryProperties = physical_device->memory_properties;
2178 }
2179
2180 static void
2181 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
2182 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
2183 {
2184 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2185 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
2186 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
2187 uint64_t vram_size = radv_get_vram_size(device);
2188 uint64_t gtt_size = device->rad_info.gart_size;
2189 uint64_t heap_budget, heap_usage;
2190
2191 /* For all memory heaps, the computation of budget is as follow:
2192 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2193 *
2194 * The Vulkan spec 1.1.97 says that the budget should include any
2195 * currently allocated device memory.
2196 *
2197 * Note that the application heap usages are not really accurate (eg.
2198 * in presence of shared buffers).
2199 */
2200 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
2201 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
2202
2203 if ((device->memory_domains[i] & RADEON_DOMAIN_VRAM) && (device->memory_flags[i] & RADEON_FLAG_NO_CPU_ACCESS)) {
2204 heap_usage = device->ws->query_value(device->ws,
2205 RADEON_ALLOCATED_VRAM);
2206
2207 heap_budget = vram_size -
2208 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
2209 heap_usage;
2210
2211 memoryBudget->heapBudget[heap_index] = heap_budget;
2212 memoryBudget->heapUsage[heap_index] = heap_usage;
2213 } else if (device->memory_domains[i] & RADEON_DOMAIN_VRAM) {
2214 heap_usage = device->ws->query_value(device->ws,
2215 RADEON_ALLOCATED_VRAM_VIS);
2216
2217 heap_budget = visible_vram_size -
2218 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
2219 heap_usage;
2220
2221 memoryBudget->heapBudget[heap_index] = heap_budget;
2222 memoryBudget->heapUsage[heap_index] = heap_usage;
2223 } else {
2224 assert(device->memory_domains[i] & RADEON_DOMAIN_GTT);
2225
2226 heap_usage = device->ws->query_value(device->ws,
2227 RADEON_ALLOCATED_GTT);
2228
2229 heap_budget = gtt_size -
2230 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
2231 heap_usage;
2232
2233 memoryBudget->heapBudget[heap_index] = heap_budget;
2234 memoryBudget->heapUsage[heap_index] = heap_usage;
2235 }
2236 }
2237
2238 /* The heapBudget and heapUsage values must be zero for array elements
2239 * greater than or equal to
2240 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2241 */
2242 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
2243 memoryBudget->heapBudget[i] = 0;
2244 memoryBudget->heapUsage[i] = 0;
2245 }
2246 }
2247
2248 void radv_GetPhysicalDeviceMemoryProperties2(
2249 VkPhysicalDevice physicalDevice,
2250 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
2251 {
2252 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
2253 &pMemoryProperties->memoryProperties);
2254
2255 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
2256 vk_find_struct(pMemoryProperties->pNext,
2257 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
2258 if (memory_budget)
2259 radv_get_memory_budget_properties(physicalDevice, memory_budget);
2260 }
2261
2262 VkResult radv_GetMemoryHostPointerPropertiesEXT(
2263 VkDevice _device,
2264 VkExternalMemoryHandleTypeFlagBits handleType,
2265 const void *pHostPointer,
2266 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
2267 {
2268 RADV_FROM_HANDLE(radv_device, device, _device);
2269
2270 switch (handleType)
2271 {
2272 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
2273 const struct radv_physical_device *physical_device = device->physical_device;
2274 uint32_t memoryTypeBits = 0;
2275 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
2276 if (physical_device->memory_domains[i] == RADEON_DOMAIN_GTT &&
2277 !(physical_device->memory_flags[i] & RADEON_FLAG_GTT_WC)) {
2278 memoryTypeBits = (1 << i);
2279 break;
2280 }
2281 }
2282 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
2283 return VK_SUCCESS;
2284 }
2285 default:
2286 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
2287 }
2288 }
2289
2290 static enum radeon_ctx_priority
2291 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
2292 {
2293 /* Default to MEDIUM when a specific global priority isn't requested */
2294 if (!pObj)
2295 return RADEON_CTX_PRIORITY_MEDIUM;
2296
2297 switch(pObj->globalPriority) {
2298 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
2299 return RADEON_CTX_PRIORITY_REALTIME;
2300 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
2301 return RADEON_CTX_PRIORITY_HIGH;
2302 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
2303 return RADEON_CTX_PRIORITY_MEDIUM;
2304 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
2305 return RADEON_CTX_PRIORITY_LOW;
2306 default:
2307 unreachable("Illegal global priority value");
2308 return RADEON_CTX_PRIORITY_INVALID;
2309 }
2310 }
2311
2312 static int
2313 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
2314 uint32_t queue_family_index, int idx,
2315 VkDeviceQueueCreateFlags flags,
2316 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
2317 {
2318 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2319 queue->device = device;
2320 queue->queue_family_index = queue_family_index;
2321 queue->queue_idx = idx;
2322 queue->priority = radv_get_queue_global_priority(global_priority);
2323 queue->flags = flags;
2324 queue->hw_ctx = NULL;
2325
2326 VkResult result = device->ws->ctx_create(device->ws, queue->priority, &queue->hw_ctx);
2327 if (result != VK_SUCCESS)
2328 return vk_error(device->instance, result);
2329
2330 list_inithead(&queue->pending_submissions);
2331 pthread_mutex_init(&queue->pending_mutex, NULL);
2332
2333 pthread_mutex_init(&queue->thread_mutex, NULL);
2334 queue->thread_submission = NULL;
2335 queue->thread_running = queue->thread_exit = false;
2336 result = radv_create_pthread_cond(&queue->thread_cond);
2337 if (result != VK_SUCCESS)
2338 return vk_error(device->instance, result);
2339
2340 return VK_SUCCESS;
2341 }
2342
2343 static void
2344 radv_queue_finish(struct radv_queue *queue)
2345 {
2346 if (queue->thread_running) {
2347 p_atomic_set(&queue->thread_exit, true);
2348 pthread_cond_broadcast(&queue->thread_cond);
2349 pthread_join(queue->submission_thread, NULL);
2350 }
2351 pthread_cond_destroy(&queue->thread_cond);
2352 pthread_mutex_destroy(&queue->pending_mutex);
2353 pthread_mutex_destroy(&queue->thread_mutex);
2354
2355 if (queue->hw_ctx)
2356 queue->device->ws->ctx_destroy(queue->hw_ctx);
2357
2358 if (queue->initial_full_flush_preamble_cs)
2359 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2360 if (queue->initial_preamble_cs)
2361 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2362 if (queue->continue_preamble_cs)
2363 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2364 if (queue->descriptor_bo)
2365 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2366 if (queue->scratch_bo)
2367 queue->device->ws->buffer_destroy(queue->scratch_bo);
2368 if (queue->esgs_ring_bo)
2369 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2370 if (queue->gsvs_ring_bo)
2371 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2372 if (queue->tess_rings_bo)
2373 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
2374 if (queue->gds_bo)
2375 queue->device->ws->buffer_destroy(queue->gds_bo);
2376 if (queue->gds_oa_bo)
2377 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
2378 if (queue->compute_scratch_bo)
2379 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2380 }
2381
2382 static void
2383 radv_bo_list_init(struct radv_bo_list *bo_list)
2384 {
2385 pthread_mutex_init(&bo_list->mutex, NULL);
2386 bo_list->list.count = bo_list->capacity = 0;
2387 bo_list->list.bos = NULL;
2388 }
2389
2390 static void
2391 radv_bo_list_finish(struct radv_bo_list *bo_list)
2392 {
2393 free(bo_list->list.bos);
2394 pthread_mutex_destroy(&bo_list->mutex);
2395 }
2396
2397 VkResult radv_bo_list_add(struct radv_device *device,
2398 struct radeon_winsys_bo *bo)
2399 {
2400 struct radv_bo_list *bo_list = &device->bo_list;
2401
2402 if (bo->is_local)
2403 return VK_SUCCESS;
2404
2405 if (unlikely(!device->use_global_bo_list))
2406 return VK_SUCCESS;
2407
2408 pthread_mutex_lock(&bo_list->mutex);
2409 if (bo_list->list.count == bo_list->capacity) {
2410 unsigned capacity = MAX2(4, bo_list->capacity * 2);
2411 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
2412
2413 if (!data) {
2414 pthread_mutex_unlock(&bo_list->mutex);
2415 return VK_ERROR_OUT_OF_HOST_MEMORY;
2416 }
2417
2418 bo_list->list.bos = (struct radeon_winsys_bo**)data;
2419 bo_list->capacity = capacity;
2420 }
2421
2422 bo_list->list.bos[bo_list->list.count++] = bo;
2423 pthread_mutex_unlock(&bo_list->mutex);
2424 return VK_SUCCESS;
2425 }
2426
2427 void radv_bo_list_remove(struct radv_device *device,
2428 struct radeon_winsys_bo *bo)
2429 {
2430 struct radv_bo_list *bo_list = &device->bo_list;
2431
2432 if (bo->is_local)
2433 return;
2434
2435 if (unlikely(!device->use_global_bo_list))
2436 return;
2437
2438 pthread_mutex_lock(&bo_list->mutex);
2439 /* Loop the list backwards so we find the most recently added
2440 * memory first. */
2441 for(unsigned i = bo_list->list.count; i-- > 0;) {
2442 if (bo_list->list.bos[i] == bo) {
2443 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
2444 --bo_list->list.count;
2445 break;
2446 }
2447 }
2448 pthread_mutex_unlock(&bo_list->mutex);
2449 }
2450
2451 static void
2452 radv_device_init_gs_info(struct radv_device *device)
2453 {
2454 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
2455 device->physical_device->rad_info.family);
2456 }
2457
2458 static int radv_get_device_extension_index(const char *name)
2459 {
2460 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
2461 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
2462 return i;
2463 }
2464 return -1;
2465 }
2466
2467 static int
2468 radv_get_int_debug_option(const char *name, int default_value)
2469 {
2470 const char *str;
2471 int result;
2472
2473 str = getenv(name);
2474 if (!str) {
2475 result = default_value;
2476 } else {
2477 char *endptr;
2478
2479 result = strtol(str, &endptr, 0);
2480 if (str == endptr) {
2481 /* No digits founs. */
2482 result = default_value;
2483 }
2484 }
2485
2486 return result;
2487 }
2488
2489 static void
2490 radv_device_init_dispatch(struct radv_device *device)
2491 {
2492 const struct radv_instance *instance = device->physical_device->instance;
2493 const struct radv_device_dispatch_table *dispatch_table_layer = NULL;
2494 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
2495 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2496
2497 if (radv_thread_trace >= 0) {
2498 /* Use device entrypoints from the SQTT layer if enabled. */
2499 dispatch_table_layer = &sqtt_device_dispatch_table;
2500 }
2501
2502 for (unsigned i = 0; i < ARRAY_SIZE(device->dispatch.entrypoints); i++) {
2503 /* Vulkan requires that entrypoints for extensions which have not been
2504 * enabled must not be advertised.
2505 */
2506 if (!unchecked &&
2507 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
2508 &instance->enabled_extensions,
2509 &device->enabled_extensions)) {
2510 device->dispatch.entrypoints[i] = NULL;
2511 } else if (dispatch_table_layer &&
2512 dispatch_table_layer->entrypoints[i]) {
2513 device->dispatch.entrypoints[i] =
2514 dispatch_table_layer->entrypoints[i];
2515 } else {
2516 device->dispatch.entrypoints[i] =
2517 radv_device_dispatch_table.entrypoints[i];
2518 }
2519 }
2520 }
2521
2522 static VkResult
2523 radv_create_pthread_cond(pthread_cond_t *cond)
2524 {
2525 pthread_condattr_t condattr;
2526 if (pthread_condattr_init(&condattr)) {
2527 return VK_ERROR_INITIALIZATION_FAILED;
2528 }
2529
2530 if (pthread_condattr_setclock(&condattr, CLOCK_MONOTONIC)) {
2531 pthread_condattr_destroy(&condattr);
2532 return VK_ERROR_INITIALIZATION_FAILED;
2533 }
2534 if (pthread_cond_init(cond, &condattr)) {
2535 pthread_condattr_destroy(&condattr);
2536 return VK_ERROR_INITIALIZATION_FAILED;
2537 }
2538 pthread_condattr_destroy(&condattr);
2539 return VK_SUCCESS;
2540 }
2541
2542 static VkResult
2543 check_physical_device_features(VkPhysicalDevice physicalDevice,
2544 const VkPhysicalDeviceFeatures *features)
2545 {
2546 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2547 VkPhysicalDeviceFeatures supported_features;
2548 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
2549 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
2550 VkBool32 *enabled_feature = (VkBool32 *)features;
2551 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
2552 for (uint32_t i = 0; i < num_features; i++) {
2553 if (enabled_feature[i] && !supported_feature[i])
2554 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
2555 }
2556
2557 return VK_SUCCESS;
2558 }
2559
2560 static VkResult radv_device_init_border_color(struct radv_device *device)
2561 {
2562 device->border_color_data.bo =
2563 device->ws->buffer_create(device->ws,
2564 RADV_BORDER_COLOR_BUFFER_SIZE,
2565 4096,
2566 RADEON_DOMAIN_VRAM,
2567 RADEON_FLAG_CPU_ACCESS |
2568 RADEON_FLAG_READ_ONLY |
2569 RADEON_FLAG_NO_INTERPROCESS_SHARING,
2570 RADV_BO_PRIORITY_SHADER);
2571
2572 if (device->border_color_data.bo == NULL)
2573 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2574
2575 device->border_color_data.colors_gpu_ptr =
2576 device->ws->buffer_map(device->border_color_data.bo);
2577 if (!device->border_color_data.colors_gpu_ptr)
2578 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2579 pthread_mutex_init(&device->border_color_data.mutex, NULL);
2580
2581 return VK_SUCCESS;
2582 }
2583
2584 static void radv_device_finish_border_color(struct radv_device *device)
2585 {
2586 if (device->border_color_data.bo) {
2587 device->ws->buffer_destroy(device->border_color_data.bo);
2588
2589 pthread_mutex_destroy(&device->border_color_data.mutex);
2590 }
2591 }
2592
2593 VkResult radv_CreateDevice(
2594 VkPhysicalDevice physicalDevice,
2595 const VkDeviceCreateInfo* pCreateInfo,
2596 const VkAllocationCallbacks* pAllocator,
2597 VkDevice* pDevice)
2598 {
2599 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2600 VkResult result;
2601 struct radv_device *device;
2602
2603 bool keep_shader_info = false;
2604 bool robust_buffer_access = false;
2605 bool overallocation_disallowed = false;
2606 bool custom_border_colors = false;
2607
2608 /* Check enabled features */
2609 if (pCreateInfo->pEnabledFeatures) {
2610 result = check_physical_device_features(physicalDevice,
2611 pCreateInfo->pEnabledFeatures);
2612 if (result != VK_SUCCESS)
2613 return result;
2614
2615 if (pCreateInfo->pEnabledFeatures->robustBufferAccess)
2616 robust_buffer_access = true;
2617 }
2618
2619 vk_foreach_struct_const(ext, pCreateInfo->pNext) {
2620 switch (ext->sType) {
2621 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2: {
2622 const VkPhysicalDeviceFeatures2 *features = (const void *)ext;
2623 result = check_physical_device_features(physicalDevice,
2624 &features->features);
2625 if (result != VK_SUCCESS)
2626 return result;
2627
2628 if (features->features.robustBufferAccess)
2629 robust_buffer_access = true;
2630 break;
2631 }
2632 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
2633 const VkDeviceMemoryOverallocationCreateInfoAMD *overallocation = (const void *)ext;
2634 if (overallocation->overallocationBehavior == VK_MEMORY_OVERALLOCATION_BEHAVIOR_DISALLOWED_AMD)
2635 overallocation_disallowed = true;
2636 break;
2637 }
2638 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
2639 const VkPhysicalDeviceCustomBorderColorFeaturesEXT *border_color_features = (const void *)ext;
2640 custom_border_colors = border_color_features->customBorderColors;
2641 break;
2642 }
2643 default:
2644 break;
2645 }
2646 }
2647
2648 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
2649 sizeof(*device), 8,
2650 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2651 if (!device)
2652 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2653
2654 vk_device_init(&device->vk, pCreateInfo,
2655 &physical_device->instance->alloc, pAllocator);
2656
2657 device->instance = physical_device->instance;
2658 device->physical_device = physical_device;
2659
2660 device->ws = physical_device->ws;
2661
2662 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
2663 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
2664 int index = radv_get_device_extension_index(ext_name);
2665 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
2666 vk_free(&device->vk.alloc, device);
2667 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
2668 }
2669
2670 device->enabled_extensions.extensions[index] = true;
2671 }
2672
2673 radv_device_init_dispatch(device);
2674
2675 keep_shader_info = device->enabled_extensions.AMD_shader_info;
2676
2677 /* With update after bind we can't attach bo's to the command buffer
2678 * from the descriptor set anymore, so we have to use a global BO list.
2679 */
2680 device->use_global_bo_list =
2681 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
2682 device->enabled_extensions.EXT_descriptor_indexing ||
2683 device->enabled_extensions.EXT_buffer_device_address ||
2684 device->enabled_extensions.KHR_buffer_device_address;
2685
2686 device->robust_buffer_access = robust_buffer_access;
2687
2688 mtx_init(&device->shader_slab_mutex, mtx_plain);
2689 list_inithead(&device->shader_slabs);
2690
2691 device->overallocation_disallowed = overallocation_disallowed;
2692 mtx_init(&device->overallocation_mutex, mtx_plain);
2693
2694 radv_bo_list_init(&device->bo_list);
2695
2696 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
2697 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
2698 uint32_t qfi = queue_create->queueFamilyIndex;
2699 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
2700 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
2701
2702 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
2703
2704 device->queues[qfi] = vk_alloc(&device->vk.alloc,
2705 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2706 if (!device->queues[qfi]) {
2707 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2708 goto fail;
2709 }
2710
2711 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
2712
2713 device->queue_count[qfi] = queue_create->queueCount;
2714
2715 for (unsigned q = 0; q < queue_create->queueCount; q++) {
2716 result = radv_queue_init(device, &device->queues[qfi][q],
2717 qfi, q, queue_create->flags,
2718 global_priority);
2719 if (result != VK_SUCCESS)
2720 goto fail;
2721 }
2722 }
2723
2724 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
2725 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
2726
2727 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2728 device->dfsm_allowed = device->pbb_allowed &&
2729 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
2730
2731 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
2732
2733 /* The maximum number of scratch waves. Scratch space isn't divided
2734 * evenly between CUs. The number is only a function of the number of CUs.
2735 * We can decrease the constant to decrease the scratch buffer size.
2736 *
2737 * sctx->scratch_waves must be >= the maximum possible size of
2738 * 1 threadgroup, so that the hw doesn't hang from being unable
2739 * to start any.
2740 *
2741 * The recommended value is 4 per CU at most. Higher numbers don't
2742 * bring much benefit, but they still occupy chip resources (think
2743 * async compute). I've seen ~2% performance difference between 4 and 32.
2744 */
2745 uint32_t max_threads_per_block = 2048;
2746 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
2747 max_threads_per_block / 64);
2748
2749 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
2750
2751 if (device->physical_device->rad_info.chip_class >= GFX7) {
2752 /* If the KMD allows it (there is a KMD hw register for it),
2753 * allow launching waves out-of-order.
2754 */
2755 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
2756 }
2757
2758 radv_device_init_gs_info(device);
2759
2760 device->tess_offchip_block_dw_size =
2761 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2762
2763 if (getenv("RADV_TRACE_FILE")) {
2764 const char *filename = getenv("RADV_TRACE_FILE");
2765
2766 keep_shader_info = true;
2767
2768 if (!radv_init_trace(device))
2769 goto fail;
2770
2771 fprintf(stderr, "*****************************************************************************\n");
2772 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2773 fprintf(stderr, "*****************************************************************************\n");
2774
2775 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2776 radv_dump_enabled_options(device, stderr);
2777 }
2778
2779 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2780 if (radv_thread_trace >= 0) {
2781 fprintf(stderr, "*************************************************\n");
2782 fprintf(stderr, "* WARNING: Thread trace support is experimental *\n");
2783 fprintf(stderr, "*************************************************\n");
2784
2785 if (device->physical_device->rad_info.chip_class < GFX8) {
2786 fprintf(stderr, "GPU hardware not supported: refer to "
2787 "the RGP documentation for the list of "
2788 "supported GPUs!\n");
2789 abort();
2790 }
2791
2792 /* Default buffer size set to 1MB per SE. */
2793 device->thread_trace_buffer_size =
2794 radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024);
2795 device->thread_trace_start_frame = radv_thread_trace;
2796
2797 if (!radv_thread_trace_init(device))
2798 goto fail;
2799 }
2800
2801 device->keep_shader_info = keep_shader_info;
2802 result = radv_device_init_meta(device);
2803 if (result != VK_SUCCESS)
2804 goto fail;
2805
2806 radv_device_init_msaa(device);
2807
2808 /* If the border color extension is enabled, let's create the buffer we need. */
2809 if (custom_border_colors) {
2810 result = radv_device_init_border_color(device);
2811 if (result != VK_SUCCESS)
2812 goto fail;
2813 }
2814
2815 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2816 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2817 if (!device->empty_cs[family])
2818 goto fail;
2819
2820 switch (family) {
2821 case RADV_QUEUE_GENERAL:
2822 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2823 radeon_emit(device->empty_cs[family], CC0_UPDATE_LOAD_ENABLES(1));
2824 radeon_emit(device->empty_cs[family], CC1_UPDATE_SHADOW_ENABLES(1));
2825 break;
2826 case RADV_QUEUE_COMPUTE:
2827 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2828 radeon_emit(device->empty_cs[family], 0);
2829 break;
2830 }
2831
2832 result = device->ws->cs_finalize(device->empty_cs[family]);
2833 if (result != VK_SUCCESS)
2834 goto fail;
2835 }
2836
2837 if (device->physical_device->rad_info.chip_class >= GFX7)
2838 cik_create_gfx_config(device);
2839
2840 VkPipelineCacheCreateInfo ci;
2841 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2842 ci.pNext = NULL;
2843 ci.flags = 0;
2844 ci.pInitialData = NULL;
2845 ci.initialDataSize = 0;
2846 VkPipelineCache pc;
2847 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2848 &ci, NULL, &pc);
2849 if (result != VK_SUCCESS)
2850 goto fail_meta;
2851
2852 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2853
2854 result = radv_create_pthread_cond(&device->timeline_cond);
2855 if (result != VK_SUCCESS)
2856 goto fail_mem_cache;
2857
2858 device->force_aniso =
2859 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2860 if (device->force_aniso >= 0) {
2861 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2862 1 << util_logbase2(device->force_aniso));
2863 }
2864
2865 *pDevice = radv_device_to_handle(device);
2866 return VK_SUCCESS;
2867
2868 fail_mem_cache:
2869 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2870 fail_meta:
2871 radv_device_finish_meta(device);
2872 fail:
2873 radv_bo_list_finish(&device->bo_list);
2874
2875 radv_thread_trace_finish(device);
2876
2877 if (device->trace_bo)
2878 device->ws->buffer_destroy(device->trace_bo);
2879
2880 if (device->gfx_init)
2881 device->ws->buffer_destroy(device->gfx_init);
2882
2883 radv_device_finish_border_color(device);
2884
2885 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2886 for (unsigned q = 0; q < device->queue_count[i]; q++)
2887 radv_queue_finish(&device->queues[i][q]);
2888 if (device->queue_count[i])
2889 vk_free(&device->vk.alloc, device->queues[i]);
2890 }
2891
2892 vk_free(&device->vk.alloc, device);
2893 return result;
2894 }
2895
2896 void radv_DestroyDevice(
2897 VkDevice _device,
2898 const VkAllocationCallbacks* pAllocator)
2899 {
2900 RADV_FROM_HANDLE(radv_device, device, _device);
2901
2902 if (!device)
2903 return;
2904
2905 if (device->trace_bo)
2906 device->ws->buffer_destroy(device->trace_bo);
2907
2908 if (device->gfx_init)
2909 device->ws->buffer_destroy(device->gfx_init);
2910
2911 radv_device_finish_border_color(device);
2912
2913 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2914 for (unsigned q = 0; q < device->queue_count[i]; q++)
2915 radv_queue_finish(&device->queues[i][q]);
2916 if (device->queue_count[i])
2917 vk_free(&device->vk.alloc, device->queues[i]);
2918 if (device->empty_cs[i])
2919 device->ws->cs_destroy(device->empty_cs[i]);
2920 }
2921 radv_device_finish_meta(device);
2922
2923 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2924 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2925
2926 radv_destroy_shader_slabs(device);
2927
2928 pthread_cond_destroy(&device->timeline_cond);
2929 radv_bo_list_finish(&device->bo_list);
2930
2931 radv_thread_trace_finish(device);
2932
2933 vk_free(&device->vk.alloc, device);
2934 }
2935
2936 VkResult radv_EnumerateInstanceLayerProperties(
2937 uint32_t* pPropertyCount,
2938 VkLayerProperties* pProperties)
2939 {
2940 if (pProperties == NULL) {
2941 *pPropertyCount = 0;
2942 return VK_SUCCESS;
2943 }
2944
2945 /* None supported at this time */
2946 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2947 }
2948
2949 VkResult radv_EnumerateDeviceLayerProperties(
2950 VkPhysicalDevice physicalDevice,
2951 uint32_t* pPropertyCount,
2952 VkLayerProperties* pProperties)
2953 {
2954 if (pProperties == NULL) {
2955 *pPropertyCount = 0;
2956 return VK_SUCCESS;
2957 }
2958
2959 /* None supported at this time */
2960 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2961 }
2962
2963 void radv_GetDeviceQueue2(
2964 VkDevice _device,
2965 const VkDeviceQueueInfo2* pQueueInfo,
2966 VkQueue* pQueue)
2967 {
2968 RADV_FROM_HANDLE(radv_device, device, _device);
2969 struct radv_queue *queue;
2970
2971 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2972 if (pQueueInfo->flags != queue->flags) {
2973 /* From the Vulkan 1.1.70 spec:
2974 *
2975 * "The queue returned by vkGetDeviceQueue2 must have the same
2976 * flags value from this structure as that used at device
2977 * creation time in a VkDeviceQueueCreateInfo instance. If no
2978 * matching flags were specified at device creation time then
2979 * pQueue will return VK_NULL_HANDLE."
2980 */
2981 *pQueue = VK_NULL_HANDLE;
2982 return;
2983 }
2984
2985 *pQueue = radv_queue_to_handle(queue);
2986 }
2987
2988 void radv_GetDeviceQueue(
2989 VkDevice _device,
2990 uint32_t queueFamilyIndex,
2991 uint32_t queueIndex,
2992 VkQueue* pQueue)
2993 {
2994 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2995 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2996 .queueFamilyIndex = queueFamilyIndex,
2997 .queueIndex = queueIndex
2998 };
2999
3000 radv_GetDeviceQueue2(_device, &info, pQueue);
3001 }
3002
3003 static void
3004 fill_geom_tess_rings(struct radv_queue *queue,
3005 uint32_t *map,
3006 bool add_sample_positions,
3007 uint32_t esgs_ring_size,
3008 struct radeon_winsys_bo *esgs_ring_bo,
3009 uint32_t gsvs_ring_size,
3010 struct radeon_winsys_bo *gsvs_ring_bo,
3011 uint32_t tess_factor_ring_size,
3012 uint32_t tess_offchip_ring_offset,
3013 uint32_t tess_offchip_ring_size,
3014 struct radeon_winsys_bo *tess_rings_bo)
3015 {
3016 uint32_t *desc = &map[4];
3017
3018 if (esgs_ring_bo) {
3019 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
3020
3021 /* stride 0, num records - size, add tid, swizzle, elsize4,
3022 index stride 64 */
3023 desc[0] = esgs_va;
3024 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
3025 S_008F04_SWIZZLE_ENABLE(true);
3026 desc[2] = esgs_ring_size;
3027 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3028 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3029 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3030 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3031 S_008F0C_INDEX_STRIDE(3) |
3032 S_008F0C_ADD_TID_ENABLE(1);
3033
3034 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3035 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3036 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3037 S_008F0C_RESOURCE_LEVEL(1);
3038 } else {
3039 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3040 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3041 S_008F0C_ELEMENT_SIZE(1);
3042 }
3043
3044 /* GS entry for ES->GS ring */
3045 /* stride 0, num records - size, elsize0,
3046 index stride 0 */
3047 desc[4] = esgs_va;
3048 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
3049 desc[6] = esgs_ring_size;
3050 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3051 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3052 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3053 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3054
3055 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3056 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3057 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3058 S_008F0C_RESOURCE_LEVEL(1);
3059 } else {
3060 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3061 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3062 }
3063 }
3064
3065 desc += 8;
3066
3067 if (gsvs_ring_bo) {
3068 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
3069
3070 /* VS entry for GS->VS ring */
3071 /* stride 0, num records - size, elsize0,
3072 index stride 0 */
3073 desc[0] = gsvs_va;
3074 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
3075 desc[2] = gsvs_ring_size;
3076 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3077 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3078 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3079 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3080
3081 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3082 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3083 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3084 S_008F0C_RESOURCE_LEVEL(1);
3085 } else {
3086 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3087 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3088 }
3089
3090 /* stride gsvs_itemsize, num records 64
3091 elsize 4, index stride 16 */
3092 /* shader will patch stride and desc[2] */
3093 desc[4] = gsvs_va;
3094 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
3095 S_008F04_SWIZZLE_ENABLE(1);
3096 desc[6] = 0;
3097 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3098 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3099 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3100 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3101 S_008F0C_INDEX_STRIDE(1) |
3102 S_008F0C_ADD_TID_ENABLE(true);
3103
3104 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3105 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3106 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3107 S_008F0C_RESOURCE_LEVEL(1);
3108 } else {
3109 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3110 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3111 S_008F0C_ELEMENT_SIZE(1);
3112 }
3113
3114 }
3115
3116 desc += 8;
3117
3118 if (tess_rings_bo) {
3119 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
3120 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
3121
3122 desc[0] = tess_va;
3123 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
3124 desc[2] = tess_factor_ring_size;
3125 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3126 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3127 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3128 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3129
3130 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3131 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3132 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3133 S_008F0C_RESOURCE_LEVEL(1);
3134 } else {
3135 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3136 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3137 }
3138
3139 desc[4] = tess_offchip_va;
3140 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
3141 desc[6] = tess_offchip_ring_size;
3142 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3143 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3144 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3145 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3146
3147 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3148 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3149 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3150 S_008F0C_RESOURCE_LEVEL(1);
3151 } else {
3152 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3153 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3154 }
3155 }
3156
3157 desc += 8;
3158
3159 if (add_sample_positions) {
3160 /* add sample positions after all rings */
3161 memcpy(desc, queue->device->sample_locations_1x, 8);
3162 desc += 2;
3163 memcpy(desc, queue->device->sample_locations_2x, 16);
3164 desc += 4;
3165 memcpy(desc, queue->device->sample_locations_4x, 32);
3166 desc += 8;
3167 memcpy(desc, queue->device->sample_locations_8x, 64);
3168 }
3169 }
3170
3171 static unsigned
3172 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
3173 {
3174 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
3175 device->physical_device->rad_info.family != CHIP_CARRIZO &&
3176 device->physical_device->rad_info.family != CHIP_STONEY;
3177 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
3178 unsigned max_offchip_buffers;
3179 unsigned offchip_granularity;
3180 unsigned hs_offchip_param;
3181
3182 /*
3183 * Per RadeonSI:
3184 * This must be one less than the maximum number due to a hw limitation.
3185 * Various hardware bugs need thGFX7
3186 *
3187 * Per AMDVLK:
3188 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3189 * Gfx7 should limit max_offchip_buffers to 508
3190 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3191 *
3192 * Follow AMDVLK here.
3193 */
3194 if (device->physical_device->rad_info.chip_class >= GFX10) {
3195 max_offchip_buffers_per_se = 256;
3196 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
3197 device->physical_device->rad_info.chip_class == GFX7 ||
3198 device->physical_device->rad_info.chip_class == GFX6)
3199 --max_offchip_buffers_per_se;
3200
3201 max_offchip_buffers = max_offchip_buffers_per_se *
3202 device->physical_device->rad_info.max_se;
3203
3204 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3205 * around by setting 4K granularity.
3206 */
3207 if (device->tess_offchip_block_dw_size == 4096) {
3208 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
3209 offchip_granularity = V_03093C_X_4K_DWORDS;
3210 } else {
3211 assert(device->tess_offchip_block_dw_size == 8192);
3212 offchip_granularity = V_03093C_X_8K_DWORDS;
3213 }
3214
3215 switch (device->physical_device->rad_info.chip_class) {
3216 case GFX6:
3217 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
3218 break;
3219 case GFX7:
3220 case GFX8:
3221 case GFX9:
3222 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
3223 break;
3224 case GFX10:
3225 break;
3226 default:
3227 break;
3228 }
3229
3230 *max_offchip_buffers_p = max_offchip_buffers;
3231 if (device->physical_device->rad_info.chip_class >= GFX10_3) {
3232 hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers - 1) |
3233 S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity);
3234 } else if (device->physical_device->rad_info.chip_class >= GFX7) {
3235 if (device->physical_device->rad_info.chip_class >= GFX8)
3236 --max_offchip_buffers;
3237 hs_offchip_param =
3238 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
3239 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
3240 } else {
3241 hs_offchip_param =
3242 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
3243 }
3244 return hs_offchip_param;
3245 }
3246
3247 static void
3248 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3249 struct radeon_winsys_bo *esgs_ring_bo,
3250 uint32_t esgs_ring_size,
3251 struct radeon_winsys_bo *gsvs_ring_bo,
3252 uint32_t gsvs_ring_size)
3253 {
3254 if (!esgs_ring_bo && !gsvs_ring_bo)
3255 return;
3256
3257 if (esgs_ring_bo)
3258 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
3259
3260 if (gsvs_ring_bo)
3261 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
3262
3263 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3264 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
3265 radeon_emit(cs, esgs_ring_size >> 8);
3266 radeon_emit(cs, gsvs_ring_size >> 8);
3267 } else {
3268 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
3269 radeon_emit(cs, esgs_ring_size >> 8);
3270 radeon_emit(cs, gsvs_ring_size >> 8);
3271 }
3272 }
3273
3274 static void
3275 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3276 unsigned hs_offchip_param, unsigned tf_ring_size,
3277 struct radeon_winsys_bo *tess_rings_bo)
3278 {
3279 uint64_t tf_va;
3280
3281 if (!tess_rings_bo)
3282 return;
3283
3284 tf_va = radv_buffer_get_va(tess_rings_bo);
3285
3286 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
3287
3288 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3289 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
3290 S_030938_SIZE(tf_ring_size / 4));
3291 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
3292 tf_va >> 8);
3293
3294 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3295 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3296 S_030984_BASE_HI(tf_va >> 40));
3297 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3298 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
3299 S_030944_BASE_HI(tf_va >> 40));
3300 }
3301 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
3302 hs_offchip_param);
3303 } else {
3304 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
3305 S_008988_SIZE(tf_ring_size / 4));
3306 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
3307 tf_va >> 8);
3308 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3309 hs_offchip_param);
3310 }
3311 }
3312
3313 static void
3314 radv_emit_graphics_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3315 uint32_t size_per_wave, uint32_t waves,
3316 struct radeon_winsys_bo *scratch_bo)
3317 {
3318 if (queue->queue_family_index != RADV_QUEUE_GENERAL)
3319 return;
3320
3321 if (!scratch_bo)
3322 return;
3323
3324 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3325
3326 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3327 S_0286E8_WAVES(waves) |
3328 S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3329 }
3330
3331 static void
3332 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3333 uint32_t size_per_wave, uint32_t waves,
3334 struct radeon_winsys_bo *compute_scratch_bo)
3335 {
3336 uint64_t scratch_va;
3337
3338 if (!compute_scratch_bo)
3339 return;
3340
3341 scratch_va = radv_buffer_get_va(compute_scratch_bo);
3342
3343 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
3344
3345 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
3346 radeon_emit(cs, scratch_va);
3347 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3348 S_008F04_SWIZZLE_ENABLE(1));
3349
3350 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
3351 S_00B860_WAVES(waves) |
3352 S_00B860_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3353 }
3354
3355 static void
3356 radv_emit_global_shader_pointers(struct radv_queue *queue,
3357 struct radeon_cmdbuf *cs,
3358 struct radeon_winsys_bo *descriptor_bo)
3359 {
3360 uint64_t va;
3361
3362 if (!descriptor_bo)
3363 return;
3364
3365 va = radv_buffer_get_va(descriptor_bo);
3366
3367 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
3368
3369 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3370 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3371 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3372 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3373 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3374
3375 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3376 radv_emit_shader_pointer(queue->device, cs, regs[i],
3377 va, true);
3378 }
3379 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3380 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3381 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3382 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3383 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3384
3385 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3386 radv_emit_shader_pointer(queue->device, cs, regs[i],
3387 va, true);
3388 }
3389 } else {
3390 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3391 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3392 R_00B230_SPI_SHADER_USER_DATA_GS_0,
3393 R_00B330_SPI_SHADER_USER_DATA_ES_0,
3394 R_00B430_SPI_SHADER_USER_DATA_HS_0,
3395 R_00B530_SPI_SHADER_USER_DATA_LS_0};
3396
3397 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3398 radv_emit_shader_pointer(queue->device, cs, regs[i],
3399 va, true);
3400 }
3401 }
3402 }
3403
3404 static void
3405 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3406 {
3407 struct radv_device *device = queue->device;
3408
3409 if (device->gfx_init) {
3410 uint64_t va = radv_buffer_get_va(device->gfx_init);
3411
3412 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
3413 radeon_emit(cs, va);
3414 radeon_emit(cs, va >> 32);
3415 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
3416
3417 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
3418 } else {
3419 si_emit_graphics(device, cs);
3420 }
3421 }
3422
3423 static void
3424 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3425 {
3426 si_emit_compute(queue->device, cs);
3427 }
3428
3429 static VkResult
3430 radv_get_preamble_cs(struct radv_queue *queue,
3431 uint32_t scratch_size_per_wave,
3432 uint32_t scratch_waves,
3433 uint32_t compute_scratch_size_per_wave,
3434 uint32_t compute_scratch_waves,
3435 uint32_t esgs_ring_size,
3436 uint32_t gsvs_ring_size,
3437 bool needs_tess_rings,
3438 bool needs_gds,
3439 bool needs_gds_oa,
3440 bool needs_sample_positions,
3441 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
3442 struct radeon_cmdbuf **initial_preamble_cs,
3443 struct radeon_cmdbuf **continue_preamble_cs)
3444 {
3445 struct radeon_winsys_bo *scratch_bo = NULL;
3446 struct radeon_winsys_bo *descriptor_bo = NULL;
3447 struct radeon_winsys_bo *compute_scratch_bo = NULL;
3448 struct radeon_winsys_bo *esgs_ring_bo = NULL;
3449 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
3450 struct radeon_winsys_bo *tess_rings_bo = NULL;
3451 struct radeon_winsys_bo *gds_bo = NULL;
3452 struct radeon_winsys_bo *gds_oa_bo = NULL;
3453 struct radeon_cmdbuf *dest_cs[3] = {0};
3454 bool add_tess_rings = false, add_gds = false, add_gds_oa = false, add_sample_positions = false;
3455 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
3456 unsigned max_offchip_buffers;
3457 unsigned hs_offchip_param = 0;
3458 unsigned tess_offchip_ring_offset;
3459 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
3460 if (!queue->has_tess_rings) {
3461 if (needs_tess_rings)
3462 add_tess_rings = true;
3463 }
3464 if (!queue->has_gds) {
3465 if (needs_gds)
3466 add_gds = true;
3467 }
3468 if (!queue->has_gds_oa) {
3469 if (needs_gds_oa)
3470 add_gds_oa = true;
3471 }
3472 if (!queue->has_sample_positions) {
3473 if (needs_sample_positions)
3474 add_sample_positions = true;
3475 }
3476 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
3477 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
3478 &max_offchip_buffers);
3479 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
3480 tess_offchip_ring_size = max_offchip_buffers *
3481 queue->device->tess_offchip_block_dw_size * 4;
3482
3483 scratch_size_per_wave = MAX2(scratch_size_per_wave, queue->scratch_size_per_wave);
3484 if (scratch_size_per_wave)
3485 scratch_waves = MIN2(scratch_waves, UINT32_MAX / scratch_size_per_wave);
3486 else
3487 scratch_waves = 0;
3488
3489 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave, queue->compute_scratch_size_per_wave);
3490 if (compute_scratch_size_per_wave)
3491 compute_scratch_waves = MIN2(compute_scratch_waves, UINT32_MAX / compute_scratch_size_per_wave);
3492 else
3493 compute_scratch_waves = 0;
3494
3495 if (scratch_size_per_wave <= queue->scratch_size_per_wave &&
3496 scratch_waves <= queue->scratch_waves &&
3497 compute_scratch_size_per_wave <= queue->compute_scratch_size_per_wave &&
3498 compute_scratch_waves <= queue->compute_scratch_waves &&
3499 esgs_ring_size <= queue->esgs_ring_size &&
3500 gsvs_ring_size <= queue->gsvs_ring_size &&
3501 !add_tess_rings && !add_gds && !add_gds_oa && !add_sample_positions &&
3502 queue->initial_preamble_cs) {
3503 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3504 *initial_preamble_cs = queue->initial_preamble_cs;
3505 *continue_preamble_cs = queue->continue_preamble_cs;
3506 if (!scratch_size_per_wave && !compute_scratch_size_per_wave &&
3507 !esgs_ring_size && !gsvs_ring_size && !needs_tess_rings &&
3508 !needs_gds && !needs_gds_oa && !needs_sample_positions)
3509 *continue_preamble_cs = NULL;
3510 return VK_SUCCESS;
3511 }
3512
3513 uint32_t scratch_size = scratch_size_per_wave * scratch_waves;
3514 uint32_t queue_scratch_size = queue->scratch_size_per_wave * queue->scratch_waves;
3515 if (scratch_size > queue_scratch_size) {
3516 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3517 scratch_size,
3518 4096,
3519 RADEON_DOMAIN_VRAM,
3520 ring_bo_flags,
3521 RADV_BO_PRIORITY_SCRATCH);
3522 if (!scratch_bo)
3523 goto fail;
3524 } else
3525 scratch_bo = queue->scratch_bo;
3526
3527 uint32_t compute_scratch_size = compute_scratch_size_per_wave * compute_scratch_waves;
3528 uint32_t compute_queue_scratch_size = queue->compute_scratch_size_per_wave * queue->compute_scratch_waves;
3529 if (compute_scratch_size > compute_queue_scratch_size) {
3530 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3531 compute_scratch_size,
3532 4096,
3533 RADEON_DOMAIN_VRAM,
3534 ring_bo_flags,
3535 RADV_BO_PRIORITY_SCRATCH);
3536 if (!compute_scratch_bo)
3537 goto fail;
3538
3539 } else
3540 compute_scratch_bo = queue->compute_scratch_bo;
3541
3542 if (esgs_ring_size > queue->esgs_ring_size) {
3543 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3544 esgs_ring_size,
3545 4096,
3546 RADEON_DOMAIN_VRAM,
3547 ring_bo_flags,
3548 RADV_BO_PRIORITY_SCRATCH);
3549 if (!esgs_ring_bo)
3550 goto fail;
3551 } else {
3552 esgs_ring_bo = queue->esgs_ring_bo;
3553 esgs_ring_size = queue->esgs_ring_size;
3554 }
3555
3556 if (gsvs_ring_size > queue->gsvs_ring_size) {
3557 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3558 gsvs_ring_size,
3559 4096,
3560 RADEON_DOMAIN_VRAM,
3561 ring_bo_flags,
3562 RADV_BO_PRIORITY_SCRATCH);
3563 if (!gsvs_ring_bo)
3564 goto fail;
3565 } else {
3566 gsvs_ring_bo = queue->gsvs_ring_bo;
3567 gsvs_ring_size = queue->gsvs_ring_size;
3568 }
3569
3570 if (add_tess_rings) {
3571 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
3572 tess_offchip_ring_offset + tess_offchip_ring_size,
3573 256,
3574 RADEON_DOMAIN_VRAM,
3575 ring_bo_flags,
3576 RADV_BO_PRIORITY_SCRATCH);
3577 if (!tess_rings_bo)
3578 goto fail;
3579 } else {
3580 tess_rings_bo = queue->tess_rings_bo;
3581 }
3582
3583 if (add_gds) {
3584 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3585
3586 /* 4 streamout GDS counters.
3587 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3588 */
3589 gds_bo = queue->device->ws->buffer_create(queue->device->ws,
3590 256, 4,
3591 RADEON_DOMAIN_GDS,
3592 ring_bo_flags,
3593 RADV_BO_PRIORITY_SCRATCH);
3594 if (!gds_bo)
3595 goto fail;
3596 } else {
3597 gds_bo = queue->gds_bo;
3598 }
3599
3600 if (add_gds_oa) {
3601 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3602
3603 gds_oa_bo = queue->device->ws->buffer_create(queue->device->ws,
3604 4, 1,
3605 RADEON_DOMAIN_OA,
3606 ring_bo_flags,
3607 RADV_BO_PRIORITY_SCRATCH);
3608 if (!gds_oa_bo)
3609 goto fail;
3610 } else {
3611 gds_oa_bo = queue->gds_oa_bo;
3612 }
3613
3614 if (scratch_bo != queue->scratch_bo ||
3615 esgs_ring_bo != queue->esgs_ring_bo ||
3616 gsvs_ring_bo != queue->gsvs_ring_bo ||
3617 tess_rings_bo != queue->tess_rings_bo ||
3618 add_sample_positions) {
3619 uint32_t size = 0;
3620 if (gsvs_ring_bo || esgs_ring_bo ||
3621 tess_rings_bo || add_sample_positions) {
3622 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
3623 if (add_sample_positions)
3624 size += 128; /* 64+32+16+8 = 120 bytes */
3625 }
3626 else if (scratch_bo)
3627 size = 8; /* 2 dword */
3628
3629 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
3630 size,
3631 4096,
3632 RADEON_DOMAIN_VRAM,
3633 RADEON_FLAG_CPU_ACCESS |
3634 RADEON_FLAG_NO_INTERPROCESS_SHARING |
3635 RADEON_FLAG_READ_ONLY,
3636 RADV_BO_PRIORITY_DESCRIPTOR);
3637 if (!descriptor_bo)
3638 goto fail;
3639 } else
3640 descriptor_bo = queue->descriptor_bo;
3641
3642 if (descriptor_bo != queue->descriptor_bo) {
3643 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
3644 if (!map)
3645 goto fail;
3646
3647 if (scratch_bo) {
3648 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
3649 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3650 S_008F04_SWIZZLE_ENABLE(1);
3651 map[0] = scratch_va;
3652 map[1] = rsrc1;
3653 }
3654
3655 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
3656 fill_geom_tess_rings(queue, map, add_sample_positions,
3657 esgs_ring_size, esgs_ring_bo,
3658 gsvs_ring_size, gsvs_ring_bo,
3659 tess_factor_ring_size,
3660 tess_offchip_ring_offset,
3661 tess_offchip_ring_size,
3662 tess_rings_bo);
3663
3664 queue->device->ws->buffer_unmap(descriptor_bo);
3665 }
3666
3667 for(int i = 0; i < 3; ++i) {
3668 struct radeon_cmdbuf *cs = NULL;
3669 cs = queue->device->ws->cs_create(queue->device->ws,
3670 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
3671 if (!cs)
3672 goto fail;
3673
3674 dest_cs[i] = cs;
3675
3676 if (scratch_bo)
3677 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3678
3679 /* Emit initial configuration. */
3680 switch (queue->queue_family_index) {
3681 case RADV_QUEUE_GENERAL:
3682 radv_init_graphics_state(cs, queue);
3683 break;
3684 case RADV_QUEUE_COMPUTE:
3685 radv_init_compute_state(cs, queue);
3686 break;
3687 case RADV_QUEUE_TRANSFER:
3688 break;
3689 }
3690
3691 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
3692 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3693 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3694
3695 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3696 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3697 }
3698
3699 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
3700 gsvs_ring_bo, gsvs_ring_size);
3701 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
3702 tess_factor_ring_size, tess_rings_bo);
3703 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
3704 radv_emit_compute_scratch(queue, cs, compute_scratch_size_per_wave,
3705 compute_scratch_waves, compute_scratch_bo);
3706 radv_emit_graphics_scratch(queue, cs, scratch_size_per_wave,
3707 scratch_waves, scratch_bo);
3708
3709 if (gds_bo)
3710 radv_cs_add_buffer(queue->device->ws, cs, gds_bo);
3711 if (gds_oa_bo)
3712 radv_cs_add_buffer(queue->device->ws, cs, gds_oa_bo);
3713
3714 if (queue->device->trace_bo)
3715 radv_cs_add_buffer(queue->device->ws, cs, queue->device->trace_bo);
3716
3717 if (queue->device->border_color_data.bo)
3718 radv_cs_add_buffer(queue->device->ws, cs,
3719 queue->device->border_color_data.bo);
3720
3721 if (i == 0) {
3722 si_cs_emit_cache_flush(cs,
3723 queue->device->physical_device->rad_info.chip_class,
3724 NULL, 0,
3725 queue->queue_family_index == RING_COMPUTE &&
3726 queue->device->physical_device->rad_info.chip_class >= GFX7,
3727 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
3728 RADV_CMD_FLAG_INV_ICACHE |
3729 RADV_CMD_FLAG_INV_SCACHE |
3730 RADV_CMD_FLAG_INV_VCACHE |
3731 RADV_CMD_FLAG_INV_L2 |
3732 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3733 } else if (i == 1) {
3734 si_cs_emit_cache_flush(cs,
3735 queue->device->physical_device->rad_info.chip_class,
3736 NULL, 0,
3737 queue->queue_family_index == RING_COMPUTE &&
3738 queue->device->physical_device->rad_info.chip_class >= GFX7,
3739 RADV_CMD_FLAG_INV_ICACHE |
3740 RADV_CMD_FLAG_INV_SCACHE |
3741 RADV_CMD_FLAG_INV_VCACHE |
3742 RADV_CMD_FLAG_INV_L2 |
3743 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3744 }
3745
3746 if (queue->device->ws->cs_finalize(cs) != VK_SUCCESS)
3747 goto fail;
3748 }
3749
3750 if (queue->initial_full_flush_preamble_cs)
3751 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
3752
3753 if (queue->initial_preamble_cs)
3754 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
3755
3756 if (queue->continue_preamble_cs)
3757 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
3758
3759 queue->initial_full_flush_preamble_cs = dest_cs[0];
3760 queue->initial_preamble_cs = dest_cs[1];
3761 queue->continue_preamble_cs = dest_cs[2];
3762
3763 if (scratch_bo != queue->scratch_bo) {
3764 if (queue->scratch_bo)
3765 queue->device->ws->buffer_destroy(queue->scratch_bo);
3766 queue->scratch_bo = scratch_bo;
3767 }
3768 queue->scratch_size_per_wave = scratch_size_per_wave;
3769 queue->scratch_waves = scratch_waves;
3770
3771 if (compute_scratch_bo != queue->compute_scratch_bo) {
3772 if (queue->compute_scratch_bo)
3773 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
3774 queue->compute_scratch_bo = compute_scratch_bo;
3775 }
3776 queue->compute_scratch_size_per_wave = compute_scratch_size_per_wave;
3777 queue->compute_scratch_waves = compute_scratch_waves;
3778
3779 if (esgs_ring_bo != queue->esgs_ring_bo) {
3780 if (queue->esgs_ring_bo)
3781 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
3782 queue->esgs_ring_bo = esgs_ring_bo;
3783 queue->esgs_ring_size = esgs_ring_size;
3784 }
3785
3786 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
3787 if (queue->gsvs_ring_bo)
3788 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
3789 queue->gsvs_ring_bo = gsvs_ring_bo;
3790 queue->gsvs_ring_size = gsvs_ring_size;
3791 }
3792
3793 if (tess_rings_bo != queue->tess_rings_bo) {
3794 queue->tess_rings_bo = tess_rings_bo;
3795 queue->has_tess_rings = true;
3796 }
3797
3798 if (gds_bo != queue->gds_bo) {
3799 queue->gds_bo = gds_bo;
3800 queue->has_gds = true;
3801 }
3802
3803 if (gds_oa_bo != queue->gds_oa_bo) {
3804 queue->gds_oa_bo = gds_oa_bo;
3805 queue->has_gds_oa = true;
3806 }
3807
3808 if (descriptor_bo != queue->descriptor_bo) {
3809 if (queue->descriptor_bo)
3810 queue->device->ws->buffer_destroy(queue->descriptor_bo);
3811
3812 queue->descriptor_bo = descriptor_bo;
3813 }
3814
3815 if (add_sample_positions)
3816 queue->has_sample_positions = true;
3817
3818 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3819 *initial_preamble_cs = queue->initial_preamble_cs;
3820 *continue_preamble_cs = queue->continue_preamble_cs;
3821 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
3822 *continue_preamble_cs = NULL;
3823 return VK_SUCCESS;
3824 fail:
3825 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
3826 if (dest_cs[i])
3827 queue->device->ws->cs_destroy(dest_cs[i]);
3828 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
3829 queue->device->ws->buffer_destroy(descriptor_bo);
3830 if (scratch_bo && scratch_bo != queue->scratch_bo)
3831 queue->device->ws->buffer_destroy(scratch_bo);
3832 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
3833 queue->device->ws->buffer_destroy(compute_scratch_bo);
3834 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
3835 queue->device->ws->buffer_destroy(esgs_ring_bo);
3836 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
3837 queue->device->ws->buffer_destroy(gsvs_ring_bo);
3838 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
3839 queue->device->ws->buffer_destroy(tess_rings_bo);
3840 if (gds_bo && gds_bo != queue->gds_bo)
3841 queue->device->ws->buffer_destroy(gds_bo);
3842 if (gds_oa_bo && gds_oa_bo != queue->gds_oa_bo)
3843 queue->device->ws->buffer_destroy(gds_oa_bo);
3844
3845 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3846 }
3847
3848 static VkResult radv_alloc_sem_counts(struct radv_device *device,
3849 struct radv_winsys_sem_counts *counts,
3850 int num_sems,
3851 struct radv_semaphore_part **sems,
3852 const uint64_t *timeline_values,
3853 VkFence _fence,
3854 bool is_signal)
3855 {
3856 int syncobj_idx = 0, non_reset_idx = 0, sem_idx = 0, timeline_idx = 0;
3857
3858 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
3859 return VK_SUCCESS;
3860
3861 for (uint32_t i = 0; i < num_sems; i++) {
3862 switch(sems[i]->kind) {
3863 case RADV_SEMAPHORE_SYNCOBJ:
3864 counts->syncobj_count++;
3865 counts->syncobj_reset_count++;
3866 break;
3867 case RADV_SEMAPHORE_WINSYS:
3868 counts->sem_count++;
3869 break;
3870 case RADV_SEMAPHORE_NONE:
3871 break;
3872 case RADV_SEMAPHORE_TIMELINE:
3873 counts->syncobj_count++;
3874 break;
3875 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ:
3876 counts->timeline_syncobj_count++;
3877 break;
3878 }
3879 }
3880
3881 if (_fence != VK_NULL_HANDLE) {
3882 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3883
3884 struct radv_fence_part *part =
3885 fence->temporary.kind != RADV_FENCE_NONE ?
3886 &fence->temporary : &fence->permanent;
3887 if (part->kind == RADV_FENCE_SYNCOBJ)
3888 counts->syncobj_count++;
3889 }
3890
3891 if (counts->syncobj_count || counts->timeline_syncobj_count) {
3892 counts->points = (uint64_t *)malloc(
3893 sizeof(*counts->syncobj) * counts->syncobj_count +
3894 (sizeof(*counts->syncobj) + sizeof(*counts->points)) * counts->timeline_syncobj_count);
3895 if (!counts->points)
3896 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3897 counts->syncobj = (uint32_t*)(counts->points + counts->timeline_syncobj_count);
3898 }
3899
3900 if (counts->sem_count) {
3901 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
3902 if (!counts->sem) {
3903 free(counts->syncobj);
3904 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3905 }
3906 }
3907
3908 non_reset_idx = counts->syncobj_reset_count;
3909
3910 for (uint32_t i = 0; i < num_sems; i++) {
3911 switch(sems[i]->kind) {
3912 case RADV_SEMAPHORE_NONE:
3913 unreachable("Empty semaphore");
3914 break;
3915 case RADV_SEMAPHORE_SYNCOBJ:
3916 counts->syncobj[syncobj_idx++] = sems[i]->syncobj;
3917 break;
3918 case RADV_SEMAPHORE_WINSYS:
3919 counts->sem[sem_idx++] = sems[i]->ws_sem;
3920 break;
3921 case RADV_SEMAPHORE_TIMELINE: {
3922 pthread_mutex_lock(&sems[i]->timeline.mutex);
3923 struct radv_timeline_point *point = NULL;
3924 if (is_signal) {
3925 point = radv_timeline_add_point_locked(device, &sems[i]->timeline, timeline_values[i]);
3926 } else {
3927 point = radv_timeline_find_point_at_least_locked(device, &sems[i]->timeline, timeline_values[i]);
3928 }
3929
3930 pthread_mutex_unlock(&sems[i]->timeline.mutex);
3931
3932 if (point) {
3933 counts->syncobj[non_reset_idx++] = point->syncobj;
3934 } else {
3935 /* Explicitly remove the semaphore so we might not find
3936 * a point later post-submit. */
3937 sems[i] = NULL;
3938 }
3939 break;
3940 }
3941 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ:
3942 counts->syncobj[counts->syncobj_count + timeline_idx] = sems[i]->syncobj;
3943 counts->points[timeline_idx] = timeline_values[i];
3944 ++timeline_idx;
3945 break;
3946 }
3947 }
3948
3949 if (_fence != VK_NULL_HANDLE) {
3950 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3951
3952 struct radv_fence_part *part =
3953 fence->temporary.kind != RADV_FENCE_NONE ?
3954 &fence->temporary : &fence->permanent;
3955 if (part->kind == RADV_FENCE_SYNCOBJ)
3956 counts->syncobj[non_reset_idx++] = part->syncobj;
3957 }
3958
3959 assert(MAX2(syncobj_idx, non_reset_idx) <= counts->syncobj_count);
3960 counts->syncobj_count = MAX2(syncobj_idx, non_reset_idx);
3961
3962 return VK_SUCCESS;
3963 }
3964
3965 static void
3966 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
3967 {
3968 free(sem_info->wait.points);
3969 free(sem_info->wait.sem);
3970 free(sem_info->signal.points);
3971 free(sem_info->signal.sem);
3972 }
3973
3974
3975 static void radv_free_temp_syncobjs(struct radv_device *device,
3976 int num_sems,
3977 struct radv_semaphore_part *sems)
3978 {
3979 for (uint32_t i = 0; i < num_sems; i++) {
3980 radv_destroy_semaphore_part(device, sems + i);
3981 }
3982 }
3983
3984 static VkResult
3985 radv_alloc_sem_info(struct radv_device *device,
3986 struct radv_winsys_sem_info *sem_info,
3987 int num_wait_sems,
3988 struct radv_semaphore_part **wait_sems,
3989 const uint64_t *wait_values,
3990 int num_signal_sems,
3991 struct radv_semaphore_part **signal_sems,
3992 const uint64_t *signal_values,
3993 VkFence fence)
3994 {
3995 VkResult ret;
3996 memset(sem_info, 0, sizeof(*sem_info));
3997
3998 ret = radv_alloc_sem_counts(device, &sem_info->wait, num_wait_sems, wait_sems, wait_values, VK_NULL_HANDLE, false);
3999 if (ret)
4000 return ret;
4001 ret = radv_alloc_sem_counts(device, &sem_info->signal, num_signal_sems, signal_sems, signal_values, fence, true);
4002 if (ret)
4003 radv_free_sem_info(sem_info);
4004
4005 /* caller can override these */
4006 sem_info->cs_emit_wait = true;
4007 sem_info->cs_emit_signal = true;
4008 return ret;
4009 }
4010
4011 static void
4012 radv_finalize_timelines(struct radv_device *device,
4013 uint32_t num_wait_sems,
4014 struct radv_semaphore_part **wait_sems,
4015 const uint64_t *wait_values,
4016 uint32_t num_signal_sems,
4017 struct radv_semaphore_part **signal_sems,
4018 const uint64_t *signal_values,
4019 struct list_head *processing_list)
4020 {
4021 for (uint32_t i = 0; i < num_wait_sems; ++i) {
4022 if (wait_sems[i] && wait_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4023 pthread_mutex_lock(&wait_sems[i]->timeline.mutex);
4024 struct radv_timeline_point *point =
4025 radv_timeline_find_point_at_least_locked(device, &wait_sems[i]->timeline, wait_values[i]);
4026 point->wait_count -= 2;
4027 pthread_mutex_unlock(&wait_sems[i]->timeline.mutex);
4028 }
4029 }
4030 for (uint32_t i = 0; i < num_signal_sems; ++i) {
4031 if (signal_sems[i] && signal_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4032 pthread_mutex_lock(&signal_sems[i]->timeline.mutex);
4033 struct radv_timeline_point *point =
4034 radv_timeline_find_point_at_least_locked(device, &signal_sems[i]->timeline, signal_values[i]);
4035 signal_sems[i]->timeline.highest_submitted =
4036 MAX2(signal_sems[i]->timeline.highest_submitted, point->value);
4037 point->wait_count -= 2;
4038 radv_timeline_trigger_waiters_locked(&signal_sems[i]->timeline, processing_list);
4039 pthread_mutex_unlock(&signal_sems[i]->timeline.mutex);
4040 } else if (signal_sems[i] && signal_sems[i]->kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ) {
4041 signal_sems[i]->timeline_syncobj.max_point =
4042 MAX2(signal_sems[i]->timeline_syncobj.max_point, signal_values[i]);
4043 }
4044 }
4045 }
4046
4047 static VkResult
4048 radv_sparse_buffer_bind_memory(struct radv_device *device,
4049 const VkSparseBufferMemoryBindInfo *bind)
4050 {
4051 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
4052 VkResult result;
4053
4054 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4055 struct radv_device_memory *mem = NULL;
4056
4057 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4058 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4059
4060 result = device->ws->buffer_virtual_bind(buffer->bo,
4061 bind->pBinds[i].resourceOffset,
4062 bind->pBinds[i].size,
4063 mem ? mem->bo : NULL,
4064 bind->pBinds[i].memoryOffset);
4065 if (result != VK_SUCCESS)
4066 return result;
4067 }
4068
4069 return VK_SUCCESS;
4070 }
4071
4072 static VkResult
4073 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
4074 const VkSparseImageOpaqueMemoryBindInfo *bind)
4075 {
4076 RADV_FROM_HANDLE(radv_image, image, bind->image);
4077 VkResult result;
4078
4079 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4080 struct radv_device_memory *mem = NULL;
4081
4082 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4083 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4084
4085 result = device->ws->buffer_virtual_bind(image->bo,
4086 bind->pBinds[i].resourceOffset,
4087 bind->pBinds[i].size,
4088 mem ? mem->bo : NULL,
4089 bind->pBinds[i].memoryOffset);
4090 if (result != VK_SUCCESS)
4091 return result;
4092 }
4093
4094 return VK_SUCCESS;
4095 }
4096
4097 static VkResult
4098 radv_get_preambles(struct radv_queue *queue,
4099 const VkCommandBuffer *cmd_buffers,
4100 uint32_t cmd_buffer_count,
4101 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
4102 struct radeon_cmdbuf **initial_preamble_cs,
4103 struct radeon_cmdbuf **continue_preamble_cs)
4104 {
4105 uint32_t scratch_size_per_wave = 0, waves_wanted = 0;
4106 uint32_t compute_scratch_size_per_wave = 0, compute_waves_wanted = 0;
4107 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
4108 bool tess_rings_needed = false;
4109 bool gds_needed = false;
4110 bool gds_oa_needed = false;
4111 bool sample_positions_needed = false;
4112
4113 for (uint32_t j = 0; j < cmd_buffer_count; j++) {
4114 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
4115 cmd_buffers[j]);
4116
4117 scratch_size_per_wave = MAX2(scratch_size_per_wave, cmd_buffer->scratch_size_per_wave_needed);
4118 waves_wanted = MAX2(waves_wanted, cmd_buffer->scratch_waves_wanted);
4119 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave,
4120 cmd_buffer->compute_scratch_size_per_wave_needed);
4121 compute_waves_wanted = MAX2(compute_waves_wanted,
4122 cmd_buffer->compute_scratch_waves_wanted);
4123 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
4124 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
4125 tess_rings_needed |= cmd_buffer->tess_rings_needed;
4126 gds_needed |= cmd_buffer->gds_needed;
4127 gds_oa_needed |= cmd_buffer->gds_oa_needed;
4128 sample_positions_needed |= cmd_buffer->sample_positions_needed;
4129 }
4130
4131 return radv_get_preamble_cs(queue, scratch_size_per_wave, waves_wanted,
4132 compute_scratch_size_per_wave, compute_waves_wanted,
4133 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
4134 gds_needed, gds_oa_needed, sample_positions_needed,
4135 initial_full_flush_preamble_cs,
4136 initial_preamble_cs, continue_preamble_cs);
4137 }
4138
4139 struct radv_deferred_queue_submission {
4140 struct radv_queue *queue;
4141 VkCommandBuffer *cmd_buffers;
4142 uint32_t cmd_buffer_count;
4143
4144 /* Sparse bindings that happen on a queue. */
4145 VkSparseBufferMemoryBindInfo *buffer_binds;
4146 uint32_t buffer_bind_count;
4147 VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4148 uint32_t image_opaque_bind_count;
4149
4150 bool flush_caches;
4151 VkShaderStageFlags wait_dst_stage_mask;
4152 struct radv_semaphore_part **wait_semaphores;
4153 uint32_t wait_semaphore_count;
4154 struct radv_semaphore_part **signal_semaphores;
4155 uint32_t signal_semaphore_count;
4156 VkFence fence;
4157
4158 uint64_t *wait_values;
4159 uint64_t *signal_values;
4160
4161 struct radv_semaphore_part *temporary_semaphore_parts;
4162 uint32_t temporary_semaphore_part_count;
4163
4164 struct list_head queue_pending_list;
4165 uint32_t submission_wait_count;
4166 struct radv_timeline_waiter *wait_nodes;
4167
4168 struct list_head processing_list;
4169 };
4170
4171 struct radv_queue_submission {
4172 const VkCommandBuffer *cmd_buffers;
4173 uint32_t cmd_buffer_count;
4174
4175 /* Sparse bindings that happen on a queue. */
4176 const VkSparseBufferMemoryBindInfo *buffer_binds;
4177 uint32_t buffer_bind_count;
4178 const VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4179 uint32_t image_opaque_bind_count;
4180
4181 bool flush_caches;
4182 VkPipelineStageFlags wait_dst_stage_mask;
4183 const VkSemaphore *wait_semaphores;
4184 uint32_t wait_semaphore_count;
4185 const VkSemaphore *signal_semaphores;
4186 uint32_t signal_semaphore_count;
4187 VkFence fence;
4188
4189 const uint64_t *wait_values;
4190 uint32_t wait_value_count;
4191 const uint64_t *signal_values;
4192 uint32_t signal_value_count;
4193 };
4194
4195 static VkResult
4196 radv_queue_trigger_submission(struct radv_deferred_queue_submission *submission,
4197 uint32_t decrement,
4198 struct list_head *processing_list);
4199
4200 static VkResult
4201 radv_create_deferred_submission(struct radv_queue *queue,
4202 const struct radv_queue_submission *submission,
4203 struct radv_deferred_queue_submission **out)
4204 {
4205 struct radv_deferred_queue_submission *deferred = NULL;
4206 size_t size = sizeof(struct radv_deferred_queue_submission);
4207
4208 uint32_t temporary_count = 0;
4209 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4210 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4211 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE)
4212 ++temporary_count;
4213 }
4214
4215 size += submission->cmd_buffer_count * sizeof(VkCommandBuffer);
4216 size += submission->buffer_bind_count * sizeof(VkSparseBufferMemoryBindInfo);
4217 size += submission->image_opaque_bind_count * sizeof(VkSparseImageOpaqueMemoryBindInfo);
4218 size += submission->wait_semaphore_count * sizeof(struct radv_semaphore_part *);
4219 size += temporary_count * sizeof(struct radv_semaphore_part);
4220 size += submission->signal_semaphore_count * sizeof(struct radv_semaphore_part *);
4221 size += submission->wait_value_count * sizeof(uint64_t);
4222 size += submission->signal_value_count * sizeof(uint64_t);
4223 size += submission->wait_semaphore_count * sizeof(struct radv_timeline_waiter);
4224
4225 deferred = calloc(1, size);
4226 if (!deferred)
4227 return VK_ERROR_OUT_OF_HOST_MEMORY;
4228
4229 deferred->queue = queue;
4230
4231 deferred->cmd_buffers = (void*)(deferred + 1);
4232 deferred->cmd_buffer_count = submission->cmd_buffer_count;
4233 memcpy(deferred->cmd_buffers, submission->cmd_buffers,
4234 submission->cmd_buffer_count * sizeof(*deferred->cmd_buffers));
4235
4236 deferred->buffer_binds = (void*)(deferred->cmd_buffers + submission->cmd_buffer_count);
4237 deferred->buffer_bind_count = submission->buffer_bind_count;
4238 memcpy(deferred->buffer_binds, submission->buffer_binds,
4239 submission->buffer_bind_count * sizeof(*deferred->buffer_binds));
4240
4241 deferred->image_opaque_binds = (void*)(deferred->buffer_binds + submission->buffer_bind_count);
4242 deferred->image_opaque_bind_count = submission->image_opaque_bind_count;
4243 memcpy(deferred->image_opaque_binds, submission->image_opaque_binds,
4244 submission->image_opaque_bind_count * sizeof(*deferred->image_opaque_binds));
4245
4246 deferred->flush_caches = submission->flush_caches;
4247 deferred->wait_dst_stage_mask = submission->wait_dst_stage_mask;
4248
4249 deferred->wait_semaphores = (void*)(deferred->image_opaque_binds + deferred->image_opaque_bind_count);
4250 deferred->wait_semaphore_count = submission->wait_semaphore_count;
4251
4252 deferred->signal_semaphores = (void*)(deferred->wait_semaphores + deferred->wait_semaphore_count);
4253 deferred->signal_semaphore_count = submission->signal_semaphore_count;
4254
4255 deferred->fence = submission->fence;
4256
4257 deferred->temporary_semaphore_parts = (void*)(deferred->signal_semaphores + deferred->signal_semaphore_count);
4258 deferred->temporary_semaphore_part_count = temporary_count;
4259
4260 uint32_t temporary_idx = 0;
4261 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4262 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4263 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4264 deferred->wait_semaphores[i] = &deferred->temporary_semaphore_parts[temporary_idx];
4265 deferred->temporary_semaphore_parts[temporary_idx] = semaphore->temporary;
4266 semaphore->temporary.kind = RADV_SEMAPHORE_NONE;
4267 ++temporary_idx;
4268 } else
4269 deferred->wait_semaphores[i] = &semaphore->permanent;
4270 }
4271
4272 for (uint32_t i = 0; i < submission->signal_semaphore_count; ++i) {
4273 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->signal_semaphores[i]);
4274 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4275 deferred->signal_semaphores[i] = &semaphore->temporary;
4276 } else {
4277 deferred->signal_semaphores[i] = &semaphore->permanent;
4278 }
4279 }
4280
4281 deferred->wait_values = (void*)(deferred->temporary_semaphore_parts + temporary_count);
4282 memcpy(deferred->wait_values, submission->wait_values, submission->wait_value_count * sizeof(uint64_t));
4283 deferred->signal_values = deferred->wait_values + submission->wait_value_count;
4284 memcpy(deferred->signal_values, submission->signal_values, submission->signal_value_count * sizeof(uint64_t));
4285
4286 deferred->wait_nodes = (void*)(deferred->signal_values + submission->signal_value_count);
4287 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4288 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4289 deferred->submission_wait_count = 1 + submission->wait_semaphore_count;
4290
4291 *out = deferred;
4292 return VK_SUCCESS;
4293 }
4294
4295 static VkResult
4296 radv_queue_enqueue_submission(struct radv_deferred_queue_submission *submission,
4297 struct list_head *processing_list)
4298 {
4299 uint32_t wait_cnt = 0;
4300 struct radv_timeline_waiter *waiter = submission->wait_nodes;
4301 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4302 if (submission->wait_semaphores[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4303 pthread_mutex_lock(&submission->wait_semaphores[i]->timeline.mutex);
4304 if (submission->wait_semaphores[i]->timeline.highest_submitted < submission->wait_values[i]) {
4305 ++wait_cnt;
4306 waiter->value = submission->wait_values[i];
4307 waiter->submission = submission;
4308 list_addtail(&waiter->list, &submission->wait_semaphores[i]->timeline.waiters);
4309 ++waiter;
4310 }
4311 pthread_mutex_unlock(&submission->wait_semaphores[i]->timeline.mutex);
4312 }
4313 }
4314
4315 pthread_mutex_lock(&submission->queue->pending_mutex);
4316
4317 bool is_first = list_is_empty(&submission->queue->pending_submissions);
4318 list_addtail(&submission->queue_pending_list, &submission->queue->pending_submissions);
4319
4320 pthread_mutex_unlock(&submission->queue->pending_mutex);
4321
4322 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4323 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4324 * submission. */
4325 uint32_t decrement = submission->wait_semaphore_count - wait_cnt + (is_first ? 1 : 0);
4326 return radv_queue_trigger_submission(submission, decrement, processing_list);
4327 }
4328
4329 static void
4330 radv_queue_submission_update_queue(struct radv_deferred_queue_submission *submission,
4331 struct list_head *processing_list)
4332 {
4333 pthread_mutex_lock(&submission->queue->pending_mutex);
4334 list_del(&submission->queue_pending_list);
4335
4336 /* trigger the next submission in the queue. */
4337 if (!list_is_empty(&submission->queue->pending_submissions)) {
4338 struct radv_deferred_queue_submission *next_submission =
4339 list_first_entry(&submission->queue->pending_submissions,
4340 struct radv_deferred_queue_submission,
4341 queue_pending_list);
4342 radv_queue_trigger_submission(next_submission, 1, processing_list);
4343 }
4344 pthread_mutex_unlock(&submission->queue->pending_mutex);
4345
4346 pthread_cond_broadcast(&submission->queue->device->timeline_cond);
4347 }
4348
4349 static VkResult
4350 radv_queue_submit_deferred(struct radv_deferred_queue_submission *submission,
4351 struct list_head *processing_list)
4352 {
4353 RADV_FROM_HANDLE(radv_fence, fence, submission->fence);
4354 struct radv_queue *queue = submission->queue;
4355 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4356 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
4357 struct radeon_winsys_fence *base_fence = NULL;
4358 bool do_flush = submission->flush_caches || submission->wait_dst_stage_mask;
4359 bool can_patch = true;
4360 uint32_t advance;
4361 struct radv_winsys_sem_info sem_info;
4362 VkResult result;
4363 struct radeon_cmdbuf *initial_preamble_cs = NULL;
4364 struct radeon_cmdbuf *initial_flush_preamble_cs = NULL;
4365 struct radeon_cmdbuf *continue_preamble_cs = NULL;
4366
4367 if (fence) {
4368 /* Under most circumstances, out fences won't be temporary.
4369 * However, the spec does allow it for opaque_fd.
4370 *
4371 * From the Vulkan 1.0.53 spec:
4372 *
4373 * "If the import is temporary, the implementation must
4374 * restore the semaphore to its prior permanent state after
4375 * submitting the next semaphore wait operation."
4376 */
4377 struct radv_fence_part *part =
4378 fence->temporary.kind != RADV_FENCE_NONE ?
4379 &fence->temporary : &fence->permanent;
4380 if (part->kind == RADV_FENCE_WINSYS)
4381 base_fence = part->fence;
4382 }
4383
4384 result = radv_get_preambles(queue, submission->cmd_buffers,
4385 submission->cmd_buffer_count,
4386 &initial_preamble_cs,
4387 &initial_flush_preamble_cs,
4388 &continue_preamble_cs);
4389 if (result != VK_SUCCESS)
4390 goto fail;
4391
4392 result = radv_alloc_sem_info(queue->device,
4393 &sem_info,
4394 submission->wait_semaphore_count,
4395 submission->wait_semaphores,
4396 submission->wait_values,
4397 submission->signal_semaphore_count,
4398 submission->signal_semaphores,
4399 submission->signal_values,
4400 submission->fence);
4401 if (result != VK_SUCCESS)
4402 goto fail;
4403
4404 for (uint32_t i = 0; i < submission->buffer_bind_count; ++i) {
4405 result = radv_sparse_buffer_bind_memory(queue->device,
4406 submission->buffer_binds + i);
4407 if (result != VK_SUCCESS)
4408 goto fail;
4409 }
4410
4411 for (uint32_t i = 0; i < submission->image_opaque_bind_count; ++i) {
4412 result = radv_sparse_image_opaque_bind_memory(queue->device,
4413 submission->image_opaque_binds + i);
4414 if (result != VK_SUCCESS)
4415 goto fail;
4416 }
4417
4418 if (!submission->cmd_buffer_count) {
4419 result = queue->device->ws->cs_submit(ctx, queue->queue_idx,
4420 &queue->device->empty_cs[queue->queue_family_index],
4421 1, NULL, NULL,
4422 &sem_info, NULL,
4423 false, base_fence);
4424 if (result != VK_SUCCESS)
4425 goto fail;
4426 } else {
4427 struct radeon_cmdbuf **cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
4428 (submission->cmd_buffer_count));
4429
4430 for (uint32_t j = 0; j < submission->cmd_buffer_count; j++) {
4431 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, submission->cmd_buffers[j]);
4432 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
4433
4434 cs_array[j] = cmd_buffer->cs;
4435 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
4436 can_patch = false;
4437
4438 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
4439 }
4440
4441 for (uint32_t j = 0; j < submission->cmd_buffer_count; j += advance) {
4442 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
4443 const struct radv_winsys_bo_list *bo_list = NULL;
4444
4445 advance = MIN2(max_cs_submission,
4446 submission->cmd_buffer_count - j);
4447
4448 if (queue->device->trace_bo)
4449 *queue->device->trace_id_ptr = 0;
4450
4451 sem_info.cs_emit_wait = j == 0;
4452 sem_info.cs_emit_signal = j + advance == submission->cmd_buffer_count;
4453
4454 if (unlikely(queue->device->use_global_bo_list)) {
4455 pthread_mutex_lock(&queue->device->bo_list.mutex);
4456 bo_list = &queue->device->bo_list.list;
4457 }
4458
4459 result = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
4460 advance, initial_preamble, continue_preamble_cs,
4461 &sem_info, bo_list,
4462 can_patch, base_fence);
4463
4464 if (unlikely(queue->device->use_global_bo_list))
4465 pthread_mutex_unlock(&queue->device->bo_list.mutex);
4466
4467 if (result != VK_SUCCESS)
4468 goto fail;
4469
4470 if (queue->device->trace_bo) {
4471 radv_check_gpu_hangs(queue, cs_array[j]);
4472 }
4473 }
4474
4475 free(cs_array);
4476 }
4477
4478 radv_free_temp_syncobjs(queue->device,
4479 submission->temporary_semaphore_part_count,
4480 submission->temporary_semaphore_parts);
4481 radv_finalize_timelines(queue->device,
4482 submission->wait_semaphore_count,
4483 submission->wait_semaphores,
4484 submission->wait_values,
4485 submission->signal_semaphore_count,
4486 submission->signal_semaphores,
4487 submission->signal_values,
4488 processing_list);
4489 /* Has to happen after timeline finalization to make sure the
4490 * condition variable is only triggered when timelines and queue have
4491 * been updated. */
4492 radv_queue_submission_update_queue(submission, processing_list);
4493 radv_free_sem_info(&sem_info);
4494 free(submission);
4495 return VK_SUCCESS;
4496
4497 fail:
4498 if (result != VK_SUCCESS && result != VK_ERROR_DEVICE_LOST) {
4499 /* When something bad happened during the submission, such as
4500 * an out of memory issue, it might be hard to recover from
4501 * this inconsistent state. To avoid this sort of problem, we
4502 * assume that we are in a really bad situation and return
4503 * VK_ERROR_DEVICE_LOST to ensure the clients do not attempt
4504 * to submit the same job again to this device.
4505 */
4506 result = VK_ERROR_DEVICE_LOST;
4507 }
4508
4509 radv_free_temp_syncobjs(queue->device,
4510 submission->temporary_semaphore_part_count,
4511 submission->temporary_semaphore_parts);
4512 free(submission);
4513 return result;
4514 }
4515
4516 static VkResult
4517 radv_process_submissions(struct list_head *processing_list)
4518 {
4519 while(!list_is_empty(processing_list)) {
4520 struct radv_deferred_queue_submission *submission =
4521 list_first_entry(processing_list, struct radv_deferred_queue_submission, processing_list);
4522 list_del(&submission->processing_list);
4523
4524 VkResult result = radv_queue_submit_deferred(submission, processing_list);
4525 if (result != VK_SUCCESS)
4526 return result;
4527 }
4528 return VK_SUCCESS;
4529 }
4530
4531 static VkResult
4532 wait_for_submission_timelines_available(struct radv_deferred_queue_submission *submission,
4533 uint64_t timeout)
4534 {
4535 struct radv_device *device = submission->queue->device;
4536 uint32_t syncobj_count = 0;
4537 uint32_t syncobj_idx = 0;
4538
4539 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4540 if (submission->wait_semaphores[i]->kind != RADV_SEMAPHORE_TIMELINE_SYNCOBJ)
4541 continue;
4542
4543 if (submission->wait_semaphores[i]->timeline_syncobj.max_point >= submission->wait_values[i])
4544 continue;
4545 ++syncobj_count;
4546 }
4547
4548 if (!syncobj_count)
4549 return VK_SUCCESS;
4550
4551 uint64_t *points = malloc((sizeof(uint64_t) + sizeof(uint32_t)) * syncobj_count);
4552 if (!points)
4553 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4554
4555 uint32_t *syncobj = (uint32_t*)(points + syncobj_count);
4556
4557 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4558 if (submission->wait_semaphores[i]->kind != RADV_SEMAPHORE_TIMELINE_SYNCOBJ)
4559 continue;
4560
4561 if (submission->wait_semaphores[i]->timeline_syncobj.max_point >= submission->wait_values[i])
4562 continue;
4563
4564 syncobj[syncobj_idx] = submission->wait_semaphores[i]->syncobj;
4565 points[syncobj_idx] = submission->wait_values[i];
4566 ++syncobj_idx;
4567 }
4568 bool success = device->ws->wait_timeline_syncobj(device->ws, syncobj, points, syncobj_idx, true, true, timeout);
4569
4570 free(points);
4571 return success ? VK_SUCCESS : VK_TIMEOUT;
4572 }
4573
4574 static void* radv_queue_submission_thread_run(void *q)
4575 {
4576 struct radv_queue *queue = q;
4577
4578 pthread_mutex_lock(&queue->thread_mutex);
4579 while (!p_atomic_read(&queue->thread_exit)) {
4580 struct radv_deferred_queue_submission *submission = queue->thread_submission;
4581 struct list_head processing_list;
4582 VkResult result = VK_SUCCESS;
4583 if (!submission) {
4584 pthread_cond_wait(&queue->thread_cond, &queue->thread_mutex);
4585 continue;
4586 }
4587 pthread_mutex_unlock(&queue->thread_mutex);
4588
4589 /* Wait at most 5 seconds so we have a chance to notice shutdown when
4590 * a semaphore never gets signaled. If it takes longer we just retry
4591 * the wait next iteration. */
4592 result = wait_for_submission_timelines_available(submission,
4593 radv_get_absolute_timeout(5000000000));
4594 if (result != VK_SUCCESS) {
4595 pthread_mutex_lock(&queue->thread_mutex);
4596 continue;
4597 }
4598
4599 /* The lock isn't held but nobody will add one until we finish
4600 * the current submission. */
4601 p_atomic_set(&queue->thread_submission, NULL);
4602
4603 list_inithead(&processing_list);
4604 list_addtail(&submission->processing_list, &processing_list);
4605 result = radv_process_submissions(&processing_list);
4606
4607 pthread_mutex_lock(&queue->thread_mutex);
4608 }
4609 pthread_mutex_unlock(&queue->thread_mutex);
4610 return NULL;
4611 }
4612
4613 static VkResult
4614 radv_queue_trigger_submission(struct radv_deferred_queue_submission *submission,
4615 uint32_t decrement,
4616 struct list_head *processing_list)
4617 {
4618 struct radv_queue *queue = submission->queue;
4619 int ret;
4620 if (p_atomic_add_return(&submission->submission_wait_count, -decrement))
4621 return VK_SUCCESS;
4622
4623 if (wait_for_submission_timelines_available(submission, radv_get_absolute_timeout(0)) == VK_SUCCESS) {
4624 list_addtail(&submission->processing_list, processing_list);
4625 return VK_SUCCESS;
4626 }
4627
4628 pthread_mutex_lock(&queue->thread_mutex);
4629
4630 /* A submission can only be ready for the thread if it doesn't have
4631 * any predecessors in the same queue, so there can only be one such
4632 * submission at a time. */
4633 assert(queue->thread_submission == NULL);
4634
4635 /* Only start the thread on demand to save resources for the many games
4636 * which only use binary semaphores. */
4637 if (!queue->thread_running) {
4638 ret = pthread_create(&queue->submission_thread, NULL,
4639 radv_queue_submission_thread_run, queue);
4640 if (ret) {
4641 pthread_mutex_unlock(&queue->thread_mutex);
4642 return vk_errorf(queue->device->instance,
4643 VK_ERROR_DEVICE_LOST,
4644 "Failed to start submission thread");
4645 }
4646 queue->thread_running = true;
4647 }
4648
4649 queue->thread_submission = submission;
4650 pthread_mutex_unlock(&queue->thread_mutex);
4651
4652 pthread_cond_signal(&queue->thread_cond);
4653 return VK_SUCCESS;
4654 }
4655
4656 static VkResult radv_queue_submit(struct radv_queue *queue,
4657 const struct radv_queue_submission *submission)
4658 {
4659 struct radv_deferred_queue_submission *deferred = NULL;
4660
4661 VkResult result = radv_create_deferred_submission(queue, submission, &deferred);
4662 if (result != VK_SUCCESS)
4663 return result;
4664
4665 struct list_head processing_list;
4666 list_inithead(&processing_list);
4667
4668 result = radv_queue_enqueue_submission(deferred, &processing_list);
4669 if (result != VK_SUCCESS) {
4670 /* If anything is in the list we leak. */
4671 assert(list_is_empty(&processing_list));
4672 return result;
4673 }
4674 return radv_process_submissions(&processing_list);
4675 }
4676
4677 bool
4678 radv_queue_internal_submit(struct radv_queue *queue, struct radeon_cmdbuf *cs)
4679 {
4680 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4681 struct radv_winsys_sem_info sem_info;
4682 VkResult result;
4683
4684 result = radv_alloc_sem_info(queue->device, &sem_info, 0, NULL, 0, 0,
4685 0, NULL, VK_NULL_HANDLE);
4686 if (result != VK_SUCCESS)
4687 return false;
4688
4689 result = queue->device->ws->cs_submit(ctx, queue->queue_idx, &cs, 1,
4690 NULL, NULL, &sem_info, NULL,
4691 false, NULL);
4692 radv_free_sem_info(&sem_info);
4693 if (result != VK_SUCCESS)
4694 return false;
4695
4696 return true;
4697
4698 }
4699
4700 /* Signals fence as soon as all the work currently put on queue is done. */
4701 static VkResult radv_signal_fence(struct radv_queue *queue,
4702 VkFence fence)
4703 {
4704 return radv_queue_submit(queue, &(struct radv_queue_submission) {
4705 .fence = fence
4706 });
4707 }
4708
4709 static bool radv_submit_has_effects(const VkSubmitInfo *info)
4710 {
4711 return info->commandBufferCount ||
4712 info->waitSemaphoreCount ||
4713 info->signalSemaphoreCount;
4714 }
4715
4716 VkResult radv_QueueSubmit(
4717 VkQueue _queue,
4718 uint32_t submitCount,
4719 const VkSubmitInfo* pSubmits,
4720 VkFence fence)
4721 {
4722 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4723 VkResult result;
4724 uint32_t fence_idx = 0;
4725 bool flushed_caches = false;
4726
4727 if (fence != VK_NULL_HANDLE) {
4728 for (uint32_t i = 0; i < submitCount; ++i)
4729 if (radv_submit_has_effects(pSubmits + i))
4730 fence_idx = i;
4731 } else
4732 fence_idx = UINT32_MAX;
4733
4734 for (uint32_t i = 0; i < submitCount; i++) {
4735 if (!radv_submit_has_effects(pSubmits + i) && fence_idx != i)
4736 continue;
4737
4738 VkPipelineStageFlags wait_dst_stage_mask = 0;
4739 for (unsigned j = 0; j < pSubmits[i].waitSemaphoreCount; ++j) {
4740 wait_dst_stage_mask |= pSubmits[i].pWaitDstStageMask[j];
4741 }
4742
4743 const VkTimelineSemaphoreSubmitInfo *timeline_info =
4744 vk_find_struct_const(pSubmits[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
4745
4746 result = radv_queue_submit(queue, &(struct radv_queue_submission) {
4747 .cmd_buffers = pSubmits[i].pCommandBuffers,
4748 .cmd_buffer_count = pSubmits[i].commandBufferCount,
4749 .wait_dst_stage_mask = wait_dst_stage_mask,
4750 .flush_caches = !flushed_caches,
4751 .wait_semaphores = pSubmits[i].pWaitSemaphores,
4752 .wait_semaphore_count = pSubmits[i].waitSemaphoreCount,
4753 .signal_semaphores = pSubmits[i].pSignalSemaphores,
4754 .signal_semaphore_count = pSubmits[i].signalSemaphoreCount,
4755 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
4756 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
4757 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
4758 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
4759 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
4760 });
4761 if (result != VK_SUCCESS)
4762 return result;
4763
4764 flushed_caches = true;
4765 }
4766
4767 if (fence != VK_NULL_HANDLE && !submitCount) {
4768 result = radv_signal_fence(queue, fence);
4769 if (result != VK_SUCCESS)
4770 return result;
4771 }
4772
4773 return VK_SUCCESS;
4774 }
4775
4776 static const char *
4777 radv_get_queue_family_name(struct radv_queue *queue)
4778 {
4779 switch (queue->queue_family_index) {
4780 case RADV_QUEUE_GENERAL:
4781 return "graphics";
4782 case RADV_QUEUE_COMPUTE:
4783 return "compute";
4784 case RADV_QUEUE_TRANSFER:
4785 return "transfer";
4786 default:
4787 unreachable("Unknown queue family");
4788 }
4789 }
4790
4791 VkResult radv_QueueWaitIdle(
4792 VkQueue _queue)
4793 {
4794 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4795
4796 pthread_mutex_lock(&queue->pending_mutex);
4797 while (!list_is_empty(&queue->pending_submissions)) {
4798 pthread_cond_wait(&queue->device->timeline_cond, &queue->pending_mutex);
4799 }
4800 pthread_mutex_unlock(&queue->pending_mutex);
4801
4802 if (!queue->device->ws->ctx_wait_idle(queue->hw_ctx,
4803 radv_queue_family_to_ring(queue->queue_family_index),
4804 queue->queue_idx)) {
4805 return vk_errorf(queue->device->instance, VK_ERROR_DEVICE_LOST,
4806 "Failed to wait for a '%s' queue to be idle. "
4807 "GPU hang ?", radv_get_queue_family_name(queue));
4808 }
4809
4810 return VK_SUCCESS;
4811 }
4812
4813 VkResult radv_DeviceWaitIdle(
4814 VkDevice _device)
4815 {
4816 RADV_FROM_HANDLE(radv_device, device, _device);
4817
4818 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
4819 for (unsigned q = 0; q < device->queue_count[i]; q++) {
4820 VkResult result =
4821 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
4822
4823 if (result != VK_SUCCESS)
4824 return result;
4825 }
4826 }
4827 return VK_SUCCESS;
4828 }
4829
4830 VkResult radv_EnumerateInstanceExtensionProperties(
4831 const char* pLayerName,
4832 uint32_t* pPropertyCount,
4833 VkExtensionProperties* pProperties)
4834 {
4835 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4836
4837 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
4838 if (radv_instance_extensions_supported.extensions[i]) {
4839 vk_outarray_append(&out, prop) {
4840 *prop = radv_instance_extensions[i];
4841 }
4842 }
4843 }
4844
4845 return vk_outarray_status(&out);
4846 }
4847
4848 VkResult radv_EnumerateDeviceExtensionProperties(
4849 VkPhysicalDevice physicalDevice,
4850 const char* pLayerName,
4851 uint32_t* pPropertyCount,
4852 VkExtensionProperties* pProperties)
4853 {
4854 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
4855 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4856
4857 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
4858 if (device->supported_extensions.extensions[i]) {
4859 vk_outarray_append(&out, prop) {
4860 *prop = radv_device_extensions[i];
4861 }
4862 }
4863 }
4864
4865 return vk_outarray_status(&out);
4866 }
4867
4868 PFN_vkVoidFunction radv_GetInstanceProcAddr(
4869 VkInstance _instance,
4870 const char* pName)
4871 {
4872 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4873
4874 /* The Vulkan 1.0 spec for vkGetInstanceProcAddr has a table of exactly
4875 * when we have to return valid function pointers, NULL, or it's left
4876 * undefined. See the table for exact details.
4877 */
4878 if (pName == NULL)
4879 return NULL;
4880
4881 #define LOOKUP_RADV_ENTRYPOINT(entrypoint) \
4882 if (strcmp(pName, "vk" #entrypoint) == 0) \
4883 return (PFN_vkVoidFunction)radv_##entrypoint
4884
4885 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceExtensionProperties);
4886 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceLayerProperties);
4887 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceVersion);
4888 LOOKUP_RADV_ENTRYPOINT(CreateInstance);
4889
4890 /* GetInstanceProcAddr() can also be called with a NULL instance.
4891 * See https://gitlab.khronos.org/vulkan/vulkan/issues/2057
4892 */
4893 LOOKUP_RADV_ENTRYPOINT(GetInstanceProcAddr);
4894
4895 #undef LOOKUP_RADV_ENTRYPOINT
4896
4897 if (instance == NULL)
4898 return NULL;
4899
4900 int idx = radv_get_instance_entrypoint_index(pName);
4901 if (idx >= 0)
4902 return instance->dispatch.entrypoints[idx];
4903
4904 idx = radv_get_physical_device_entrypoint_index(pName);
4905 if (idx >= 0)
4906 return instance->physical_device_dispatch.entrypoints[idx];
4907
4908 idx = radv_get_device_entrypoint_index(pName);
4909 if (idx >= 0)
4910 return instance->device_dispatch.entrypoints[idx];
4911
4912 return NULL;
4913 }
4914
4915 /* The loader wants us to expose a second GetInstanceProcAddr function
4916 * to work around certain LD_PRELOAD issues seen in apps.
4917 */
4918 PUBLIC
4919 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4920 VkInstance instance,
4921 const char* pName);
4922
4923 PUBLIC
4924 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4925 VkInstance instance,
4926 const char* pName)
4927 {
4928 return radv_GetInstanceProcAddr(instance, pName);
4929 }
4930
4931 PUBLIC
4932 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
4933 VkInstance _instance,
4934 const char* pName);
4935
4936 PUBLIC
4937 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
4938 VkInstance _instance,
4939 const char* pName)
4940 {
4941 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4942
4943 if (!pName || !instance)
4944 return NULL;
4945
4946 int idx = radv_get_physical_device_entrypoint_index(pName);
4947 if (idx < 0)
4948 return NULL;
4949
4950 return instance->physical_device_dispatch.entrypoints[idx];
4951 }
4952
4953 PFN_vkVoidFunction radv_GetDeviceProcAddr(
4954 VkDevice _device,
4955 const char* pName)
4956 {
4957 RADV_FROM_HANDLE(radv_device, device, _device);
4958
4959 if (!device || !pName)
4960 return NULL;
4961
4962 int idx = radv_get_device_entrypoint_index(pName);
4963 if (idx < 0)
4964 return NULL;
4965
4966 return device->dispatch.entrypoints[idx];
4967 }
4968
4969 bool radv_get_memory_fd(struct radv_device *device,
4970 struct radv_device_memory *memory,
4971 int *pFD)
4972 {
4973 struct radeon_bo_metadata metadata;
4974
4975 if (memory->image) {
4976 if (memory->image->tiling != VK_IMAGE_TILING_LINEAR)
4977 radv_init_metadata(device, memory->image, &metadata);
4978 device->ws->buffer_set_metadata(memory->bo, &metadata);
4979 }
4980
4981 return device->ws->buffer_get_fd(device->ws, memory->bo,
4982 pFD);
4983 }
4984
4985
4986 void
4987 radv_free_memory(struct radv_device *device,
4988 const VkAllocationCallbacks* pAllocator,
4989 struct radv_device_memory *mem)
4990 {
4991 if (mem == NULL)
4992 return;
4993
4994 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4995 if (mem->android_hardware_buffer)
4996 AHardwareBuffer_release(mem->android_hardware_buffer);
4997 #endif
4998
4999 if (mem->bo) {
5000 if (device->overallocation_disallowed) {
5001 mtx_lock(&device->overallocation_mutex);
5002 device->allocated_memory_size[mem->heap_index] -= mem->alloc_size;
5003 mtx_unlock(&device->overallocation_mutex);
5004 }
5005
5006 radv_bo_list_remove(device, mem->bo);
5007 device->ws->buffer_destroy(mem->bo);
5008 mem->bo = NULL;
5009 }
5010
5011 vk_object_base_finish(&mem->base);
5012 vk_free2(&device->vk.alloc, pAllocator, mem);
5013 }
5014
5015 static VkResult radv_alloc_memory(struct radv_device *device,
5016 const VkMemoryAllocateInfo* pAllocateInfo,
5017 const VkAllocationCallbacks* pAllocator,
5018 VkDeviceMemory* pMem)
5019 {
5020 struct radv_device_memory *mem;
5021 VkResult result;
5022 enum radeon_bo_domain domain;
5023 uint32_t flags = 0;
5024
5025 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
5026
5027 const VkImportMemoryFdInfoKHR *import_info =
5028 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
5029 const VkMemoryDedicatedAllocateInfo *dedicate_info =
5030 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
5031 const VkExportMemoryAllocateInfo *export_info =
5032 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
5033 const struct VkImportAndroidHardwareBufferInfoANDROID *ahb_import_info =
5034 vk_find_struct_const(pAllocateInfo->pNext,
5035 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID);
5036 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
5037 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
5038
5039 const struct wsi_memory_allocate_info *wsi_info =
5040 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
5041
5042 if (pAllocateInfo->allocationSize == 0 && !ahb_import_info &&
5043 !(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID))) {
5044 /* Apparently, this is allowed */
5045 *pMem = VK_NULL_HANDLE;
5046 return VK_SUCCESS;
5047 }
5048
5049 mem = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*mem), 8,
5050 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5051 if (mem == NULL)
5052 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5053
5054 vk_object_base_init(&device->vk, &mem->base,
5055 VK_OBJECT_TYPE_DEVICE_MEMORY);
5056
5057 if (wsi_info && wsi_info->implicit_sync)
5058 flags |= RADEON_FLAG_IMPLICIT_SYNC;
5059
5060 if (dedicate_info) {
5061 mem->image = radv_image_from_handle(dedicate_info->image);
5062 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
5063 } else {
5064 mem->image = NULL;
5065 mem->buffer = NULL;
5066 }
5067
5068 float priority_float = 0.5;
5069 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
5070 vk_find_struct_const(pAllocateInfo->pNext,
5071 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
5072 if (priority_ext)
5073 priority_float = priority_ext->priority;
5074
5075 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
5076 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
5077
5078 mem->user_ptr = NULL;
5079 mem->bo = NULL;
5080
5081 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
5082 mem->android_hardware_buffer = NULL;
5083 #endif
5084
5085 if (ahb_import_info) {
5086 result = radv_import_ahb_memory(device, mem, priority, ahb_import_info);
5087 if (result != VK_SUCCESS)
5088 goto fail;
5089 } else if(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID)) {
5090 result = radv_create_ahb_memory(device, mem, priority, pAllocateInfo);
5091 if (result != VK_SUCCESS)
5092 goto fail;
5093 } else if (import_info) {
5094 assert(import_info->handleType ==
5095 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5096 import_info->handleType ==
5097 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5098 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
5099 priority, NULL);
5100 if (!mem->bo) {
5101 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
5102 goto fail;
5103 } else {
5104 close(import_info->fd);
5105 }
5106
5107 if (mem->image && mem->image->plane_count == 1 &&
5108 !vk_format_is_depth_or_stencil(mem->image->vk_format)) {
5109 struct radeon_bo_metadata metadata;
5110 device->ws->buffer_get_metadata(mem->bo, &metadata);
5111
5112 struct radv_image_create_info create_info = {
5113 .no_metadata_planes = true,
5114 .bo_metadata = &metadata
5115 };
5116
5117 /* This gives a basic ability to import radeonsi images
5118 * that don't have DCC. This is not guaranteed by any
5119 * spec and can be removed after we support modifiers. */
5120 result = radv_image_create_layout(device, create_info, mem->image);
5121 if (result != VK_SUCCESS) {
5122 device->ws->buffer_destroy(mem->bo);
5123 goto fail;
5124 }
5125 }
5126 } else if (host_ptr_info) {
5127 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
5128 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
5129 pAllocateInfo->allocationSize,
5130 priority);
5131 if (!mem->bo) {
5132 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
5133 goto fail;
5134 } else {
5135 mem->user_ptr = host_ptr_info->pHostPointer;
5136 }
5137 } else {
5138 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
5139 uint32_t heap_index;
5140
5141 heap_index = device->physical_device->memory_properties.memoryTypes[pAllocateInfo->memoryTypeIndex].heapIndex;
5142 domain = device->physical_device->memory_domains[pAllocateInfo->memoryTypeIndex];
5143 flags |= device->physical_device->memory_flags[pAllocateInfo->memoryTypeIndex];
5144
5145 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
5146 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
5147 if (device->use_global_bo_list) {
5148 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
5149 }
5150 }
5151
5152 if (device->overallocation_disallowed) {
5153 uint64_t total_size =
5154 device->physical_device->memory_properties.memoryHeaps[heap_index].size;
5155
5156 mtx_lock(&device->overallocation_mutex);
5157 if (device->allocated_memory_size[heap_index] + alloc_size > total_size) {
5158 mtx_unlock(&device->overallocation_mutex);
5159 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
5160 goto fail;
5161 }
5162 device->allocated_memory_size[heap_index] += alloc_size;
5163 mtx_unlock(&device->overallocation_mutex);
5164 }
5165
5166 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
5167 domain, flags, priority);
5168
5169 if (!mem->bo) {
5170 if (device->overallocation_disallowed) {
5171 mtx_lock(&device->overallocation_mutex);
5172 device->allocated_memory_size[heap_index] -= alloc_size;
5173 mtx_unlock(&device->overallocation_mutex);
5174 }
5175 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
5176 goto fail;
5177 }
5178
5179 mem->heap_index = heap_index;
5180 mem->alloc_size = alloc_size;
5181 }
5182
5183 if (!wsi_info) {
5184 result = radv_bo_list_add(device, mem->bo);
5185 if (result != VK_SUCCESS)
5186 goto fail;
5187 }
5188
5189 *pMem = radv_device_memory_to_handle(mem);
5190
5191 return VK_SUCCESS;
5192
5193 fail:
5194 radv_free_memory(device, pAllocator,mem);
5195
5196 return result;
5197 }
5198
5199 VkResult radv_AllocateMemory(
5200 VkDevice _device,
5201 const VkMemoryAllocateInfo* pAllocateInfo,
5202 const VkAllocationCallbacks* pAllocator,
5203 VkDeviceMemory* pMem)
5204 {
5205 RADV_FROM_HANDLE(radv_device, device, _device);
5206 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
5207 }
5208
5209 void radv_FreeMemory(
5210 VkDevice _device,
5211 VkDeviceMemory _mem,
5212 const VkAllocationCallbacks* pAllocator)
5213 {
5214 RADV_FROM_HANDLE(radv_device, device, _device);
5215 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
5216
5217 radv_free_memory(device, pAllocator, mem);
5218 }
5219
5220 VkResult radv_MapMemory(
5221 VkDevice _device,
5222 VkDeviceMemory _memory,
5223 VkDeviceSize offset,
5224 VkDeviceSize size,
5225 VkMemoryMapFlags flags,
5226 void** ppData)
5227 {
5228 RADV_FROM_HANDLE(radv_device, device, _device);
5229 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
5230
5231 if (mem == NULL) {
5232 *ppData = NULL;
5233 return VK_SUCCESS;
5234 }
5235
5236 if (mem->user_ptr)
5237 *ppData = mem->user_ptr;
5238 else
5239 *ppData = device->ws->buffer_map(mem->bo);
5240
5241 if (*ppData) {
5242 *ppData += offset;
5243 return VK_SUCCESS;
5244 }
5245
5246 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
5247 }
5248
5249 void radv_UnmapMemory(
5250 VkDevice _device,
5251 VkDeviceMemory _memory)
5252 {
5253 RADV_FROM_HANDLE(radv_device, device, _device);
5254 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
5255
5256 if (mem == NULL)
5257 return;
5258
5259 if (mem->user_ptr == NULL)
5260 device->ws->buffer_unmap(mem->bo);
5261 }
5262
5263 VkResult radv_FlushMappedMemoryRanges(
5264 VkDevice _device,
5265 uint32_t memoryRangeCount,
5266 const VkMappedMemoryRange* pMemoryRanges)
5267 {
5268 return VK_SUCCESS;
5269 }
5270
5271 VkResult radv_InvalidateMappedMemoryRanges(
5272 VkDevice _device,
5273 uint32_t memoryRangeCount,
5274 const VkMappedMemoryRange* pMemoryRanges)
5275 {
5276 return VK_SUCCESS;
5277 }
5278
5279 void radv_GetBufferMemoryRequirements(
5280 VkDevice _device,
5281 VkBuffer _buffer,
5282 VkMemoryRequirements* pMemoryRequirements)
5283 {
5284 RADV_FROM_HANDLE(radv_device, device, _device);
5285 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5286
5287 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
5288
5289 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
5290 pMemoryRequirements->alignment = 4096;
5291 else
5292 pMemoryRequirements->alignment = 16;
5293
5294 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
5295 }
5296
5297 void radv_GetBufferMemoryRequirements2(
5298 VkDevice device,
5299 const VkBufferMemoryRequirementsInfo2 *pInfo,
5300 VkMemoryRequirements2 *pMemoryRequirements)
5301 {
5302 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
5303 &pMemoryRequirements->memoryRequirements);
5304 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5305 switch (ext->sType) {
5306 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5307 VkMemoryDedicatedRequirements *req =
5308 (VkMemoryDedicatedRequirements *) ext;
5309 req->requiresDedicatedAllocation = false;
5310 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5311 break;
5312 }
5313 default:
5314 break;
5315 }
5316 }
5317 }
5318
5319 void radv_GetImageMemoryRequirements(
5320 VkDevice _device,
5321 VkImage _image,
5322 VkMemoryRequirements* pMemoryRequirements)
5323 {
5324 RADV_FROM_HANDLE(radv_device, device, _device);
5325 RADV_FROM_HANDLE(radv_image, image, _image);
5326
5327 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
5328
5329 pMemoryRequirements->size = image->size;
5330 pMemoryRequirements->alignment = image->alignment;
5331 }
5332
5333 void radv_GetImageMemoryRequirements2(
5334 VkDevice device,
5335 const VkImageMemoryRequirementsInfo2 *pInfo,
5336 VkMemoryRequirements2 *pMemoryRequirements)
5337 {
5338 radv_GetImageMemoryRequirements(device, pInfo->image,
5339 &pMemoryRequirements->memoryRequirements);
5340
5341 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
5342
5343 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5344 switch (ext->sType) {
5345 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5346 VkMemoryDedicatedRequirements *req =
5347 (VkMemoryDedicatedRequirements *) ext;
5348 req->requiresDedicatedAllocation = image->shareable &&
5349 image->tiling != VK_IMAGE_TILING_LINEAR;
5350 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5351 break;
5352 }
5353 default:
5354 break;
5355 }
5356 }
5357 }
5358
5359 void radv_GetImageSparseMemoryRequirements(
5360 VkDevice device,
5361 VkImage image,
5362 uint32_t* pSparseMemoryRequirementCount,
5363 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
5364 {
5365 stub();
5366 }
5367
5368 void radv_GetImageSparseMemoryRequirements2(
5369 VkDevice device,
5370 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
5371 uint32_t* pSparseMemoryRequirementCount,
5372 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
5373 {
5374 stub();
5375 }
5376
5377 void radv_GetDeviceMemoryCommitment(
5378 VkDevice device,
5379 VkDeviceMemory memory,
5380 VkDeviceSize* pCommittedMemoryInBytes)
5381 {
5382 *pCommittedMemoryInBytes = 0;
5383 }
5384
5385 VkResult radv_BindBufferMemory2(VkDevice device,
5386 uint32_t bindInfoCount,
5387 const VkBindBufferMemoryInfo *pBindInfos)
5388 {
5389 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5390 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5391 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
5392
5393 if (mem) {
5394 buffer->bo = mem->bo;
5395 buffer->offset = pBindInfos[i].memoryOffset;
5396 } else {
5397 buffer->bo = NULL;
5398 }
5399 }
5400 return VK_SUCCESS;
5401 }
5402
5403 VkResult radv_BindBufferMemory(
5404 VkDevice device,
5405 VkBuffer buffer,
5406 VkDeviceMemory memory,
5407 VkDeviceSize memoryOffset)
5408 {
5409 const VkBindBufferMemoryInfo info = {
5410 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5411 .buffer = buffer,
5412 .memory = memory,
5413 .memoryOffset = memoryOffset
5414 };
5415
5416 return radv_BindBufferMemory2(device, 1, &info);
5417 }
5418
5419 VkResult radv_BindImageMemory2(VkDevice device,
5420 uint32_t bindInfoCount,
5421 const VkBindImageMemoryInfo *pBindInfos)
5422 {
5423 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5424 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5425 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
5426
5427 if (mem) {
5428 image->bo = mem->bo;
5429 image->offset = pBindInfos[i].memoryOffset;
5430 } else {
5431 image->bo = NULL;
5432 image->offset = 0;
5433 }
5434 }
5435 return VK_SUCCESS;
5436 }
5437
5438
5439 VkResult radv_BindImageMemory(
5440 VkDevice device,
5441 VkImage image,
5442 VkDeviceMemory memory,
5443 VkDeviceSize memoryOffset)
5444 {
5445 const VkBindImageMemoryInfo info = {
5446 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5447 .image = image,
5448 .memory = memory,
5449 .memoryOffset = memoryOffset
5450 };
5451
5452 return radv_BindImageMemory2(device, 1, &info);
5453 }
5454
5455 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo *info)
5456 {
5457 return info->bufferBindCount ||
5458 info->imageOpaqueBindCount ||
5459 info->imageBindCount ||
5460 info->waitSemaphoreCount ||
5461 info->signalSemaphoreCount;
5462 }
5463
5464 VkResult radv_QueueBindSparse(
5465 VkQueue _queue,
5466 uint32_t bindInfoCount,
5467 const VkBindSparseInfo* pBindInfo,
5468 VkFence fence)
5469 {
5470 RADV_FROM_HANDLE(radv_queue, queue, _queue);
5471 VkResult result;
5472 uint32_t fence_idx = 0;
5473
5474 if (fence != VK_NULL_HANDLE) {
5475 for (uint32_t i = 0; i < bindInfoCount; ++i)
5476 if (radv_sparse_bind_has_effects(pBindInfo + i))
5477 fence_idx = i;
5478 } else
5479 fence_idx = UINT32_MAX;
5480
5481 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5482 if (i != fence_idx && !radv_sparse_bind_has_effects(pBindInfo + i))
5483 continue;
5484
5485 const VkTimelineSemaphoreSubmitInfo *timeline_info =
5486 vk_find_struct_const(pBindInfo[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
5487
5488 VkResult result = radv_queue_submit(queue, &(struct radv_queue_submission) {
5489 .buffer_binds = pBindInfo[i].pBufferBinds,
5490 .buffer_bind_count = pBindInfo[i].bufferBindCount,
5491 .image_opaque_binds = pBindInfo[i].pImageOpaqueBinds,
5492 .image_opaque_bind_count = pBindInfo[i].imageOpaqueBindCount,
5493 .wait_semaphores = pBindInfo[i].pWaitSemaphores,
5494 .wait_semaphore_count = pBindInfo[i].waitSemaphoreCount,
5495 .signal_semaphores = pBindInfo[i].pSignalSemaphores,
5496 .signal_semaphore_count = pBindInfo[i].signalSemaphoreCount,
5497 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
5498 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
5499 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
5500 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
5501 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
5502 });
5503
5504 if (result != VK_SUCCESS)
5505 return result;
5506 }
5507
5508 if (fence != VK_NULL_HANDLE && !bindInfoCount) {
5509 result = radv_signal_fence(queue, fence);
5510 if (result != VK_SUCCESS)
5511 return result;
5512 }
5513
5514 return VK_SUCCESS;
5515 }
5516
5517 static void
5518 radv_destroy_fence_part(struct radv_device *device,
5519 struct radv_fence_part *part)
5520 {
5521 switch (part->kind) {
5522 case RADV_FENCE_NONE:
5523 break;
5524 case RADV_FENCE_WINSYS:
5525 device->ws->destroy_fence(part->fence);
5526 break;
5527 case RADV_FENCE_SYNCOBJ:
5528 device->ws->destroy_syncobj(device->ws, part->syncobj);
5529 break;
5530 case RADV_FENCE_WSI:
5531 part->fence_wsi->destroy(part->fence_wsi);
5532 break;
5533 default:
5534 unreachable("Invalid fence type");
5535 }
5536
5537 part->kind = RADV_FENCE_NONE;
5538 }
5539
5540 static void
5541 radv_destroy_fence(struct radv_device *device,
5542 const VkAllocationCallbacks *pAllocator,
5543 struct radv_fence *fence)
5544 {
5545 radv_destroy_fence_part(device, &fence->temporary);
5546 radv_destroy_fence_part(device, &fence->permanent);
5547
5548 vk_object_base_finish(&fence->base);
5549 vk_free2(&device->vk.alloc, pAllocator, fence);
5550 }
5551
5552 VkResult radv_CreateFence(
5553 VkDevice _device,
5554 const VkFenceCreateInfo* pCreateInfo,
5555 const VkAllocationCallbacks* pAllocator,
5556 VkFence* pFence)
5557 {
5558 RADV_FROM_HANDLE(radv_device, device, _device);
5559 const VkExportFenceCreateInfo *export =
5560 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
5561 VkExternalFenceHandleTypeFlags handleTypes =
5562 export ? export->handleTypes : 0;
5563 struct radv_fence *fence;
5564
5565 fence = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*fence), 8,
5566 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5567 if (!fence)
5568 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5569
5570 vk_object_base_init(&device->vk, &fence->base, VK_OBJECT_TYPE_FENCE);
5571
5572 if (device->always_use_syncobj || handleTypes) {
5573 fence->permanent.kind = RADV_FENCE_SYNCOBJ;
5574
5575 bool create_signaled = false;
5576 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5577 create_signaled = true;
5578
5579 int ret = device->ws->create_syncobj(device->ws, create_signaled,
5580 &fence->permanent.syncobj);
5581 if (ret) {
5582 radv_destroy_fence(device, pAllocator, fence);
5583 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5584 }
5585 } else {
5586 fence->permanent.kind = RADV_FENCE_WINSYS;
5587
5588 fence->permanent.fence = device->ws->create_fence();
5589 if (!fence->permanent.fence) {
5590 vk_free2(&device->vk.alloc, pAllocator, fence);
5591 radv_destroy_fence(device, pAllocator, fence);
5592 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5593 }
5594 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5595 device->ws->signal_fence(fence->permanent.fence);
5596 }
5597
5598 *pFence = radv_fence_to_handle(fence);
5599
5600 return VK_SUCCESS;
5601 }
5602
5603
5604 void radv_DestroyFence(
5605 VkDevice _device,
5606 VkFence _fence,
5607 const VkAllocationCallbacks* pAllocator)
5608 {
5609 RADV_FROM_HANDLE(radv_device, device, _device);
5610 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5611
5612 if (!fence)
5613 return;
5614
5615 radv_destroy_fence(device, pAllocator, fence);
5616 }
5617
5618 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
5619 uint32_t fenceCount, const VkFence *pFences)
5620 {
5621 for (uint32_t i = 0; i < fenceCount; ++i) {
5622 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5623
5624 struct radv_fence_part *part =
5625 fence->temporary.kind != RADV_FENCE_NONE ?
5626 &fence->temporary : &fence->permanent;
5627 if (part->kind != RADV_FENCE_WINSYS ||
5628 !device->ws->is_fence_waitable(part->fence))
5629 return false;
5630 }
5631 return true;
5632 }
5633
5634 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
5635 {
5636 for (uint32_t i = 0; i < fenceCount; ++i) {
5637 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5638
5639 struct radv_fence_part *part =
5640 fence->temporary.kind != RADV_FENCE_NONE ?
5641 &fence->temporary : &fence->permanent;
5642 if (part->kind != RADV_FENCE_SYNCOBJ)
5643 return false;
5644 }
5645 return true;
5646 }
5647
5648 VkResult radv_WaitForFences(
5649 VkDevice _device,
5650 uint32_t fenceCount,
5651 const VkFence* pFences,
5652 VkBool32 waitAll,
5653 uint64_t timeout)
5654 {
5655 RADV_FROM_HANDLE(radv_device, device, _device);
5656 timeout = radv_get_absolute_timeout(timeout);
5657
5658 if (device->always_use_syncobj &&
5659 radv_all_fences_syncobj(fenceCount, pFences))
5660 {
5661 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
5662 if (!handles)
5663 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5664
5665 for (uint32_t i = 0; i < fenceCount; ++i) {
5666 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5667
5668 struct radv_fence_part *part =
5669 fence->temporary.kind != RADV_FENCE_NONE ?
5670 &fence->temporary : &fence->permanent;
5671
5672 assert(part->kind == RADV_FENCE_SYNCOBJ);
5673 handles[i] = part->syncobj;
5674 }
5675
5676 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
5677
5678 free(handles);
5679 return success ? VK_SUCCESS : VK_TIMEOUT;
5680 }
5681
5682 if (!waitAll && fenceCount > 1) {
5683 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5684 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
5685 uint32_t wait_count = 0;
5686 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
5687 if (!fences)
5688 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5689
5690 for (uint32_t i = 0; i < fenceCount; ++i) {
5691 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5692
5693 struct radv_fence_part *part =
5694 fence->temporary.kind != RADV_FENCE_NONE ?
5695 &fence->temporary : &fence->permanent;
5696 assert(part->kind == RADV_FENCE_WINSYS);
5697
5698 if (device->ws->fence_wait(device->ws, part->fence, false, 0)) {
5699 free(fences);
5700 return VK_SUCCESS;
5701 }
5702
5703 fences[wait_count++] = part->fence;
5704 }
5705
5706 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
5707 waitAll, timeout - radv_get_current_time());
5708
5709 free(fences);
5710 return success ? VK_SUCCESS : VK_TIMEOUT;
5711 }
5712
5713 while(radv_get_current_time() <= timeout) {
5714 for (uint32_t i = 0; i < fenceCount; ++i) {
5715 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
5716 return VK_SUCCESS;
5717 }
5718 }
5719 return VK_TIMEOUT;
5720 }
5721
5722 for (uint32_t i = 0; i < fenceCount; ++i) {
5723 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5724 bool expired = false;
5725
5726 struct radv_fence_part *part =
5727 fence->temporary.kind != RADV_FENCE_NONE ?
5728 &fence->temporary : &fence->permanent;
5729
5730 switch (part->kind) {
5731 case RADV_FENCE_NONE:
5732 break;
5733 case RADV_FENCE_WINSYS:
5734 if (!device->ws->is_fence_waitable(part->fence)) {
5735 while (!device->ws->is_fence_waitable(part->fence) &&
5736 radv_get_current_time() <= timeout)
5737 /* Do nothing */;
5738 }
5739
5740 expired = device->ws->fence_wait(device->ws,
5741 part->fence,
5742 true, timeout);
5743 if (!expired)
5744 return VK_TIMEOUT;
5745 break;
5746 case RADV_FENCE_SYNCOBJ:
5747 if (!device->ws->wait_syncobj(device->ws,
5748 &part->syncobj, 1, true,
5749 timeout))
5750 return VK_TIMEOUT;
5751 break;
5752 case RADV_FENCE_WSI: {
5753 VkResult result = part->fence_wsi->wait(part->fence_wsi, timeout);
5754 if (result != VK_SUCCESS)
5755 return result;
5756 break;
5757 }
5758 default:
5759 unreachable("Invalid fence type");
5760 }
5761 }
5762
5763 return VK_SUCCESS;
5764 }
5765
5766 VkResult radv_ResetFences(VkDevice _device,
5767 uint32_t fenceCount,
5768 const VkFence *pFences)
5769 {
5770 RADV_FROM_HANDLE(radv_device, device, _device);
5771
5772 for (unsigned i = 0; i < fenceCount; ++i) {
5773 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5774
5775 /* From the Vulkan 1.0.53 spec:
5776 *
5777 * "If any member of pFences currently has its payload
5778 * imported with temporary permanence, that fence’s prior
5779 * permanent payload is irst restored. The remaining
5780 * operations described therefore operate on the restored
5781 * payload."
5782 */
5783 if (fence->temporary.kind != RADV_FENCE_NONE)
5784 radv_destroy_fence_part(device, &fence->temporary);
5785
5786 struct radv_fence_part *part = &fence->permanent;
5787
5788 switch (part->kind) {
5789 case RADV_FENCE_WSI:
5790 device->ws->reset_fence(part->fence);
5791 break;
5792 case RADV_FENCE_SYNCOBJ:
5793 device->ws->reset_syncobj(device->ws, part->syncobj);
5794 break;
5795 default:
5796 unreachable("Invalid fence type");
5797 }
5798 }
5799
5800 return VK_SUCCESS;
5801 }
5802
5803 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
5804 {
5805 RADV_FROM_HANDLE(radv_device, device, _device);
5806 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5807
5808 struct radv_fence_part *part =
5809 fence->temporary.kind != RADV_FENCE_NONE ?
5810 &fence->temporary : &fence->permanent;
5811
5812 switch (part->kind) {
5813 case RADV_FENCE_NONE:
5814 break;
5815 case RADV_FENCE_WINSYS:
5816 if (!device->ws->fence_wait(device->ws, part->fence, false, 0))
5817 return VK_NOT_READY;
5818 break;
5819 case RADV_FENCE_SYNCOBJ: {
5820 bool success = device->ws->wait_syncobj(device->ws,
5821 &part->syncobj, 1, true, 0);
5822 if (!success)
5823 return VK_NOT_READY;
5824 break;
5825 }
5826 case RADV_FENCE_WSI: {
5827 VkResult result = part->fence_wsi->wait(part->fence_wsi, 0);
5828 if (result != VK_SUCCESS) {
5829 if (result == VK_TIMEOUT)
5830 return VK_NOT_READY;
5831 return result;
5832 }
5833 break;
5834 }
5835 default:
5836 unreachable("Invalid fence type");
5837 }
5838
5839 return VK_SUCCESS;
5840 }
5841
5842
5843 // Queue semaphore functions
5844
5845 static void
5846 radv_create_timeline(struct radv_timeline *timeline, uint64_t value)
5847 {
5848 timeline->highest_signaled = value;
5849 timeline->highest_submitted = value;
5850 list_inithead(&timeline->points);
5851 list_inithead(&timeline->free_points);
5852 list_inithead(&timeline->waiters);
5853 pthread_mutex_init(&timeline->mutex, NULL);
5854 }
5855
5856 static void
5857 radv_destroy_timeline(struct radv_device *device,
5858 struct radv_timeline *timeline)
5859 {
5860 list_for_each_entry_safe(struct radv_timeline_point, point,
5861 &timeline->free_points, list) {
5862 list_del(&point->list);
5863 device->ws->destroy_syncobj(device->ws, point->syncobj);
5864 free(point);
5865 }
5866 list_for_each_entry_safe(struct radv_timeline_point, point,
5867 &timeline->points, list) {
5868 list_del(&point->list);
5869 device->ws->destroy_syncobj(device->ws, point->syncobj);
5870 free(point);
5871 }
5872 pthread_mutex_destroy(&timeline->mutex);
5873 }
5874
5875 static void
5876 radv_timeline_gc_locked(struct radv_device *device,
5877 struct radv_timeline *timeline)
5878 {
5879 list_for_each_entry_safe(struct radv_timeline_point, point,
5880 &timeline->points, list) {
5881 if (point->wait_count || point->value > timeline->highest_submitted)
5882 return;
5883
5884 if (device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, 0)) {
5885 timeline->highest_signaled = point->value;
5886 list_del(&point->list);
5887 list_add(&point->list, &timeline->free_points);
5888 }
5889 }
5890 }
5891
5892 static struct radv_timeline_point *
5893 radv_timeline_find_point_at_least_locked(struct radv_device *device,
5894 struct radv_timeline *timeline,
5895 uint64_t p)
5896 {
5897 radv_timeline_gc_locked(device, timeline);
5898
5899 if (p <= timeline->highest_signaled)
5900 return NULL;
5901
5902 list_for_each_entry(struct radv_timeline_point, point,
5903 &timeline->points, list) {
5904 if (point->value >= p) {
5905 ++point->wait_count;
5906 return point;
5907 }
5908 }
5909 return NULL;
5910 }
5911
5912 static struct radv_timeline_point *
5913 radv_timeline_add_point_locked(struct radv_device *device,
5914 struct radv_timeline *timeline,
5915 uint64_t p)
5916 {
5917 radv_timeline_gc_locked(device, timeline);
5918
5919 struct radv_timeline_point *ret = NULL;
5920 struct radv_timeline_point *prev = NULL;
5921 int r;
5922
5923 if (p <= timeline->highest_signaled)
5924 return NULL;
5925
5926 list_for_each_entry(struct radv_timeline_point, point,
5927 &timeline->points, list) {
5928 if (point->value == p) {
5929 return NULL;
5930 }
5931
5932 if (point->value < p)
5933 prev = point;
5934 }
5935
5936 if (list_is_empty(&timeline->free_points)) {
5937 ret = malloc(sizeof(struct radv_timeline_point));
5938 r = device->ws->create_syncobj(device->ws, false, &ret->syncobj);
5939 if (r) {
5940 free(ret);
5941 return NULL;
5942 }
5943 } else {
5944 ret = list_first_entry(&timeline->free_points, struct radv_timeline_point, list);
5945 list_del(&ret->list);
5946
5947 device->ws->reset_syncobj(device->ws, ret->syncobj);
5948 }
5949
5950 ret->value = p;
5951 ret->wait_count = 1;
5952
5953 if (prev) {
5954 list_add(&ret->list, &prev->list);
5955 } else {
5956 list_addtail(&ret->list, &timeline->points);
5957 }
5958 return ret;
5959 }
5960
5961
5962 static VkResult
5963 radv_timeline_wait(struct radv_device *device,
5964 struct radv_timeline *timeline,
5965 uint64_t value,
5966 uint64_t abs_timeout)
5967 {
5968 pthread_mutex_lock(&timeline->mutex);
5969
5970 while(timeline->highest_submitted < value) {
5971 struct timespec abstime;
5972 timespec_from_nsec(&abstime, abs_timeout);
5973
5974 pthread_cond_timedwait(&device->timeline_cond, &timeline->mutex, &abstime);
5975
5976 if (radv_get_current_time() >= abs_timeout && timeline->highest_submitted < value) {
5977 pthread_mutex_unlock(&timeline->mutex);
5978 return VK_TIMEOUT;
5979 }
5980 }
5981
5982 struct radv_timeline_point *point = radv_timeline_find_point_at_least_locked(device, timeline, value);
5983 pthread_mutex_unlock(&timeline->mutex);
5984 if (!point)
5985 return VK_SUCCESS;
5986
5987 bool success = device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, abs_timeout);
5988
5989 pthread_mutex_lock(&timeline->mutex);
5990 point->wait_count--;
5991 pthread_mutex_unlock(&timeline->mutex);
5992 return success ? VK_SUCCESS : VK_TIMEOUT;
5993 }
5994
5995 static void
5996 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
5997 struct list_head *processing_list)
5998 {
5999 list_for_each_entry_safe(struct radv_timeline_waiter, waiter,
6000 &timeline->waiters, list) {
6001 if (waiter->value > timeline->highest_submitted)
6002 continue;
6003
6004 radv_queue_trigger_submission(waiter->submission, 1, processing_list);
6005 list_del(&waiter->list);
6006 }
6007 }
6008
6009 static
6010 void radv_destroy_semaphore_part(struct radv_device *device,
6011 struct radv_semaphore_part *part)
6012 {
6013 switch(part->kind) {
6014 case RADV_SEMAPHORE_NONE:
6015 break;
6016 case RADV_SEMAPHORE_WINSYS:
6017 device->ws->destroy_sem(part->ws_sem);
6018 break;
6019 case RADV_SEMAPHORE_TIMELINE:
6020 radv_destroy_timeline(device, &part->timeline);
6021 break;
6022 case RADV_SEMAPHORE_SYNCOBJ:
6023 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ:
6024 device->ws->destroy_syncobj(device->ws, part->syncobj);
6025 break;
6026 }
6027 part->kind = RADV_SEMAPHORE_NONE;
6028 }
6029
6030 static VkSemaphoreTypeKHR
6031 radv_get_semaphore_type(const void *pNext, uint64_t *initial_value)
6032 {
6033 const VkSemaphoreTypeCreateInfo *type_info =
6034 vk_find_struct_const(pNext, SEMAPHORE_TYPE_CREATE_INFO);
6035
6036 if (!type_info)
6037 return VK_SEMAPHORE_TYPE_BINARY;
6038
6039 if (initial_value)
6040 *initial_value = type_info->initialValue;
6041 return type_info->semaphoreType;
6042 }
6043
6044 static void
6045 radv_destroy_semaphore(struct radv_device *device,
6046 const VkAllocationCallbacks *pAllocator,
6047 struct radv_semaphore *sem)
6048 {
6049 radv_destroy_semaphore_part(device, &sem->temporary);
6050 radv_destroy_semaphore_part(device, &sem->permanent);
6051 vk_object_base_finish(&sem->base);
6052 vk_free2(&device->vk.alloc, pAllocator, sem);
6053 }
6054
6055 VkResult radv_CreateSemaphore(
6056 VkDevice _device,
6057 const VkSemaphoreCreateInfo* pCreateInfo,
6058 const VkAllocationCallbacks* pAllocator,
6059 VkSemaphore* pSemaphore)
6060 {
6061 RADV_FROM_HANDLE(radv_device, device, _device);
6062 const VkExportSemaphoreCreateInfo *export =
6063 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
6064 VkExternalSemaphoreHandleTypeFlags handleTypes =
6065 export ? export->handleTypes : 0;
6066 uint64_t initial_value = 0;
6067 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pCreateInfo->pNext, &initial_value);
6068
6069 struct radv_semaphore *sem = vk_alloc2(&device->vk.alloc, pAllocator,
6070 sizeof(*sem), 8,
6071 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6072 if (!sem)
6073 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6074
6075 vk_object_base_init(&device->vk, &sem->base,
6076 VK_OBJECT_TYPE_SEMAPHORE);
6077
6078 sem->temporary.kind = RADV_SEMAPHORE_NONE;
6079 sem->permanent.kind = RADV_SEMAPHORE_NONE;
6080
6081 if (type == VK_SEMAPHORE_TYPE_TIMELINE &&
6082 device->physical_device->rad_info.has_timeline_syncobj) {
6083 int ret = device->ws->create_syncobj(device->ws, false, &sem->permanent.syncobj);
6084 if (ret) {
6085 radv_destroy_semaphore(device, pAllocator, sem);
6086 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6087 }
6088 device->ws->signal_syncobj(device->ws, sem->permanent.syncobj, initial_value);
6089 sem->permanent.timeline_syncobj.max_point = initial_value;
6090 sem->permanent.kind = RADV_SEMAPHORE_TIMELINE_SYNCOBJ;
6091 } else if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
6092 radv_create_timeline(&sem->permanent.timeline, initial_value);
6093 sem->permanent.kind = RADV_SEMAPHORE_TIMELINE;
6094 } else if (device->always_use_syncobj || handleTypes) {
6095 assert (device->physical_device->rad_info.has_syncobj);
6096 int ret = device->ws->create_syncobj(device->ws, false,
6097 &sem->permanent.syncobj);
6098 if (ret) {
6099 radv_destroy_semaphore(device, pAllocator, sem);
6100 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6101 }
6102 sem->permanent.kind = RADV_SEMAPHORE_SYNCOBJ;
6103 } else {
6104 sem->permanent.ws_sem = device->ws->create_sem(device->ws);
6105 if (!sem->permanent.ws_sem) {
6106 radv_destroy_semaphore(device, pAllocator, sem);
6107 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6108 }
6109 sem->permanent.kind = RADV_SEMAPHORE_WINSYS;
6110 }
6111
6112 *pSemaphore = radv_semaphore_to_handle(sem);
6113 return VK_SUCCESS;
6114 }
6115
6116 void radv_DestroySemaphore(
6117 VkDevice _device,
6118 VkSemaphore _semaphore,
6119 const VkAllocationCallbacks* pAllocator)
6120 {
6121 RADV_FROM_HANDLE(radv_device, device, _device);
6122 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
6123 if (!_semaphore)
6124 return;
6125
6126 radv_destroy_semaphore(device, pAllocator, sem);
6127 }
6128
6129 VkResult
6130 radv_GetSemaphoreCounterValue(VkDevice _device,
6131 VkSemaphore _semaphore,
6132 uint64_t* pValue)
6133 {
6134 RADV_FROM_HANDLE(radv_device, device, _device);
6135 RADV_FROM_HANDLE(radv_semaphore, semaphore, _semaphore);
6136
6137 struct radv_semaphore_part *part =
6138 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
6139
6140 switch (part->kind) {
6141 case RADV_SEMAPHORE_TIMELINE: {
6142 pthread_mutex_lock(&part->timeline.mutex);
6143 radv_timeline_gc_locked(device, &part->timeline);
6144 *pValue = part->timeline.highest_signaled;
6145 pthread_mutex_unlock(&part->timeline.mutex);
6146 return VK_SUCCESS;
6147 }
6148 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ: {
6149 return device->ws->query_syncobj(device->ws, part->syncobj, pValue);
6150 }
6151 case RADV_SEMAPHORE_NONE:
6152 case RADV_SEMAPHORE_SYNCOBJ:
6153 case RADV_SEMAPHORE_WINSYS:
6154 unreachable("Invalid semaphore type");
6155 }
6156 unreachable("Unhandled semaphore type");
6157 }
6158
6159
6160 static VkResult
6161 radv_wait_timelines(struct radv_device *device,
6162 const VkSemaphoreWaitInfo* pWaitInfo,
6163 uint64_t abs_timeout)
6164 {
6165 if ((pWaitInfo->flags & VK_SEMAPHORE_WAIT_ANY_BIT_KHR) && pWaitInfo->semaphoreCount > 1) {
6166 for (;;) {
6167 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
6168 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
6169 VkResult result = radv_timeline_wait(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], 0);
6170
6171 if (result == VK_SUCCESS)
6172 return VK_SUCCESS;
6173 }
6174 if (radv_get_current_time() > abs_timeout)
6175 return VK_TIMEOUT;
6176 }
6177 }
6178
6179 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
6180 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
6181 VkResult result = radv_timeline_wait(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], abs_timeout);
6182
6183 if (result != VK_SUCCESS)
6184 return result;
6185 }
6186 return VK_SUCCESS;
6187 }
6188 VkResult
6189 radv_WaitSemaphores(VkDevice _device,
6190 const VkSemaphoreWaitInfo* pWaitInfo,
6191 uint64_t timeout)
6192 {
6193 RADV_FROM_HANDLE(radv_device, device, _device);
6194 uint64_t abs_timeout = radv_get_absolute_timeout(timeout);
6195
6196 if (radv_semaphore_from_handle(pWaitInfo->pSemaphores[0])->permanent.kind == RADV_SEMAPHORE_TIMELINE)
6197 return radv_wait_timelines(device, pWaitInfo, abs_timeout);
6198
6199 if (pWaitInfo->semaphoreCount > UINT32_MAX / sizeof(uint32_t))
6200 return vk_errorf(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY, "semaphoreCount integer overflow");
6201
6202 bool wait_all = !(pWaitInfo->flags & VK_SEMAPHORE_WAIT_ANY_BIT_KHR);
6203 uint32_t *handles = malloc(sizeof(*handles) * pWaitInfo->semaphoreCount);
6204 if (!handles)
6205 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6206
6207 for (uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
6208 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
6209 handles[i] = semaphore->permanent.syncobj;
6210 }
6211
6212 bool success = device->ws->wait_timeline_syncobj(device->ws, handles, pWaitInfo->pValues,
6213 pWaitInfo->semaphoreCount, wait_all, false,
6214 abs_timeout);
6215 free(handles);
6216 return success ? VK_SUCCESS : VK_TIMEOUT;
6217 }
6218
6219 VkResult
6220 radv_SignalSemaphore(VkDevice _device,
6221 const VkSemaphoreSignalInfo* pSignalInfo)
6222 {
6223 RADV_FROM_HANDLE(radv_device, device, _device);
6224 RADV_FROM_HANDLE(radv_semaphore, semaphore, pSignalInfo->semaphore);
6225
6226 struct radv_semaphore_part *part =
6227 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
6228
6229 switch(part->kind) {
6230 case RADV_SEMAPHORE_TIMELINE: {
6231 pthread_mutex_lock(&part->timeline.mutex);
6232 radv_timeline_gc_locked(device, &part->timeline);
6233 part->timeline.highest_submitted = MAX2(part->timeline.highest_submitted, pSignalInfo->value);
6234 part->timeline.highest_signaled = MAX2(part->timeline.highest_signaled, pSignalInfo->value);
6235
6236 struct list_head processing_list;
6237 list_inithead(&processing_list);
6238 radv_timeline_trigger_waiters_locked(&part->timeline, &processing_list);
6239 pthread_mutex_unlock(&part->timeline.mutex);
6240
6241 VkResult result = radv_process_submissions(&processing_list);
6242
6243 /* This needs to happen after radv_process_submissions, so
6244 * that any submitted submissions that are now unblocked get
6245 * processed before we wake the application. This way we
6246 * ensure that any binary semaphores that are now unblocked
6247 * are usable by the application. */
6248 pthread_cond_broadcast(&device->timeline_cond);
6249
6250 return result;
6251 }
6252 case RADV_SEMAPHORE_TIMELINE_SYNCOBJ: {
6253 part->timeline_syncobj.max_point = MAX2(part->timeline_syncobj.max_point, pSignalInfo->value);
6254 device->ws->signal_syncobj(device->ws, part->syncobj, pSignalInfo->value);
6255 break;
6256 }
6257 case RADV_SEMAPHORE_NONE:
6258 case RADV_SEMAPHORE_SYNCOBJ:
6259 case RADV_SEMAPHORE_WINSYS:
6260 unreachable("Invalid semaphore type");
6261 }
6262 return VK_SUCCESS;
6263 }
6264
6265 static void radv_destroy_event(struct radv_device *device,
6266 const VkAllocationCallbacks* pAllocator,
6267 struct radv_event *event)
6268 {
6269 if (event->bo)
6270 device->ws->buffer_destroy(event->bo);
6271
6272 vk_object_base_finish(&event->base);
6273 vk_free2(&device->vk.alloc, pAllocator, event);
6274 }
6275
6276 VkResult radv_CreateEvent(
6277 VkDevice _device,
6278 const VkEventCreateInfo* pCreateInfo,
6279 const VkAllocationCallbacks* pAllocator,
6280 VkEvent* pEvent)
6281 {
6282 RADV_FROM_HANDLE(radv_device, device, _device);
6283 struct radv_event *event = vk_alloc2(&device->vk.alloc, pAllocator,
6284 sizeof(*event), 8,
6285 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6286
6287 if (!event)
6288 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6289
6290 vk_object_base_init(&device->vk, &event->base, VK_OBJECT_TYPE_EVENT);
6291
6292 event->bo = device->ws->buffer_create(device->ws, 8, 8,
6293 RADEON_DOMAIN_GTT,
6294 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
6295 RADV_BO_PRIORITY_FENCE);
6296 if (!event->bo) {
6297 radv_destroy_event(device, pAllocator, event);
6298 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6299 }
6300
6301 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
6302 if (!event->map) {
6303 radv_destroy_event(device, pAllocator, event);
6304 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6305 }
6306
6307 *pEvent = radv_event_to_handle(event);
6308
6309 return VK_SUCCESS;
6310 }
6311
6312 void radv_DestroyEvent(
6313 VkDevice _device,
6314 VkEvent _event,
6315 const VkAllocationCallbacks* pAllocator)
6316 {
6317 RADV_FROM_HANDLE(radv_device, device, _device);
6318 RADV_FROM_HANDLE(radv_event, event, _event);
6319
6320 if (!event)
6321 return;
6322
6323 radv_destroy_event(device, pAllocator, event);
6324 }
6325
6326 VkResult radv_GetEventStatus(
6327 VkDevice _device,
6328 VkEvent _event)
6329 {
6330 RADV_FROM_HANDLE(radv_event, event, _event);
6331
6332 if (*event->map == 1)
6333 return VK_EVENT_SET;
6334 return VK_EVENT_RESET;
6335 }
6336
6337 VkResult radv_SetEvent(
6338 VkDevice _device,
6339 VkEvent _event)
6340 {
6341 RADV_FROM_HANDLE(radv_event, event, _event);
6342 *event->map = 1;
6343
6344 return VK_SUCCESS;
6345 }
6346
6347 VkResult radv_ResetEvent(
6348 VkDevice _device,
6349 VkEvent _event)
6350 {
6351 RADV_FROM_HANDLE(radv_event, event, _event);
6352 *event->map = 0;
6353
6354 return VK_SUCCESS;
6355 }
6356
6357 static void
6358 radv_destroy_buffer(struct radv_device *device,
6359 const VkAllocationCallbacks *pAllocator,
6360 struct radv_buffer *buffer)
6361 {
6362 if ((buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) && buffer->bo)
6363 device->ws->buffer_destroy(buffer->bo);
6364
6365 vk_object_base_finish(&buffer->base);
6366 vk_free2(&device->vk.alloc, pAllocator, buffer);
6367 }
6368
6369 VkResult radv_CreateBuffer(
6370 VkDevice _device,
6371 const VkBufferCreateInfo* pCreateInfo,
6372 const VkAllocationCallbacks* pAllocator,
6373 VkBuffer* pBuffer)
6374 {
6375 RADV_FROM_HANDLE(radv_device, device, _device);
6376 struct radv_buffer *buffer;
6377
6378 if (pCreateInfo->size > RADV_MAX_MEMORY_ALLOCATION_SIZE)
6379 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
6380
6381 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
6382
6383 buffer = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*buffer), 8,
6384 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6385 if (buffer == NULL)
6386 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6387
6388 vk_object_base_init(&device->vk, &buffer->base, VK_OBJECT_TYPE_BUFFER);
6389
6390 buffer->size = pCreateInfo->size;
6391 buffer->usage = pCreateInfo->usage;
6392 buffer->bo = NULL;
6393 buffer->offset = 0;
6394 buffer->flags = pCreateInfo->flags;
6395
6396 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
6397 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
6398
6399 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
6400 buffer->bo = device->ws->buffer_create(device->ws,
6401 align64(buffer->size, 4096),
6402 4096, 0, RADEON_FLAG_VIRTUAL,
6403 RADV_BO_PRIORITY_VIRTUAL);
6404 if (!buffer->bo) {
6405 radv_destroy_buffer(device, pAllocator, buffer);
6406 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6407 }
6408 }
6409
6410 *pBuffer = radv_buffer_to_handle(buffer);
6411
6412 return VK_SUCCESS;
6413 }
6414
6415 void radv_DestroyBuffer(
6416 VkDevice _device,
6417 VkBuffer _buffer,
6418 const VkAllocationCallbacks* pAllocator)
6419 {
6420 RADV_FROM_HANDLE(radv_device, device, _device);
6421 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
6422
6423 if (!buffer)
6424 return;
6425
6426 radv_destroy_buffer(device, pAllocator, buffer);
6427 }
6428
6429 VkDeviceAddress radv_GetBufferDeviceAddress(
6430 VkDevice device,
6431 const VkBufferDeviceAddressInfo* pInfo)
6432 {
6433 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
6434 return radv_buffer_get_va(buffer->bo) + buffer->offset;
6435 }
6436
6437
6438 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device,
6439 const VkBufferDeviceAddressInfo* pInfo)
6440 {
6441 return 0;
6442 }
6443
6444 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device,
6445 const VkDeviceMemoryOpaqueCaptureAddressInfo* pInfo)
6446 {
6447 return 0;
6448 }
6449
6450 static inline unsigned
6451 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
6452 {
6453 if (stencil)
6454 return plane->surface.u.legacy.stencil_tiling_index[level];
6455 else
6456 return plane->surface.u.legacy.tiling_index[level];
6457 }
6458
6459 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
6460 {
6461 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
6462 }
6463
6464 static uint32_t
6465 radv_init_dcc_control_reg(struct radv_device *device,
6466 struct radv_image_view *iview)
6467 {
6468 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
6469 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
6470 unsigned max_compressed_block_size;
6471 unsigned independent_128b_blocks;
6472 unsigned independent_64b_blocks;
6473
6474 if (!radv_dcc_enabled(iview->image, iview->base_mip))
6475 return 0;
6476
6477 if (!device->physical_device->rad_info.has_dedicated_vram) {
6478 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6479 * dGPU and 64 for APU because all of our APUs to date use
6480 * DIMMs which have a request granularity size of 64B while all
6481 * other chips have a 32B request size.
6482 */
6483 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
6484 }
6485
6486 if (device->physical_device->rad_info.chip_class >= GFX10) {
6487 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6488 independent_64b_blocks = 0;
6489 independent_128b_blocks = 1;
6490 } else {
6491 independent_128b_blocks = 0;
6492
6493 if (iview->image->info.samples > 1) {
6494 if (iview->image->planes[0].surface.bpe == 1)
6495 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6496 else if (iview->image->planes[0].surface.bpe == 2)
6497 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6498 }
6499
6500 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
6501 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
6502 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
6503 /* If this DCC image is potentially going to be used in texture
6504 * fetches, we need some special settings.
6505 */
6506 independent_64b_blocks = 1;
6507 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6508 } else {
6509 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6510 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6511 * big as possible for better compression state.
6512 */
6513 independent_64b_blocks = 0;
6514 max_compressed_block_size = max_uncompressed_block_size;
6515 }
6516 }
6517
6518 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
6519 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
6520 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
6521 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
6522 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
6523 }
6524
6525 void
6526 radv_initialise_color_surface(struct radv_device *device,
6527 struct radv_color_buffer_info *cb,
6528 struct radv_image_view *iview)
6529 {
6530 const struct vk_format_description *desc;
6531 unsigned ntype, format, swap, endian;
6532 unsigned blend_clamp = 0, blend_bypass = 0;
6533 uint64_t va;
6534 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
6535 const struct radeon_surf *surf = &plane->surface;
6536
6537 desc = vk_format_description(iview->vk_format);
6538
6539 memset(cb, 0, sizeof(*cb));
6540
6541 /* Intensity is implemented as Red, so treat it that way. */
6542 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
6543
6544 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
6545
6546 cb->cb_color_base = va >> 8;
6547
6548 if (device->physical_device->rad_info.chip_class >= GFX9) {
6549 if (device->physical_device->rad_info.chip_class >= GFX10) {
6550 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6551 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6552 S_028EE0_CMASK_PIPE_ALIGNED(1) |
6553 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
6554 } else {
6555 struct gfx9_surf_meta_flags meta = {
6556 .rb_aligned = 1,
6557 .pipe_aligned = 1,
6558 };
6559
6560 if (surf->dcc_offset)
6561 meta = surf->u.gfx9.dcc;
6562
6563 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6564 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6565 S_028C74_RB_ALIGNED(meta.rb_aligned) |
6566 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
6567 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
6568 }
6569
6570 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
6571 cb->cb_color_base |= surf->tile_swizzle;
6572 } else {
6573 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
6574 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
6575
6576 cb->cb_color_base += level_info->offset >> 8;
6577 if (level_info->mode == RADEON_SURF_MODE_2D)
6578 cb->cb_color_base |= surf->tile_swizzle;
6579
6580 pitch_tile_max = level_info->nblk_x / 8 - 1;
6581 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
6582 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
6583
6584 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
6585 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
6586 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
6587
6588 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
6589
6590 if (radv_image_has_fmask(iview->image)) {
6591 if (device->physical_device->rad_info.chip_class >= GFX7)
6592 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
6593 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
6594 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
6595 } else {
6596 /* This must be set for fast clear to work without FMASK. */
6597 if (device->physical_device->rad_info.chip_class >= GFX7)
6598 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
6599 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
6600 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
6601 }
6602 }
6603
6604 /* CMASK variables */
6605 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6606 va += surf->cmask_offset;
6607 cb->cb_color_cmask = va >> 8;
6608
6609 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6610 va += surf->dcc_offset;
6611
6612 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
6613 device->physical_device->rad_info.chip_class <= GFX8)
6614 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
6615
6616 unsigned dcc_tile_swizzle = surf->tile_swizzle;
6617 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
6618
6619 cb->cb_dcc_base = va >> 8;
6620 cb->cb_dcc_base |= dcc_tile_swizzle;
6621
6622 /* GFX10 field has the same base shift as the GFX6 field. */
6623 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6624 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
6625 S_028C6C_SLICE_MAX_GFX10(max_slice);
6626
6627 if (iview->image->info.samples > 1) {
6628 unsigned log_samples = util_logbase2(iview->image->info.samples);
6629
6630 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
6631 S_028C74_NUM_FRAGMENTS(log_samples);
6632 }
6633
6634 if (radv_image_has_fmask(iview->image)) {
6635 va = radv_buffer_get_va(iview->bo) + iview->image->offset + surf->fmask_offset;
6636 cb->cb_color_fmask = va >> 8;
6637 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
6638 } else {
6639 cb->cb_color_fmask = cb->cb_color_base;
6640 }
6641
6642 ntype = radv_translate_color_numformat(iview->vk_format,
6643 desc,
6644 vk_format_get_first_non_void_channel(iview->vk_format));
6645 format = radv_translate_colorformat(iview->vk_format);
6646 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
6647 radv_finishme("Illegal color\n");
6648 swap = radv_translate_colorswap(iview->vk_format, false);
6649 endian = radv_colorformat_endian_swap(format);
6650
6651 /* blend clamp should be set for all NORM/SRGB types */
6652 if (ntype == V_028C70_NUMBER_UNORM ||
6653 ntype == V_028C70_NUMBER_SNORM ||
6654 ntype == V_028C70_NUMBER_SRGB)
6655 blend_clamp = 1;
6656
6657 /* set blend bypass according to docs if SINT/UINT or
6658 8/24 COLOR variants */
6659 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
6660 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
6661 format == V_028C70_COLOR_X24_8_32_FLOAT) {
6662 blend_clamp = 0;
6663 blend_bypass = 1;
6664 }
6665 #if 0
6666 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
6667 (format == V_028C70_COLOR_8 ||
6668 format == V_028C70_COLOR_8_8 ||
6669 format == V_028C70_COLOR_8_8_8_8))
6670 ->color_is_int8 = true;
6671 #endif
6672 cb->cb_color_info = S_028C70_FORMAT(format) |
6673 S_028C70_COMP_SWAP(swap) |
6674 S_028C70_BLEND_CLAMP(blend_clamp) |
6675 S_028C70_BLEND_BYPASS(blend_bypass) |
6676 S_028C70_SIMPLE_FLOAT(1) |
6677 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
6678 ntype != V_028C70_NUMBER_SNORM &&
6679 ntype != V_028C70_NUMBER_SRGB &&
6680 format != V_028C70_COLOR_8_24 &&
6681 format != V_028C70_COLOR_24_8) |
6682 S_028C70_NUMBER_TYPE(ntype) |
6683 S_028C70_ENDIAN(endian);
6684 if (radv_image_has_fmask(iview->image)) {
6685 cb->cb_color_info |= S_028C70_COMPRESSION(1);
6686 if (device->physical_device->rad_info.chip_class == GFX6) {
6687 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
6688 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
6689 }
6690
6691 if (radv_image_is_tc_compat_cmask(iview->image)) {
6692 /* Allow the texture block to read FMASK directly
6693 * without decompressing it. This bit must be cleared
6694 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6695 * otherwise the operation doesn't happen.
6696 */
6697 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6698
6699 /* Set CMASK into a tiling format that allows the
6700 * texture block to read it.
6701 */
6702 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
6703 }
6704 }
6705
6706 if (radv_image_has_cmask(iview->image) &&
6707 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
6708 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
6709
6710 if (radv_dcc_enabled(iview->image, iview->base_mip))
6711 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
6712
6713 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
6714
6715 /* This must be set for fast clear to work without FMASK. */
6716 if (!radv_image_has_fmask(iview->image) &&
6717 device->physical_device->rad_info.chip_class == GFX6) {
6718 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
6719 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
6720 }
6721
6722 if (device->physical_device->rad_info.chip_class >= GFX9) {
6723 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
6724
6725 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
6726 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
6727 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
6728 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
6729
6730 if (device->physical_device->rad_info.chip_class >= GFX10) {
6731 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
6732
6733 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
6734 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
6735 S_028EE0_RESOURCE_LEVEL(1);
6736 } else {
6737 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
6738 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
6739 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
6740 }
6741
6742 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
6743 S_028C68_MIP0_HEIGHT(height - 1) |
6744 S_028C68_MAX_MIP(iview->image->info.levels - 1);
6745 }
6746 }
6747
6748 static unsigned
6749 radv_calc_decompress_on_z_planes(struct radv_device *device,
6750 struct radv_image_view *iview)
6751 {
6752 unsigned max_zplanes = 0;
6753
6754 assert(radv_image_is_tc_compat_htile(iview->image));
6755
6756 if (device->physical_device->rad_info.chip_class >= GFX9) {
6757 /* Default value for 32-bit depth surfaces. */
6758 max_zplanes = 4;
6759
6760 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
6761 iview->image->info.samples > 1)
6762 max_zplanes = 2;
6763
6764 max_zplanes = max_zplanes + 1;
6765 } else {
6766 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
6767 /* Do not enable Z plane compression for 16-bit depth
6768 * surfaces because isn't supported on GFX8. Only
6769 * 32-bit depth surfaces are supported by the hardware.
6770 * This allows to maintain shader compatibility and to
6771 * reduce the number of depth decompressions.
6772 */
6773 max_zplanes = 1;
6774 } else {
6775 if (iview->image->info.samples <= 1)
6776 max_zplanes = 5;
6777 else if (iview->image->info.samples <= 4)
6778 max_zplanes = 3;
6779 else
6780 max_zplanes = 2;
6781 }
6782 }
6783
6784 return max_zplanes;
6785 }
6786
6787 void
6788 radv_initialise_ds_surface(struct radv_device *device,
6789 struct radv_ds_buffer_info *ds,
6790 struct radv_image_view *iview)
6791 {
6792 unsigned level = iview->base_mip;
6793 unsigned format, stencil_format;
6794 uint64_t va, s_offs, z_offs;
6795 bool stencil_only = false;
6796 const struct radv_image_plane *plane = &iview->image->planes[0];
6797 const struct radeon_surf *surf = &plane->surface;
6798
6799 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
6800
6801 memset(ds, 0, sizeof(*ds));
6802 switch (iview->image->vk_format) {
6803 case VK_FORMAT_D24_UNORM_S8_UINT:
6804 case VK_FORMAT_X8_D24_UNORM_PACK32:
6805 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6806 ds->offset_scale = 2.0f;
6807 break;
6808 case VK_FORMAT_D16_UNORM:
6809 case VK_FORMAT_D16_UNORM_S8_UINT:
6810 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6811 ds->offset_scale = 4.0f;
6812 break;
6813 case VK_FORMAT_D32_SFLOAT:
6814 case VK_FORMAT_D32_SFLOAT_S8_UINT:
6815 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6816 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6817 ds->offset_scale = 1.0f;
6818 break;
6819 case VK_FORMAT_S8_UINT:
6820 stencil_only = true;
6821 break;
6822 default:
6823 break;
6824 }
6825
6826 format = radv_translate_dbformat(iview->image->vk_format);
6827 stencil_format = surf->has_stencil ?
6828 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
6829
6830 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6831 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
6832 S_028008_SLICE_MAX(max_slice);
6833 if (device->physical_device->rad_info.chip_class >= GFX10) {
6834 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
6835 S_028008_SLICE_MAX_HI(max_slice >> 11);
6836 }
6837
6838 ds->db_htile_data_base = 0;
6839 ds->db_htile_surface = 0;
6840
6841 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6842 s_offs = z_offs = va;
6843
6844 if (device->physical_device->rad_info.chip_class >= GFX9) {
6845 assert(surf->u.gfx9.surf_offset == 0);
6846 s_offs += surf->u.gfx9.stencil_offset;
6847
6848 ds->db_z_info = S_028038_FORMAT(format) |
6849 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
6850 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6851 S_028038_MAXMIP(iview->image->info.levels - 1) |
6852 S_028038_ZRANGE_PRECISION(1);
6853 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
6854 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
6855
6856 if (device->physical_device->rad_info.chip_class == GFX9) {
6857 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
6858 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
6859 }
6860
6861 ds->db_depth_view |= S_028008_MIPID(level);
6862 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
6863 S_02801C_Y_MAX(iview->image->info.height - 1);
6864
6865 if (radv_htile_enabled(iview->image, level)) {
6866 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
6867
6868 if (radv_image_is_tc_compat_htile(iview->image)) {
6869 unsigned max_zplanes =
6870 radv_calc_decompress_on_z_planes(device, iview);
6871
6872 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6873
6874 if (device->physical_device->rad_info.chip_class >= GFX10) {
6875 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
6876 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
6877 } else {
6878 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
6879 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
6880 }
6881 }
6882
6883 if (!surf->has_stencil)
6884 /* Use all of the htile_buffer for depth if there's no stencil. */
6885 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
6886 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
6887 surf->htile_offset;
6888 ds->db_htile_data_base = va >> 8;
6889 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
6890 S_028ABC_PIPE_ALIGNED(1);
6891
6892 if (device->physical_device->rad_info.chip_class == GFX9) {
6893 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(1);
6894 }
6895 }
6896 } else {
6897 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
6898
6899 if (stencil_only)
6900 level_info = &surf->u.legacy.stencil_level[level];
6901
6902 z_offs += surf->u.legacy.level[level].offset;
6903 s_offs += surf->u.legacy.stencil_level[level].offset;
6904
6905 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
6906 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
6907 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
6908
6909 if (iview->image->info.samples > 1)
6910 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
6911
6912 if (device->physical_device->rad_info.chip_class >= GFX7) {
6913 struct radeon_info *info = &device->physical_device->rad_info;
6914 unsigned tiling_index = surf->u.legacy.tiling_index[level];
6915 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
6916 unsigned macro_index = surf->u.legacy.macro_tile_index;
6917 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
6918 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
6919 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
6920
6921 if (stencil_only)
6922 tile_mode = stencil_tile_mode;
6923
6924 ds->db_depth_info |=
6925 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
6926 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
6927 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
6928 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
6929 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
6930 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
6931 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
6932 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
6933 } else {
6934 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
6935 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6936 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
6937 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
6938 if (stencil_only)
6939 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6940 }
6941
6942 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
6943 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
6944 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
6945
6946 if (radv_htile_enabled(iview->image, level)) {
6947 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
6948
6949 if (!surf->has_stencil &&
6950 !radv_image_is_tc_compat_htile(iview->image))
6951 /* Use all of the htile_buffer for depth if there's no stencil. */
6952 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
6953
6954 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
6955 surf->htile_offset;
6956 ds->db_htile_data_base = va >> 8;
6957 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
6958
6959 if (radv_image_is_tc_compat_htile(iview->image)) {
6960 unsigned max_zplanes =
6961 radv_calc_decompress_on_z_planes(device, iview);
6962
6963 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
6964 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6965 }
6966 }
6967 }
6968
6969 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
6970 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
6971 }
6972
6973 VkResult radv_CreateFramebuffer(
6974 VkDevice _device,
6975 const VkFramebufferCreateInfo* pCreateInfo,
6976 const VkAllocationCallbacks* pAllocator,
6977 VkFramebuffer* pFramebuffer)
6978 {
6979 RADV_FROM_HANDLE(radv_device, device, _device);
6980 struct radv_framebuffer *framebuffer;
6981 const VkFramebufferAttachmentsCreateInfo *imageless_create_info =
6982 vk_find_struct_const(pCreateInfo->pNext,
6983 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO);
6984
6985 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
6986
6987 size_t size = sizeof(*framebuffer);
6988 if (!imageless_create_info)
6989 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
6990 framebuffer = vk_alloc2(&device->vk.alloc, pAllocator, size, 8,
6991 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6992 if (framebuffer == NULL)
6993 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6994
6995 vk_object_base_init(&device->vk, &framebuffer->base,
6996 VK_OBJECT_TYPE_FRAMEBUFFER);
6997
6998 framebuffer->attachment_count = pCreateInfo->attachmentCount;
6999 framebuffer->width = pCreateInfo->width;
7000 framebuffer->height = pCreateInfo->height;
7001 framebuffer->layers = pCreateInfo->layers;
7002 if (imageless_create_info) {
7003 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
7004 const VkFramebufferAttachmentImageInfo *attachment =
7005 imageless_create_info->pAttachmentImageInfos + i;
7006 framebuffer->width = MIN2(framebuffer->width, attachment->width);
7007 framebuffer->height = MIN2(framebuffer->height, attachment->height);
7008 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
7009 }
7010 } else {
7011 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
7012 VkImageView _iview = pCreateInfo->pAttachments[i];
7013 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
7014 framebuffer->attachments[i] = iview;
7015 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
7016 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
7017 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
7018 }
7019 }
7020
7021 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
7022 return VK_SUCCESS;
7023 }
7024
7025 void radv_DestroyFramebuffer(
7026 VkDevice _device,
7027 VkFramebuffer _fb,
7028 const VkAllocationCallbacks* pAllocator)
7029 {
7030 RADV_FROM_HANDLE(radv_device, device, _device);
7031 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
7032
7033 if (!fb)
7034 return;
7035 vk_object_base_finish(&fb->base);
7036 vk_free2(&device->vk.alloc, pAllocator, fb);
7037 }
7038
7039 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
7040 {
7041 switch (address_mode) {
7042 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
7043 return V_008F30_SQ_TEX_WRAP;
7044 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
7045 return V_008F30_SQ_TEX_MIRROR;
7046 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
7047 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
7048 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
7049 return V_008F30_SQ_TEX_CLAMP_BORDER;
7050 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
7051 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
7052 default:
7053 unreachable("illegal tex wrap mode");
7054 break;
7055 }
7056 }
7057
7058 static unsigned
7059 radv_tex_compare(VkCompareOp op)
7060 {
7061 switch (op) {
7062 case VK_COMPARE_OP_NEVER:
7063 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
7064 case VK_COMPARE_OP_LESS:
7065 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
7066 case VK_COMPARE_OP_EQUAL:
7067 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
7068 case VK_COMPARE_OP_LESS_OR_EQUAL:
7069 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
7070 case VK_COMPARE_OP_GREATER:
7071 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
7072 case VK_COMPARE_OP_NOT_EQUAL:
7073 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
7074 case VK_COMPARE_OP_GREATER_OR_EQUAL:
7075 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
7076 case VK_COMPARE_OP_ALWAYS:
7077 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
7078 default:
7079 unreachable("illegal compare mode");
7080 break;
7081 }
7082 }
7083
7084 static unsigned
7085 radv_tex_filter(VkFilter filter, unsigned max_ansio)
7086 {
7087 switch (filter) {
7088 case VK_FILTER_NEAREST:
7089 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
7090 V_008F38_SQ_TEX_XY_FILTER_POINT);
7091 case VK_FILTER_LINEAR:
7092 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
7093 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
7094 case VK_FILTER_CUBIC_IMG:
7095 default:
7096 fprintf(stderr, "illegal texture filter");
7097 return 0;
7098 }
7099 }
7100
7101 static unsigned
7102 radv_tex_mipfilter(VkSamplerMipmapMode mode)
7103 {
7104 switch (mode) {
7105 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
7106 return V_008F38_SQ_TEX_Z_FILTER_POINT;
7107 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
7108 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
7109 default:
7110 return V_008F38_SQ_TEX_Z_FILTER_NONE;
7111 }
7112 }
7113
7114 static unsigned
7115 radv_tex_bordercolor(VkBorderColor bcolor)
7116 {
7117 switch (bcolor) {
7118 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
7119 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
7120 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
7121 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
7122 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
7123 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
7124 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
7125 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
7126 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
7127 case VK_BORDER_COLOR_FLOAT_CUSTOM_EXT:
7128 case VK_BORDER_COLOR_INT_CUSTOM_EXT:
7129 return V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
7130 default:
7131 break;
7132 }
7133 return 0;
7134 }
7135
7136 static unsigned
7137 radv_tex_aniso_filter(unsigned filter)
7138 {
7139 if (filter < 2)
7140 return 0;
7141 if (filter < 4)
7142 return 1;
7143 if (filter < 8)
7144 return 2;
7145 if (filter < 16)
7146 return 3;
7147 return 4;
7148 }
7149
7150 static unsigned
7151 radv_tex_filter_mode(VkSamplerReductionMode mode)
7152 {
7153 switch (mode) {
7154 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
7155 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
7156 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
7157 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
7158 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
7159 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
7160 default:
7161 break;
7162 }
7163 return 0;
7164 }
7165
7166 static uint32_t
7167 radv_get_max_anisotropy(struct radv_device *device,
7168 const VkSamplerCreateInfo *pCreateInfo)
7169 {
7170 if (device->force_aniso >= 0)
7171 return device->force_aniso;
7172
7173 if (pCreateInfo->anisotropyEnable &&
7174 pCreateInfo->maxAnisotropy > 1.0f)
7175 return (uint32_t)pCreateInfo->maxAnisotropy;
7176
7177 return 0;
7178 }
7179
7180 static inline int S_FIXED(float value, unsigned frac_bits)
7181 {
7182 return value * (1 << frac_bits);
7183 }
7184
7185 static uint32_t radv_register_border_color(struct radv_device *device,
7186 VkClearColorValue value)
7187 {
7188 uint32_t slot;
7189
7190 pthread_mutex_lock(&device->border_color_data.mutex);
7191
7192 for (slot = 0; slot < RADV_BORDER_COLOR_COUNT; slot++) {
7193 if (!device->border_color_data.used[slot]) {
7194 /* Copy to the GPU wrt endian-ness. */
7195 util_memcpy_cpu_to_le32(&device->border_color_data.colors_gpu_ptr[slot],
7196 &value,
7197 sizeof(VkClearColorValue));
7198
7199 device->border_color_data.used[slot] = true;
7200 break;
7201 }
7202 }
7203
7204 pthread_mutex_unlock(&device->border_color_data.mutex);
7205
7206 return slot;
7207 }
7208
7209 static void radv_unregister_border_color(struct radv_device *device,
7210 uint32_t slot)
7211 {
7212 pthread_mutex_lock(&device->border_color_data.mutex);
7213
7214 device->border_color_data.used[slot] = false;
7215
7216 pthread_mutex_unlock(&device->border_color_data.mutex);
7217 }
7218
7219 static void
7220 radv_init_sampler(struct radv_device *device,
7221 struct radv_sampler *sampler,
7222 const VkSamplerCreateInfo *pCreateInfo)
7223 {
7224 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
7225 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
7226 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
7227 device->physical_device->rad_info.chip_class == GFX9;
7228 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
7229 unsigned depth_compare_func = V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
7230 bool trunc_coord = pCreateInfo->minFilter == VK_FILTER_NEAREST && pCreateInfo->magFilter == VK_FILTER_NEAREST;
7231 bool uses_border_color = pCreateInfo->addressModeU == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER ||
7232 pCreateInfo->addressModeV == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER ||
7233 pCreateInfo->addressModeW == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER;
7234 VkBorderColor border_color = uses_border_color ? pCreateInfo->borderColor : VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK;
7235 uint32_t border_color_ptr;
7236
7237 const struct VkSamplerReductionModeCreateInfo *sampler_reduction =
7238 vk_find_struct_const(pCreateInfo->pNext,
7239 SAMPLER_REDUCTION_MODE_CREATE_INFO);
7240 if (sampler_reduction)
7241 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
7242
7243 if (pCreateInfo->compareEnable)
7244 depth_compare_func = radv_tex_compare(pCreateInfo->compareOp);
7245
7246 sampler->border_color_slot = RADV_BORDER_COLOR_COUNT;
7247
7248 if (border_color == VK_BORDER_COLOR_FLOAT_CUSTOM_EXT || border_color == VK_BORDER_COLOR_INT_CUSTOM_EXT) {
7249 const VkSamplerCustomBorderColorCreateInfoEXT *custom_border_color =
7250 vk_find_struct_const(pCreateInfo->pNext,
7251 SAMPLER_CUSTOM_BORDER_COLOR_CREATE_INFO_EXT);
7252
7253 assert(custom_border_color);
7254
7255 sampler->border_color_slot =
7256 radv_register_border_color(device, custom_border_color->customBorderColor);
7257
7258 /* Did we fail to find a slot? */
7259 if (sampler->border_color_slot == RADV_BORDER_COLOR_COUNT) {
7260 fprintf(stderr, "WARNING: no free border color slots, defaulting to TRANS_BLACK.\n");
7261 border_color = VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK;
7262 }
7263 }
7264
7265 /* If we don't have a custom color, set the ptr to 0 */
7266 border_color_ptr = sampler->border_color_slot != RADV_BORDER_COLOR_COUNT
7267 ? sampler->border_color_slot
7268 : 0;
7269
7270 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
7271 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
7272 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
7273 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
7274 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func) |
7275 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
7276 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
7277 S_008F30_ANISO_BIAS(max_aniso_ratio) |
7278 S_008F30_DISABLE_CUBE_WRAP(0) |
7279 S_008F30_COMPAT_MODE(compat_mode) |
7280 S_008F30_FILTER_MODE(filter_mode) |
7281 S_008F30_TRUNC_COORD(trunc_coord));
7282 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
7283 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
7284 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
7285 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
7286 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
7287 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
7288 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
7289 S_008F38_MIP_POINT_PRECLAMP(0));
7290 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(border_color_ptr) |
7291 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(border_color)));
7292
7293 if (device->physical_device->rad_info.chip_class >= GFX10) {
7294 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
7295 } else {
7296 sampler->state[2] |=
7297 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
7298 S_008F38_FILTER_PREC_FIX(1) |
7299 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
7300 }
7301 }
7302
7303 VkResult radv_CreateSampler(
7304 VkDevice _device,
7305 const VkSamplerCreateInfo* pCreateInfo,
7306 const VkAllocationCallbacks* pAllocator,
7307 VkSampler* pSampler)
7308 {
7309 RADV_FROM_HANDLE(radv_device, device, _device);
7310 struct radv_sampler *sampler;
7311
7312 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
7313 vk_find_struct_const(pCreateInfo->pNext,
7314 SAMPLER_YCBCR_CONVERSION_INFO);
7315
7316 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
7317
7318 sampler = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*sampler), 8,
7319 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
7320 if (!sampler)
7321 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7322
7323 vk_object_base_init(&device->vk, &sampler->base,
7324 VK_OBJECT_TYPE_SAMPLER);
7325
7326 radv_init_sampler(device, sampler, pCreateInfo);
7327
7328 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
7329 *pSampler = radv_sampler_to_handle(sampler);
7330
7331 return VK_SUCCESS;
7332 }
7333
7334 void radv_DestroySampler(
7335 VkDevice _device,
7336 VkSampler _sampler,
7337 const VkAllocationCallbacks* pAllocator)
7338 {
7339 RADV_FROM_HANDLE(radv_device, device, _device);
7340 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
7341
7342 if (!sampler)
7343 return;
7344
7345 if (sampler->border_color_slot != RADV_BORDER_COLOR_COUNT)
7346 radv_unregister_border_color(device, sampler->border_color_slot);
7347
7348 vk_object_base_finish(&sampler->base);
7349 vk_free2(&device->vk.alloc, pAllocator, sampler);
7350 }
7351
7352 /* vk_icd.h does not declare this function, so we declare it here to
7353 * suppress Wmissing-prototypes.
7354 */
7355 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7356 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
7357
7358 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7359 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
7360 {
7361 /* For the full details on loader interface versioning, see
7362 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
7363 * What follows is a condensed summary, to help you navigate the large and
7364 * confusing official doc.
7365 *
7366 * - Loader interface v0 is incompatible with later versions. We don't
7367 * support it.
7368 *
7369 * - In loader interface v1:
7370 * - The first ICD entrypoint called by the loader is
7371 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
7372 * entrypoint.
7373 * - The ICD must statically expose no other Vulkan symbol unless it is
7374 * linked with -Bsymbolic.
7375 * - Each dispatchable Vulkan handle created by the ICD must be
7376 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7377 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7378 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7379 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7380 * such loader-managed surfaces.
7381 *
7382 * - Loader interface v2 differs from v1 in:
7383 * - The first ICD entrypoint called by the loader is
7384 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7385 * statically expose this entrypoint.
7386 *
7387 * - Loader interface v3 differs from v2 in:
7388 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7389 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7390 * because the loader no longer does so.
7391 */
7392 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
7393 return VK_SUCCESS;
7394 }
7395
7396 VkResult radv_GetMemoryFdKHR(VkDevice _device,
7397 const VkMemoryGetFdInfoKHR *pGetFdInfo,
7398 int *pFD)
7399 {
7400 RADV_FROM_HANDLE(radv_device, device, _device);
7401 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
7402
7403 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
7404
7405 /* At the moment, we support only the below handle types. */
7406 assert(pGetFdInfo->handleType ==
7407 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
7408 pGetFdInfo->handleType ==
7409 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
7410
7411 bool ret = radv_get_memory_fd(device, memory, pFD);
7412 if (ret == false)
7413 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
7414 return VK_SUCCESS;
7415 }
7416
7417 static uint32_t radv_compute_valid_memory_types_attempt(struct radv_physical_device *dev,
7418 enum radeon_bo_domain domains,
7419 enum radeon_bo_flag flags,
7420 enum radeon_bo_flag ignore_flags)
7421 {
7422 /* Don't count GTT/CPU as relevant:
7423 *
7424 * - We're not fully consistent between the two.
7425 * - Sometimes VRAM gets VRAM|GTT.
7426 */
7427 const enum radeon_bo_domain relevant_domains = RADEON_DOMAIN_VRAM |
7428 RADEON_DOMAIN_GDS |
7429 RADEON_DOMAIN_OA;
7430 uint32_t bits = 0;
7431 for (unsigned i = 0; i < dev->memory_properties.memoryTypeCount; ++i) {
7432 if ((domains & relevant_domains) != (dev->memory_domains[i] & relevant_domains))
7433 continue;
7434
7435 if ((flags & ~ignore_flags) != (dev->memory_flags[i] & ~ignore_flags))
7436 continue;
7437
7438 bits |= 1u << i;
7439 }
7440
7441 return bits;
7442 }
7443
7444 static uint32_t radv_compute_valid_memory_types(struct radv_physical_device *dev,
7445 enum radeon_bo_domain domains,
7446 enum radeon_bo_flag flags)
7447 {
7448 enum radeon_bo_flag ignore_flags = ~(RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_GTT_WC);
7449 uint32_t bits = radv_compute_valid_memory_types_attempt(dev, domains, flags, ignore_flags);
7450
7451 if (!bits) {
7452 ignore_flags |= RADEON_FLAG_NO_CPU_ACCESS;
7453 bits = radv_compute_valid_memory_types_attempt(dev, domains, flags, ignore_flags);
7454 }
7455
7456 return bits;
7457 }
7458 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
7459 VkExternalMemoryHandleTypeFlagBits handleType,
7460 int fd,
7461 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
7462 {
7463 RADV_FROM_HANDLE(radv_device, device, _device);
7464
7465 switch (handleType) {
7466 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT: {
7467 enum radeon_bo_domain domains;
7468 enum radeon_bo_flag flags;
7469 if (!device->ws->buffer_get_flags_from_fd(device->ws, fd, &domains, &flags))
7470 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7471
7472 pMemoryFdProperties->memoryTypeBits = radv_compute_valid_memory_types(device->physical_device, domains, flags);
7473 return VK_SUCCESS;
7474 }
7475 default:
7476 /* The valid usage section for this function says:
7477 *
7478 * "handleType must not be one of the handle types defined as
7479 * opaque."
7480 *
7481 * So opaque handle types fall into the default "unsupported" case.
7482 */
7483 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7484 }
7485 }
7486
7487 static VkResult radv_import_opaque_fd(struct radv_device *device,
7488 int fd,
7489 uint32_t *syncobj)
7490 {
7491 uint32_t syncobj_handle = 0;
7492 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
7493 if (ret != 0)
7494 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7495
7496 if (*syncobj)
7497 device->ws->destroy_syncobj(device->ws, *syncobj);
7498
7499 *syncobj = syncobj_handle;
7500 close(fd);
7501
7502 return VK_SUCCESS;
7503 }
7504
7505 static VkResult radv_import_sync_fd(struct radv_device *device,
7506 int fd,
7507 uint32_t *syncobj)
7508 {
7509 /* If we create a syncobj we do it locally so that if we have an error, we don't
7510 * leave a syncobj in an undetermined state in the fence. */
7511 uint32_t syncobj_handle = *syncobj;
7512 if (!syncobj_handle) {
7513 bool create_signaled = fd == -1 ? true : false;
7514
7515 int ret = device->ws->create_syncobj(device->ws, create_signaled,
7516 &syncobj_handle);
7517 if (ret) {
7518 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7519 }
7520 } else {
7521 if (fd == -1)
7522 device->ws->signal_syncobj(device->ws, syncobj_handle, 0);
7523 }
7524
7525 if (fd != -1) {
7526 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
7527 if (ret)
7528 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7529 close(fd);
7530 }
7531
7532 *syncobj = syncobj_handle;
7533
7534 return VK_SUCCESS;
7535 }
7536
7537 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
7538 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
7539 {
7540 RADV_FROM_HANDLE(radv_device, device, _device);
7541 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
7542 VkResult result;
7543 struct radv_semaphore_part *dst = NULL;
7544 bool timeline = sem->permanent.kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ;
7545
7546 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
7547 assert(!timeline);
7548 dst = &sem->temporary;
7549 } else {
7550 dst = &sem->permanent;
7551 }
7552
7553 uint32_t syncobj = (dst->kind == RADV_SEMAPHORE_SYNCOBJ ||
7554 dst->kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ) ? dst->syncobj : 0;
7555
7556 switch(pImportSemaphoreFdInfo->handleType) {
7557 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7558 result = radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7559 break;
7560 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7561 assert(!timeline);
7562 result = radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7563 break;
7564 default:
7565 unreachable("Unhandled semaphore handle type");
7566 }
7567
7568 if (result == VK_SUCCESS) {
7569 dst->syncobj = syncobj;
7570 dst->kind = RADV_SEMAPHORE_SYNCOBJ;
7571 if (timeline) {
7572 dst->kind = RADV_SEMAPHORE_TIMELINE_SYNCOBJ;
7573 dst->timeline_syncobj.max_point = 0;
7574 }
7575 }
7576
7577 return result;
7578 }
7579
7580 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
7581 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
7582 int *pFd)
7583 {
7584 RADV_FROM_HANDLE(radv_device, device, _device);
7585 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
7586 int ret;
7587 uint32_t syncobj_handle;
7588
7589 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7590 assert(sem->temporary.kind == RADV_SEMAPHORE_SYNCOBJ ||
7591 sem->temporary.kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ);
7592 syncobj_handle = sem->temporary.syncobj;
7593 } else {
7594 assert(sem->permanent.kind == RADV_SEMAPHORE_SYNCOBJ ||
7595 sem->permanent.kind == RADV_SEMAPHORE_TIMELINE_SYNCOBJ);
7596 syncobj_handle = sem->permanent.syncobj;
7597 }
7598
7599 switch(pGetFdInfo->handleType) {
7600 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7601 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
7602 if (ret)
7603 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7604 break;
7605 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7606 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
7607 if (ret)
7608 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7609
7610 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7611 radv_destroy_semaphore_part(device, &sem->temporary);
7612 } else {
7613 device->ws->reset_syncobj(device->ws, syncobj_handle);
7614 }
7615 break;
7616 default:
7617 unreachable("Unhandled semaphore handle type");
7618 }
7619
7620 return VK_SUCCESS;
7621 }
7622
7623 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7624 VkPhysicalDevice physicalDevice,
7625 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
7626 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
7627 {
7628 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7629 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pExternalSemaphoreInfo->pNext, NULL);
7630
7631 if (type == VK_SEMAPHORE_TYPE_TIMELINE && pdevice->rad_info.has_timeline_syncobj &&
7632 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
7633 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7634 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7635 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7636 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7637 } else if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
7638 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7639 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7640 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7641
7642 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7643 } else if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7644 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7645 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
7646 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7647 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7648 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7649 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7650 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
7651 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7652 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7653 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7654 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7655 } else {
7656 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7657 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7658 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7659 }
7660 }
7661
7662 VkResult radv_ImportFenceFdKHR(VkDevice _device,
7663 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
7664 {
7665 RADV_FROM_HANDLE(radv_device, device, _device);
7666 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
7667 struct radv_fence_part *dst = NULL;
7668 VkResult result;
7669
7670 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
7671 dst = &fence->temporary;
7672 } else {
7673 dst = &fence->permanent;
7674 }
7675
7676 uint32_t syncobj = dst->kind == RADV_FENCE_SYNCOBJ ? dst->syncobj : 0;
7677
7678 switch(pImportFenceFdInfo->handleType) {
7679 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7680 result = radv_import_opaque_fd(device, pImportFenceFdInfo->fd, &syncobj);
7681 break;
7682 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7683 result = radv_import_sync_fd(device, pImportFenceFdInfo->fd, &syncobj);
7684 break;
7685 default:
7686 unreachable("Unhandled fence handle type");
7687 }
7688
7689 if (result == VK_SUCCESS) {
7690 dst->syncobj = syncobj;
7691 dst->kind = RADV_FENCE_SYNCOBJ;
7692 }
7693
7694 return result;
7695 }
7696
7697 VkResult radv_GetFenceFdKHR(VkDevice _device,
7698 const VkFenceGetFdInfoKHR *pGetFdInfo,
7699 int *pFd)
7700 {
7701 RADV_FROM_HANDLE(radv_device, device, _device);
7702 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
7703 int ret;
7704
7705 struct radv_fence_part *part =
7706 fence->temporary.kind != RADV_FENCE_NONE ?
7707 &fence->temporary : &fence->permanent;
7708
7709 switch(pGetFdInfo->handleType) {
7710 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7711 ret = device->ws->export_syncobj(device->ws, part->syncobj, pFd);
7712 if (ret)
7713 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7714 break;
7715 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7716 ret = device->ws->export_syncobj_to_sync_file(device->ws,
7717 part->syncobj, pFd);
7718 if (ret)
7719 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7720
7721 if (part == &fence->temporary) {
7722 radv_destroy_fence_part(device, part);
7723 } else {
7724 device->ws->reset_syncobj(device->ws, part->syncobj);
7725 }
7726 break;
7727 default:
7728 unreachable("Unhandled fence handle type");
7729 }
7730
7731 return VK_SUCCESS;
7732 }
7733
7734 void radv_GetPhysicalDeviceExternalFenceProperties(
7735 VkPhysicalDevice physicalDevice,
7736 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
7737 VkExternalFenceProperties *pExternalFenceProperties)
7738 {
7739 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7740
7741 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7742 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7743 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
7744 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7745 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7746 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
7747 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7748 } else {
7749 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
7750 pExternalFenceProperties->compatibleHandleTypes = 0;
7751 pExternalFenceProperties->externalFenceFeatures = 0;
7752 }
7753 }
7754
7755 VkResult
7756 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
7757 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
7758 const VkAllocationCallbacks* pAllocator,
7759 VkDebugReportCallbackEXT* pCallback)
7760 {
7761 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7762 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
7763 pCreateInfo, pAllocator, &instance->alloc,
7764 pCallback);
7765 }
7766
7767 void
7768 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
7769 VkDebugReportCallbackEXT _callback,
7770 const VkAllocationCallbacks* pAllocator)
7771 {
7772 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7773 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
7774 _callback, pAllocator, &instance->alloc);
7775 }
7776
7777 void
7778 radv_DebugReportMessageEXT(VkInstance _instance,
7779 VkDebugReportFlagsEXT flags,
7780 VkDebugReportObjectTypeEXT objectType,
7781 uint64_t object,
7782 size_t location,
7783 int32_t messageCode,
7784 const char* pLayerPrefix,
7785 const char* pMessage)
7786 {
7787 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7788 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
7789 object, location, messageCode, pLayerPrefix, pMessage);
7790 }
7791
7792 void
7793 radv_GetDeviceGroupPeerMemoryFeatures(
7794 VkDevice device,
7795 uint32_t heapIndex,
7796 uint32_t localDeviceIndex,
7797 uint32_t remoteDeviceIndex,
7798 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
7799 {
7800 assert(localDeviceIndex == remoteDeviceIndex);
7801
7802 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
7803 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
7804 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
7805 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
7806 }
7807
7808 static const VkTimeDomainEXT radv_time_domains[] = {
7809 VK_TIME_DOMAIN_DEVICE_EXT,
7810 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
7811 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
7812 };
7813
7814 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7815 VkPhysicalDevice physicalDevice,
7816 uint32_t *pTimeDomainCount,
7817 VkTimeDomainEXT *pTimeDomains)
7818 {
7819 int d;
7820 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
7821
7822 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
7823 vk_outarray_append(&out, i) {
7824 *i = radv_time_domains[d];
7825 }
7826 }
7827
7828 return vk_outarray_status(&out);
7829 }
7830
7831 static uint64_t
7832 radv_clock_gettime(clockid_t clock_id)
7833 {
7834 struct timespec current;
7835 int ret;
7836
7837 ret = clock_gettime(clock_id, &current);
7838 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
7839 ret = clock_gettime(CLOCK_MONOTONIC, &current);
7840 if (ret < 0)
7841 return 0;
7842
7843 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
7844 }
7845
7846 VkResult radv_GetCalibratedTimestampsEXT(
7847 VkDevice _device,
7848 uint32_t timestampCount,
7849 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
7850 uint64_t *pTimestamps,
7851 uint64_t *pMaxDeviation)
7852 {
7853 RADV_FROM_HANDLE(radv_device, device, _device);
7854 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
7855 int d;
7856 uint64_t begin, end;
7857 uint64_t max_clock_period = 0;
7858
7859 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7860
7861 for (d = 0; d < timestampCount; d++) {
7862 switch (pTimestampInfos[d].timeDomain) {
7863 case VK_TIME_DOMAIN_DEVICE_EXT:
7864 pTimestamps[d] = device->ws->query_value(device->ws,
7865 RADEON_TIMESTAMP);
7866 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
7867 max_clock_period = MAX2(max_clock_period, device_period);
7868 break;
7869 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
7870 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
7871 max_clock_period = MAX2(max_clock_period, 1);
7872 break;
7873
7874 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
7875 pTimestamps[d] = begin;
7876 break;
7877 default:
7878 pTimestamps[d] = 0;
7879 break;
7880 }
7881 }
7882
7883 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7884
7885 /*
7886 * The maximum deviation is the sum of the interval over which we
7887 * perform the sampling and the maximum period of any sampled
7888 * clock. That's because the maximum skew between any two sampled
7889 * clock edges is when the sampled clock with the largest period is
7890 * sampled at the end of that period but right at the beginning of the
7891 * sampling interval and some other clock is sampled right at the
7892 * begining of its sampling period and right at the end of the
7893 * sampling interval. Let's assume the GPU has the longest clock
7894 * period and that the application is sampling GPU and monotonic:
7895 *
7896 * s e
7897 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
7898 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7899 *
7900 * g
7901 * 0 1 2 3
7902 * GPU -----_____-----_____-----_____-----_____
7903 *
7904 * m
7905 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
7906 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7907 *
7908 * Interval <----------------->
7909 * Deviation <-------------------------->
7910 *
7911 * s = read(raw) 2
7912 * g = read(GPU) 1
7913 * m = read(monotonic) 2
7914 * e = read(raw) b
7915 *
7916 * We round the sample interval up by one tick to cover sampling error
7917 * in the interval clock
7918 */
7919
7920 uint64_t sample_interval = end - begin + 1;
7921
7922 *pMaxDeviation = sample_interval + max_clock_period;
7923
7924 return VK_SUCCESS;
7925 }
7926
7927 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
7928 VkPhysicalDevice physicalDevice,
7929 VkSampleCountFlagBits samples,
7930 VkMultisamplePropertiesEXT* pMultisampleProperties)
7931 {
7932 if (samples & (VK_SAMPLE_COUNT_2_BIT |
7933 VK_SAMPLE_COUNT_4_BIT |
7934 VK_SAMPLE_COUNT_8_BIT)) {
7935 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
7936 } else {
7937 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
7938 }
7939 }
7940
7941 VkResult radv_CreatePrivateDataSlotEXT(
7942 VkDevice _device,
7943 const VkPrivateDataSlotCreateInfoEXT* pCreateInfo,
7944 const VkAllocationCallbacks* pAllocator,
7945 VkPrivateDataSlotEXT* pPrivateDataSlot)
7946 {
7947 RADV_FROM_HANDLE(radv_device, device, _device);
7948 return vk_private_data_slot_create(&device->vk, pCreateInfo, pAllocator,
7949 pPrivateDataSlot);
7950 }
7951
7952 void radv_DestroyPrivateDataSlotEXT(
7953 VkDevice _device,
7954 VkPrivateDataSlotEXT privateDataSlot,
7955 const VkAllocationCallbacks* pAllocator)
7956 {
7957 RADV_FROM_HANDLE(radv_device, device, _device);
7958 vk_private_data_slot_destroy(&device->vk, privateDataSlot, pAllocator);
7959 }
7960
7961 VkResult radv_SetPrivateDataEXT(
7962 VkDevice _device,
7963 VkObjectType objectType,
7964 uint64_t objectHandle,
7965 VkPrivateDataSlotEXT privateDataSlot,
7966 uint64_t data)
7967 {
7968 RADV_FROM_HANDLE(radv_device, device, _device);
7969 return vk_object_base_set_private_data(&device->vk, objectType,
7970 objectHandle, privateDataSlot,
7971 data);
7972 }
7973
7974 void radv_GetPrivateDataEXT(
7975 VkDevice _device,
7976 VkObjectType objectType,
7977 uint64_t objectHandle,
7978 VkPrivateDataSlotEXT privateDataSlot,
7979 uint64_t* pData)
7980 {
7981 RADV_FROM_HANDLE(radv_device, device, _device);
7982 vk_object_base_get_private_data(&device->vk, objectType, objectHandle,
7983 privateDataSlot, pData);
7984 }