2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
32 #include "radv_private.h"
34 #include "util/disk_cache.h"
35 #include "util/strtod.h"
36 #include "util/vk_util.h"
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
46 #include "util/debug.h"
49 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
51 uint32_t mesa_timestamp
, llvm_timestamp
;
53 memset(uuid
, 0, VK_UUID_SIZE
);
54 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid
, &mesa_timestamp
) ||
55 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo
, &llvm_timestamp
))
58 memcpy(uuid
, &mesa_timestamp
, 4);
59 memcpy((char*)uuid
+ 4, &llvm_timestamp
, 4);
60 memcpy((char*)uuid
+ 8, &f
, 2);
61 snprintf((char*)uuid
+ 10, VK_UUID_SIZE
- 10, "radv");
66 radv_get_device_uuid(drmDevicePtr device
, void *uuid
) {
67 memset(uuid
, 0, VK_UUID_SIZE
);
68 memcpy((char*)uuid
+ 0, &device
->businfo
.pci
->domain
, 2);
69 memcpy((char*)uuid
+ 2, &device
->businfo
.pci
->bus
, 1);
70 memcpy((char*)uuid
+ 3, &device
->businfo
.pci
->dev
, 1);
71 memcpy((char*)uuid
+ 4, &device
->businfo
.pci
->func
, 1);
74 static const VkExtensionProperties instance_extensions
[] = {
76 .extensionName
= VK_KHR_SURFACE_EXTENSION_NAME
,
79 #ifdef VK_USE_PLATFORM_XCB_KHR
81 .extensionName
= VK_KHR_XCB_SURFACE_EXTENSION_NAME
,
85 #ifdef VK_USE_PLATFORM_XLIB_KHR
87 .extensionName
= VK_KHR_XLIB_SURFACE_EXTENSION_NAME
,
91 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
93 .extensionName
= VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME
,
98 .extensionName
= VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME
,
102 .extensionName
= VK_KHX_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME
,
107 static const VkExtensionProperties common_device_extensions
[] = {
109 .extensionName
= VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME
,
113 .extensionName
= VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME
,
117 .extensionName
= VK_KHR_MAINTENANCE1_EXTENSION_NAME
,
121 .extensionName
= VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME
,
125 .extensionName
= VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME
,
129 .extensionName
= VK_KHR_SWAPCHAIN_EXTENSION_NAME
,
133 .extensionName
= VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME
,
137 .extensionName
= VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME
,
141 .extensionName
= VK_NV_DEDICATED_ALLOCATION_EXTENSION_NAME
,
145 .extensionName
= VK_KHX_EXTERNAL_MEMORY_EXTENSION_NAME
,
149 .extensionName
= VK_KHX_EXTERNAL_MEMORY_FD_EXTENSION_NAME
,
155 radv_extensions_register(struct radv_instance
*instance
,
156 struct radv_extensions
*extensions
,
157 const VkExtensionProperties
*new_ext
,
161 VkExtensionProperties
*new_ptr
;
163 assert(new_ext
&& num_ext
> 0);
166 return VK_ERROR_INITIALIZATION_FAILED
;
168 new_size
= (extensions
->num_ext
+ num_ext
) * sizeof(VkExtensionProperties
);
169 new_ptr
= vk_realloc(&instance
->alloc
, extensions
->ext_array
,
170 new_size
, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
172 /* Old array continues to be valid, update nothing */
174 return VK_ERROR_OUT_OF_HOST_MEMORY
;
176 memcpy(&new_ptr
[extensions
->num_ext
], new_ext
,
177 num_ext
* sizeof(VkExtensionProperties
));
178 extensions
->ext_array
= new_ptr
;
179 extensions
->num_ext
+= num_ext
;
185 radv_extensions_finish(struct radv_instance
*instance
,
186 struct radv_extensions
*extensions
)
191 radv_loge("Attemted to free invalid extension struct\n");
193 if (extensions
->ext_array
)
194 vk_free(&instance
->alloc
, extensions
->ext_array
);
198 is_extension_enabled(const VkExtensionProperties
*extensions
,
202 assert(extensions
&& name
);
204 for (uint32_t i
= 0; i
< num_ext
; i
++) {
205 if (strcmp(name
, extensions
[i
].extensionName
) == 0)
213 get_chip_name(enum radeon_family family
)
216 case CHIP_TAHITI
: return "AMD RADV TAHITI";
217 case CHIP_PITCAIRN
: return "AMD RADV PITCAIRN";
218 case CHIP_VERDE
: return "AMD RADV CAPE VERDE";
219 case CHIP_OLAND
: return "AMD RADV OLAND";
220 case CHIP_HAINAN
: return "AMD RADV HAINAN";
221 case CHIP_BONAIRE
: return "AMD RADV BONAIRE";
222 case CHIP_KAVERI
: return "AMD RADV KAVERI";
223 case CHIP_KABINI
: return "AMD RADV KABINI";
224 case CHIP_HAWAII
: return "AMD RADV HAWAII";
225 case CHIP_MULLINS
: return "AMD RADV MULLINS";
226 case CHIP_TONGA
: return "AMD RADV TONGA";
227 case CHIP_ICELAND
: return "AMD RADV ICELAND";
228 case CHIP_CARRIZO
: return "AMD RADV CARRIZO";
229 case CHIP_FIJI
: return "AMD RADV FIJI";
230 case CHIP_POLARIS10
: return "AMD RADV POLARIS10";
231 case CHIP_POLARIS11
: return "AMD RADV POLARIS11";
232 case CHIP_POLARIS12
: return "AMD RADV POLARIS12";
233 case CHIP_STONEY
: return "AMD RADV STONEY";
234 case CHIP_VEGA10
: return "AMD RADV VEGA";
235 case CHIP_RAVEN
: return "AMD RADV RAVEN";
236 default: return "AMD RADV unknown";
241 radv_physical_device_init(struct radv_physical_device
*device
,
242 struct radv_instance
*instance
,
243 drmDevicePtr drm_device
)
245 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
247 drmVersionPtr version
;
250 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
252 return VK_ERROR_INCOMPATIBLE_DRIVER
;
254 version
= drmGetVersion(fd
);
257 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER
,
258 "failed to get version %s: %m", path
);
261 if (strcmp(version
->name
, "amdgpu")) {
262 drmFreeVersion(version
);
264 return VK_ERROR_INCOMPATIBLE_DRIVER
;
266 drmFreeVersion(version
);
268 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
269 device
->instance
= instance
;
270 assert(strlen(path
) < ARRAY_SIZE(device
->path
));
271 strncpy(device
->path
, path
, ARRAY_SIZE(device
->path
));
273 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
);
275 result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
279 device
->local_fd
= fd
;
280 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
281 result
= radv_init_wsi(device
);
282 if (result
!= VK_SUCCESS
) {
283 device
->ws
->destroy(device
->ws
);
287 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->uuid
)) {
288 radv_finish_wsi(device
);
289 device
->ws
->destroy(device
->ws
);
290 result
= vk_errorf(VK_ERROR_INITIALIZATION_FAILED
,
291 "cannot generate UUID");
295 result
= radv_extensions_register(instance
,
297 common_device_extensions
,
298 ARRAY_SIZE(common_device_extensions
));
299 if (result
!= VK_SUCCESS
)
302 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
303 device
->name
= get_chip_name(device
->rad_info
.family
);
305 radv_get_device_uuid(drm_device
, device
->device_uuid
);
315 radv_physical_device_finish(struct radv_physical_device
*device
)
317 radv_extensions_finish(device
->instance
, &device
->extensions
);
318 radv_finish_wsi(device
);
319 device
->ws
->destroy(device
->ws
);
320 close(device
->local_fd
);
324 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
325 VkSystemAllocationScope allocationScope
)
331 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
332 size_t align
, VkSystemAllocationScope allocationScope
)
334 return realloc(pOriginal
, size
);
338 default_free_func(void *pUserData
, void *pMemory
)
343 static const VkAllocationCallbacks default_alloc
= {
345 .pfnAllocation
= default_alloc_func
,
346 .pfnReallocation
= default_realloc_func
,
347 .pfnFree
= default_free_func
,
350 static const struct debug_control radv_debug_options
[] = {
351 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
352 {"nodcc", RADV_DEBUG_NO_DCC
},
353 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
354 {"nocache", RADV_DEBUG_NO_CACHE
},
355 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
356 {"nohiz", RADV_DEBUG_NO_HIZ
},
357 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
358 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
359 {"allbos", RADV_DEBUG_ALL_BOS
},
360 {"noibs", RADV_DEBUG_NO_IBS
},
364 VkResult
radv_CreateInstance(
365 const VkInstanceCreateInfo
* pCreateInfo
,
366 const VkAllocationCallbacks
* pAllocator
,
367 VkInstance
* pInstance
)
369 struct radv_instance
*instance
;
371 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
373 uint32_t client_version
;
374 if (pCreateInfo
->pApplicationInfo
&&
375 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
376 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
378 client_version
= VK_MAKE_VERSION(1, 0, 0);
381 if (VK_MAKE_VERSION(1, 0, 0) > client_version
||
382 client_version
> VK_MAKE_VERSION(1, 0, 0xfff)) {
383 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER
,
384 "Client requested version %d.%d.%d",
385 VK_VERSION_MAJOR(client_version
),
386 VK_VERSION_MINOR(client_version
),
387 VK_VERSION_PATCH(client_version
));
390 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
391 if (!is_extension_enabled(instance_extensions
,
392 ARRAY_SIZE(instance_extensions
),
393 pCreateInfo
->ppEnabledExtensionNames
[i
]))
394 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT
);
397 instance
= vk_alloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
398 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
400 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
402 memset(instance
, 0, sizeof(*instance
));
404 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
407 instance
->alloc
= *pAllocator
;
409 instance
->alloc
= default_alloc
;
411 instance
->apiVersion
= client_version
;
412 instance
->physicalDeviceCount
= -1;
416 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
418 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
421 *pInstance
= radv_instance_to_handle(instance
);
426 void radv_DestroyInstance(
427 VkInstance _instance
,
428 const VkAllocationCallbacks
* pAllocator
)
430 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
435 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
436 radv_physical_device_finish(instance
->physicalDevices
+ i
);
439 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
443 vk_free(&instance
->alloc
, instance
);
447 radv_enumerate_devices(struct radv_instance
*instance
)
449 /* TODO: Check for more devices ? */
450 drmDevicePtr devices
[8];
451 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
454 instance
->physicalDeviceCount
= 0;
456 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
458 return VK_ERROR_INCOMPATIBLE_DRIVER
;
460 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
461 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
462 devices
[i
]->bustype
== DRM_BUS_PCI
&&
463 devices
[i
]->deviceinfo
.pci
->vendor_id
== 0x1002) {
465 result
= radv_physical_device_init(instance
->physicalDevices
+
466 instance
->physicalDeviceCount
,
469 if (result
== VK_SUCCESS
)
470 ++instance
->physicalDeviceCount
;
471 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
475 drmFreeDevices(devices
, max_devices
);
480 VkResult
radv_EnumeratePhysicalDevices(
481 VkInstance _instance
,
482 uint32_t* pPhysicalDeviceCount
,
483 VkPhysicalDevice
* pPhysicalDevices
)
485 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
488 if (instance
->physicalDeviceCount
< 0) {
489 result
= radv_enumerate_devices(instance
);
490 if (result
!= VK_SUCCESS
&&
491 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
495 if (!pPhysicalDevices
) {
496 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
498 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
499 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
500 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
503 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
507 void radv_GetPhysicalDeviceFeatures(
508 VkPhysicalDevice physicalDevice
,
509 VkPhysicalDeviceFeatures
* pFeatures
)
511 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
513 memset(pFeatures
, 0, sizeof(*pFeatures
));
515 *pFeatures
= (VkPhysicalDeviceFeatures
) {
516 .robustBufferAccess
= true,
517 .fullDrawIndexUint32
= true,
518 .imageCubeArray
= true,
519 .independentBlend
= true,
520 .geometryShader
= true,
521 .tessellationShader
= true,
522 .sampleRateShading
= false,
523 .dualSrcBlend
= true,
525 .multiDrawIndirect
= true,
526 .drawIndirectFirstInstance
= true,
528 .depthBiasClamp
= true,
529 .fillModeNonSolid
= true,
534 .multiViewport
= true,
535 .samplerAnisotropy
= true,
536 .textureCompressionETC2
= false,
537 .textureCompressionASTC_LDR
= false,
538 .textureCompressionBC
= true,
539 .occlusionQueryPrecise
= true,
540 .pipelineStatisticsQuery
= true,
541 .vertexPipelineStoresAndAtomics
= true,
542 .fragmentStoresAndAtomics
= true,
543 .shaderTessellationAndGeometryPointSize
= true,
544 .shaderImageGatherExtended
= true,
545 .shaderStorageImageExtendedFormats
= true,
546 .shaderStorageImageMultisample
= false,
547 .shaderUniformBufferArrayDynamicIndexing
= true,
548 .shaderSampledImageArrayDynamicIndexing
= true,
549 .shaderStorageBufferArrayDynamicIndexing
= true,
550 .shaderStorageImageArrayDynamicIndexing
= true,
551 .shaderStorageImageReadWithoutFormat
= true,
552 .shaderStorageImageWriteWithoutFormat
= true,
553 .shaderClipDistance
= true,
554 .shaderCullDistance
= true,
555 .shaderFloat64
= true,
556 .shaderInt64
= false,
557 .shaderInt16
= false,
558 .sparseBinding
= true,
559 .variableMultisampleRate
= true,
560 .inheritedQueries
= true,
564 void radv_GetPhysicalDeviceFeatures2KHR(
565 VkPhysicalDevice physicalDevice
,
566 VkPhysicalDeviceFeatures2KHR
*pFeatures
)
568 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
571 static uint32_t radv_get_driver_version()
573 const char *minor_string
= strchr(VERSION
, '.');
574 const char *patch_string
= minor_string
? strchr(minor_string
+ 1, ','): NULL
;
575 int major
= atoi(VERSION
);
576 int minor
= minor_string
? atoi(minor_string
+ 1) : 0;
577 int patch
= patch_string
? atoi(patch_string
+ 1) : 0;
578 if (strstr(VERSION
, "devel")) {
589 uint32_t version
= VK_MAKE_VERSION(major
, minor
, patch
);
593 void radv_GetPhysicalDeviceProperties(
594 VkPhysicalDevice physicalDevice
,
595 VkPhysicalDeviceProperties
* pProperties
)
597 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
598 VkSampleCountFlags sample_counts
= 0xf;
600 /* make sure that the entire descriptor set is addressable with a signed
601 * 32-bit int. So the sum of all limits scaled by descriptor size has to
602 * be at most 2 GiB. the combined image & samples object count as one of
603 * both. This limit is for the pipeline layout, not for the set layout, but
604 * there is no set limit, so we just set a pipeline limit. I don't think
605 * any app is going to hit this soon. */
606 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
) /
607 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
608 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
609 32 /* sampler, largest when combined with image */ +
610 64 /* sampled image */ +
611 64 /* storage image */);
613 VkPhysicalDeviceLimits limits
= {
614 .maxImageDimension1D
= (1 << 14),
615 .maxImageDimension2D
= (1 << 14),
616 .maxImageDimension3D
= (1 << 11),
617 .maxImageDimensionCube
= (1 << 14),
618 .maxImageArrayLayers
= (1 << 11),
619 .maxTexelBufferElements
= 128 * 1024 * 1024,
620 .maxUniformBufferRange
= UINT32_MAX
,
621 .maxStorageBufferRange
= UINT32_MAX
,
622 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
623 .maxMemoryAllocationCount
= UINT32_MAX
,
624 .maxSamplerAllocationCount
= 64 * 1024,
625 .bufferImageGranularity
= 64, /* A cache line */
626 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
627 .maxBoundDescriptorSets
= MAX_SETS
,
628 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
629 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
630 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
631 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
632 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
633 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
634 .maxPerStageResources
= max_descriptor_set_size
,
635 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
636 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
637 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_BUFFERS
/ 2,
638 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
639 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_BUFFERS
/ 2,
640 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
641 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
642 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
643 .maxVertexInputAttributes
= 32,
644 .maxVertexInputBindings
= 32,
645 .maxVertexInputAttributeOffset
= 2047,
646 .maxVertexInputBindingStride
= 2048,
647 .maxVertexOutputComponents
= 128,
648 .maxTessellationGenerationLevel
= 64,
649 .maxTessellationPatchSize
= 32,
650 .maxTessellationControlPerVertexInputComponents
= 128,
651 .maxTessellationControlPerVertexOutputComponents
= 128,
652 .maxTessellationControlPerPatchOutputComponents
= 120,
653 .maxTessellationControlTotalOutputComponents
= 4096,
654 .maxTessellationEvaluationInputComponents
= 128,
655 .maxTessellationEvaluationOutputComponents
= 128,
656 .maxGeometryShaderInvocations
= 127,
657 .maxGeometryInputComponents
= 64,
658 .maxGeometryOutputComponents
= 128,
659 .maxGeometryOutputVertices
= 256,
660 .maxGeometryTotalOutputComponents
= 1024,
661 .maxFragmentInputComponents
= 128,
662 .maxFragmentOutputAttachments
= 8,
663 .maxFragmentDualSrcAttachments
= 1,
664 .maxFragmentCombinedOutputResources
= 8,
665 .maxComputeSharedMemorySize
= 32768,
666 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
667 .maxComputeWorkGroupInvocations
= 2048,
668 .maxComputeWorkGroupSize
= {
673 .subPixelPrecisionBits
= 4 /* FIXME */,
674 .subTexelPrecisionBits
= 4 /* FIXME */,
675 .mipmapPrecisionBits
= 4 /* FIXME */,
676 .maxDrawIndexedIndexValue
= UINT32_MAX
,
677 .maxDrawIndirectCount
= UINT32_MAX
,
678 .maxSamplerLodBias
= 16,
679 .maxSamplerAnisotropy
= 16,
680 .maxViewports
= MAX_VIEWPORTS
,
681 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
682 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
683 .viewportSubPixelBits
= 13, /* We take a float? */
684 .minMemoryMapAlignment
= 4096, /* A page */
685 .minTexelBufferOffsetAlignment
= 1,
686 .minUniformBufferOffsetAlignment
= 4,
687 .minStorageBufferOffsetAlignment
= 4,
688 .minTexelOffset
= -32,
689 .maxTexelOffset
= 31,
690 .minTexelGatherOffset
= -32,
691 .maxTexelGatherOffset
= 31,
692 .minInterpolationOffset
= -2,
693 .maxInterpolationOffset
= 2,
694 .subPixelInterpolationOffsetBits
= 8,
695 .maxFramebufferWidth
= (1 << 14),
696 .maxFramebufferHeight
= (1 << 14),
697 .maxFramebufferLayers
= (1 << 10),
698 .framebufferColorSampleCounts
= sample_counts
,
699 .framebufferDepthSampleCounts
= sample_counts
,
700 .framebufferStencilSampleCounts
= sample_counts
,
701 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
702 .maxColorAttachments
= MAX_RTS
,
703 .sampledImageColorSampleCounts
= sample_counts
,
704 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
705 .sampledImageDepthSampleCounts
= sample_counts
,
706 .sampledImageStencilSampleCounts
= sample_counts
,
707 .storageImageSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
708 .maxSampleMaskWords
= 1,
709 .timestampComputeAndGraphics
= true,
710 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
711 .maxClipDistances
= 8,
712 .maxCullDistances
= 8,
713 .maxCombinedClipAndCullDistances
= 8,
714 .discreteQueuePriorities
= 1,
715 .pointSizeRange
= { 0.125, 255.875 },
716 .lineWidthRange
= { 0.0, 7.9921875 },
717 .pointSizeGranularity
= (1.0 / 8.0),
718 .lineWidthGranularity
= (1.0 / 128.0),
719 .strictLines
= false, /* FINISHME */
720 .standardSampleLocations
= true,
721 .optimalBufferCopyOffsetAlignment
= 128,
722 .optimalBufferCopyRowPitchAlignment
= 128,
723 .nonCoherentAtomSize
= 64,
726 *pProperties
= (VkPhysicalDeviceProperties
) {
727 .apiVersion
= VK_MAKE_VERSION(1, 0, 42),
728 .driverVersion
= radv_get_driver_version(),
730 .deviceID
= pdevice
->rad_info
.pci_id
,
731 .deviceType
= VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
,
733 .sparseProperties
= {0},
736 strcpy(pProperties
->deviceName
, pdevice
->name
);
737 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->uuid
, VK_UUID_SIZE
);
740 void radv_GetPhysicalDeviceProperties2KHR(
741 VkPhysicalDevice physicalDevice
,
742 VkPhysicalDeviceProperties2KHR
*pProperties
)
744 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
745 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
747 vk_foreach_struct(ext
, pProperties
->pNext
) {
748 switch (ext
->sType
) {
749 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
750 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
751 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
752 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
755 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHX
: {
756 VkPhysicalDeviceIDPropertiesKHX
*properties
= (VkPhysicalDeviceIDPropertiesKHX
*)ext
;
757 radv_device_get_cache_uuid(0, properties
->driverUUID
);
758 memcpy(properties
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
759 properties
->deviceLUIDValid
= false;
768 static void radv_get_physical_device_queue_family_properties(
769 struct radv_physical_device
* pdevice
,
771 VkQueueFamilyProperties
** pQueueFamilyProperties
)
773 int num_queue_families
= 1;
775 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
776 pdevice
->rad_info
.chip_class
>= CIK
&&
777 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
778 num_queue_families
++;
780 if (pQueueFamilyProperties
== NULL
) {
781 *pCount
= num_queue_families
;
790 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
791 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
792 VK_QUEUE_COMPUTE_BIT
|
793 VK_QUEUE_TRANSFER_BIT
|
794 VK_QUEUE_SPARSE_BINDING_BIT
,
796 .timestampValidBits
= 64,
797 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
802 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
803 pdevice
->rad_info
.chip_class
>= CIK
&&
804 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
806 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
807 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
808 VK_QUEUE_TRANSFER_BIT
|
809 VK_QUEUE_SPARSE_BINDING_BIT
,
810 .queueCount
= pdevice
->rad_info
.num_compute_rings
,
811 .timestampValidBits
= 64,
812 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
820 void radv_GetPhysicalDeviceQueueFamilyProperties(
821 VkPhysicalDevice physicalDevice
,
823 VkQueueFamilyProperties
* pQueueFamilyProperties
)
825 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
826 if (!pQueueFamilyProperties
) {
827 return radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
830 VkQueueFamilyProperties
*properties
[] = {
831 pQueueFamilyProperties
+ 0,
832 pQueueFamilyProperties
+ 1,
833 pQueueFamilyProperties
+ 2,
835 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
836 assert(*pCount
<= 3);
839 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
840 VkPhysicalDevice physicalDevice
,
842 VkQueueFamilyProperties2KHR
*pQueueFamilyProperties
)
844 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
845 if (!pQueueFamilyProperties
) {
846 return radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
849 VkQueueFamilyProperties
*properties
[] = {
850 &pQueueFamilyProperties
[0].queueFamilyProperties
,
851 &pQueueFamilyProperties
[1].queueFamilyProperties
,
852 &pQueueFamilyProperties
[2].queueFamilyProperties
,
854 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
855 assert(*pCount
<= 3);
858 void radv_GetPhysicalDeviceMemoryProperties(
859 VkPhysicalDevice physicalDevice
,
860 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
862 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
864 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
866 pMemoryProperties
->memoryTypeCount
= RADV_MEM_TYPE_COUNT
;
867 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_VRAM
] = (VkMemoryType
) {
868 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
869 .heapIndex
= RADV_MEM_HEAP_VRAM
,
871 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_GTT_WRITE_COMBINE
] = (VkMemoryType
) {
872 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
873 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
874 .heapIndex
= RADV_MEM_HEAP_GTT
,
876 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_VRAM_CPU_ACCESS
] = (VkMemoryType
) {
877 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
878 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
879 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
880 .heapIndex
= RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
882 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_GTT_CACHED
] = (VkMemoryType
) {
883 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
884 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
885 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
,
886 .heapIndex
= RADV_MEM_HEAP_GTT
,
889 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
891 pMemoryProperties
->memoryHeapCount
= RADV_MEM_HEAP_COUNT
;
892 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_VRAM
] = (VkMemoryHeap
) {
893 .size
= physical_device
->rad_info
.vram_size
-
894 physical_device
->rad_info
.vram_vis_size
,
895 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
897 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_VRAM_CPU_ACCESS
] = (VkMemoryHeap
) {
898 .size
= physical_device
->rad_info
.vram_vis_size
,
899 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
901 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_GTT
] = (VkMemoryHeap
) {
902 .size
= physical_device
->rad_info
.gart_size
,
907 void radv_GetPhysicalDeviceMemoryProperties2KHR(
908 VkPhysicalDevice physicalDevice
,
909 VkPhysicalDeviceMemoryProperties2KHR
*pMemoryProperties
)
911 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
912 &pMemoryProperties
->memoryProperties
);
916 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
917 int queue_family_index
, int idx
)
919 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
920 queue
->device
= device
;
921 queue
->queue_family_index
= queue_family_index
;
922 queue
->queue_idx
= idx
;
924 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
);
926 return VK_ERROR_OUT_OF_HOST_MEMORY
;
932 radv_queue_finish(struct radv_queue
*queue
)
935 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
937 if (queue
->initial_preamble_cs
)
938 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
939 if (queue
->continue_preamble_cs
)
940 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
941 if (queue
->descriptor_bo
)
942 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
943 if (queue
->scratch_bo
)
944 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
945 if (queue
->esgs_ring_bo
)
946 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
947 if (queue
->gsvs_ring_bo
)
948 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
949 if (queue
->tess_factor_ring_bo
)
950 queue
->device
->ws
->buffer_destroy(queue
->tess_factor_ring_bo
);
951 if (queue
->tess_offchip_ring_bo
)
952 queue
->device
->ws
->buffer_destroy(queue
->tess_offchip_ring_bo
);
953 if (queue
->compute_scratch_bo
)
954 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
958 radv_device_init_gs_info(struct radv_device
*device
)
960 switch (device
->physical_device
->rad_info
.family
) {
969 device
->gs_table_depth
= 16;
983 device
->gs_table_depth
= 32;
986 unreachable("unknown GPU");
990 VkResult
radv_CreateDevice(
991 VkPhysicalDevice physicalDevice
,
992 const VkDeviceCreateInfo
* pCreateInfo
,
993 const VkAllocationCallbacks
* pAllocator
,
996 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
998 struct radv_device
*device
;
1000 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
1001 if (!is_extension_enabled(physical_device
->extensions
.ext_array
,
1002 physical_device
->extensions
.num_ext
,
1003 pCreateInfo
->ppEnabledExtensionNames
[i
]))
1004 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT
);
1007 device
= vk_alloc2(&physical_device
->instance
->alloc
, pAllocator
,
1009 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1011 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1013 memset(device
, 0, sizeof(*device
));
1015 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1016 device
->instance
= physical_device
->instance
;
1017 device
->physical_device
= physical_device
;
1019 device
->debug_flags
= device
->instance
->debug_flags
;
1021 device
->ws
= physical_device
->ws
;
1023 device
->alloc
= *pAllocator
;
1025 device
->alloc
= physical_device
->instance
->alloc
;
1027 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
1028 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
1029 uint32_t qfi
= queue_create
->queueFamilyIndex
;
1031 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
1032 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1033 if (!device
->queues
[qfi
]) {
1034 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1038 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
1040 device
->queue_count
[qfi
] = queue_create
->queueCount
;
1042 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
1043 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
], qfi
, q
);
1044 if (result
!= VK_SUCCESS
)
1049 #if HAVE_LLVM < 0x0400
1050 device
->llvm_supports_spill
= false;
1052 device
->llvm_supports_spill
= true;
1055 /* The maximum number of scratch waves. Scratch space isn't divided
1056 * evenly between CUs. The number is only a function of the number of CUs.
1057 * We can decrease the constant to decrease the scratch buffer size.
1059 * sctx->scratch_waves must be >= the maximum posible size of
1060 * 1 threadgroup, so that the hw doesn't hang from being unable
1063 * The recommended value is 4 per CU at most. Higher numbers don't
1064 * bring much benefit, but they still occupy chip resources (think
1065 * async compute). I've seen ~2% performance difference between 4 and 32.
1067 uint32_t max_threads_per_block
= 2048;
1068 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
1069 max_threads_per_block
/ 64);
1071 radv_device_init_gs_info(device
);
1073 device
->tess_offchip_block_dw_size
=
1074 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
1075 device
->has_distributed_tess
=
1076 device
->physical_device
->rad_info
.chip_class
>= VI
&&
1077 device
->physical_device
->rad_info
.max_se
>= 2;
1079 result
= radv_device_init_meta(device
);
1080 if (result
!= VK_SUCCESS
)
1083 radv_device_init_msaa(device
);
1085 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
1086 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1088 case RADV_QUEUE_GENERAL
:
1089 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
1090 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
1091 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1093 case RADV_QUEUE_COMPUTE
:
1094 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
1095 radeon_emit(device
->empty_cs
[family
], 0);
1098 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
1100 device
->flush_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1102 case RADV_QUEUE_GENERAL
:
1103 case RADV_QUEUE_COMPUTE
:
1104 si_cs_emit_cache_flush(device
->flush_cs
[family
],
1105 device
->physical_device
->rad_info
.chip_class
,
1106 family
== RADV_QUEUE_COMPUTE
&& device
->physical_device
->rad_info
.chip_class
>= CIK
,
1107 RADV_CMD_FLAG_INV_ICACHE
|
1108 RADV_CMD_FLAG_INV_SMEM_L1
|
1109 RADV_CMD_FLAG_INV_VMEM_L1
|
1110 RADV_CMD_FLAG_INV_GLOBAL_L2
);
1113 device
->ws
->cs_finalize(device
->flush_cs
[family
]);
1115 device
->flush_shader_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1117 case RADV_QUEUE_GENERAL
:
1118 case RADV_QUEUE_COMPUTE
:
1119 si_cs_emit_cache_flush(device
->flush_shader_cs
[family
],
1120 device
->physical_device
->rad_info
.chip_class
,
1121 family
== RADV_QUEUE_COMPUTE
&& device
->physical_device
->rad_info
.chip_class
>= CIK
,
1122 family
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
) |
1123 RADV_CMD_FLAG_INV_ICACHE
|
1124 RADV_CMD_FLAG_INV_SMEM_L1
|
1125 RADV_CMD_FLAG_INV_VMEM_L1
|
1126 RADV_CMD_FLAG_INV_GLOBAL_L2
);
1129 device
->ws
->cs_finalize(device
->flush_shader_cs
[family
]);
1132 if (getenv("RADV_TRACE_FILE")) {
1133 device
->trace_bo
= device
->ws
->buffer_create(device
->ws
, 4096, 8,
1134 RADEON_DOMAIN_VRAM
, RADEON_FLAG_CPU_ACCESS
);
1135 if (!device
->trace_bo
)
1138 device
->trace_id_ptr
= device
->ws
->buffer_map(device
->trace_bo
);
1139 if (!device
->trace_id_ptr
)
1143 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
1144 cik_create_gfx_config(device
);
1146 VkPipelineCacheCreateInfo ci
;
1147 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
1150 ci
.pInitialData
= NULL
;
1151 ci
.initialDataSize
= 0;
1153 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
1155 if (result
!= VK_SUCCESS
)
1158 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
1160 *pDevice
= radv_device_to_handle(device
);
1164 if (device
->trace_bo
)
1165 device
->ws
->buffer_destroy(device
->trace_bo
);
1167 if (device
->gfx_init
)
1168 device
->ws
->buffer_destroy(device
->gfx_init
);
1170 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1171 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1172 radv_queue_finish(&device
->queues
[i
][q
]);
1173 if (device
->queue_count
[i
])
1174 vk_free(&device
->alloc
, device
->queues
[i
]);
1177 vk_free(&device
->alloc
, device
);
1181 void radv_DestroyDevice(
1183 const VkAllocationCallbacks
* pAllocator
)
1185 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1190 if (device
->trace_bo
)
1191 device
->ws
->buffer_destroy(device
->trace_bo
);
1193 if (device
->gfx_init
)
1194 device
->ws
->buffer_destroy(device
->gfx_init
);
1196 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1197 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1198 radv_queue_finish(&device
->queues
[i
][q
]);
1199 if (device
->queue_count
[i
])
1200 vk_free(&device
->alloc
, device
->queues
[i
]);
1201 if (device
->empty_cs
[i
])
1202 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
1203 if (device
->flush_cs
[i
])
1204 device
->ws
->cs_destroy(device
->flush_cs
[i
]);
1205 if (device
->flush_shader_cs
[i
])
1206 device
->ws
->cs_destroy(device
->flush_shader_cs
[i
]);
1208 radv_device_finish_meta(device
);
1210 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
1211 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
1213 vk_free(&device
->alloc
, device
);
1216 VkResult
radv_EnumerateInstanceExtensionProperties(
1217 const char* pLayerName
,
1218 uint32_t* pPropertyCount
,
1219 VkExtensionProperties
* pProperties
)
1221 if (pProperties
== NULL
) {
1222 *pPropertyCount
= ARRAY_SIZE(instance_extensions
);
1226 *pPropertyCount
= MIN2(*pPropertyCount
, ARRAY_SIZE(instance_extensions
));
1227 typed_memcpy(pProperties
, instance_extensions
, *pPropertyCount
);
1229 if (*pPropertyCount
< ARRAY_SIZE(instance_extensions
))
1230 return VK_INCOMPLETE
;
1235 VkResult
radv_EnumerateDeviceExtensionProperties(
1236 VkPhysicalDevice physicalDevice
,
1237 const char* pLayerName
,
1238 uint32_t* pPropertyCount
,
1239 VkExtensionProperties
* pProperties
)
1241 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1243 if (pProperties
== NULL
) {
1244 *pPropertyCount
= pdevice
->extensions
.num_ext
;
1248 *pPropertyCount
= MIN2(*pPropertyCount
, pdevice
->extensions
.num_ext
);
1249 typed_memcpy(pProperties
, pdevice
->extensions
.ext_array
, *pPropertyCount
);
1251 if (*pPropertyCount
< pdevice
->extensions
.num_ext
)
1252 return VK_INCOMPLETE
;
1257 VkResult
radv_EnumerateInstanceLayerProperties(
1258 uint32_t* pPropertyCount
,
1259 VkLayerProperties
* pProperties
)
1261 if (pProperties
== NULL
) {
1262 *pPropertyCount
= 0;
1266 /* None supported at this time */
1267 return vk_error(VK_ERROR_LAYER_NOT_PRESENT
);
1270 VkResult
radv_EnumerateDeviceLayerProperties(
1271 VkPhysicalDevice physicalDevice
,
1272 uint32_t* pPropertyCount
,
1273 VkLayerProperties
* pProperties
)
1275 if (pProperties
== NULL
) {
1276 *pPropertyCount
= 0;
1280 /* None supported at this time */
1281 return vk_error(VK_ERROR_LAYER_NOT_PRESENT
);
1284 void radv_GetDeviceQueue(
1286 uint32_t queueFamilyIndex
,
1287 uint32_t queueIndex
,
1290 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1292 *pQueue
= radv_queue_to_handle(&device
->queues
[queueFamilyIndex
][queueIndex
]);
1295 static void radv_dump_trace(struct radv_device
*device
,
1296 struct radeon_winsys_cs
*cs
)
1298 const char *filename
= getenv("RADV_TRACE_FILE");
1299 FILE *f
= fopen(filename
, "w");
1301 fprintf(stderr
, "Failed to write trace dump to %s\n", filename
);
1305 fprintf(f
, "Trace ID: %x\n", *device
->trace_id_ptr
);
1306 device
->ws
->cs_dump(cs
, f
, *device
->trace_id_ptr
);
1311 fill_geom_tess_rings(struct radv_queue
*queue
,
1313 bool add_sample_positions
,
1314 uint32_t esgs_ring_size
,
1315 struct radeon_winsys_bo
*esgs_ring_bo
,
1316 uint32_t gsvs_ring_size
,
1317 struct radeon_winsys_bo
*gsvs_ring_bo
,
1318 uint32_t tess_factor_ring_size
,
1319 struct radeon_winsys_bo
*tess_factor_ring_bo
,
1320 uint32_t tess_offchip_ring_size
,
1321 struct radeon_winsys_bo
*tess_offchip_ring_bo
)
1323 uint64_t esgs_va
= 0, gsvs_va
= 0;
1324 uint64_t tess_factor_va
= 0, tess_offchip_va
= 0;
1325 uint32_t *desc
= &map
[4];
1328 esgs_va
= queue
->device
->ws
->buffer_get_va(esgs_ring_bo
);
1330 gsvs_va
= queue
->device
->ws
->buffer_get_va(gsvs_ring_bo
);
1331 if (tess_factor_ring_bo
)
1332 tess_factor_va
= queue
->device
->ws
->buffer_get_va(tess_factor_ring_bo
);
1333 if (tess_offchip_ring_bo
)
1334 tess_offchip_va
= queue
->device
->ws
->buffer_get_va(tess_offchip_ring_bo
);
1336 /* stride 0, num records - size, add tid, swizzle, elsize4,
1339 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
1340 S_008F04_STRIDE(0) |
1341 S_008F04_SWIZZLE_ENABLE(true);
1342 desc
[2] = esgs_ring_size
;
1343 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1344 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1345 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1346 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1347 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1348 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1349 S_008F0C_ELEMENT_SIZE(1) |
1350 S_008F0C_INDEX_STRIDE(3) |
1351 S_008F0C_ADD_TID_ENABLE(true);
1354 /* GS entry for ES->GS ring */
1355 /* stride 0, num records - size, elsize0,
1358 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32)|
1359 S_008F04_STRIDE(0) |
1360 S_008F04_SWIZZLE_ENABLE(false);
1361 desc
[2] = esgs_ring_size
;
1362 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1363 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1364 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1365 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1366 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1367 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1368 S_008F0C_ELEMENT_SIZE(0) |
1369 S_008F0C_INDEX_STRIDE(0) |
1370 S_008F0C_ADD_TID_ENABLE(false);
1373 /* VS entry for GS->VS ring */
1374 /* stride 0, num records - size, elsize0,
1377 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
1378 S_008F04_STRIDE(0) |
1379 S_008F04_SWIZZLE_ENABLE(false);
1380 desc
[2] = gsvs_ring_size
;
1381 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1382 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1383 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1384 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1385 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1386 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1387 S_008F0C_ELEMENT_SIZE(0) |
1388 S_008F0C_INDEX_STRIDE(0) |
1389 S_008F0C_ADD_TID_ENABLE(false);
1392 /* stride gsvs_itemsize, num records 64
1393 elsize 4, index stride 16 */
1394 /* shader will patch stride and desc[2] */
1396 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
1397 S_008F04_STRIDE(0) |
1398 S_008F04_SWIZZLE_ENABLE(true);
1400 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1401 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1402 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1403 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1404 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1405 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1406 S_008F0C_ELEMENT_SIZE(1) |
1407 S_008F0C_INDEX_STRIDE(1) |
1408 S_008F0C_ADD_TID_ENABLE(true);
1411 desc
[0] = tess_factor_va
;
1412 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va
>> 32) |
1413 S_008F04_STRIDE(0) |
1414 S_008F04_SWIZZLE_ENABLE(false);
1415 desc
[2] = tess_factor_ring_size
;
1416 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1417 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1418 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1419 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1420 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1421 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1422 S_008F0C_ELEMENT_SIZE(0) |
1423 S_008F0C_INDEX_STRIDE(0) |
1424 S_008F0C_ADD_TID_ENABLE(false);
1427 desc
[0] = tess_offchip_va
;
1428 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32) |
1429 S_008F04_STRIDE(0) |
1430 S_008F04_SWIZZLE_ENABLE(false);
1431 desc
[2] = tess_offchip_ring_size
;
1432 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1433 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1434 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1435 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1436 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1437 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1438 S_008F0C_ELEMENT_SIZE(0) |
1439 S_008F0C_INDEX_STRIDE(0) |
1440 S_008F0C_ADD_TID_ENABLE(false);
1443 /* add sample positions after all rings */
1444 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
1446 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
1448 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
1450 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
1452 memcpy(desc
, queue
->device
->sample_locations_16x
, 128);
1456 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
1458 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= CIK
&&
1459 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
1460 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
1461 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
1462 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
1463 device
->physical_device
->rad_info
.max_se
;
1464 unsigned offchip_granularity
;
1465 unsigned hs_offchip_param
;
1466 switch (device
->tess_offchip_block_dw_size
) {
1471 offchip_granularity
= V_03093C_X_8K_DWORDS
;
1474 offchip_granularity
= V_03093C_X_4K_DWORDS
;
1478 switch (device
->physical_device
->rad_info
.chip_class
) {
1480 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
1486 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
1490 *max_offchip_buffers_p
= max_offchip_buffers
;
1491 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1492 if (device
->physical_device
->rad_info
.chip_class
>= VI
)
1493 --max_offchip_buffers
;
1495 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
1496 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
1499 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
1501 return hs_offchip_param
;
1505 radv_get_preamble_cs(struct radv_queue
*queue
,
1506 uint32_t scratch_size
,
1507 uint32_t compute_scratch_size
,
1508 uint32_t esgs_ring_size
,
1509 uint32_t gsvs_ring_size
,
1510 bool needs_tess_rings
,
1511 bool needs_sample_positions
,
1512 struct radeon_winsys_cs
**initial_preamble_cs
,
1513 struct radeon_winsys_cs
**continue_preamble_cs
)
1515 struct radeon_winsys_bo
*scratch_bo
= NULL
;
1516 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
1517 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
1518 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
1519 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
1520 struct radeon_winsys_bo
*tess_factor_ring_bo
= NULL
;
1521 struct radeon_winsys_bo
*tess_offchip_ring_bo
= NULL
;
1522 struct radeon_winsys_cs
*dest_cs
[2] = {0};
1523 bool add_tess_rings
= false, add_sample_positions
= false;
1524 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
1525 unsigned max_offchip_buffers
;
1526 unsigned hs_offchip_param
= 0;
1527 if (!queue
->has_tess_rings
) {
1528 if (needs_tess_rings
)
1529 add_tess_rings
= true;
1531 if (!queue
->has_sample_positions
) {
1532 if (needs_sample_positions
)
1533 add_sample_positions
= true;
1535 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
1536 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
1537 &max_offchip_buffers
);
1538 tess_offchip_ring_size
= max_offchip_buffers
*
1539 queue
->device
->tess_offchip_block_dw_size
* 4;
1541 if (scratch_size
<= queue
->scratch_size
&&
1542 compute_scratch_size
<= queue
->compute_scratch_size
&&
1543 esgs_ring_size
<= queue
->esgs_ring_size
&&
1544 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
1545 !add_tess_rings
&& !add_sample_positions
&&
1546 queue
->initial_preamble_cs
) {
1547 *initial_preamble_cs
= queue
->initial_preamble_cs
;
1548 *continue_preamble_cs
= queue
->continue_preamble_cs
;
1549 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
1550 *continue_preamble_cs
= NULL
;
1554 if (scratch_size
> queue
->scratch_size
) {
1555 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1559 RADEON_FLAG_NO_CPU_ACCESS
);
1563 scratch_bo
= queue
->scratch_bo
;
1565 if (compute_scratch_size
> queue
->compute_scratch_size
) {
1566 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1567 compute_scratch_size
,
1570 RADEON_FLAG_NO_CPU_ACCESS
);
1571 if (!compute_scratch_bo
)
1575 compute_scratch_bo
= queue
->compute_scratch_bo
;
1577 if (esgs_ring_size
> queue
->esgs_ring_size
) {
1578 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1582 RADEON_FLAG_NO_CPU_ACCESS
);
1586 esgs_ring_bo
= queue
->esgs_ring_bo
;
1587 esgs_ring_size
= queue
->esgs_ring_size
;
1590 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
1591 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1595 RADEON_FLAG_NO_CPU_ACCESS
);
1599 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
1600 gsvs_ring_size
= queue
->gsvs_ring_size
;
1603 if (add_tess_rings
) {
1604 tess_factor_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1605 tess_factor_ring_size
,
1608 RADEON_FLAG_NO_CPU_ACCESS
);
1609 if (!tess_factor_ring_bo
)
1611 tess_offchip_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1612 tess_offchip_ring_size
,
1615 RADEON_FLAG_NO_CPU_ACCESS
);
1616 if (!tess_offchip_ring_bo
)
1619 tess_factor_ring_bo
= queue
->tess_factor_ring_bo
;
1620 tess_offchip_ring_bo
= queue
->tess_offchip_ring_bo
;
1623 if (scratch_bo
!= queue
->scratch_bo
||
1624 esgs_ring_bo
!= queue
->esgs_ring_bo
||
1625 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
1626 tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
||
1627 tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
|| add_sample_positions
) {
1629 if (gsvs_ring_bo
|| esgs_ring_bo
||
1630 tess_factor_ring_bo
|| tess_offchip_ring_bo
|| add_sample_positions
) {
1631 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
1632 if (add_sample_positions
)
1633 size
+= 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1635 else if (scratch_bo
)
1636 size
= 8; /* 2 dword */
1638 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1642 RADEON_FLAG_CPU_ACCESS
);
1646 descriptor_bo
= queue
->descriptor_bo
;
1648 for(int i
= 0; i
< 2; ++i
) {
1649 struct radeon_winsys_cs
*cs
= NULL
;
1650 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
1651 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
1658 queue
->device
->ws
->cs_add_buffer(cs
, scratch_bo
, 8);
1661 queue
->device
->ws
->cs_add_buffer(cs
, esgs_ring_bo
, 8);
1664 queue
->device
->ws
->cs_add_buffer(cs
, gsvs_ring_bo
, 8);
1666 if (tess_factor_ring_bo
)
1667 queue
->device
->ws
->cs_add_buffer(cs
, tess_factor_ring_bo
, 8);
1669 if (tess_offchip_ring_bo
)
1670 queue
->device
->ws
->cs_add_buffer(cs
, tess_offchip_ring_bo
, 8);
1673 queue
->device
->ws
->cs_add_buffer(cs
, descriptor_bo
, 8);
1675 if (descriptor_bo
!= queue
->descriptor_bo
) {
1676 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
1679 uint64_t scratch_va
= queue
->device
->ws
->buffer_get_va(scratch_bo
);
1680 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
1681 S_008F04_SWIZZLE_ENABLE(1);
1682 map
[0] = scratch_va
;
1686 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_factor_ring_bo
|| tess_offchip_ring_bo
||
1687 add_sample_positions
)
1688 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
1689 esgs_ring_size
, esgs_ring_bo
,
1690 gsvs_ring_size
, gsvs_ring_bo
,
1691 tess_factor_ring_size
, tess_factor_ring_bo
,
1692 tess_offchip_ring_size
, tess_offchip_ring_bo
);
1694 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
1697 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_factor_ring_bo
|| tess_offchip_ring_bo
) {
1698 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1699 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1700 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1701 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1704 if (esgs_ring_bo
|| gsvs_ring_bo
) {
1705 if (queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1706 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
1707 radeon_emit(cs
, esgs_ring_size
>> 8);
1708 radeon_emit(cs
, gsvs_ring_size
>> 8);
1710 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
1711 radeon_emit(cs
, esgs_ring_size
>> 8);
1712 radeon_emit(cs
, gsvs_ring_size
>> 8);
1716 if (tess_factor_ring_bo
) {
1717 uint64_t tf_va
= queue
->device
->ws
->buffer_get_va(tess_factor_ring_bo
);
1718 if (queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1719 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
1720 S_030938_SIZE(tess_factor_ring_size
/ 4));
1721 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
1723 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
, hs_offchip_param
);
1725 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
1726 S_008988_SIZE(tess_factor_ring_size
/ 4));
1727 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
1729 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
1734 if (descriptor_bo
) {
1735 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
1736 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
1737 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
1738 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
1739 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
1740 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
1742 uint64_t va
= queue
->device
->ws
->buffer_get_va(descriptor_bo
);
1744 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
1745 radeon_set_sh_reg_seq(cs
, regs
[i
], 2);
1746 radeon_emit(cs
, va
);
1747 radeon_emit(cs
, va
>> 32);
1751 if (compute_scratch_bo
) {
1752 uint64_t scratch_va
= queue
->device
->ws
->buffer_get_va(compute_scratch_bo
);
1753 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
1754 S_008F04_SWIZZLE_ENABLE(1);
1756 queue
->device
->ws
->cs_add_buffer(cs
, compute_scratch_bo
, 8);
1758 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
1759 radeon_emit(cs
, scratch_va
);
1760 radeon_emit(cs
, rsrc1
);
1764 si_cs_emit_cache_flush(cs
,
1765 queue
->device
->physical_device
->rad_info
.chip_class
,
1766 queue
->queue_family_index
== RING_COMPUTE
&&
1767 queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
,
1768 RADV_CMD_FLAG_INV_ICACHE
|
1769 RADV_CMD_FLAG_INV_SMEM_L1
|
1770 RADV_CMD_FLAG_INV_VMEM_L1
|
1771 RADV_CMD_FLAG_INV_GLOBAL_L2
);
1774 if (!queue
->device
->ws
->cs_finalize(cs
))
1778 if (queue
->initial_preamble_cs
)
1779 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
1781 if (queue
->continue_preamble_cs
)
1782 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
1784 queue
->initial_preamble_cs
= dest_cs
[0];
1785 queue
->continue_preamble_cs
= dest_cs
[1];
1787 if (scratch_bo
!= queue
->scratch_bo
) {
1788 if (queue
->scratch_bo
)
1789 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1790 queue
->scratch_bo
= scratch_bo
;
1791 queue
->scratch_size
= scratch_size
;
1794 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
1795 if (queue
->compute_scratch_bo
)
1796 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1797 queue
->compute_scratch_bo
= compute_scratch_bo
;
1798 queue
->compute_scratch_size
= compute_scratch_size
;
1801 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
1802 if (queue
->esgs_ring_bo
)
1803 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
1804 queue
->esgs_ring_bo
= esgs_ring_bo
;
1805 queue
->esgs_ring_size
= esgs_ring_size
;
1808 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
1809 if (queue
->gsvs_ring_bo
)
1810 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
1811 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
1812 queue
->gsvs_ring_size
= gsvs_ring_size
;
1815 if (tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
) {
1816 queue
->tess_factor_ring_bo
= tess_factor_ring_bo
;
1819 if (tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
) {
1820 queue
->tess_offchip_ring_bo
= tess_offchip_ring_bo
;
1821 queue
->has_tess_rings
= true;
1824 if (descriptor_bo
!= queue
->descriptor_bo
) {
1825 if (queue
->descriptor_bo
)
1826 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1828 queue
->descriptor_bo
= descriptor_bo
;
1831 if (add_sample_positions
)
1832 queue
->has_sample_positions
= true;
1834 *initial_preamble_cs
= queue
->initial_preamble_cs
;
1835 *continue_preamble_cs
= queue
->continue_preamble_cs
;
1836 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
1837 *continue_preamble_cs
= NULL
;
1840 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
1842 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
1843 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
1844 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
1845 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
1846 queue
->device
->ws
->buffer_destroy(scratch_bo
);
1847 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
1848 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
1849 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
1850 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
1851 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
1852 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
1853 if (tess_factor_ring_bo
&& tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
)
1854 queue
->device
->ws
->buffer_destroy(tess_factor_ring_bo
);
1855 if (tess_offchip_ring_bo
&& tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
)
1856 queue
->device
->ws
->buffer_destroy(tess_offchip_ring_bo
);
1857 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1860 VkResult
radv_QueueSubmit(
1862 uint32_t submitCount
,
1863 const VkSubmitInfo
* pSubmits
,
1866 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
1867 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
1868 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
1869 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
1871 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : UINT32_MAX
;
1872 uint32_t scratch_size
= 0;
1873 uint32_t compute_scratch_size
= 0;
1874 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
1875 struct radeon_winsys_cs
*initial_preamble_cs
= NULL
, *continue_preamble_cs
= NULL
;
1877 bool fence_emitted
= false;
1878 bool tess_rings_needed
= false;
1879 bool sample_positions_needed
= false;
1881 /* Do this first so failing to allocate scratch buffers can't result in
1882 * partially executed submissions. */
1883 for (uint32_t i
= 0; i
< submitCount
; i
++) {
1884 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
1885 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
1886 pSubmits
[i
].pCommandBuffers
[j
]);
1888 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
1889 compute_scratch_size
= MAX2(compute_scratch_size
,
1890 cmd_buffer
->compute_scratch_size_needed
);
1891 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
1892 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
1893 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
1894 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
1898 result
= radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
,
1899 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
1900 sample_positions_needed
,
1901 &initial_preamble_cs
, &continue_preamble_cs
);
1902 if (result
!= VK_SUCCESS
)
1905 for (uint32_t i
= 0; i
< submitCount
; i
++) {
1906 struct radeon_winsys_cs
**cs_array
;
1907 bool do_flush
= !i
|| pSubmits
[i
].pWaitDstStageMask
;
1908 bool can_patch
= !do_flush
;
1911 if (!pSubmits
[i
].commandBufferCount
) {
1912 if (pSubmits
[i
].waitSemaphoreCount
|| pSubmits
[i
].signalSemaphoreCount
) {
1913 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
1914 &queue
->device
->empty_cs
[queue
->queue_family_index
],
1916 (struct radeon_winsys_sem
**)pSubmits
[i
].pWaitSemaphores
,
1917 pSubmits
[i
].waitSemaphoreCount
,
1918 (struct radeon_winsys_sem
**)pSubmits
[i
].pSignalSemaphores
,
1919 pSubmits
[i
].signalSemaphoreCount
,
1922 radv_loge("failed to submit CS %d\n", i
);
1925 fence_emitted
= true;
1930 cs_array
= malloc(sizeof(struct radeon_winsys_cs
*) *
1931 (pSubmits
[i
].commandBufferCount
+ do_flush
));
1934 cs_array
[0] = pSubmits
[i
].waitSemaphoreCount
?
1935 queue
->device
->flush_shader_cs
[queue
->queue_family_index
] :
1936 queue
->device
->flush_cs
[queue
->queue_family_index
];
1938 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
1939 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
1940 pSubmits
[i
].pCommandBuffers
[j
]);
1941 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1943 cs_array
[j
+ do_flush
] = cmd_buffer
->cs
;
1944 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
1948 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
+ do_flush
; j
+= advance
) {
1949 advance
= MIN2(max_cs_submission
,
1950 pSubmits
[i
].commandBufferCount
+ do_flush
- j
);
1952 bool e
= j
+ advance
== pSubmits
[i
].commandBufferCount
+ do_flush
;
1954 if (queue
->device
->trace_bo
)
1955 *queue
->device
->trace_id_ptr
= 0;
1957 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
1958 advance
, initial_preamble_cs
, continue_preamble_cs
,
1959 (struct radeon_winsys_sem
**)pSubmits
[i
].pWaitSemaphores
,
1960 b
? pSubmits
[i
].waitSemaphoreCount
: 0,
1961 (struct radeon_winsys_sem
**)pSubmits
[i
].pSignalSemaphores
,
1962 e
? pSubmits
[i
].signalSemaphoreCount
: 0,
1963 can_patch
, base_fence
);
1966 radv_loge("failed to submit CS %d\n", i
);
1969 fence_emitted
= true;
1970 if (queue
->device
->trace_bo
) {
1971 bool success
= queue
->device
->ws
->ctx_wait_idle(
1973 radv_queue_family_to_ring(
1974 queue
->queue_family_index
),
1977 if (!success
) { /* Hang */
1978 radv_dump_trace(queue
->device
, cs_array
[j
]);
1988 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
1989 &queue
->device
->empty_cs
[queue
->queue_family_index
],
1990 1, NULL
, NULL
, NULL
, 0, NULL
, 0,
1993 fence
->submitted
= true;
1999 VkResult
radv_QueueWaitIdle(
2002 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2004 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
2005 radv_queue_family_to_ring(queue
->queue_family_index
),
2010 VkResult
radv_DeviceWaitIdle(
2013 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2015 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2016 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
2017 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
2023 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
2024 VkInstance instance
,
2027 return radv_lookup_entrypoint(pName
);
2030 /* The loader wants us to expose a second GetInstanceProcAddr function
2031 * to work around certain LD_PRELOAD issues seen in apps.
2034 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
2035 VkInstance instance
,
2039 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
2040 VkInstance instance
,
2043 return radv_GetInstanceProcAddr(instance
, pName
);
2046 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
2050 return radv_lookup_entrypoint(pName
);
2053 bool radv_get_memory_fd(struct radv_device
*device
,
2054 struct radv_device_memory
*memory
,
2057 struct radeon_bo_metadata metadata
;
2059 if (memory
->image
) {
2060 radv_init_metadata(device
, memory
->image
, &metadata
);
2061 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
2064 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
2068 VkResult
radv_AllocateMemory(
2070 const VkMemoryAllocateInfo
* pAllocateInfo
,
2071 const VkAllocationCallbacks
* pAllocator
,
2072 VkDeviceMemory
* pMem
)
2074 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2075 struct radv_device_memory
*mem
;
2077 enum radeon_bo_domain domain
;
2080 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
2082 if (pAllocateInfo
->allocationSize
== 0) {
2083 /* Apparently, this is allowed */
2084 *pMem
= VK_NULL_HANDLE
;
2088 const VkImportMemoryFdInfoKHX
*import_info
=
2089 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHX
);
2090 const VkDedicatedAllocationMemoryAllocateInfoNV
*dedicate_info
=
2091 vk_find_struct_const(pAllocateInfo
->pNext
, DEDICATED_ALLOCATION_MEMORY_ALLOCATE_INFO_NV
);
2093 mem
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
2094 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2096 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2098 if (dedicate_info
) {
2099 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
2100 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
2107 assert(import_info
->handleType
==
2108 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHX
);
2109 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
2117 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
2118 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
2119 pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_CACHED
)
2120 domain
= RADEON_DOMAIN_GTT
;
2122 domain
= RADEON_DOMAIN_VRAM
;
2124 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_VRAM
)
2125 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
2127 flags
|= RADEON_FLAG_CPU_ACCESS
;
2129 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
2130 flags
|= RADEON_FLAG_GTT_WC
;
2132 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, 65536,
2136 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2139 mem
->type_index
= pAllocateInfo
->memoryTypeIndex
;
2141 *pMem
= radv_device_memory_to_handle(mem
);
2146 vk_free2(&device
->alloc
, pAllocator
, mem
);
2151 void radv_FreeMemory(
2153 VkDeviceMemory _mem
,
2154 const VkAllocationCallbacks
* pAllocator
)
2156 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2157 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
2162 device
->ws
->buffer_destroy(mem
->bo
);
2165 vk_free2(&device
->alloc
, pAllocator
, mem
);
2168 VkResult
radv_MapMemory(
2170 VkDeviceMemory _memory
,
2171 VkDeviceSize offset
,
2173 VkMemoryMapFlags flags
,
2176 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2177 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2184 *ppData
= device
->ws
->buffer_map(mem
->bo
);
2190 return VK_ERROR_MEMORY_MAP_FAILED
;
2193 void radv_UnmapMemory(
2195 VkDeviceMemory _memory
)
2197 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2198 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2203 device
->ws
->buffer_unmap(mem
->bo
);
2206 VkResult
radv_FlushMappedMemoryRanges(
2208 uint32_t memoryRangeCount
,
2209 const VkMappedMemoryRange
* pMemoryRanges
)
2214 VkResult
radv_InvalidateMappedMemoryRanges(
2216 uint32_t memoryRangeCount
,
2217 const VkMappedMemoryRange
* pMemoryRanges
)
2222 void radv_GetBufferMemoryRequirements(
2225 VkMemoryRequirements
* pMemoryRequirements
)
2227 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2229 pMemoryRequirements
->memoryTypeBits
= (1u << RADV_MEM_TYPE_COUNT
) - 1;
2231 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
2232 pMemoryRequirements
->alignment
= 4096;
2234 pMemoryRequirements
->alignment
= 16;
2236 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
2239 void radv_GetImageMemoryRequirements(
2242 VkMemoryRequirements
* pMemoryRequirements
)
2244 RADV_FROM_HANDLE(radv_image
, image
, _image
);
2246 pMemoryRequirements
->memoryTypeBits
= (1u << RADV_MEM_TYPE_COUNT
) - 1;
2248 pMemoryRequirements
->size
= image
->size
;
2249 pMemoryRequirements
->alignment
= image
->alignment
;
2252 void radv_GetImageSparseMemoryRequirements(
2255 uint32_t* pSparseMemoryRequirementCount
,
2256 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
2261 void radv_GetDeviceMemoryCommitment(
2263 VkDeviceMemory memory
,
2264 VkDeviceSize
* pCommittedMemoryInBytes
)
2266 *pCommittedMemoryInBytes
= 0;
2269 VkResult
radv_BindBufferMemory(
2272 VkDeviceMemory _memory
,
2273 VkDeviceSize memoryOffset
)
2275 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2276 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2279 buffer
->bo
= mem
->bo
;
2280 buffer
->offset
= memoryOffset
;
2289 VkResult
radv_BindImageMemory(
2292 VkDeviceMemory _memory
,
2293 VkDeviceSize memoryOffset
)
2295 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2296 RADV_FROM_HANDLE(radv_image
, image
, _image
);
2299 image
->bo
= mem
->bo
;
2300 image
->offset
= memoryOffset
;
2311 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
2312 const VkSparseBufferMemoryBindInfo
*bind
)
2314 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
2316 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
2317 struct radv_device_memory
*mem
= NULL
;
2319 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
2320 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
2322 device
->ws
->buffer_virtual_bind(buffer
->bo
,
2323 bind
->pBinds
[i
].resourceOffset
,
2324 bind
->pBinds
[i
].size
,
2325 mem
? mem
->bo
: NULL
,
2326 bind
->pBinds
[i
].memoryOffset
);
2331 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
2332 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
2334 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
2336 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
2337 struct radv_device_memory
*mem
= NULL
;
2339 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
2340 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
2342 device
->ws
->buffer_virtual_bind(image
->bo
,
2343 bind
->pBinds
[i
].resourceOffset
,
2344 bind
->pBinds
[i
].size
,
2345 mem
? mem
->bo
: NULL
,
2346 bind
->pBinds
[i
].memoryOffset
);
2350 VkResult
radv_QueueBindSparse(
2352 uint32_t bindInfoCount
,
2353 const VkBindSparseInfo
* pBindInfo
,
2356 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2357 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2358 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
2359 bool fence_emitted
= false;
2361 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
2362 for (uint32_t j
= 0; j
< pBindInfo
[i
].bufferBindCount
; ++j
) {
2363 radv_sparse_buffer_bind_memory(queue
->device
,
2364 pBindInfo
[i
].pBufferBinds
+ j
);
2367 for (uint32_t j
= 0; j
< pBindInfo
[i
].imageOpaqueBindCount
; ++j
) {
2368 radv_sparse_image_opaque_bind_memory(queue
->device
,
2369 pBindInfo
[i
].pImageOpaqueBinds
+ j
);
2372 if (pBindInfo
[i
].waitSemaphoreCount
|| pBindInfo
[i
].signalSemaphoreCount
) {
2373 queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
2374 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2376 (struct radeon_winsys_sem
**)pBindInfo
[i
].pWaitSemaphores
,
2377 pBindInfo
[i
].waitSemaphoreCount
,
2378 (struct radeon_winsys_sem
**)pBindInfo
[i
].pSignalSemaphores
,
2379 pBindInfo
[i
].signalSemaphoreCount
,
2381 fence_emitted
= true;
2383 fence
->submitted
= true;
2387 if (fence
&& !fence_emitted
) {
2388 fence
->signalled
= true;
2394 VkResult
radv_CreateFence(
2396 const VkFenceCreateInfo
* pCreateInfo
,
2397 const VkAllocationCallbacks
* pAllocator
,
2400 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2401 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
2403 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2406 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2408 memset(fence
, 0, sizeof(*fence
));
2409 fence
->submitted
= false;
2410 fence
->signalled
= !!(pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
);
2411 fence
->fence
= device
->ws
->create_fence();
2412 if (!fence
->fence
) {
2413 vk_free2(&device
->alloc
, pAllocator
, fence
);
2414 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2417 *pFence
= radv_fence_to_handle(fence
);
2422 void radv_DestroyFence(
2425 const VkAllocationCallbacks
* pAllocator
)
2427 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2428 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2432 device
->ws
->destroy_fence(fence
->fence
);
2433 vk_free2(&device
->alloc
, pAllocator
, fence
);
2436 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
2438 uint64_t current_time
;
2441 clock_gettime(CLOCK_MONOTONIC
, &tv
);
2442 current_time
= tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
2444 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
2446 return current_time
+ timeout
;
2449 VkResult
radv_WaitForFences(
2451 uint32_t fenceCount
,
2452 const VkFence
* pFences
,
2456 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2457 timeout
= radv_get_absolute_timeout(timeout
);
2459 if (!waitAll
&& fenceCount
> 1) {
2460 fprintf(stderr
, "radv: WaitForFences without waitAll not implemented yet\n");
2463 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
2464 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
2465 bool expired
= false;
2467 if (fence
->signalled
)
2470 if (!fence
->submitted
)
2473 expired
= device
->ws
->fence_wait(device
->ws
, fence
->fence
, true, timeout
);
2477 fence
->signalled
= true;
2483 VkResult
radv_ResetFences(VkDevice device
,
2484 uint32_t fenceCount
,
2485 const VkFence
*pFences
)
2487 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
2488 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
2489 fence
->submitted
= fence
->signalled
= false;
2495 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
2497 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2498 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2500 if (fence
->signalled
)
2502 if (!fence
->submitted
)
2503 return VK_NOT_READY
;
2505 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
2506 return VK_NOT_READY
;
2512 // Queue semaphore functions
2514 VkResult
radv_CreateSemaphore(
2516 const VkSemaphoreCreateInfo
* pCreateInfo
,
2517 const VkAllocationCallbacks
* pAllocator
,
2518 VkSemaphore
* pSemaphore
)
2520 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2521 struct radeon_winsys_sem
*sem
;
2523 sem
= device
->ws
->create_sem(device
->ws
);
2525 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2527 *pSemaphore
= radeon_winsys_sem_to_handle(sem
);
2531 void radv_DestroySemaphore(
2533 VkSemaphore _semaphore
,
2534 const VkAllocationCallbacks
* pAllocator
)
2536 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2537 RADV_FROM_HANDLE(radeon_winsys_sem
, sem
, _semaphore
);
2541 device
->ws
->destroy_sem(sem
);
2544 VkResult
radv_CreateEvent(
2546 const VkEventCreateInfo
* pCreateInfo
,
2547 const VkAllocationCallbacks
* pAllocator
,
2550 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2551 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
2553 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2556 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2558 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
2560 RADEON_FLAG_CPU_ACCESS
);
2562 vk_free2(&device
->alloc
, pAllocator
, event
);
2563 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2566 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
2568 *pEvent
= radv_event_to_handle(event
);
2573 void radv_DestroyEvent(
2576 const VkAllocationCallbacks
* pAllocator
)
2578 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2579 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2583 device
->ws
->buffer_destroy(event
->bo
);
2584 vk_free2(&device
->alloc
, pAllocator
, event
);
2587 VkResult
radv_GetEventStatus(
2591 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2593 if (*event
->map
== 1)
2594 return VK_EVENT_SET
;
2595 return VK_EVENT_RESET
;
2598 VkResult
radv_SetEvent(
2602 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2608 VkResult
radv_ResetEvent(
2612 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2618 VkResult
radv_CreateBuffer(
2620 const VkBufferCreateInfo
* pCreateInfo
,
2621 const VkAllocationCallbacks
* pAllocator
,
2624 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2625 struct radv_buffer
*buffer
;
2627 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
2629 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
2630 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2632 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2634 buffer
->size
= pCreateInfo
->size
;
2635 buffer
->usage
= pCreateInfo
->usage
;
2638 buffer
->flags
= pCreateInfo
->flags
;
2640 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
2641 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
2642 align64(buffer
->size
, 4096),
2643 4096, 0, RADEON_FLAG_VIRTUAL
);
2645 vk_free2(&device
->alloc
, pAllocator
, buffer
);
2646 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2650 *pBuffer
= radv_buffer_to_handle(buffer
);
2655 void radv_DestroyBuffer(
2658 const VkAllocationCallbacks
* pAllocator
)
2660 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2661 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2666 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
2667 device
->ws
->buffer_destroy(buffer
->bo
);
2669 vk_free2(&device
->alloc
, pAllocator
, buffer
);
2672 static inline unsigned
2673 si_tile_mode_index(const struct radv_image
*image
, unsigned level
, bool stencil
)
2676 return image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2678 return image
->surface
.u
.legacy
.tiling_index
[level
];
2681 static uint32_t radv_surface_layer_count(struct radv_image_view
*iview
)
2683 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: iview
->layer_count
;
2687 radv_initialise_color_surface(struct radv_device
*device
,
2688 struct radv_color_buffer_info
*cb
,
2689 struct radv_image_view
*iview
)
2691 const struct vk_format_description
*desc
;
2692 unsigned ntype
, format
, swap
, endian
;
2693 unsigned blend_clamp
= 0, blend_bypass
= 0;
2695 const struct radeon_surf
*surf
= &iview
->image
->surface
;
2697 desc
= vk_format_description(iview
->vk_format
);
2699 memset(cb
, 0, sizeof(*cb
));
2701 /* Intensity is implemented as Red, so treat it that way. */
2702 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
2704 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2707 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
2708 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
2710 va
+= level_info
->offset
;
2712 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
2713 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
2714 tile_mode_index
= si_tile_mode_index(iview
->image
, iview
->base_mip
, false);
2716 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
2717 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
2718 cb
->cb_color_cmask_slice
= iview
->image
->cmask
.slice_tile_max
;
2720 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
2721 cb
->micro_tile_mode
= iview
->image
->surface
.micro_tile_mode
;
2723 if (iview
->image
->fmask
.size
) {
2724 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
2725 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(iview
->image
->fmask
.pitch_in_pixels
/ 8 - 1);
2726 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(iview
->image
->fmask
.tile_mode_index
);
2727 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(iview
->image
->fmask
.slice_tile_max
);
2729 /* This must be set for fast clear to work without FMASK. */
2730 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
2731 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
2732 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
2733 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
2737 cb
->cb_color_base
= va
>> 8;
2739 /* CMASK variables */
2740 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2741 va
+= iview
->image
->cmask
.offset
;
2742 cb
->cb_color_cmask
= va
>> 8;
2744 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2745 va
+= iview
->image
->dcc_offset
;
2746 cb
->cb_dcc_base
= va
>> 8;
2748 uint32_t max_slice
= radv_surface_layer_count(iview
);
2749 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
2750 S_028C6C_SLICE_MAX(iview
->base_layer
+ max_slice
- 1);
2752 if (iview
->image
->info
.samples
> 1) {
2753 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
2755 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2756 S_028C74_NUM_FRAGMENTS(log_samples
);
2759 if (iview
->image
->fmask
.size
) {
2760 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask
.offset
;
2761 cb
->cb_color_fmask
= va
>> 8;
2763 cb
->cb_color_fmask
= cb
->cb_color_base
;
2766 ntype
= radv_translate_color_numformat(iview
->vk_format
,
2768 vk_format_get_first_non_void_channel(iview
->vk_format
));
2769 format
= radv_translate_colorformat(iview
->vk_format
);
2770 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
2771 radv_finishme("Illegal color\n");
2772 swap
= radv_translate_colorswap(iview
->vk_format
, FALSE
);
2773 endian
= radv_colorformat_endian_swap(format
);
2775 /* blend clamp should be set for all NORM/SRGB types */
2776 if (ntype
== V_028C70_NUMBER_UNORM
||
2777 ntype
== V_028C70_NUMBER_SNORM
||
2778 ntype
== V_028C70_NUMBER_SRGB
)
2781 /* set blend bypass according to docs if SINT/UINT or
2782 8/24 COLOR variants */
2783 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2784 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2785 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2790 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
2791 (format
== V_028C70_COLOR_8
||
2792 format
== V_028C70_COLOR_8_8
||
2793 format
== V_028C70_COLOR_8_8_8_8
))
2794 ->color_is_int8
= true;
2796 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
2797 S_028C70_COMP_SWAP(swap
) |
2798 S_028C70_BLEND_CLAMP(blend_clamp
) |
2799 S_028C70_BLEND_BYPASS(blend_bypass
) |
2800 S_028C70_SIMPLE_FLOAT(1) |
2801 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2802 ntype
!= V_028C70_NUMBER_SNORM
&&
2803 ntype
!= V_028C70_NUMBER_SRGB
&&
2804 format
!= V_028C70_COLOR_8_24
&&
2805 format
!= V_028C70_COLOR_24_8
) |
2806 S_028C70_NUMBER_TYPE(ntype
) |
2807 S_028C70_ENDIAN(endian
);
2808 if (iview
->image
->info
.samples
> 1)
2809 if (iview
->image
->fmask
.size
)
2810 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
2812 if (iview
->image
->cmask
.size
&&
2813 !(device
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
2814 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
2816 if (iview
->image
->surface
.dcc_size
&& iview
->base_mip
< surf
->num_dcc_levels
)
2817 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
2819 if (device
->physical_device
->rad_info
.chip_class
>= VI
) {
2820 unsigned max_uncompressed_block_size
= 2;
2821 if (iview
->image
->info
.samples
> 1) {
2822 if (iview
->image
->surface
.bpe
== 1)
2823 max_uncompressed_block_size
= 0;
2824 else if (iview
->image
->surface
.bpe
== 2)
2825 max_uncompressed_block_size
= 1;
2828 cb
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2829 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2832 /* This must be set for fast clear to work without FMASK. */
2833 if (!iview
->image
->fmask
.size
&&
2834 device
->physical_device
->rad_info
.chip_class
== SI
) {
2835 unsigned bankh
= util_logbase2(iview
->image
->surface
.u
.legacy
.bankh
);
2836 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2841 radv_initialise_ds_surface(struct radv_device
*device
,
2842 struct radv_ds_buffer_info
*ds
,
2843 struct radv_image_view
*iview
)
2845 unsigned level
= iview
->base_mip
;
2846 unsigned format
, stencil_format
;
2847 uint64_t va
, s_offs
, z_offs
;
2848 bool stencil_only
= false;
2849 memset(ds
, 0, sizeof(*ds
));
2850 switch (iview
->vk_format
) {
2851 case VK_FORMAT_D24_UNORM_S8_UINT
:
2852 case VK_FORMAT_X8_D24_UNORM_PACK32
:
2853 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2854 ds
->offset_scale
= 2.0f
;
2856 case VK_FORMAT_D16_UNORM
:
2857 case VK_FORMAT_D16_UNORM_S8_UINT
:
2858 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2859 ds
->offset_scale
= 4.0f
;
2861 case VK_FORMAT_D32_SFLOAT
:
2862 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
2863 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2864 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2865 ds
->offset_scale
= 1.0f
;
2867 case VK_FORMAT_S8_UINT
:
2868 stencil_only
= true;
2874 format
= radv_translate_dbformat(iview
->vk_format
);
2875 stencil_format
= iview
->image
->surface
.flags
& RADEON_SURF_SBUFFER
?
2876 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2878 uint32_t max_slice
= radv_surface_layer_count(iview
);
2879 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
2880 S_028008_SLICE_MAX(iview
->base_layer
+ max_slice
- 1);
2882 ds
->db_htile_data_base
= 0;
2883 ds
->db_htile_surface
= 0;
2885 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2886 s_offs
= z_offs
= va
;
2889 const struct legacy_surf_level
*level_info
= &iview
->image
->surface
.u
.legacy
.level
[level
];
2892 level_info
= &iview
->image
->surface
.u
.legacy
.stencil_level
[level
];
2894 z_offs
+= iview
->image
->surface
.u
.legacy
.level
[level
].offset
;
2895 s_offs
+= iview
->image
->surface
.u
.legacy
.stencil_level
[level
].offset
;
2897 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(1);
2898 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
2899 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
2901 if (iview
->image
->info
.samples
> 1)
2902 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
2904 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
2905 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
2906 unsigned tiling_index
= iview
->image
->surface
.u
.legacy
.tiling_index
[level
];
2907 unsigned stencil_index
= iview
->image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2908 unsigned macro_index
= iview
->image
->surface
.u
.legacy
.macro_tile_index
;
2909 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
2910 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2911 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2914 tile_mode
= stencil_tile_mode
;
2916 ds
->db_depth_info
|=
2917 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2918 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2919 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2920 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2921 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2922 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2923 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2924 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2926 unsigned tile_mode_index
= si_tile_mode_index(iview
->image
, level
, false);
2927 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2928 tile_mode_index
= si_tile_mode_index(iview
->image
, level
, true);
2929 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2932 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
2933 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
2934 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
2936 if (iview
->image
->surface
.htile_size
&& !level
) {
2937 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
2939 if (!(iview
->image
->surface
.flags
& RADEON_SURF_SBUFFER
))
2940 /* Use all of the htile_buffer for depth if there's no stencil. */
2941 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2943 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
+
2944 iview
->image
->htile_offset
;
2945 ds
->db_htile_data_base
= va
>> 8;
2946 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2950 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
2951 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
2954 VkResult
radv_CreateFramebuffer(
2956 const VkFramebufferCreateInfo
* pCreateInfo
,
2957 const VkAllocationCallbacks
* pAllocator
,
2958 VkFramebuffer
* pFramebuffer
)
2960 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2961 struct radv_framebuffer
*framebuffer
;
2963 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
2965 size_t size
= sizeof(*framebuffer
) +
2966 sizeof(struct radv_attachment_info
) * pCreateInfo
->attachmentCount
;
2967 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
2968 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2969 if (framebuffer
== NULL
)
2970 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2972 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
2973 framebuffer
->width
= pCreateInfo
->width
;
2974 framebuffer
->height
= pCreateInfo
->height
;
2975 framebuffer
->layers
= pCreateInfo
->layers
;
2976 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
2977 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
2978 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
2979 framebuffer
->attachments
[i
].attachment
= iview
;
2980 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
2981 radv_initialise_color_surface(device
, &framebuffer
->attachments
[i
].cb
, iview
);
2982 } else if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
2983 radv_initialise_ds_surface(device
, &framebuffer
->attachments
[i
].ds
, iview
);
2985 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
2986 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
2987 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_layer_count(iview
));
2990 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
2994 void radv_DestroyFramebuffer(
2997 const VkAllocationCallbacks
* pAllocator
)
2999 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3000 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
3004 vk_free2(&device
->alloc
, pAllocator
, fb
);
3007 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
3009 switch (address_mode
) {
3010 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
3011 return V_008F30_SQ_TEX_WRAP
;
3012 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
3013 return V_008F30_SQ_TEX_MIRROR
;
3014 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
3015 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
3016 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
3017 return V_008F30_SQ_TEX_CLAMP_BORDER
;
3018 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
3019 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
3021 unreachable("illegal tex wrap mode");
3027 radv_tex_compare(VkCompareOp op
)
3030 case VK_COMPARE_OP_NEVER
:
3031 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
3032 case VK_COMPARE_OP_LESS
:
3033 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
3034 case VK_COMPARE_OP_EQUAL
:
3035 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
3036 case VK_COMPARE_OP_LESS_OR_EQUAL
:
3037 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
3038 case VK_COMPARE_OP_GREATER
:
3039 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
3040 case VK_COMPARE_OP_NOT_EQUAL
:
3041 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
3042 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
3043 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
3044 case VK_COMPARE_OP_ALWAYS
:
3045 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
3047 unreachable("illegal compare mode");
3053 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
3056 case VK_FILTER_NEAREST
:
3057 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
3058 V_008F38_SQ_TEX_XY_FILTER_POINT
);
3059 case VK_FILTER_LINEAR
:
3060 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
3061 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
3062 case VK_FILTER_CUBIC_IMG
:
3064 fprintf(stderr
, "illegal texture filter");
3070 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
3073 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
3074 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
3075 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
3076 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
3078 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
3083 radv_tex_bordercolor(VkBorderColor bcolor
)
3086 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
3087 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
3088 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3089 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
3090 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
3091 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
3092 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
3093 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
3094 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
3102 radv_tex_aniso_filter(unsigned filter
)
3116 radv_init_sampler(struct radv_device
*device
,
3117 struct radv_sampler
*sampler
,
3118 const VkSamplerCreateInfo
*pCreateInfo
)
3120 uint32_t max_aniso
= pCreateInfo
->anisotropyEnable
&& pCreateInfo
->maxAnisotropy
> 1.0 ?
3121 (uint32_t) pCreateInfo
->maxAnisotropy
: 0;
3122 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
3123 bool is_vi
= (device
->physical_device
->rad_info
.chip_class
>= VI
);
3125 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
3126 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
3127 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
3128 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
3129 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
3130 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
3131 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
3132 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
3133 S_008F30_DISABLE_CUBE_WRAP(0) |
3134 S_008F30_COMPAT_MODE(is_vi
));
3135 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
3136 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
3137 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
3138 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
3139 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
3140 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
3141 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
3142 S_008F38_MIP_POINT_PRECLAMP(0) |
3143 S_008F38_DISABLE_LSB_CEIL(1) |
3144 S_008F38_FILTER_PREC_FIX(1) |
3145 S_008F38_ANISO_OVERRIDE(is_vi
));
3146 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3147 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
3150 VkResult
radv_CreateSampler(
3152 const VkSamplerCreateInfo
* pCreateInfo
,
3153 const VkAllocationCallbacks
* pAllocator
,
3154 VkSampler
* pSampler
)
3156 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3157 struct radv_sampler
*sampler
;
3159 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
3161 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
3162 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3164 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
3166 radv_init_sampler(device
, sampler
, pCreateInfo
);
3167 *pSampler
= radv_sampler_to_handle(sampler
);
3172 void radv_DestroySampler(
3175 const VkAllocationCallbacks
* pAllocator
)
3177 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3178 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
3182 vk_free2(&device
->alloc
, pAllocator
, sampler
);
3185 /* vk_icd.h does not declare this function, so we declare it here to
3186 * suppress Wmissing-prototypes.
3188 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3189 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
3191 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3192 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
3194 /* For the full details on loader interface versioning, see
3195 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3196 * What follows is a condensed summary, to help you navigate the large and
3197 * confusing official doc.
3199 * - Loader interface v0 is incompatible with later versions. We don't
3202 * - In loader interface v1:
3203 * - The first ICD entrypoint called by the loader is
3204 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3206 * - The ICD must statically expose no other Vulkan symbol unless it is
3207 * linked with -Bsymbolic.
3208 * - Each dispatchable Vulkan handle created by the ICD must be
3209 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3210 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3211 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3212 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3213 * such loader-managed surfaces.
3215 * - Loader interface v2 differs from v1 in:
3216 * - The first ICD entrypoint called by the loader is
3217 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3218 * statically expose this entrypoint.
3220 * - Loader interface v3 differs from v2 in:
3221 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3222 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3223 * because the loader no longer does so.
3225 *pSupportedVersion
= MIN2(*pSupportedVersion
, 3u);
3229 VkResult
radv_GetMemoryFdKHX(VkDevice _device
,
3230 VkDeviceMemory _memory
,
3231 VkExternalMemoryHandleTypeFlagsKHX handleType
,
3234 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3235 RADV_FROM_HANDLE(radv_device_memory
, memory
, _memory
);
3237 /* We support only one handle type. */
3238 assert(handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHX
);
3240 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
3242 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
3246 VkResult
radv_GetMemoryFdPropertiesKHX(VkDevice _device
,
3247 VkExternalMemoryHandleTypeFlagBitsKHX handleType
,
3249 VkMemoryFdPropertiesKHX
*pMemoryFdProperties
)
3251 /* The valid usage section for this function says:
3253 * "handleType must not be one of the handle types defined as opaque."
3255 * Since we only handle opaque handles for now, there are no FD properties.
3257 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHX
;