projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: drop the return type for radv_queue_init()
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <dlfcn.h>
29 #include <stdbool.h>
30 #include <string.h>
31 #include <unistd.h>
32 #include <fcntl.h>
33 #include <sys/stat.h>
34 #include "radv_private.h"
35 #include "util/strtod.h"
36
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "util/debug.h"
46 struct radv_dispatch_table dtable;
47
48 static int
49 radv_get_function_timestamp(void *ptr, uint32_t* timestamp)
50 {
51 Dl_info info;
52 struct stat st;
53 if (!dladdr(ptr, &info) || !info.dli_fname) {
54 return -1;
55 }
56 if (stat(info.dli_fname, &st)) {
57 return -1;
58 }
59 *timestamp = st.st_mtim.tv_sec;
60 return 0;
61 }
62
63 static int
64 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
65 {
66 uint32_t mesa_timestamp, llvm_timestamp;
67 uint16_t f = family;
68 memset(uuid, 0, VK_UUID_SIZE);
69 if (radv_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
70 radv_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
71 return -1;
72
73 memcpy(uuid, &mesa_timestamp, 4);
74 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
75 memcpy((char*)uuid + 8, &f, 2);
76 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
77 return 0;
78 }
79
80 static VkResult
81 radv_physical_device_init(struct radv_physical_device *device,
82 struct radv_instance *instance,
83 const char *path)
84 {
85 VkResult result;
86 drmVersionPtr version;
87 int fd;
88
89 fd = open(path, O_RDWR | O_CLOEXEC);
90 if (fd < 0)
91 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
92 "failed to open %s: %m", path);
93
94 version = drmGetVersion(fd);
95 if (!version) {
96 close(fd);
97 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
98 "failed to get version %s: %m", path);
99 }
100
101 if (strcmp(version->name, "amdgpu")) {
102 drmFreeVersion(version);
103 close(fd);
104 return VK_ERROR_INCOMPATIBLE_DRIVER;
105 }
106 drmFreeVersion(version);
107
108 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
109 device->instance = instance;
110 assert(strlen(path) < ARRAY_SIZE(device->path));
111 strncpy(device->path, path, ARRAY_SIZE(device->path));
112
113 device->ws = radv_amdgpu_winsys_create(fd);
114 if (!device->ws) {
115 result = VK_ERROR_INCOMPATIBLE_DRIVER;
116 goto fail;
117 }
118 device->ws->query_info(device->ws, &device->rad_info);
119 result = radv_init_wsi(device);
120 if (result != VK_SUCCESS) {
121 device->ws->destroy(device->ws);
122 goto fail;
123 }
124
125 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
126 radv_finish_wsi(device);
127 device->ws->destroy(device->ws);
128 goto fail;
129 }
130
131 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
132 device->name = device->rad_info.name;
133 return VK_SUCCESS;
134
135 fail:
136 close(fd);
137 return result;
138 }
139
140 static void
141 radv_physical_device_finish(struct radv_physical_device *device)
142 {
143 radv_finish_wsi(device);
144 device->ws->destroy(device->ws);
145 }
146
147 static const VkExtensionProperties global_extensions[] = {
148 {
149 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
150 .specVersion = 25,
151 },
152 #ifdef VK_USE_PLATFORM_XCB_KHR
153 {
154 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
155 .specVersion = 6,
156 },
157 #endif
158 #ifdef VK_USE_PLATFORM_XLIB_KHR
159 {
160 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
161 .specVersion = 6,
162 },
163 #endif
164 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
165 {
166 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
167 .specVersion = 5,
168 },
169 #endif
170 };
171
172 static const VkExtensionProperties device_extensions[] = {
173 {
174 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
175 .specVersion = 1,
176 },
177 {
178 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
179 .specVersion = 68,
180 },
181 {
182 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
183 .specVersion = 1,
184 },
185 {
186 .extensionName = VK_AMD_NEGATIVE_VIEWPORT_HEIGHT_EXTENSION_NAME,
187 .specVersion = 1,
188 },
189 };
190
191 static void *
192 default_alloc_func(void *pUserData, size_t size, size_t align,
193 VkSystemAllocationScope allocationScope)
194 {
195 return malloc(size);
196 }
197
198 static void *
199 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
200 size_t align, VkSystemAllocationScope allocationScope)
201 {
202 return realloc(pOriginal, size);
203 }
204
205 static void
206 default_free_func(void *pUserData, void *pMemory)
207 {
208 free(pMemory);
209 }
210
211 static const VkAllocationCallbacks default_alloc = {
212 .pUserData = NULL,
213 .pfnAllocation = default_alloc_func,
214 .pfnReallocation = default_realloc_func,
215 .pfnFree = default_free_func,
216 };
217
218 VkResult radv_CreateInstance(
219 const VkInstanceCreateInfo* pCreateInfo,
220 const VkAllocationCallbacks* pAllocator,
221 VkInstance* pInstance)
222 {
223 struct radv_instance *instance;
224
225 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
226
227 uint32_t client_version;
228 if (pCreateInfo->pApplicationInfo &&
229 pCreateInfo->pApplicationInfo->apiVersion != 0) {
230 client_version = pCreateInfo->pApplicationInfo->apiVersion;
231 } else {
232 client_version = VK_MAKE_VERSION(1, 0, 0);
233 }
234
235 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
236 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
237 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
238 "Client requested version %d.%d.%d",
239 VK_VERSION_MAJOR(client_version),
240 VK_VERSION_MINOR(client_version),
241 VK_VERSION_PATCH(client_version));
242 }
243
244 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
245 bool found = false;
246 for (uint32_t j = 0; j < ARRAY_SIZE(global_extensions); j++) {
247 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
248 global_extensions[j].extensionName) == 0) {
249 found = true;
250 break;
251 }
252 }
253 if (!found)
254 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
255 }
256
257 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
258 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
259 if (!instance)
260 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
261
262 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
263
264 if (pAllocator)
265 instance->alloc = *pAllocator;
266 else
267 instance->alloc = default_alloc;
268
269 instance->apiVersion = client_version;
270 instance->physicalDeviceCount = -1;
271
272 _mesa_locale_init();
273
274 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
275
276 *pInstance = radv_instance_to_handle(instance);
277
278 return VK_SUCCESS;
279 }
280
281 void radv_DestroyInstance(
282 VkInstance _instance,
283 const VkAllocationCallbacks* pAllocator)
284 {
285 RADV_FROM_HANDLE(radv_instance, instance, _instance);
286
287 if (instance->physicalDeviceCount > 0) {
288 /* We support at most one physical device. */
289 assert(instance->physicalDeviceCount == 1);
290 radv_physical_device_finish(&instance->physicalDevice);
291 }
292
293 VG(VALGRIND_DESTROY_MEMPOOL(instance));
294
295 _mesa_locale_fini();
296
297 vk_free(&instance->alloc, instance);
298 }
299
300 VkResult radv_EnumeratePhysicalDevices(
301 VkInstance _instance,
302 uint32_t* pPhysicalDeviceCount,
303 VkPhysicalDevice* pPhysicalDevices)
304 {
305 RADV_FROM_HANDLE(radv_instance, instance, _instance);
306 VkResult result;
307
308 if (instance->physicalDeviceCount < 0) {
309 char path[20];
310 for (unsigned i = 0; i < 8; i++) {
311 snprintf(path, sizeof(path), "/dev/dri/renderD%d", 128 + i);
312 result = radv_physical_device_init(&instance->physicalDevice,
313 instance, path);
314 if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
315 break;
316 }
317
318 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
319 instance->physicalDeviceCount = 0;
320 } else if (result == VK_SUCCESS) {
321 instance->physicalDeviceCount = 1;
322 } else {
323 return result;
324 }
325 }
326
327 /* pPhysicalDeviceCount is an out parameter if pPhysicalDevices is NULL;
328 * otherwise it's an inout parameter.
329 *
330 * The Vulkan spec (git aaed022) says:
331 *
332 * pPhysicalDeviceCount is a pointer to an unsigned integer variable
333 * that is initialized with the number of devices the application is
334 * prepared to receive handles to. pname:pPhysicalDevices is pointer to
335 * an array of at least this many VkPhysicalDevice handles [...].
336 *
337 * Upon success, if pPhysicalDevices is NULL, vkEnumeratePhysicalDevices
338 * overwrites the contents of the variable pointed to by
339 * pPhysicalDeviceCount with the number of physical devices in in the
340 * instance; otherwise, vkEnumeratePhysicalDevices overwrites
341 * pPhysicalDeviceCount with the number of physical handles written to
342 * pPhysicalDevices.
343 */
344 if (!pPhysicalDevices) {
345 *pPhysicalDeviceCount = instance->physicalDeviceCount;
346 } else if (*pPhysicalDeviceCount >= 1) {
347 pPhysicalDevices[0] = radv_physical_device_to_handle(&instance->physicalDevice);
348 *pPhysicalDeviceCount = 1;
349 } else if (*pPhysicalDeviceCount < instance->physicalDeviceCount) {
350 return VK_INCOMPLETE;
351 } else {
352 *pPhysicalDeviceCount = 0;
353 }
354
355 return VK_SUCCESS;
356 }
357
358 void radv_GetPhysicalDeviceFeatures(
359 VkPhysicalDevice physicalDevice,
360 VkPhysicalDeviceFeatures* pFeatures)
361 {
362 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
363
364 memset(pFeatures, 0, sizeof(*pFeatures));
365
366 *pFeatures = (VkPhysicalDeviceFeatures) {
367 .robustBufferAccess = true,
368 .fullDrawIndexUint32 = true,
369 .imageCubeArray = true,
370 .independentBlend = true,
371 .geometryShader = false,
372 .tessellationShader = false,
373 .sampleRateShading = false,
374 .dualSrcBlend = true,
375 .logicOp = true,
376 .multiDrawIndirect = true,
377 .drawIndirectFirstInstance = true,
378 .depthClamp = true,
379 .depthBiasClamp = true,
380 .fillModeNonSolid = true,
381 .depthBounds = true,
382 .wideLines = true,
383 .largePoints = true,
384 .alphaToOne = true,
385 .multiViewport = false,
386 .samplerAnisotropy = true,
387 .textureCompressionETC2 = false,
388 .textureCompressionASTC_LDR = false,
389 .textureCompressionBC = true,
390 .occlusionQueryPrecise = true,
391 .pipelineStatisticsQuery = false,
392 .vertexPipelineStoresAndAtomics = true,
393 .fragmentStoresAndAtomics = true,
394 .shaderTessellationAndGeometryPointSize = true,
395 .shaderImageGatherExtended = false,
396 .shaderStorageImageExtendedFormats = false,
397 .shaderStorageImageMultisample = false,
398 .shaderUniformBufferArrayDynamicIndexing = true,
399 .shaderSampledImageArrayDynamicIndexing = true,
400 .shaderStorageBufferArrayDynamicIndexing = true,
401 .shaderStorageImageArrayDynamicIndexing = true,
402 .shaderStorageImageReadWithoutFormat = false,
403 .shaderStorageImageWriteWithoutFormat = true,
404 .shaderClipDistance = true,
405 .shaderCullDistance = true,
406 .shaderFloat64 = false,
407 .shaderInt64 = false,
408 .shaderInt16 = false,
409 .alphaToOne = true,
410 .variableMultisampleRate = false,
411 .inheritedQueries = false,
412 };
413 }
414
415 void radv_GetPhysicalDeviceProperties(
416 VkPhysicalDevice physicalDevice,
417 VkPhysicalDeviceProperties* pProperties)
418 {
419 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
420 VkSampleCountFlags sample_counts = 0xf;
421 VkPhysicalDeviceLimits limits = {
422 .maxImageDimension1D = (1 << 14),
423 .maxImageDimension2D = (1 << 14),
424 .maxImageDimension3D = (1 << 11),
425 .maxImageDimensionCube = (1 << 14),
426 .maxImageArrayLayers = (1 << 11),
427 .maxTexelBufferElements = 128 * 1024 * 1024,
428 .maxUniformBufferRange = UINT32_MAX,
429 .maxStorageBufferRange = UINT32_MAX,
430 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
431 .maxMemoryAllocationCount = UINT32_MAX,
432 .maxSamplerAllocationCount = 64 * 1024,
433 .bufferImageGranularity = 64, /* A cache line */
434 .sparseAddressSpaceSize = 0,
435 .maxBoundDescriptorSets = MAX_SETS,
436 .maxPerStageDescriptorSamplers = 64,
437 .maxPerStageDescriptorUniformBuffers = 64,
438 .maxPerStageDescriptorStorageBuffers = 64,
439 .maxPerStageDescriptorSampledImages = 64,
440 .maxPerStageDescriptorStorageImages = 64,
441 .maxPerStageDescriptorInputAttachments = 64,
442 .maxPerStageResources = 128,
443 .maxDescriptorSetSamplers = 256,
444 .maxDescriptorSetUniformBuffers = 256,
445 .maxDescriptorSetUniformBuffersDynamic = 256,
446 .maxDescriptorSetStorageBuffers = 256,
447 .maxDescriptorSetStorageBuffersDynamic = 256,
448 .maxDescriptorSetSampledImages = 256,
449 .maxDescriptorSetStorageImages = 256,
450 .maxDescriptorSetInputAttachments = 256,
451 .maxVertexInputAttributes = 32,
452 .maxVertexInputBindings = 32,
453 .maxVertexInputAttributeOffset = 2047,
454 .maxVertexInputBindingStride = 2048,
455 .maxVertexOutputComponents = 128,
456 .maxTessellationGenerationLevel = 0,
457 .maxTessellationPatchSize = 0,
458 .maxTessellationControlPerVertexInputComponents = 0,
459 .maxTessellationControlPerVertexOutputComponents = 0,
460 .maxTessellationControlPerPatchOutputComponents = 0,
461 .maxTessellationControlTotalOutputComponents = 0,
462 .maxTessellationEvaluationInputComponents = 0,
463 .maxTessellationEvaluationOutputComponents = 0,
464 .maxGeometryShaderInvocations = 32,
465 .maxGeometryInputComponents = 64,
466 .maxGeometryOutputComponents = 128,
467 .maxGeometryOutputVertices = 256,
468 .maxGeometryTotalOutputComponents = 1024,
469 .maxFragmentInputComponents = 128,
470 .maxFragmentOutputAttachments = 8,
471 .maxFragmentDualSrcAttachments = 2,
472 .maxFragmentCombinedOutputResources = 8,
473 .maxComputeSharedMemorySize = 32768,
474 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
475 .maxComputeWorkGroupInvocations = 16 * 1024,
476 .maxComputeWorkGroupSize = {
477 16 * 1024/*devinfo->max_cs_threads*/,
478 16 * 1024,
479 16 * 1024
480 },
481 .subPixelPrecisionBits = 4 /* FIXME */,
482 .subTexelPrecisionBits = 4 /* FIXME */,
483 .mipmapPrecisionBits = 4 /* FIXME */,
484 .maxDrawIndexedIndexValue = UINT32_MAX,
485 .maxDrawIndirectCount = UINT32_MAX,
486 .maxSamplerLodBias = 16,
487 .maxSamplerAnisotropy = 16,
488 .maxViewports = MAX_VIEWPORTS,
489 .maxViewportDimensions = { (1 << 14), (1 << 14) },
490 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
491 .viewportSubPixelBits = 13, /* We take a float? */
492 .minMemoryMapAlignment = 4096, /* A page */
493 .minTexelBufferOffsetAlignment = 1,
494 .minUniformBufferOffsetAlignment = 4,
495 .minStorageBufferOffsetAlignment = 4,
496 .minTexelOffset = -8,
497 .maxTexelOffset = 7,
498 .minTexelGatherOffset = -8,
499 .maxTexelGatherOffset = 7,
500 .minInterpolationOffset = 0, /* FIXME */
501 .maxInterpolationOffset = 0, /* FIXME */
502 .subPixelInterpolationOffsetBits = 0, /* FIXME */
503 .maxFramebufferWidth = (1 << 14),
504 .maxFramebufferHeight = (1 << 14),
505 .maxFramebufferLayers = (1 << 10),
506 .framebufferColorSampleCounts = sample_counts,
507 .framebufferDepthSampleCounts = sample_counts,
508 .framebufferStencilSampleCounts = sample_counts,
509 .framebufferNoAttachmentsSampleCounts = sample_counts,
510 .maxColorAttachments = MAX_RTS,
511 .sampledImageColorSampleCounts = sample_counts,
512 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
513 .sampledImageDepthSampleCounts = sample_counts,
514 .sampledImageStencilSampleCounts = sample_counts,
515 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
516 .maxSampleMaskWords = 1,
517 .timestampComputeAndGraphics = false,
518 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
519 .maxClipDistances = 8,
520 .maxCullDistances = 8,
521 .maxCombinedClipAndCullDistances = 8,
522 .discreteQueuePriorities = 1,
523 .pointSizeRange = { 0.125, 255.875 },
524 .lineWidthRange = { 0.0, 7.9921875 },
525 .pointSizeGranularity = (1.0 / 8.0),
526 .lineWidthGranularity = (1.0 / 128.0),
527 .strictLines = false, /* FINISHME */
528 .standardSampleLocations = true,
529 .optimalBufferCopyOffsetAlignment = 128,
530 .optimalBufferCopyRowPitchAlignment = 128,
531 .nonCoherentAtomSize = 64,
532 };
533
534 *pProperties = (VkPhysicalDeviceProperties) {
535 .apiVersion = VK_MAKE_VERSION(1, 0, 5),
536 .driverVersion = 1,
537 .vendorID = 0x1002,
538 .deviceID = pdevice->rad_info.pci_id,
539 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
540 .limits = limits,
541 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
542 };
543
544 strcpy(pProperties->deviceName, pdevice->name);
545 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
546 }
547
548 void radv_GetPhysicalDeviceQueueFamilyProperties(
549 VkPhysicalDevice physicalDevice,
550 uint32_t* pCount,
551 VkQueueFamilyProperties* pQueueFamilyProperties)
552 {
553 if (pQueueFamilyProperties == NULL) {
554 *pCount = 1;
555 return;
556 }
557 assert(*pCount >= 1);
558
559 *pQueueFamilyProperties = (VkQueueFamilyProperties) {
560 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
561 VK_QUEUE_COMPUTE_BIT |
562 VK_QUEUE_TRANSFER_BIT,
563 .queueCount = 1,
564 .timestampValidBits = 64,
565 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
566 };
567 }
568
569 void radv_GetPhysicalDeviceMemoryProperties(
570 VkPhysicalDevice physicalDevice,
571 VkPhysicalDeviceMemoryProperties* pMemoryProperties)
572 {
573 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
574
575 pMemoryProperties->memoryTypeCount = 4;
576 pMemoryProperties->memoryTypes[0] = (VkMemoryType) {
577 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
578 .heapIndex = 0,
579 };
580 pMemoryProperties->memoryTypes[1] = (VkMemoryType) {
581 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
582 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
583 .heapIndex = 2,
584 };
585 pMemoryProperties->memoryTypes[2] = (VkMemoryType) {
586 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
587 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
588 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
589 .heapIndex = 1,
590 };
591 pMemoryProperties->memoryTypes[3] = (VkMemoryType) {
592 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
593 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
594 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
595 .heapIndex = 2,
596 };
597
598 pMemoryProperties->memoryHeapCount = 3;
599 pMemoryProperties->memoryHeaps[0] = (VkMemoryHeap) {
600 .size = physical_device->rad_info.vram_size -
601 physical_device->rad_info.visible_vram_size,
602 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
603 };
604 pMemoryProperties->memoryHeaps[1] = (VkMemoryHeap) {
605 .size = physical_device->rad_info.visible_vram_size,
606 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
607 };
608 pMemoryProperties->memoryHeaps[2] = (VkMemoryHeap) {
609 .size = physical_device->rad_info.gart_size,
610 .flags = 0,
611 };
612 }
613
614 static void
615 radv_queue_init(struct radv_device *device, struct radv_queue *queue)
616 {
617 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
618 queue->device = device;
619 }
620
621 static void
622 radv_queue_finish(struct radv_queue *queue)
623 {
624 }
625
626 VkResult radv_CreateDevice(
627 VkPhysicalDevice physicalDevice,
628 const VkDeviceCreateInfo* pCreateInfo,
629 const VkAllocationCallbacks* pAllocator,
630 VkDevice* pDevice)
631 {
632 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
633 VkResult result;
634 struct radv_device *device;
635
636 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
637 bool found = false;
638 for (uint32_t j = 0; j < ARRAY_SIZE(device_extensions); j++) {
639 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
640 device_extensions[j].extensionName) == 0) {
641 found = true;
642 break;
643 }
644 }
645 if (!found)
646 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
647 }
648
649 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
650 sizeof(*device), 8,
651 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
652 if (!device)
653 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
654
655 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
656 device->instance = physical_device->instance;
657
658 device->ws = physical_device->ws;
659 if (pAllocator)
660 device->alloc = *pAllocator;
661 else
662 device->alloc = physical_device->instance->alloc;
663
664 device->hw_ctx = device->ws->ctx_create(device->ws);
665 if (!device->hw_ctx) {
666 result = VK_ERROR_OUT_OF_HOST_MEMORY;
667 goto fail_free;
668 }
669
670 radv_queue_init(device, &device->queue);
671
672 result = radv_device_init_meta(device);
673 if (result != VK_SUCCESS) {
674 device->ws->ctx_destroy(device->hw_ctx);
675 goto fail_free;
676 }
677 device->allow_fast_clears = env_var_as_boolean("RADV_FAST_CLEARS", false);
678 device->allow_dcc = !env_var_as_boolean("RADV_DCC_DISABLE", false);
679 device->shader_stats_dump = env_var_as_boolean("RADV_SHADER_STATS", false);
680
681 if (device->allow_fast_clears && device->allow_dcc)
682 radv_finishme("DCC fast clears have not been tested\n");
683
684 radv_device_init_msaa(device);
685 device->empty_cs = device->ws->cs_create(device->ws, RING_GFX);
686 radeon_emit(device->empty_cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
687 radeon_emit(device->empty_cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
688 radeon_emit(device->empty_cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
689 device->ws->cs_finalize(device->empty_cs);
690 *pDevice = radv_device_to_handle(device);
691 return VK_SUCCESS;
692 fail_free:
693 vk_free(&device->alloc, device);
694 return result;
695 }
696
697 void radv_DestroyDevice(
698 VkDevice _device,
699 const VkAllocationCallbacks* pAllocator)
700 {
701 RADV_FROM_HANDLE(radv_device, device, _device);
702
703 device->ws->ctx_destroy(device->hw_ctx);
704 radv_queue_finish(&device->queue);
705 radv_device_finish_meta(device);
706
707 vk_free(&device->alloc, device);
708 }
709
710 VkResult radv_EnumerateInstanceExtensionProperties(
711 const char* pLayerName,
712 uint32_t* pPropertyCount,
713 VkExtensionProperties* pProperties)
714 {
715 unsigned i;
716 if (pProperties == NULL) {
717 *pPropertyCount = ARRAY_SIZE(global_extensions);
718 return VK_SUCCESS;
719 }
720
721 for (i = 0; i < *pPropertyCount; i++)
722 memcpy(&pProperties[i], &global_extensions[i], sizeof(VkExtensionProperties));
723
724 *pPropertyCount = i;
725 if (i < ARRAY_SIZE(global_extensions))
726 return VK_INCOMPLETE;
727
728 return VK_SUCCESS;
729 }
730
731 VkResult radv_EnumerateDeviceExtensionProperties(
732 VkPhysicalDevice physicalDevice,
733 const char* pLayerName,
734 uint32_t* pPropertyCount,
735 VkExtensionProperties* pProperties)
736 {
737 unsigned i;
738
739 if (pProperties == NULL) {
740 *pPropertyCount = ARRAY_SIZE(device_extensions);
741 return VK_SUCCESS;
742 }
743
744 for (i = 0; i < *pPropertyCount; i++)
745 memcpy(&pProperties[i], &device_extensions[i], sizeof(VkExtensionProperties));
746
747 *pPropertyCount = i;
748 if (i < ARRAY_SIZE(device_extensions))
749 return VK_INCOMPLETE;
750 return VK_SUCCESS;
751 }
752
753 VkResult radv_EnumerateInstanceLayerProperties(
754 uint32_t* pPropertyCount,
755 VkLayerProperties* pProperties)
756 {
757 if (pProperties == NULL) {
758 *pPropertyCount = 0;
759 return VK_SUCCESS;
760 }
761
762 /* None supported at this time */
763 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
764 }
765
766 VkResult radv_EnumerateDeviceLayerProperties(
767 VkPhysicalDevice physicalDevice,
768 uint32_t* pPropertyCount,
769 VkLayerProperties* pProperties)
770 {
771 if (pProperties == NULL) {
772 *pPropertyCount = 0;
773 return VK_SUCCESS;
774 }
775
776 /* None supported at this time */
777 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
778 }
779
780 void radv_GetDeviceQueue(
781 VkDevice _device,
782 uint32_t queueNodeIndex,
783 uint32_t queueIndex,
784 VkQueue* pQueue)
785 {
786 RADV_FROM_HANDLE(radv_device, device, _device);
787
788 assert(queueIndex == 0);
789
790 *pQueue = radv_queue_to_handle(&device->queue);
791 }
792
793 VkResult radv_QueueSubmit(
794 VkQueue _queue,
795 uint32_t submitCount,
796 const VkSubmitInfo* pSubmits,
797 VkFence _fence)
798 {
799 RADV_FROM_HANDLE(radv_queue, queue, _queue);
800 RADV_FROM_HANDLE(radv_fence, fence, _fence);
801 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
802 struct radeon_winsys_ctx *ctx = queue->device->hw_ctx;
803 int ret;
804
805 for (uint32_t i = 0; i < submitCount; i++) {
806 struct radeon_winsys_cs **cs_array;
807 bool can_patch = true;
808
809 if (!pSubmits[i].commandBufferCount)
810 continue;
811
812 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
813 pSubmits[i].commandBufferCount);
814
815 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
816 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
817 pSubmits[i].pCommandBuffers[j]);
818 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
819
820 cs_array[j] = cmd_buffer->cs;
821 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
822 can_patch = false;
823 }
824 ret = queue->device->ws->cs_submit(ctx, cs_array,
825 pSubmits[i].commandBufferCount,
826 can_patch, base_fence);
827 if (ret)
828 radv_loge("failed to submit CS %d\n", i);
829 free(cs_array);
830 }
831
832 if (fence) {
833 if (!submitCount)
834 ret = queue->device->ws->cs_submit(ctx, &queue->device->empty_cs,
835 1, false, base_fence);
836
837 fence->submitted = true;
838 }
839
840 return VK_SUCCESS;
841 }
842
843 VkResult radv_QueueWaitIdle(
844 VkQueue _queue)
845 {
846 RADV_FROM_HANDLE(radv_queue, queue, _queue);
847
848 queue->device->ws->ctx_wait_idle(queue->device->hw_ctx);
849 return VK_SUCCESS;
850 }
851
852 VkResult radv_DeviceWaitIdle(
853 VkDevice _device)
854 {
855 RADV_FROM_HANDLE(radv_device, device, _device);
856
857 device->ws->ctx_wait_idle(device->hw_ctx);
858 return VK_SUCCESS;
859 }
860
861 PFN_vkVoidFunction radv_GetInstanceProcAddr(
862 VkInstance instance,
863 const char* pName)
864 {
865 return radv_lookup_entrypoint(pName);
866 }
867
868 /* The loader wants us to expose a second GetInstanceProcAddr function
869 * to work around certain LD_PRELOAD issues seen in apps.
870 */
871 PUBLIC
872 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
873 VkInstance instance,
874 const char* pName);
875
876 PUBLIC
877 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
878 VkInstance instance,
879 const char* pName)
880 {
881 return radv_GetInstanceProcAddr(instance, pName);
882 }
883
884 PFN_vkVoidFunction radv_GetDeviceProcAddr(
885 VkDevice device,
886 const char* pName)
887 {
888 return radv_lookup_entrypoint(pName);
889 }
890
891 VkResult radv_AllocateMemory(
892 VkDevice _device,
893 const VkMemoryAllocateInfo* pAllocateInfo,
894 const VkAllocationCallbacks* pAllocator,
895 VkDeviceMemory* pMem)
896 {
897 RADV_FROM_HANDLE(radv_device, device, _device);
898 struct radv_device_memory *mem;
899 VkResult result;
900 enum radeon_bo_domain domain;
901 uint32_t flags = 0;
902 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
903
904 if (pAllocateInfo->allocationSize == 0) {
905 /* Apparently, this is allowed */
906 *pMem = VK_NULL_HANDLE;
907 return VK_SUCCESS;
908 }
909
910 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
911 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
912 if (mem == NULL)
913 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
914
915 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
916 if (pAllocateInfo->memoryTypeIndex == 1 || pAllocateInfo->memoryTypeIndex == 3)
917 domain = RADEON_DOMAIN_GTT;
918 else
919 domain = RADEON_DOMAIN_VRAM;
920
921 if (pAllocateInfo->memoryTypeIndex == 0)
922 flags |= RADEON_FLAG_NO_CPU_ACCESS;
923 else
924 flags |= RADEON_FLAG_CPU_ACCESS;
925
926 if (pAllocateInfo->memoryTypeIndex == 1)
927 flags |= RADEON_FLAG_GTT_WC;
928
929 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 32768,
930 domain, flags);
931
932 if (!mem->bo) {
933 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
934 goto fail;
935 }
936 mem->type_index = pAllocateInfo->memoryTypeIndex;
937
938 *pMem = radv_device_memory_to_handle(mem);
939
940 return VK_SUCCESS;
941
942 fail:
943 vk_free2(&device->alloc, pAllocator, mem);
944
945 return result;
946 }
947
948 void radv_FreeMemory(
949 VkDevice _device,
950 VkDeviceMemory _mem,
951 const VkAllocationCallbacks* pAllocator)
952 {
953 RADV_FROM_HANDLE(radv_device, device, _device);
954 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
955
956 if (mem == NULL)
957 return;
958
959 device->ws->buffer_destroy(mem->bo);
960 mem->bo = NULL;
961
962 vk_free2(&device->alloc, pAllocator, mem);
963 }
964
965 VkResult radv_MapMemory(
966 VkDevice _device,
967 VkDeviceMemory _memory,
968 VkDeviceSize offset,
969 VkDeviceSize size,
970 VkMemoryMapFlags flags,
971 void** ppData)
972 {
973 RADV_FROM_HANDLE(radv_device, device, _device);
974 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
975
976 if (mem == NULL) {
977 *ppData = NULL;
978 return VK_SUCCESS;
979 }
980
981 *ppData = device->ws->buffer_map(mem->bo);
982 if (*ppData) {
983 *ppData += offset;
984 return VK_SUCCESS;
985 }
986
987 return VK_ERROR_MEMORY_MAP_FAILED;
988 }
989
990 void radv_UnmapMemory(
991 VkDevice _device,
992 VkDeviceMemory _memory)
993 {
994 RADV_FROM_HANDLE(radv_device, device, _device);
995 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
996
997 if (mem == NULL)
998 return;
999
1000 device->ws->buffer_unmap(mem->bo);
1001 }
1002
1003 VkResult radv_FlushMappedMemoryRanges(
1004 VkDevice _device,
1005 uint32_t memoryRangeCount,
1006 const VkMappedMemoryRange* pMemoryRanges)
1007 {
1008 return VK_SUCCESS;
1009 }
1010
1011 VkResult radv_InvalidateMappedMemoryRanges(
1012 VkDevice _device,
1013 uint32_t memoryRangeCount,
1014 const VkMappedMemoryRange* pMemoryRanges)
1015 {
1016 return VK_SUCCESS;
1017 }
1018
1019 void radv_GetBufferMemoryRequirements(
1020 VkDevice device,
1021 VkBuffer _buffer,
1022 VkMemoryRequirements* pMemoryRequirements)
1023 {
1024 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1025
1026 /* The Vulkan spec (git aaed022) says:
1027 *
1028 * memoryTypeBits is a bitfield and contains one bit set for every
1029 * supported memory type for the resource. The bit `1<<i` is set if and
1030 * only if the memory type `i` in the VkPhysicalDeviceMemoryProperties
1031 * structure for the physical device is supported.
1032 *
1033 * We support exactly one memory type.
1034 */
1035 pMemoryRequirements->memoryTypeBits = 0x7;
1036
1037 pMemoryRequirements->size = buffer->size;
1038 pMemoryRequirements->alignment = 16;
1039 }
1040
1041 void radv_GetImageMemoryRequirements(
1042 VkDevice device,
1043 VkImage _image,
1044 VkMemoryRequirements* pMemoryRequirements)
1045 {
1046 RADV_FROM_HANDLE(radv_image, image, _image);
1047
1048 /* The Vulkan spec (git aaed022) says:
1049 *
1050 * memoryTypeBits is a bitfield and contains one bit set for every
1051 * supported memory type for the resource. The bit `1<<i` is set if and
1052 * only if the memory type `i` in the VkPhysicalDeviceMemoryProperties
1053 * structure for the physical device is supported.
1054 *
1055 * We support exactly one memory type.
1056 */
1057 pMemoryRequirements->memoryTypeBits = 0x7;
1058
1059 pMemoryRequirements->size = image->size;
1060 pMemoryRequirements->alignment = image->alignment;
1061 }
1062
1063 void radv_GetImageSparseMemoryRequirements(
1064 VkDevice device,
1065 VkImage image,
1066 uint32_t* pSparseMemoryRequirementCount,
1067 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
1068 {
1069 stub();
1070 }
1071
1072 void radv_GetDeviceMemoryCommitment(
1073 VkDevice device,
1074 VkDeviceMemory memory,
1075 VkDeviceSize* pCommittedMemoryInBytes)
1076 {
1077 *pCommittedMemoryInBytes = 0;
1078 }
1079
1080 VkResult radv_BindBufferMemory(
1081 VkDevice device,
1082 VkBuffer _buffer,
1083 VkDeviceMemory _memory,
1084 VkDeviceSize memoryOffset)
1085 {
1086 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1087 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1088
1089 if (mem) {
1090 buffer->bo = mem->bo;
1091 buffer->offset = memoryOffset;
1092 } else {
1093 buffer->bo = NULL;
1094 buffer->offset = 0;
1095 }
1096
1097 return VK_SUCCESS;
1098 }
1099
1100 VkResult radv_BindImageMemory(
1101 VkDevice device,
1102 VkImage _image,
1103 VkDeviceMemory _memory,
1104 VkDeviceSize memoryOffset)
1105 {
1106 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1107 RADV_FROM_HANDLE(radv_image, image, _image);
1108
1109 if (mem) {
1110 image->bo = mem->bo;
1111 image->offset = memoryOffset;
1112 } else {
1113 image->bo = NULL;
1114 image->offset = 0;
1115 }
1116
1117 return VK_SUCCESS;
1118 }
1119
1120 VkResult radv_QueueBindSparse(
1121 VkQueue queue,
1122 uint32_t bindInfoCount,
1123 const VkBindSparseInfo* pBindInfo,
1124 VkFence fence)
1125 {
1126 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER);
1127 }
1128
1129 VkResult radv_CreateFence(
1130 VkDevice _device,
1131 const VkFenceCreateInfo* pCreateInfo,
1132 const VkAllocationCallbacks* pAllocator,
1133 VkFence* pFence)
1134 {
1135 RADV_FROM_HANDLE(radv_device, device, _device);
1136 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
1137 sizeof(*fence), 8,
1138 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1139
1140 if (!fence)
1141 return VK_ERROR_OUT_OF_HOST_MEMORY;
1142
1143 memset(fence, 0, sizeof(*fence));
1144 fence->submitted = false;
1145 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
1146 fence->fence = device->ws->create_fence();
1147
1148
1149 *pFence = radv_fence_to_handle(fence);
1150
1151 return VK_SUCCESS;
1152 }
1153
1154 void radv_DestroyFence(
1155 VkDevice _device,
1156 VkFence _fence,
1157 const VkAllocationCallbacks* pAllocator)
1158 {
1159 RADV_FROM_HANDLE(radv_device, device, _device);
1160 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1161
1162 if (!fence)
1163 return;
1164 device->ws->destroy_fence(fence->fence);
1165 vk_free2(&device->alloc, pAllocator, fence);
1166 }
1167
1168 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
1169 {
1170 uint64_t current_time;
1171 struct timespec tv;
1172
1173 clock_gettime(CLOCK_MONOTONIC, &tv);
1174 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
1175
1176 timeout = MIN2(UINT64_MAX - current_time, timeout);
1177
1178 return current_time + timeout;
1179 }
1180
1181 VkResult radv_WaitForFences(
1182 VkDevice _device,
1183 uint32_t fenceCount,
1184 const VkFence* pFences,
1185 VkBool32 waitAll,
1186 uint64_t timeout)
1187 {
1188 RADV_FROM_HANDLE(radv_device, device, _device);
1189 timeout = radv_get_absolute_timeout(timeout);
1190
1191 if (!waitAll && fenceCount > 1) {
1192 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
1193 }
1194
1195 for (uint32_t i = 0; i < fenceCount; ++i) {
1196 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1197 bool expired = false;
1198
1199 if (fence->signalled)
1200 continue;
1201
1202 if (!fence->submitted)
1203 return VK_TIMEOUT;
1204
1205 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
1206 if (!expired)
1207 return VK_TIMEOUT;
1208
1209 fence->signalled = true;
1210 }
1211
1212 return VK_SUCCESS;
1213 }
1214
1215 VkResult radv_ResetFences(VkDevice device,
1216 uint32_t fenceCount,
1217 const VkFence *pFences)
1218 {
1219 for (unsigned i = 0; i < fenceCount; ++i) {
1220 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1221 fence->submitted = fence->signalled = false;
1222 }
1223
1224 return VK_SUCCESS;
1225 }
1226
1227 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
1228 {
1229 RADV_FROM_HANDLE(radv_device, device, _device);
1230 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1231
1232 if (fence->signalled)
1233 return VK_SUCCESS;
1234 if (!fence->submitted)
1235 return VK_NOT_READY;
1236
1237 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
1238 return VK_NOT_READY;
1239
1240 return VK_SUCCESS;
1241 }
1242
1243
1244 // Queue semaphore functions
1245
1246 VkResult radv_CreateSemaphore(
1247 VkDevice device,
1248 const VkSemaphoreCreateInfo* pCreateInfo,
1249 const VkAllocationCallbacks* pAllocator,
1250 VkSemaphore* pSemaphore)
1251 {
1252 /* The DRM execbuffer ioctl always execute in-oder, even between different
1253 * rings. As such, there's nothing to do for the user space semaphore.
1254 */
1255
1256 *pSemaphore = (VkSemaphore)1;
1257
1258 return VK_SUCCESS;
1259 }
1260
1261 void radv_DestroySemaphore(
1262 VkDevice device,
1263 VkSemaphore semaphore,
1264 const VkAllocationCallbacks* pAllocator)
1265 {
1266 }
1267
1268 VkResult radv_CreateEvent(
1269 VkDevice _device,
1270 const VkEventCreateInfo* pCreateInfo,
1271 const VkAllocationCallbacks* pAllocator,
1272 VkEvent* pEvent)
1273 {
1274 RADV_FROM_HANDLE(radv_device, device, _device);
1275 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
1276 sizeof(*event), 8,
1277 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1278
1279 if (!event)
1280 return VK_ERROR_OUT_OF_HOST_MEMORY;
1281
1282 event->bo = device->ws->buffer_create(device->ws, 8, 8,
1283 RADEON_DOMAIN_GTT,
1284 RADEON_FLAG_CPU_ACCESS);
1285 if (!event->bo) {
1286 vk_free2(&device->alloc, pAllocator, event);
1287 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1288 }
1289
1290 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
1291
1292 *pEvent = radv_event_to_handle(event);
1293
1294 return VK_SUCCESS;
1295 }
1296
1297 void radv_DestroyEvent(
1298 VkDevice _device,
1299 VkEvent _event,
1300 const VkAllocationCallbacks* pAllocator)
1301 {
1302 RADV_FROM_HANDLE(radv_device, device, _device);
1303 RADV_FROM_HANDLE(radv_event, event, _event);
1304
1305 if (!event)
1306 return;
1307 device->ws->buffer_destroy(event->bo);
1308 vk_free2(&device->alloc, pAllocator, event);
1309 }
1310
1311 VkResult radv_GetEventStatus(
1312 VkDevice _device,
1313 VkEvent _event)
1314 {
1315 RADV_FROM_HANDLE(radv_event, event, _event);
1316
1317 if (*event->map == 1)
1318 return VK_EVENT_SET;
1319 return VK_EVENT_RESET;
1320 }
1321
1322 VkResult radv_SetEvent(
1323 VkDevice _device,
1324 VkEvent _event)
1325 {
1326 RADV_FROM_HANDLE(radv_event, event, _event);
1327 *event->map = 1;
1328
1329 return VK_SUCCESS;
1330 }
1331
1332 VkResult radv_ResetEvent(
1333 VkDevice _device,
1334 VkEvent _event)
1335 {
1336 RADV_FROM_HANDLE(radv_event, event, _event);
1337 *event->map = 0;
1338
1339 return VK_SUCCESS;
1340 }
1341
1342 VkResult radv_CreateBuffer(
1343 VkDevice _device,
1344 const VkBufferCreateInfo* pCreateInfo,
1345 const VkAllocationCallbacks* pAllocator,
1346 VkBuffer* pBuffer)
1347 {
1348 RADV_FROM_HANDLE(radv_device, device, _device);
1349 struct radv_buffer *buffer;
1350
1351 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
1352
1353 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
1354 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1355 if (buffer == NULL)
1356 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1357
1358 buffer->size = pCreateInfo->size;
1359 buffer->usage = pCreateInfo->usage;
1360 buffer->bo = NULL;
1361 buffer->offset = 0;
1362
1363 *pBuffer = radv_buffer_to_handle(buffer);
1364
1365 return VK_SUCCESS;
1366 }
1367
1368 void radv_DestroyBuffer(
1369 VkDevice _device,
1370 VkBuffer _buffer,
1371 const VkAllocationCallbacks* pAllocator)
1372 {
1373 RADV_FROM_HANDLE(radv_device, device, _device);
1374 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1375
1376 if (!buffer)
1377 return;
1378
1379 vk_free2(&device->alloc, pAllocator, buffer);
1380 }
1381
1382 static inline unsigned
1383 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
1384 {
1385 if (stencil)
1386 return image->surface.stencil_tiling_index[level];
1387 else
1388 return image->surface.tiling_index[level];
1389 }
1390
1391 static void
1392 radv_initialise_color_surface(struct radv_device *device,
1393 struct radv_color_buffer_info *cb,
1394 struct radv_image_view *iview)
1395 {
1396 const struct vk_format_description *desc;
1397 unsigned ntype, format, swap, endian;
1398 unsigned blend_clamp = 0, blend_bypass = 0;
1399 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
1400 uint64_t va;
1401 const struct radeon_surf *surf = &iview->image->surface;
1402 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
1403
1404 desc = vk_format_description(iview->vk_format);
1405
1406 memset(cb, 0, sizeof(*cb));
1407
1408 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1409 va += level_info->offset;
1410 cb->cb_color_base = va >> 8;
1411
1412 /* CMASK variables */
1413 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1414 va += iview->image->cmask.offset;
1415 cb->cb_color_cmask = va >> 8;
1416 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
1417
1418 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1419 va += iview->image->dcc_offset;
1420 cb->cb_dcc_base = va >> 8;
1421
1422 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
1423 S_028C6C_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1424
1425 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
1426 pitch_tile_max = level_info->nblk_x / 8 - 1;
1427 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
1428 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
1429
1430 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
1431 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
1432
1433 /* Intensity is implemented as Red, so treat it that way. */
1434 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
1435 S_028C74_TILE_MODE_INDEX(tile_mode_index);
1436
1437 if (iview->image->samples > 1) {
1438 unsigned log_samples = util_logbase2(iview->image->samples);
1439
1440 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1441 S_028C74_NUM_FRAGMENTS(log_samples);
1442 }
1443
1444 if (iview->image->fmask.size) {
1445 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
1446 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1447 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
1448 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
1449 cb->cb_color_fmask = va >> 8;
1450 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
1451 } else {
1452 /* This must be set for fast clear to work without FMASK. */
1453 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1454 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
1455 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1456 cb->cb_color_fmask = cb->cb_color_base;
1457 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
1458 }
1459
1460 ntype = radv_translate_color_numformat(iview->vk_format,
1461 desc,
1462 vk_format_get_first_non_void_channel(iview->vk_format));
1463 format = radv_translate_colorformat(iview->vk_format);
1464 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
1465 radv_finishme("Illegal color\n");
1466 swap = radv_translate_colorswap(iview->vk_format, FALSE);
1467 endian = radv_colorformat_endian_swap(format);
1468
1469 /* blend clamp should be set for all NORM/SRGB types */
1470 if (ntype == V_028C70_NUMBER_UNORM ||
1471 ntype == V_028C70_NUMBER_SNORM ||
1472 ntype == V_028C70_NUMBER_SRGB)
1473 blend_clamp = 1;
1474
1475 /* set blend bypass according to docs if SINT/UINT or
1476 8/24 COLOR variants */
1477 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1478 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1479 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1480 blend_clamp = 0;
1481 blend_bypass = 1;
1482 }
1483 #if 0
1484 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
1485 (format == V_028C70_COLOR_8 ||
1486 format == V_028C70_COLOR_8_8 ||
1487 format == V_028C70_COLOR_8_8_8_8))
1488 ->color_is_int8 = true;
1489 #endif
1490 cb->cb_color_info = S_028C70_FORMAT(format) |
1491 S_028C70_COMP_SWAP(swap) |
1492 S_028C70_BLEND_CLAMP(blend_clamp) |
1493 S_028C70_BLEND_BYPASS(blend_bypass) |
1494 S_028C70_SIMPLE_FLOAT(1) |
1495 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
1496 ntype != V_028C70_NUMBER_SNORM &&
1497 ntype != V_028C70_NUMBER_SRGB &&
1498 format != V_028C70_COLOR_8_24 &&
1499 format != V_028C70_COLOR_24_8) |
1500 S_028C70_NUMBER_TYPE(ntype) |
1501 S_028C70_ENDIAN(endian);
1502 if (iview->image->samples > 1)
1503 if (iview->image->fmask.size)
1504 cb->cb_color_info |= S_028C70_COMPRESSION(1);
1505
1506 if (iview->image->cmask.size && device->allow_fast_clears)
1507 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
1508
1509 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
1510 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
1511
1512 if (device->instance->physicalDevice.rad_info.chip_class >= VI) {
1513 unsigned max_uncompressed_block_size = 2;
1514 if (iview->image->samples > 1) {
1515 if (iview->image->surface.bpe == 1)
1516 max_uncompressed_block_size = 0;
1517 else if (iview->image->surface.bpe == 2)
1518 max_uncompressed_block_size = 1;
1519 }
1520
1521 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
1522 S_028C78_INDEPENDENT_64B_BLOCKS(1);
1523 }
1524
1525 /* This must be set for fast clear to work without FMASK. */
1526 if (!iview->image->fmask.size &&
1527 device->instance->physicalDevice.rad_info.chip_class == SI) {
1528 unsigned bankh = util_logbase2(iview->image->surface.bankh);
1529 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1530 }
1531 }
1532
1533 static void
1534 radv_initialise_ds_surface(struct radv_device *device,
1535 struct radv_ds_buffer_info *ds,
1536 struct radv_image_view *iview)
1537 {
1538 unsigned level = iview->base_mip;
1539 unsigned format;
1540 uint64_t va, s_offs, z_offs;
1541 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
1542 memset(ds, 0, sizeof(*ds));
1543 switch (iview->vk_format) {
1544 case VK_FORMAT_D24_UNORM_S8_UINT:
1545 case VK_FORMAT_X8_D24_UNORM_PACK32:
1546 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1547 ds->offset_scale = 2.0f;
1548 break;
1549 case VK_FORMAT_D16_UNORM:
1550 case VK_FORMAT_D16_UNORM_S8_UINT:
1551 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1552 ds->offset_scale = 4.0f;
1553 break;
1554 case VK_FORMAT_D32_SFLOAT:
1555 case VK_FORMAT_D32_SFLOAT_S8_UINT:
1556 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1557 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1558 ds->offset_scale = 1.0f;
1559 break;
1560 default:
1561 break;
1562 }
1563
1564 format = radv_translate_dbformat(iview->vk_format);
1565 if (format == V_028040_Z_INVALID) {
1566 fprintf(stderr, "Invalid DB format: %d, disabling DB.\n", iview->vk_format);
1567 }
1568
1569 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1570 s_offs = z_offs = va;
1571 z_offs += iview->image->surface.level[level].offset;
1572 s_offs += iview->image->surface.stencil_level[level].offset;
1573
1574 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
1575 S_028008_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1576 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1577 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
1578
1579 if (iview->image->samples > 1)
1580 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
1581
1582 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
1583 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
1584 else
1585 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1586
1587 if (device->instance->physicalDevice.rad_info.chip_class >= CIK) {
1588 struct radeon_info *info = &device->instance->physicalDevice.rad_info;
1589 unsigned tiling_index = iview->image->surface.tiling_index[level];
1590 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
1591 unsigned macro_index = iview->image->surface.macro_tile_index;
1592 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
1593 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
1594 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
1595
1596 ds->db_depth_info |=
1597 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
1598 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
1599 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
1600 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
1601 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
1602 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
1603 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
1604 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
1605 } else {
1606 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
1607 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1608 tile_mode_index = si_tile_mode_index(iview->image, level, true);
1609 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1610 }
1611
1612 if (iview->image->htile.size && !level) {
1613 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1614 S_028040_ALLOW_EXPCLEAR(1);
1615
1616 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
1617 /* Workaround: For a not yet understood reason, the
1618 * combination of MSAA, fast stencil clear and stencil
1619 * decompress messes with subsequent stencil buffer
1620 * uses. Problem was reproduced on Verde, Bonaire,
1621 * Tonga, and Carrizo.
1622 *
1623 * Disabling EXPCLEAR works around the problem.
1624 *
1625 * Check piglit's arb_texture_multisample-stencil-clear
1626 * test if you want to try changing this.
1627 */
1628 if (iview->image->samples <= 1)
1629 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
1630 } else
1631 /* Use all of the htile_buffer for depth if there's no stencil. */
1632 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1633
1634 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
1635 iview->image->htile.offset;
1636 ds->db_htile_data_base = va >> 8;
1637 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
1638 } else {
1639 ds->db_htile_data_base = 0;
1640 ds->db_htile_surface = 0;
1641 }
1642
1643 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
1644 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
1645
1646 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
1647 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
1648 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
1649 }
1650
1651 VkResult radv_CreateFramebuffer(
1652 VkDevice _device,
1653 const VkFramebufferCreateInfo* pCreateInfo,
1654 const VkAllocationCallbacks* pAllocator,
1655 VkFramebuffer* pFramebuffer)
1656 {
1657 RADV_FROM_HANDLE(radv_device, device, _device);
1658 struct radv_framebuffer *framebuffer;
1659
1660 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
1661
1662 size_t size = sizeof(*framebuffer) +
1663 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
1664 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
1665 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1666 if (framebuffer == NULL)
1667 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1668
1669 framebuffer->attachment_count = pCreateInfo->attachmentCount;
1670 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
1671 VkImageView _iview = pCreateInfo->pAttachments[i];
1672 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
1673 framebuffer->attachments[i].attachment = iview;
1674 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
1675 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
1676 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
1677 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
1678 }
1679 }
1680
1681 framebuffer->width = pCreateInfo->width;
1682 framebuffer->height = pCreateInfo->height;
1683 framebuffer->layers = pCreateInfo->layers;
1684
1685 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
1686 return VK_SUCCESS;
1687 }
1688
1689 void radv_DestroyFramebuffer(
1690 VkDevice _device,
1691 VkFramebuffer _fb,
1692 const VkAllocationCallbacks* pAllocator)
1693 {
1694 RADV_FROM_HANDLE(radv_device, device, _device);
1695 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
1696
1697 if (!fb)
1698 return;
1699 vk_free2(&device->alloc, pAllocator, fb);
1700 }
1701
1702 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
1703 {
1704 switch (address_mode) {
1705 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
1706 return V_008F30_SQ_TEX_WRAP;
1707 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
1708 return V_008F30_SQ_TEX_MIRROR;
1709 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
1710 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1711 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
1712 return V_008F30_SQ_TEX_CLAMP_BORDER;
1713 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
1714 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1715 default:
1716 unreachable("illegal tex wrap mode");
1717 break;
1718 }
1719 }
1720
1721 static unsigned
1722 radv_tex_compare(VkCompareOp op)
1723 {
1724 switch (op) {
1725 case VK_COMPARE_OP_NEVER:
1726 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1727 case VK_COMPARE_OP_LESS:
1728 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1729 case VK_COMPARE_OP_EQUAL:
1730 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1731 case VK_COMPARE_OP_LESS_OR_EQUAL:
1732 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1733 case VK_COMPARE_OP_GREATER:
1734 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1735 case VK_COMPARE_OP_NOT_EQUAL:
1736 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1737 case VK_COMPARE_OP_GREATER_OR_EQUAL:
1738 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1739 case VK_COMPARE_OP_ALWAYS:
1740 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1741 default:
1742 unreachable("illegal compare mode");
1743 break;
1744 }
1745 }
1746
1747 static unsigned
1748 radv_tex_filter(VkFilter filter, unsigned max_ansio)
1749 {
1750 switch (filter) {
1751 case VK_FILTER_NEAREST:
1752 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
1753 V_008F38_SQ_TEX_XY_FILTER_POINT);
1754 case VK_FILTER_LINEAR:
1755 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
1756 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
1757 case VK_FILTER_CUBIC_IMG:
1758 default:
1759 fprintf(stderr, "illegal texture filter");
1760 return 0;
1761 }
1762 }
1763
1764 static unsigned
1765 radv_tex_mipfilter(VkSamplerMipmapMode mode)
1766 {
1767 switch (mode) {
1768 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
1769 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1770 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
1771 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1772 default:
1773 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1774 }
1775 }
1776
1777 static unsigned
1778 radv_tex_bordercolor(VkBorderColor bcolor)
1779 {
1780 switch (bcolor) {
1781 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
1782 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
1783 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
1784 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
1785 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
1786 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
1787 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
1788 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
1789 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
1790 default:
1791 break;
1792 }
1793 return 0;
1794 }
1795
1796 static unsigned
1797 radv_tex_aniso_filter(unsigned filter)
1798 {
1799 if (filter < 2)
1800 return 0;
1801 if (filter < 4)
1802 return 1;
1803 if (filter < 8)
1804 return 2;
1805 if (filter < 16)
1806 return 3;
1807 return 4;
1808 }
1809
1810 static void
1811 radv_init_sampler(struct radv_device *device,
1812 struct radv_sampler *sampler,
1813 const VkSamplerCreateInfo *pCreateInfo)
1814 {
1815 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
1816 (uint32_t) pCreateInfo->maxAnisotropy : 0;
1817 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
1818 bool is_vi = (device->instance->physicalDevice.rad_info.chip_class >= VI);
1819
1820 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
1821 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
1822 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
1823 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
1824 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
1825 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
1826 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
1827 S_008F30_ANISO_BIAS(max_aniso_ratio) |
1828 S_008F30_DISABLE_CUBE_WRAP(0) |
1829 S_008F30_COMPAT_MODE(is_vi));
1830 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
1831 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
1832 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
1833 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
1834 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
1835 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
1836 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
1837 S_008F38_MIP_POINT_PRECLAMP(1) |
1838 S_008F38_DISABLE_LSB_CEIL(1) |
1839 S_008F38_FILTER_PREC_FIX(1) |
1840 S_008F38_ANISO_OVERRIDE(is_vi));
1841 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
1842 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
1843 }
1844
1845 VkResult radv_CreateSampler(
1846 VkDevice _device,
1847 const VkSamplerCreateInfo* pCreateInfo,
1848 const VkAllocationCallbacks* pAllocator,
1849 VkSampler* pSampler)
1850 {
1851 RADV_FROM_HANDLE(radv_device, device, _device);
1852 struct radv_sampler *sampler;
1853
1854 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
1855
1856 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
1857 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1858 if (!sampler)
1859 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1860
1861 radv_init_sampler(device, sampler, pCreateInfo);
1862 *pSampler = radv_sampler_to_handle(sampler);
1863
1864 return VK_SUCCESS;
1865 }
1866
1867 void radv_DestroySampler(
1868 VkDevice _device,
1869 VkSampler _sampler,
1870 const VkAllocationCallbacks* pAllocator)
1871 {
1872 RADV_FROM_HANDLE(radv_device, device, _device);
1873 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
1874
1875 if (!sampler)
1876 return;
1877 vk_free2(&device->alloc, pAllocator, sampler);
1878 }