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radv: Return correct result in EnumeratePhysicalDevices
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_private.h"
33 #include "util/strtod.h"
34
35 #include <xf86drm.h>
36 #include <amdgpu.h>
37 #include <amdgpu_drm.h>
38 #include "amdgpu_id.h"
39 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
40 #include "ac_llvm_util.h"
41 #include "vk_format.h"
42 #include "sid.h"
43 #include "radv_timestamp.h"
44 #include "util/debug.h"
45 struct radv_dispatch_table dtable;
46
47 struct radv_fence {
48 struct radeon_winsys_fence *fence;
49 bool submitted;
50 bool signalled;
51 };
52
53 static VkResult
54 radv_physical_device_init(struct radv_physical_device *device,
55 struct radv_instance *instance,
56 const char *path)
57 {
58 VkResult result;
59 drmVersionPtr version;
60 int fd;
61
62 fd = open(path, O_RDWR | O_CLOEXEC);
63 if (fd < 0)
64 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
65 "failed to open %s: %m", path);
66
67 version = drmGetVersion(fd);
68 if (!version) {
69 close(fd);
70 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
71 "failed to get version %s: %m", path);
72 }
73
74 if (strcmp(version->name, "amdgpu")) {
75 drmFreeVersion(version);
76 close(fd);
77 return VK_ERROR_INCOMPATIBLE_DRIVER;
78 }
79 drmFreeVersion(version);
80
81 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
82 device->instance = instance;
83 assert(strlen(path) < ARRAY_SIZE(device->path));
84 strncpy(device->path, path, ARRAY_SIZE(device->path));
85
86 device->ws = radv_amdgpu_winsys_create(fd);
87 if (!device->ws) {
88 result = VK_ERROR_INCOMPATIBLE_DRIVER;
89 goto fail;
90 }
91 device->ws->query_info(device->ws, &device->rad_info);
92 result = radv_init_wsi(device);
93 if (result != VK_SUCCESS) {
94 device->ws->destroy(device->ws);
95 goto fail;
96 }
97
98 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
99 device->name = device->rad_info.name;
100 return VK_SUCCESS;
101
102 fail:
103 close(fd);
104 return result;
105 }
106
107 static void
108 radv_physical_device_finish(struct radv_physical_device *device)
109 {
110 radv_finish_wsi(device);
111 device->ws->destroy(device->ws);
112 }
113
114 static const VkExtensionProperties global_extensions[] = {
115 {
116 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
117 .specVersion = 25,
118 },
119 #ifdef VK_USE_PLATFORM_XCB_KHR
120 {
121 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
122 .specVersion = 5,
123 },
124 #endif
125 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
126 {
127 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
128 .specVersion = 4,
129 },
130 #endif
131 };
132
133 static const VkExtensionProperties device_extensions[] = {
134 {
135 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
136 .specVersion = 67,
137 },
138 };
139
140 static void *
141 default_alloc_func(void *pUserData, size_t size, size_t align,
142 VkSystemAllocationScope allocationScope)
143 {
144 return malloc(size);
145 }
146
147 static void *
148 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
149 size_t align, VkSystemAllocationScope allocationScope)
150 {
151 return realloc(pOriginal, size);
152 }
153
154 static void
155 default_free_func(void *pUserData, void *pMemory)
156 {
157 free(pMemory);
158 }
159
160 static const VkAllocationCallbacks default_alloc = {
161 .pUserData = NULL,
162 .pfnAllocation = default_alloc_func,
163 .pfnReallocation = default_realloc_func,
164 .pfnFree = default_free_func,
165 };
166
167 VkResult radv_CreateInstance(
168 const VkInstanceCreateInfo* pCreateInfo,
169 const VkAllocationCallbacks* pAllocator,
170 VkInstance* pInstance)
171 {
172 struct radv_instance *instance;
173
174 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
175
176 uint32_t client_version;
177 if (pCreateInfo->pApplicationInfo &&
178 pCreateInfo->pApplicationInfo->apiVersion != 0) {
179 client_version = pCreateInfo->pApplicationInfo->apiVersion;
180 } else {
181 client_version = VK_MAKE_VERSION(1, 0, 0);
182 }
183
184 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
185 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
186 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
187 "Client requested version %d.%d.%d",
188 VK_VERSION_MAJOR(client_version),
189 VK_VERSION_MINOR(client_version),
190 VK_VERSION_PATCH(client_version));
191 }
192
193 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
194 bool found = false;
195 for (uint32_t j = 0; j < ARRAY_SIZE(global_extensions); j++) {
196 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
197 global_extensions[j].extensionName) == 0) {
198 found = true;
199 break;
200 }
201 }
202 if (!found)
203 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
204 }
205
206 instance = radv_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
207 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
208 if (!instance)
209 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
210
211 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
212
213 if (pAllocator)
214 instance->alloc = *pAllocator;
215 else
216 instance->alloc = default_alloc;
217
218 instance->apiVersion = client_version;
219 instance->physicalDeviceCount = -1;
220
221 _mesa_locale_init();
222
223 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
224
225 *pInstance = radv_instance_to_handle(instance);
226
227 return VK_SUCCESS;
228 }
229
230 void radv_DestroyInstance(
231 VkInstance _instance,
232 const VkAllocationCallbacks* pAllocator)
233 {
234 RADV_FROM_HANDLE(radv_instance, instance, _instance);
235
236 if (instance->physicalDeviceCount > 0) {
237 /* We support at most one physical device. */
238 assert(instance->physicalDeviceCount == 1);
239 radv_physical_device_finish(&instance->physicalDevice);
240 }
241
242 VG(VALGRIND_DESTROY_MEMPOOL(instance));
243
244 _mesa_locale_fini();
245
246 radv_free(&instance->alloc, instance);
247 }
248
249 VkResult radv_EnumeratePhysicalDevices(
250 VkInstance _instance,
251 uint32_t* pPhysicalDeviceCount,
252 VkPhysicalDevice* pPhysicalDevices)
253 {
254 RADV_FROM_HANDLE(radv_instance, instance, _instance);
255 VkResult result;
256
257 if (instance->physicalDeviceCount < 0) {
258 char path[20];
259 for (unsigned i = 0; i < 8; i++) {
260 snprintf(path, sizeof(path), "/dev/dri/renderD%d", 128 + i);
261 result = radv_physical_device_init(&instance->physicalDevice,
262 instance, path);
263 if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
264 break;
265 }
266
267 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
268 instance->physicalDeviceCount = 0;
269 } else if (result == VK_SUCCESS) {
270 instance->physicalDeviceCount = 1;
271 } else {
272 return result;
273 }
274 }
275
276 /* pPhysicalDeviceCount is an out parameter if pPhysicalDevices is NULL;
277 * otherwise it's an inout parameter.
278 *
279 * The Vulkan spec (git aaed022) says:
280 *
281 * pPhysicalDeviceCount is a pointer to an unsigned integer variable
282 * that is initialized with the number of devices the application is
283 * prepared to receive handles to. pname:pPhysicalDevices is pointer to
284 * an array of at least this many VkPhysicalDevice handles [...].
285 *
286 * Upon success, if pPhysicalDevices is NULL, vkEnumeratePhysicalDevices
287 * overwrites the contents of the variable pointed to by
288 * pPhysicalDeviceCount with the number of physical devices in in the
289 * instance; otherwise, vkEnumeratePhysicalDevices overwrites
290 * pPhysicalDeviceCount with the number of physical handles written to
291 * pPhysicalDevices.
292 */
293 if (!pPhysicalDevices) {
294 *pPhysicalDeviceCount = instance->physicalDeviceCount;
295 } else if (*pPhysicalDeviceCount >= 1) {
296 pPhysicalDevices[0] = radv_physical_device_to_handle(&instance->physicalDevice);
297 *pPhysicalDeviceCount = 1;
298 } else if (*pPhysicalDeviceCount < instance->physicalDeviceCount) {
299 return VK_INCOMPLETE;
300 } else {
301 *pPhysicalDeviceCount = 0;
302 }
303
304 return VK_SUCCESS;
305 }
306
307 void radv_GetPhysicalDeviceFeatures(
308 VkPhysicalDevice physicalDevice,
309 VkPhysicalDeviceFeatures* pFeatures)
310 {
311 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
312
313 memset(pFeatures, 0, sizeof(*pFeatures));
314
315 *pFeatures = (VkPhysicalDeviceFeatures) {
316 .robustBufferAccess = true,
317 .fullDrawIndexUint32 = true,
318 .imageCubeArray = true,
319 .independentBlend = true,
320 .geometryShader = false,
321 .tessellationShader = false,
322 .sampleRateShading = false,
323 .dualSrcBlend = true,
324 .logicOp = true,
325 .multiDrawIndirect = true,
326 .drawIndirectFirstInstance = true,
327 .depthClamp = true,
328 .depthBiasClamp = true,
329 .fillModeNonSolid = true,
330 .depthBounds = true,
331 .wideLines = true,
332 .largePoints = true,
333 .alphaToOne = true,
334 .multiViewport = false,
335 .samplerAnisotropy = false, /* FINISHME */
336 .textureCompressionETC2 = false,
337 .textureCompressionASTC_LDR = false,
338 .textureCompressionBC = true,
339 .occlusionQueryPrecise = true,
340 .pipelineStatisticsQuery = false,
341 .vertexPipelineStoresAndAtomics = true,
342 .fragmentStoresAndAtomics = true,
343 .shaderTessellationAndGeometryPointSize = true,
344 .shaderImageGatherExtended = false,
345 .shaderStorageImageExtendedFormats = false,
346 .shaderStorageImageMultisample = false,
347 .shaderUniformBufferArrayDynamicIndexing = true,
348 .shaderSampledImageArrayDynamicIndexing = true,
349 .shaderStorageBufferArrayDynamicIndexing = true,
350 .shaderStorageImageArrayDynamicIndexing = true,
351 .shaderStorageImageReadWithoutFormat = false,
352 .shaderStorageImageWriteWithoutFormat = true,
353 .shaderClipDistance = true,
354 .shaderCullDistance = true,
355 .shaderFloat64 = false,
356 .shaderInt64 = false,
357 .shaderInt16 = false,
358 .alphaToOne = true,
359 .variableMultisampleRate = false,
360 .inheritedQueries = false,
361 };
362 }
363
364 void
365 radv_device_get_cache_uuid(void *uuid)
366 {
367 memset(uuid, 0, VK_UUID_SIZE);
368 snprintf(uuid, VK_UUID_SIZE, "radv-%s", RADV_TIMESTAMP);
369 }
370
371 void radv_GetPhysicalDeviceProperties(
372 VkPhysicalDevice physicalDevice,
373 VkPhysicalDeviceProperties* pProperties)
374 {
375 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
376 VkSampleCountFlags sample_counts = 0xf;
377 VkPhysicalDeviceLimits limits = {
378 .maxImageDimension1D = (1 << 14),
379 .maxImageDimension2D = (1 << 14),
380 .maxImageDimension3D = (1 << 11),
381 .maxImageDimensionCube = (1 << 14),
382 .maxImageArrayLayers = (1 << 11),
383 .maxTexelBufferElements = 128 * 1024 * 1024,
384 .maxUniformBufferRange = UINT32_MAX,
385 .maxStorageBufferRange = UINT32_MAX,
386 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
387 .maxMemoryAllocationCount = UINT32_MAX,
388 .maxSamplerAllocationCount = 64 * 1024,
389 .bufferImageGranularity = 64, /* A cache line */
390 .sparseAddressSpaceSize = 0,
391 .maxBoundDescriptorSets = MAX_SETS,
392 .maxPerStageDescriptorSamplers = 64,
393 .maxPerStageDescriptorUniformBuffers = 64,
394 .maxPerStageDescriptorStorageBuffers = 64,
395 .maxPerStageDescriptorSampledImages = 64,
396 .maxPerStageDescriptorStorageImages = 64,
397 .maxPerStageDescriptorInputAttachments = 64,
398 .maxPerStageResources = 128,
399 .maxDescriptorSetSamplers = 256,
400 .maxDescriptorSetUniformBuffers = 256,
401 .maxDescriptorSetUniformBuffersDynamic = 256,
402 .maxDescriptorSetStorageBuffers = 256,
403 .maxDescriptorSetStorageBuffersDynamic = 256,
404 .maxDescriptorSetSampledImages = 256,
405 .maxDescriptorSetStorageImages = 256,
406 .maxDescriptorSetInputAttachments = 256,
407 .maxVertexInputAttributes = 32,
408 .maxVertexInputBindings = 32,
409 .maxVertexInputAttributeOffset = 2047,
410 .maxVertexInputBindingStride = 2048,
411 .maxVertexOutputComponents = 128,
412 .maxTessellationGenerationLevel = 0,
413 .maxTessellationPatchSize = 0,
414 .maxTessellationControlPerVertexInputComponents = 0,
415 .maxTessellationControlPerVertexOutputComponents = 0,
416 .maxTessellationControlPerPatchOutputComponents = 0,
417 .maxTessellationControlTotalOutputComponents = 0,
418 .maxTessellationEvaluationInputComponents = 0,
419 .maxTessellationEvaluationOutputComponents = 0,
420 .maxGeometryShaderInvocations = 32,
421 .maxGeometryInputComponents = 64,
422 .maxGeometryOutputComponents = 128,
423 .maxGeometryOutputVertices = 256,
424 .maxGeometryTotalOutputComponents = 1024,
425 .maxFragmentInputComponents = 128,
426 .maxFragmentOutputAttachments = 8,
427 .maxFragmentDualSrcAttachments = 2,
428 .maxFragmentCombinedOutputResources = 8,
429 .maxComputeSharedMemorySize = 32768,
430 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
431 .maxComputeWorkGroupInvocations = 16 * 1024,
432 .maxComputeWorkGroupSize = {
433 16 * 1024/*devinfo->max_cs_threads*/,
434 16 * 1024,
435 16 * 1024
436 },
437 .subPixelPrecisionBits = 4 /* FIXME */,
438 .subTexelPrecisionBits = 4 /* FIXME */,
439 .mipmapPrecisionBits = 4 /* FIXME */,
440 .maxDrawIndexedIndexValue = UINT32_MAX,
441 .maxDrawIndirectCount = UINT32_MAX,
442 .maxSamplerLodBias = 16,
443 .maxSamplerAnisotropy = 16,
444 .maxViewports = MAX_VIEWPORTS,
445 .maxViewportDimensions = { (1 << 14), (1 << 14) },
446 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
447 .viewportSubPixelBits = 13, /* We take a float? */
448 .minMemoryMapAlignment = 4096, /* A page */
449 .minTexelBufferOffsetAlignment = 1,
450 .minUniformBufferOffsetAlignment = 4,
451 .minStorageBufferOffsetAlignment = 4,
452 .minTexelOffset = -8,
453 .maxTexelOffset = 7,
454 .minTexelGatherOffset = -8,
455 .maxTexelGatherOffset = 7,
456 .minInterpolationOffset = 0, /* FIXME */
457 .maxInterpolationOffset = 0, /* FIXME */
458 .subPixelInterpolationOffsetBits = 0, /* FIXME */
459 .maxFramebufferWidth = (1 << 14),
460 .maxFramebufferHeight = (1 << 14),
461 .maxFramebufferLayers = (1 << 10),
462 .framebufferColorSampleCounts = sample_counts,
463 .framebufferDepthSampleCounts = sample_counts,
464 .framebufferStencilSampleCounts = sample_counts,
465 .framebufferNoAttachmentsSampleCounts = sample_counts,
466 .maxColorAttachments = MAX_RTS,
467 .sampledImageColorSampleCounts = sample_counts,
468 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
469 .sampledImageDepthSampleCounts = sample_counts,
470 .sampledImageStencilSampleCounts = sample_counts,
471 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
472 .maxSampleMaskWords = 1,
473 .timestampComputeAndGraphics = false,
474 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
475 .maxClipDistances = 8,
476 .maxCullDistances = 8,
477 .maxCombinedClipAndCullDistances = 8,
478 .discreteQueuePriorities = 1,
479 .pointSizeRange = { 0.125, 255.875 },
480 .lineWidthRange = { 0.0, 7.9921875 },
481 .pointSizeGranularity = (1.0 / 8.0),
482 .lineWidthGranularity = (1.0 / 128.0),
483 .strictLines = false, /* FINISHME */
484 .standardSampleLocations = true,
485 .optimalBufferCopyOffsetAlignment = 128,
486 .optimalBufferCopyRowPitchAlignment = 128,
487 .nonCoherentAtomSize = 64,
488 };
489
490 *pProperties = (VkPhysicalDeviceProperties) {
491 .apiVersion = VK_MAKE_VERSION(1, 0, 5),
492 .driverVersion = 1,
493 .vendorID = 0x1002,
494 .deviceID = pdevice->rad_info.pci_id,
495 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
496 .limits = limits,
497 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
498 };
499
500 strcpy(pProperties->deviceName, pdevice->name);
501 radv_device_get_cache_uuid(pProperties->pipelineCacheUUID);
502 }
503
504 void radv_GetPhysicalDeviceQueueFamilyProperties(
505 VkPhysicalDevice physicalDevice,
506 uint32_t* pCount,
507 VkQueueFamilyProperties* pQueueFamilyProperties)
508 {
509 if (pQueueFamilyProperties == NULL) {
510 *pCount = 1;
511 return;
512 }
513 assert(*pCount >= 1);
514
515 *pQueueFamilyProperties = (VkQueueFamilyProperties) {
516 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
517 VK_QUEUE_COMPUTE_BIT |
518 VK_QUEUE_TRANSFER_BIT,
519 .queueCount = 1,
520 .timestampValidBits = 64,
521 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
522 };
523 }
524
525 void radv_GetPhysicalDeviceMemoryProperties(
526 VkPhysicalDevice physicalDevice,
527 VkPhysicalDeviceMemoryProperties* pMemoryProperties)
528 {
529 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
530
531 pMemoryProperties->memoryTypeCount = 3;
532 pMemoryProperties->memoryTypes[0] = (VkMemoryType) {
533 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
534 .heapIndex = 0,
535 };
536 pMemoryProperties->memoryTypes[1] = (VkMemoryType) {
537 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
538 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
539 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
540 .heapIndex = 0,
541 };
542 pMemoryProperties->memoryTypes[2] = (VkMemoryType) {
543 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT|
544 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
545 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
546 .heapIndex = 1,
547 };
548
549 pMemoryProperties->memoryHeapCount = 2;
550 pMemoryProperties->memoryHeaps[0] = (VkMemoryHeap) {
551 .size = physical_device->rad_info.vram_size,
552 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
553 };
554 pMemoryProperties->memoryHeaps[1] = (VkMemoryHeap) {
555 .size = physical_device->rad_info.gart_size,
556 .flags = 0,
557 };
558 }
559
560 static VkResult
561 radv_queue_init(struct radv_device *device, struct radv_queue *queue)
562 {
563 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
564 queue->device = device;
565
566 return VK_SUCCESS;
567 }
568
569 static void
570 radv_queue_finish(struct radv_queue *queue)
571 {
572 }
573
574 VkResult radv_CreateDevice(
575 VkPhysicalDevice physicalDevice,
576 const VkDeviceCreateInfo* pCreateInfo,
577 const VkAllocationCallbacks* pAllocator,
578 VkDevice* pDevice)
579 {
580 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
581 VkResult result;
582 struct radv_device *device;
583
584 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
585 bool found = false;
586 for (uint32_t j = 0; j < ARRAY_SIZE(device_extensions); j++) {
587 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
588 device_extensions[j].extensionName) == 0) {
589 found = true;
590 break;
591 }
592 }
593 if (!found)
594 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
595 }
596
597 device = radv_alloc2(&physical_device->instance->alloc, pAllocator,
598 sizeof(*device), 8,
599 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
600 if (!device)
601 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
602
603 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
604 device->instance = physical_device->instance;
605
606 device->ws = physical_device->ws;
607 if (pAllocator)
608 device->alloc = *pAllocator;
609 else
610 device->alloc = physical_device->instance->alloc;
611
612 device->hw_ctx = device->ws->ctx_create(device->ws);
613 if (!device->hw_ctx) {
614 result = VK_ERROR_OUT_OF_HOST_MEMORY;
615 goto fail_free;
616 }
617
618 radv_queue_init(device, &device->queue);
619
620 result = radv_device_init_meta(device);
621 if (result != VK_SUCCESS) {
622 device->ws->ctx_destroy(device->hw_ctx);
623 goto fail_free;
624 }
625 device->allow_fast_clears = env_var_as_boolean("RADV_FAST_CLEARS", false);
626 device->allow_dcc = !env_var_as_boolean("RADV_DCC_DISABLE", false);
627
628 if (device->allow_fast_clears && device->allow_dcc)
629 radv_finishme("DCC fast clears have not been tested\n");
630
631 radv_device_init_msaa(device);
632 device->empty_cs = device->ws->cs_create(device->ws, RING_GFX);
633 radeon_emit(device->empty_cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
634 radeon_emit(device->empty_cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
635 radeon_emit(device->empty_cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
636 device->ws->cs_finalize(device->empty_cs);
637 *pDevice = radv_device_to_handle(device);
638 return VK_SUCCESS;
639 fail_free:
640 radv_free(&device->alloc, device);
641 return result;
642 }
643
644 void radv_DestroyDevice(
645 VkDevice _device,
646 const VkAllocationCallbacks* pAllocator)
647 {
648 RADV_FROM_HANDLE(radv_device, device, _device);
649
650 device->ws->ctx_destroy(device->hw_ctx);
651 radv_queue_finish(&device->queue);
652 radv_device_finish_meta(device);
653
654 radv_free(&device->alloc, device);
655 }
656
657 VkResult radv_EnumerateInstanceExtensionProperties(
658 const char* pLayerName,
659 uint32_t* pPropertyCount,
660 VkExtensionProperties* pProperties)
661 {
662 unsigned i;
663 if (pProperties == NULL) {
664 *pPropertyCount = ARRAY_SIZE(global_extensions);
665 return VK_SUCCESS;
666 }
667
668 for (i = 0; i < *pPropertyCount; i++)
669 memcpy(&pProperties[i], &global_extensions[i], sizeof(VkExtensionProperties));
670
671 *pPropertyCount = i;
672 if (i < ARRAY_SIZE(global_extensions))
673 return VK_INCOMPLETE;
674
675 return VK_SUCCESS;
676 }
677
678 VkResult radv_EnumerateDeviceExtensionProperties(
679 VkPhysicalDevice physicalDevice,
680 const char* pLayerName,
681 uint32_t* pPropertyCount,
682 VkExtensionProperties* pProperties)
683 {
684 unsigned i;
685
686 if (pProperties == NULL) {
687 *pPropertyCount = ARRAY_SIZE(device_extensions);
688 return VK_SUCCESS;
689 }
690
691 for (i = 0; i < *pPropertyCount; i++)
692 memcpy(&pProperties[i], &device_extensions[i], sizeof(VkExtensionProperties));
693
694 *pPropertyCount = i;
695 if (i < ARRAY_SIZE(device_extensions))
696 return VK_INCOMPLETE;
697 return VK_SUCCESS;
698 }
699
700 VkResult radv_EnumerateInstanceLayerProperties(
701 uint32_t* pPropertyCount,
702 VkLayerProperties* pProperties)
703 {
704 if (pProperties == NULL) {
705 *pPropertyCount = 0;
706 return VK_SUCCESS;
707 }
708
709 /* None supported at this time */
710 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
711 }
712
713 VkResult radv_EnumerateDeviceLayerProperties(
714 VkPhysicalDevice physicalDevice,
715 uint32_t* pPropertyCount,
716 VkLayerProperties* pProperties)
717 {
718 if (pProperties == NULL) {
719 *pPropertyCount = 0;
720 return VK_SUCCESS;
721 }
722
723 /* None supported at this time */
724 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
725 }
726
727 void radv_GetDeviceQueue(
728 VkDevice _device,
729 uint32_t queueNodeIndex,
730 uint32_t queueIndex,
731 VkQueue* pQueue)
732 {
733 RADV_FROM_HANDLE(radv_device, device, _device);
734
735 assert(queueIndex == 0);
736
737 *pQueue = radv_queue_to_handle(&device->queue);
738 }
739
740 VkResult radv_QueueSubmit(
741 VkQueue _queue,
742 uint32_t submitCount,
743 const VkSubmitInfo* pSubmits,
744 VkFence _fence)
745 {
746 RADV_FROM_HANDLE(radv_queue, queue, _queue);
747 RADV_FROM_HANDLE(radv_fence, fence, _fence);
748 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
749 struct radeon_winsys_ctx *ctx = queue->device->hw_ctx;
750 int ret;
751
752 for (uint32_t i = 0; i < submitCount; i++) {
753 struct radeon_winsys_cs **cs_array;
754 bool can_patch = true;
755
756 if (!pSubmits[i].commandBufferCount)
757 continue;
758
759 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
760 pSubmits[i].commandBufferCount);
761
762 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
763 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
764 pSubmits[i].pCommandBuffers[j]);
765 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
766
767 cs_array[j] = cmd_buffer->cs;
768 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
769 can_patch = false;
770 }
771 ret = queue->device->ws->cs_submit(ctx, cs_array,
772 pSubmits[i].commandBufferCount,
773 can_patch, base_fence);
774 if (ret)
775 radv_loge("failed to submit CS %d\n", i);
776 free(cs_array);
777 }
778
779 if (fence) {
780 if (!submitCount)
781 ret = queue->device->ws->cs_submit(ctx, &queue->device->empty_cs,
782 1, false, base_fence);
783
784 fence->submitted = true;
785 }
786
787 return VK_SUCCESS;
788 }
789
790 VkResult radv_QueueWaitIdle(
791 VkQueue _queue)
792 {
793 RADV_FROM_HANDLE(radv_queue, queue, _queue);
794
795 queue->device->ws->ctx_wait_idle(queue->device->hw_ctx);
796 return VK_SUCCESS;
797 }
798
799 VkResult radv_DeviceWaitIdle(
800 VkDevice _device)
801 {
802 RADV_FROM_HANDLE(radv_device, device, _device);
803
804 device->ws->ctx_wait_idle(device->hw_ctx);
805 return VK_SUCCESS;
806 }
807
808 PFN_vkVoidFunction radv_GetInstanceProcAddr(
809 VkInstance instance,
810 const char* pName)
811 {
812 return radv_lookup_entrypoint(pName);
813 }
814
815 /* The loader wants us to expose a second GetInstanceProcAddr function
816 * to work around certain LD_PRELOAD issues seen in apps.
817 */
818 PUBLIC
819 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
820 VkInstance instance,
821 const char* pName);
822
823 PUBLIC
824 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
825 VkInstance instance,
826 const char* pName)
827 {
828 return radv_GetInstanceProcAddr(instance, pName);
829 }
830
831 PFN_vkVoidFunction radv_GetDeviceProcAddr(
832 VkDevice device,
833 const char* pName)
834 {
835 return radv_lookup_entrypoint(pName);
836 }
837
838 VkResult radv_AllocateMemory(
839 VkDevice _device,
840 const VkMemoryAllocateInfo* pAllocateInfo,
841 const VkAllocationCallbacks* pAllocator,
842 VkDeviceMemory* pMem)
843 {
844 RADV_FROM_HANDLE(radv_device, device, _device);
845 struct radv_device_memory *mem;
846 VkResult result;
847 enum radeon_bo_domain domain;
848 uint32_t flags = 0;
849 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
850
851 if (pAllocateInfo->allocationSize == 0) {
852 /* Apparently, this is allowed */
853 *pMem = VK_NULL_HANDLE;
854 return VK_SUCCESS;
855 }
856
857 mem = radv_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
858 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
859 if (mem == NULL)
860 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
861
862 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
863 if (pAllocateInfo->memoryTypeIndex == 2)
864 domain = RADEON_DOMAIN_GTT;
865 else
866 domain = RADEON_DOMAIN_VRAM;
867
868 if (pAllocateInfo->memoryTypeIndex == 0)
869 flags |= RADEON_FLAG_NO_CPU_ACCESS;
870 else
871 flags |= RADEON_FLAG_CPU_ACCESS;
872 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 32768,
873 domain, flags);
874
875 if (!mem->bo) {
876 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
877 goto fail;
878 }
879 mem->type_index = pAllocateInfo->memoryTypeIndex;
880
881 *pMem = radv_device_memory_to_handle(mem);
882
883 return VK_SUCCESS;
884
885 fail:
886 radv_free2(&device->alloc, pAllocator, mem);
887
888 return result;
889 }
890
891 void radv_FreeMemory(
892 VkDevice _device,
893 VkDeviceMemory _mem,
894 const VkAllocationCallbacks* pAllocator)
895 {
896 RADV_FROM_HANDLE(radv_device, device, _device);
897 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
898
899 if (mem == NULL)
900 return;
901
902 device->ws->buffer_destroy(mem->bo);
903 mem->bo = NULL;
904
905 radv_free2(&device->alloc, pAllocator, mem);
906 }
907
908 VkResult radv_MapMemory(
909 VkDevice _device,
910 VkDeviceMemory _memory,
911 VkDeviceSize offset,
912 VkDeviceSize size,
913 VkMemoryMapFlags flags,
914 void** ppData)
915 {
916 RADV_FROM_HANDLE(radv_device, device, _device);
917 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
918
919 if (mem == NULL) {
920 *ppData = NULL;
921 return VK_SUCCESS;
922 }
923
924 *ppData = device->ws->buffer_map(mem->bo);
925 if (*ppData) {
926 *ppData += offset;
927 return VK_SUCCESS;
928 }
929
930 return VK_ERROR_MEMORY_MAP_FAILED;
931 }
932
933 void radv_UnmapMemory(
934 VkDevice _device,
935 VkDeviceMemory _memory)
936 {
937 RADV_FROM_HANDLE(radv_device, device, _device);
938 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
939
940 if (mem == NULL)
941 return;
942
943 device->ws->buffer_unmap(mem->bo);
944 }
945
946 VkResult radv_FlushMappedMemoryRanges(
947 VkDevice _device,
948 uint32_t memoryRangeCount,
949 const VkMappedMemoryRange* pMemoryRanges)
950 {
951 return VK_SUCCESS;
952 }
953
954 VkResult radv_InvalidateMappedMemoryRanges(
955 VkDevice _device,
956 uint32_t memoryRangeCount,
957 const VkMappedMemoryRange* pMemoryRanges)
958 {
959 return VK_SUCCESS;
960 }
961
962 void radv_GetBufferMemoryRequirements(
963 VkDevice device,
964 VkBuffer _buffer,
965 VkMemoryRequirements* pMemoryRequirements)
966 {
967 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
968
969 /* The Vulkan spec (git aaed022) says:
970 *
971 * memoryTypeBits is a bitfield and contains one bit set for every
972 * supported memory type for the resource. The bit `1<<i` is set if and
973 * only if the memory type `i` in the VkPhysicalDeviceMemoryProperties
974 * structure for the physical device is supported.
975 *
976 * We support exactly one memory type.
977 */
978 pMemoryRequirements->memoryTypeBits = 0x7;
979
980 pMemoryRequirements->size = buffer->size;
981 pMemoryRequirements->alignment = 16;
982 }
983
984 void radv_GetImageMemoryRequirements(
985 VkDevice device,
986 VkImage _image,
987 VkMemoryRequirements* pMemoryRequirements)
988 {
989 RADV_FROM_HANDLE(radv_image, image, _image);
990
991 /* The Vulkan spec (git aaed022) says:
992 *
993 * memoryTypeBits is a bitfield and contains one bit set for every
994 * supported memory type for the resource. The bit `1<<i` is set if and
995 * only if the memory type `i` in the VkPhysicalDeviceMemoryProperties
996 * structure for the physical device is supported.
997 *
998 * We support exactly one memory type.
999 */
1000 pMemoryRequirements->memoryTypeBits = 0x7;
1001
1002 pMemoryRequirements->size = image->size;
1003 pMemoryRequirements->alignment = image->alignment;
1004 }
1005
1006 void radv_GetImageSparseMemoryRequirements(
1007 VkDevice device,
1008 VkImage image,
1009 uint32_t* pSparseMemoryRequirementCount,
1010 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
1011 {
1012 stub();
1013 }
1014
1015 void radv_GetDeviceMemoryCommitment(
1016 VkDevice device,
1017 VkDeviceMemory memory,
1018 VkDeviceSize* pCommittedMemoryInBytes)
1019 {
1020 *pCommittedMemoryInBytes = 0;
1021 }
1022
1023 VkResult radv_BindBufferMemory(
1024 VkDevice device,
1025 VkBuffer _buffer,
1026 VkDeviceMemory _memory,
1027 VkDeviceSize memoryOffset)
1028 {
1029 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1030 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1031
1032 if (mem) {
1033 buffer->bo = mem->bo;
1034 buffer->offset = memoryOffset;
1035 } else {
1036 buffer->bo = NULL;
1037 buffer->offset = 0;
1038 }
1039
1040 return VK_SUCCESS;
1041 }
1042
1043 VkResult radv_BindImageMemory(
1044 VkDevice device,
1045 VkImage _image,
1046 VkDeviceMemory _memory,
1047 VkDeviceSize memoryOffset)
1048 {
1049 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1050 RADV_FROM_HANDLE(radv_image, image, _image);
1051
1052 if (mem) {
1053 image->bo = mem->bo;
1054 image->offset = memoryOffset;
1055 } else {
1056 image->bo = NULL;
1057 image->offset = 0;
1058 }
1059
1060 return VK_SUCCESS;
1061 }
1062
1063 VkResult radv_QueueBindSparse(
1064 VkQueue queue,
1065 uint32_t bindInfoCount,
1066 const VkBindSparseInfo* pBindInfo,
1067 VkFence fence)
1068 {
1069 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER);
1070 }
1071
1072 VkResult radv_CreateFence(
1073 VkDevice _device,
1074 const VkFenceCreateInfo* pCreateInfo,
1075 const VkAllocationCallbacks* pAllocator,
1076 VkFence* pFence)
1077 {
1078 RADV_FROM_HANDLE(radv_device, device, _device);
1079 struct radv_fence *fence = radv_alloc2(&device->alloc, pAllocator,
1080 sizeof(*fence), 8,
1081 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1082
1083 if (!fence)
1084 return VK_ERROR_OUT_OF_HOST_MEMORY;
1085
1086 memset(fence, 0, sizeof(*fence));
1087 fence->submitted = false;
1088 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
1089 fence->fence = device->ws->create_fence();
1090
1091
1092 *pFence = radv_fence_to_handle(fence);
1093
1094 return VK_SUCCESS;
1095 }
1096
1097 void radv_DestroyFence(
1098 VkDevice _device,
1099 VkFence _fence,
1100 const VkAllocationCallbacks* pAllocator)
1101 {
1102 RADV_FROM_HANDLE(radv_device, device, _device);
1103 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1104
1105 if (!fence)
1106 return;
1107 device->ws->destroy_fence(fence->fence);
1108 radv_free2(&device->alloc, pAllocator, fence);
1109 }
1110
1111 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
1112 {
1113 uint64_t current_time;
1114 struct timespec tv;
1115
1116 clock_gettime(CLOCK_MONOTONIC, &tv);
1117 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
1118
1119 timeout = MIN2(UINT64_MAX - current_time, timeout);
1120
1121 return current_time + timeout;
1122 }
1123
1124 VkResult radv_WaitForFences(
1125 VkDevice _device,
1126 uint32_t fenceCount,
1127 const VkFence* pFences,
1128 VkBool32 waitAll,
1129 uint64_t timeout)
1130 {
1131 RADV_FROM_HANDLE(radv_device, device, _device);
1132 timeout = radv_get_absolute_timeout(timeout);
1133
1134 if (!waitAll && fenceCount > 1) {
1135 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
1136 }
1137
1138 for (uint32_t i = 0; i < fenceCount; ++i) {
1139 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1140 bool expired = false;
1141
1142 if (fence->signalled)
1143 continue;
1144
1145 if (!fence->submitted)
1146 return VK_TIMEOUT;
1147
1148 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
1149 if (!expired)
1150 return VK_TIMEOUT;
1151
1152 fence->signalled = true;
1153 }
1154
1155 return VK_SUCCESS;
1156 }
1157
1158 VkResult radv_ResetFences(VkDevice device,
1159 uint32_t fenceCount,
1160 const VkFence *pFences)
1161 {
1162 for (unsigned i = 0; i < fenceCount; ++i) {
1163 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1164 fence->submitted = fence->signalled = false;
1165 }
1166
1167 return VK_SUCCESS;
1168 }
1169
1170 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
1171 {
1172 RADV_FROM_HANDLE(radv_device, device, _device);
1173 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1174
1175 if (!fence->submitted)
1176 return VK_NOT_READY;
1177
1178 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
1179 return VK_NOT_READY;
1180
1181 return VK_SUCCESS;
1182 }
1183
1184
1185 // Queue semaphore functions
1186
1187 VkResult radv_CreateSemaphore(
1188 VkDevice device,
1189 const VkSemaphoreCreateInfo* pCreateInfo,
1190 const VkAllocationCallbacks* pAllocator,
1191 VkSemaphore* pSemaphore)
1192 {
1193 /* The DRM execbuffer ioctl always execute in-oder, even between different
1194 * rings. As such, there's nothing to do for the user space semaphore.
1195 */
1196
1197 *pSemaphore = (VkSemaphore)1;
1198
1199 return VK_SUCCESS;
1200 }
1201
1202 void radv_DestroySemaphore(
1203 VkDevice device,
1204 VkSemaphore semaphore,
1205 const VkAllocationCallbacks* pAllocator)
1206 {
1207 }
1208
1209 VkResult radv_CreateEvent(
1210 VkDevice _device,
1211 const VkEventCreateInfo* pCreateInfo,
1212 const VkAllocationCallbacks* pAllocator,
1213 VkEvent* pEvent)
1214 {
1215 RADV_FROM_HANDLE(radv_device, device, _device);
1216 struct radv_event *event = radv_alloc2(&device->alloc, pAllocator,
1217 sizeof(*event), 8,
1218 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1219
1220 if (!event)
1221 return VK_ERROR_OUT_OF_HOST_MEMORY;
1222
1223 event->bo = device->ws->buffer_create(device->ws, 8, 8,
1224 RADEON_DOMAIN_GTT,
1225 RADEON_FLAG_CPU_ACCESS);
1226 if (!event->bo) {
1227 radv_free2(&device->alloc, pAllocator, event);
1228 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1229 }
1230
1231 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
1232
1233 *pEvent = radv_event_to_handle(event);
1234
1235 return VK_SUCCESS;
1236 }
1237
1238 void radv_DestroyEvent(
1239 VkDevice _device,
1240 VkEvent _event,
1241 const VkAllocationCallbacks* pAllocator)
1242 {
1243 RADV_FROM_HANDLE(radv_device, device, _device);
1244 RADV_FROM_HANDLE(radv_event, event, _event);
1245
1246 if (!event)
1247 return;
1248 device->ws->buffer_destroy(event->bo);
1249 radv_free2(&device->alloc, pAllocator, event);
1250 }
1251
1252 VkResult radv_GetEventStatus(
1253 VkDevice _device,
1254 VkEvent _event)
1255 {
1256 RADV_FROM_HANDLE(radv_event, event, _event);
1257
1258 if (*event->map == 1)
1259 return VK_EVENT_SET;
1260 return VK_EVENT_RESET;
1261 }
1262
1263 VkResult radv_SetEvent(
1264 VkDevice _device,
1265 VkEvent _event)
1266 {
1267 RADV_FROM_HANDLE(radv_event, event, _event);
1268 *event->map = 1;
1269
1270 return VK_SUCCESS;
1271 }
1272
1273 VkResult radv_ResetEvent(
1274 VkDevice _device,
1275 VkEvent _event)
1276 {
1277 RADV_FROM_HANDLE(radv_event, event, _event);
1278 *event->map = 0;
1279
1280 return VK_SUCCESS;
1281 }
1282
1283 VkResult radv_CreateBuffer(
1284 VkDevice _device,
1285 const VkBufferCreateInfo* pCreateInfo,
1286 const VkAllocationCallbacks* pAllocator,
1287 VkBuffer* pBuffer)
1288 {
1289 RADV_FROM_HANDLE(radv_device, device, _device);
1290 struct radv_buffer *buffer;
1291
1292 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
1293
1294 buffer = radv_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
1295 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1296 if (buffer == NULL)
1297 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1298
1299 buffer->size = pCreateInfo->size;
1300 buffer->usage = pCreateInfo->usage;
1301 buffer->bo = NULL;
1302 buffer->offset = 0;
1303
1304 *pBuffer = radv_buffer_to_handle(buffer);
1305
1306 return VK_SUCCESS;
1307 }
1308
1309 void radv_DestroyBuffer(
1310 VkDevice _device,
1311 VkBuffer _buffer,
1312 const VkAllocationCallbacks* pAllocator)
1313 {
1314 RADV_FROM_HANDLE(radv_device, device, _device);
1315 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1316
1317 if (!buffer)
1318 return;
1319
1320 radv_free2(&device->alloc, pAllocator, buffer);
1321 }
1322
1323 static inline unsigned
1324 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
1325 {
1326 if (stencil)
1327 return image->surface.stencil_tiling_index[level];
1328 else
1329 return image->surface.tiling_index[level];
1330 }
1331
1332 static void
1333 radv_initialise_color_surface(struct radv_device *device,
1334 struct radv_color_buffer_info *cb,
1335 struct radv_image_view *iview)
1336 {
1337 const struct vk_format_description *desc;
1338 unsigned ntype, format, swap, endian;
1339 unsigned blend_clamp = 0, blend_bypass = 0;
1340 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
1341 uint64_t va;
1342 const struct radeon_surf *surf = &iview->image->surface;
1343 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
1344
1345 desc = vk_format_description(iview->vk_format);
1346
1347 memset(cb, 0, sizeof(*cb));
1348
1349 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1350 va += level_info->offset;
1351 cb->cb_color_base = va >> 8;
1352
1353 /* CMASK variables */
1354 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1355 va += iview->image->cmask.offset;
1356 cb->cb_color_cmask = va >> 8;
1357 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
1358
1359 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1360 va += iview->image->dcc_offset;
1361 cb->cb_dcc_base = va >> 8;
1362
1363 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
1364 S_028C6C_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1365
1366 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
1367 pitch_tile_max = level_info->nblk_x / 8 - 1;
1368 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
1369 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
1370
1371 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
1372 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
1373
1374 /* Intensity is implemented as Red, so treat it that way. */
1375 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
1376 S_028C74_TILE_MODE_INDEX(tile_mode_index);
1377
1378 if (iview->image->samples > 1) {
1379 unsigned log_samples = util_logbase2(iview->image->samples);
1380
1381 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1382 S_028C74_NUM_FRAGMENTS(log_samples);
1383 }
1384
1385 if (iview->image->fmask.size) {
1386 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
1387 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1388 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
1389 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
1390 cb->cb_color_fmask = va >> 8;
1391 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
1392 } else {
1393 /* This must be set for fast clear to work without FMASK. */
1394 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1395 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
1396 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1397 cb->cb_color_fmask = cb->cb_color_base;
1398 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
1399 }
1400
1401 ntype = radv_translate_color_numformat(iview->vk_format,
1402 desc,
1403 vk_format_get_first_non_void_channel(iview->vk_format));
1404 format = radv_translate_colorformat(iview->vk_format);
1405 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
1406 radv_finishme("Illegal color\n");
1407 swap = radv_translate_colorswap(iview->vk_format, FALSE);
1408 endian = radv_colorformat_endian_swap(format);
1409
1410 /* blend clamp should be set for all NORM/SRGB types */
1411 if (ntype == V_028C70_NUMBER_UNORM ||
1412 ntype == V_028C70_NUMBER_SNORM ||
1413 ntype == V_028C70_NUMBER_SRGB)
1414 blend_clamp = 1;
1415
1416 /* set blend bypass according to docs if SINT/UINT or
1417 8/24 COLOR variants */
1418 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1419 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1420 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1421 blend_clamp = 0;
1422 blend_bypass = 1;
1423 }
1424 #if 0
1425 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
1426 (format == V_028C70_COLOR_8 ||
1427 format == V_028C70_COLOR_8_8 ||
1428 format == V_028C70_COLOR_8_8_8_8))
1429 ->color_is_int8 = true;
1430 #endif
1431 cb->cb_color_info = S_028C70_FORMAT(format) |
1432 S_028C70_COMP_SWAP(swap) |
1433 S_028C70_BLEND_CLAMP(blend_clamp) |
1434 S_028C70_BLEND_BYPASS(blend_bypass) |
1435 S_028C70_SIMPLE_FLOAT(1) |
1436 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
1437 ntype != V_028C70_NUMBER_SNORM &&
1438 ntype != V_028C70_NUMBER_SRGB &&
1439 format != V_028C70_COLOR_8_24 &&
1440 format != V_028C70_COLOR_24_8) |
1441 S_028C70_NUMBER_TYPE(ntype) |
1442 S_028C70_ENDIAN(endian);
1443 if (iview->image->samples > 1)
1444 if (iview->image->fmask.size)
1445 cb->cb_color_info |= S_028C70_COMPRESSION(1);
1446
1447 if (iview->image->cmask.size && device->allow_fast_clears)
1448 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
1449
1450 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
1451 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
1452
1453 if (device->instance->physicalDevice.rad_info.chip_class >= VI) {
1454 unsigned max_uncompressed_block_size = 2;
1455 if (iview->image->samples > 1) {
1456 if (iview->image->surface.bpe == 1)
1457 max_uncompressed_block_size = 0;
1458 else if (iview->image->surface.bpe == 2)
1459 max_uncompressed_block_size = 1;
1460 }
1461
1462 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
1463 S_028C78_INDEPENDENT_64B_BLOCKS(1);
1464 }
1465
1466 /* This must be set for fast clear to work without FMASK. */
1467 if (!iview->image->fmask.size &&
1468 device->instance->physicalDevice.rad_info.chip_class == SI) {
1469 unsigned bankh = util_logbase2(iview->image->surface.bankh);
1470 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1471 }
1472 }
1473
1474 static void
1475 radv_initialise_ds_surface(struct radv_device *device,
1476 struct radv_ds_buffer_info *ds,
1477 struct radv_image_view *iview)
1478 {
1479 unsigned level = iview->base_mip;
1480 unsigned format;
1481 uint64_t va, s_offs, z_offs;
1482 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
1483 memset(ds, 0, sizeof(*ds));
1484 switch (iview->vk_format) {
1485 case VK_FORMAT_D24_UNORM_S8_UINT:
1486 case VK_FORMAT_X8_D24_UNORM_PACK32:
1487 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1488 ds->offset_scale = 2.0f;
1489 break;
1490 case VK_FORMAT_D16_UNORM:
1491 case VK_FORMAT_D16_UNORM_S8_UINT:
1492 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1493 ds->offset_scale = 4.0f;
1494 break;
1495 case VK_FORMAT_D32_SFLOAT:
1496 case VK_FORMAT_D32_SFLOAT_S8_UINT:
1497 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1498 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1499 ds->offset_scale = 1.0f;
1500 break;
1501 default:
1502 break;
1503 }
1504
1505 format = radv_translate_dbformat(iview->vk_format);
1506 if (format == V_028040_Z_INVALID) {
1507 fprintf(stderr, "Invalid DB format: %d, disabling DB.\n", iview->vk_format);
1508 }
1509
1510 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1511 s_offs = z_offs = va;
1512 z_offs += iview->image->surface.level[level].offset;
1513 s_offs += iview->image->surface.stencil_level[level].offset;
1514
1515 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
1516 S_028008_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1517 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1518 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
1519
1520 if (iview->image->samples > 1)
1521 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
1522
1523 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
1524 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
1525 else
1526 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1527
1528 if (device->instance->physicalDevice.rad_info.chip_class >= CIK) {
1529 struct radeon_info *info = &device->instance->physicalDevice.rad_info;
1530 unsigned tiling_index = iview->image->surface.tiling_index[level];
1531 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
1532 unsigned macro_index = iview->image->surface.macro_tile_index;
1533 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
1534 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
1535 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
1536
1537 ds->db_depth_info |=
1538 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
1539 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
1540 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
1541 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
1542 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
1543 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
1544 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
1545 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
1546 } else {
1547 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
1548 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1549 tile_mode_index = si_tile_mode_index(iview->image, level, true);
1550 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1551 }
1552
1553 if (iview->image->htile.size && !level) {
1554 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1555 S_028040_ALLOW_EXPCLEAR(1);
1556
1557 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
1558 /* Workaround: For a not yet understood reason, the
1559 * combination of MSAA, fast stencil clear and stencil
1560 * decompress messes with subsequent stencil buffer
1561 * uses. Problem was reproduced on Verde, Bonaire,
1562 * Tonga, and Carrizo.
1563 *
1564 * Disabling EXPCLEAR works around the problem.
1565 *
1566 * Check piglit's arb_texture_multisample-stencil-clear
1567 * test if you want to try changing this.
1568 */
1569 if (iview->image->samples <= 1)
1570 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
1571 } else
1572 /* Use all of the htile_buffer for depth if there's no stencil. */
1573 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1574
1575 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
1576 iview->image->htile.offset;
1577 ds->db_htile_data_base = va >> 8;
1578 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
1579 } else {
1580 ds->db_htile_data_base = 0;
1581 ds->db_htile_surface = 0;
1582 }
1583
1584 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
1585 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
1586
1587 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
1588 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
1589 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
1590 }
1591
1592 VkResult radv_CreateFramebuffer(
1593 VkDevice _device,
1594 const VkFramebufferCreateInfo* pCreateInfo,
1595 const VkAllocationCallbacks* pAllocator,
1596 VkFramebuffer* pFramebuffer)
1597 {
1598 RADV_FROM_HANDLE(radv_device, device, _device);
1599 struct radv_framebuffer *framebuffer;
1600
1601 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
1602
1603 size_t size = sizeof(*framebuffer) +
1604 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
1605 framebuffer = radv_alloc2(&device->alloc, pAllocator, size, 8,
1606 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1607 if (framebuffer == NULL)
1608 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1609
1610 framebuffer->attachment_count = pCreateInfo->attachmentCount;
1611 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
1612 VkImageView _iview = pCreateInfo->pAttachments[i];
1613 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
1614 framebuffer->attachments[i].attachment = iview;
1615 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
1616 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
1617 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
1618 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
1619 }
1620 }
1621
1622 framebuffer->width = pCreateInfo->width;
1623 framebuffer->height = pCreateInfo->height;
1624 framebuffer->layers = pCreateInfo->layers;
1625
1626 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
1627 return VK_SUCCESS;
1628 }
1629
1630 void radv_DestroyFramebuffer(
1631 VkDevice _device,
1632 VkFramebuffer _fb,
1633 const VkAllocationCallbacks* pAllocator)
1634 {
1635 RADV_FROM_HANDLE(radv_device, device, _device);
1636 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
1637
1638 if (!fb)
1639 return;
1640 radv_free2(&device->alloc, pAllocator, fb);
1641 }
1642
1643 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
1644 {
1645 switch (address_mode) {
1646 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
1647 return V_008F30_SQ_TEX_WRAP;
1648 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
1649 return V_008F30_SQ_TEX_MIRROR;
1650 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
1651 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1652 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
1653 return V_008F30_SQ_TEX_CLAMP_BORDER;
1654 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
1655 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1656 default:
1657 unreachable("illegal tex wrap mode");
1658 break;
1659 }
1660 }
1661
1662 static unsigned
1663 radv_tex_compare(VkCompareOp op)
1664 {
1665 switch (op) {
1666 case VK_COMPARE_OP_NEVER:
1667 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1668 case VK_COMPARE_OP_LESS:
1669 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1670 case VK_COMPARE_OP_EQUAL:
1671 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1672 case VK_COMPARE_OP_LESS_OR_EQUAL:
1673 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1674 case VK_COMPARE_OP_GREATER:
1675 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1676 case VK_COMPARE_OP_NOT_EQUAL:
1677 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1678 case VK_COMPARE_OP_GREATER_OR_EQUAL:
1679 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1680 case VK_COMPARE_OP_ALWAYS:
1681 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1682 default:
1683 unreachable("illegal compare mode");
1684 break;
1685 }
1686 }
1687
1688 static unsigned
1689 radv_tex_filter(VkFilter filter, unsigned max_ansio)
1690 {
1691 switch (filter) {
1692 case VK_FILTER_NEAREST:
1693 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
1694 V_008F38_SQ_TEX_XY_FILTER_POINT);
1695 case VK_FILTER_LINEAR:
1696 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
1697 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
1698 case VK_FILTER_CUBIC_IMG:
1699 default:
1700 fprintf(stderr, "illegal texture filter");
1701 return 0;
1702 }
1703 }
1704
1705 static unsigned
1706 radv_tex_mipfilter(VkSamplerMipmapMode mode)
1707 {
1708 switch (mode) {
1709 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
1710 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1711 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
1712 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1713 default:
1714 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1715 }
1716 }
1717
1718 static unsigned
1719 radv_tex_bordercolor(VkBorderColor bcolor)
1720 {
1721 switch (bcolor) {
1722 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
1723 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
1724 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
1725 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
1726 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
1727 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
1728 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
1729 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
1730 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
1731 default:
1732 break;
1733 }
1734 return 0;
1735 }
1736
1737 static void
1738 radv_init_sampler(struct radv_device *device,
1739 struct radv_sampler *sampler,
1740 const VkSamplerCreateInfo *pCreateInfo)
1741 {
1742 uint32_t max_aniso = 0;
1743 uint32_t max_aniso_ratio = 0;//TODO
1744 bool is_vi;
1745 is_vi = (device->instance->physicalDevice.rad_info.chip_class >= VI);
1746
1747 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
1748 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
1749 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
1750 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
1751 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
1752 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
1753 S_008F30_DISABLE_CUBE_WRAP(0) |
1754 S_008F30_COMPAT_MODE(is_vi));
1755 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
1756 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)));
1757 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
1758 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
1759 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
1760 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
1761 S_008F38_MIP_POINT_PRECLAMP(1) |
1762 S_008F38_DISABLE_LSB_CEIL(1) |
1763 S_008F38_FILTER_PREC_FIX(1) |
1764 S_008F38_ANISO_OVERRIDE(is_vi));
1765 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
1766 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
1767 }
1768
1769 VkResult radv_CreateSampler(
1770 VkDevice _device,
1771 const VkSamplerCreateInfo* pCreateInfo,
1772 const VkAllocationCallbacks* pAllocator,
1773 VkSampler* pSampler)
1774 {
1775 RADV_FROM_HANDLE(radv_device, device, _device);
1776 struct radv_sampler *sampler;
1777
1778 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
1779
1780 sampler = radv_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
1781 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1782 if (!sampler)
1783 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1784
1785 radv_init_sampler(device, sampler, pCreateInfo);
1786 *pSampler = radv_sampler_to_handle(sampler);
1787
1788 return VK_SUCCESS;
1789 }
1790
1791 void radv_DestroySampler(
1792 VkDevice _device,
1793 VkSampler _sampler,
1794 const VkAllocationCallbacks* pAllocator)
1795 {
1796 RADV_FROM_HANDLE(radv_device, device, _device);
1797 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
1798
1799 if (!sampler)
1800 return;
1801 radv_free2(&device->alloc, pAllocator, sampler);
1802 }