2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
40 #include <sys/prctl.h>
44 #include <llvm/Config/llvm-config.h>
46 #include "radv_debug.h"
47 #include "radv_private.h"
48 #include "radv_shader.h"
50 #include "util/disk_cache.h"
54 #include <amdgpu_drm.h>
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "ac_llvm_util.h"
57 #include "vk_format.h"
60 #include "util/build_id.h"
61 #include "util/debug.h"
62 #include "util/mesa-sha1.h"
63 #include "util/timespec.h"
64 #include "util/u_atomic.h"
65 #include "compiler/glsl_types.h"
66 #include "util/xmlpool.h"
68 static struct radv_timeline_point
*
69 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
70 struct radv_timeline
*timeline
,
73 static struct radv_timeline_point
*
74 radv_timeline_add_point_locked(struct radv_device
*device
,
75 struct radv_timeline
*timeline
,
79 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
80 struct list_head
*processing_list
);
83 void radv_destroy_semaphore_part(struct radv_device
*device
,
84 struct radv_semaphore_part
*part
);
87 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
90 unsigned char sha1
[20];
91 unsigned ptr_size
= sizeof(void*);
93 memset(uuid
, 0, VK_UUID_SIZE
);
94 _mesa_sha1_init(&ctx
);
96 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
97 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
100 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
101 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
102 _mesa_sha1_final(&ctx
, sha1
);
104 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
109 radv_get_driver_uuid(void *uuid
)
111 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
115 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
117 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
121 radv_get_visible_vram_size(struct radv_physical_device
*device
)
123 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
127 radv_get_vram_size(struct radv_physical_device
*device
)
129 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
133 radv_is_mem_type_vram(enum radv_mem_type type
)
135 return type
== RADV_MEM_TYPE_VRAM
||
136 type
== RADV_MEM_TYPE_VRAM_UNCACHED
;
140 radv_is_mem_type_vram_visible(enum radv_mem_type type
)
142 return type
== RADV_MEM_TYPE_VRAM_CPU_ACCESS
||
143 type
== RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
;
146 radv_is_mem_type_gtt_wc(enum radv_mem_type type
)
148 return type
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
149 type
== RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
;
153 radv_is_mem_type_gtt_cached(enum radv_mem_type type
)
155 return type
== RADV_MEM_TYPE_GTT_CACHED
||
156 type
== RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
;
160 radv_is_mem_type_uncached(enum radv_mem_type type
)
162 return type
== RADV_MEM_TYPE_VRAM_UNCACHED
||
163 type
== RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
||
164 type
== RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
||
165 type
== RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
;
169 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
171 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
172 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
173 uint64_t vram_size
= radv_get_vram_size(device
);
174 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
175 device
->memory_properties
.memoryHeapCount
= 0;
177 vram_index
= device
->memory_properties
.memoryHeapCount
++;
178 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
180 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
183 if (visible_vram_size
) {
184 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
185 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
186 .size
= visible_vram_size
,
187 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
190 if (device
->rad_info
.gart_size
> 0) {
191 gart_index
= device
->memory_properties
.memoryHeapCount
++;
192 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
193 .size
= device
->rad_info
.gart_size
,
194 .flags
= device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
198 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
199 unsigned type_count
= 0;
200 if (vram_index
>= 0) {
201 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM
;
202 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
203 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
204 .heapIndex
= vram_index
,
207 if (gart_index
>= 0 && device
->rad_info
.has_dedicated_vram
) {
208 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
209 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
210 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
211 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
212 .heapIndex
= gart_index
,
215 if (visible_vram_index
>= 0) {
216 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM_CPU_ACCESS
;
217 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
218 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
219 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
220 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
221 .heapIndex
= visible_vram_index
,
224 if (gart_index
>= 0 && !device
->rad_info
.has_dedicated_vram
) {
225 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
226 * as they have identical property flags, and according to the
227 * spec, for types with identical flags, the one with greater
228 * performance must be given a lower index. */
229 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
230 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
231 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
232 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
233 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
234 .heapIndex
= gart_index
,
237 if (gart_index
>= 0) {
238 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_CACHED
;
239 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
240 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
241 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
242 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
|
243 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
244 .heapIndex
= gart_index
,
247 device
->memory_properties
.memoryTypeCount
= type_count
;
249 if (device
->rad_info
.has_l2_uncached
) {
250 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
251 VkMemoryType mem_type
= device
->memory_properties
.memoryTypes
[i
];
253 if ((mem_type
.propertyFlags
& (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
254 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
)) ||
255 mem_type
.propertyFlags
== VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
) {
256 enum radv_mem_type mem_type_id
;
258 switch (device
->mem_type_indices
[i
]) {
259 case RADV_MEM_TYPE_VRAM
:
260 mem_type_id
= RADV_MEM_TYPE_VRAM_UNCACHED
;
262 case RADV_MEM_TYPE_VRAM_CPU_ACCESS
:
263 mem_type_id
= RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
;
265 case RADV_MEM_TYPE_GTT_WRITE_COMBINE
:
266 mem_type_id
= RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
;
268 case RADV_MEM_TYPE_GTT_CACHED
:
269 mem_type_id
= RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
;
272 unreachable("invalid memory type");
275 VkMemoryPropertyFlags property_flags
= mem_type
.propertyFlags
|
276 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD
|
277 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD
;
279 device
->mem_type_indices
[type_count
] = mem_type_id
;
280 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
281 .propertyFlags
= property_flags
,
282 .heapIndex
= mem_type
.heapIndex
,
286 device
->memory_properties
.memoryTypeCount
= type_count
;
291 radv_handle_env_var_force_family(struct radv_physical_device
*device
)
293 const char *family
= getenv("RADV_FORCE_FAMILY");
299 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
300 if (!strcmp(family
, ac_get_llvm_processor_name(i
))) {
301 /* Override family and chip_class. */
302 device
->rad_info
.family
= i
;
304 if (i
>= CHIP_NAVI10
)
305 device
->rad_info
.chip_class
= GFX10
;
306 else if (i
>= CHIP_VEGA10
)
307 device
->rad_info
.chip_class
= GFX9
;
308 else if (i
>= CHIP_TONGA
)
309 device
->rad_info
.chip_class
= GFX8
;
310 else if (i
>= CHIP_BONAIRE
)
311 device
->rad_info
.chip_class
= GFX7
;
313 device
->rad_info
.chip_class
= GFX6
;
319 fprintf(stderr
, "radv: Unknown family: %s\n", family
);
324 radv_physical_device_init(struct radv_physical_device
*device
,
325 struct radv_instance
*instance
,
326 drmDevicePtr drm_device
)
328 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
330 drmVersionPtr version
;
334 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
336 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
337 radv_logi("Could not open device '%s'", path
);
339 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
342 version
= drmGetVersion(fd
);
346 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
347 radv_logi("Could not get the kernel driver version for device '%s'", path
);
349 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
350 "failed to get version %s: %m", path
);
353 if (strcmp(version
->name
, "amdgpu")) {
354 drmFreeVersion(version
);
357 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
358 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
360 return VK_ERROR_INCOMPATIBLE_DRIVER
;
362 drmFreeVersion(version
);
364 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
365 radv_logi("Found compatible device '%s'.", path
);
367 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
368 device
->instance
= instance
;
370 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
371 instance
->perftest_flags
);
373 result
= vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
377 if (instance
->enabled_extensions
.KHR_display
) {
378 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
379 if (master_fd
>= 0) {
380 uint32_t accel_working
= 0;
381 struct drm_amdgpu_info request
= {
382 .return_pointer
= (uintptr_t)&accel_working
,
383 .return_size
= sizeof(accel_working
),
384 .query
= AMDGPU_INFO_ACCEL_WORKING
387 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
394 device
->master_fd
= master_fd
;
395 device
->local_fd
= fd
;
396 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
398 radv_handle_env_var_force_family(device
);
400 device
->use_aco
= instance
->perftest_flags
& RADV_PERFTEST_ACO
;
402 snprintf(device
->name
, sizeof(device
->name
),
403 "AMD RADV%s %s (LLVM " MESA_LLVM_VERSION_STRING
")", device
->use_aco
? "/ACO" : "",
404 device
->rad_info
.name
);
406 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
407 device
->ws
->destroy(device
->ws
);
408 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
409 "cannot generate UUID");
413 /* These flags affect shader compilation. */
414 uint64_t shader_env_flags
=
415 (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
? 0x1 : 0) |
416 (device
->use_aco
? 0x2 : 0);
418 /* The gpu id is already embedded in the uuid so we just pass "radv"
419 * when creating the cache.
421 char buf
[VK_UUID_SIZE
* 2 + 1];
422 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
423 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
425 if (device
->rad_info
.chip_class
< GFX8
)
426 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
428 radv_get_driver_uuid(&device
->driver_uuid
);
429 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
431 device
->out_of_order_rast_allowed
= device
->rad_info
.has_out_of_order_rast
&&
432 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
434 device
->dcc_msaa_allowed
=
435 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
437 device
->use_shader_ballot
= (device
->use_aco
&& device
->rad_info
.chip_class
>= GFX8
) ||
438 (device
->instance
->perftest_flags
& RADV_PERFTEST_SHADER_BALLOT
);
440 device
->use_ngg
= device
->rad_info
.chip_class
>= GFX10
&&
441 device
->rad_info
.family
!= CHIP_NAVI14
&&
442 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
);
443 if (device
->use_aco
&& device
->use_ngg
) {
444 fprintf(stderr
, "WARNING: disabling NGG because ACO is used.\n");
445 device
->use_ngg
= false;
448 device
->use_ngg_streamout
= false;
450 /* Determine the number of threads per wave for all stages. */
451 device
->cs_wave_size
= 64;
452 device
->ps_wave_size
= 64;
453 device
->ge_wave_size
= 64;
455 if (device
->rad_info
.chip_class
>= GFX10
) {
456 if (device
->instance
->perftest_flags
& RADV_PERFTEST_CS_WAVE_32
)
457 device
->cs_wave_size
= 32;
459 /* For pixel shaders, wave64 is recommanded. */
460 if (device
->instance
->perftest_flags
& RADV_PERFTEST_PS_WAVE_32
)
461 device
->ps_wave_size
= 32;
463 if (device
->instance
->perftest_flags
& RADV_PERFTEST_GE_WAVE_32
)
464 device
->ge_wave_size
= 32;
467 radv_physical_device_init_mem_types(device
);
468 radv_fill_device_extension_table(device
, &device
->supported_extensions
);
470 device
->bus_info
= *drm_device
->businfo
.pci
;
472 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
473 ac_print_gpu_info(&device
->rad_info
);
475 /* The WSI is structured as a layer on top of the driver, so this has
476 * to be the last part of initialization (at least until we get other
479 result
= radv_init_wsi(device
);
480 if (result
!= VK_SUCCESS
) {
481 device
->ws
->destroy(device
->ws
);
482 vk_error(instance
, result
);
496 radv_physical_device_finish(struct radv_physical_device
*device
)
498 radv_finish_wsi(device
);
499 device
->ws
->destroy(device
->ws
);
500 disk_cache_destroy(device
->disk_cache
);
501 close(device
->local_fd
);
502 if (device
->master_fd
!= -1)
503 close(device
->master_fd
);
507 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
508 VkSystemAllocationScope allocationScope
)
514 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
515 size_t align
, VkSystemAllocationScope allocationScope
)
517 return realloc(pOriginal
, size
);
521 default_free_func(void *pUserData
, void *pMemory
)
526 static const VkAllocationCallbacks default_alloc
= {
528 .pfnAllocation
= default_alloc_func
,
529 .pfnReallocation
= default_realloc_func
,
530 .pfnFree
= default_free_func
,
533 static const struct debug_control radv_debug_options
[] = {
534 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
535 {"nodcc", RADV_DEBUG_NO_DCC
},
536 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
537 {"nocache", RADV_DEBUG_NO_CACHE
},
538 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
539 {"nohiz", RADV_DEBUG_NO_HIZ
},
540 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
541 {"allbos", RADV_DEBUG_ALL_BOS
},
542 {"noibs", RADV_DEBUG_NO_IBS
},
543 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
544 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
545 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
546 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
547 {"nosisched", RADV_DEBUG_NO_SISCHED
},
548 {"preoptir", RADV_DEBUG_PREOPTIR
},
549 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
550 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
551 {"info", RADV_DEBUG_INFO
},
552 {"errors", RADV_DEBUG_ERRORS
},
553 {"startup", RADV_DEBUG_STARTUP
},
554 {"checkir", RADV_DEBUG_CHECKIR
},
555 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
556 {"nobinning", RADV_DEBUG_NOBINNING
},
557 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT
},
558 {"nongg", RADV_DEBUG_NO_NGG
},
559 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT
},
560 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS
},
561 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS
},
562 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE
},
567 radv_get_debug_option_name(int id
)
569 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
570 return radv_debug_options
[id
].string
;
573 static const struct debug_control radv_perftest_options
[] = {
574 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN
},
575 {"sisched", RADV_PERFTEST_SISCHED
},
576 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
577 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
578 {"bolist", RADV_PERFTEST_BO_LIST
},
579 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT
},
580 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK
},
581 {"cswave32", RADV_PERFTEST_CS_WAVE_32
},
582 {"pswave32", RADV_PERFTEST_PS_WAVE_32
},
583 {"gewave32", RADV_PERFTEST_GE_WAVE_32
},
584 {"dfsm", RADV_PERFTEST_DFSM
},
585 {"aco", RADV_PERFTEST_ACO
},
590 radv_get_perftest_option_name(int id
)
592 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
593 return radv_perftest_options
[id
].string
;
597 radv_handle_per_app_options(struct radv_instance
*instance
,
598 const VkApplicationInfo
*info
)
600 const char *name
= info
? info
->pApplicationName
: NULL
;
605 if (!strcmp(name
, "Talos - Linux - 32bit") ||
606 !strcmp(name
, "Talos - Linux - 64bit")) {
607 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SISCHED
)) {
608 /* Force enable LLVM sisched for Talos because it looks
609 * safe and it gives few more FPS.
611 instance
->perftest_flags
|= RADV_PERFTEST_SISCHED
;
613 } else if (!strcmp(name
, "DOOM_VFR")) {
614 /* Work around a Doom VFR game bug */
615 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
616 } else if (!strcmp(name
, "MonsterHunterWorld.exe")) {
617 /* Workaround for a WaW hazard when LLVM moves/merges
618 * load/store memory operations.
619 * See https://reviews.llvm.org/D61313
621 if (LLVM_VERSION_MAJOR
< 9)
622 instance
->debug_flags
|= RADV_DEBUG_NO_LOAD_STORE_OPT
;
623 } else if (!strcmp(name
, "Wolfenstein: Youngblood")) {
624 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SHADER_BALLOT
) &&
625 !(instance
->perftest_flags
& RADV_PERFTEST_ACO
)) {
626 /* Force enable VK_AMD_shader_ballot because it looks
627 * safe and it gives a nice boost (+20% on Vega 56 at
628 * this time). It also prevents corruption on LLVM.
630 instance
->perftest_flags
|= RADV_PERFTEST_SHADER_BALLOT
;
632 } else if (!strcmp(name
, "Fledge")) {
634 * Zero VRAM for "The Surge 2"
636 * This avoid a hang when when rendering any level. Likely
637 * uninitialized data in an indirect draw.
639 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
;
643 static int radv_get_instance_extension_index(const char *name
)
645 for (unsigned i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; ++i
) {
646 if (strcmp(name
, radv_instance_extensions
[i
].extensionName
) == 0)
652 static const char radv_dri_options_xml
[] =
654 DRI_CONF_SECTION_PERFORMANCE
655 DRI_CONF_ADAPTIVE_SYNC("true")
656 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
657 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
660 DRI_CONF_SECTION_DEBUG
661 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
665 static void radv_init_dri_options(struct radv_instance
*instance
)
667 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
668 driParseConfigFiles(&instance
->dri_options
,
669 &instance
->available_dri_options
,
671 instance
->engineName
,
672 instance
->engineVersion
);
675 VkResult
radv_CreateInstance(
676 const VkInstanceCreateInfo
* pCreateInfo
,
677 const VkAllocationCallbacks
* pAllocator
,
678 VkInstance
* pInstance
)
680 struct radv_instance
*instance
;
683 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
685 uint32_t client_version
;
686 if (pCreateInfo
->pApplicationInfo
&&
687 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
688 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
690 client_version
= VK_API_VERSION_1_0
;
693 const char *engine_name
= NULL
;
694 uint32_t engine_version
= 0;
695 if (pCreateInfo
->pApplicationInfo
) {
696 engine_name
= pCreateInfo
->pApplicationInfo
->pEngineName
;
697 engine_version
= pCreateInfo
->pApplicationInfo
->engineVersion
;
700 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
701 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
703 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
705 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
708 instance
->alloc
= *pAllocator
;
710 instance
->alloc
= default_alloc
;
712 instance
->apiVersion
= client_version
;
713 instance
->physicalDeviceCount
= -1;
715 /* Get secure compile thread count. NOTE: We cap this at 32 */
716 #define MAX_SC_PROCS 32
717 char *num_sc_threads
= getenv("RADV_SECURE_COMPILE_THREADS");
719 instance
->num_sc_threads
= MIN2(strtoul(num_sc_threads
, NULL
, 10), MAX_SC_PROCS
);
721 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
724 /* Disable memory cache when secure compile is set */
725 if (radv_device_use_secure_compile(instance
))
726 instance
->debug_flags
|= RADV_DEBUG_NO_MEMORY_CACHE
;
728 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
729 radv_perftest_options
);
731 if (instance
->perftest_flags
& RADV_PERFTEST_ACO
)
732 fprintf(stderr
, "WARNING: Experimental compiler backend enabled. Here be dragons! Incorrect rendering, GPU hangs and/or resets are likely\n");
734 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
735 radv_logi("Created an instance");
737 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
738 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
739 int index
= radv_get_instance_extension_index(ext_name
);
741 if (index
< 0 || !radv_supported_instance_extensions
.extensions
[index
]) {
742 vk_free2(&default_alloc
, pAllocator
, instance
);
743 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
746 instance
->enabled_extensions
.extensions
[index
] = true;
749 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
750 if (result
!= VK_SUCCESS
) {
751 vk_free2(&default_alloc
, pAllocator
, instance
);
752 return vk_error(instance
, result
);
755 instance
->engineName
= vk_strdup(&instance
->alloc
, engine_name
,
756 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
757 instance
->engineVersion
= engine_version
;
759 glsl_type_singleton_init_or_ref();
761 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
763 radv_init_dri_options(instance
);
764 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
766 *pInstance
= radv_instance_to_handle(instance
);
771 void radv_DestroyInstance(
772 VkInstance _instance
,
773 const VkAllocationCallbacks
* pAllocator
)
775 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
780 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
781 radv_physical_device_finish(instance
->physicalDevices
+ i
);
784 vk_free(&instance
->alloc
, instance
->engineName
);
786 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
788 glsl_type_singleton_decref();
790 driDestroyOptionCache(&instance
->dri_options
);
791 driDestroyOptionInfo(&instance
->available_dri_options
);
793 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
795 vk_free(&instance
->alloc
, instance
);
799 radv_enumerate_devices(struct radv_instance
*instance
)
801 /* TODO: Check for more devices ? */
802 drmDevicePtr devices
[8];
803 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
806 instance
->physicalDeviceCount
= 0;
808 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
810 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
811 radv_logi("Found %d drm nodes", max_devices
);
814 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
816 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
817 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
818 devices
[i
]->bustype
== DRM_BUS_PCI
&&
819 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
821 result
= radv_physical_device_init(instance
->physicalDevices
+
822 instance
->physicalDeviceCount
,
825 if (result
== VK_SUCCESS
)
826 ++instance
->physicalDeviceCount
;
827 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
831 drmFreeDevices(devices
, max_devices
);
836 VkResult
radv_EnumeratePhysicalDevices(
837 VkInstance _instance
,
838 uint32_t* pPhysicalDeviceCount
,
839 VkPhysicalDevice
* pPhysicalDevices
)
841 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
844 if (instance
->physicalDeviceCount
< 0) {
845 result
= radv_enumerate_devices(instance
);
846 if (result
!= VK_SUCCESS
&&
847 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
851 if (!pPhysicalDevices
) {
852 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
854 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
855 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
856 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
859 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
863 VkResult
radv_EnumeratePhysicalDeviceGroups(
864 VkInstance _instance
,
865 uint32_t* pPhysicalDeviceGroupCount
,
866 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
868 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
871 if (instance
->physicalDeviceCount
< 0) {
872 result
= radv_enumerate_devices(instance
);
873 if (result
!= VK_SUCCESS
&&
874 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
878 if (!pPhysicalDeviceGroupProperties
) {
879 *pPhysicalDeviceGroupCount
= instance
->physicalDeviceCount
;
881 *pPhysicalDeviceGroupCount
= MIN2(*pPhysicalDeviceGroupCount
, instance
->physicalDeviceCount
);
882 for (unsigned i
= 0; i
< *pPhysicalDeviceGroupCount
; ++i
) {
883 pPhysicalDeviceGroupProperties
[i
].physicalDeviceCount
= 1;
884 pPhysicalDeviceGroupProperties
[i
].physicalDevices
[0] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
885 pPhysicalDeviceGroupProperties
[i
].subsetAllocation
= false;
888 return *pPhysicalDeviceGroupCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
892 void radv_GetPhysicalDeviceFeatures(
893 VkPhysicalDevice physicalDevice
,
894 VkPhysicalDeviceFeatures
* pFeatures
)
896 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
897 memset(pFeatures
, 0, sizeof(*pFeatures
));
899 *pFeatures
= (VkPhysicalDeviceFeatures
) {
900 .robustBufferAccess
= true,
901 .fullDrawIndexUint32
= true,
902 .imageCubeArray
= true,
903 .independentBlend
= true,
904 .geometryShader
= true,
905 .tessellationShader
= true,
906 .sampleRateShading
= true,
907 .dualSrcBlend
= true,
909 .multiDrawIndirect
= true,
910 .drawIndirectFirstInstance
= true,
912 .depthBiasClamp
= true,
913 .fillModeNonSolid
= true,
918 .multiViewport
= true,
919 .samplerAnisotropy
= true,
920 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
921 .textureCompressionASTC_LDR
= false,
922 .textureCompressionBC
= true,
923 .occlusionQueryPrecise
= true,
924 .pipelineStatisticsQuery
= true,
925 .vertexPipelineStoresAndAtomics
= true,
926 .fragmentStoresAndAtomics
= true,
927 .shaderTessellationAndGeometryPointSize
= true,
928 .shaderImageGatherExtended
= true,
929 .shaderStorageImageExtendedFormats
= true,
930 .shaderStorageImageMultisample
= pdevice
->rad_info
.chip_class
>= GFX8
,
931 .shaderUniformBufferArrayDynamicIndexing
= true,
932 .shaderSampledImageArrayDynamicIndexing
= true,
933 .shaderStorageBufferArrayDynamicIndexing
= true,
934 .shaderStorageImageArrayDynamicIndexing
= true,
935 .shaderStorageImageReadWithoutFormat
= true,
936 .shaderStorageImageWriteWithoutFormat
= true,
937 .shaderClipDistance
= true,
938 .shaderCullDistance
= true,
939 .shaderFloat64
= true,
941 .shaderInt16
= pdevice
->rad_info
.chip_class
>= GFX9
&& !pdevice
->use_aco
,
942 .sparseBinding
= true,
943 .variableMultisampleRate
= true,
944 .inheritedQueries
= true,
948 void radv_GetPhysicalDeviceFeatures2(
949 VkPhysicalDevice physicalDevice
,
950 VkPhysicalDeviceFeatures2
*pFeatures
)
952 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
953 vk_foreach_struct(ext
, pFeatures
->pNext
) {
954 switch (ext
->sType
) {
955 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES
: {
956 VkPhysicalDeviceVariablePointersFeatures
*features
= (void *)ext
;
957 features
->variablePointersStorageBuffer
= true;
958 features
->variablePointers
= true;
961 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
962 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
963 features
->multiview
= true;
964 features
->multiviewGeometryShader
= true;
965 features
->multiviewTessellationShader
= true;
968 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES
: {
969 VkPhysicalDeviceShaderDrawParametersFeatures
*features
=
970 (VkPhysicalDeviceShaderDrawParametersFeatures
*)ext
;
971 features
->shaderDrawParameters
= true;
974 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
975 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
976 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
977 features
->protectedMemory
= false;
980 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
981 VkPhysicalDevice16BitStorageFeatures
*features
=
982 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
983 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
984 features
->storageBuffer16BitAccess
= enabled
;
985 features
->uniformAndStorageBuffer16BitAccess
= enabled
;
986 features
->storagePushConstant16
= enabled
;
987 features
->storageInputOutput16
= enabled
&& LLVM_VERSION_MAJOR
>= 9;
990 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
991 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
992 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
993 features
->samplerYcbcrConversion
= true;
996 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES
: {
997 VkPhysicalDeviceDescriptorIndexingFeatures
*features
=
998 (VkPhysicalDeviceDescriptorIndexingFeatures
*)ext
;
999 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
1000 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
1001 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
1002 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
1003 features
->shaderSampledImageArrayNonUniformIndexing
= true;
1004 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
1005 features
->shaderStorageImageArrayNonUniformIndexing
= true;
1006 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
1007 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
1008 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
1009 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
1010 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
1011 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
1012 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
1013 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
1014 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
1015 features
->descriptorBindingUpdateUnusedWhilePending
= true;
1016 features
->descriptorBindingPartiallyBound
= true;
1017 features
->descriptorBindingVariableDescriptorCount
= true;
1018 features
->runtimeDescriptorArray
= true;
1021 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
1022 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
1023 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
1024 features
->conditionalRendering
= true;
1025 features
->inheritedConditionalRendering
= false;
1028 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
1029 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
1030 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
1031 features
->vertexAttributeInstanceRateDivisor
= true;
1032 features
->vertexAttributeInstanceRateZeroDivisor
= true;
1035 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
1036 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
1037 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
1038 features
->transformFeedback
= true;
1039 features
->geometryStreams
= !pdevice
->use_ngg_streamout
;
1042 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES
: {
1043 VkPhysicalDeviceScalarBlockLayoutFeatures
*features
=
1044 (VkPhysicalDeviceScalarBlockLayoutFeatures
*)ext
;
1045 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
1048 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
1049 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
1050 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
1051 features
->memoryPriority
= true;
1054 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT
: {
1055 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*features
=
1056 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*)ext
;
1057 features
->bufferDeviceAddress
= true;
1058 features
->bufferDeviceAddressCaptureReplay
= false;
1059 features
->bufferDeviceAddressMultiDevice
= false;
1062 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES
: {
1063 VkPhysicalDeviceBufferDeviceAddressFeatures
*features
=
1064 (VkPhysicalDeviceBufferDeviceAddressFeatures
*)ext
;
1065 features
->bufferDeviceAddress
= true;
1066 features
->bufferDeviceAddressCaptureReplay
= false;
1067 features
->bufferDeviceAddressMultiDevice
= false;
1070 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
1071 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
1072 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
1073 features
->depthClipEnable
= true;
1076 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES
: {
1077 VkPhysicalDeviceHostQueryResetFeatures
*features
=
1078 (VkPhysicalDeviceHostQueryResetFeatures
*)ext
;
1079 features
->hostQueryReset
= true;
1082 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES
: {
1083 VkPhysicalDevice8BitStorageFeatures
*features
=
1084 (VkPhysicalDevice8BitStorageFeatures
*)ext
;
1085 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1086 features
->storageBuffer8BitAccess
= enabled
;
1087 features
->uniformAndStorageBuffer8BitAccess
= enabled
;
1088 features
->storagePushConstant8
= enabled
;
1091 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES
: {
1092 VkPhysicalDeviceShaderFloat16Int8Features
*features
=
1093 (VkPhysicalDeviceShaderFloat16Int8Features
*)ext
;
1094 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1095 features
->shaderInt8
= !pdevice
->use_aco
;
1098 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES
: {
1099 VkPhysicalDeviceShaderAtomicInt64Features
*features
=
1100 (VkPhysicalDeviceShaderAtomicInt64Features
*)ext
;
1101 features
->shaderBufferInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1102 features
->shaderSharedInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1105 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT
: {
1106 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*features
=
1107 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*)ext
;
1108 features
->shaderDemoteToHelperInvocation
= pdevice
->use_aco
;
1111 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
1112 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
1113 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
1115 features
->inlineUniformBlock
= true;
1116 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
1119 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
1120 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
1121 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
1122 features
->computeDerivativeGroupQuads
= false;
1123 features
->computeDerivativeGroupLinear
= true;
1126 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT
: {
1127 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*features
=
1128 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*)ext
;
1129 features
->ycbcrImageArrays
= true;
1132 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES
: {
1133 VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*features
=
1134 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*)ext
;
1135 features
->uniformBufferStandardLayout
= true;
1138 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT
: {
1139 VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*features
=
1140 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*)ext
;
1141 features
->indexTypeUint8
= pdevice
->rad_info
.chip_class
>= GFX8
;
1144 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES
: {
1145 VkPhysicalDeviceImagelessFramebufferFeatures
*features
=
1146 (VkPhysicalDeviceImagelessFramebufferFeatures
*)ext
;
1147 features
->imagelessFramebuffer
= true;
1150 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR
: {
1151 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*features
=
1152 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*)ext
;
1153 features
->pipelineExecutableInfo
= true;
1156 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR
: {
1157 VkPhysicalDeviceShaderClockFeaturesKHR
*features
=
1158 (VkPhysicalDeviceShaderClockFeaturesKHR
*)ext
;
1159 features
->shaderSubgroupClock
= true;
1160 features
->shaderDeviceClock
= false;
1163 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT
: {
1164 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*features
=
1165 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*)ext
;
1166 features
->texelBufferAlignment
= true;
1169 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES
: {
1170 VkPhysicalDeviceTimelineSemaphoreFeatures
*features
=
1171 (VkPhysicalDeviceTimelineSemaphoreFeatures
*) ext
;
1172 features
->timelineSemaphore
= true;
1175 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT
: {
1176 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*features
=
1177 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*)ext
;
1178 features
->subgroupSizeControl
= true;
1179 features
->computeFullSubgroups
= true;
1182 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD
: {
1183 VkPhysicalDeviceCoherentMemoryFeaturesAMD
*features
=
1184 (VkPhysicalDeviceCoherentMemoryFeaturesAMD
*)ext
;
1185 features
->deviceCoherentMemory
= pdevice
->rad_info
.has_l2_uncached
;
1188 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES
: {
1189 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*features
=
1190 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*)ext
;
1191 features
->shaderSubgroupExtendedTypes
= true;
1194 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR
: {
1195 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*features
=
1196 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*)ext
;
1197 features
->separateDepthStencilLayouts
= true;
1200 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES
: {
1201 VkPhysicalDeviceVulkan11Features
*features
=
1202 (VkPhysicalDeviceVulkan11Features
*)ext
;
1203 features
->storageBuffer16BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1204 features
->uniformAndStorageBuffer16BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1205 features
->storagePushConstant16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1206 features
->storageInputOutput16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
&& LLVM_VERSION_MAJOR
>= 9;
1207 features
->multiview
= true;
1208 features
->multiviewGeometryShader
= true;
1209 features
->multiviewTessellationShader
= true;
1210 features
->variablePointersStorageBuffer
= true;
1211 features
->variablePointers
= true;
1212 features
->protectedMemory
= false;
1213 features
->samplerYcbcrConversion
= true;
1214 features
->shaderDrawParameters
= true;
1217 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES
: {
1218 VkPhysicalDeviceVulkan12Features
*features
=
1219 (VkPhysicalDeviceVulkan12Features
*)ext
;
1220 features
->samplerMirrorClampToEdge
= true;
1221 features
->drawIndirectCount
= true;
1222 features
->storageBuffer8BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1223 features
->uniformAndStorageBuffer8BitAccess
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1224 features
->storagePushConstant8
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1225 features
->shaderBufferInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1226 features
->shaderSharedInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1227 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
1228 features
->shaderInt8
= !pdevice
->use_aco
;
1229 features
->descriptorIndexing
= true;
1230 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
1231 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
1232 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
1233 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
1234 features
->shaderSampledImageArrayNonUniformIndexing
= true;
1235 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
1236 features
->shaderStorageImageArrayNonUniformIndexing
= true;
1237 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
1238 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
1239 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
1240 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
1241 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
1242 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
1243 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
1244 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
1245 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
1246 features
->descriptorBindingUpdateUnusedWhilePending
= true;
1247 features
->descriptorBindingPartiallyBound
= true;
1248 features
->descriptorBindingVariableDescriptorCount
= true;
1249 features
->runtimeDescriptorArray
= true;
1250 features
->samplerFilterMinmax
= pdevice
->rad_info
.chip_class
>= GFX7
;
1251 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
1252 features
->imagelessFramebuffer
= true;
1253 features
->uniformBufferStandardLayout
= true;
1254 features
->shaderSubgroupExtendedTypes
= true;
1255 features
->separateDepthStencilLayouts
= true;
1256 features
->hostQueryReset
= true;
1257 features
->timelineSemaphore
= pdevice
->rad_info
.has_syncobj_wait_for_submit
;
1258 features
->bufferDeviceAddress
= true;
1259 features
->bufferDeviceAddressCaptureReplay
= false;
1260 features
->bufferDeviceAddressMultiDevice
= false;
1261 features
->vulkanMemoryModel
= false;
1262 features
->vulkanMemoryModelDeviceScope
= false;
1263 features
->vulkanMemoryModelAvailabilityVisibilityChains
= false;
1264 features
->shaderOutputViewportIndex
= true;
1265 features
->shaderOutputLayer
= true;
1266 features
->subgroupBroadcastDynamicId
= true;
1273 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
1277 radv_max_descriptor_set_size()
1279 /* make sure that the entire descriptor set is addressable with a signed
1280 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1281 * be at most 2 GiB. the combined image & samples object count as one of
1282 * both. This limit is for the pipeline layout, not for the set layout, but
1283 * there is no set limit, so we just set a pipeline limit. I don't think
1284 * any app is going to hit this soon. */
1285 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1286 - MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1287 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1288 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1289 32 /* sampler, largest when combined with image */ +
1290 64 /* sampled image */ +
1291 64 /* storage image */);
1294 void radv_GetPhysicalDeviceProperties(
1295 VkPhysicalDevice physicalDevice
,
1296 VkPhysicalDeviceProperties
* pProperties
)
1298 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1299 VkSampleCountFlags sample_counts
= 0xf;
1301 size_t max_descriptor_set_size
= radv_max_descriptor_set_size();
1303 VkPhysicalDeviceLimits limits
= {
1304 .maxImageDimension1D
= (1 << 14),
1305 .maxImageDimension2D
= (1 << 14),
1306 .maxImageDimension3D
= (1 << 11),
1307 .maxImageDimensionCube
= (1 << 14),
1308 .maxImageArrayLayers
= (1 << 11),
1309 .maxTexelBufferElements
= 128 * 1024 * 1024,
1310 .maxUniformBufferRange
= UINT32_MAX
,
1311 .maxStorageBufferRange
= UINT32_MAX
,
1312 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
1313 .maxMemoryAllocationCount
= UINT32_MAX
,
1314 .maxSamplerAllocationCount
= 64 * 1024,
1315 .bufferImageGranularity
= 64, /* A cache line */
1316 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
1317 .maxBoundDescriptorSets
= MAX_SETS
,
1318 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
1319 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
1320 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
1321 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
1322 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1323 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1324 .maxPerStageResources
= max_descriptor_set_size
,
1325 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1326 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1327 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1328 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1329 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1330 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1331 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1332 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1333 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1334 .maxVertexInputBindings
= MAX_VBS
,
1335 .maxVertexInputAttributeOffset
= 2047,
1336 .maxVertexInputBindingStride
= 2048,
1337 .maxVertexOutputComponents
= 128,
1338 .maxTessellationGenerationLevel
= 64,
1339 .maxTessellationPatchSize
= 32,
1340 .maxTessellationControlPerVertexInputComponents
= 128,
1341 .maxTessellationControlPerVertexOutputComponents
= 128,
1342 .maxTessellationControlPerPatchOutputComponents
= 120,
1343 .maxTessellationControlTotalOutputComponents
= 4096,
1344 .maxTessellationEvaluationInputComponents
= 128,
1345 .maxTessellationEvaluationOutputComponents
= 128,
1346 .maxGeometryShaderInvocations
= 127,
1347 .maxGeometryInputComponents
= 64,
1348 .maxGeometryOutputComponents
= 128,
1349 .maxGeometryOutputVertices
= 256,
1350 .maxGeometryTotalOutputComponents
= 1024,
1351 .maxFragmentInputComponents
= 128,
1352 .maxFragmentOutputAttachments
= 8,
1353 .maxFragmentDualSrcAttachments
= 1,
1354 .maxFragmentCombinedOutputResources
= 8,
1355 .maxComputeSharedMemorySize
= 32768,
1356 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1357 .maxComputeWorkGroupInvocations
= 1024,
1358 .maxComputeWorkGroupSize
= {
1363 .subPixelPrecisionBits
= 8,
1364 .subTexelPrecisionBits
= 8,
1365 .mipmapPrecisionBits
= 8,
1366 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1367 .maxDrawIndirectCount
= UINT32_MAX
,
1368 .maxSamplerLodBias
= 16,
1369 .maxSamplerAnisotropy
= 16,
1370 .maxViewports
= MAX_VIEWPORTS
,
1371 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1372 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1373 .viewportSubPixelBits
= 8,
1374 .minMemoryMapAlignment
= 4096, /* A page */
1375 .minTexelBufferOffsetAlignment
= 4,
1376 .minUniformBufferOffsetAlignment
= 4,
1377 .minStorageBufferOffsetAlignment
= 4,
1378 .minTexelOffset
= -32,
1379 .maxTexelOffset
= 31,
1380 .minTexelGatherOffset
= -32,
1381 .maxTexelGatherOffset
= 31,
1382 .minInterpolationOffset
= -2,
1383 .maxInterpolationOffset
= 2,
1384 .subPixelInterpolationOffsetBits
= 8,
1385 .maxFramebufferWidth
= (1 << 14),
1386 .maxFramebufferHeight
= (1 << 14),
1387 .maxFramebufferLayers
= (1 << 10),
1388 .framebufferColorSampleCounts
= sample_counts
,
1389 .framebufferDepthSampleCounts
= sample_counts
,
1390 .framebufferStencilSampleCounts
= sample_counts
,
1391 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1392 .maxColorAttachments
= MAX_RTS
,
1393 .sampledImageColorSampleCounts
= sample_counts
,
1394 .sampledImageIntegerSampleCounts
= sample_counts
,
1395 .sampledImageDepthSampleCounts
= sample_counts
,
1396 .sampledImageStencilSampleCounts
= sample_counts
,
1397 .storageImageSampleCounts
= pdevice
->rad_info
.chip_class
>= GFX8
? sample_counts
: VK_SAMPLE_COUNT_1_BIT
,
1398 .maxSampleMaskWords
= 1,
1399 .timestampComputeAndGraphics
= true,
1400 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1401 .maxClipDistances
= 8,
1402 .maxCullDistances
= 8,
1403 .maxCombinedClipAndCullDistances
= 8,
1404 .discreteQueuePriorities
= 2,
1405 .pointSizeRange
= { 0.0, 8192.0 },
1406 .lineWidthRange
= { 0.0, 7.9921875 },
1407 .pointSizeGranularity
= (1.0 / 8.0),
1408 .lineWidthGranularity
= (1.0 / 128.0),
1409 .strictLines
= false, /* FINISHME */
1410 .standardSampleLocations
= true,
1411 .optimalBufferCopyOffsetAlignment
= 128,
1412 .optimalBufferCopyRowPitchAlignment
= 128,
1413 .nonCoherentAtomSize
= 64,
1416 *pProperties
= (VkPhysicalDeviceProperties
) {
1417 .apiVersion
= radv_physical_device_api_version(pdevice
),
1418 .driverVersion
= vk_get_driver_version(),
1419 .vendorID
= ATI_VENDOR_ID
,
1420 .deviceID
= pdevice
->rad_info
.pci_id
,
1421 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1423 .sparseProperties
= {0},
1426 strcpy(pProperties
->deviceName
, pdevice
->name
);
1427 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1430 void radv_GetPhysicalDeviceProperties2(
1431 VkPhysicalDevice physicalDevice
,
1432 VkPhysicalDeviceProperties2
*pProperties
)
1434 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1435 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1437 vk_foreach_struct(ext
, pProperties
->pNext
) {
1438 switch (ext
->sType
) {
1439 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1440 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1441 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1442 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1445 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1446 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1447 memcpy(properties
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1448 memcpy(properties
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1449 properties
->deviceLUIDValid
= false;
1452 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1453 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1454 properties
->maxMultiviewViewCount
= MAX_VIEWS
;
1455 properties
->maxMultiviewInstanceIndex
= INT_MAX
;
1458 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1459 VkPhysicalDevicePointClippingProperties
*properties
=
1460 (VkPhysicalDevicePointClippingProperties
*)ext
;
1461 properties
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1464 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1465 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1466 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1467 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1470 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1471 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1472 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1473 properties
->minImportedHostPointerAlignment
= 4096;
1476 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1477 VkPhysicalDeviceSubgroupProperties
*properties
=
1478 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1479 properties
->subgroupSize
= RADV_SUBGROUP_SIZE
;
1480 properties
->supportedStages
= VK_SHADER_STAGE_ALL
;
1481 properties
->supportedOperations
=
1482 VK_SUBGROUP_FEATURE_BASIC_BIT
|
1483 VK_SUBGROUP_FEATURE_VOTE_BIT
|
1484 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1485 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1486 VK_SUBGROUP_FEATURE_CLUSTERED_BIT
|
1487 VK_SUBGROUP_FEATURE_QUAD_BIT
;
1488 if (pdevice
->rad_info
.chip_class
== GFX8
||
1489 pdevice
->rad_info
.chip_class
== GFX9
) {
1490 properties
->supportedOperations
|=
1491 VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1492 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1494 properties
->quadOperationsInAllStages
= true;
1497 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1498 VkPhysicalDeviceMaintenance3Properties
*properties
=
1499 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1500 properties
->maxPerSetDescriptors
= RADV_MAX_PER_SET_DESCRIPTORS
;
1501 properties
->maxMemoryAllocationSize
= RADV_MAX_MEMORY_ALLOCATION_SIZE
;
1504 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES
: {
1505 VkPhysicalDeviceSamplerFilterMinmaxProperties
*properties
=
1506 (VkPhysicalDeviceSamplerFilterMinmaxProperties
*)ext
;
1507 /* GFX6-8 only support single channel min/max filter. */
1508 properties
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1509 properties
->filterMinmaxSingleComponentFormats
= true;
1512 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1513 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1514 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1516 /* Shader engines. */
1517 properties
->shaderEngineCount
=
1518 pdevice
->rad_info
.max_se
;
1519 properties
->shaderArraysPerEngineCount
=
1520 pdevice
->rad_info
.max_sh_per_se
;
1521 properties
->computeUnitsPerShaderArray
=
1522 pdevice
->rad_info
.num_good_cu_per_sh
;
1523 properties
->simdPerComputeUnit
= 4;
1524 properties
->wavefrontsPerSimd
=
1525 pdevice
->rad_info
.family
== CHIP_TONGA
||
1526 pdevice
->rad_info
.family
== CHIP_ICELAND
||
1527 pdevice
->rad_info
.family
== CHIP_POLARIS10
||
1528 pdevice
->rad_info
.family
== CHIP_POLARIS11
||
1529 pdevice
->rad_info
.family
== CHIP_POLARIS12
||
1530 pdevice
->rad_info
.family
== CHIP_VEGAM
? 8 : 10;
1531 properties
->wavefrontSize
= 64;
1534 properties
->sgprsPerSimd
=
1535 pdevice
->rad_info
.num_physical_sgprs_per_simd
;
1536 properties
->minSgprAllocation
=
1537 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1538 properties
->maxSgprAllocation
=
1539 pdevice
->rad_info
.family
== CHIP_TONGA
||
1540 pdevice
->rad_info
.family
== CHIP_ICELAND
? 96 : 104;
1541 properties
->sgprAllocationGranularity
=
1542 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1545 properties
->vgprsPerSimd
= RADV_NUM_PHYSICAL_VGPRS
;
1546 properties
->minVgprAllocation
= 4;
1547 properties
->maxVgprAllocation
= 256;
1548 properties
->vgprAllocationGranularity
= 4;
1551 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD
: {
1552 VkPhysicalDeviceShaderCoreProperties2AMD
*properties
=
1553 (VkPhysicalDeviceShaderCoreProperties2AMD
*)ext
;
1555 properties
->shaderCoreFeatures
= 0;
1556 properties
->activeComputeUnitCount
=
1557 pdevice
->rad_info
.num_good_compute_units
;
1560 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1561 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1562 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1563 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1566 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES
: {
1567 VkPhysicalDeviceDescriptorIndexingProperties
*properties
=
1568 (VkPhysicalDeviceDescriptorIndexingProperties
*)ext
;
1569 properties
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1570 properties
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1571 properties
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1572 properties
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1573 properties
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1574 properties
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1575 properties
->robustBufferAccessUpdateAfterBind
= false;
1576 properties
->quadDivergentImplicitLod
= false;
1578 size_t max_descriptor_set_size
= radv_max_descriptor_set_size();
1579 properties
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1580 properties
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1581 properties
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1582 properties
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1583 properties
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1584 properties
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1585 properties
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1586 properties
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1587 properties
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1588 properties
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1589 properties
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1590 properties
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1591 properties
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1592 properties
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1593 properties
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1596 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1597 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1598 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1599 properties
->protectedNoFault
= false;
1602 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1603 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1604 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1605 properties
->primitiveOverestimationSize
= 0;
1606 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1607 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1608 properties
->primitiveUnderestimation
= false;
1609 properties
->conservativePointAndLineRasterization
= false;
1610 properties
->degenerateTrianglesRasterized
= false;
1611 properties
->degenerateLinesRasterized
= false;
1612 properties
->fullyCoveredFragmentShaderInputVariable
= false;
1613 properties
->conservativeRasterizationPostDepthCoverage
= false;
1616 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1617 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1618 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1619 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1620 properties
->pciBus
= pdevice
->bus_info
.bus
;
1621 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1622 properties
->pciFunction
= pdevice
->bus_info
.func
;
1625 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES
: {
1626 VkPhysicalDeviceDriverProperties
*driver_props
=
1627 (VkPhysicalDeviceDriverProperties
*) ext
;
1629 driver_props
->driverID
= VK_DRIVER_ID_MESA_RADV
;
1630 snprintf(driver_props
->driverName
, VK_MAX_DRIVER_NAME_SIZE
, "radv");
1631 snprintf(driver_props
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE
,
1632 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1633 " (LLVM " MESA_LLVM_VERSION_STRING
")");
1635 driver_props
->conformanceVersion
= (VkConformanceVersion
) {
1643 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1644 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1645 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1646 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1647 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1648 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1649 properties
->maxTransformFeedbackStreamDataSize
= 512;
1650 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1651 properties
->maxTransformFeedbackBufferDataStride
= 512;
1652 properties
->transformFeedbackQueries
= !pdevice
->use_ngg_streamout
;
1653 properties
->transformFeedbackStreamsLinesTriangles
= !pdevice
->use_ngg_streamout
;
1654 properties
->transformFeedbackRasterizationStreamSelect
= false;
1655 properties
->transformFeedbackDraw
= true;
1658 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1659 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1660 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1662 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1663 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1664 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1665 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1666 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1669 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT
: {
1670 VkPhysicalDeviceSampleLocationsPropertiesEXT
*properties
=
1671 (VkPhysicalDeviceSampleLocationsPropertiesEXT
*)ext
;
1672 properties
->sampleLocationSampleCounts
= VK_SAMPLE_COUNT_2_BIT
|
1673 VK_SAMPLE_COUNT_4_BIT
|
1674 VK_SAMPLE_COUNT_8_BIT
;
1675 properties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2 , 2 };
1676 properties
->sampleLocationCoordinateRange
[0] = 0.0f
;
1677 properties
->sampleLocationCoordinateRange
[1] = 0.9375f
;
1678 properties
->sampleLocationSubPixelBits
= 4;
1679 properties
->variableSampleLocations
= false;
1682 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES
: {
1683 VkPhysicalDeviceDepthStencilResolveProperties
*properties
=
1684 (VkPhysicalDeviceDepthStencilResolveProperties
*)ext
;
1686 /* We support all of the depth resolve modes */
1687 properties
->supportedDepthResolveModes
=
1688 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1689 VK_RESOLVE_MODE_AVERAGE_BIT_KHR
|
1690 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1691 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1693 /* Average doesn't make sense for stencil so we don't support that */
1694 properties
->supportedStencilResolveModes
=
1695 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1696 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1697 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1699 properties
->independentResolveNone
= true;
1700 properties
->independentResolve
= true;
1703 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT
: {
1704 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*properties
=
1705 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*)ext
;
1706 properties
->storageTexelBufferOffsetAlignmentBytes
= 4;
1707 properties
->storageTexelBufferOffsetSingleTexelAlignment
= true;
1708 properties
->uniformTexelBufferOffsetAlignmentBytes
= 4;
1709 properties
->uniformTexelBufferOffsetSingleTexelAlignment
= true;
1712 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES
: {
1713 VkPhysicalDeviceFloatControlsProperties
*properties
=
1714 (VkPhysicalDeviceFloatControlsProperties
*)ext
;
1716 /* On AMD hardware, denormals and rounding modes for
1717 * fp16/fp64 are controlled by the same config
1720 properties
->denormBehaviorIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY
;
1721 properties
->roundingModeIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY
;
1723 /* Do not allow both preserving and flushing denorms
1724 * because different shaders in the same pipeline can
1725 * have different settings and this won't work for
1726 * merged shaders. To make it work, this requires LLVM
1727 * support for changing the register. The same logic
1728 * applies for the rounding modes because they are
1729 * configured with the same config register.
1730 * TODO: we can enable a lot of these for ACO when it
1731 * supports all stages
1733 properties
->shaderDenormFlushToZeroFloat32
= true;
1734 properties
->shaderDenormPreserveFloat32
= false;
1735 properties
->shaderRoundingModeRTEFloat32
= true;
1736 properties
->shaderRoundingModeRTZFloat32
= false;
1737 properties
->shaderSignedZeroInfNanPreserveFloat32
= true;
1739 properties
->shaderDenormFlushToZeroFloat16
= false;
1740 properties
->shaderDenormPreserveFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1741 properties
->shaderRoundingModeRTEFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1742 properties
->shaderRoundingModeRTZFloat16
= false;
1743 properties
->shaderSignedZeroInfNanPreserveFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1745 properties
->shaderDenormFlushToZeroFloat64
= false;
1746 properties
->shaderDenormPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1747 properties
->shaderRoundingModeRTEFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1748 properties
->shaderRoundingModeRTZFloat64
= false;
1749 properties
->shaderSignedZeroInfNanPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1752 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES
: {
1753 VkPhysicalDeviceTimelineSemaphoreProperties
*props
=
1754 (VkPhysicalDeviceTimelineSemaphoreProperties
*) ext
;
1755 props
->maxTimelineSemaphoreValueDifference
= UINT64_MAX
;
1758 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT
: {
1759 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*props
=
1760 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*)ext
;
1761 props
->minSubgroupSize
= 64;
1762 props
->maxSubgroupSize
= 64;
1763 props
->maxComputeWorkgroupSubgroups
= UINT32_MAX
;
1764 props
->requiredSubgroupSizeStages
= 0;
1766 if (pdevice
->rad_info
.chip_class
>= GFX10
) {
1767 /* Only GFX10+ supports wave32. */
1768 props
->minSubgroupSize
= 32;
1769 props
->requiredSubgroupSizeStages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1773 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
: {
1774 VkPhysicalDeviceVulkan11Properties
*props
=
1775 (VkPhysicalDeviceVulkan11Properties
*)ext
;
1777 memcpy(props
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1778 memcpy(props
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1779 memset(props
->deviceLUID
, 0, VK_LUID_SIZE
);
1780 /* The LUID is for Windows. */
1781 props
->deviceLUIDValid
= false;
1782 props
->deviceNodeMask
= 0;
1784 props
->subgroupSize
= RADV_SUBGROUP_SIZE
;
1785 props
->subgroupSupportedStages
= VK_SHADER_STAGE_ALL
;
1786 props
->subgroupSupportedOperations
=
1787 VK_SUBGROUP_FEATURE_BASIC_BIT
|
1788 VK_SUBGROUP_FEATURE_VOTE_BIT
|
1789 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1790 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1791 VK_SUBGROUP_FEATURE_CLUSTERED_BIT
|
1792 VK_SUBGROUP_FEATURE_QUAD_BIT
;
1793 if (pdevice
->rad_info
.chip_class
== GFX8
||
1794 pdevice
->rad_info
.chip_class
== GFX9
) {
1795 props
->subgroupSupportedOperations
|=
1796 VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1797 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1799 props
->subgroupQuadOperationsInAllStages
= true;
1801 props
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1802 props
->maxMultiviewViewCount
= MAX_VIEWS
;
1803 props
->maxMultiviewInstanceIndex
= INT_MAX
;
1804 props
->protectedNoFault
= false;
1805 props
->maxPerSetDescriptors
= RADV_MAX_PER_SET_DESCRIPTORS
;
1806 props
->maxMemoryAllocationSize
= RADV_MAX_MEMORY_ALLOCATION_SIZE
;
1809 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
: {
1810 VkPhysicalDeviceVulkan12Properties
*props
=
1811 (VkPhysicalDeviceVulkan12Properties
*)ext
;
1814 props
->driverID
= VK_DRIVER_ID_MESA_RADV
;
1815 snprintf(props
->driverName
, VK_MAX_DRIVER_NAME_SIZE
, "radv");
1816 snprintf(props
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE
,
1817 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1818 " (LLVM " MESA_LLVM_VERSION_STRING
")");
1820 props
->conformanceVersion
= (VkConformanceVersion
) {
1828 props
->denormBehaviorIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1829 props
->roundingModeIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1831 props
->shaderDenormFlushToZeroFloat32
= true;
1832 props
->shaderDenormPreserveFloat32
= false;
1833 props
->shaderRoundingModeRTEFloat32
= true;
1834 props
->shaderRoundingModeRTZFloat32
= false;
1835 props
->shaderSignedZeroInfNanPreserveFloat32
= true;
1837 props
->shaderDenormFlushToZeroFloat16
= false;
1838 props
->shaderDenormPreserveFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1839 props
->shaderRoundingModeRTEFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1840 props
->shaderRoundingModeRTZFloat16
= false;
1841 props
->shaderSignedZeroInfNanPreserveFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1843 props
->shaderDenormFlushToZeroFloat64
= false;
1844 props
->shaderDenormPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1845 props
->shaderRoundingModeRTEFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1846 props
->shaderRoundingModeRTZFloat64
= false;
1847 props
->shaderSignedZeroInfNanPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1849 props
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1850 props
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1851 props
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1852 props
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1853 props
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1854 props
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1855 props
->robustBufferAccessUpdateAfterBind
= false;
1856 props
->quadDivergentImplicitLod
= false;
1858 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1859 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1860 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1861 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1862 32 /* sampler, largest when combined with image */ +
1863 64 /* sampled image */ +
1864 64 /* storage image */);
1865 props
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1866 props
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1867 props
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1868 props
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1869 props
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1870 props
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1871 props
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1872 props
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1873 props
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1874 props
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1875 props
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1876 props
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1877 props
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1878 props
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1879 props
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1881 /* We support all of the depth resolve modes */
1882 props
->supportedDepthResolveModes
=
1883 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1884 VK_RESOLVE_MODE_AVERAGE_BIT_KHR
|
1885 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1886 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1888 /* Average doesn't make sense for stencil so we don't support that */
1889 props
->supportedStencilResolveModes
=
1890 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1891 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1892 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1894 props
->independentResolveNone
= true;
1895 props
->independentResolve
= true;
1897 props
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1898 props
->filterMinmaxSingleComponentFormats
= true;
1900 props
->maxTimelineSemaphoreValueDifference
= UINT64_MAX
;
1902 props
->framebufferIntegerColorSampleCounts
= VK_SAMPLE_COUNT_1_BIT
;
1911 static void radv_get_physical_device_queue_family_properties(
1912 struct radv_physical_device
* pdevice
,
1914 VkQueueFamilyProperties
** pQueueFamilyProperties
)
1916 int num_queue_families
= 1;
1918 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
1919 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
1920 num_queue_families
++;
1922 if (pQueueFamilyProperties
== NULL
) {
1923 *pCount
= num_queue_families
;
1932 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1933 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
1934 VK_QUEUE_COMPUTE_BIT
|
1935 VK_QUEUE_TRANSFER_BIT
|
1936 VK_QUEUE_SPARSE_BINDING_BIT
,
1938 .timestampValidBits
= 64,
1939 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1944 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
1945 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
1946 if (*pCount
> idx
) {
1947 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1948 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
1949 VK_QUEUE_TRANSFER_BIT
|
1950 VK_QUEUE_SPARSE_BINDING_BIT
,
1951 .queueCount
= pdevice
->rad_info
.num_rings
[RING_COMPUTE
],
1952 .timestampValidBits
= 64,
1953 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1961 void radv_GetPhysicalDeviceQueueFamilyProperties(
1962 VkPhysicalDevice physicalDevice
,
1964 VkQueueFamilyProperties
* pQueueFamilyProperties
)
1966 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1967 if (!pQueueFamilyProperties
) {
1968 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1971 VkQueueFamilyProperties
*properties
[] = {
1972 pQueueFamilyProperties
+ 0,
1973 pQueueFamilyProperties
+ 1,
1974 pQueueFamilyProperties
+ 2,
1976 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1977 assert(*pCount
<= 3);
1980 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1981 VkPhysicalDevice physicalDevice
,
1983 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
1985 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1986 if (!pQueueFamilyProperties
) {
1987 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1990 VkQueueFamilyProperties
*properties
[] = {
1991 &pQueueFamilyProperties
[0].queueFamilyProperties
,
1992 &pQueueFamilyProperties
[1].queueFamilyProperties
,
1993 &pQueueFamilyProperties
[2].queueFamilyProperties
,
1995 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1996 assert(*pCount
<= 3);
1999 void radv_GetPhysicalDeviceMemoryProperties(
2000 VkPhysicalDevice physicalDevice
,
2001 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
2003 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2005 *pMemoryProperties
= physical_device
->memory_properties
;
2009 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
2010 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
2012 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
2013 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
2014 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
2015 uint64_t vram_size
= radv_get_vram_size(device
);
2016 uint64_t gtt_size
= device
->rad_info
.gart_size
;
2017 uint64_t heap_budget
, heap_usage
;
2019 /* For all memory heaps, the computation of budget is as follow:
2020 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2022 * The Vulkan spec 1.1.97 says that the budget should include any
2023 * currently allocated device memory.
2025 * Note that the application heap usages are not really accurate (eg.
2026 * in presence of shared buffers).
2028 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
2029 uint32_t heap_index
= device
->memory_properties
.memoryTypes
[i
].heapIndex
;
2031 if (radv_is_mem_type_vram(device
->mem_type_indices
[i
])) {
2032 heap_usage
= device
->ws
->query_value(device
->ws
,
2033 RADEON_ALLOCATED_VRAM
);
2035 heap_budget
= vram_size
-
2036 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
2039 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2040 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2041 } else if (radv_is_mem_type_vram_visible(device
->mem_type_indices
[i
])) {
2042 heap_usage
= device
->ws
->query_value(device
->ws
,
2043 RADEON_ALLOCATED_VRAM_VIS
);
2045 heap_budget
= visible_vram_size
-
2046 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
2049 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2050 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2051 } else if (radv_is_mem_type_gtt_wc(device
->mem_type_indices
[i
])) {
2052 heap_usage
= device
->ws
->query_value(device
->ws
,
2053 RADEON_ALLOCATED_GTT
);
2055 heap_budget
= gtt_size
-
2056 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
2059 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2060 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2064 /* The heapBudget and heapUsage values must be zero for array elements
2065 * greater than or equal to
2066 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2068 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
2069 memoryBudget
->heapBudget
[i
] = 0;
2070 memoryBudget
->heapUsage
[i
] = 0;
2074 void radv_GetPhysicalDeviceMemoryProperties2(
2075 VkPhysicalDevice physicalDevice
,
2076 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
2078 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
2079 &pMemoryProperties
->memoryProperties
);
2081 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
2082 vk_find_struct(pMemoryProperties
->pNext
,
2083 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
2085 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
2088 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
2090 VkExternalMemoryHandleTypeFlagBits handleType
,
2091 const void *pHostPointer
,
2092 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
2094 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2098 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
2099 const struct radv_physical_device
*physical_device
= device
->physical_device
;
2100 uint32_t memoryTypeBits
= 0;
2101 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
2102 if (radv_is_mem_type_gtt_cached(physical_device
->mem_type_indices
[i
])) {
2103 memoryTypeBits
= (1 << i
);
2107 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
2111 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
2115 static enum radeon_ctx_priority
2116 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
2118 /* Default to MEDIUM when a specific global priority isn't requested */
2120 return RADEON_CTX_PRIORITY_MEDIUM
;
2122 switch(pObj
->globalPriority
) {
2123 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
2124 return RADEON_CTX_PRIORITY_REALTIME
;
2125 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
2126 return RADEON_CTX_PRIORITY_HIGH
;
2127 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
2128 return RADEON_CTX_PRIORITY_MEDIUM
;
2129 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
2130 return RADEON_CTX_PRIORITY_LOW
;
2132 unreachable("Illegal global priority value");
2133 return RADEON_CTX_PRIORITY_INVALID
;
2138 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
2139 uint32_t queue_family_index
, int idx
,
2140 VkDeviceQueueCreateFlags flags
,
2141 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
2143 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2144 queue
->device
= device
;
2145 queue
->queue_family_index
= queue_family_index
;
2146 queue
->queue_idx
= idx
;
2147 queue
->priority
= radv_get_queue_global_priority(global_priority
);
2148 queue
->flags
= flags
;
2150 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
2152 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2154 list_inithead(&queue
->pending_submissions
);
2155 pthread_mutex_init(&queue
->pending_mutex
, NULL
);
2161 radv_queue_finish(struct radv_queue
*queue
)
2163 pthread_mutex_destroy(&queue
->pending_mutex
);
2166 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
2168 if (queue
->initial_full_flush_preamble_cs
)
2169 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2170 if (queue
->initial_preamble_cs
)
2171 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2172 if (queue
->continue_preamble_cs
)
2173 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2174 if (queue
->descriptor_bo
)
2175 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2176 if (queue
->scratch_bo
)
2177 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2178 if (queue
->esgs_ring_bo
)
2179 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2180 if (queue
->gsvs_ring_bo
)
2181 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2182 if (queue
->tess_rings_bo
)
2183 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
2185 queue
->device
->ws
->buffer_destroy(queue
->gds_bo
);
2186 if (queue
->gds_oa_bo
)
2187 queue
->device
->ws
->buffer_destroy(queue
->gds_oa_bo
);
2188 if (queue
->compute_scratch_bo
)
2189 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2193 radv_bo_list_init(struct radv_bo_list
*bo_list
)
2195 pthread_mutex_init(&bo_list
->mutex
, NULL
);
2196 bo_list
->list
.count
= bo_list
->capacity
= 0;
2197 bo_list
->list
.bos
= NULL
;
2201 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
2203 free(bo_list
->list
.bos
);
2204 pthread_mutex_destroy(&bo_list
->mutex
);
2207 static VkResult
radv_bo_list_add(struct radv_device
*device
,
2208 struct radeon_winsys_bo
*bo
)
2210 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2215 if (unlikely(!device
->use_global_bo_list
))
2218 pthread_mutex_lock(&bo_list
->mutex
);
2219 if (bo_list
->list
.count
== bo_list
->capacity
) {
2220 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
2221 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
2224 pthread_mutex_unlock(&bo_list
->mutex
);
2225 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2228 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
2229 bo_list
->capacity
= capacity
;
2232 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
2233 pthread_mutex_unlock(&bo_list
->mutex
);
2237 static void radv_bo_list_remove(struct radv_device
*device
,
2238 struct radeon_winsys_bo
*bo
)
2240 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2245 if (unlikely(!device
->use_global_bo_list
))
2248 pthread_mutex_lock(&bo_list
->mutex
);
2249 for(unsigned i
= 0; i
< bo_list
->list
.count
; ++i
) {
2250 if (bo_list
->list
.bos
[i
] == bo
) {
2251 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
2252 --bo_list
->list
.count
;
2256 pthread_mutex_unlock(&bo_list
->mutex
);
2260 radv_device_init_gs_info(struct radv_device
*device
)
2262 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
2263 device
->physical_device
->rad_info
.family
);
2266 static int radv_get_device_extension_index(const char *name
)
2268 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
2269 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
2276 radv_get_int_debug_option(const char *name
, int default_value
)
2283 result
= default_value
;
2287 result
= strtol(str
, &endptr
, 0);
2288 if (str
== endptr
) {
2289 /* No digits founs. */
2290 result
= default_value
;
2297 static int install_seccomp_filter() {
2299 struct sock_filter filter
[] = {
2300 /* Check arch is 64bit x86 */
2301 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, arch
))),
2302 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, AUDIT_ARCH_X86_64
, 0, 12),
2304 /* Futex is required for mutex locks */
2305 #if defined __NR__newselect
2306 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2307 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR__newselect
, 11, 0),
2308 #elif defined __NR_select
2309 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2310 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_select
, 11, 0),
2312 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2313 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_pselect6
, 11, 0),
2316 /* Allow system exit calls for the forked process */
2317 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2318 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_exit_group
, 9, 0),
2320 /* Allow system read calls */
2321 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2322 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_read
, 7, 0),
2324 /* Allow system write calls */
2325 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2326 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_write
, 5, 0),
2328 /* Allow system brk calls (we need this for malloc) */
2329 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2330 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_brk
, 3, 0),
2332 /* Futex is required for mutex locks */
2333 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
2334 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_futex
, 1, 0),
2336 /* Return error if we hit a system call not on the whitelist */
2337 BPF_STMT(BPF_RET
+ BPF_K
, SECCOMP_RET_ERRNO
| (EPERM
& SECCOMP_RET_DATA
)),
2339 /* Allow whitelisted system calls */
2340 BPF_STMT(BPF_RET
+ BPF_K
, SECCOMP_RET_ALLOW
),
2343 struct sock_fprog prog
= {
2344 .len
= (unsigned short)(sizeof(filter
) / sizeof(filter
[0])),
2348 if (prctl(PR_SET_NO_NEW_PRIVS
, 1, 0, 0, 0))
2351 if (prctl(PR_SET_SECCOMP
, SECCOMP_MODE_FILTER
, &prog
))
2357 /* Helper function with timeout support for reading from the pipe between
2358 * processes used for secure compile.
2360 bool radv_sc_read(int fd
, void *buf
, size_t size
, bool timeout
)
2369 /* We can't rely on the value of tv after calling select() so
2370 * we must reset it on each iteration of the loop.
2375 int rval
= select(fd
+ 1, &fds
, NULL
, NULL
, timeout
? &tv
: NULL
);
2381 ssize_t bytes_read
= read(fd
, buf
, size
);
2390 /* select timeout */
2396 static bool radv_close_all_fds(const int *keep_fds
, int keep_fd_count
)
2400 d
= opendir("/proc/self/fd");
2403 int dir_fd
= dirfd(d
);
2405 while ((dir
= readdir(d
)) != NULL
) {
2406 if (dir
->d_name
[0] == '.')
2409 int fd
= atoi(dir
->d_name
);
2414 for (int i
= 0; !keep
&& i
< keep_fd_count
; ++i
)
2415 if (keep_fds
[i
] == fd
)
2427 static bool secure_compile_open_fifo_fds(struct radv_secure_compile_state
*sc
,
2428 int *fd_server
, int *fd_client
,
2429 unsigned process
, bool make_fifo
)
2431 bool result
= false;
2432 char *fifo_server_path
= NULL
;
2433 char *fifo_client_path
= NULL
;
2435 if (asprintf(&fifo_server_path
, "/tmp/radv_server_%s_%u", sc
->uid
, process
) == -1)
2436 goto open_fifo_exit
;
2438 if (asprintf(&fifo_client_path
, "/tmp/radv_client_%s_%u", sc
->uid
, process
) == -1)
2439 goto open_fifo_exit
;
2442 int file1
= mkfifo(fifo_server_path
, 0666);
2444 goto open_fifo_exit
;
2446 int file2
= mkfifo(fifo_client_path
, 0666);
2448 goto open_fifo_exit
;
2451 *fd_server
= open(fifo_server_path
, O_RDWR
);
2453 goto open_fifo_exit
;
2455 *fd_client
= open(fifo_client_path
, O_RDWR
);
2456 if(*fd_client
< 1) {
2458 goto open_fifo_exit
;
2464 free(fifo_server_path
);
2465 free(fifo_client_path
);
2470 static void run_secure_compile_device(struct radv_device
*device
, unsigned process
,
2471 int fd_idle_device_output
)
2473 int fd_secure_input
;
2474 int fd_secure_output
;
2475 bool fifo_result
= secure_compile_open_fifo_fds(device
->sc_state
,
2480 enum radv_secure_compile_type sc_type
;
2482 const int needed_fds
[] = {
2485 fd_idle_device_output
,
2488 if (!fifo_result
|| !radv_close_all_fds(needed_fds
, ARRAY_SIZE(needed_fds
)) ||
2489 install_seccomp_filter() == -1) {
2490 sc_type
= RADV_SC_TYPE_INIT_FAILURE
;
2492 sc_type
= RADV_SC_TYPE_INIT_SUCCESS
;
2493 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
;
2494 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
;
2497 write(fd_idle_device_output
, &sc_type
, sizeof(sc_type
));
2499 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
)
2500 goto secure_compile_exit
;
2503 radv_sc_read(fd_secure_input
, &sc_type
, sizeof(sc_type
), false);
2505 if (sc_type
== RADV_SC_TYPE_COMPILE_PIPELINE
) {
2506 struct radv_pipeline
*pipeline
;
2507 bool sc_read
= true;
2509 pipeline
= vk_zalloc2(&device
->alloc
, NULL
, sizeof(*pipeline
), 8,
2510 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2512 pipeline
->device
= device
;
2514 /* Read pipeline layout */
2515 struct radv_pipeline_layout layout
;
2516 sc_read
= radv_sc_read(fd_secure_input
, &layout
, sizeof(struct radv_pipeline_layout
), true);
2517 sc_read
&= radv_sc_read(fd_secure_input
, &layout
.num_sets
, sizeof(uint32_t), true);
2519 goto secure_compile_exit
;
2521 for (uint32_t set
= 0; set
< layout
.num_sets
; set
++) {
2522 uint32_t layout_size
;
2523 sc_read
&= radv_sc_read(fd_secure_input
, &layout_size
, sizeof(uint32_t), true);
2525 goto secure_compile_exit
;
2527 layout
.set
[set
].layout
= malloc(layout_size
);
2528 layout
.set
[set
].layout
->layout_size
= layout_size
;
2529 sc_read
&= radv_sc_read(fd_secure_input
, layout
.set
[set
].layout
,
2530 layout
.set
[set
].layout
->layout_size
, true);
2533 pipeline
->layout
= &layout
;
2535 /* Read pipeline key */
2536 struct radv_pipeline_key key
;
2537 sc_read
&= radv_sc_read(fd_secure_input
, &key
, sizeof(struct radv_pipeline_key
), true);
2539 /* Read pipeline create flags */
2540 VkPipelineCreateFlags flags
;
2541 sc_read
&= radv_sc_read(fd_secure_input
, &flags
, sizeof(VkPipelineCreateFlags
), true);
2543 /* Read stage and shader information */
2544 uint32_t num_stages
;
2545 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
2546 sc_read
&= radv_sc_read(fd_secure_input
, &num_stages
, sizeof(uint32_t), true);
2548 goto secure_compile_exit
;
2550 for (uint32_t i
= 0; i
< num_stages
; i
++) {
2553 gl_shader_stage stage
;
2554 sc_read
&= radv_sc_read(fd_secure_input
, &stage
, sizeof(gl_shader_stage
), true);
2556 VkPipelineShaderStageCreateInfo
*pStage
= calloc(1, sizeof(VkPipelineShaderStageCreateInfo
));
2558 /* Read entry point name */
2560 sc_read
&= radv_sc_read(fd_secure_input
, &name_size
, sizeof(size_t), true);
2562 goto secure_compile_exit
;
2564 char *ep_name
= malloc(name_size
);
2565 sc_read
&= radv_sc_read(fd_secure_input
, ep_name
, name_size
, true);
2566 pStage
->pName
= ep_name
;
2568 /* Read shader module */
2570 sc_read
&= radv_sc_read(fd_secure_input
, &module_size
, sizeof(size_t), true);
2572 goto secure_compile_exit
;
2574 struct radv_shader_module
*module
= malloc(module_size
);
2575 sc_read
&= radv_sc_read(fd_secure_input
, module
, module_size
, true);
2576 pStage
->module
= radv_shader_module_to_handle(module
);
2578 /* Read specialization info */
2580 sc_read
&= radv_sc_read(fd_secure_input
, &has_spec_info
, sizeof(bool), true);
2582 goto secure_compile_exit
;
2584 if (has_spec_info
) {
2585 VkSpecializationInfo
*specInfo
= malloc(sizeof(VkSpecializationInfo
));
2586 pStage
->pSpecializationInfo
= specInfo
;
2588 sc_read
&= radv_sc_read(fd_secure_input
, &specInfo
->dataSize
, sizeof(size_t), true);
2590 goto secure_compile_exit
;
2592 void *si_data
= malloc(specInfo
->dataSize
);
2593 sc_read
&= radv_sc_read(fd_secure_input
, si_data
, specInfo
->dataSize
, true);
2594 specInfo
->pData
= si_data
;
2596 sc_read
&= radv_sc_read(fd_secure_input
, &specInfo
->mapEntryCount
, sizeof(uint32_t), true);
2598 goto secure_compile_exit
;
2600 VkSpecializationMapEntry
*mapEntries
= malloc(sizeof(VkSpecializationMapEntry
) * specInfo
->mapEntryCount
);
2601 for (uint32_t j
= 0; j
< specInfo
->mapEntryCount
; j
++) {
2602 sc_read
&= radv_sc_read(fd_secure_input
, &mapEntries
[j
], sizeof(VkSpecializationMapEntry
), true);
2604 goto secure_compile_exit
;
2607 specInfo
->pMapEntries
= mapEntries
;
2610 pStages
[stage
] = pStage
;
2613 /* Compile the shaders */
2614 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
2615 radv_create_shaders(pipeline
, device
, NULL
, &key
, pStages
, flags
, NULL
, stage_feedbacks
);
2617 /* free memory allocated above */
2618 for (uint32_t set
= 0; set
< layout
.num_sets
; set
++)
2619 free(layout
.set
[set
].layout
);
2621 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2625 free((void *) pStages
[i
]->pName
);
2626 free(radv_shader_module_from_handle(pStages
[i
]->module
));
2627 if (pStages
[i
]->pSpecializationInfo
) {
2628 free((void *) pStages
[i
]->pSpecializationInfo
->pData
);
2629 free((void *) pStages
[i
]->pSpecializationInfo
->pMapEntries
);
2630 free((void *) pStages
[i
]->pSpecializationInfo
);
2632 free((void *) pStages
[i
]);
2635 vk_free(&device
->alloc
, pipeline
);
2637 sc_type
= RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
;
2638 write(fd_secure_output
, &sc_type
, sizeof(sc_type
));
2640 } else if (sc_type
== RADV_SC_TYPE_DESTROY_DEVICE
) {
2641 goto secure_compile_exit
;
2645 secure_compile_exit
:
2646 close(fd_secure_input
);
2647 close(fd_secure_output
);
2648 close(fd_idle_device_output
);
2652 static enum radv_secure_compile_type
fork_secure_compile_device(struct radv_device
*device
, unsigned process
)
2654 int fd_secure_input
[2];
2655 int fd_secure_output
[2];
2657 /* create pipe descriptors (used to communicate between processes) */
2658 if (pipe(fd_secure_input
) == -1 || pipe(fd_secure_output
) == -1)
2659 return RADV_SC_TYPE_INIT_FAILURE
;
2663 if ((sc_pid
= fork()) == 0) {
2664 device
->sc_state
->secure_compile_thread_counter
= process
;
2665 run_secure_compile_device(device
, process
, fd_secure_output
[1]);
2668 return RADV_SC_TYPE_INIT_FAILURE
;
2670 /* Read the init result returned from the secure process */
2671 enum radv_secure_compile_type sc_type
;
2672 bool sc_read
= radv_sc_read(fd_secure_output
[0], &sc_type
, sizeof(sc_type
), true);
2674 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
|| !sc_read
) {
2675 close(fd_secure_input
[0]);
2676 close(fd_secure_input
[1]);
2677 close(fd_secure_output
[1]);
2678 close(fd_secure_output
[0]);
2680 waitpid(sc_pid
, &status
, 0);
2682 return RADV_SC_TYPE_INIT_FAILURE
;
2684 assert(sc_type
== RADV_SC_TYPE_INIT_SUCCESS
);
2685 write(device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
, &sc_type
, sizeof(sc_type
));
2687 close(fd_secure_input
[0]);
2688 close(fd_secure_input
[1]);
2689 close(fd_secure_output
[1]);
2690 close(fd_secure_output
[0]);
2693 waitpid(sc_pid
, &status
, 0);
2697 return RADV_SC_TYPE_INIT_SUCCESS
;
2700 /* Run a bare bones fork of a device that was forked right after its creation.
2701 * This device will have low overhead when it is forked again before each
2702 * pipeline compilation. This device sits idle and its only job is to fork
2705 static void run_secure_compile_idle_device(struct radv_device
*device
, unsigned process
,
2706 int fd_secure_input
, int fd_secure_output
)
2708 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_INIT_SUCCESS
;
2709 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
;
2710 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
;
2712 write(fd_secure_output
, &sc_type
, sizeof(sc_type
));
2715 radv_sc_read(fd_secure_input
, &sc_type
, sizeof(sc_type
), false);
2717 if (sc_type
== RADV_SC_TYPE_FORK_DEVICE
) {
2718 sc_type
= fork_secure_compile_device(device
, process
);
2720 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
)
2721 goto secure_compile_exit
;
2723 } else if (sc_type
== RADV_SC_TYPE_DESTROY_DEVICE
) {
2724 goto secure_compile_exit
;
2728 secure_compile_exit
:
2729 close(fd_secure_input
);
2730 close(fd_secure_output
);
2734 static void destroy_secure_compile_device(struct radv_device
*device
, unsigned process
)
2736 int fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
;
2738 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_DESTROY_DEVICE
;
2739 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
2741 close(device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
);
2742 close(device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
);
2745 waitpid(device
->sc_state
->secure_compile_processes
[process
].sc_pid
, &status
, 0);
2748 static VkResult
fork_secure_compile_idle_device(struct radv_device
*device
)
2750 device
->sc_state
= vk_zalloc(&device
->alloc
,
2751 sizeof(struct radv_secure_compile_state
),
2752 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2754 mtx_init(&device
->sc_state
->secure_compile_mutex
, mtx_plain
);
2756 pid_t upid
= getpid();
2757 time_t seconds
= time(NULL
);
2760 if (asprintf(&uid
, "%ld_%ld", (long) upid
, (long) seconds
) == -1)
2761 return VK_ERROR_INITIALIZATION_FAILED
;
2763 device
->sc_state
->uid
= uid
;
2765 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
2766 int fd_secure_input
[MAX_SC_PROCS
][2];
2767 int fd_secure_output
[MAX_SC_PROCS
][2];
2769 /* create pipe descriptors (used to communicate between processes) */
2770 for (unsigned i
= 0; i
< sc_threads
; i
++) {
2771 if (pipe(fd_secure_input
[i
]) == -1 ||
2772 pipe(fd_secure_output
[i
]) == -1) {
2773 return VK_ERROR_INITIALIZATION_FAILED
;
2777 device
->sc_state
->secure_compile_processes
= vk_zalloc(&device
->alloc
,
2778 sizeof(struct radv_secure_compile_process
) * sc_threads
, 8,
2779 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2781 for (unsigned process
= 0; process
< sc_threads
; process
++) {
2782 if ((device
->sc_state
->secure_compile_processes
[process
].sc_pid
= fork()) == 0) {
2783 device
->sc_state
->secure_compile_thread_counter
= process
;
2784 run_secure_compile_idle_device(device
, process
, fd_secure_input
[process
][0], fd_secure_output
[process
][1]);
2786 if (device
->sc_state
->secure_compile_processes
[process
].sc_pid
== -1)
2787 return VK_ERROR_INITIALIZATION_FAILED
;
2789 /* Read the init result returned from the secure process */
2790 enum radv_secure_compile_type sc_type
;
2791 bool sc_read
= radv_sc_read(fd_secure_output
[process
][0], &sc_type
, sizeof(sc_type
), true);
2794 if (sc_read
&& sc_type
== RADV_SC_TYPE_INIT_SUCCESS
) {
2795 fifo_result
= secure_compile_open_fifo_fds(device
->sc_state
,
2796 &device
->sc_state
->secure_compile_processes
[process
].fd_server
,
2797 &device
->sc_state
->secure_compile_processes
[process
].fd_client
,
2800 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
[process
][1];
2801 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
[process
][0];
2804 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
|| !sc_read
|| !fifo_result
) {
2805 close(fd_secure_input
[process
][0]);
2806 close(fd_secure_input
[process
][1]);
2807 close(fd_secure_output
[process
][1]);
2808 close(fd_secure_output
[process
][0]);
2810 waitpid(device
->sc_state
->secure_compile_processes
[process
].sc_pid
, &status
, 0);
2812 /* Destroy any forks that were created sucessfully */
2813 for (unsigned i
= 0; i
< process
; i
++) {
2814 destroy_secure_compile_device(device
, i
);
2817 return VK_ERROR_INITIALIZATION_FAILED
;
2825 radv_create_pthread_cond(pthread_cond_t
*cond
)
2827 pthread_condattr_t condattr
;
2828 if (pthread_condattr_init(&condattr
)) {
2829 return VK_ERROR_INITIALIZATION_FAILED
;
2832 if (pthread_condattr_setclock(&condattr
, CLOCK_MONOTONIC
)) {
2833 pthread_condattr_destroy(&condattr
);
2834 return VK_ERROR_INITIALIZATION_FAILED
;
2836 if (pthread_cond_init(cond
, &condattr
)) {
2837 pthread_condattr_destroy(&condattr
);
2838 return VK_ERROR_INITIALIZATION_FAILED
;
2840 pthread_condattr_destroy(&condattr
);
2844 VkResult
radv_CreateDevice(
2845 VkPhysicalDevice physicalDevice
,
2846 const VkDeviceCreateInfo
* pCreateInfo
,
2847 const VkAllocationCallbacks
* pAllocator
,
2850 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2852 struct radv_device
*device
;
2854 bool keep_shader_info
= false;
2856 /* Check enabled features */
2857 if (pCreateInfo
->pEnabledFeatures
) {
2858 VkPhysicalDeviceFeatures supported_features
;
2859 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
2860 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
2861 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
2862 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
2863 for (uint32_t i
= 0; i
< num_features
; i
++) {
2864 if (enabled_feature
[i
] && !supported_feature
[i
])
2865 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
2869 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
2871 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2873 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2875 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2876 device
->instance
= physical_device
->instance
;
2877 device
->physical_device
= physical_device
;
2879 device
->ws
= physical_device
->ws
;
2881 device
->alloc
= *pAllocator
;
2883 device
->alloc
= physical_device
->instance
->alloc
;
2885 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
2886 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
2887 int index
= radv_get_device_extension_index(ext_name
);
2888 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
2889 vk_free(&device
->alloc
, device
);
2890 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
2893 device
->enabled_extensions
.extensions
[index
] = true;
2896 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
2898 /* With update after bind we can't attach bo's to the command buffer
2899 * from the descriptor set anymore, so we have to use a global BO list.
2901 device
->use_global_bo_list
=
2902 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
2903 device
->enabled_extensions
.EXT_descriptor_indexing
||
2904 device
->enabled_extensions
.EXT_buffer_device_address
||
2905 device
->enabled_extensions
.KHR_buffer_device_address
;
2907 device
->robust_buffer_access
= pCreateInfo
->pEnabledFeatures
&&
2908 pCreateInfo
->pEnabledFeatures
->robustBufferAccess
;
2910 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
2911 list_inithead(&device
->shader_slabs
);
2913 radv_bo_list_init(&device
->bo_list
);
2915 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
2916 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
2917 uint32_t qfi
= queue_create
->queueFamilyIndex
;
2918 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
2919 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
2921 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
2923 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
2924 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2925 if (!device
->queues
[qfi
]) {
2926 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2930 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
2932 device
->queue_count
[qfi
] = queue_create
->queueCount
;
2934 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
2935 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
2936 qfi
, q
, queue_create
->flags
,
2938 if (result
!= VK_SUCCESS
)
2943 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2944 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
2946 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2947 device
->dfsm_allowed
= device
->pbb_allowed
&&
2948 (device
->instance
->perftest_flags
& RADV_PERFTEST_DFSM
);
2950 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
2952 /* The maximum number of scratch waves. Scratch space isn't divided
2953 * evenly between CUs. The number is only a function of the number of CUs.
2954 * We can decrease the constant to decrease the scratch buffer size.
2956 * sctx->scratch_waves must be >= the maximum possible size of
2957 * 1 threadgroup, so that the hw doesn't hang from being unable
2960 * The recommended value is 4 per CU at most. Higher numbers don't
2961 * bring much benefit, but they still occupy chip resources (think
2962 * async compute). I've seen ~2% performance difference between 4 and 32.
2964 uint32_t max_threads_per_block
= 2048;
2965 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
2966 max_threads_per_block
/ 64);
2968 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1);
2970 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2971 /* If the KMD allows it (there is a KMD hw register for it),
2972 * allow launching waves out-of-order.
2974 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
2977 radv_device_init_gs_info(device
);
2979 device
->tess_offchip_block_dw_size
=
2980 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
2982 if (getenv("RADV_TRACE_FILE")) {
2983 const char *filename
= getenv("RADV_TRACE_FILE");
2985 keep_shader_info
= true;
2987 if (!radv_init_trace(device
))
2990 fprintf(stderr
, "*****************************************************************************\n");
2991 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2992 fprintf(stderr
, "*****************************************************************************\n");
2994 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
2995 radv_dump_enabled_options(device
, stderr
);
2998 /* Temporarily disable secure compile while we create meta shaders, etc */
2999 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
3001 device
->instance
->num_sc_threads
= 0;
3003 device
->keep_shader_info
= keep_shader_info
;
3004 result
= radv_device_init_meta(device
);
3005 if (result
!= VK_SUCCESS
)
3008 radv_device_init_msaa(device
);
3010 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
3011 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
3013 case RADV_QUEUE_GENERAL
:
3014 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
3015 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
3016 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
3018 case RADV_QUEUE_COMPUTE
:
3019 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
3020 radeon_emit(device
->empty_cs
[family
], 0);
3023 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
3026 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
3027 cik_create_gfx_config(device
);
3029 VkPipelineCacheCreateInfo ci
;
3030 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
3033 ci
.pInitialData
= NULL
;
3034 ci
.initialDataSize
= 0;
3036 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
3038 if (result
!= VK_SUCCESS
)
3041 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
3043 result
= radv_create_pthread_cond(&device
->timeline_cond
);
3044 if (result
!= VK_SUCCESS
)
3045 goto fail_mem_cache
;
3047 device
->force_aniso
=
3048 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
3049 if (device
->force_aniso
>= 0) {
3050 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
3051 1 << util_logbase2(device
->force_aniso
));
3054 /* Fork device for secure compile as required */
3055 device
->instance
->num_sc_threads
= sc_threads
;
3056 if (radv_device_use_secure_compile(device
->instance
)) {
3058 result
= fork_secure_compile_idle_device(device
);
3059 if (result
!= VK_SUCCESS
)
3063 *pDevice
= radv_device_to_handle(device
);
3067 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
3069 radv_device_finish_meta(device
);
3071 radv_bo_list_finish(&device
->bo_list
);
3073 if (device
->trace_bo
)
3074 device
->ws
->buffer_destroy(device
->trace_bo
);
3076 if (device
->gfx_init
)
3077 device
->ws
->buffer_destroy(device
->gfx_init
);
3079 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3080 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
3081 radv_queue_finish(&device
->queues
[i
][q
]);
3082 if (device
->queue_count
[i
])
3083 vk_free(&device
->alloc
, device
->queues
[i
]);
3086 vk_free(&device
->alloc
, device
);
3090 void radv_DestroyDevice(
3092 const VkAllocationCallbacks
* pAllocator
)
3094 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3099 if (device
->trace_bo
)
3100 device
->ws
->buffer_destroy(device
->trace_bo
);
3102 if (device
->gfx_init
)
3103 device
->ws
->buffer_destroy(device
->gfx_init
);
3105 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3106 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
3107 radv_queue_finish(&device
->queues
[i
][q
]);
3108 if (device
->queue_count
[i
])
3109 vk_free(&device
->alloc
, device
->queues
[i
]);
3110 if (device
->empty_cs
[i
])
3111 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
3113 radv_device_finish_meta(device
);
3115 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
3116 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
3118 radv_destroy_shader_slabs(device
);
3120 pthread_cond_destroy(&device
->timeline_cond
);
3121 radv_bo_list_finish(&device
->bo_list
);
3122 if (radv_device_use_secure_compile(device
->instance
)) {
3123 for (unsigned i
= 0; i
< device
->instance
->num_sc_threads
; i
++ ) {
3124 destroy_secure_compile_device(device
, i
);
3128 if (device
->sc_state
) {
3129 free(device
->sc_state
->uid
);
3130 vk_free(&device
->alloc
, device
->sc_state
->secure_compile_processes
);
3132 vk_free(&device
->alloc
, device
->sc_state
);
3133 vk_free(&device
->alloc
, device
);
3136 VkResult
radv_EnumerateInstanceLayerProperties(
3137 uint32_t* pPropertyCount
,
3138 VkLayerProperties
* pProperties
)
3140 if (pProperties
== NULL
) {
3141 *pPropertyCount
= 0;
3145 /* None supported at this time */
3146 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
3149 VkResult
radv_EnumerateDeviceLayerProperties(
3150 VkPhysicalDevice physicalDevice
,
3151 uint32_t* pPropertyCount
,
3152 VkLayerProperties
* pProperties
)
3154 if (pProperties
== NULL
) {
3155 *pPropertyCount
= 0;
3159 /* None supported at this time */
3160 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
3163 void radv_GetDeviceQueue2(
3165 const VkDeviceQueueInfo2
* pQueueInfo
,
3168 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3169 struct radv_queue
*queue
;
3171 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
3172 if (pQueueInfo
->flags
!= queue
->flags
) {
3173 /* From the Vulkan 1.1.70 spec:
3175 * "The queue returned by vkGetDeviceQueue2 must have the same
3176 * flags value from this structure as that used at device
3177 * creation time in a VkDeviceQueueCreateInfo instance. If no
3178 * matching flags were specified at device creation time then
3179 * pQueue will return VK_NULL_HANDLE."
3181 *pQueue
= VK_NULL_HANDLE
;
3185 *pQueue
= radv_queue_to_handle(queue
);
3188 void radv_GetDeviceQueue(
3190 uint32_t queueFamilyIndex
,
3191 uint32_t queueIndex
,
3194 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
3195 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
3196 .queueFamilyIndex
= queueFamilyIndex
,
3197 .queueIndex
= queueIndex
3200 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
3204 fill_geom_tess_rings(struct radv_queue
*queue
,
3206 bool add_sample_positions
,
3207 uint32_t esgs_ring_size
,
3208 struct radeon_winsys_bo
*esgs_ring_bo
,
3209 uint32_t gsvs_ring_size
,
3210 struct radeon_winsys_bo
*gsvs_ring_bo
,
3211 uint32_t tess_factor_ring_size
,
3212 uint32_t tess_offchip_ring_offset
,
3213 uint32_t tess_offchip_ring_size
,
3214 struct radeon_winsys_bo
*tess_rings_bo
)
3216 uint32_t *desc
= &map
[4];
3219 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
3221 /* stride 0, num records - size, add tid, swizzle, elsize4,
3224 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
3225 S_008F04_SWIZZLE_ENABLE(true);
3226 desc
[2] = esgs_ring_size
;
3227 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3228 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3229 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3230 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3231 S_008F0C_INDEX_STRIDE(3) |
3232 S_008F0C_ADD_TID_ENABLE(1);
3234 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3235 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3236 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3237 S_008F0C_RESOURCE_LEVEL(1);
3239 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3240 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
3241 S_008F0C_ELEMENT_SIZE(1);
3244 /* GS entry for ES->GS ring */
3245 /* stride 0, num records - size, elsize0,
3248 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32);
3249 desc
[6] = esgs_ring_size
;
3250 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3251 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3252 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3253 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3255 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3256 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3257 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3258 S_008F0C_RESOURCE_LEVEL(1);
3260 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3261 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3268 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
3270 /* VS entry for GS->VS ring */
3271 /* stride 0, num records - size, elsize0,
3274 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32);
3275 desc
[2] = gsvs_ring_size
;
3276 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3277 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3278 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3279 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3281 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3282 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3283 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3284 S_008F0C_RESOURCE_LEVEL(1);
3286 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3287 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3290 /* stride gsvs_itemsize, num records 64
3291 elsize 4, index stride 16 */
3292 /* shader will patch stride and desc[2] */
3294 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32) |
3295 S_008F04_SWIZZLE_ENABLE(1);
3297 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3298 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3299 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3300 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3301 S_008F0C_INDEX_STRIDE(1) |
3302 S_008F0C_ADD_TID_ENABLE(true);
3304 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3305 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3306 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3307 S_008F0C_RESOURCE_LEVEL(1);
3309 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3310 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
3311 S_008F0C_ELEMENT_SIZE(1);
3318 if (tess_rings_bo
) {
3319 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
3320 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
3323 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32);
3324 desc
[2] = tess_factor_ring_size
;
3325 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3326 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3327 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3328 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3330 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3331 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3332 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3333 S_008F0C_RESOURCE_LEVEL(1);
3335 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3336 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3339 desc
[4] = tess_offchip_va
;
3340 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32);
3341 desc
[6] = tess_offchip_ring_size
;
3342 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3343 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3344 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3345 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3347 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3348 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3349 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3350 S_008F0C_RESOURCE_LEVEL(1);
3352 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3353 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3359 if (add_sample_positions
) {
3360 /* add sample positions after all rings */
3361 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
3363 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
3365 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
3367 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
3372 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
3374 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= GFX7
&&
3375 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
3376 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
3377 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
3378 unsigned max_offchip_buffers
;
3379 unsigned offchip_granularity
;
3380 unsigned hs_offchip_param
;
3384 * This must be one less than the maximum number due to a hw limitation.
3385 * Various hardware bugs need thGFX7
3388 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3389 * Gfx7 should limit max_offchip_buffers to 508
3390 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3392 * Follow AMDVLK here.
3394 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3395 max_offchip_buffers_per_se
= 256;
3396 } else if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
3397 device
->physical_device
->rad_info
.chip_class
== GFX7
||
3398 device
->physical_device
->rad_info
.chip_class
== GFX6
)
3399 --max_offchip_buffers_per_se
;
3401 max_offchip_buffers
= max_offchip_buffers_per_se
*
3402 device
->physical_device
->rad_info
.max_se
;
3404 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3405 * around by setting 4K granularity.
3407 if (device
->tess_offchip_block_dw_size
== 4096) {
3408 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
3409 offchip_granularity
= V_03093C_X_4K_DWORDS
;
3411 assert(device
->tess_offchip_block_dw_size
== 8192);
3412 offchip_granularity
= V_03093C_X_8K_DWORDS
;
3415 switch (device
->physical_device
->rad_info
.chip_class
) {
3417 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
3422 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
3430 *max_offchip_buffers_p
= max_offchip_buffers
;
3431 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3432 if (device
->physical_device
->rad_info
.chip_class
>= GFX8
)
3433 --max_offchip_buffers
;
3435 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
3436 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
3439 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
3441 return hs_offchip_param
;
3445 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3446 struct radeon_winsys_bo
*esgs_ring_bo
,
3447 uint32_t esgs_ring_size
,
3448 struct radeon_winsys_bo
*gsvs_ring_bo
,
3449 uint32_t gsvs_ring_size
)
3451 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
3455 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
3458 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
3460 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3461 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
3462 radeon_emit(cs
, esgs_ring_size
>> 8);
3463 radeon_emit(cs
, gsvs_ring_size
>> 8);
3465 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
3466 radeon_emit(cs
, esgs_ring_size
>> 8);
3467 radeon_emit(cs
, gsvs_ring_size
>> 8);
3472 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3473 unsigned hs_offchip_param
, unsigned tf_ring_size
,
3474 struct radeon_winsys_bo
*tess_rings_bo
)
3481 tf_va
= radv_buffer_get_va(tess_rings_bo
);
3483 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
3485 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3486 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
3487 S_030938_SIZE(tf_ring_size
/ 4));
3488 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
3491 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3492 radeon_set_uconfig_reg(cs
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3493 S_030984_BASE_HI(tf_va
>> 40));
3494 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3495 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3496 S_030944_BASE_HI(tf_va
>> 40));
3498 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3501 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
3502 S_008988_SIZE(tf_ring_size
/ 4));
3503 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
3505 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3511 radv_emit_graphics_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3512 uint32_t size_per_wave
, uint32_t waves
,
3513 struct radeon_winsys_bo
*scratch_bo
)
3515 if (queue
->queue_family_index
!= RADV_QUEUE_GENERAL
)
3521 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3523 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3524 S_0286E8_WAVES(waves
) |
3525 S_0286E8_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3529 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3530 uint32_t size_per_wave
, uint32_t waves
,
3531 struct radeon_winsys_bo
*compute_scratch_bo
)
3533 uint64_t scratch_va
;
3535 if (!compute_scratch_bo
)
3538 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
3540 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
3542 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
3543 radeon_emit(cs
, scratch_va
);
3544 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3545 S_008F04_SWIZZLE_ENABLE(1));
3547 radeon_set_sh_reg(cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
3548 S_00B860_WAVES(waves
) |
3549 S_00B860_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3553 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
3554 struct radeon_cmdbuf
*cs
,
3555 struct radeon_winsys_bo
*descriptor_bo
)
3562 va
= radv_buffer_get_va(descriptor_bo
);
3564 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
3566 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3567 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3568 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3569 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3570 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3572 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3573 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3576 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3577 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3578 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3579 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3580 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3582 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3583 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3587 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3588 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3589 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
3590 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
3591 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
3592 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
3594 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3595 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3602 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3604 struct radv_device
*device
= queue
->device
;
3606 if (device
->gfx_init
) {
3607 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
3609 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
3610 radeon_emit(cs
, va
);
3611 radeon_emit(cs
, va
>> 32);
3612 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
3614 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
3616 struct radv_physical_device
*physical_device
= device
->physical_device
;
3617 si_emit_graphics(physical_device
, cs
);
3622 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3624 struct radv_physical_device
*physical_device
= queue
->device
->physical_device
;
3625 si_emit_compute(physical_device
, cs
);
3629 radv_get_preamble_cs(struct radv_queue
*queue
,
3630 uint32_t scratch_size_per_wave
,
3631 uint32_t scratch_waves
,
3632 uint32_t compute_scratch_size_per_wave
,
3633 uint32_t compute_scratch_waves
,
3634 uint32_t esgs_ring_size
,
3635 uint32_t gsvs_ring_size
,
3636 bool needs_tess_rings
,
3639 bool needs_sample_positions
,
3640 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
3641 struct radeon_cmdbuf
**initial_preamble_cs
,
3642 struct radeon_cmdbuf
**continue_preamble_cs
)
3644 struct radeon_winsys_bo
*scratch_bo
= NULL
;
3645 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
3646 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
3647 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
3648 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
3649 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
3650 struct radeon_winsys_bo
*gds_bo
= NULL
;
3651 struct radeon_winsys_bo
*gds_oa_bo
= NULL
;
3652 struct radeon_cmdbuf
*dest_cs
[3] = {0};
3653 bool add_tess_rings
= false, add_gds
= false, add_gds_oa
= false, add_sample_positions
= false;
3654 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
3655 unsigned max_offchip_buffers
;
3656 unsigned hs_offchip_param
= 0;
3657 unsigned tess_offchip_ring_offset
;
3658 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3659 if (!queue
->has_tess_rings
) {
3660 if (needs_tess_rings
)
3661 add_tess_rings
= true;
3663 if (!queue
->has_gds
) {
3667 if (!queue
->has_gds_oa
) {
3671 if (!queue
->has_sample_positions
) {
3672 if (needs_sample_positions
)
3673 add_sample_positions
= true;
3675 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
3676 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
3677 &max_offchip_buffers
);
3678 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
3679 tess_offchip_ring_size
= max_offchip_buffers
*
3680 queue
->device
->tess_offchip_block_dw_size
* 4;
3682 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, queue
->scratch_size_per_wave
);
3683 if (scratch_size_per_wave
)
3684 scratch_waves
= MIN2(scratch_waves
, UINT32_MAX
/ scratch_size_per_wave
);
3688 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
, queue
->compute_scratch_size_per_wave
);
3689 if (compute_scratch_size_per_wave
)
3690 compute_scratch_waves
= MIN2(compute_scratch_waves
, UINT32_MAX
/ compute_scratch_size_per_wave
);
3692 compute_scratch_waves
= 0;
3694 if (scratch_size_per_wave
<= queue
->scratch_size_per_wave
&&
3695 scratch_waves
<= queue
->scratch_waves
&&
3696 compute_scratch_size_per_wave
<= queue
->compute_scratch_size_per_wave
&&
3697 compute_scratch_waves
<= queue
->compute_scratch_waves
&&
3698 esgs_ring_size
<= queue
->esgs_ring_size
&&
3699 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
3700 !add_tess_rings
&& !add_gds
&& !add_gds_oa
&& !add_sample_positions
&&
3701 queue
->initial_preamble_cs
) {
3702 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
3703 *initial_preamble_cs
= queue
->initial_preamble_cs
;
3704 *continue_preamble_cs
= queue
->continue_preamble_cs
;
3705 if (!scratch_size_per_wave
&& !compute_scratch_size_per_wave
&&
3706 !esgs_ring_size
&& !gsvs_ring_size
&& !needs_tess_rings
&&
3707 !needs_gds
&& !needs_gds_oa
&& !needs_sample_positions
)
3708 *continue_preamble_cs
= NULL
;
3712 uint32_t scratch_size
= scratch_size_per_wave
* scratch_waves
;
3713 uint32_t queue_scratch_size
= queue
->scratch_size_per_wave
* queue
->scratch_waves
;
3714 if (scratch_size
> queue_scratch_size
) {
3715 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3720 RADV_BO_PRIORITY_SCRATCH
);
3724 scratch_bo
= queue
->scratch_bo
;
3726 uint32_t compute_scratch_size
= compute_scratch_size_per_wave
* compute_scratch_waves
;
3727 uint32_t compute_queue_scratch_size
= queue
->compute_scratch_size_per_wave
* queue
->compute_scratch_waves
;
3728 if (compute_scratch_size
> compute_queue_scratch_size
) {
3729 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3730 compute_scratch_size
,
3734 RADV_BO_PRIORITY_SCRATCH
);
3735 if (!compute_scratch_bo
)
3739 compute_scratch_bo
= queue
->compute_scratch_bo
;
3741 if (esgs_ring_size
> queue
->esgs_ring_size
) {
3742 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3747 RADV_BO_PRIORITY_SCRATCH
);
3751 esgs_ring_bo
= queue
->esgs_ring_bo
;
3752 esgs_ring_size
= queue
->esgs_ring_size
;
3755 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
3756 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3761 RADV_BO_PRIORITY_SCRATCH
);
3765 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
3766 gsvs_ring_size
= queue
->gsvs_ring_size
;
3769 if (add_tess_rings
) {
3770 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3771 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
3775 RADV_BO_PRIORITY_SCRATCH
);
3779 tess_rings_bo
= queue
->tess_rings_bo
;
3783 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3785 /* 4 streamout GDS counters.
3786 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3788 gds_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3792 RADV_BO_PRIORITY_SCRATCH
);
3796 gds_bo
= queue
->gds_bo
;
3800 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3802 gds_oa_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3806 RADV_BO_PRIORITY_SCRATCH
);
3810 gds_oa_bo
= queue
->gds_oa_bo
;
3813 if (scratch_bo
!= queue
->scratch_bo
||
3814 esgs_ring_bo
!= queue
->esgs_ring_bo
||
3815 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
3816 tess_rings_bo
!= queue
->tess_rings_bo
||
3817 add_sample_positions
) {
3819 if (gsvs_ring_bo
|| esgs_ring_bo
||
3820 tess_rings_bo
|| add_sample_positions
) {
3821 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
3822 if (add_sample_positions
)
3823 size
+= 128; /* 64+32+16+8 = 120 bytes */
3825 else if (scratch_bo
)
3826 size
= 8; /* 2 dword */
3828 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3832 RADEON_FLAG_CPU_ACCESS
|
3833 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
3834 RADEON_FLAG_READ_ONLY
,
3835 RADV_BO_PRIORITY_DESCRIPTOR
);
3839 descriptor_bo
= queue
->descriptor_bo
;
3841 if (descriptor_bo
!= queue
->descriptor_bo
) {
3842 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
3845 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
3846 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3847 S_008F04_SWIZZLE_ENABLE(1);
3848 map
[0] = scratch_va
;
3852 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
3853 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
3854 esgs_ring_size
, esgs_ring_bo
,
3855 gsvs_ring_size
, gsvs_ring_bo
,
3856 tess_factor_ring_size
,
3857 tess_offchip_ring_offset
,
3858 tess_offchip_ring_size
,
3861 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
3864 for(int i
= 0; i
< 3; ++i
) {
3865 struct radeon_cmdbuf
*cs
= NULL
;
3866 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
3867 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
3874 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3876 /* Emit initial configuration. */
3877 switch (queue
->queue_family_index
) {
3878 case RADV_QUEUE_GENERAL
:
3879 radv_init_graphics_state(cs
, queue
);
3881 case RADV_QUEUE_COMPUTE
:
3882 radv_init_compute_state(cs
, queue
);
3884 case RADV_QUEUE_TRANSFER
:
3888 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
3889 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3890 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3892 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3893 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3896 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
3897 gsvs_ring_bo
, gsvs_ring_size
);
3898 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
3899 tess_factor_ring_size
, tess_rings_bo
);
3900 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
3901 radv_emit_compute_scratch(queue
, cs
, compute_scratch_size_per_wave
,
3902 compute_scratch_waves
, compute_scratch_bo
);
3903 radv_emit_graphics_scratch(queue
, cs
, scratch_size_per_wave
,
3904 scratch_waves
, scratch_bo
);
3907 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_bo
);
3909 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_oa_bo
);
3912 si_cs_emit_cache_flush(cs
,
3913 queue
->device
->physical_device
->rad_info
.chip_class
,
3915 queue
->queue_family_index
== RING_COMPUTE
&&
3916 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3917 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
3918 RADV_CMD_FLAG_INV_ICACHE
|
3919 RADV_CMD_FLAG_INV_SCACHE
|
3920 RADV_CMD_FLAG_INV_VCACHE
|
3921 RADV_CMD_FLAG_INV_L2
|
3922 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
3923 } else if (i
== 1) {
3924 si_cs_emit_cache_flush(cs
,
3925 queue
->device
->physical_device
->rad_info
.chip_class
,
3927 queue
->queue_family_index
== RING_COMPUTE
&&
3928 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3929 RADV_CMD_FLAG_INV_ICACHE
|
3930 RADV_CMD_FLAG_INV_SCACHE
|
3931 RADV_CMD_FLAG_INV_VCACHE
|
3932 RADV_CMD_FLAG_INV_L2
|
3933 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
3936 if (!queue
->device
->ws
->cs_finalize(cs
))
3940 if (queue
->initial_full_flush_preamble_cs
)
3941 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
3943 if (queue
->initial_preamble_cs
)
3944 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
3946 if (queue
->continue_preamble_cs
)
3947 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
3949 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
3950 queue
->initial_preamble_cs
= dest_cs
[1];
3951 queue
->continue_preamble_cs
= dest_cs
[2];
3953 if (scratch_bo
!= queue
->scratch_bo
) {
3954 if (queue
->scratch_bo
)
3955 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
3956 queue
->scratch_bo
= scratch_bo
;
3958 queue
->scratch_size_per_wave
= scratch_size_per_wave
;
3959 queue
->scratch_waves
= scratch_waves
;
3961 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
3962 if (queue
->compute_scratch_bo
)
3963 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
3964 queue
->compute_scratch_bo
= compute_scratch_bo
;
3966 queue
->compute_scratch_size_per_wave
= compute_scratch_size_per_wave
;
3967 queue
->compute_scratch_waves
= compute_scratch_waves
;
3969 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
3970 if (queue
->esgs_ring_bo
)
3971 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
3972 queue
->esgs_ring_bo
= esgs_ring_bo
;
3973 queue
->esgs_ring_size
= esgs_ring_size
;
3976 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
3977 if (queue
->gsvs_ring_bo
)
3978 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
3979 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
3980 queue
->gsvs_ring_size
= gsvs_ring_size
;
3983 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
3984 queue
->tess_rings_bo
= tess_rings_bo
;
3985 queue
->has_tess_rings
= true;
3988 if (gds_bo
!= queue
->gds_bo
) {
3989 queue
->gds_bo
= gds_bo
;
3990 queue
->has_gds
= true;
3993 if (gds_oa_bo
!= queue
->gds_oa_bo
) {
3994 queue
->gds_oa_bo
= gds_oa_bo
;
3995 queue
->has_gds_oa
= true;
3998 if (descriptor_bo
!= queue
->descriptor_bo
) {
3999 if (queue
->descriptor_bo
)
4000 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
4002 queue
->descriptor_bo
= descriptor_bo
;
4005 if (add_sample_positions
)
4006 queue
->has_sample_positions
= true;
4008 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
4009 *initial_preamble_cs
= queue
->initial_preamble_cs
;
4010 *continue_preamble_cs
= queue
->continue_preamble_cs
;
4011 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
4012 *continue_preamble_cs
= NULL
;
4015 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
4017 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
4018 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
4019 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
4020 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
4021 queue
->device
->ws
->buffer_destroy(scratch_bo
);
4022 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
4023 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
4024 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
4025 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
4026 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
4027 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
4028 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
4029 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
4030 if (gds_bo
&& gds_bo
!= queue
->gds_bo
)
4031 queue
->device
->ws
->buffer_destroy(gds_bo
);
4032 if (gds_oa_bo
&& gds_oa_bo
!= queue
->gds_oa_bo
)
4033 queue
->device
->ws
->buffer_destroy(gds_oa_bo
);
4035 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4038 static VkResult
radv_alloc_sem_counts(struct radv_device
*device
,
4039 struct radv_winsys_sem_counts
*counts
,
4041 struct radv_semaphore_part
**sems
,
4042 const uint64_t *timeline_values
,
4046 int syncobj_idx
= 0, sem_idx
= 0;
4048 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
4051 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4052 switch(sems
[i
]->kind
) {
4053 case RADV_SEMAPHORE_SYNCOBJ
:
4054 counts
->syncobj_count
++;
4056 case RADV_SEMAPHORE_WINSYS
:
4057 counts
->sem_count
++;
4059 case RADV_SEMAPHORE_NONE
:
4061 case RADV_SEMAPHORE_TIMELINE
:
4062 counts
->syncobj_count
++;
4067 if (_fence
!= VK_NULL_HANDLE
) {
4068 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4069 if (fence
->temp_syncobj
|| fence
->syncobj
)
4070 counts
->syncobj_count
++;
4073 if (counts
->syncobj_count
) {
4074 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
4075 if (!counts
->syncobj
)
4076 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4079 if (counts
->sem_count
) {
4080 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
4082 free(counts
->syncobj
);
4083 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4087 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4088 switch(sems
[i
]->kind
) {
4089 case RADV_SEMAPHORE_NONE
:
4090 unreachable("Empty semaphore");
4092 case RADV_SEMAPHORE_SYNCOBJ
:
4093 counts
->syncobj
[syncobj_idx
++] = sems
[i
]->syncobj
;
4095 case RADV_SEMAPHORE_WINSYS
:
4096 counts
->sem
[sem_idx
++] = sems
[i
]->ws_sem
;
4098 case RADV_SEMAPHORE_TIMELINE
: {
4099 pthread_mutex_lock(&sems
[i
]->timeline
.mutex
);
4100 struct radv_timeline_point
*point
= NULL
;
4102 point
= radv_timeline_add_point_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
4104 point
= radv_timeline_find_point_at_least_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
4107 pthread_mutex_unlock(&sems
[i
]->timeline
.mutex
);
4110 counts
->syncobj
[syncobj_idx
++] = point
->syncobj
;
4112 /* Explicitly remove the semaphore so we might not find
4113 * a point later post-submit. */
4121 if (_fence
!= VK_NULL_HANDLE
) {
4122 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4123 if (fence
->temp_syncobj
)
4124 counts
->syncobj
[syncobj_idx
++] = fence
->temp_syncobj
;
4125 else if (fence
->syncobj
)
4126 counts
->syncobj
[syncobj_idx
++] = fence
->syncobj
;
4129 assert(syncobj_idx
<= counts
->syncobj_count
);
4130 counts
->syncobj_count
= syncobj_idx
;
4136 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
4138 free(sem_info
->wait
.syncobj
);
4139 free(sem_info
->wait
.sem
);
4140 free(sem_info
->signal
.syncobj
);
4141 free(sem_info
->signal
.sem
);
4145 static void radv_free_temp_syncobjs(struct radv_device
*device
,
4147 struct radv_semaphore_part
*sems
)
4149 for (uint32_t i
= 0; i
< num_sems
; i
++) {
4150 radv_destroy_semaphore_part(device
, sems
+ i
);
4155 radv_alloc_sem_info(struct radv_device
*device
,
4156 struct radv_winsys_sem_info
*sem_info
,
4158 struct radv_semaphore_part
**wait_sems
,
4159 const uint64_t *wait_values
,
4160 int num_signal_sems
,
4161 struct radv_semaphore_part
**signal_sems
,
4162 const uint64_t *signal_values
,
4166 memset(sem_info
, 0, sizeof(*sem_info
));
4168 ret
= radv_alloc_sem_counts(device
, &sem_info
->wait
, num_wait_sems
, wait_sems
, wait_values
, VK_NULL_HANDLE
, false);
4171 ret
= radv_alloc_sem_counts(device
, &sem_info
->signal
, num_signal_sems
, signal_sems
, signal_values
, fence
, true);
4173 radv_free_sem_info(sem_info
);
4175 /* caller can override these */
4176 sem_info
->cs_emit_wait
= true;
4177 sem_info
->cs_emit_signal
= true;
4182 radv_finalize_timelines(struct radv_device
*device
,
4183 uint32_t num_wait_sems
,
4184 struct radv_semaphore_part
**wait_sems
,
4185 const uint64_t *wait_values
,
4186 uint32_t num_signal_sems
,
4187 struct radv_semaphore_part
**signal_sems
,
4188 const uint64_t *signal_values
,
4189 struct list_head
*processing_list
)
4191 for (uint32_t i
= 0; i
< num_wait_sems
; ++i
) {
4192 if (wait_sems
[i
] && wait_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4193 pthread_mutex_lock(&wait_sems
[i
]->timeline
.mutex
);
4194 struct radv_timeline_point
*point
=
4195 radv_timeline_find_point_at_least_locked(device
, &wait_sems
[i
]->timeline
, wait_values
[i
]);
4196 point
->wait_count
-= 2;
4197 pthread_mutex_unlock(&wait_sems
[i
]->timeline
.mutex
);
4200 for (uint32_t i
= 0; i
< num_signal_sems
; ++i
) {
4201 if (signal_sems
[i
] && signal_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4202 pthread_mutex_lock(&signal_sems
[i
]->timeline
.mutex
);
4203 struct radv_timeline_point
*point
=
4204 radv_timeline_find_point_at_least_locked(device
, &signal_sems
[i
]->timeline
, signal_values
[i
]);
4205 signal_sems
[i
]->timeline
.highest_submitted
=
4206 MAX2(signal_sems
[i
]->timeline
.highest_submitted
, point
->value
);
4207 point
->wait_count
-= 2;
4208 radv_timeline_trigger_waiters_locked(&signal_sems
[i
]->timeline
, processing_list
);
4209 pthread_mutex_unlock(&signal_sems
[i
]->timeline
.mutex
);
4215 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
4216 const VkSparseBufferMemoryBindInfo
*bind
)
4218 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
4220 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
4221 struct radv_device_memory
*mem
= NULL
;
4223 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
4224 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
4226 device
->ws
->buffer_virtual_bind(buffer
->bo
,
4227 bind
->pBinds
[i
].resourceOffset
,
4228 bind
->pBinds
[i
].size
,
4229 mem
? mem
->bo
: NULL
,
4230 bind
->pBinds
[i
].memoryOffset
);
4235 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
4236 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
4238 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
4240 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
4241 struct radv_device_memory
*mem
= NULL
;
4243 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
4244 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
4246 device
->ws
->buffer_virtual_bind(image
->bo
,
4247 bind
->pBinds
[i
].resourceOffset
,
4248 bind
->pBinds
[i
].size
,
4249 mem
? mem
->bo
: NULL
,
4250 bind
->pBinds
[i
].memoryOffset
);
4255 radv_get_preambles(struct radv_queue
*queue
,
4256 const VkCommandBuffer
*cmd_buffers
,
4257 uint32_t cmd_buffer_count
,
4258 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
4259 struct radeon_cmdbuf
**initial_preamble_cs
,
4260 struct radeon_cmdbuf
**continue_preamble_cs
)
4262 uint32_t scratch_size_per_wave
= 0, waves_wanted
= 0;
4263 uint32_t compute_scratch_size_per_wave
= 0, compute_waves_wanted
= 0;
4264 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
4265 bool tess_rings_needed
= false;
4266 bool gds_needed
= false;
4267 bool gds_oa_needed
= false;
4268 bool sample_positions_needed
= false;
4270 for (uint32_t j
= 0; j
< cmd_buffer_count
; j
++) {
4271 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
4274 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, cmd_buffer
->scratch_size_per_wave_needed
);
4275 waves_wanted
= MAX2(waves_wanted
, cmd_buffer
->scratch_waves_wanted
);
4276 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
,
4277 cmd_buffer
->compute_scratch_size_per_wave_needed
);
4278 compute_waves_wanted
= MAX2(compute_waves_wanted
,
4279 cmd_buffer
->compute_scratch_waves_wanted
);
4280 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
4281 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
4282 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
4283 gds_needed
|= cmd_buffer
->gds_needed
;
4284 gds_oa_needed
|= cmd_buffer
->gds_oa_needed
;
4285 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
4288 return radv_get_preamble_cs(queue
, scratch_size_per_wave
, waves_wanted
,
4289 compute_scratch_size_per_wave
, compute_waves_wanted
,
4290 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
4291 gds_needed
, gds_oa_needed
, sample_positions_needed
,
4292 initial_full_flush_preamble_cs
,
4293 initial_preamble_cs
, continue_preamble_cs
);
4296 struct radv_deferred_queue_submission
{
4297 struct radv_queue
*queue
;
4298 VkCommandBuffer
*cmd_buffers
;
4299 uint32_t cmd_buffer_count
;
4301 /* Sparse bindings that happen on a queue. */
4302 VkSparseBufferMemoryBindInfo
*buffer_binds
;
4303 uint32_t buffer_bind_count
;
4304 VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4305 uint32_t image_opaque_bind_count
;
4308 VkShaderStageFlags wait_dst_stage_mask
;
4309 struct radv_semaphore_part
**wait_semaphores
;
4310 uint32_t wait_semaphore_count
;
4311 struct radv_semaphore_part
**signal_semaphores
;
4312 uint32_t signal_semaphore_count
;
4315 uint64_t *wait_values
;
4316 uint64_t *signal_values
;
4318 struct radv_semaphore_part
*temporary_semaphore_parts
;
4319 uint32_t temporary_semaphore_part_count
;
4321 struct list_head queue_pending_list
;
4322 uint32_t submission_wait_count
;
4323 struct radv_timeline_waiter
*wait_nodes
;
4325 struct list_head processing_list
;
4328 struct radv_queue_submission
{
4329 const VkCommandBuffer
*cmd_buffers
;
4330 uint32_t cmd_buffer_count
;
4332 /* Sparse bindings that happen on a queue. */
4333 const VkSparseBufferMemoryBindInfo
*buffer_binds
;
4334 uint32_t buffer_bind_count
;
4335 const VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4336 uint32_t image_opaque_bind_count
;
4339 VkPipelineStageFlags wait_dst_stage_mask
;
4340 const VkSemaphore
*wait_semaphores
;
4341 uint32_t wait_semaphore_count
;
4342 const VkSemaphore
*signal_semaphores
;
4343 uint32_t signal_semaphore_count
;
4346 const uint64_t *wait_values
;
4347 uint32_t wait_value_count
;
4348 const uint64_t *signal_values
;
4349 uint32_t signal_value_count
;
4353 radv_create_deferred_submission(struct radv_queue
*queue
,
4354 const struct radv_queue_submission
*submission
,
4355 struct radv_deferred_queue_submission
**out
)
4357 struct radv_deferred_queue_submission
*deferred
= NULL
;
4358 size_t size
= sizeof(struct radv_deferred_queue_submission
);
4360 uint32_t temporary_count
= 0;
4361 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4362 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4363 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
)
4367 size
+= submission
->cmd_buffer_count
* sizeof(VkCommandBuffer
);
4368 size
+= submission
->buffer_bind_count
* sizeof(VkSparseBufferMemoryBindInfo
);
4369 size
+= submission
->image_opaque_bind_count
* sizeof(VkSparseImageOpaqueMemoryBindInfo
);
4370 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4371 size
+= temporary_count
* sizeof(struct radv_semaphore_part
);
4372 size
+= submission
->signal_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4373 size
+= submission
->wait_value_count
* sizeof(uint64_t);
4374 size
+= submission
->signal_value_count
* sizeof(uint64_t);
4375 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_timeline_waiter
);
4377 deferred
= calloc(1, size
);
4379 return VK_ERROR_OUT_OF_HOST_MEMORY
;
4381 deferred
->queue
= queue
;
4383 deferred
->cmd_buffers
= (void*)(deferred
+ 1);
4384 deferred
->cmd_buffer_count
= submission
->cmd_buffer_count
;
4385 memcpy(deferred
->cmd_buffers
, submission
->cmd_buffers
,
4386 submission
->cmd_buffer_count
* sizeof(*deferred
->cmd_buffers
));
4388 deferred
->buffer_binds
= (void*)(deferred
->cmd_buffers
+ submission
->cmd_buffer_count
);
4389 deferred
->buffer_bind_count
= submission
->buffer_bind_count
;
4390 memcpy(deferred
->buffer_binds
, submission
->buffer_binds
,
4391 submission
->buffer_bind_count
* sizeof(*deferred
->buffer_binds
));
4393 deferred
->image_opaque_binds
= (void*)(deferred
->buffer_binds
+ submission
->buffer_bind_count
);
4394 deferred
->image_opaque_bind_count
= submission
->image_opaque_bind_count
;
4395 memcpy(deferred
->image_opaque_binds
, submission
->image_opaque_binds
,
4396 submission
->image_opaque_bind_count
* sizeof(*deferred
->image_opaque_binds
));
4398 deferred
->flush_caches
= submission
->flush_caches
;
4399 deferred
->wait_dst_stage_mask
= submission
->wait_dst_stage_mask
;
4401 deferred
->wait_semaphores
= (void*)(deferred
->image_opaque_binds
+ deferred
->image_opaque_bind_count
);
4402 deferred
->wait_semaphore_count
= submission
->wait_semaphore_count
;
4404 deferred
->signal_semaphores
= (void*)(deferred
->wait_semaphores
+ deferred
->wait_semaphore_count
);
4405 deferred
->signal_semaphore_count
= submission
->signal_semaphore_count
;
4407 deferred
->fence
= submission
->fence
;
4409 deferred
->temporary_semaphore_parts
= (void*)(deferred
->signal_semaphores
+ deferred
->signal_semaphore_count
);
4410 deferred
->temporary_semaphore_part_count
= temporary_count
;
4412 uint32_t temporary_idx
= 0;
4413 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4414 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4415 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4416 deferred
->wait_semaphores
[i
] = &deferred
->temporary_semaphore_parts
[temporary_idx
];
4417 deferred
->temporary_semaphore_parts
[temporary_idx
] = semaphore
->temporary
;
4418 semaphore
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
4421 deferred
->wait_semaphores
[i
] = &semaphore
->permanent
;
4424 for (uint32_t i
= 0; i
< submission
->signal_semaphore_count
; ++i
) {
4425 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->signal_semaphores
[i
]);
4426 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4427 deferred
->signal_semaphores
[i
] = &semaphore
->temporary
;
4429 deferred
->signal_semaphores
[i
] = &semaphore
->permanent
;
4433 deferred
->wait_values
= (void*)(deferred
->temporary_semaphore_parts
+ temporary_count
);
4434 memcpy(deferred
->wait_values
, submission
->wait_values
, submission
->wait_value_count
* sizeof(uint64_t));
4435 deferred
->signal_values
= deferred
->wait_values
+ submission
->wait_value_count
;
4436 memcpy(deferred
->signal_values
, submission
->signal_values
, submission
->signal_value_count
* sizeof(uint64_t));
4438 deferred
->wait_nodes
= (void*)(deferred
->signal_values
+ submission
->signal_value_count
);
4439 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4440 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4441 deferred
->submission_wait_count
= 1 + submission
->wait_semaphore_count
;
4448 radv_queue_enqueue_submission(struct radv_deferred_queue_submission
*submission
,
4449 struct list_head
*processing_list
)
4451 uint32_t wait_cnt
= 0;
4452 struct radv_timeline_waiter
*waiter
= submission
->wait_nodes
;
4453 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4454 if (submission
->wait_semaphores
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4455 pthread_mutex_lock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4456 if (submission
->wait_semaphores
[i
]->timeline
.highest_submitted
< submission
->wait_values
[i
]) {
4458 waiter
->value
= submission
->wait_values
[i
];
4459 waiter
->submission
= submission
;
4460 list_addtail(&waiter
->list
, &submission
->wait_semaphores
[i
]->timeline
.waiters
);
4463 pthread_mutex_unlock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4467 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4469 bool is_first
= list_is_empty(&submission
->queue
->pending_submissions
);
4470 list_addtail(&submission
->queue_pending_list
, &submission
->queue
->pending_submissions
);
4472 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4474 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4475 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4477 uint32_t decrement
= submission
->wait_semaphore_count
- wait_cnt
+ (is_first
? 1 : 0);
4478 if (__atomic_sub_fetch(&submission
->submission_wait_count
, decrement
, __ATOMIC_ACQ_REL
) == 0) {
4479 list_addtail(&submission
->processing_list
, processing_list
);
4484 radv_queue_submission_update_queue(struct radv_deferred_queue_submission
*submission
,
4485 struct list_head
*processing_list
)
4487 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4488 list_del(&submission
->queue_pending_list
);
4490 /* trigger the next submission in the queue. */
4491 if (!list_is_empty(&submission
->queue
->pending_submissions
)) {
4492 struct radv_deferred_queue_submission
*next_submission
=
4493 list_first_entry(&submission
->queue
->pending_submissions
,
4494 struct radv_deferred_queue_submission
,
4495 queue_pending_list
);
4496 if (p_atomic_dec_zero(&next_submission
->submission_wait_count
)) {
4497 list_addtail(&next_submission
->processing_list
, processing_list
);
4500 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4502 pthread_cond_broadcast(&submission
->queue
->device
->timeline_cond
);
4506 radv_queue_submit_deferred(struct radv_deferred_queue_submission
*submission
,
4507 struct list_head
*processing_list
)
4509 RADV_FROM_HANDLE(radv_fence
, fence
, submission
->fence
);
4510 struct radv_queue
*queue
= submission
->queue
;
4511 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
4512 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
4513 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
4514 bool do_flush
= submission
->flush_caches
|| submission
->wait_dst_stage_mask
;
4515 bool can_patch
= true;
4517 struct radv_winsys_sem_info sem_info
;
4520 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
;
4521 struct radeon_cmdbuf
*initial_flush_preamble_cs
= NULL
;
4522 struct radeon_cmdbuf
*continue_preamble_cs
= NULL
;
4524 result
= radv_get_preambles(queue
, submission
->cmd_buffers
,
4525 submission
->cmd_buffer_count
,
4526 &initial_preamble_cs
,
4527 &initial_flush_preamble_cs
,
4528 &continue_preamble_cs
);
4529 if (result
!= VK_SUCCESS
)
4532 result
= radv_alloc_sem_info(queue
->device
,
4534 submission
->wait_semaphore_count
,
4535 submission
->wait_semaphores
,
4536 submission
->wait_values
,
4537 submission
->signal_semaphore_count
,
4538 submission
->signal_semaphores
,
4539 submission
->signal_values
,
4541 if (result
!= VK_SUCCESS
)
4544 for (uint32_t i
= 0; i
< submission
->buffer_bind_count
; ++i
) {
4545 radv_sparse_buffer_bind_memory(queue
->device
,
4546 submission
->buffer_binds
+ i
);
4549 for (uint32_t i
= 0; i
< submission
->image_opaque_bind_count
; ++i
) {
4550 radv_sparse_image_opaque_bind_memory(queue
->device
,
4551 submission
->image_opaque_binds
+ i
);
4554 if (!submission
->cmd_buffer_count
) {
4555 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
4556 &queue
->device
->empty_cs
[queue
->queue_family_index
],
4561 radv_loge("failed to submit CS\n");
4567 struct radeon_cmdbuf
**cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
4568 (submission
->cmd_buffer_count
));
4570 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
++) {
4571 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, submission
->cmd_buffers
[j
]);
4572 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4574 cs_array
[j
] = cmd_buffer
->cs
;
4575 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
4578 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
4581 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
+= advance
) {
4582 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
4583 const struct radv_winsys_bo_list
*bo_list
= NULL
;
4585 advance
= MIN2(max_cs_submission
,
4586 submission
->cmd_buffer_count
- j
);
4588 if (queue
->device
->trace_bo
)
4589 *queue
->device
->trace_id_ptr
= 0;
4591 sem_info
.cs_emit_wait
= j
== 0;
4592 sem_info
.cs_emit_signal
= j
+ advance
== submission
->cmd_buffer_count
;
4594 if (unlikely(queue
->device
->use_global_bo_list
)) {
4595 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
4596 bo_list
= &queue
->device
->bo_list
.list
;
4599 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
4600 advance
, initial_preamble
, continue_preamble_cs
,
4602 can_patch
, base_fence
);
4604 if (unlikely(queue
->device
->use_global_bo_list
))
4605 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
4608 radv_loge("failed to submit CS\n");
4611 if (queue
->device
->trace_bo
) {
4612 radv_check_gpu_hangs(queue
, cs_array
[j
]);
4620 radv_free_temp_syncobjs(queue
->device
,
4621 submission
->temporary_semaphore_part_count
,
4622 submission
->temporary_semaphore_parts
);
4623 radv_finalize_timelines(queue
->device
,
4624 submission
->wait_semaphore_count
,
4625 submission
->wait_semaphores
,
4626 submission
->wait_values
,
4627 submission
->signal_semaphore_count
,
4628 submission
->signal_semaphores
,
4629 submission
->signal_values
,
4631 /* Has to happen after timeline finalization to make sure the
4632 * condition variable is only triggered when timelines and queue have
4634 radv_queue_submission_update_queue(submission
, processing_list
);
4635 radv_free_sem_info(&sem_info
);
4640 radv_free_temp_syncobjs(queue
->device
,
4641 submission
->temporary_semaphore_part_count
,
4642 submission
->temporary_semaphore_parts
);
4644 return VK_ERROR_DEVICE_LOST
;
4648 radv_process_submissions(struct list_head
*processing_list
)
4650 while(!list_is_empty(processing_list
)) {
4651 struct radv_deferred_queue_submission
*submission
=
4652 list_first_entry(processing_list
, struct radv_deferred_queue_submission
, processing_list
);
4653 list_del(&submission
->processing_list
);
4655 VkResult result
= radv_queue_submit_deferred(submission
, processing_list
);
4656 if (result
!= VK_SUCCESS
)
4662 static VkResult
radv_queue_submit(struct radv_queue
*queue
,
4663 const struct radv_queue_submission
*submission
)
4665 struct radv_deferred_queue_submission
*deferred
= NULL
;
4667 VkResult result
= radv_create_deferred_submission(queue
, submission
, &deferred
);
4668 if (result
!= VK_SUCCESS
)
4671 struct list_head processing_list
;
4672 list_inithead(&processing_list
);
4674 radv_queue_enqueue_submission(deferred
, &processing_list
);
4675 return radv_process_submissions(&processing_list
);
4678 /* Signals fence as soon as all the work currently put on queue is done. */
4679 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
4682 return radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4687 static bool radv_submit_has_effects(const VkSubmitInfo
*info
)
4689 return info
->commandBufferCount
||
4690 info
->waitSemaphoreCount
||
4691 info
->signalSemaphoreCount
;
4694 VkResult
radv_QueueSubmit(
4696 uint32_t submitCount
,
4697 const VkSubmitInfo
* pSubmits
,
4700 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4702 uint32_t fence_idx
= 0;
4703 bool flushed_caches
= false;
4705 if (fence
!= VK_NULL_HANDLE
) {
4706 for (uint32_t i
= 0; i
< submitCount
; ++i
)
4707 if (radv_submit_has_effects(pSubmits
+ i
))
4710 fence_idx
= UINT32_MAX
;
4712 for (uint32_t i
= 0; i
< submitCount
; i
++) {
4713 if (!radv_submit_has_effects(pSubmits
+ i
) && fence_idx
!= i
)
4716 VkPipelineStageFlags wait_dst_stage_mask
= 0;
4717 for (unsigned j
= 0; j
< pSubmits
[i
].waitSemaphoreCount
; ++j
) {
4718 wait_dst_stage_mask
|= pSubmits
[i
].pWaitDstStageMask
[j
];
4721 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
4722 vk_find_struct_const(pSubmits
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
4724 result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4725 .cmd_buffers
= pSubmits
[i
].pCommandBuffers
,
4726 .cmd_buffer_count
= pSubmits
[i
].commandBufferCount
,
4727 .wait_dst_stage_mask
= wait_dst_stage_mask
,
4728 .flush_caches
= !flushed_caches
,
4729 .wait_semaphores
= pSubmits
[i
].pWaitSemaphores
,
4730 .wait_semaphore_count
= pSubmits
[i
].waitSemaphoreCount
,
4731 .signal_semaphores
= pSubmits
[i
].pSignalSemaphores
,
4732 .signal_semaphore_count
= pSubmits
[i
].signalSemaphoreCount
,
4733 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
4734 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
4735 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
4736 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
4737 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
4739 if (result
!= VK_SUCCESS
)
4742 flushed_caches
= true;
4745 if (fence
!= VK_NULL_HANDLE
&& !submitCount
) {
4746 result
= radv_signal_fence(queue
, fence
);
4747 if (result
!= VK_SUCCESS
)
4754 VkResult
radv_QueueWaitIdle(
4757 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4759 pthread_mutex_lock(&queue
->pending_mutex
);
4760 while (!list_is_empty(&queue
->pending_submissions
)) {
4761 pthread_cond_wait(&queue
->device
->timeline_cond
, &queue
->pending_mutex
);
4763 pthread_mutex_unlock(&queue
->pending_mutex
);
4765 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
4766 radv_queue_family_to_ring(queue
->queue_family_index
),
4771 VkResult
radv_DeviceWaitIdle(
4774 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4776 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
4777 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
4778 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
4784 VkResult
radv_EnumerateInstanceExtensionProperties(
4785 const char* pLayerName
,
4786 uint32_t* pPropertyCount
,
4787 VkExtensionProperties
* pProperties
)
4789 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4791 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
4792 if (radv_supported_instance_extensions
.extensions
[i
]) {
4793 vk_outarray_append(&out
, prop
) {
4794 *prop
= radv_instance_extensions
[i
];
4799 return vk_outarray_status(&out
);
4802 VkResult
radv_EnumerateDeviceExtensionProperties(
4803 VkPhysicalDevice physicalDevice
,
4804 const char* pLayerName
,
4805 uint32_t* pPropertyCount
,
4806 VkExtensionProperties
* pProperties
)
4808 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
4809 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4811 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
4812 if (device
->supported_extensions
.extensions
[i
]) {
4813 vk_outarray_append(&out
, prop
) {
4814 *prop
= radv_device_extensions
[i
];
4819 return vk_outarray_status(&out
);
4822 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
4823 VkInstance _instance
,
4826 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4827 bool unchecked
= instance
? instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
: false;
4830 return radv_lookup_entrypoint_unchecked(pName
);
4832 return radv_lookup_entrypoint_checked(pName
,
4833 instance
? instance
->apiVersion
: 0,
4834 instance
? &instance
->enabled_extensions
: NULL
,
4839 /* The loader wants us to expose a second GetInstanceProcAddr function
4840 * to work around certain LD_PRELOAD issues seen in apps.
4843 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
4844 VkInstance instance
,
4848 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
4849 VkInstance instance
,
4852 return radv_GetInstanceProcAddr(instance
, pName
);
4856 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
4857 VkInstance _instance
,
4861 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
4862 VkInstance _instance
,
4865 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4867 return radv_lookup_physical_device_entrypoint_checked(pName
,
4868 instance
? instance
->apiVersion
: 0,
4869 instance
? &instance
->enabled_extensions
: NULL
);
4872 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
4876 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4877 bool unchecked
= device
? device
->instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
: false;
4880 return radv_lookup_entrypoint_unchecked(pName
);
4882 return radv_lookup_entrypoint_checked(pName
,
4883 device
->instance
->apiVersion
,
4884 &device
->instance
->enabled_extensions
,
4885 &device
->enabled_extensions
);
4889 bool radv_get_memory_fd(struct radv_device
*device
,
4890 struct radv_device_memory
*memory
,
4893 struct radeon_bo_metadata metadata
;
4895 if (memory
->image
) {
4896 radv_init_metadata(device
, memory
->image
, &metadata
);
4897 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
4900 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
4905 static void radv_free_memory(struct radv_device
*device
,
4906 const VkAllocationCallbacks
* pAllocator
,
4907 struct radv_device_memory
*mem
)
4912 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4913 if (mem
->android_hardware_buffer
)
4914 AHardwareBuffer_release(mem
->android_hardware_buffer
);
4918 radv_bo_list_remove(device
, mem
->bo
);
4919 device
->ws
->buffer_destroy(mem
->bo
);
4923 vk_free2(&device
->alloc
, pAllocator
, mem
);
4926 static VkResult
radv_alloc_memory(struct radv_device
*device
,
4927 const VkMemoryAllocateInfo
* pAllocateInfo
,
4928 const VkAllocationCallbacks
* pAllocator
,
4929 VkDeviceMemory
* pMem
)
4931 struct radv_device_memory
*mem
;
4933 enum radeon_bo_domain domain
;
4935 enum radv_mem_type mem_type_index
= device
->physical_device
->mem_type_indices
[pAllocateInfo
->memoryTypeIndex
];
4937 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
4939 const VkImportMemoryFdInfoKHR
*import_info
=
4940 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
4941 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
4942 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
4943 const VkExportMemoryAllocateInfo
*export_info
=
4944 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
4945 const struct VkImportAndroidHardwareBufferInfoANDROID
*ahb_import_info
=
4946 vk_find_struct_const(pAllocateInfo
->pNext
,
4947 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID
);
4948 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
4949 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
4951 const struct wsi_memory_allocate_info
*wsi_info
=
4952 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
4954 if (pAllocateInfo
->allocationSize
== 0 && !ahb_import_info
&&
4955 !(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
))) {
4956 /* Apparently, this is allowed */
4957 *pMem
= VK_NULL_HANDLE
;
4961 mem
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
4962 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4964 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4966 if (wsi_info
&& wsi_info
->implicit_sync
)
4967 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
4969 if (dedicate_info
) {
4970 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
4971 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
4977 float priority_float
= 0.5;
4978 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
4979 vk_find_struct_const(pAllocateInfo
->pNext
,
4980 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
4982 priority_float
= priority_ext
->priority
;
4984 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
4985 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
4987 mem
->user_ptr
= NULL
;
4990 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4991 mem
->android_hardware_buffer
= NULL
;
4994 if (ahb_import_info
) {
4995 result
= radv_import_ahb_memory(device
, mem
, priority
, ahb_import_info
);
4996 if (result
!= VK_SUCCESS
)
4998 } else if(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
)) {
4999 result
= radv_create_ahb_memory(device
, mem
, priority
, pAllocateInfo
);
5000 if (result
!= VK_SUCCESS
)
5002 } else if (import_info
) {
5003 assert(import_info
->handleType
==
5004 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
5005 import_info
->handleType
==
5006 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
5007 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
5010 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
5013 close(import_info
->fd
);
5015 } else if (host_ptr_info
) {
5016 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
5017 assert(radv_is_mem_type_gtt_cached(mem_type_index
));
5018 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
5019 pAllocateInfo
->allocationSize
,
5022 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
5025 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
5028 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
5029 if (radv_is_mem_type_gtt_wc(mem_type_index
) ||
5030 radv_is_mem_type_gtt_cached(mem_type_index
))
5031 domain
= RADEON_DOMAIN_GTT
;
5033 domain
= RADEON_DOMAIN_VRAM
;
5035 if (radv_is_mem_type_vram(mem_type_index
))
5036 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
5038 flags
|= RADEON_FLAG_CPU_ACCESS
;
5040 if (radv_is_mem_type_gtt_wc(mem_type_index
))
5041 flags
|= RADEON_FLAG_GTT_WC
;
5043 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
5044 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
5045 if (device
->use_global_bo_list
) {
5046 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
5050 if (radv_is_mem_type_uncached(mem_type_index
)) {
5051 assert(device
->physical_device
->rad_info
.has_l2_uncached
);
5052 flags
|= RADEON_FLAG_VA_UNCACHED
;
5055 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
5056 domain
, flags
, priority
);
5059 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
5062 mem
->type_index
= mem_type_index
;
5065 result
= radv_bo_list_add(device
, mem
->bo
);
5066 if (result
!= VK_SUCCESS
)
5069 *pMem
= radv_device_memory_to_handle(mem
);
5074 radv_free_memory(device
, pAllocator
,mem
);
5079 VkResult
radv_AllocateMemory(
5081 const VkMemoryAllocateInfo
* pAllocateInfo
,
5082 const VkAllocationCallbacks
* pAllocator
,
5083 VkDeviceMemory
* pMem
)
5085 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5086 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
5089 void radv_FreeMemory(
5091 VkDeviceMemory _mem
,
5092 const VkAllocationCallbacks
* pAllocator
)
5094 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5095 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
5097 radv_free_memory(device
, pAllocator
, mem
);
5100 VkResult
radv_MapMemory(
5102 VkDeviceMemory _memory
,
5103 VkDeviceSize offset
,
5105 VkMemoryMapFlags flags
,
5108 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5109 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
5117 *ppData
= mem
->user_ptr
;
5119 *ppData
= device
->ws
->buffer_map(mem
->bo
);
5126 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
5129 void radv_UnmapMemory(
5131 VkDeviceMemory _memory
)
5133 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5134 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
5139 if (mem
->user_ptr
== NULL
)
5140 device
->ws
->buffer_unmap(mem
->bo
);
5143 VkResult
radv_FlushMappedMemoryRanges(
5145 uint32_t memoryRangeCount
,
5146 const VkMappedMemoryRange
* pMemoryRanges
)
5151 VkResult
radv_InvalidateMappedMemoryRanges(
5153 uint32_t memoryRangeCount
,
5154 const VkMappedMemoryRange
* pMemoryRanges
)
5159 void radv_GetBufferMemoryRequirements(
5162 VkMemoryRequirements
* pMemoryRequirements
)
5164 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5165 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5167 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5169 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
5170 pMemoryRequirements
->alignment
= 4096;
5172 pMemoryRequirements
->alignment
= 16;
5174 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
5177 void radv_GetBufferMemoryRequirements2(
5179 const VkBufferMemoryRequirementsInfo2
*pInfo
,
5180 VkMemoryRequirements2
*pMemoryRequirements
)
5182 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
5183 &pMemoryRequirements
->memoryRequirements
);
5184 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
5185 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5186 switch (ext
->sType
) {
5187 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5188 VkMemoryDedicatedRequirements
*req
=
5189 (VkMemoryDedicatedRequirements
*) ext
;
5190 req
->requiresDedicatedAllocation
= buffer
->shareable
;
5191 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5200 void radv_GetImageMemoryRequirements(
5203 VkMemoryRequirements
* pMemoryRequirements
)
5205 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5206 RADV_FROM_HANDLE(radv_image
, image
, _image
);
5208 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5210 pMemoryRequirements
->size
= image
->size
;
5211 pMemoryRequirements
->alignment
= image
->alignment
;
5214 void radv_GetImageMemoryRequirements2(
5216 const VkImageMemoryRequirementsInfo2
*pInfo
,
5217 VkMemoryRequirements2
*pMemoryRequirements
)
5219 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
5220 &pMemoryRequirements
->memoryRequirements
);
5222 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
5224 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5225 switch (ext
->sType
) {
5226 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5227 VkMemoryDedicatedRequirements
*req
=
5228 (VkMemoryDedicatedRequirements
*) ext
;
5229 req
->requiresDedicatedAllocation
= image
->shareable
;
5230 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5239 void radv_GetImageSparseMemoryRequirements(
5242 uint32_t* pSparseMemoryRequirementCount
,
5243 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
5248 void radv_GetImageSparseMemoryRequirements2(
5250 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
5251 uint32_t* pSparseMemoryRequirementCount
,
5252 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
5257 void radv_GetDeviceMemoryCommitment(
5259 VkDeviceMemory memory
,
5260 VkDeviceSize
* pCommittedMemoryInBytes
)
5262 *pCommittedMemoryInBytes
= 0;
5265 VkResult
radv_BindBufferMemory2(VkDevice device
,
5266 uint32_t bindInfoCount
,
5267 const VkBindBufferMemoryInfo
*pBindInfos
)
5269 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5270 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5271 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
5274 buffer
->bo
= mem
->bo
;
5275 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
5283 VkResult
radv_BindBufferMemory(
5286 VkDeviceMemory memory
,
5287 VkDeviceSize memoryOffset
)
5289 const VkBindBufferMemoryInfo info
= {
5290 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5293 .memoryOffset
= memoryOffset
5296 return radv_BindBufferMemory2(device
, 1, &info
);
5299 VkResult
radv_BindImageMemory2(VkDevice device
,
5300 uint32_t bindInfoCount
,
5301 const VkBindImageMemoryInfo
*pBindInfos
)
5303 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5304 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5305 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
5308 image
->bo
= mem
->bo
;
5309 image
->offset
= pBindInfos
[i
].memoryOffset
;
5319 VkResult
radv_BindImageMemory(
5322 VkDeviceMemory memory
,
5323 VkDeviceSize memoryOffset
)
5325 const VkBindImageMemoryInfo info
= {
5326 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5329 .memoryOffset
= memoryOffset
5332 return radv_BindImageMemory2(device
, 1, &info
);
5335 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo
*info
)
5337 return info
->bufferBindCount
||
5338 info
->imageOpaqueBindCount
||
5339 info
->imageBindCount
||
5340 info
->waitSemaphoreCount
||
5341 info
->signalSemaphoreCount
;
5344 VkResult
radv_QueueBindSparse(
5346 uint32_t bindInfoCount
,
5347 const VkBindSparseInfo
* pBindInfo
,
5350 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
5352 uint32_t fence_idx
= 0;
5354 if (fence
!= VK_NULL_HANDLE
) {
5355 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
)
5356 if (radv_sparse_bind_has_effects(pBindInfo
+ i
))
5359 fence_idx
= UINT32_MAX
;
5361 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5362 if (i
!= fence_idx
&& !radv_sparse_bind_has_effects(pBindInfo
+ i
))
5365 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
5366 vk_find_struct_const(pBindInfo
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
5368 VkResult result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
5369 .buffer_binds
= pBindInfo
[i
].pBufferBinds
,
5370 .buffer_bind_count
= pBindInfo
[i
].bufferBindCount
,
5371 .image_opaque_binds
= pBindInfo
[i
].pImageOpaqueBinds
,
5372 .image_opaque_bind_count
= pBindInfo
[i
].imageOpaqueBindCount
,
5373 .wait_semaphores
= pBindInfo
[i
].pWaitSemaphores
,
5374 .wait_semaphore_count
= pBindInfo
[i
].waitSemaphoreCount
,
5375 .signal_semaphores
= pBindInfo
[i
].pSignalSemaphores
,
5376 .signal_semaphore_count
= pBindInfo
[i
].signalSemaphoreCount
,
5377 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
5378 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
5379 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
5380 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
5381 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
5384 if (result
!= VK_SUCCESS
)
5388 if (fence
!= VK_NULL_HANDLE
&& !bindInfoCount
) {
5389 result
= radv_signal_fence(queue
, fence
);
5390 if (result
!= VK_SUCCESS
)
5397 VkResult
radv_CreateFence(
5399 const VkFenceCreateInfo
* pCreateInfo
,
5400 const VkAllocationCallbacks
* pAllocator
,
5403 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5404 const VkExportFenceCreateInfo
*export
=
5405 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
5406 VkExternalFenceHandleTypeFlags handleTypes
=
5407 export
? export
->handleTypes
: 0;
5409 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
5411 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5414 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5416 fence
->fence_wsi
= NULL
;
5417 fence
->temp_syncobj
= 0;
5418 if (device
->always_use_syncobj
|| handleTypes
) {
5419 int ret
= device
->ws
->create_syncobj(device
->ws
, &fence
->syncobj
);
5421 vk_free2(&device
->alloc
, pAllocator
, fence
);
5422 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5424 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
) {
5425 device
->ws
->signal_syncobj(device
->ws
, fence
->syncobj
);
5427 fence
->fence
= NULL
;
5429 fence
->fence
= device
->ws
->create_fence();
5430 if (!fence
->fence
) {
5431 vk_free2(&device
->alloc
, pAllocator
, fence
);
5432 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5435 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
5436 device
->ws
->signal_fence(fence
->fence
);
5439 *pFence
= radv_fence_to_handle(fence
);
5444 void radv_DestroyFence(
5447 const VkAllocationCallbacks
* pAllocator
)
5449 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5450 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5455 if (fence
->temp_syncobj
)
5456 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
5458 device
->ws
->destroy_syncobj(device
->ws
, fence
->syncobj
);
5460 device
->ws
->destroy_fence(fence
->fence
);
5461 if (fence
->fence_wsi
)
5462 fence
->fence_wsi
->destroy(fence
->fence_wsi
);
5463 vk_free2(&device
->alloc
, pAllocator
, fence
);
5467 uint64_t radv_get_current_time(void)
5470 clock_gettime(CLOCK_MONOTONIC
, &tv
);
5471 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
5474 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
5476 uint64_t current_time
= radv_get_current_time();
5478 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
5480 return current_time
+ timeout
;
5484 static bool radv_all_fences_plain_and_submitted(struct radv_device
*device
,
5485 uint32_t fenceCount
, const VkFence
*pFences
)
5487 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5488 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5489 if (fence
->fence
== NULL
|| fence
->syncobj
||
5490 fence
->temp_syncobj
|| fence
->fence_wsi
||
5491 (!device
->ws
->is_fence_waitable(fence
->fence
)))
5497 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
5499 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5500 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5501 if (fence
->syncobj
== 0 && fence
->temp_syncobj
== 0)
5507 VkResult
radv_WaitForFences(
5509 uint32_t fenceCount
,
5510 const VkFence
* pFences
,
5514 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5515 timeout
= radv_get_absolute_timeout(timeout
);
5517 if (device
->always_use_syncobj
&&
5518 radv_all_fences_syncobj(fenceCount
, pFences
))
5520 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
5522 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5524 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5525 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5526 handles
[i
] = fence
->temp_syncobj
? fence
->temp_syncobj
: fence
->syncobj
;
5529 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
5532 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5535 if (!waitAll
&& fenceCount
> 1) {
5536 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5537 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(device
, fenceCount
, pFences
)) {
5538 uint32_t wait_count
= 0;
5539 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
5541 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5543 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5544 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5546 if (device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0)) {
5551 fences
[wait_count
++] = fence
->fence
;
5554 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
5555 waitAll
, timeout
- radv_get_current_time());
5558 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5561 while(radv_get_current_time() <= timeout
) {
5562 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5563 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
5570 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5571 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5572 bool expired
= false;
5574 if (fence
->temp_syncobj
) {
5575 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, timeout
))
5580 if (fence
->syncobj
) {
5581 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, timeout
))
5587 if (!device
->ws
->is_fence_waitable(fence
->fence
)) {
5588 while(!device
->ws
->is_fence_waitable(fence
->fence
) &&
5589 radv_get_current_time() <= timeout
)
5593 expired
= device
->ws
->fence_wait(device
->ws
,
5600 if (fence
->fence_wsi
) {
5601 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, timeout
);
5602 if (result
!= VK_SUCCESS
)
5610 VkResult
radv_ResetFences(VkDevice _device
,
5611 uint32_t fenceCount
,
5612 const VkFence
*pFences
)
5614 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5616 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
5617 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5619 device
->ws
->reset_fence(fence
->fence
);
5621 /* Per spec, we first restore the permanent payload, and then reset, so
5622 * having a temp syncobj should not skip resetting the permanent syncobj. */
5623 if (fence
->temp_syncobj
) {
5624 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
5625 fence
->temp_syncobj
= 0;
5628 if (fence
->syncobj
) {
5629 device
->ws
->reset_syncobj(device
->ws
, fence
->syncobj
);
5636 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
5638 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5639 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5641 if (fence
->temp_syncobj
) {
5642 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, 0);
5643 return success
? VK_SUCCESS
: VK_NOT_READY
;
5646 if (fence
->syncobj
) {
5647 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, 0);
5648 return success
? VK_SUCCESS
: VK_NOT_READY
;
5652 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
5653 return VK_NOT_READY
;
5655 if (fence
->fence_wsi
) {
5656 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, 0);
5658 if (result
!= VK_SUCCESS
) {
5659 if (result
== VK_TIMEOUT
)
5660 return VK_NOT_READY
;
5668 // Queue semaphore functions
5671 radv_create_timeline(struct radv_timeline
*timeline
, uint64_t value
)
5673 timeline
->highest_signaled
= value
;
5674 timeline
->highest_submitted
= value
;
5675 list_inithead(&timeline
->points
);
5676 list_inithead(&timeline
->free_points
);
5677 list_inithead(&timeline
->waiters
);
5678 pthread_mutex_init(&timeline
->mutex
, NULL
);
5682 radv_destroy_timeline(struct radv_device
*device
,
5683 struct radv_timeline
*timeline
)
5685 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5686 &timeline
->free_points
, list
) {
5687 list_del(&point
->list
);
5688 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5691 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5692 &timeline
->points
, list
) {
5693 list_del(&point
->list
);
5694 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5697 pthread_mutex_destroy(&timeline
->mutex
);
5701 radv_timeline_gc_locked(struct radv_device
*device
,
5702 struct radv_timeline
*timeline
)
5704 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5705 &timeline
->points
, list
) {
5706 if (point
->wait_count
|| point
->value
> timeline
->highest_submitted
)
5709 if (device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, 0)) {
5710 timeline
->highest_signaled
= point
->value
;
5711 list_del(&point
->list
);
5712 list_add(&point
->list
, &timeline
->free_points
);
5717 static struct radv_timeline_point
*
5718 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
5719 struct radv_timeline
*timeline
,
5722 radv_timeline_gc_locked(device
, timeline
);
5724 if (p
<= timeline
->highest_signaled
)
5727 list_for_each_entry(struct radv_timeline_point
, point
,
5728 &timeline
->points
, list
) {
5729 if (point
->value
>= p
) {
5730 ++point
->wait_count
;
5737 static struct radv_timeline_point
*
5738 radv_timeline_add_point_locked(struct radv_device
*device
,
5739 struct radv_timeline
*timeline
,
5742 radv_timeline_gc_locked(device
, timeline
);
5744 struct radv_timeline_point
*ret
= NULL
;
5745 struct radv_timeline_point
*prev
= NULL
;
5747 if (p
<= timeline
->highest_signaled
)
5750 list_for_each_entry(struct radv_timeline_point
, point
,
5751 &timeline
->points
, list
) {
5752 if (point
->value
== p
) {
5756 if (point
->value
< p
)
5760 if (list_is_empty(&timeline
->free_points
)) {
5761 ret
= malloc(sizeof(struct radv_timeline_point
));
5762 device
->ws
->create_syncobj(device
->ws
, &ret
->syncobj
);
5764 ret
= list_first_entry(&timeline
->free_points
, struct radv_timeline_point
, list
);
5765 list_del(&ret
->list
);
5767 device
->ws
->reset_syncobj(device
->ws
, ret
->syncobj
);
5771 ret
->wait_count
= 1;
5774 list_add(&ret
->list
, &prev
->list
);
5776 list_addtail(&ret
->list
, &timeline
->points
);
5783 radv_timeline_wait_locked(struct radv_device
*device
,
5784 struct radv_timeline
*timeline
,
5786 uint64_t abs_timeout
)
5788 while(timeline
->highest_submitted
< value
) {
5789 struct timespec abstime
;
5790 timespec_from_nsec(&abstime
, abs_timeout
);
5792 pthread_cond_timedwait(&device
->timeline_cond
, &timeline
->mutex
, &abstime
);
5794 if (radv_get_current_time() >= abs_timeout
&& timeline
->highest_submitted
< value
)
5798 struct radv_timeline_point
*point
= radv_timeline_find_point_at_least_locked(device
, timeline
, value
);
5802 pthread_mutex_unlock(&timeline
->mutex
);
5804 bool success
= device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, abs_timeout
);
5806 pthread_mutex_lock(&timeline
->mutex
);
5807 point
->wait_count
--;
5808 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5812 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
5813 struct list_head
*processing_list
)
5815 list_for_each_entry_safe(struct radv_timeline_waiter
, waiter
,
5816 &timeline
->waiters
, list
) {
5817 if (waiter
->value
> timeline
->highest_submitted
)
5820 if (p_atomic_dec_zero(&waiter
->submission
->submission_wait_count
)) {
5821 list_addtail(&waiter
->submission
->processing_list
, processing_list
);
5823 list_del(&waiter
->list
);
5828 void radv_destroy_semaphore_part(struct radv_device
*device
,
5829 struct radv_semaphore_part
*part
)
5831 switch(part
->kind
) {
5832 case RADV_SEMAPHORE_NONE
:
5834 case RADV_SEMAPHORE_WINSYS
:
5835 device
->ws
->destroy_sem(part
->ws_sem
);
5837 case RADV_SEMAPHORE_TIMELINE
:
5838 radv_destroy_timeline(device
, &part
->timeline
);
5840 case RADV_SEMAPHORE_SYNCOBJ
:
5841 device
->ws
->destroy_syncobj(device
->ws
, part
->syncobj
);
5844 part
->kind
= RADV_SEMAPHORE_NONE
;
5847 static VkSemaphoreTypeKHR
5848 radv_get_semaphore_type(const void *pNext
, uint64_t *initial_value
)
5850 const VkSemaphoreTypeCreateInfo
*type_info
=
5851 vk_find_struct_const(pNext
, SEMAPHORE_TYPE_CREATE_INFO
);
5854 return VK_SEMAPHORE_TYPE_BINARY
;
5857 *initial_value
= type_info
->initialValue
;
5858 return type_info
->semaphoreType
;
5861 VkResult
radv_CreateSemaphore(
5863 const VkSemaphoreCreateInfo
* pCreateInfo
,
5864 const VkAllocationCallbacks
* pAllocator
,
5865 VkSemaphore
* pSemaphore
)
5867 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5868 const VkExportSemaphoreCreateInfo
*export
=
5869 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
5870 VkExternalSemaphoreHandleTypeFlags handleTypes
=
5871 export
? export
->handleTypes
: 0;
5872 uint64_t initial_value
= 0;
5873 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pCreateInfo
->pNext
, &initial_value
);
5875 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
5877 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5879 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5881 sem
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
5882 sem
->permanent
.kind
= RADV_SEMAPHORE_NONE
;
5884 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
5885 radv_create_timeline(&sem
->permanent
.timeline
, initial_value
);
5886 sem
->permanent
.kind
= RADV_SEMAPHORE_TIMELINE
;
5887 } else if (device
->always_use_syncobj
|| handleTypes
) {
5888 assert (device
->physical_device
->rad_info
.has_syncobj
);
5889 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->permanent
.syncobj
);
5891 vk_free2(&device
->alloc
, pAllocator
, sem
);
5892 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5894 sem
->permanent
.kind
= RADV_SEMAPHORE_SYNCOBJ
;
5896 sem
->permanent
.ws_sem
= device
->ws
->create_sem(device
->ws
);
5897 if (!sem
->permanent
.ws_sem
) {
5898 vk_free2(&device
->alloc
, pAllocator
, sem
);
5899 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5901 sem
->permanent
.kind
= RADV_SEMAPHORE_WINSYS
;
5904 *pSemaphore
= radv_semaphore_to_handle(sem
);
5908 void radv_DestroySemaphore(
5910 VkSemaphore _semaphore
,
5911 const VkAllocationCallbacks
* pAllocator
)
5913 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5914 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
5918 radv_destroy_semaphore_part(device
, &sem
->temporary
);
5919 radv_destroy_semaphore_part(device
, &sem
->permanent
);
5920 vk_free2(&device
->alloc
, pAllocator
, sem
);
5924 radv_GetSemaphoreCounterValue(VkDevice _device
,
5925 VkSemaphore _semaphore
,
5928 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5929 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, _semaphore
);
5931 struct radv_semaphore_part
*part
=
5932 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
5934 switch (part
->kind
) {
5935 case RADV_SEMAPHORE_TIMELINE
: {
5936 pthread_mutex_lock(&part
->timeline
.mutex
);
5937 radv_timeline_gc_locked(device
, &part
->timeline
);
5938 *pValue
= part
->timeline
.highest_signaled
;
5939 pthread_mutex_unlock(&part
->timeline
.mutex
);
5942 case RADV_SEMAPHORE_NONE
:
5943 case RADV_SEMAPHORE_SYNCOBJ
:
5944 case RADV_SEMAPHORE_WINSYS
:
5945 unreachable("Invalid semaphore type");
5947 unreachable("Unhandled semaphore type");
5952 radv_wait_timelines(struct radv_device
*device
,
5953 const VkSemaphoreWaitInfo
* pWaitInfo
,
5954 uint64_t abs_timeout
)
5956 if ((pWaitInfo
->flags
& VK_SEMAPHORE_WAIT_ANY_BIT_KHR
) && pWaitInfo
->semaphoreCount
> 1) {
5958 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
5959 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
5960 pthread_mutex_lock(&semaphore
->permanent
.timeline
.mutex
);
5961 VkResult result
= radv_timeline_wait_locked(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], 0);
5962 pthread_mutex_unlock(&semaphore
->permanent
.timeline
.mutex
);
5964 if (result
== VK_SUCCESS
)
5967 if (radv_get_current_time() > abs_timeout
)
5972 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
5973 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
5974 pthread_mutex_lock(&semaphore
->permanent
.timeline
.mutex
);
5975 VkResult result
= radv_timeline_wait_locked(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], abs_timeout
);
5976 pthread_mutex_unlock(&semaphore
->permanent
.timeline
.mutex
);
5978 if (result
!= VK_SUCCESS
)
5984 radv_WaitSemaphores(VkDevice _device
,
5985 const VkSemaphoreWaitInfo
* pWaitInfo
,
5988 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5989 uint64_t abs_timeout
= radv_get_absolute_timeout(timeout
);
5990 return radv_wait_timelines(device
, pWaitInfo
, abs_timeout
);
5994 radv_SignalSemaphore(VkDevice _device
,
5995 const VkSemaphoreSignalInfo
* pSignalInfo
)
5997 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5998 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pSignalInfo
->semaphore
);
6000 struct radv_semaphore_part
*part
=
6001 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
6003 switch(part
->kind
) {
6004 case RADV_SEMAPHORE_TIMELINE
: {
6005 pthread_mutex_lock(&part
->timeline
.mutex
);
6006 radv_timeline_gc_locked(device
, &part
->timeline
);
6007 part
->timeline
.highest_submitted
= MAX2(part
->timeline
.highest_submitted
, pSignalInfo
->value
);
6008 part
->timeline
.highest_signaled
= MAX2(part
->timeline
.highest_signaled
, pSignalInfo
->value
);
6010 struct list_head processing_list
;
6011 list_inithead(&processing_list
);
6012 radv_timeline_trigger_waiters_locked(&part
->timeline
, &processing_list
);
6013 pthread_mutex_unlock(&part
->timeline
.mutex
);
6015 return radv_process_submissions(&processing_list
);
6017 case RADV_SEMAPHORE_NONE
:
6018 case RADV_SEMAPHORE_SYNCOBJ
:
6019 case RADV_SEMAPHORE_WINSYS
:
6020 unreachable("Invalid semaphore type");
6027 VkResult
radv_CreateEvent(
6029 const VkEventCreateInfo
* pCreateInfo
,
6030 const VkAllocationCallbacks
* pAllocator
,
6033 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6034 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
6036 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6039 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6041 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
6043 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
6044 RADV_BO_PRIORITY_FENCE
);
6046 vk_free2(&device
->alloc
, pAllocator
, event
);
6047 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6050 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
6052 *pEvent
= radv_event_to_handle(event
);
6057 void radv_DestroyEvent(
6060 const VkAllocationCallbacks
* pAllocator
)
6062 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6063 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6067 device
->ws
->buffer_destroy(event
->bo
);
6068 vk_free2(&device
->alloc
, pAllocator
, event
);
6071 VkResult
radv_GetEventStatus(
6075 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6077 if (*event
->map
== 1)
6078 return VK_EVENT_SET
;
6079 return VK_EVENT_RESET
;
6082 VkResult
radv_SetEvent(
6086 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6092 VkResult
radv_ResetEvent(
6096 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6102 VkResult
radv_CreateBuffer(
6104 const VkBufferCreateInfo
* pCreateInfo
,
6105 const VkAllocationCallbacks
* pAllocator
,
6108 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6109 struct radv_buffer
*buffer
;
6111 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
6113 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
6114 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6116 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6118 buffer
->size
= pCreateInfo
->size
;
6119 buffer
->usage
= pCreateInfo
->usage
;
6122 buffer
->flags
= pCreateInfo
->flags
;
6124 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
6125 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
6127 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
6128 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
6129 align64(buffer
->size
, 4096),
6130 4096, 0, RADEON_FLAG_VIRTUAL
,
6131 RADV_BO_PRIORITY_VIRTUAL
);
6133 vk_free2(&device
->alloc
, pAllocator
, buffer
);
6134 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6138 *pBuffer
= radv_buffer_to_handle(buffer
);
6143 void radv_DestroyBuffer(
6146 const VkAllocationCallbacks
* pAllocator
)
6148 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6149 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
6154 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
6155 device
->ws
->buffer_destroy(buffer
->bo
);
6157 vk_free2(&device
->alloc
, pAllocator
, buffer
);
6160 VkDeviceAddress
radv_GetBufferDeviceAddress(
6162 const VkBufferDeviceAddressInfo
* pInfo
)
6164 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
6165 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
6169 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device
,
6170 const VkBufferDeviceAddressInfo
* pInfo
)
6175 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device
,
6176 const VkDeviceMemoryOpaqueCaptureAddressInfo
* pInfo
)
6181 static inline unsigned
6182 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
6185 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
6187 return plane
->surface
.u
.legacy
.tiling_index
[level
];
6190 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
6192 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
6196 radv_init_dcc_control_reg(struct radv_device
*device
,
6197 struct radv_image_view
*iview
)
6199 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
6200 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
6201 unsigned max_compressed_block_size
;
6202 unsigned independent_128b_blocks
;
6203 unsigned independent_64b_blocks
;
6205 if (!radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6208 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
6209 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6210 * dGPU and 64 for APU because all of our APUs to date use
6211 * DIMMs which have a request granularity size of 64B while all
6212 * other chips have a 32B request size.
6214 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
6217 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6218 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6219 independent_64b_blocks
= 0;
6220 independent_128b_blocks
= 1;
6222 independent_128b_blocks
= 0;
6224 if (iview
->image
->info
.samples
> 1) {
6225 if (iview
->image
->planes
[0].surface
.bpe
== 1)
6226 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6227 else if (iview
->image
->planes
[0].surface
.bpe
== 2)
6228 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6231 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
6232 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
6233 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
6234 /* If this DCC image is potentially going to be used in texture
6235 * fetches, we need some special settings.
6237 independent_64b_blocks
= 1;
6238 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6240 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6241 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6242 * big as possible for better compression state.
6244 independent_64b_blocks
= 0;
6245 max_compressed_block_size
= max_uncompressed_block_size
;
6249 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
6250 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
6251 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
6252 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
) |
6253 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks
);
6257 radv_initialise_color_surface(struct radv_device
*device
,
6258 struct radv_color_buffer_info
*cb
,
6259 struct radv_image_view
*iview
)
6261 const struct vk_format_description
*desc
;
6262 unsigned ntype
, format
, swap
, endian
;
6263 unsigned blend_clamp
= 0, blend_bypass
= 0;
6265 const struct radv_image_plane
*plane
= &iview
->image
->planes
[iview
->plane_id
];
6266 const struct radeon_surf
*surf
= &plane
->surface
;
6268 desc
= vk_format_description(iview
->vk_format
);
6270 memset(cb
, 0, sizeof(*cb
));
6272 /* Intensity is implemented as Red, so treat it that way. */
6273 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
6275 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ plane
->offset
;
6277 cb
->cb_color_base
= va
>> 8;
6279 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6280 struct gfx9_surf_meta_flags meta
;
6281 if (iview
->image
->dcc_offset
)
6282 meta
= surf
->u
.gfx9
.dcc
;
6284 meta
= surf
->u
.gfx9
.cmask
;
6286 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6287 cb
->cb_color_attrib3
|= S_028EE0_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6288 S_028EE0_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6289 S_028EE0_CMASK_PIPE_ALIGNED(surf
->u
.gfx9
.cmask
.pipe_aligned
) |
6290 S_028EE0_DCC_PIPE_ALIGNED(surf
->u
.gfx9
.dcc
.pipe_aligned
);
6292 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6293 S_028C74_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6294 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
6295 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
6296 cb
->cb_mrt_epitch
= S_0287A0_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6299 cb
->cb_color_base
+= surf
->u
.gfx9
.surf_offset
>> 8;
6300 cb
->cb_color_base
|= surf
->tile_swizzle
;
6302 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
6303 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
6305 cb
->cb_color_base
+= level_info
->offset
>> 8;
6306 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
6307 cb
->cb_color_base
|= surf
->tile_swizzle
;
6309 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
6310 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
6311 tile_mode_index
= si_tile_mode_index(plane
, iview
->base_mip
, false);
6313 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
6314 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
6315 cb
->cb_color_cmask_slice
= surf
->u
.legacy
.cmask_slice_tile_max
;
6317 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
6319 if (radv_image_has_fmask(iview
->image
)) {
6320 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6321 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(surf
->u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
6322 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(surf
->u
.legacy
.fmask
.tiling_index
);
6323 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(surf
->u
.legacy
.fmask
.slice_tile_max
);
6325 /* This must be set for fast clear to work without FMASK. */
6326 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6327 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
6328 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
6329 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
6333 /* CMASK variables */
6334 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6335 va
+= iview
->image
->cmask_offset
;
6336 cb
->cb_color_cmask
= va
>> 8;
6338 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6339 va
+= iview
->image
->dcc_offset
;
6341 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
) &&
6342 device
->physical_device
->rad_info
.chip_class
<= GFX8
)
6343 va
+= plane
->surface
.u
.legacy
.level
[iview
->base_mip
].dcc_offset
;
6345 unsigned dcc_tile_swizzle
= surf
->tile_swizzle
;
6346 dcc_tile_swizzle
&= (surf
->dcc_alignment
- 1) >> 8;
6348 cb
->cb_dcc_base
= va
>> 8;
6349 cb
->cb_dcc_base
|= dcc_tile_swizzle
;
6351 /* GFX10 field has the same base shift as the GFX6 field. */
6352 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6353 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
6354 S_028C6C_SLICE_MAX_GFX10(max_slice
);
6356 if (iview
->image
->info
.samples
> 1) {
6357 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
6359 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
6360 S_028C74_NUM_FRAGMENTS(log_samples
);
6363 if (radv_image_has_fmask(iview
->image
)) {
6364 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask_offset
;
6365 cb
->cb_color_fmask
= va
>> 8;
6366 cb
->cb_color_fmask
|= surf
->fmask_tile_swizzle
;
6368 cb
->cb_color_fmask
= cb
->cb_color_base
;
6371 ntype
= radv_translate_color_numformat(iview
->vk_format
,
6373 vk_format_get_first_non_void_channel(iview
->vk_format
));
6374 format
= radv_translate_colorformat(iview
->vk_format
);
6375 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
6376 radv_finishme("Illegal color\n");
6377 swap
= radv_translate_colorswap(iview
->vk_format
, false);
6378 endian
= radv_colorformat_endian_swap(format
);
6380 /* blend clamp should be set for all NORM/SRGB types */
6381 if (ntype
== V_028C70_NUMBER_UNORM
||
6382 ntype
== V_028C70_NUMBER_SNORM
||
6383 ntype
== V_028C70_NUMBER_SRGB
)
6386 /* set blend bypass according to docs if SINT/UINT or
6387 8/24 COLOR variants */
6388 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
6389 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
6390 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
6395 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
6396 (format
== V_028C70_COLOR_8
||
6397 format
== V_028C70_COLOR_8_8
||
6398 format
== V_028C70_COLOR_8_8_8_8
))
6399 ->color_is_int8
= true;
6401 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
6402 S_028C70_COMP_SWAP(swap
) |
6403 S_028C70_BLEND_CLAMP(blend_clamp
) |
6404 S_028C70_BLEND_BYPASS(blend_bypass
) |
6405 S_028C70_SIMPLE_FLOAT(1) |
6406 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
6407 ntype
!= V_028C70_NUMBER_SNORM
&&
6408 ntype
!= V_028C70_NUMBER_SRGB
&&
6409 format
!= V_028C70_COLOR_8_24
&&
6410 format
!= V_028C70_COLOR_24_8
) |
6411 S_028C70_NUMBER_TYPE(ntype
) |
6412 S_028C70_ENDIAN(endian
);
6413 if (radv_image_has_fmask(iview
->image
)) {
6414 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
6415 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6416 unsigned fmask_bankh
= util_logbase2(surf
->u
.legacy
.fmask
.bankh
);
6417 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
6420 if (radv_image_is_tc_compat_cmask(iview
->image
)) {
6421 /* Allow the texture block to read FMASK directly
6422 * without decompressing it. This bit must be cleared
6423 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6424 * otherwise the operation doesn't happen.
6426 cb
->cb_color_info
|= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6428 /* Set CMASK into a tiling format that allows the
6429 * texture block to read it.
6431 cb
->cb_color_info
|= S_028C70_CMASK_ADDR_TYPE(2);
6435 if (radv_image_has_cmask(iview
->image
) &&
6436 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
6437 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
6439 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6440 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
6442 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
6444 /* This must be set for fast clear to work without FMASK. */
6445 if (!radv_image_has_fmask(iview
->image
) &&
6446 device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6447 unsigned bankh
= util_logbase2(surf
->u
.legacy
.bankh
);
6448 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
6451 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6452 const struct vk_format_description
*format_desc
= vk_format_description(iview
->image
->vk_format
);
6454 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
6455 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
6456 unsigned width
= iview
->extent
.width
/ (iview
->plane_id
? format_desc
->width_divisor
: 1);
6457 unsigned height
= iview
->extent
.height
/ (iview
->plane_id
? format_desc
->height_divisor
: 1);
6459 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6460 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX10(iview
->base_mip
);
6462 cb
->cb_color_attrib3
|= S_028EE0_MIP0_DEPTH(mip0_depth
) |
6463 S_028EE0_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
) |
6464 S_028EE0_RESOURCE_LEVEL(1);
6466 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX9(iview
->base_mip
);
6467 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
6468 S_028C74_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
);
6471 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(width
- 1) |
6472 S_028C68_MIP0_HEIGHT(height
- 1) |
6473 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
6478 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
6479 struct radv_image_view
*iview
)
6481 unsigned max_zplanes
= 0;
6483 assert(radv_image_is_tc_compat_htile(iview
->image
));
6485 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6486 /* Default value for 32-bit depth surfaces. */
6489 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
6490 iview
->image
->info
.samples
> 1)
6493 max_zplanes
= max_zplanes
+ 1;
6495 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
6496 /* Do not enable Z plane compression for 16-bit depth
6497 * surfaces because isn't supported on GFX8. Only
6498 * 32-bit depth surfaces are supported by the hardware.
6499 * This allows to maintain shader compatibility and to
6500 * reduce the number of depth decompressions.
6504 if (iview
->image
->info
.samples
<= 1)
6506 else if (iview
->image
->info
.samples
<= 4)
6517 radv_initialise_ds_surface(struct radv_device
*device
,
6518 struct radv_ds_buffer_info
*ds
,
6519 struct radv_image_view
*iview
)
6521 unsigned level
= iview
->base_mip
;
6522 unsigned format
, stencil_format
;
6523 uint64_t va
, s_offs
, z_offs
;
6524 bool stencil_only
= false;
6525 const struct radv_image_plane
*plane
= &iview
->image
->planes
[0];
6526 const struct radeon_surf
*surf
= &plane
->surface
;
6528 assert(vk_format_get_plane_count(iview
->image
->vk_format
) == 1);
6530 memset(ds
, 0, sizeof(*ds
));
6531 switch (iview
->image
->vk_format
) {
6532 case VK_FORMAT_D24_UNORM_S8_UINT
:
6533 case VK_FORMAT_X8_D24_UNORM_PACK32
:
6534 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6535 ds
->offset_scale
= 2.0f
;
6537 case VK_FORMAT_D16_UNORM
:
6538 case VK_FORMAT_D16_UNORM_S8_UINT
:
6539 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6540 ds
->offset_scale
= 4.0f
;
6542 case VK_FORMAT_D32_SFLOAT
:
6543 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
6544 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6545 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6546 ds
->offset_scale
= 1.0f
;
6548 case VK_FORMAT_S8_UINT
:
6549 stencil_only
= true;
6555 format
= radv_translate_dbformat(iview
->image
->vk_format
);
6556 stencil_format
= surf
->has_stencil
?
6557 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
6559 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6560 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
6561 S_028008_SLICE_MAX(max_slice
);
6562 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6563 ds
->db_depth_view
|= S_028008_SLICE_START_HI(iview
->base_layer
>> 11) |
6564 S_028008_SLICE_MAX_HI(max_slice
>> 11);
6567 ds
->db_htile_data_base
= 0;
6568 ds
->db_htile_surface
= 0;
6570 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6571 s_offs
= z_offs
= va
;
6573 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6574 assert(surf
->u
.gfx9
.surf_offset
== 0);
6575 s_offs
+= surf
->u
.gfx9
.stencil_offset
;
6577 ds
->db_z_info
= S_028038_FORMAT(format
) |
6578 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
6579 S_028038_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6580 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
6581 S_028038_ZRANGE_PRECISION(1);
6582 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
6583 S_02803C_SW_MODE(surf
->u
.gfx9
.stencil
.swizzle_mode
);
6585 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
6586 ds
->db_z_info2
= S_028068_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6587 ds
->db_stencil_info2
= S_02806C_EPITCH(surf
->u
.gfx9
.stencil
.epitch
);
6590 ds
->db_depth_view
|= S_028008_MIPID(level
);
6591 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
6592 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
6594 if (radv_htile_enabled(iview
->image
, level
)) {
6595 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
6597 if (radv_image_is_tc_compat_htile(iview
->image
)) {
6598 unsigned max_zplanes
=
6599 radv_calc_decompress_on_z_planes(device
, iview
);
6601 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
6603 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6604 ds
->db_z_info
|= S_028040_ITERATE_FLUSH(1);
6605 ds
->db_stencil_info
|= S_028044_ITERATE_FLUSH(1);
6607 ds
->db_z_info
|= S_028038_ITERATE_FLUSH(1);
6608 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
6612 if (!surf
->has_stencil
)
6613 /* Use all of the htile_buffer for depth if there's no stencil. */
6614 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
6615 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
6616 iview
->image
->htile_offset
;
6617 ds
->db_htile_data_base
= va
>> 8;
6618 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
6619 S_028ABC_PIPE_ALIGNED(surf
->u
.gfx9
.htile
.pipe_aligned
);
6621 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
6622 ds
->db_htile_surface
|= S_028ABC_RB_ALIGNED(surf
->u
.gfx9
.htile
.rb_aligned
);
6626 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[level
];
6629 level_info
= &surf
->u
.legacy
.stencil_level
[level
];
6631 z_offs
+= surf
->u
.legacy
.level
[level
].offset
;
6632 s_offs
+= surf
->u
.legacy
.stencil_level
[level
].offset
;
6634 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
6635 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
6636 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
6638 if (iview
->image
->info
.samples
> 1)
6639 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
6641 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
6642 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
6643 unsigned tiling_index
= surf
->u
.legacy
.tiling_index
[level
];
6644 unsigned stencil_index
= surf
->u
.legacy
.stencil_tiling_index
[level
];
6645 unsigned macro_index
= surf
->u
.legacy
.macro_tile_index
;
6646 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
6647 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
6648 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
6651 tile_mode
= stencil_tile_mode
;
6653 ds
->db_depth_info
|=
6654 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
6655 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
6656 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
6657 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
6658 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
6659 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
6660 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
6661 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
6663 unsigned tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, false);
6664 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
6665 tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, true);
6666 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
6668 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
6671 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
6672 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
6673 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
6675 if (radv_htile_enabled(iview
->image
, level
)) {
6676 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
6678 if (!surf
->has_stencil
&&
6679 !radv_image_is_tc_compat_htile(iview
->image
))
6680 /* Use all of the htile_buffer for depth if there's no stencil. */
6681 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
6683 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
6684 iview
->image
->htile_offset
;
6685 ds
->db_htile_data_base
= va
>> 8;
6686 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
6688 if (radv_image_is_tc_compat_htile(iview
->image
)) {
6689 unsigned max_zplanes
=
6690 radv_calc_decompress_on_z_planes(device
, iview
);
6692 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
6693 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
6698 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
6699 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
6702 VkResult
radv_CreateFramebuffer(
6704 const VkFramebufferCreateInfo
* pCreateInfo
,
6705 const VkAllocationCallbacks
* pAllocator
,
6706 VkFramebuffer
* pFramebuffer
)
6708 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6709 struct radv_framebuffer
*framebuffer
;
6710 const VkFramebufferAttachmentsCreateInfo
*imageless_create_info
=
6711 vk_find_struct_const(pCreateInfo
->pNext
,
6712 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO
);
6714 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
6716 size_t size
= sizeof(*framebuffer
);
6717 if (!imageless_create_info
)
6718 size
+= sizeof(struct radv_image_view
*) * pCreateInfo
->attachmentCount
;
6719 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
6720 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6721 if (framebuffer
== NULL
)
6722 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6724 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
6725 framebuffer
->width
= pCreateInfo
->width
;
6726 framebuffer
->height
= pCreateInfo
->height
;
6727 framebuffer
->layers
= pCreateInfo
->layers
;
6728 if (imageless_create_info
) {
6729 for (unsigned i
= 0; i
< imageless_create_info
->attachmentImageInfoCount
; ++i
) {
6730 const VkFramebufferAttachmentImageInfo
*attachment
=
6731 imageless_create_info
->pAttachmentImageInfos
+ i
;
6732 framebuffer
->width
= MIN2(framebuffer
->width
, attachment
->width
);
6733 framebuffer
->height
= MIN2(framebuffer
->height
, attachment
->height
);
6734 framebuffer
->layers
= MIN2(framebuffer
->layers
, attachment
->layerCount
);
6737 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
6738 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
6739 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
6740 framebuffer
->attachments
[i
] = iview
;
6741 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
6742 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
6743 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
6747 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
6751 void radv_DestroyFramebuffer(
6754 const VkAllocationCallbacks
* pAllocator
)
6756 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6757 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
6761 vk_free2(&device
->alloc
, pAllocator
, fb
);
6764 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
6766 switch (address_mode
) {
6767 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
6768 return V_008F30_SQ_TEX_WRAP
;
6769 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
6770 return V_008F30_SQ_TEX_MIRROR
;
6771 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
6772 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
6773 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
6774 return V_008F30_SQ_TEX_CLAMP_BORDER
;
6775 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
6776 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
6778 unreachable("illegal tex wrap mode");
6784 radv_tex_compare(VkCompareOp op
)
6787 case VK_COMPARE_OP_NEVER
:
6788 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
6789 case VK_COMPARE_OP_LESS
:
6790 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
6791 case VK_COMPARE_OP_EQUAL
:
6792 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
6793 case VK_COMPARE_OP_LESS_OR_EQUAL
:
6794 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
6795 case VK_COMPARE_OP_GREATER
:
6796 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
6797 case VK_COMPARE_OP_NOT_EQUAL
:
6798 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
6799 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
6800 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
6801 case VK_COMPARE_OP_ALWAYS
:
6802 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
6804 unreachable("illegal compare mode");
6810 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
6813 case VK_FILTER_NEAREST
:
6814 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
6815 V_008F38_SQ_TEX_XY_FILTER_POINT
);
6816 case VK_FILTER_LINEAR
:
6817 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
6818 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
6819 case VK_FILTER_CUBIC_IMG
:
6821 fprintf(stderr
, "illegal texture filter");
6827 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
6830 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
6831 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
6832 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
6833 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
6835 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
6840 radv_tex_bordercolor(VkBorderColor bcolor
)
6843 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
6844 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
6845 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
6846 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
6847 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
6848 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
6849 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
6850 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
6851 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
6859 radv_tex_aniso_filter(unsigned filter
)
6873 radv_tex_filter_mode(VkSamplerReductionMode mode
)
6876 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
6877 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
6878 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
6879 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
6880 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
6881 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
6889 radv_get_max_anisotropy(struct radv_device
*device
,
6890 const VkSamplerCreateInfo
*pCreateInfo
)
6892 if (device
->force_aniso
>= 0)
6893 return device
->force_aniso
;
6895 if (pCreateInfo
->anisotropyEnable
&&
6896 pCreateInfo
->maxAnisotropy
> 1.0f
)
6897 return (uint32_t)pCreateInfo
->maxAnisotropy
;
6903 radv_init_sampler(struct radv_device
*device
,
6904 struct radv_sampler
*sampler
,
6905 const VkSamplerCreateInfo
*pCreateInfo
)
6907 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
6908 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
6909 bool compat_mode
= device
->physical_device
->rad_info
.chip_class
== GFX8
||
6910 device
->physical_device
->rad_info
.chip_class
== GFX9
;
6911 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
6912 unsigned depth_compare_func
= V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
6914 const struct VkSamplerReductionModeCreateInfo
*sampler_reduction
=
6915 vk_find_struct_const(pCreateInfo
->pNext
,
6916 SAMPLER_REDUCTION_MODE_CREATE_INFO
);
6917 if (sampler_reduction
)
6918 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
6920 if (pCreateInfo
->compareEnable
)
6921 depth_compare_func
= radv_tex_compare(pCreateInfo
->compareOp
);
6923 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
6924 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
6925 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
6926 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
6927 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func
) |
6928 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
6929 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
6930 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
6931 S_008F30_DISABLE_CUBE_WRAP(0) |
6932 S_008F30_COMPAT_MODE(compat_mode
) |
6933 S_008F30_FILTER_MODE(filter_mode
));
6934 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
6935 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
6936 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
6937 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
6938 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
6939 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
6940 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
6941 S_008F38_MIP_POINT_PRECLAMP(0));
6942 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
6943 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
6945 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6946 sampler
->state
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
6948 sampler
->state
[2] |=
6949 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= GFX8
) |
6950 S_008F38_FILTER_PREC_FIX(1) |
6951 S_008F38_ANISO_OVERRIDE_GFX6(device
->physical_device
->rad_info
.chip_class
>= GFX8
);
6955 VkResult
radv_CreateSampler(
6957 const VkSamplerCreateInfo
* pCreateInfo
,
6958 const VkAllocationCallbacks
* pAllocator
,
6959 VkSampler
* pSampler
)
6961 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6962 struct radv_sampler
*sampler
;
6964 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
6965 vk_find_struct_const(pCreateInfo
->pNext
,
6966 SAMPLER_YCBCR_CONVERSION_INFO
);
6968 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
6970 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
6971 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6973 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6975 radv_init_sampler(device
, sampler
, pCreateInfo
);
6977 sampler
->ycbcr_sampler
= ycbcr_conversion
? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
): NULL
;
6978 *pSampler
= radv_sampler_to_handle(sampler
);
6983 void radv_DestroySampler(
6986 const VkAllocationCallbacks
* pAllocator
)
6988 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6989 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
6993 vk_free2(&device
->alloc
, pAllocator
, sampler
);
6996 /* vk_icd.h does not declare this function, so we declare it here to
6997 * suppress Wmissing-prototypes.
6999 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7000 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
7002 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7003 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
7005 /* For the full details on loader interface versioning, see
7006 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
7007 * What follows is a condensed summary, to help you navigate the large and
7008 * confusing official doc.
7010 * - Loader interface v0 is incompatible with later versions. We don't
7013 * - In loader interface v1:
7014 * - The first ICD entrypoint called by the loader is
7015 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
7017 * - The ICD must statically expose no other Vulkan symbol unless it is
7018 * linked with -Bsymbolic.
7019 * - Each dispatchable Vulkan handle created by the ICD must be
7020 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7021 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7022 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7023 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7024 * such loader-managed surfaces.
7026 * - Loader interface v2 differs from v1 in:
7027 * - The first ICD entrypoint called by the loader is
7028 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7029 * statically expose this entrypoint.
7031 * - Loader interface v3 differs from v2 in:
7032 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7033 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7034 * because the loader no longer does so.
7036 *pSupportedVersion
= MIN2(*pSupportedVersion
, 4u);
7040 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
7041 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
7044 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7045 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
7047 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
7049 /* At the moment, we support only the below handle types. */
7050 assert(pGetFdInfo
->handleType
==
7051 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
7052 pGetFdInfo
->handleType
==
7053 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
7055 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
7057 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
7061 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
7062 VkExternalMemoryHandleTypeFlagBits handleType
,
7064 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
7066 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7068 switch (handleType
) {
7069 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
:
7070 pMemoryFdProperties
->memoryTypeBits
= (1 << RADV_MEM_TYPE_COUNT
) - 1;
7074 /* The valid usage section for this function says:
7076 * "handleType must not be one of the handle types defined as
7079 * So opaque handle types fall into the default "unsupported" case.
7081 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7085 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
7089 uint32_t syncobj_handle
= 0;
7090 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
7092 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7095 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
7097 *syncobj
= syncobj_handle
;
7103 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
7107 /* If we create a syncobj we do it locally so that if we have an error, we don't
7108 * leave a syncobj in an undetermined state in the fence. */
7109 uint32_t syncobj_handle
= *syncobj
;
7110 if (!syncobj_handle
) {
7111 int ret
= device
->ws
->create_syncobj(device
->ws
, &syncobj_handle
);
7113 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7118 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
);
7120 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
7122 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7125 *syncobj
= syncobj_handle
;
7132 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
7133 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
7135 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7136 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
7138 struct radv_semaphore_part
*dst
= NULL
;
7140 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
7141 dst
= &sem
->temporary
;
7143 dst
= &sem
->permanent
;
7146 uint32_t syncobj
= dst
->kind
== RADV_SEMAPHORE_SYNCOBJ
? dst
->syncobj
: 0;
7148 switch(pImportSemaphoreFdInfo
->handleType
) {
7149 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7150 result
= radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7152 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7153 result
= radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7156 unreachable("Unhandled semaphore handle type");
7159 if (result
== VK_SUCCESS
) {
7160 dst
->syncobj
= syncobj
;
7161 dst
->kind
= RADV_SEMAPHORE_SYNCOBJ
;
7167 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
7168 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
7171 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7172 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
7174 uint32_t syncobj_handle
;
7176 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7177 assert(sem
->temporary
.kind
== RADV_SEMAPHORE_SYNCOBJ
);
7178 syncobj_handle
= sem
->temporary
.syncobj
;
7180 assert(sem
->permanent
.kind
== RADV_SEMAPHORE_SYNCOBJ
);
7181 syncobj_handle
= sem
->permanent
.syncobj
;
7184 switch(pGetFdInfo
->handleType
) {
7185 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7186 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
7188 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7189 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
7191 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7192 radv_destroy_semaphore_part(device
, &sem
->temporary
);
7194 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
7199 unreachable("Unhandled semaphore handle type");
7203 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7207 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7208 VkPhysicalDevice physicalDevice
,
7209 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
7210 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
7212 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7213 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pExternalSemaphoreInfo
->pNext
, NULL
);
7215 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
7216 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7217 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7218 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7220 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7221 } else if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7222 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7223 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7224 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7225 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7226 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7227 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7228 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
7229 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7230 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7231 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7232 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7234 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7235 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7236 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7240 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
7241 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
7243 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7244 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
7245 uint32_t *syncobj_dst
= NULL
;
7248 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
7249 syncobj_dst
= &fence
->temp_syncobj
;
7251 syncobj_dst
= &fence
->syncobj
;
7254 switch(pImportFenceFdInfo
->handleType
) {
7255 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7256 return radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
7257 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7258 return radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
7260 unreachable("Unhandled fence handle type");
7264 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
7265 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
7268 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7269 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
7271 uint32_t syncobj_handle
;
7273 if (fence
->temp_syncobj
)
7274 syncobj_handle
= fence
->temp_syncobj
;
7276 syncobj_handle
= fence
->syncobj
;
7278 switch(pGetFdInfo
->handleType
) {
7279 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7280 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
7282 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7283 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
7285 if (fence
->temp_syncobj
) {
7286 close (fence
->temp_syncobj
);
7287 fence
->temp_syncobj
= 0;
7289 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
7294 unreachable("Unhandled fence handle type");
7298 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7302 void radv_GetPhysicalDeviceExternalFenceProperties(
7303 VkPhysicalDevice physicalDevice
,
7304 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
7305 VkExternalFenceProperties
*pExternalFenceProperties
)
7307 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7309 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7310 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7311 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7312 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7313 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7314 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
7315 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7317 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
7318 pExternalFenceProperties
->compatibleHandleTypes
= 0;
7319 pExternalFenceProperties
->externalFenceFeatures
= 0;
7324 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
7325 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
7326 const VkAllocationCallbacks
* pAllocator
,
7327 VkDebugReportCallbackEXT
* pCallback
)
7329 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7330 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
7331 pCreateInfo
, pAllocator
, &instance
->alloc
,
7336 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
7337 VkDebugReportCallbackEXT _callback
,
7338 const VkAllocationCallbacks
* pAllocator
)
7340 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7341 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
7342 _callback
, pAllocator
, &instance
->alloc
);
7346 radv_DebugReportMessageEXT(VkInstance _instance
,
7347 VkDebugReportFlagsEXT flags
,
7348 VkDebugReportObjectTypeEXT objectType
,
7351 int32_t messageCode
,
7352 const char* pLayerPrefix
,
7353 const char* pMessage
)
7355 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7356 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
7357 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
7361 radv_GetDeviceGroupPeerMemoryFeatures(
7364 uint32_t localDeviceIndex
,
7365 uint32_t remoteDeviceIndex
,
7366 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
7368 assert(localDeviceIndex
== remoteDeviceIndex
);
7370 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
7371 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
7372 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
7373 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
7376 static const VkTimeDomainEXT radv_time_domains
[] = {
7377 VK_TIME_DOMAIN_DEVICE_EXT
,
7378 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
7379 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
7382 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7383 VkPhysicalDevice physicalDevice
,
7384 uint32_t *pTimeDomainCount
,
7385 VkTimeDomainEXT
*pTimeDomains
)
7388 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
7390 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
7391 vk_outarray_append(&out
, i
) {
7392 *i
= radv_time_domains
[d
];
7396 return vk_outarray_status(&out
);
7400 radv_clock_gettime(clockid_t clock_id
)
7402 struct timespec current
;
7405 ret
= clock_gettime(clock_id
, ¤t
);
7406 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
7407 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
7411 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
7414 VkResult
radv_GetCalibratedTimestampsEXT(
7416 uint32_t timestampCount
,
7417 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
7418 uint64_t *pTimestamps
,
7419 uint64_t *pMaxDeviation
)
7421 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7422 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
7424 uint64_t begin
, end
;
7425 uint64_t max_clock_period
= 0;
7427 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
7429 for (d
= 0; d
< timestampCount
; d
++) {
7430 switch (pTimestampInfos
[d
].timeDomain
) {
7431 case VK_TIME_DOMAIN_DEVICE_EXT
:
7432 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
7434 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
7435 max_clock_period
= MAX2(max_clock_period
, device_period
);
7437 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
7438 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
7439 max_clock_period
= MAX2(max_clock_period
, 1);
7442 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
7443 pTimestamps
[d
] = begin
;
7451 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
7454 * The maximum deviation is the sum of the interval over which we
7455 * perform the sampling and the maximum period of any sampled
7456 * clock. That's because the maximum skew between any two sampled
7457 * clock edges is when the sampled clock with the largest period is
7458 * sampled at the end of that period but right at the beginning of the
7459 * sampling interval and some other clock is sampled right at the
7460 * begining of its sampling period and right at the end of the
7461 * sampling interval. Let's assume the GPU has the longest clock
7462 * period and that the application is sampling GPU and monotonic:
7465 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
7466 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7470 * GPU -----_____-----_____-----_____-----_____
7473 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
7474 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7476 * Interval <----------------->
7477 * Deviation <-------------------------->
7481 * m = read(monotonic) 2
7484 * We round the sample interval up by one tick to cover sampling error
7485 * in the interval clock
7488 uint64_t sample_interval
= end
- begin
+ 1;
7490 *pMaxDeviation
= sample_interval
+ max_clock_period
;
7495 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
7496 VkPhysicalDevice physicalDevice
,
7497 VkSampleCountFlagBits samples
,
7498 VkMultisamplePropertiesEXT
* pMultisampleProperties
)
7500 if (samples
& (VK_SAMPLE_COUNT_2_BIT
|
7501 VK_SAMPLE_COUNT_4_BIT
|
7502 VK_SAMPLE_COUNT_8_BIT
)) {
7503 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2, 2 };
7505 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 0, 0 };