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radv: Fix timeline semaphore refcounting.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "dirent.h"
29 #include <errno.h>
30 #include <fcntl.h>
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
36 #include <stdbool.h>
37 #include <stddef.h>
38 #include <stdio.h>
39 #include <string.h>
40 #include <sys/prctl.h>
41 #include <sys/wait.h>
42 #include <unistd.h>
43 #include <fcntl.h>
44 #include <llvm/Config/llvm-config.h>
45
46 #include "radv_debug.h"
47 #include "radv_private.h"
48 #include "radv_shader.h"
49 #include "radv_cs.h"
50 #include "util/disk_cache.h"
51 #include "vk_util.h"
52 #include <xf86drm.h>
53 #include <amdgpu.h>
54 #include <amdgpu_drm.h>
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "ac_llvm_util.h"
57 #include "vk_format.h"
58 #include "sid.h"
59 #include "git_sha1.h"
60 #include "util/build_id.h"
61 #include "util/debug.h"
62 #include "util/mesa-sha1.h"
63 #include "util/timespec.h"
64 #include "util/u_atomic.h"
65 #include "compiler/glsl_types.h"
66 #include "util/xmlpool.h"
67
68 static struct radv_timeline_point *
69 radv_timeline_find_point_at_least_locked(struct radv_device *device,
70 struct radv_timeline *timeline,
71 uint64_t p);
72
73 static struct radv_timeline_point *
74 radv_timeline_add_point_locked(struct radv_device *device,
75 struct radv_timeline *timeline,
76 uint64_t p);
77
78 static void
79 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
80 struct list_head *processing_list);
81
82 static
83 void radv_destroy_semaphore_part(struct radv_device *device,
84 struct radv_semaphore_part *part);
85
86 static int
87 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
88 {
89 struct mesa_sha1 ctx;
90 unsigned char sha1[20];
91 unsigned ptr_size = sizeof(void*);
92
93 memset(uuid, 0, VK_UUID_SIZE);
94 _mesa_sha1_init(&ctx);
95
96 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
97 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
98 return -1;
99
100 _mesa_sha1_update(&ctx, &family, sizeof(family));
101 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
102 _mesa_sha1_final(&ctx, sha1);
103
104 memcpy(uuid, sha1, VK_UUID_SIZE);
105 return 0;
106 }
107
108 static void
109 radv_get_driver_uuid(void *uuid)
110 {
111 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
112 }
113
114 static void
115 radv_get_device_uuid(struct radeon_info *info, void *uuid)
116 {
117 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
118 }
119
120 static uint64_t
121 radv_get_visible_vram_size(struct radv_physical_device *device)
122 {
123 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
124 }
125
126 static uint64_t
127 radv_get_vram_size(struct radv_physical_device *device)
128 {
129 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
130 }
131
132 static bool
133 radv_is_mem_type_vram(enum radv_mem_type type)
134 {
135 return type == RADV_MEM_TYPE_VRAM ||
136 type == RADV_MEM_TYPE_VRAM_UNCACHED;
137 }
138
139 static bool
140 radv_is_mem_type_vram_visible(enum radv_mem_type type)
141 {
142 return type == RADV_MEM_TYPE_VRAM_CPU_ACCESS ||
143 type == RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED;
144 }
145 static bool
146 radv_is_mem_type_gtt_wc(enum radv_mem_type type)
147 {
148 return type == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
149 type == RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED;
150 }
151
152 static bool
153 radv_is_mem_type_gtt_cached(enum radv_mem_type type)
154 {
155 return type == RADV_MEM_TYPE_GTT_CACHED ||
156 type == RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED;
157 }
158
159 static bool
160 radv_is_mem_type_uncached(enum radv_mem_type type)
161 {
162 return type == RADV_MEM_TYPE_VRAM_UNCACHED ||
163 type == RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED ||
164 type == RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED ||
165 type == RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED;
166 }
167
168 static void
169 radv_physical_device_init_mem_types(struct radv_physical_device *device)
170 {
171 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
172 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
173 uint64_t vram_size = radv_get_vram_size(device);
174 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
175 device->memory_properties.memoryHeapCount = 0;
176 if (vram_size > 0) {
177 vram_index = device->memory_properties.memoryHeapCount++;
178 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
179 .size = vram_size,
180 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
181 };
182 }
183 if (visible_vram_size) {
184 visible_vram_index = device->memory_properties.memoryHeapCount++;
185 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
186 .size = visible_vram_size,
187 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
188 };
189 }
190 if (device->rad_info.gart_size > 0) {
191 gart_index = device->memory_properties.memoryHeapCount++;
192 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
193 .size = device->rad_info.gart_size,
194 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
195 };
196 }
197
198 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
199 unsigned type_count = 0;
200 if (vram_index >= 0) {
201 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
202 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
203 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
204 .heapIndex = vram_index,
205 };
206 }
207 if (gart_index >= 0 && device->rad_info.has_dedicated_vram) {
208 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
209 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
210 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
211 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
212 .heapIndex = gart_index,
213 };
214 }
215 if (visible_vram_index >= 0) {
216 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
217 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
218 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
219 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
220 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
221 .heapIndex = visible_vram_index,
222 };
223 }
224 if (gart_index >= 0 && !device->rad_info.has_dedicated_vram) {
225 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
226 * as they have identical property flags, and according to the
227 * spec, for types with identical flags, the one with greater
228 * performance must be given a lower index. */
229 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
230 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
231 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
232 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
233 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
234 .heapIndex = gart_index,
235 };
236 }
237 if (gart_index >= 0) {
238 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
239 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
240 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
241 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
242 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
243 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
244 .heapIndex = gart_index,
245 };
246 }
247 device->memory_properties.memoryTypeCount = type_count;
248
249 if (device->rad_info.has_l2_uncached) {
250 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
251 VkMemoryType mem_type = device->memory_properties.memoryTypes[i];
252
253 if ((mem_type.propertyFlags & (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
254 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)) ||
255 mem_type.propertyFlags == VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) {
256 enum radv_mem_type mem_type_id;
257
258 switch (device->mem_type_indices[i]) {
259 case RADV_MEM_TYPE_VRAM:
260 mem_type_id = RADV_MEM_TYPE_VRAM_UNCACHED;
261 break;
262 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
263 mem_type_id = RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED;
264 break;
265 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
266 mem_type_id = RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED;
267 break;
268 case RADV_MEM_TYPE_GTT_CACHED:
269 mem_type_id = RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED;
270 break;
271 default:
272 unreachable("invalid memory type");
273 }
274
275 VkMemoryPropertyFlags property_flags = mem_type.propertyFlags |
276 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD |
277 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD;
278
279 device->mem_type_indices[type_count] = mem_type_id;
280 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
281 .propertyFlags = property_flags,
282 .heapIndex = mem_type.heapIndex,
283 };
284 }
285 }
286 device->memory_properties.memoryTypeCount = type_count;
287 }
288 }
289
290 static void
291 radv_handle_env_var_force_family(struct radv_physical_device *device)
292 {
293 const char *family = getenv("RADV_FORCE_FAMILY");
294 unsigned i;
295
296 if (!family)
297 return;
298
299 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
300 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
301 /* Override family and chip_class. */
302 device->rad_info.family = i;
303
304 if (i >= CHIP_NAVI10)
305 device->rad_info.chip_class = GFX10;
306 else if (i >= CHIP_VEGA10)
307 device->rad_info.chip_class = GFX9;
308 else if (i >= CHIP_TONGA)
309 device->rad_info.chip_class = GFX8;
310 else if (i >= CHIP_BONAIRE)
311 device->rad_info.chip_class = GFX7;
312 else
313 device->rad_info.chip_class = GFX6;
314
315 return;
316 }
317 }
318
319 fprintf(stderr, "radv: Unknown family: %s\n", family);
320 exit(1);
321 }
322
323 static VkResult
324 radv_physical_device_init(struct radv_physical_device *device,
325 struct radv_instance *instance,
326 drmDevicePtr drm_device)
327 {
328 const char *path = drm_device->nodes[DRM_NODE_RENDER];
329 VkResult result;
330 drmVersionPtr version;
331 int fd;
332 int master_fd = -1;
333
334 fd = open(path, O_RDWR | O_CLOEXEC);
335 if (fd < 0) {
336 if (instance->debug_flags & RADV_DEBUG_STARTUP)
337 radv_logi("Could not open device '%s'", path);
338
339 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
340 }
341
342 version = drmGetVersion(fd);
343 if (!version) {
344 close(fd);
345
346 if (instance->debug_flags & RADV_DEBUG_STARTUP)
347 radv_logi("Could not get the kernel driver version for device '%s'", path);
348
349 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
350 "failed to get version %s: %m", path);
351 }
352
353 if (strcmp(version->name, "amdgpu")) {
354 drmFreeVersion(version);
355 close(fd);
356
357 if (instance->debug_flags & RADV_DEBUG_STARTUP)
358 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
359
360 return VK_ERROR_INCOMPATIBLE_DRIVER;
361 }
362 drmFreeVersion(version);
363
364 if (instance->debug_flags & RADV_DEBUG_STARTUP)
365 radv_logi("Found compatible device '%s'.", path);
366
367 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
368 device->instance = instance;
369
370 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
371 instance->perftest_flags);
372 if (!device->ws) {
373 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
374 goto fail;
375 }
376
377 if (instance->enabled_extensions.KHR_display) {
378 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
379 if (master_fd >= 0) {
380 uint32_t accel_working = 0;
381 struct drm_amdgpu_info request = {
382 .return_pointer = (uintptr_t)&accel_working,
383 .return_size = sizeof(accel_working),
384 .query = AMDGPU_INFO_ACCEL_WORKING
385 };
386
387 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
388 close(master_fd);
389 master_fd = -1;
390 }
391 }
392 }
393
394 device->master_fd = master_fd;
395 device->local_fd = fd;
396 device->ws->query_info(device->ws, &device->rad_info);
397
398 radv_handle_env_var_force_family(device);
399
400 device->use_aco = instance->perftest_flags & RADV_PERFTEST_ACO;
401 if (device->rad_info.chip_class < GFX8 && device->use_aco) {
402 fprintf(stderr, "WARNING: disabling ACO on unsupported GPUs.\n");
403 device->use_aco = false;
404 }
405
406 snprintf(device->name, sizeof(device->name),
407 "AMD RADV%s %s (LLVM " MESA_LLVM_VERSION_STRING ")", device->use_aco ? "/ACO" : "",
408 device->rad_info.name);
409
410 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
411 device->ws->destroy(device->ws);
412 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
413 "cannot generate UUID");
414 goto fail;
415 }
416
417 /* These flags affect shader compilation. */
418 uint64_t shader_env_flags =
419 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
420 (device->use_aco ? 0x2 : 0);
421
422 /* The gpu id is already embedded in the uuid so we just pass "radv"
423 * when creating the cache.
424 */
425 char buf[VK_UUID_SIZE * 2 + 1];
426 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
427 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
428
429 if (device->rad_info.chip_class < GFX8 ||
430 device->rad_info.chip_class > GFX9)
431 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
432
433 radv_get_driver_uuid(&device->driver_uuid);
434 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
435
436 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
437 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
438
439 device->dcc_msaa_allowed =
440 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
441
442 device->use_shader_ballot = device->use_aco || (device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT);
443
444 device->use_ngg = device->rad_info.chip_class >= GFX10 &&
445 device->rad_info.family != CHIP_NAVI14 &&
446 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
447 if (device->use_aco && device->use_ngg) {
448 fprintf(stderr, "WARNING: disabling NGG because ACO is used.\n");
449 device->use_ngg = false;
450 }
451
452 device->use_ngg_streamout = false;
453
454 /* Determine the number of threads per wave for all stages. */
455 device->cs_wave_size = 64;
456 device->ps_wave_size = 64;
457 device->ge_wave_size = 64;
458
459 if (device->rad_info.chip_class >= GFX10) {
460 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
461 device->cs_wave_size = 32;
462
463 /* For pixel shaders, wave64 is recommanded. */
464 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
465 device->ps_wave_size = 32;
466
467 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
468 device->ge_wave_size = 32;
469 }
470
471 radv_physical_device_init_mem_types(device);
472 radv_fill_device_extension_table(device, &device->supported_extensions);
473
474 device->bus_info = *drm_device->businfo.pci;
475
476 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
477 ac_print_gpu_info(&device->rad_info);
478
479 /* The WSI is structured as a layer on top of the driver, so this has
480 * to be the last part of initialization (at least until we get other
481 * semi-layers).
482 */
483 result = radv_init_wsi(device);
484 if (result != VK_SUCCESS) {
485 device->ws->destroy(device->ws);
486 vk_error(instance, result);
487 goto fail;
488 }
489
490 return VK_SUCCESS;
491
492 fail:
493 close(fd);
494 if (master_fd != -1)
495 close(master_fd);
496 return result;
497 }
498
499 static void
500 radv_physical_device_finish(struct radv_physical_device *device)
501 {
502 radv_finish_wsi(device);
503 device->ws->destroy(device->ws);
504 disk_cache_destroy(device->disk_cache);
505 close(device->local_fd);
506 if (device->master_fd != -1)
507 close(device->master_fd);
508 }
509
510 static void *
511 default_alloc_func(void *pUserData, size_t size, size_t align,
512 VkSystemAllocationScope allocationScope)
513 {
514 return malloc(size);
515 }
516
517 static void *
518 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
519 size_t align, VkSystemAllocationScope allocationScope)
520 {
521 return realloc(pOriginal, size);
522 }
523
524 static void
525 default_free_func(void *pUserData, void *pMemory)
526 {
527 free(pMemory);
528 }
529
530 static const VkAllocationCallbacks default_alloc = {
531 .pUserData = NULL,
532 .pfnAllocation = default_alloc_func,
533 .pfnReallocation = default_realloc_func,
534 .pfnFree = default_free_func,
535 };
536
537 static const struct debug_control radv_debug_options[] = {
538 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
539 {"nodcc", RADV_DEBUG_NO_DCC},
540 {"shaders", RADV_DEBUG_DUMP_SHADERS},
541 {"nocache", RADV_DEBUG_NO_CACHE},
542 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
543 {"nohiz", RADV_DEBUG_NO_HIZ},
544 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
545 {"allbos", RADV_DEBUG_ALL_BOS},
546 {"noibs", RADV_DEBUG_NO_IBS},
547 {"spirv", RADV_DEBUG_DUMP_SPIRV},
548 {"vmfaults", RADV_DEBUG_VM_FAULTS},
549 {"zerovram", RADV_DEBUG_ZERO_VRAM},
550 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
551 {"nosisched", RADV_DEBUG_NO_SISCHED},
552 {"preoptir", RADV_DEBUG_PREOPTIR},
553 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
554 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
555 {"info", RADV_DEBUG_INFO},
556 {"errors", RADV_DEBUG_ERRORS},
557 {"startup", RADV_DEBUG_STARTUP},
558 {"checkir", RADV_DEBUG_CHECKIR},
559 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
560 {"nobinning", RADV_DEBUG_NOBINNING},
561 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
562 {"nongg", RADV_DEBUG_NO_NGG},
563 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT},
564 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
565 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
566 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE},
567 {NULL, 0}
568 };
569
570 const char *
571 radv_get_debug_option_name(int id)
572 {
573 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
574 return radv_debug_options[id].string;
575 }
576
577 static const struct debug_control radv_perftest_options[] = {
578 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
579 {"sisched", RADV_PERFTEST_SISCHED},
580 {"localbos", RADV_PERFTEST_LOCAL_BOS},
581 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
582 {"bolist", RADV_PERFTEST_BO_LIST},
583 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
584 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
585 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
586 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
587 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
588 {"dfsm", RADV_PERFTEST_DFSM},
589 {"aco", RADV_PERFTEST_ACO},
590 {NULL, 0}
591 };
592
593 const char *
594 radv_get_perftest_option_name(int id)
595 {
596 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
597 return radv_perftest_options[id].string;
598 }
599
600 static void
601 radv_handle_per_app_options(struct radv_instance *instance,
602 const VkApplicationInfo *info)
603 {
604 const char *name = info ? info->pApplicationName : NULL;
605
606 if (!name)
607 return;
608
609 if (!strcmp(name, "Talos - Linux - 32bit") ||
610 !strcmp(name, "Talos - Linux - 64bit")) {
611 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
612 /* Force enable LLVM sisched for Talos because it looks
613 * safe and it gives few more FPS.
614 */
615 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
616 }
617 } else if (!strcmp(name, "DOOM_VFR")) {
618 /* Work around a Doom VFR game bug */
619 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
620 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
621 /* Workaround for a WaW hazard when LLVM moves/merges
622 * load/store memory operations.
623 * See https://reviews.llvm.org/D61313
624 */
625 if (LLVM_VERSION_MAJOR < 9)
626 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
627 } else if (!strcmp(name, "Wolfenstein: Youngblood")) {
628 if (!(instance->debug_flags & RADV_DEBUG_NO_SHADER_BALLOT)) {
629 /* Force enable VK_AMD_shader_ballot because it looks
630 * safe and it gives a nice boost (+20% on Vega 56 at
631 * this time).
632 */
633 instance->perftest_flags |= RADV_PERFTEST_SHADER_BALLOT;
634 }
635 } else if (!strcmp(name, "Fledge")) {
636 /*
637 * Zero VRAM for "The Surge 2"
638 *
639 * This avoid a hang when when rendering any level. Likely
640 * uninitialized data in an indirect draw.
641 */
642 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
643 }
644 }
645
646 static int radv_get_instance_extension_index(const char *name)
647 {
648 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
649 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
650 return i;
651 }
652 return -1;
653 }
654
655 static const char radv_dri_options_xml[] =
656 DRI_CONF_BEGIN
657 DRI_CONF_SECTION_PERFORMANCE
658 DRI_CONF_ADAPTIVE_SYNC("true")
659 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
660 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
661 DRI_CONF_SECTION_END
662 DRI_CONF_END;
663
664 static void radv_init_dri_options(struct radv_instance *instance)
665 {
666 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
667 driParseConfigFiles(&instance->dri_options,
668 &instance->available_dri_options,
669 0, "radv", NULL,
670 instance->engineName,
671 instance->engineVersion);
672 }
673
674 VkResult radv_CreateInstance(
675 const VkInstanceCreateInfo* pCreateInfo,
676 const VkAllocationCallbacks* pAllocator,
677 VkInstance* pInstance)
678 {
679 struct radv_instance *instance;
680 VkResult result;
681
682 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
683
684 uint32_t client_version;
685 if (pCreateInfo->pApplicationInfo &&
686 pCreateInfo->pApplicationInfo->apiVersion != 0) {
687 client_version = pCreateInfo->pApplicationInfo->apiVersion;
688 } else {
689 client_version = VK_API_VERSION_1_0;
690 }
691
692 const char *engine_name = NULL;
693 uint32_t engine_version = 0;
694 if (pCreateInfo->pApplicationInfo) {
695 engine_name = pCreateInfo->pApplicationInfo->pEngineName;
696 engine_version = pCreateInfo->pApplicationInfo->engineVersion;
697 }
698
699 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
700 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
701 if (!instance)
702 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
703
704 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
705
706 if (pAllocator)
707 instance->alloc = *pAllocator;
708 else
709 instance->alloc = default_alloc;
710
711 instance->apiVersion = client_version;
712 instance->physicalDeviceCount = -1;
713
714 /* Get secure compile thread count. NOTE: We cap this at 32 */
715 #define MAX_SC_PROCS 32
716 char *num_sc_threads = getenv("RADV_SECURE_COMPILE_THREADS");
717 if (num_sc_threads)
718 instance->num_sc_threads = MIN2(strtoul(num_sc_threads, NULL, 10), MAX_SC_PROCS);
719
720 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
721 radv_debug_options);
722
723 /* Disable memory cache when secure compile is set */
724 if (radv_device_use_secure_compile(instance))
725 instance->debug_flags |= RADV_DEBUG_NO_MEMORY_CACHE;
726
727 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
728 radv_perftest_options);
729
730 if (instance->perftest_flags & RADV_PERFTEST_ACO)
731 fprintf(stderr, "WARNING: Experimental compiler backend enabled. Here be dragons! Incorrect rendering, GPU hangs and/or resets are likely\n");
732
733 if (instance->debug_flags & RADV_DEBUG_STARTUP)
734 radv_logi("Created an instance");
735
736 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
737 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
738 int index = radv_get_instance_extension_index(ext_name);
739
740 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
741 vk_free2(&default_alloc, pAllocator, instance);
742 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
743 }
744
745 instance->enabled_extensions.extensions[index] = true;
746 }
747
748 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
749 if (result != VK_SUCCESS) {
750 vk_free2(&default_alloc, pAllocator, instance);
751 return vk_error(instance, result);
752 }
753
754 instance->engineName = vk_strdup(&instance->alloc, engine_name,
755 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
756 instance->engineVersion = engine_version;
757
758 glsl_type_singleton_init_or_ref();
759
760 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
761
762 radv_init_dri_options(instance);
763 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
764
765 *pInstance = radv_instance_to_handle(instance);
766
767 return VK_SUCCESS;
768 }
769
770 void radv_DestroyInstance(
771 VkInstance _instance,
772 const VkAllocationCallbacks* pAllocator)
773 {
774 RADV_FROM_HANDLE(radv_instance, instance, _instance);
775
776 if (!instance)
777 return;
778
779 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
780 radv_physical_device_finish(instance->physicalDevices + i);
781 }
782
783 vk_free(&instance->alloc, instance->engineName);
784
785 VG(VALGRIND_DESTROY_MEMPOOL(instance));
786
787 glsl_type_singleton_decref();
788
789 driDestroyOptionCache(&instance->dri_options);
790 driDestroyOptionInfo(&instance->available_dri_options);
791
792 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
793
794 vk_free(&instance->alloc, instance);
795 }
796
797 static VkResult
798 radv_enumerate_devices(struct radv_instance *instance)
799 {
800 /* TODO: Check for more devices ? */
801 drmDevicePtr devices[8];
802 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
803 int max_devices;
804
805 instance->physicalDeviceCount = 0;
806
807 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
808
809 if (instance->debug_flags & RADV_DEBUG_STARTUP)
810 radv_logi("Found %d drm nodes", max_devices);
811
812 if (max_devices < 1)
813 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
814
815 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
816 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
817 devices[i]->bustype == DRM_BUS_PCI &&
818 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
819
820 result = radv_physical_device_init(instance->physicalDevices +
821 instance->physicalDeviceCount,
822 instance,
823 devices[i]);
824 if (result == VK_SUCCESS)
825 ++instance->physicalDeviceCount;
826 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
827 break;
828 }
829 }
830 drmFreeDevices(devices, max_devices);
831
832 return result;
833 }
834
835 VkResult radv_EnumeratePhysicalDevices(
836 VkInstance _instance,
837 uint32_t* pPhysicalDeviceCount,
838 VkPhysicalDevice* pPhysicalDevices)
839 {
840 RADV_FROM_HANDLE(radv_instance, instance, _instance);
841 VkResult result;
842
843 if (instance->physicalDeviceCount < 0) {
844 result = radv_enumerate_devices(instance);
845 if (result != VK_SUCCESS &&
846 result != VK_ERROR_INCOMPATIBLE_DRIVER)
847 return result;
848 }
849
850 if (!pPhysicalDevices) {
851 *pPhysicalDeviceCount = instance->physicalDeviceCount;
852 } else {
853 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
854 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
855 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
856 }
857
858 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
859 : VK_SUCCESS;
860 }
861
862 VkResult radv_EnumeratePhysicalDeviceGroups(
863 VkInstance _instance,
864 uint32_t* pPhysicalDeviceGroupCount,
865 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
866 {
867 RADV_FROM_HANDLE(radv_instance, instance, _instance);
868 VkResult result;
869
870 if (instance->physicalDeviceCount < 0) {
871 result = radv_enumerate_devices(instance);
872 if (result != VK_SUCCESS &&
873 result != VK_ERROR_INCOMPATIBLE_DRIVER)
874 return result;
875 }
876
877 if (!pPhysicalDeviceGroupProperties) {
878 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
879 } else {
880 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
881 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
882 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
883 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
884 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
885 }
886 }
887 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
888 : VK_SUCCESS;
889 }
890
891 void radv_GetPhysicalDeviceFeatures(
892 VkPhysicalDevice physicalDevice,
893 VkPhysicalDeviceFeatures* pFeatures)
894 {
895 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
896 memset(pFeatures, 0, sizeof(*pFeatures));
897
898 *pFeatures = (VkPhysicalDeviceFeatures) {
899 .robustBufferAccess = true,
900 .fullDrawIndexUint32 = true,
901 .imageCubeArray = true,
902 .independentBlend = true,
903 .geometryShader = true,
904 .tessellationShader = true,
905 .sampleRateShading = true,
906 .dualSrcBlend = true,
907 .logicOp = true,
908 .multiDrawIndirect = true,
909 .drawIndirectFirstInstance = true,
910 .depthClamp = true,
911 .depthBiasClamp = true,
912 .fillModeNonSolid = true,
913 .depthBounds = true,
914 .wideLines = true,
915 .largePoints = true,
916 .alphaToOne = true,
917 .multiViewport = true,
918 .samplerAnisotropy = true,
919 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
920 .textureCompressionASTC_LDR = false,
921 .textureCompressionBC = true,
922 .occlusionQueryPrecise = true,
923 .pipelineStatisticsQuery = true,
924 .vertexPipelineStoresAndAtomics = true,
925 .fragmentStoresAndAtomics = true,
926 .shaderTessellationAndGeometryPointSize = true,
927 .shaderImageGatherExtended = true,
928 .shaderStorageImageExtendedFormats = true,
929 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
930 .shaderUniformBufferArrayDynamicIndexing = true,
931 .shaderSampledImageArrayDynamicIndexing = true,
932 .shaderStorageBufferArrayDynamicIndexing = true,
933 .shaderStorageImageArrayDynamicIndexing = true,
934 .shaderStorageImageReadWithoutFormat = true,
935 .shaderStorageImageWriteWithoutFormat = true,
936 .shaderClipDistance = true,
937 .shaderCullDistance = true,
938 .shaderFloat64 = true,
939 .shaderInt64 = true,
940 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9 && !pdevice->use_aco,
941 .sparseBinding = true,
942 .variableMultisampleRate = true,
943 .inheritedQueries = true,
944 };
945 }
946
947 void radv_GetPhysicalDeviceFeatures2(
948 VkPhysicalDevice physicalDevice,
949 VkPhysicalDeviceFeatures2 *pFeatures)
950 {
951 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
952 vk_foreach_struct(ext, pFeatures->pNext) {
953 switch (ext->sType) {
954 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
955 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
956 features->variablePointersStorageBuffer = true;
957 features->variablePointers = true;
958 break;
959 }
960 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
961 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
962 features->multiview = true;
963 features->multiviewGeometryShader = true;
964 features->multiviewTessellationShader = true;
965 break;
966 }
967 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
968 VkPhysicalDeviceShaderDrawParametersFeatures *features =
969 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
970 features->shaderDrawParameters = true;
971 break;
972 }
973 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
974 VkPhysicalDeviceProtectedMemoryFeatures *features =
975 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
976 features->protectedMemory = false;
977 break;
978 }
979 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
980 VkPhysicalDevice16BitStorageFeatures *features =
981 (VkPhysicalDevice16BitStorageFeatures*)ext;
982 bool enabled = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
983 features->storageBuffer16BitAccess = enabled;
984 features->uniformAndStorageBuffer16BitAccess = enabled;
985 features->storagePushConstant16 = enabled;
986 features->storageInputOutput16 = enabled && LLVM_VERSION_MAJOR >= 9;
987 break;
988 }
989 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
990 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
991 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
992 features->samplerYcbcrConversion = true;
993 break;
994 }
995 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
996 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
997 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
998 features->shaderInputAttachmentArrayDynamicIndexing = true;
999 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
1000 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
1001 features->shaderUniformBufferArrayNonUniformIndexing = true;
1002 features->shaderSampledImageArrayNonUniformIndexing = true;
1003 features->shaderStorageBufferArrayNonUniformIndexing = true;
1004 features->shaderStorageImageArrayNonUniformIndexing = true;
1005 features->shaderInputAttachmentArrayNonUniformIndexing = true;
1006 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
1007 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
1008 features->descriptorBindingUniformBufferUpdateAfterBind = true;
1009 features->descriptorBindingSampledImageUpdateAfterBind = true;
1010 features->descriptorBindingStorageImageUpdateAfterBind = true;
1011 features->descriptorBindingStorageBufferUpdateAfterBind = true;
1012 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
1013 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
1014 features->descriptorBindingUpdateUnusedWhilePending = true;
1015 features->descriptorBindingPartiallyBound = true;
1016 features->descriptorBindingVariableDescriptorCount = true;
1017 features->runtimeDescriptorArray = true;
1018 break;
1019 }
1020 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
1021 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
1022 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
1023 features->conditionalRendering = true;
1024 features->inheritedConditionalRendering = false;
1025 break;
1026 }
1027 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
1028 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
1029 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
1030 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
1031 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
1032 break;
1033 }
1034 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
1035 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
1036 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
1037 features->transformFeedback = true;
1038 features->geometryStreams = !pdevice->use_ngg_streamout;
1039 break;
1040 }
1041 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
1042 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
1043 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
1044 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
1045 break;
1046 }
1047 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
1048 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
1049 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
1050 features->memoryPriority = VK_TRUE;
1051 break;
1052 }
1053 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
1054 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
1055 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
1056 features->bufferDeviceAddress = true;
1057 features->bufferDeviceAddressCaptureReplay = false;
1058 features->bufferDeviceAddressMultiDevice = false;
1059 break;
1060 }
1061 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_KHR: {
1062 VkPhysicalDeviceBufferDeviceAddressFeaturesKHR *features =
1063 (VkPhysicalDeviceBufferDeviceAddressFeaturesKHR *)ext;
1064 features->bufferDeviceAddress = true;
1065 features->bufferDeviceAddressCaptureReplay = false;
1066 features->bufferDeviceAddressMultiDevice = false;
1067 break;
1068 }
1069 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
1070 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
1071 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
1072 features->depthClipEnable = true;
1073 break;
1074 }
1075 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
1076 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
1077 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
1078 features->hostQueryReset = true;
1079 break;
1080 }
1081 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
1082 VkPhysicalDevice8BitStorageFeaturesKHR *features =
1083 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
1084 bool enabled = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
1085 features->storageBuffer8BitAccess = enabled;
1086 features->uniformAndStorageBuffer8BitAccess = enabled;
1087 features->storagePushConstant8 = enabled;
1088 break;
1089 }
1090 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES_KHR: {
1091 VkPhysicalDeviceShaderFloat16Int8FeaturesKHR *features =
1092 (VkPhysicalDeviceShaderFloat16Int8FeaturesKHR*)ext;
1093 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
1094 features->shaderInt8 = !pdevice->use_aco;
1095 break;
1096 }
1097 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
1098 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
1099 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
1100 features->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1101 features->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1102 break;
1103 }
1104 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
1105 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
1106 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
1107 features->shaderDemoteToHelperInvocation = pdevice->use_aco;
1108 break;
1109 }
1110 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
1111 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
1112 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
1113
1114 features->inlineUniformBlock = true;
1115 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1116 break;
1117 }
1118 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1119 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1120 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1121 features->computeDerivativeGroupQuads = false;
1122 features->computeDerivativeGroupLinear = true;
1123 break;
1124 }
1125 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1126 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1127 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1128 features->ycbcrImageArrays = true;
1129 break;
1130 }
1131 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
1132 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
1133 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
1134 features->uniformBufferStandardLayout = true;
1135 break;
1136 }
1137 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1138 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1139 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1140 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1141 break;
1142 }
1143 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES_KHR: {
1144 VkPhysicalDeviceImagelessFramebufferFeaturesKHR *features =
1145 (VkPhysicalDeviceImagelessFramebufferFeaturesKHR *)ext;
1146 features->imagelessFramebuffer = true;
1147 break;
1148 }
1149 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1150 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1151 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1152 features->pipelineExecutableInfo = true;
1153 break;
1154 }
1155 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR: {
1156 VkPhysicalDeviceShaderClockFeaturesKHR *features =
1157 (VkPhysicalDeviceShaderClockFeaturesKHR *)ext;
1158 features->shaderSubgroupClock = true;
1159 features->shaderDeviceClock = false;
1160 break;
1161 }
1162 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
1163 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
1164 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
1165 features->texelBufferAlignment = true;
1166 break;
1167 }
1168 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES_KHR: {
1169 VkPhysicalDeviceTimelineSemaphoreFeaturesKHR *features =
1170 (VkPhysicalDeviceTimelineSemaphoreFeaturesKHR *) ext;
1171 features->timelineSemaphore = true;
1172 break;
1173 }
1174 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT: {
1175 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *features =
1176 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *)ext;
1177 features->subgroupSizeControl = true;
1178 features->computeFullSubgroups = true;
1179 break;
1180 }
1181 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD: {
1182 VkPhysicalDeviceCoherentMemoryFeaturesAMD *features =
1183 (VkPhysicalDeviceCoherentMemoryFeaturesAMD *)ext;
1184 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1185 break;
1186 }
1187 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES_KHR: {
1188 VkPhysicalDeviceShaderSubgroupExtendedTypesFeaturesKHR *features =
1189 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeaturesKHR *)ext;
1190 features->shaderSubgroupExtendedTypes = true;
1191 break;
1192 }
1193 default:
1194 break;
1195 }
1196 }
1197 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1198 }
1199
1200 static size_t
1201 radv_max_descriptor_set_size()
1202 {
1203 /* make sure that the entire descriptor set is addressable with a signed
1204 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1205 * be at most 2 GiB. the combined image & samples object count as one of
1206 * both. This limit is for the pipeline layout, not for the set layout, but
1207 * there is no set limit, so we just set a pipeline limit. I don't think
1208 * any app is going to hit this soon. */
1209 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1210 - MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1211 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1212 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1213 32 /* sampler, largest when combined with image */ +
1214 64 /* sampled image */ +
1215 64 /* storage image */);
1216 }
1217
1218 void radv_GetPhysicalDeviceProperties(
1219 VkPhysicalDevice physicalDevice,
1220 VkPhysicalDeviceProperties* pProperties)
1221 {
1222 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1223 VkSampleCountFlags sample_counts = 0xf;
1224
1225 size_t max_descriptor_set_size = radv_max_descriptor_set_size();
1226
1227 VkPhysicalDeviceLimits limits = {
1228 .maxImageDimension1D = (1 << 14),
1229 .maxImageDimension2D = (1 << 14),
1230 .maxImageDimension3D = (1 << 11),
1231 .maxImageDimensionCube = (1 << 14),
1232 .maxImageArrayLayers = (1 << 11),
1233 .maxTexelBufferElements = 128 * 1024 * 1024,
1234 .maxUniformBufferRange = UINT32_MAX,
1235 .maxStorageBufferRange = UINT32_MAX,
1236 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1237 .maxMemoryAllocationCount = UINT32_MAX,
1238 .maxSamplerAllocationCount = 64 * 1024,
1239 .bufferImageGranularity = 64, /* A cache line */
1240 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1241 .maxBoundDescriptorSets = MAX_SETS,
1242 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1243 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1244 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1245 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1246 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1247 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1248 .maxPerStageResources = max_descriptor_set_size,
1249 .maxDescriptorSetSamplers = max_descriptor_set_size,
1250 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1251 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1252 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1253 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1254 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1255 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1256 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1257 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1258 .maxVertexInputBindings = MAX_VBS,
1259 .maxVertexInputAttributeOffset = 2047,
1260 .maxVertexInputBindingStride = 2048,
1261 .maxVertexOutputComponents = 128,
1262 .maxTessellationGenerationLevel = 64,
1263 .maxTessellationPatchSize = 32,
1264 .maxTessellationControlPerVertexInputComponents = 128,
1265 .maxTessellationControlPerVertexOutputComponents = 128,
1266 .maxTessellationControlPerPatchOutputComponents = 120,
1267 .maxTessellationControlTotalOutputComponents = 4096,
1268 .maxTessellationEvaluationInputComponents = 128,
1269 .maxTessellationEvaluationOutputComponents = 128,
1270 .maxGeometryShaderInvocations = 127,
1271 .maxGeometryInputComponents = 64,
1272 .maxGeometryOutputComponents = 128,
1273 .maxGeometryOutputVertices = 256,
1274 .maxGeometryTotalOutputComponents = 1024,
1275 .maxFragmentInputComponents = 128,
1276 .maxFragmentOutputAttachments = 8,
1277 .maxFragmentDualSrcAttachments = 1,
1278 .maxFragmentCombinedOutputResources = 8,
1279 .maxComputeSharedMemorySize = 32768,
1280 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1281 .maxComputeWorkGroupInvocations = 2048,
1282 .maxComputeWorkGroupSize = {
1283 2048,
1284 2048,
1285 2048
1286 },
1287 .subPixelPrecisionBits = 8,
1288 .subTexelPrecisionBits = 8,
1289 .mipmapPrecisionBits = 8,
1290 .maxDrawIndexedIndexValue = UINT32_MAX,
1291 .maxDrawIndirectCount = UINT32_MAX,
1292 .maxSamplerLodBias = 16,
1293 .maxSamplerAnisotropy = 16,
1294 .maxViewports = MAX_VIEWPORTS,
1295 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1296 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1297 .viewportSubPixelBits = 8,
1298 .minMemoryMapAlignment = 4096, /* A page */
1299 .minTexelBufferOffsetAlignment = 4,
1300 .minUniformBufferOffsetAlignment = 4,
1301 .minStorageBufferOffsetAlignment = 4,
1302 .minTexelOffset = -32,
1303 .maxTexelOffset = 31,
1304 .minTexelGatherOffset = -32,
1305 .maxTexelGatherOffset = 31,
1306 .minInterpolationOffset = -2,
1307 .maxInterpolationOffset = 2,
1308 .subPixelInterpolationOffsetBits = 8,
1309 .maxFramebufferWidth = (1 << 14),
1310 .maxFramebufferHeight = (1 << 14),
1311 .maxFramebufferLayers = (1 << 10),
1312 .framebufferColorSampleCounts = sample_counts,
1313 .framebufferDepthSampleCounts = sample_counts,
1314 .framebufferStencilSampleCounts = sample_counts,
1315 .framebufferNoAttachmentsSampleCounts = sample_counts,
1316 .maxColorAttachments = MAX_RTS,
1317 .sampledImageColorSampleCounts = sample_counts,
1318 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1319 .sampledImageDepthSampleCounts = sample_counts,
1320 .sampledImageStencilSampleCounts = sample_counts,
1321 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1322 .maxSampleMaskWords = 1,
1323 .timestampComputeAndGraphics = true,
1324 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1325 .maxClipDistances = 8,
1326 .maxCullDistances = 8,
1327 .maxCombinedClipAndCullDistances = 8,
1328 .discreteQueuePriorities = 2,
1329 .pointSizeRange = { 0.0, 8192.0 },
1330 .lineWidthRange = { 0.0, 7.9921875 },
1331 .pointSizeGranularity = (1.0 / 8.0),
1332 .lineWidthGranularity = (1.0 / 128.0),
1333 .strictLines = false, /* FINISHME */
1334 .standardSampleLocations = true,
1335 .optimalBufferCopyOffsetAlignment = 128,
1336 .optimalBufferCopyRowPitchAlignment = 128,
1337 .nonCoherentAtomSize = 64,
1338 };
1339
1340 *pProperties = (VkPhysicalDeviceProperties) {
1341 .apiVersion = radv_physical_device_api_version(pdevice),
1342 .driverVersion = vk_get_driver_version(),
1343 .vendorID = ATI_VENDOR_ID,
1344 .deviceID = pdevice->rad_info.pci_id,
1345 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1346 .limits = limits,
1347 .sparseProperties = {0},
1348 };
1349
1350 strcpy(pProperties->deviceName, pdevice->name);
1351 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1352 }
1353
1354 void radv_GetPhysicalDeviceProperties2(
1355 VkPhysicalDevice physicalDevice,
1356 VkPhysicalDeviceProperties2 *pProperties)
1357 {
1358 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1359 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1360
1361 vk_foreach_struct(ext, pProperties->pNext) {
1362 switch (ext->sType) {
1363 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1364 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1365 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1366 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1367 break;
1368 }
1369 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1370 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1371 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1372 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1373 properties->deviceLUIDValid = false;
1374 break;
1375 }
1376 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1377 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1378 properties->maxMultiviewViewCount = MAX_VIEWS;
1379 properties->maxMultiviewInstanceIndex = INT_MAX;
1380 break;
1381 }
1382 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1383 VkPhysicalDevicePointClippingProperties *properties =
1384 (VkPhysicalDevicePointClippingProperties*)ext;
1385 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1386 break;
1387 }
1388 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1389 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1390 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1391 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1392 break;
1393 }
1394 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1395 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1396 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1397 properties->minImportedHostPointerAlignment = 4096;
1398 break;
1399 }
1400 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1401 VkPhysicalDeviceSubgroupProperties *properties =
1402 (VkPhysicalDeviceSubgroupProperties*)ext;
1403 properties->subgroupSize = RADV_SUBGROUP_SIZE;
1404 properties->supportedStages = VK_SHADER_STAGE_ALL;
1405 properties->supportedOperations =
1406 VK_SUBGROUP_FEATURE_BASIC_BIT |
1407 VK_SUBGROUP_FEATURE_VOTE_BIT |
1408 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1409 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1410 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1411 VK_SUBGROUP_FEATURE_QUAD_BIT;
1412 if (pdevice->rad_info.chip_class == GFX8 ||
1413 pdevice->rad_info.chip_class == GFX9) {
1414 properties->supportedOperations |=
1415 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1416 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1417 }
1418 properties->quadOperationsInAllStages = true;
1419 break;
1420 }
1421 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1422 VkPhysicalDeviceMaintenance3Properties *properties =
1423 (VkPhysicalDeviceMaintenance3Properties*)ext;
1424 properties->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
1425 properties->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
1426 break;
1427 }
1428 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1429 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1430 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1431 /* GFX6-8 only support single channel min/max filter. */
1432 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1433 properties->filterMinmaxSingleComponentFormats = true;
1434 break;
1435 }
1436 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1437 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1438 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1439
1440 /* Shader engines. */
1441 properties->shaderEngineCount =
1442 pdevice->rad_info.max_se;
1443 properties->shaderArraysPerEngineCount =
1444 pdevice->rad_info.max_sh_per_se;
1445 properties->computeUnitsPerShaderArray =
1446 pdevice->rad_info.num_good_cu_per_sh;
1447 properties->simdPerComputeUnit = 4;
1448 properties->wavefrontsPerSimd =
1449 pdevice->rad_info.family == CHIP_TONGA ||
1450 pdevice->rad_info.family == CHIP_ICELAND ||
1451 pdevice->rad_info.family == CHIP_POLARIS10 ||
1452 pdevice->rad_info.family == CHIP_POLARIS11 ||
1453 pdevice->rad_info.family == CHIP_POLARIS12 ||
1454 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1455 properties->wavefrontSize = 64;
1456
1457 /* SGPR. */
1458 properties->sgprsPerSimd =
1459 pdevice->rad_info.num_physical_sgprs_per_simd;
1460 properties->minSgprAllocation =
1461 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1462 properties->maxSgprAllocation =
1463 pdevice->rad_info.family == CHIP_TONGA ||
1464 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1465 properties->sgprAllocationGranularity =
1466 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1467
1468 /* VGPR. */
1469 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1470 properties->minVgprAllocation = 4;
1471 properties->maxVgprAllocation = 256;
1472 properties->vgprAllocationGranularity = 4;
1473 break;
1474 }
1475 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1476 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1477 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1478
1479 properties->shaderCoreFeatures = 0;
1480 properties->activeComputeUnitCount =
1481 pdevice->rad_info.num_good_compute_units;
1482 break;
1483 }
1484 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1485 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1486 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1487 properties->maxVertexAttribDivisor = UINT32_MAX;
1488 break;
1489 }
1490 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1491 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1492 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1493 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1494 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1495 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1496 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1497 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1498 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1499 properties->robustBufferAccessUpdateAfterBind = false;
1500 properties->quadDivergentImplicitLod = false;
1501
1502 size_t max_descriptor_set_size = radv_max_descriptor_set_size();
1503 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1504 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1505 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1506 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1507 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1508 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1509 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1510 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1511 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1512 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1513 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1514 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1515 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1516 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1517 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1518 break;
1519 }
1520 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1521 VkPhysicalDeviceProtectedMemoryProperties *properties =
1522 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1523 properties->protectedNoFault = false;
1524 break;
1525 }
1526 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1527 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1528 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1529 properties->primitiveOverestimationSize = 0;
1530 properties->maxExtraPrimitiveOverestimationSize = 0;
1531 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1532 properties->primitiveUnderestimation = VK_FALSE;
1533 properties->conservativePointAndLineRasterization = VK_FALSE;
1534 properties->degenerateTrianglesRasterized = VK_FALSE;
1535 properties->degenerateLinesRasterized = VK_FALSE;
1536 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1537 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1538 break;
1539 }
1540 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1541 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1542 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1543 properties->pciDomain = pdevice->bus_info.domain;
1544 properties->pciBus = pdevice->bus_info.bus;
1545 properties->pciDevice = pdevice->bus_info.dev;
1546 properties->pciFunction = pdevice->bus_info.func;
1547 break;
1548 }
1549 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1550 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1551 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1552
1553 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1554 snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE_KHR, "radv");
1555 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1556 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1557 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1558
1559 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1560 .major = 1,
1561 .minor = 1,
1562 .subminor = 2,
1563 .patch = 0,
1564 };
1565 break;
1566 }
1567 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1568 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1569 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1570 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1571 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1572 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1573 properties->maxTransformFeedbackStreamDataSize = 512;
1574 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1575 properties->maxTransformFeedbackBufferDataStride = 512;
1576 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1577 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1578 properties->transformFeedbackRasterizationStreamSelect = false;
1579 properties->transformFeedbackDraw = true;
1580 break;
1581 }
1582 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1583 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1584 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1585
1586 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1587 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1588 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1589 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1590 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1591 break;
1592 }
1593 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1594 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1595 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1596 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1597 VK_SAMPLE_COUNT_4_BIT |
1598 VK_SAMPLE_COUNT_8_BIT;
1599 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1600 properties->sampleLocationCoordinateRange[0] = 0.0f;
1601 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1602 properties->sampleLocationSubPixelBits = 4;
1603 properties->variableSampleLocations = VK_FALSE;
1604 break;
1605 }
1606 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1607 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1608 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1609
1610 /* We support all of the depth resolve modes */
1611 properties->supportedDepthResolveModes =
1612 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1613 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1614 VK_RESOLVE_MODE_MIN_BIT_KHR |
1615 VK_RESOLVE_MODE_MAX_BIT_KHR;
1616
1617 /* Average doesn't make sense for stencil so we don't support that */
1618 properties->supportedStencilResolveModes =
1619 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1620 VK_RESOLVE_MODE_MIN_BIT_KHR |
1621 VK_RESOLVE_MODE_MAX_BIT_KHR;
1622
1623 properties->independentResolveNone = VK_TRUE;
1624 properties->independentResolve = VK_TRUE;
1625 break;
1626 }
1627 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
1628 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *properties =
1629 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *)ext;
1630 properties->storageTexelBufferOffsetAlignmentBytes = 4;
1631 properties->storageTexelBufferOffsetSingleTexelAlignment = true;
1632 properties->uniformTexelBufferOffsetAlignmentBytes = 4;
1633 properties->uniformTexelBufferOffsetSingleTexelAlignment = true;
1634 break;
1635 }
1636 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES_KHR : {
1637 VkPhysicalDeviceFloatControlsPropertiesKHR *properties =
1638 (VkPhysicalDeviceFloatControlsPropertiesKHR *)ext;
1639
1640 /* On AMD hardware, denormals and rounding modes for
1641 * fp16/fp64 are controlled by the same config
1642 * register.
1643 */
1644 properties->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1645 properties->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1646
1647 /* Do not allow both preserving and flushing denorms
1648 * because different shaders in the same pipeline can
1649 * have different settings and this won't work for
1650 * merged shaders. To make it work, this requires LLVM
1651 * support for changing the register. The same logic
1652 * applies for the rounding modes because they are
1653 * configured with the same config register.
1654 * TODO: we can enable a lot of these for ACO when it
1655 * supports all stages
1656 */
1657 properties->shaderDenormFlushToZeroFloat32 = true;
1658 properties->shaderDenormPreserveFloat32 = false;
1659 properties->shaderRoundingModeRTEFloat32 = true;
1660 properties->shaderRoundingModeRTZFloat32 = false;
1661 properties->shaderSignedZeroInfNanPreserveFloat32 = true;
1662
1663 properties->shaderDenormFlushToZeroFloat16 = false;
1664 properties->shaderDenormPreserveFloat16 = pdevice->rad_info.chip_class >= GFX8;
1665 properties->shaderRoundingModeRTEFloat16 = pdevice->rad_info.chip_class >= GFX8;
1666 properties->shaderRoundingModeRTZFloat16 = false;
1667 properties->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.chip_class >= GFX8;
1668
1669 properties->shaderDenormFlushToZeroFloat64 = false;
1670 properties->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1671 properties->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
1672 properties->shaderRoundingModeRTZFloat64 = false;
1673 properties->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1674 break;
1675 }
1676 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES_KHR: {
1677 VkPhysicalDeviceTimelineSemaphorePropertiesKHR *props =
1678 (VkPhysicalDeviceTimelineSemaphorePropertiesKHR *) ext;
1679 props->maxTimelineSemaphoreValueDifference = UINT64_MAX;
1680 break;
1681 }
1682 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT: {
1683 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *props =
1684 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *)ext;
1685 props->minSubgroupSize = 64;
1686 props->maxSubgroupSize = 64;
1687 props->maxComputeWorkgroupSubgroups = UINT32_MAX;
1688 props->requiredSubgroupSizeStages = 0;
1689
1690 if (pdevice->rad_info.chip_class >= GFX10) {
1691 /* Only GFX10+ supports wave32. */
1692 props->minSubgroupSize = 32;
1693 props->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT;
1694 }
1695 break;
1696 }
1697 default:
1698 break;
1699 }
1700 }
1701 }
1702
1703 static void radv_get_physical_device_queue_family_properties(
1704 struct radv_physical_device* pdevice,
1705 uint32_t* pCount,
1706 VkQueueFamilyProperties** pQueueFamilyProperties)
1707 {
1708 int num_queue_families = 1;
1709 int idx;
1710 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
1711 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1712 num_queue_families++;
1713
1714 if (pQueueFamilyProperties == NULL) {
1715 *pCount = num_queue_families;
1716 return;
1717 }
1718
1719 if (!*pCount)
1720 return;
1721
1722 idx = 0;
1723 if (*pCount >= 1) {
1724 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1725 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1726 VK_QUEUE_COMPUTE_BIT |
1727 VK_QUEUE_TRANSFER_BIT |
1728 VK_QUEUE_SPARSE_BINDING_BIT,
1729 .queueCount = 1,
1730 .timestampValidBits = 64,
1731 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1732 };
1733 idx++;
1734 }
1735
1736 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
1737 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1738 if (*pCount > idx) {
1739 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1740 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1741 VK_QUEUE_TRANSFER_BIT |
1742 VK_QUEUE_SPARSE_BINDING_BIT,
1743 .queueCount = pdevice->rad_info.num_rings[RING_COMPUTE],
1744 .timestampValidBits = 64,
1745 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1746 };
1747 idx++;
1748 }
1749 }
1750 *pCount = idx;
1751 }
1752
1753 void radv_GetPhysicalDeviceQueueFamilyProperties(
1754 VkPhysicalDevice physicalDevice,
1755 uint32_t* pCount,
1756 VkQueueFamilyProperties* pQueueFamilyProperties)
1757 {
1758 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1759 if (!pQueueFamilyProperties) {
1760 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1761 return;
1762 }
1763 VkQueueFamilyProperties *properties[] = {
1764 pQueueFamilyProperties + 0,
1765 pQueueFamilyProperties + 1,
1766 pQueueFamilyProperties + 2,
1767 };
1768 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1769 assert(*pCount <= 3);
1770 }
1771
1772 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1773 VkPhysicalDevice physicalDevice,
1774 uint32_t* pCount,
1775 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1776 {
1777 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1778 if (!pQueueFamilyProperties) {
1779 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1780 return;
1781 }
1782 VkQueueFamilyProperties *properties[] = {
1783 &pQueueFamilyProperties[0].queueFamilyProperties,
1784 &pQueueFamilyProperties[1].queueFamilyProperties,
1785 &pQueueFamilyProperties[2].queueFamilyProperties,
1786 };
1787 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1788 assert(*pCount <= 3);
1789 }
1790
1791 void radv_GetPhysicalDeviceMemoryProperties(
1792 VkPhysicalDevice physicalDevice,
1793 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1794 {
1795 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1796
1797 *pMemoryProperties = physical_device->memory_properties;
1798 }
1799
1800 static void
1801 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1802 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1803 {
1804 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1805 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1806 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1807 uint64_t vram_size = radv_get_vram_size(device);
1808 uint64_t gtt_size = device->rad_info.gart_size;
1809 uint64_t heap_budget, heap_usage;
1810
1811 /* For all memory heaps, the computation of budget is as follow:
1812 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1813 *
1814 * The Vulkan spec 1.1.97 says that the budget should include any
1815 * currently allocated device memory.
1816 *
1817 * Note that the application heap usages are not really accurate (eg.
1818 * in presence of shared buffers).
1819 */
1820 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1821 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1822
1823 if (radv_is_mem_type_vram(device->mem_type_indices[i])) {
1824 heap_usage = device->ws->query_value(device->ws,
1825 RADEON_ALLOCATED_VRAM);
1826
1827 heap_budget = vram_size -
1828 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1829 heap_usage;
1830
1831 memoryBudget->heapBudget[heap_index] = heap_budget;
1832 memoryBudget->heapUsage[heap_index] = heap_usage;
1833 } else if (radv_is_mem_type_vram_visible(device->mem_type_indices[i])) {
1834 heap_usage = device->ws->query_value(device->ws,
1835 RADEON_ALLOCATED_VRAM_VIS);
1836
1837 heap_budget = visible_vram_size -
1838 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1839 heap_usage;
1840
1841 memoryBudget->heapBudget[heap_index] = heap_budget;
1842 memoryBudget->heapUsage[heap_index] = heap_usage;
1843 } else if (radv_is_mem_type_gtt_wc(device->mem_type_indices[i])) {
1844 heap_usage = device->ws->query_value(device->ws,
1845 RADEON_ALLOCATED_GTT);
1846
1847 heap_budget = gtt_size -
1848 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1849 heap_usage;
1850
1851 memoryBudget->heapBudget[heap_index] = heap_budget;
1852 memoryBudget->heapUsage[heap_index] = heap_usage;
1853 }
1854 }
1855
1856 /* The heapBudget and heapUsage values must be zero for array elements
1857 * greater than or equal to
1858 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1859 */
1860 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1861 memoryBudget->heapBudget[i] = 0;
1862 memoryBudget->heapUsage[i] = 0;
1863 }
1864 }
1865
1866 void radv_GetPhysicalDeviceMemoryProperties2(
1867 VkPhysicalDevice physicalDevice,
1868 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1869 {
1870 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1871 &pMemoryProperties->memoryProperties);
1872
1873 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1874 vk_find_struct(pMemoryProperties->pNext,
1875 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1876 if (memory_budget)
1877 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1878 }
1879
1880 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1881 VkDevice _device,
1882 VkExternalMemoryHandleTypeFlagBits handleType,
1883 const void *pHostPointer,
1884 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1885 {
1886 RADV_FROM_HANDLE(radv_device, device, _device);
1887
1888 switch (handleType)
1889 {
1890 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1891 const struct radv_physical_device *physical_device = device->physical_device;
1892 uint32_t memoryTypeBits = 0;
1893 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1894 if (radv_is_mem_type_gtt_cached(physical_device->mem_type_indices[i])) {
1895 memoryTypeBits = (1 << i);
1896 break;
1897 }
1898 }
1899 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1900 return VK_SUCCESS;
1901 }
1902 default:
1903 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1904 }
1905 }
1906
1907 static enum radeon_ctx_priority
1908 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1909 {
1910 /* Default to MEDIUM when a specific global priority isn't requested */
1911 if (!pObj)
1912 return RADEON_CTX_PRIORITY_MEDIUM;
1913
1914 switch(pObj->globalPriority) {
1915 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1916 return RADEON_CTX_PRIORITY_REALTIME;
1917 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1918 return RADEON_CTX_PRIORITY_HIGH;
1919 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1920 return RADEON_CTX_PRIORITY_MEDIUM;
1921 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1922 return RADEON_CTX_PRIORITY_LOW;
1923 default:
1924 unreachable("Illegal global priority value");
1925 return RADEON_CTX_PRIORITY_INVALID;
1926 }
1927 }
1928
1929 static int
1930 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1931 uint32_t queue_family_index, int idx,
1932 VkDeviceQueueCreateFlags flags,
1933 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1934 {
1935 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1936 queue->device = device;
1937 queue->queue_family_index = queue_family_index;
1938 queue->queue_idx = idx;
1939 queue->priority = radv_get_queue_global_priority(global_priority);
1940 queue->flags = flags;
1941
1942 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1943 if (!queue->hw_ctx)
1944 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1945
1946 list_inithead(&queue->pending_submissions);
1947 pthread_mutex_init(&queue->pending_mutex, NULL);
1948
1949 return VK_SUCCESS;
1950 }
1951
1952 static void
1953 radv_queue_finish(struct radv_queue *queue)
1954 {
1955 pthread_mutex_destroy(&queue->pending_mutex);
1956
1957 if (queue->hw_ctx)
1958 queue->device->ws->ctx_destroy(queue->hw_ctx);
1959
1960 if (queue->initial_full_flush_preamble_cs)
1961 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1962 if (queue->initial_preamble_cs)
1963 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1964 if (queue->continue_preamble_cs)
1965 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1966 if (queue->descriptor_bo)
1967 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1968 if (queue->scratch_bo)
1969 queue->device->ws->buffer_destroy(queue->scratch_bo);
1970 if (queue->esgs_ring_bo)
1971 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1972 if (queue->gsvs_ring_bo)
1973 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1974 if (queue->tess_rings_bo)
1975 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1976 if (queue->gds_bo)
1977 queue->device->ws->buffer_destroy(queue->gds_bo);
1978 if (queue->gds_oa_bo)
1979 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
1980 if (queue->compute_scratch_bo)
1981 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1982 }
1983
1984 static void
1985 radv_bo_list_init(struct radv_bo_list *bo_list)
1986 {
1987 pthread_mutex_init(&bo_list->mutex, NULL);
1988 bo_list->list.count = bo_list->capacity = 0;
1989 bo_list->list.bos = NULL;
1990 }
1991
1992 static void
1993 radv_bo_list_finish(struct radv_bo_list *bo_list)
1994 {
1995 free(bo_list->list.bos);
1996 pthread_mutex_destroy(&bo_list->mutex);
1997 }
1998
1999 static VkResult radv_bo_list_add(struct radv_device *device,
2000 struct radeon_winsys_bo *bo)
2001 {
2002 struct radv_bo_list *bo_list = &device->bo_list;
2003
2004 if (bo->is_local)
2005 return VK_SUCCESS;
2006
2007 if (unlikely(!device->use_global_bo_list))
2008 return VK_SUCCESS;
2009
2010 pthread_mutex_lock(&bo_list->mutex);
2011 if (bo_list->list.count == bo_list->capacity) {
2012 unsigned capacity = MAX2(4, bo_list->capacity * 2);
2013 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
2014
2015 if (!data) {
2016 pthread_mutex_unlock(&bo_list->mutex);
2017 return VK_ERROR_OUT_OF_HOST_MEMORY;
2018 }
2019
2020 bo_list->list.bos = (struct radeon_winsys_bo**)data;
2021 bo_list->capacity = capacity;
2022 }
2023
2024 bo_list->list.bos[bo_list->list.count++] = bo;
2025 pthread_mutex_unlock(&bo_list->mutex);
2026 return VK_SUCCESS;
2027 }
2028
2029 static void radv_bo_list_remove(struct radv_device *device,
2030 struct radeon_winsys_bo *bo)
2031 {
2032 struct radv_bo_list *bo_list = &device->bo_list;
2033
2034 if (bo->is_local)
2035 return;
2036
2037 if (unlikely(!device->use_global_bo_list))
2038 return;
2039
2040 pthread_mutex_lock(&bo_list->mutex);
2041 for(unsigned i = 0; i < bo_list->list.count; ++i) {
2042 if (bo_list->list.bos[i] == bo) {
2043 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
2044 --bo_list->list.count;
2045 break;
2046 }
2047 }
2048 pthread_mutex_unlock(&bo_list->mutex);
2049 }
2050
2051 static void
2052 radv_device_init_gs_info(struct radv_device *device)
2053 {
2054 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
2055 device->physical_device->rad_info.family);
2056 }
2057
2058 static int radv_get_device_extension_index(const char *name)
2059 {
2060 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
2061 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
2062 return i;
2063 }
2064 return -1;
2065 }
2066
2067 static int
2068 radv_get_int_debug_option(const char *name, int default_value)
2069 {
2070 const char *str;
2071 int result;
2072
2073 str = getenv(name);
2074 if (!str) {
2075 result = default_value;
2076 } else {
2077 char *endptr;
2078
2079 result = strtol(str, &endptr, 0);
2080 if (str == endptr) {
2081 /* No digits founs. */
2082 result = default_value;
2083 }
2084 }
2085
2086 return result;
2087 }
2088
2089 static int install_seccomp_filter() {
2090
2091 struct sock_filter filter[] = {
2092 /* Check arch is 64bit x86 */
2093 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, arch))),
2094 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, AUDIT_ARCH_X86_64, 0, 12),
2095
2096 /* Futex is required for mutex locks */
2097 #if defined __NR__newselect
2098 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2099 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR__newselect, 11, 0),
2100 #elif defined __NR_select
2101 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2102 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_select, 11, 0),
2103 #else
2104 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2105 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_pselect6, 11, 0),
2106 #endif
2107
2108 /* Allow system exit calls for the forked process */
2109 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2110 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_exit_group, 9, 0),
2111
2112 /* Allow system read calls */
2113 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2114 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_read, 7, 0),
2115
2116 /* Allow system write calls */
2117 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2118 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_write, 5, 0),
2119
2120 /* Allow system brk calls (we need this for malloc) */
2121 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2122 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_brk, 3, 0),
2123
2124 /* Futex is required for mutex locks */
2125 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2126 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_futex, 1, 0),
2127
2128 /* Return error if we hit a system call not on the whitelist */
2129 BPF_STMT(BPF_RET + BPF_K, SECCOMP_RET_ERRNO | (EPERM & SECCOMP_RET_DATA)),
2130
2131 /* Allow whitelisted system calls */
2132 BPF_STMT(BPF_RET + BPF_K, SECCOMP_RET_ALLOW),
2133 };
2134
2135 struct sock_fprog prog = {
2136 .len = (unsigned short)(sizeof(filter) / sizeof(filter[0])),
2137 .filter = filter,
2138 };
2139
2140 if (prctl(PR_SET_NO_NEW_PRIVS, 1, 0, 0, 0))
2141 return -1;
2142
2143 if (prctl(PR_SET_SECCOMP, SECCOMP_MODE_FILTER, &prog))
2144 return -1;
2145
2146 return 0;
2147 }
2148
2149 /* Helper function with timeout support for reading from the pipe between
2150 * processes used for secure compile.
2151 */
2152 bool radv_sc_read(int fd, void *buf, size_t size, bool timeout)
2153 {
2154 fd_set fds;
2155 struct timeval tv;
2156
2157 FD_ZERO(&fds);
2158 FD_SET(fd, &fds);
2159
2160 while (true) {
2161 /* We can't rely on the value of tv after calling select() so
2162 * we must reset it on each iteration of the loop.
2163 */
2164 tv.tv_sec = 5;
2165 tv.tv_usec = 0;
2166
2167 int rval = select(fd + 1, &fds, NULL, NULL, timeout ? &tv : NULL);
2168
2169 if (rval == -1) {
2170 /* select error */
2171 return false;
2172 } else if (rval) {
2173 ssize_t bytes_read = read(fd, buf, size);
2174 if (bytes_read < 0)
2175 return false;
2176
2177 buf += bytes_read;
2178 size -= bytes_read;
2179 if (size == 0)
2180 return true;
2181 } else {
2182 /* select timeout */
2183 return false;
2184 }
2185 }
2186 }
2187
2188 static bool radv_close_all_fds(const int *keep_fds, int keep_fd_count)
2189 {
2190 DIR *d;
2191 struct dirent *dir;
2192 d = opendir("/proc/self/fd");
2193 if (!d)
2194 return false;
2195 int dir_fd = dirfd(d);
2196
2197 while ((dir = readdir(d)) != NULL) {
2198 if (dir->d_name[0] == '.')
2199 continue;
2200
2201 int fd = atoi(dir->d_name);
2202 if (fd == dir_fd)
2203 continue;
2204
2205 bool keep = false;
2206 for (int i = 0; !keep && i < keep_fd_count; ++i)
2207 if (keep_fds[i] == fd)
2208 keep = true;
2209
2210 if (keep)
2211 continue;
2212
2213 close(fd);
2214 }
2215 closedir(d);
2216 return true;
2217 }
2218
2219 static bool secure_compile_open_fifo_fds(struct radv_secure_compile_state *sc,
2220 int *fd_server, int *fd_client,
2221 unsigned process, bool make_fifo)
2222 {
2223 bool result = false;
2224 char *fifo_server_path = NULL;
2225 char *fifo_client_path = NULL;
2226
2227 if (asprintf(&fifo_server_path, "/tmp/radv_server_%s_%u", sc->uid, process) == -1)
2228 goto open_fifo_exit;
2229
2230 if (asprintf(&fifo_client_path, "/tmp/radv_client_%s_%u", sc->uid, process) == -1)
2231 goto open_fifo_exit;
2232
2233 if (make_fifo) {
2234 int file1 = mkfifo(fifo_server_path, 0666);
2235 if(file1 < 0)
2236 goto open_fifo_exit;
2237
2238 int file2 = mkfifo(fifo_client_path, 0666);
2239 if(file2 < 0)
2240 goto open_fifo_exit;
2241 }
2242
2243 *fd_server = open(fifo_server_path, O_RDWR);
2244 if(*fd_server < 1)
2245 goto open_fifo_exit;
2246
2247 *fd_client = open(fifo_client_path, O_RDWR);
2248 if(*fd_client < 1) {
2249 close(*fd_server);
2250 goto open_fifo_exit;
2251 }
2252
2253 result = true;
2254
2255 open_fifo_exit:
2256 free(fifo_server_path);
2257 free(fifo_client_path);
2258
2259 return result;
2260 }
2261
2262 static void run_secure_compile_device(struct radv_device *device, unsigned process,
2263 int fd_idle_device_output)
2264 {
2265 int fd_secure_input;
2266 int fd_secure_output;
2267 bool fifo_result = secure_compile_open_fifo_fds(device->sc_state,
2268 &fd_secure_input,
2269 &fd_secure_output,
2270 process, false);
2271
2272 enum radv_secure_compile_type sc_type;
2273
2274 const int needed_fds[] = {
2275 fd_secure_input,
2276 fd_secure_output,
2277 fd_idle_device_output,
2278 };
2279
2280 if (!fifo_result || !radv_close_all_fds(needed_fds, ARRAY_SIZE(needed_fds)) ||
2281 install_seccomp_filter() == -1) {
2282 sc_type = RADV_SC_TYPE_INIT_FAILURE;
2283 } else {
2284 sc_type = RADV_SC_TYPE_INIT_SUCCESS;
2285 device->sc_state->secure_compile_processes[process].fd_secure_input = fd_secure_input;
2286 device->sc_state->secure_compile_processes[process].fd_secure_output = fd_secure_output;
2287 }
2288
2289 write(fd_idle_device_output, &sc_type, sizeof(sc_type));
2290
2291 if (sc_type == RADV_SC_TYPE_INIT_FAILURE)
2292 goto secure_compile_exit;
2293
2294 while (true) {
2295 radv_sc_read(fd_secure_input, &sc_type, sizeof(sc_type), false);
2296
2297 if (sc_type == RADV_SC_TYPE_COMPILE_PIPELINE) {
2298 struct radv_pipeline *pipeline;
2299 bool sc_read = true;
2300
2301 pipeline = vk_zalloc2(&device->alloc, NULL, sizeof(*pipeline), 8,
2302 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2303
2304 pipeline->device = device;
2305
2306 /* Read pipeline layout */
2307 struct radv_pipeline_layout layout;
2308 sc_read = radv_sc_read(fd_secure_input, &layout, sizeof(struct radv_pipeline_layout), true);
2309 sc_read &= radv_sc_read(fd_secure_input, &layout.num_sets, sizeof(uint32_t), true);
2310 if (!sc_read)
2311 goto secure_compile_exit;
2312
2313 for (uint32_t set = 0; set < layout.num_sets; set++) {
2314 uint32_t layout_size;
2315 sc_read &= radv_sc_read(fd_secure_input, &layout_size, sizeof(uint32_t), true);
2316 if (!sc_read)
2317 goto secure_compile_exit;
2318
2319 layout.set[set].layout = malloc(layout_size);
2320 layout.set[set].layout->layout_size = layout_size;
2321 sc_read &= radv_sc_read(fd_secure_input, layout.set[set].layout,
2322 layout.set[set].layout->layout_size, true);
2323 }
2324
2325 pipeline->layout = &layout;
2326
2327 /* Read pipeline key */
2328 struct radv_pipeline_key key;
2329 sc_read &= radv_sc_read(fd_secure_input, &key, sizeof(struct radv_pipeline_key), true);
2330
2331 /* Read pipeline create flags */
2332 VkPipelineCreateFlags flags;
2333 sc_read &= radv_sc_read(fd_secure_input, &flags, sizeof(VkPipelineCreateFlags), true);
2334
2335 /* Read stage and shader information */
2336 uint32_t num_stages;
2337 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2338 sc_read &= radv_sc_read(fd_secure_input, &num_stages, sizeof(uint32_t), true);
2339 if (!sc_read)
2340 goto secure_compile_exit;
2341
2342 for (uint32_t i = 0; i < num_stages; i++) {
2343
2344 /* Read stage */
2345 gl_shader_stage stage;
2346 sc_read &= radv_sc_read(fd_secure_input, &stage, sizeof(gl_shader_stage), true);
2347
2348 VkPipelineShaderStageCreateInfo *pStage = calloc(1, sizeof(VkPipelineShaderStageCreateInfo));
2349
2350 /* Read entry point name */
2351 size_t name_size;
2352 sc_read &= radv_sc_read(fd_secure_input, &name_size, sizeof(size_t), true);
2353 if (!sc_read)
2354 goto secure_compile_exit;
2355
2356 char *ep_name = malloc(name_size);
2357 sc_read &= radv_sc_read(fd_secure_input, ep_name, name_size, true);
2358 pStage->pName = ep_name;
2359
2360 /* Read shader module */
2361 size_t module_size;
2362 sc_read &= radv_sc_read(fd_secure_input, &module_size, sizeof(size_t), true);
2363 if (!sc_read)
2364 goto secure_compile_exit;
2365
2366 struct radv_shader_module *module = malloc(module_size);
2367 sc_read &= radv_sc_read(fd_secure_input, module, module_size, true);
2368 pStage->module = radv_shader_module_to_handle(module);
2369
2370 /* Read specialization info */
2371 bool has_spec_info;
2372 sc_read &= radv_sc_read(fd_secure_input, &has_spec_info, sizeof(bool), true);
2373 if (!sc_read)
2374 goto secure_compile_exit;
2375
2376 if (has_spec_info) {
2377 VkSpecializationInfo *specInfo = malloc(sizeof(VkSpecializationInfo));
2378 pStage->pSpecializationInfo = specInfo;
2379
2380 sc_read &= radv_sc_read(fd_secure_input, &specInfo->dataSize, sizeof(size_t), true);
2381 if (!sc_read)
2382 goto secure_compile_exit;
2383
2384 void *si_data = malloc(specInfo->dataSize);
2385 sc_read &= radv_sc_read(fd_secure_input, si_data, specInfo->dataSize, true);
2386 specInfo->pData = si_data;
2387
2388 sc_read &= radv_sc_read(fd_secure_input, &specInfo->mapEntryCount, sizeof(uint32_t), true);
2389 if (!sc_read)
2390 goto secure_compile_exit;
2391
2392 VkSpecializationMapEntry *mapEntries = malloc(sizeof(VkSpecializationMapEntry) * specInfo->mapEntryCount);
2393 for (uint32_t j = 0; j < specInfo->mapEntryCount; j++) {
2394 sc_read &= radv_sc_read(fd_secure_input, &mapEntries[j], sizeof(VkSpecializationMapEntry), true);
2395 if (!sc_read)
2396 goto secure_compile_exit;
2397 }
2398
2399 specInfo->pMapEntries = mapEntries;
2400 }
2401
2402 pStages[stage] = pStage;
2403 }
2404
2405 /* Compile the shaders */
2406 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
2407 radv_create_shaders(pipeline, device, NULL, &key, pStages, flags, NULL, stage_feedbacks);
2408
2409 /* free memory allocated above */
2410 for (uint32_t set = 0; set < layout.num_sets; set++)
2411 free(layout.set[set].layout);
2412
2413 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2414 if (!pStages[i])
2415 continue;
2416
2417 free((void *) pStages[i]->pName);
2418 free(radv_shader_module_from_handle(pStages[i]->module));
2419 if (pStages[i]->pSpecializationInfo) {
2420 free((void *) pStages[i]->pSpecializationInfo->pData);
2421 free((void *) pStages[i]->pSpecializationInfo->pMapEntries);
2422 free((void *) pStages[i]->pSpecializationInfo);
2423 }
2424 free((void *) pStages[i]);
2425 }
2426
2427 vk_free(&device->alloc, pipeline);
2428
2429 sc_type = RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED;
2430 write(fd_secure_output, &sc_type, sizeof(sc_type));
2431
2432 } else if (sc_type == RADV_SC_TYPE_DESTROY_DEVICE) {
2433 goto secure_compile_exit;
2434 }
2435 }
2436
2437 secure_compile_exit:
2438 close(fd_secure_input);
2439 close(fd_secure_output);
2440 close(fd_idle_device_output);
2441 _exit(0);
2442 }
2443
2444 static enum radv_secure_compile_type fork_secure_compile_device(struct radv_device *device, unsigned process)
2445 {
2446 int fd_secure_input[2];
2447 int fd_secure_output[2];
2448
2449 /* create pipe descriptors (used to communicate between processes) */
2450 if (pipe(fd_secure_input) == -1 || pipe(fd_secure_output) == -1)
2451 return RADV_SC_TYPE_INIT_FAILURE;
2452
2453
2454 int sc_pid;
2455 if ((sc_pid = fork()) == 0) {
2456 device->sc_state->secure_compile_thread_counter = process;
2457 run_secure_compile_device(device, process, fd_secure_output[1]);
2458 } else {
2459 if (sc_pid == -1)
2460 return RADV_SC_TYPE_INIT_FAILURE;
2461
2462 /* Read the init result returned from the secure process */
2463 enum radv_secure_compile_type sc_type;
2464 bool sc_read = radv_sc_read(fd_secure_output[0], &sc_type, sizeof(sc_type), true);
2465
2466 if (sc_type == RADV_SC_TYPE_INIT_FAILURE || !sc_read) {
2467 close(fd_secure_input[0]);
2468 close(fd_secure_input[1]);
2469 close(fd_secure_output[1]);
2470 close(fd_secure_output[0]);
2471 int status;
2472 waitpid(sc_pid, &status, 0);
2473
2474 return RADV_SC_TYPE_INIT_FAILURE;
2475 } else {
2476 assert(sc_type == RADV_SC_TYPE_INIT_SUCCESS);
2477 write(device->sc_state->secure_compile_processes[process].fd_secure_output, &sc_type, sizeof(sc_type));
2478
2479 close(fd_secure_input[0]);
2480 close(fd_secure_input[1]);
2481 close(fd_secure_output[1]);
2482 close(fd_secure_output[0]);
2483
2484 int status;
2485 waitpid(sc_pid, &status, 0);
2486 }
2487 }
2488
2489 return RADV_SC_TYPE_INIT_SUCCESS;
2490 }
2491
2492 /* Run a bare bones fork of a device that was forked right after its creation.
2493 * This device will have low overhead when it is forked again before each
2494 * pipeline compilation. This device sits idle and its only job is to fork
2495 * itself.
2496 */
2497 static void run_secure_compile_idle_device(struct radv_device *device, unsigned process,
2498 int fd_secure_input, int fd_secure_output)
2499 {
2500 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_INIT_SUCCESS;
2501 device->sc_state->secure_compile_processes[process].fd_secure_input = fd_secure_input;
2502 device->sc_state->secure_compile_processes[process].fd_secure_output = fd_secure_output;
2503
2504 write(fd_secure_output, &sc_type, sizeof(sc_type));
2505
2506 while (true) {
2507 radv_sc_read(fd_secure_input, &sc_type, sizeof(sc_type), false);
2508
2509 if (sc_type == RADV_SC_TYPE_FORK_DEVICE) {
2510 sc_type = fork_secure_compile_device(device, process);
2511
2512 if (sc_type == RADV_SC_TYPE_INIT_FAILURE)
2513 goto secure_compile_exit;
2514
2515 } else if (sc_type == RADV_SC_TYPE_DESTROY_DEVICE) {
2516 goto secure_compile_exit;
2517 }
2518 }
2519
2520 secure_compile_exit:
2521 close(fd_secure_input);
2522 close(fd_secure_output);
2523 _exit(0);
2524 }
2525
2526 static void destroy_secure_compile_device(struct radv_device *device, unsigned process)
2527 {
2528 int fd_secure_input = device->sc_state->secure_compile_processes[process].fd_secure_input;
2529
2530 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_DESTROY_DEVICE;
2531 write(fd_secure_input, &sc_type, sizeof(sc_type));
2532
2533 close(device->sc_state->secure_compile_processes[process].fd_secure_input);
2534 close(device->sc_state->secure_compile_processes[process].fd_secure_output);
2535
2536 int status;
2537 waitpid(device->sc_state->secure_compile_processes[process].sc_pid, &status, 0);
2538 }
2539
2540 static VkResult fork_secure_compile_idle_device(struct radv_device *device)
2541 {
2542 device->sc_state = vk_zalloc(&device->alloc,
2543 sizeof(struct radv_secure_compile_state),
2544 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2545
2546 mtx_init(&device->sc_state->secure_compile_mutex, mtx_plain);
2547
2548 pid_t upid = getpid();
2549 time_t seconds = time(NULL);
2550
2551 char *uid;
2552 if (asprintf(&uid, "%ld_%ld", (long) upid, (long) seconds) == -1)
2553 return VK_ERROR_INITIALIZATION_FAILED;
2554
2555 device->sc_state->uid = uid;
2556
2557 uint8_t sc_threads = device->instance->num_sc_threads;
2558 int fd_secure_input[MAX_SC_PROCS][2];
2559 int fd_secure_output[MAX_SC_PROCS][2];
2560
2561 /* create pipe descriptors (used to communicate between processes) */
2562 for (unsigned i = 0; i < sc_threads; i++) {
2563 if (pipe(fd_secure_input[i]) == -1 ||
2564 pipe(fd_secure_output[i]) == -1) {
2565 return VK_ERROR_INITIALIZATION_FAILED;
2566 }
2567 }
2568
2569 device->sc_state->secure_compile_processes = vk_zalloc(&device->alloc,
2570 sizeof(struct radv_secure_compile_process) * sc_threads, 8,
2571 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2572
2573 for (unsigned process = 0; process < sc_threads; process++) {
2574 if ((device->sc_state->secure_compile_processes[process].sc_pid = fork()) == 0) {
2575 device->sc_state->secure_compile_thread_counter = process;
2576 run_secure_compile_idle_device(device, process, fd_secure_input[process][0], fd_secure_output[process][1]);
2577 } else {
2578 if (device->sc_state->secure_compile_processes[process].sc_pid == -1)
2579 return VK_ERROR_INITIALIZATION_FAILED;
2580
2581 /* Read the init result returned from the secure process */
2582 enum radv_secure_compile_type sc_type;
2583 bool sc_read = radv_sc_read(fd_secure_output[process][0], &sc_type, sizeof(sc_type), true);
2584
2585 bool fifo_result;
2586 if (sc_read && sc_type == RADV_SC_TYPE_INIT_SUCCESS) {
2587 fifo_result = secure_compile_open_fifo_fds(device->sc_state,
2588 &device->sc_state->secure_compile_processes[process].fd_server,
2589 &device->sc_state->secure_compile_processes[process].fd_client,
2590 process, true);
2591
2592 device->sc_state->secure_compile_processes[process].fd_secure_input = fd_secure_input[process][1];
2593 device->sc_state->secure_compile_processes[process].fd_secure_output = fd_secure_output[process][0];
2594 }
2595
2596 if (sc_type == RADV_SC_TYPE_INIT_FAILURE || !sc_read || !fifo_result) {
2597 close(fd_secure_input[process][0]);
2598 close(fd_secure_input[process][1]);
2599 close(fd_secure_output[process][1]);
2600 close(fd_secure_output[process][0]);
2601 int status;
2602 waitpid(device->sc_state->secure_compile_processes[process].sc_pid, &status, 0);
2603
2604 /* Destroy any forks that were created sucessfully */
2605 for (unsigned i = 0; i < process; i++) {
2606 destroy_secure_compile_device(device, i);
2607 }
2608
2609 return VK_ERROR_INITIALIZATION_FAILED;
2610 }
2611 }
2612 }
2613 return VK_SUCCESS;
2614 }
2615
2616 static VkResult
2617 radv_create_pthread_cond(pthread_cond_t *cond)
2618 {
2619 pthread_condattr_t condattr;
2620 if (pthread_condattr_init(&condattr)) {
2621 return VK_ERROR_INITIALIZATION_FAILED;
2622 }
2623
2624 if (pthread_condattr_setclock(&condattr, CLOCK_MONOTONIC)) {
2625 pthread_condattr_destroy(&condattr);
2626 return VK_ERROR_INITIALIZATION_FAILED;
2627 }
2628 if (pthread_cond_init(cond, &condattr)) {
2629 pthread_condattr_destroy(&condattr);
2630 return VK_ERROR_INITIALIZATION_FAILED;
2631 }
2632 pthread_condattr_destroy(&condattr);
2633 return VK_SUCCESS;
2634 }
2635
2636 VkResult radv_CreateDevice(
2637 VkPhysicalDevice physicalDevice,
2638 const VkDeviceCreateInfo* pCreateInfo,
2639 const VkAllocationCallbacks* pAllocator,
2640 VkDevice* pDevice)
2641 {
2642 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2643 VkResult result;
2644 struct radv_device *device;
2645
2646 bool keep_shader_info = false;
2647
2648 /* Check enabled features */
2649 if (pCreateInfo->pEnabledFeatures) {
2650 VkPhysicalDeviceFeatures supported_features;
2651 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
2652 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
2653 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
2654 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
2655 for (uint32_t i = 0; i < num_features; i++) {
2656 if (enabled_feature[i] && !supported_feature[i])
2657 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
2658 }
2659 }
2660
2661 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
2662 sizeof(*device), 8,
2663 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2664 if (!device)
2665 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2666
2667 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2668 device->instance = physical_device->instance;
2669 device->physical_device = physical_device;
2670
2671 device->ws = physical_device->ws;
2672 if (pAllocator)
2673 device->alloc = *pAllocator;
2674 else
2675 device->alloc = physical_device->instance->alloc;
2676
2677 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
2678 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
2679 int index = radv_get_device_extension_index(ext_name);
2680 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
2681 vk_free(&device->alloc, device);
2682 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
2683 }
2684
2685 device->enabled_extensions.extensions[index] = true;
2686 }
2687
2688 keep_shader_info = device->enabled_extensions.AMD_shader_info;
2689
2690 /* With update after bind we can't attach bo's to the command buffer
2691 * from the descriptor set anymore, so we have to use a global BO list.
2692 */
2693 device->use_global_bo_list =
2694 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
2695 device->enabled_extensions.EXT_descriptor_indexing ||
2696 device->enabled_extensions.EXT_buffer_device_address ||
2697 device->enabled_extensions.KHR_buffer_device_address;
2698
2699 device->robust_buffer_access = pCreateInfo->pEnabledFeatures &&
2700 pCreateInfo->pEnabledFeatures->robustBufferAccess;
2701
2702 mtx_init(&device->shader_slab_mutex, mtx_plain);
2703 list_inithead(&device->shader_slabs);
2704
2705 radv_bo_list_init(&device->bo_list);
2706
2707 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
2708 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
2709 uint32_t qfi = queue_create->queueFamilyIndex;
2710 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
2711 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
2712
2713 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
2714
2715 device->queues[qfi] = vk_alloc(&device->alloc,
2716 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2717 if (!device->queues[qfi]) {
2718 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2719 goto fail;
2720 }
2721
2722 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
2723
2724 device->queue_count[qfi] = queue_create->queueCount;
2725
2726 for (unsigned q = 0; q < queue_create->queueCount; q++) {
2727 result = radv_queue_init(device, &device->queues[qfi][q],
2728 qfi, q, queue_create->flags,
2729 global_priority);
2730 if (result != VK_SUCCESS)
2731 goto fail;
2732 }
2733 }
2734
2735 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
2736 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
2737
2738 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2739 device->dfsm_allowed = device->pbb_allowed &&
2740 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
2741
2742 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
2743
2744 /* The maximum number of scratch waves. Scratch space isn't divided
2745 * evenly between CUs. The number is only a function of the number of CUs.
2746 * We can decrease the constant to decrease the scratch buffer size.
2747 *
2748 * sctx->scratch_waves must be >= the maximum possible size of
2749 * 1 threadgroup, so that the hw doesn't hang from being unable
2750 * to start any.
2751 *
2752 * The recommended value is 4 per CU at most. Higher numbers don't
2753 * bring much benefit, but they still occupy chip resources (think
2754 * async compute). I've seen ~2% performance difference between 4 and 32.
2755 */
2756 uint32_t max_threads_per_block = 2048;
2757 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
2758 max_threads_per_block / 64);
2759
2760 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
2761
2762 if (device->physical_device->rad_info.chip_class >= GFX7) {
2763 /* If the KMD allows it (there is a KMD hw register for it),
2764 * allow launching waves out-of-order.
2765 */
2766 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
2767 }
2768
2769 radv_device_init_gs_info(device);
2770
2771 device->tess_offchip_block_dw_size =
2772 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2773
2774 if (getenv("RADV_TRACE_FILE")) {
2775 const char *filename = getenv("RADV_TRACE_FILE");
2776
2777 keep_shader_info = true;
2778
2779 if (!radv_init_trace(device))
2780 goto fail;
2781
2782 fprintf(stderr, "*****************************************************************************\n");
2783 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2784 fprintf(stderr, "*****************************************************************************\n");
2785
2786 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2787 radv_dump_enabled_options(device, stderr);
2788 }
2789
2790 /* Temporarily disable secure compile while we create meta shaders, etc */
2791 uint8_t sc_threads = device->instance->num_sc_threads;
2792 if (sc_threads)
2793 device->instance->num_sc_threads = 0;
2794
2795 device->keep_shader_info = keep_shader_info;
2796 result = radv_device_init_meta(device);
2797 if (result != VK_SUCCESS)
2798 goto fail;
2799
2800 radv_device_init_msaa(device);
2801
2802 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2803 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2804 switch (family) {
2805 case RADV_QUEUE_GENERAL:
2806 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2807 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
2808 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
2809 break;
2810 case RADV_QUEUE_COMPUTE:
2811 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2812 radeon_emit(device->empty_cs[family], 0);
2813 break;
2814 }
2815 device->ws->cs_finalize(device->empty_cs[family]);
2816 }
2817
2818 if (device->physical_device->rad_info.chip_class >= GFX7)
2819 cik_create_gfx_config(device);
2820
2821 VkPipelineCacheCreateInfo ci;
2822 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2823 ci.pNext = NULL;
2824 ci.flags = 0;
2825 ci.pInitialData = NULL;
2826 ci.initialDataSize = 0;
2827 VkPipelineCache pc;
2828 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2829 &ci, NULL, &pc);
2830 if (result != VK_SUCCESS)
2831 goto fail_meta;
2832
2833 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2834
2835 result = radv_create_pthread_cond(&device->timeline_cond);
2836 if (result != VK_SUCCESS)
2837 goto fail_mem_cache;
2838
2839 device->force_aniso =
2840 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2841 if (device->force_aniso >= 0) {
2842 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2843 1 << util_logbase2(device->force_aniso));
2844 }
2845
2846 /* Fork device for secure compile as required */
2847 device->instance->num_sc_threads = sc_threads;
2848 if (radv_device_use_secure_compile(device->instance)) {
2849
2850 result = fork_secure_compile_idle_device(device);
2851 if (result != VK_SUCCESS)
2852 goto fail_meta;
2853 }
2854
2855 *pDevice = radv_device_to_handle(device);
2856 return VK_SUCCESS;
2857
2858 fail_mem_cache:
2859 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2860 fail_meta:
2861 radv_device_finish_meta(device);
2862 fail:
2863 radv_bo_list_finish(&device->bo_list);
2864
2865 if (device->trace_bo)
2866 device->ws->buffer_destroy(device->trace_bo);
2867
2868 if (device->gfx_init)
2869 device->ws->buffer_destroy(device->gfx_init);
2870
2871 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2872 for (unsigned q = 0; q < device->queue_count[i]; q++)
2873 radv_queue_finish(&device->queues[i][q]);
2874 if (device->queue_count[i])
2875 vk_free(&device->alloc, device->queues[i]);
2876 }
2877
2878 vk_free(&device->alloc, device);
2879 return result;
2880 }
2881
2882 void radv_DestroyDevice(
2883 VkDevice _device,
2884 const VkAllocationCallbacks* pAllocator)
2885 {
2886 RADV_FROM_HANDLE(radv_device, device, _device);
2887
2888 if (!device)
2889 return;
2890
2891 if (device->trace_bo)
2892 device->ws->buffer_destroy(device->trace_bo);
2893
2894 if (device->gfx_init)
2895 device->ws->buffer_destroy(device->gfx_init);
2896
2897 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2898 for (unsigned q = 0; q < device->queue_count[i]; q++)
2899 radv_queue_finish(&device->queues[i][q]);
2900 if (device->queue_count[i])
2901 vk_free(&device->alloc, device->queues[i]);
2902 if (device->empty_cs[i])
2903 device->ws->cs_destroy(device->empty_cs[i]);
2904 }
2905 radv_device_finish_meta(device);
2906
2907 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2908 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2909
2910 radv_destroy_shader_slabs(device);
2911
2912 pthread_cond_destroy(&device->timeline_cond);
2913 radv_bo_list_finish(&device->bo_list);
2914 if (radv_device_use_secure_compile(device->instance)) {
2915 for (unsigned i = 0; i < device->instance->num_sc_threads; i++ ) {
2916 destroy_secure_compile_device(device, i);
2917 }
2918 }
2919
2920 if (device->sc_state) {
2921 free(device->sc_state->uid);
2922 vk_free(&device->alloc, device->sc_state->secure_compile_processes);
2923 }
2924 vk_free(&device->alloc, device->sc_state);
2925 vk_free(&device->alloc, device);
2926 }
2927
2928 VkResult radv_EnumerateInstanceLayerProperties(
2929 uint32_t* pPropertyCount,
2930 VkLayerProperties* pProperties)
2931 {
2932 if (pProperties == NULL) {
2933 *pPropertyCount = 0;
2934 return VK_SUCCESS;
2935 }
2936
2937 /* None supported at this time */
2938 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2939 }
2940
2941 VkResult radv_EnumerateDeviceLayerProperties(
2942 VkPhysicalDevice physicalDevice,
2943 uint32_t* pPropertyCount,
2944 VkLayerProperties* pProperties)
2945 {
2946 if (pProperties == NULL) {
2947 *pPropertyCount = 0;
2948 return VK_SUCCESS;
2949 }
2950
2951 /* None supported at this time */
2952 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2953 }
2954
2955 void radv_GetDeviceQueue2(
2956 VkDevice _device,
2957 const VkDeviceQueueInfo2* pQueueInfo,
2958 VkQueue* pQueue)
2959 {
2960 RADV_FROM_HANDLE(radv_device, device, _device);
2961 struct radv_queue *queue;
2962
2963 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2964 if (pQueueInfo->flags != queue->flags) {
2965 /* From the Vulkan 1.1.70 spec:
2966 *
2967 * "The queue returned by vkGetDeviceQueue2 must have the same
2968 * flags value from this structure as that used at device
2969 * creation time in a VkDeviceQueueCreateInfo instance. If no
2970 * matching flags were specified at device creation time then
2971 * pQueue will return VK_NULL_HANDLE."
2972 */
2973 *pQueue = VK_NULL_HANDLE;
2974 return;
2975 }
2976
2977 *pQueue = radv_queue_to_handle(queue);
2978 }
2979
2980 void radv_GetDeviceQueue(
2981 VkDevice _device,
2982 uint32_t queueFamilyIndex,
2983 uint32_t queueIndex,
2984 VkQueue* pQueue)
2985 {
2986 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2987 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2988 .queueFamilyIndex = queueFamilyIndex,
2989 .queueIndex = queueIndex
2990 };
2991
2992 radv_GetDeviceQueue2(_device, &info, pQueue);
2993 }
2994
2995 static void
2996 fill_geom_tess_rings(struct radv_queue *queue,
2997 uint32_t *map,
2998 bool add_sample_positions,
2999 uint32_t esgs_ring_size,
3000 struct radeon_winsys_bo *esgs_ring_bo,
3001 uint32_t gsvs_ring_size,
3002 struct radeon_winsys_bo *gsvs_ring_bo,
3003 uint32_t tess_factor_ring_size,
3004 uint32_t tess_offchip_ring_offset,
3005 uint32_t tess_offchip_ring_size,
3006 struct radeon_winsys_bo *tess_rings_bo)
3007 {
3008 uint32_t *desc = &map[4];
3009
3010 if (esgs_ring_bo) {
3011 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
3012
3013 /* stride 0, num records - size, add tid, swizzle, elsize4,
3014 index stride 64 */
3015 desc[0] = esgs_va;
3016 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
3017 S_008F04_SWIZZLE_ENABLE(true);
3018 desc[2] = esgs_ring_size;
3019 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3020 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3021 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3022 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3023 S_008F0C_INDEX_STRIDE(3) |
3024 S_008F0C_ADD_TID_ENABLE(1);
3025
3026 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3027 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3028 S_008F0C_OOB_SELECT(2) |
3029 S_008F0C_RESOURCE_LEVEL(1);
3030 } else {
3031 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3032 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3033 S_008F0C_ELEMENT_SIZE(1);
3034 }
3035
3036 /* GS entry for ES->GS ring */
3037 /* stride 0, num records - size, elsize0,
3038 index stride 0 */
3039 desc[4] = esgs_va;
3040 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
3041 desc[6] = esgs_ring_size;
3042 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3043 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3044 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3045 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3046
3047 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3048 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3049 S_008F0C_OOB_SELECT(2) |
3050 S_008F0C_RESOURCE_LEVEL(1);
3051 } else {
3052 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3053 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3054 }
3055 }
3056
3057 desc += 8;
3058
3059 if (gsvs_ring_bo) {
3060 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
3061
3062 /* VS entry for GS->VS ring */
3063 /* stride 0, num records - size, elsize0,
3064 index stride 0 */
3065 desc[0] = gsvs_va;
3066 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
3067 desc[2] = gsvs_ring_size;
3068 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3069 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3070 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3071 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3072
3073 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3074 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3075 S_008F0C_OOB_SELECT(2) |
3076 S_008F0C_RESOURCE_LEVEL(1);
3077 } else {
3078 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3079 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3080 }
3081
3082 /* stride gsvs_itemsize, num records 64
3083 elsize 4, index stride 16 */
3084 /* shader will patch stride and desc[2] */
3085 desc[4] = gsvs_va;
3086 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
3087 S_008F04_SWIZZLE_ENABLE(1);
3088 desc[6] = 0;
3089 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3090 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3091 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3092 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3093 S_008F0C_INDEX_STRIDE(1) |
3094 S_008F0C_ADD_TID_ENABLE(true);
3095
3096 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3097 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3098 S_008F0C_OOB_SELECT(2) |
3099 S_008F0C_RESOURCE_LEVEL(1);
3100 } else {
3101 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3102 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3103 S_008F0C_ELEMENT_SIZE(1);
3104 }
3105
3106 }
3107
3108 desc += 8;
3109
3110 if (tess_rings_bo) {
3111 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
3112 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
3113
3114 desc[0] = tess_va;
3115 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
3116 desc[2] = tess_factor_ring_size;
3117 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3118 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3119 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3120 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3121
3122 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3123 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3124 S_008F0C_OOB_SELECT(3) |
3125 S_008F0C_RESOURCE_LEVEL(1);
3126 } else {
3127 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3128 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3129 }
3130
3131 desc[4] = tess_offchip_va;
3132 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
3133 desc[6] = tess_offchip_ring_size;
3134 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3135 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3136 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3137 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3138
3139 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3140 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3141 S_008F0C_OOB_SELECT(3) |
3142 S_008F0C_RESOURCE_LEVEL(1);
3143 } else {
3144 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3145 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3146 }
3147 }
3148
3149 desc += 8;
3150
3151 if (add_sample_positions) {
3152 /* add sample positions after all rings */
3153 memcpy(desc, queue->device->sample_locations_1x, 8);
3154 desc += 2;
3155 memcpy(desc, queue->device->sample_locations_2x, 16);
3156 desc += 4;
3157 memcpy(desc, queue->device->sample_locations_4x, 32);
3158 desc += 8;
3159 memcpy(desc, queue->device->sample_locations_8x, 64);
3160 }
3161 }
3162
3163 static unsigned
3164 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
3165 {
3166 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
3167 device->physical_device->rad_info.family != CHIP_CARRIZO &&
3168 device->physical_device->rad_info.family != CHIP_STONEY;
3169 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
3170 unsigned max_offchip_buffers;
3171 unsigned offchip_granularity;
3172 unsigned hs_offchip_param;
3173
3174 /*
3175 * Per RadeonSI:
3176 * This must be one less than the maximum number due to a hw limitation.
3177 * Various hardware bugs need thGFX7
3178 *
3179 * Per AMDVLK:
3180 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3181 * Gfx7 should limit max_offchip_buffers to 508
3182 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3183 *
3184 * Follow AMDVLK here.
3185 */
3186 if (device->physical_device->rad_info.chip_class >= GFX10) {
3187 max_offchip_buffers_per_se = 256;
3188 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
3189 device->physical_device->rad_info.chip_class == GFX7 ||
3190 device->physical_device->rad_info.chip_class == GFX6)
3191 --max_offchip_buffers_per_se;
3192
3193 max_offchip_buffers = max_offchip_buffers_per_se *
3194 device->physical_device->rad_info.max_se;
3195
3196 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3197 * around by setting 4K granularity.
3198 */
3199 if (device->tess_offchip_block_dw_size == 4096) {
3200 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
3201 offchip_granularity = V_03093C_X_4K_DWORDS;
3202 } else {
3203 assert(device->tess_offchip_block_dw_size == 8192);
3204 offchip_granularity = V_03093C_X_8K_DWORDS;
3205 }
3206
3207 switch (device->physical_device->rad_info.chip_class) {
3208 case GFX6:
3209 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
3210 break;
3211 case GFX7:
3212 case GFX8:
3213 case GFX9:
3214 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
3215 break;
3216 case GFX10:
3217 break;
3218 default:
3219 break;
3220 }
3221
3222 *max_offchip_buffers_p = max_offchip_buffers;
3223 if (device->physical_device->rad_info.chip_class >= GFX7) {
3224 if (device->physical_device->rad_info.chip_class >= GFX8)
3225 --max_offchip_buffers;
3226 hs_offchip_param =
3227 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
3228 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
3229 } else {
3230 hs_offchip_param =
3231 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
3232 }
3233 return hs_offchip_param;
3234 }
3235
3236 static void
3237 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3238 struct radeon_winsys_bo *esgs_ring_bo,
3239 uint32_t esgs_ring_size,
3240 struct radeon_winsys_bo *gsvs_ring_bo,
3241 uint32_t gsvs_ring_size)
3242 {
3243 if (!esgs_ring_bo && !gsvs_ring_bo)
3244 return;
3245
3246 if (esgs_ring_bo)
3247 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
3248
3249 if (gsvs_ring_bo)
3250 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
3251
3252 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3253 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
3254 radeon_emit(cs, esgs_ring_size >> 8);
3255 radeon_emit(cs, gsvs_ring_size >> 8);
3256 } else {
3257 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
3258 radeon_emit(cs, esgs_ring_size >> 8);
3259 radeon_emit(cs, gsvs_ring_size >> 8);
3260 }
3261 }
3262
3263 static void
3264 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3265 unsigned hs_offchip_param, unsigned tf_ring_size,
3266 struct radeon_winsys_bo *tess_rings_bo)
3267 {
3268 uint64_t tf_va;
3269
3270 if (!tess_rings_bo)
3271 return;
3272
3273 tf_va = radv_buffer_get_va(tess_rings_bo);
3274
3275 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
3276
3277 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3278 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
3279 S_030938_SIZE(tf_ring_size / 4));
3280 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
3281 tf_va >> 8);
3282
3283 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3284 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3285 S_030984_BASE_HI(tf_va >> 40));
3286 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3287 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
3288 S_030944_BASE_HI(tf_va >> 40));
3289 }
3290 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
3291 hs_offchip_param);
3292 } else {
3293 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
3294 S_008988_SIZE(tf_ring_size / 4));
3295 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
3296 tf_va >> 8);
3297 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3298 hs_offchip_param);
3299 }
3300 }
3301
3302 static void
3303 radv_emit_graphics_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3304 uint32_t size_per_wave, uint32_t waves,
3305 struct radeon_winsys_bo *scratch_bo)
3306 {
3307 if (queue->queue_family_index != RADV_QUEUE_GENERAL)
3308 return;
3309
3310 if (!scratch_bo)
3311 return;
3312
3313 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3314
3315 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3316 S_0286E8_WAVES(waves) |
3317 S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3318 }
3319
3320 static void
3321 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3322 uint32_t size_per_wave, uint32_t waves,
3323 struct radeon_winsys_bo *compute_scratch_bo)
3324 {
3325 uint64_t scratch_va;
3326
3327 if (!compute_scratch_bo)
3328 return;
3329
3330 scratch_va = radv_buffer_get_va(compute_scratch_bo);
3331
3332 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
3333
3334 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
3335 radeon_emit(cs, scratch_va);
3336 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3337 S_008F04_SWIZZLE_ENABLE(1));
3338
3339 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
3340 S_00B860_WAVES(waves) |
3341 S_00B860_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3342 }
3343
3344 static void
3345 radv_emit_global_shader_pointers(struct radv_queue *queue,
3346 struct radeon_cmdbuf *cs,
3347 struct radeon_winsys_bo *descriptor_bo)
3348 {
3349 uint64_t va;
3350
3351 if (!descriptor_bo)
3352 return;
3353
3354 va = radv_buffer_get_va(descriptor_bo);
3355
3356 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
3357
3358 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3359 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3360 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3361 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3362 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3363
3364 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3365 radv_emit_shader_pointer(queue->device, cs, regs[i],
3366 va, true);
3367 }
3368 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3369 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3370 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3371 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3372 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3373
3374 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3375 radv_emit_shader_pointer(queue->device, cs, regs[i],
3376 va, true);
3377 }
3378 } else {
3379 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3380 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3381 R_00B230_SPI_SHADER_USER_DATA_GS_0,
3382 R_00B330_SPI_SHADER_USER_DATA_ES_0,
3383 R_00B430_SPI_SHADER_USER_DATA_HS_0,
3384 R_00B530_SPI_SHADER_USER_DATA_LS_0};
3385
3386 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3387 radv_emit_shader_pointer(queue->device, cs, regs[i],
3388 va, true);
3389 }
3390 }
3391 }
3392
3393 static void
3394 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3395 {
3396 struct radv_device *device = queue->device;
3397
3398 if (device->gfx_init) {
3399 uint64_t va = radv_buffer_get_va(device->gfx_init);
3400
3401 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
3402 radeon_emit(cs, va);
3403 radeon_emit(cs, va >> 32);
3404 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
3405
3406 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
3407 } else {
3408 struct radv_physical_device *physical_device = device->physical_device;
3409 si_emit_graphics(physical_device, cs);
3410 }
3411 }
3412
3413 static void
3414 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3415 {
3416 struct radv_physical_device *physical_device = queue->device->physical_device;
3417 si_emit_compute(physical_device, cs);
3418 }
3419
3420 static VkResult
3421 radv_get_preamble_cs(struct radv_queue *queue,
3422 uint32_t scratch_size_per_wave,
3423 uint32_t scratch_waves,
3424 uint32_t compute_scratch_size_per_wave,
3425 uint32_t compute_scratch_waves,
3426 uint32_t esgs_ring_size,
3427 uint32_t gsvs_ring_size,
3428 bool needs_tess_rings,
3429 bool needs_gds,
3430 bool needs_sample_positions,
3431 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
3432 struct radeon_cmdbuf **initial_preamble_cs,
3433 struct radeon_cmdbuf **continue_preamble_cs)
3434 {
3435 struct radeon_winsys_bo *scratch_bo = NULL;
3436 struct radeon_winsys_bo *descriptor_bo = NULL;
3437 struct radeon_winsys_bo *compute_scratch_bo = NULL;
3438 struct radeon_winsys_bo *esgs_ring_bo = NULL;
3439 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
3440 struct radeon_winsys_bo *tess_rings_bo = NULL;
3441 struct radeon_winsys_bo *gds_bo = NULL;
3442 struct radeon_winsys_bo *gds_oa_bo = NULL;
3443 struct radeon_cmdbuf *dest_cs[3] = {0};
3444 bool add_tess_rings = false, add_gds = false, add_sample_positions = false;
3445 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
3446 unsigned max_offchip_buffers;
3447 unsigned hs_offchip_param = 0;
3448 unsigned tess_offchip_ring_offset;
3449 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
3450 if (!queue->has_tess_rings) {
3451 if (needs_tess_rings)
3452 add_tess_rings = true;
3453 }
3454 if (!queue->has_gds) {
3455 if (needs_gds)
3456 add_gds = true;
3457 }
3458 if (!queue->has_sample_positions) {
3459 if (needs_sample_positions)
3460 add_sample_positions = true;
3461 }
3462 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
3463 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
3464 &max_offchip_buffers);
3465 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
3466 tess_offchip_ring_size = max_offchip_buffers *
3467 queue->device->tess_offchip_block_dw_size * 4;
3468
3469 scratch_size_per_wave = MAX2(scratch_size_per_wave, queue->scratch_size_per_wave);
3470 if (scratch_size_per_wave)
3471 scratch_waves = MIN2(scratch_waves, UINT32_MAX / scratch_size_per_wave);
3472 else
3473 scratch_waves = 0;
3474
3475 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave, queue->compute_scratch_size_per_wave);
3476 if (compute_scratch_size_per_wave)
3477 compute_scratch_waves = MIN2(compute_scratch_waves, UINT32_MAX / compute_scratch_size_per_wave);
3478 else
3479 compute_scratch_waves = 0;
3480
3481 if (scratch_size_per_wave <= queue->scratch_size_per_wave &&
3482 scratch_waves <= queue->scratch_waves &&
3483 compute_scratch_size_per_wave <= queue->compute_scratch_size_per_wave &&
3484 compute_scratch_waves <= queue->compute_scratch_waves &&
3485 esgs_ring_size <= queue->esgs_ring_size &&
3486 gsvs_ring_size <= queue->gsvs_ring_size &&
3487 !add_tess_rings && !add_gds && !add_sample_positions &&
3488 queue->initial_preamble_cs) {
3489 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3490 *initial_preamble_cs = queue->initial_preamble_cs;
3491 *continue_preamble_cs = queue->continue_preamble_cs;
3492 if (!scratch_size_per_wave && !compute_scratch_size_per_wave &&
3493 !esgs_ring_size && !gsvs_ring_size && !needs_tess_rings &&
3494 !needs_gds && !needs_sample_positions)
3495 *continue_preamble_cs = NULL;
3496 return VK_SUCCESS;
3497 }
3498
3499 uint32_t scratch_size = scratch_size_per_wave * scratch_waves;
3500 uint32_t queue_scratch_size = queue->scratch_size_per_wave * queue->scratch_waves;
3501 if (scratch_size > queue_scratch_size) {
3502 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3503 scratch_size,
3504 4096,
3505 RADEON_DOMAIN_VRAM,
3506 ring_bo_flags,
3507 RADV_BO_PRIORITY_SCRATCH);
3508 if (!scratch_bo)
3509 goto fail;
3510 } else
3511 scratch_bo = queue->scratch_bo;
3512
3513 uint32_t compute_scratch_size = compute_scratch_size_per_wave * compute_scratch_waves;
3514 uint32_t compute_queue_scratch_size = queue->compute_scratch_size_per_wave * queue->compute_scratch_waves;
3515 if (compute_scratch_size > compute_queue_scratch_size) {
3516 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3517 compute_scratch_size,
3518 4096,
3519 RADEON_DOMAIN_VRAM,
3520 ring_bo_flags,
3521 RADV_BO_PRIORITY_SCRATCH);
3522 if (!compute_scratch_bo)
3523 goto fail;
3524
3525 } else
3526 compute_scratch_bo = queue->compute_scratch_bo;
3527
3528 if (esgs_ring_size > queue->esgs_ring_size) {
3529 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3530 esgs_ring_size,
3531 4096,
3532 RADEON_DOMAIN_VRAM,
3533 ring_bo_flags,
3534 RADV_BO_PRIORITY_SCRATCH);
3535 if (!esgs_ring_bo)
3536 goto fail;
3537 } else {
3538 esgs_ring_bo = queue->esgs_ring_bo;
3539 esgs_ring_size = queue->esgs_ring_size;
3540 }
3541
3542 if (gsvs_ring_size > queue->gsvs_ring_size) {
3543 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3544 gsvs_ring_size,
3545 4096,
3546 RADEON_DOMAIN_VRAM,
3547 ring_bo_flags,
3548 RADV_BO_PRIORITY_SCRATCH);
3549 if (!gsvs_ring_bo)
3550 goto fail;
3551 } else {
3552 gsvs_ring_bo = queue->gsvs_ring_bo;
3553 gsvs_ring_size = queue->gsvs_ring_size;
3554 }
3555
3556 if (add_tess_rings) {
3557 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
3558 tess_offchip_ring_offset + tess_offchip_ring_size,
3559 256,
3560 RADEON_DOMAIN_VRAM,
3561 ring_bo_flags,
3562 RADV_BO_PRIORITY_SCRATCH);
3563 if (!tess_rings_bo)
3564 goto fail;
3565 } else {
3566 tess_rings_bo = queue->tess_rings_bo;
3567 }
3568
3569 if (add_gds) {
3570 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3571
3572 /* 4 streamout GDS counters.
3573 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3574 */
3575 gds_bo = queue->device->ws->buffer_create(queue->device->ws,
3576 256, 4,
3577 RADEON_DOMAIN_GDS,
3578 ring_bo_flags,
3579 RADV_BO_PRIORITY_SCRATCH);
3580 if (!gds_bo)
3581 goto fail;
3582
3583 gds_oa_bo = queue->device->ws->buffer_create(queue->device->ws,
3584 4, 1,
3585 RADEON_DOMAIN_OA,
3586 ring_bo_flags,
3587 RADV_BO_PRIORITY_SCRATCH);
3588 if (!gds_oa_bo)
3589 goto fail;
3590 } else {
3591 gds_bo = queue->gds_bo;
3592 gds_oa_bo = queue->gds_oa_bo;
3593 }
3594
3595 if (scratch_bo != queue->scratch_bo ||
3596 esgs_ring_bo != queue->esgs_ring_bo ||
3597 gsvs_ring_bo != queue->gsvs_ring_bo ||
3598 tess_rings_bo != queue->tess_rings_bo ||
3599 add_sample_positions) {
3600 uint32_t size = 0;
3601 if (gsvs_ring_bo || esgs_ring_bo ||
3602 tess_rings_bo || add_sample_positions) {
3603 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
3604 if (add_sample_positions)
3605 size += 128; /* 64+32+16+8 = 120 bytes */
3606 }
3607 else if (scratch_bo)
3608 size = 8; /* 2 dword */
3609
3610 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
3611 size,
3612 4096,
3613 RADEON_DOMAIN_VRAM,
3614 RADEON_FLAG_CPU_ACCESS |
3615 RADEON_FLAG_NO_INTERPROCESS_SHARING |
3616 RADEON_FLAG_READ_ONLY,
3617 RADV_BO_PRIORITY_DESCRIPTOR);
3618 if (!descriptor_bo)
3619 goto fail;
3620 } else
3621 descriptor_bo = queue->descriptor_bo;
3622
3623 if (descriptor_bo != queue->descriptor_bo) {
3624 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
3625
3626 if (scratch_bo) {
3627 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
3628 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3629 S_008F04_SWIZZLE_ENABLE(1);
3630 map[0] = scratch_va;
3631 map[1] = rsrc1;
3632 }
3633
3634 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
3635 fill_geom_tess_rings(queue, map, add_sample_positions,
3636 esgs_ring_size, esgs_ring_bo,
3637 gsvs_ring_size, gsvs_ring_bo,
3638 tess_factor_ring_size,
3639 tess_offchip_ring_offset,
3640 tess_offchip_ring_size,
3641 tess_rings_bo);
3642
3643 queue->device->ws->buffer_unmap(descriptor_bo);
3644 }
3645
3646 for(int i = 0; i < 3; ++i) {
3647 struct radeon_cmdbuf *cs = NULL;
3648 cs = queue->device->ws->cs_create(queue->device->ws,
3649 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
3650 if (!cs)
3651 goto fail;
3652
3653 dest_cs[i] = cs;
3654
3655 if (scratch_bo)
3656 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3657
3658 /* Emit initial configuration. */
3659 switch (queue->queue_family_index) {
3660 case RADV_QUEUE_GENERAL:
3661 radv_init_graphics_state(cs, queue);
3662 break;
3663 case RADV_QUEUE_COMPUTE:
3664 radv_init_compute_state(cs, queue);
3665 break;
3666 case RADV_QUEUE_TRANSFER:
3667 break;
3668 }
3669
3670 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
3671 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3672 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3673
3674 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3675 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3676 }
3677
3678 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
3679 gsvs_ring_bo, gsvs_ring_size);
3680 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
3681 tess_factor_ring_size, tess_rings_bo);
3682 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
3683 radv_emit_compute_scratch(queue, cs, compute_scratch_size_per_wave,
3684 compute_scratch_waves, compute_scratch_bo);
3685 radv_emit_graphics_scratch(queue, cs, scratch_size_per_wave,
3686 scratch_waves, scratch_bo);
3687
3688 if (gds_bo)
3689 radv_cs_add_buffer(queue->device->ws, cs, gds_bo);
3690 if (gds_oa_bo)
3691 radv_cs_add_buffer(queue->device->ws, cs, gds_oa_bo);
3692
3693 if (i == 0) {
3694 si_cs_emit_cache_flush(cs,
3695 queue->device->physical_device->rad_info.chip_class,
3696 NULL, 0,
3697 queue->queue_family_index == RING_COMPUTE &&
3698 queue->device->physical_device->rad_info.chip_class >= GFX7,
3699 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
3700 RADV_CMD_FLAG_INV_ICACHE |
3701 RADV_CMD_FLAG_INV_SCACHE |
3702 RADV_CMD_FLAG_INV_VCACHE |
3703 RADV_CMD_FLAG_INV_L2 |
3704 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3705 } else if (i == 1) {
3706 si_cs_emit_cache_flush(cs,
3707 queue->device->physical_device->rad_info.chip_class,
3708 NULL, 0,
3709 queue->queue_family_index == RING_COMPUTE &&
3710 queue->device->physical_device->rad_info.chip_class >= GFX7,
3711 RADV_CMD_FLAG_INV_ICACHE |
3712 RADV_CMD_FLAG_INV_SCACHE |
3713 RADV_CMD_FLAG_INV_VCACHE |
3714 RADV_CMD_FLAG_INV_L2 |
3715 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3716 }
3717
3718 if (!queue->device->ws->cs_finalize(cs))
3719 goto fail;
3720 }
3721
3722 if (queue->initial_full_flush_preamble_cs)
3723 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
3724
3725 if (queue->initial_preamble_cs)
3726 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
3727
3728 if (queue->continue_preamble_cs)
3729 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
3730
3731 queue->initial_full_flush_preamble_cs = dest_cs[0];
3732 queue->initial_preamble_cs = dest_cs[1];
3733 queue->continue_preamble_cs = dest_cs[2];
3734
3735 if (scratch_bo != queue->scratch_bo) {
3736 if (queue->scratch_bo)
3737 queue->device->ws->buffer_destroy(queue->scratch_bo);
3738 queue->scratch_bo = scratch_bo;
3739 }
3740 queue->scratch_size_per_wave = scratch_size_per_wave;
3741 queue->scratch_waves = scratch_waves;
3742
3743 if (compute_scratch_bo != queue->compute_scratch_bo) {
3744 if (queue->compute_scratch_bo)
3745 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
3746 queue->compute_scratch_bo = compute_scratch_bo;
3747 }
3748 queue->compute_scratch_size_per_wave = compute_scratch_size_per_wave;
3749 queue->compute_scratch_waves = compute_scratch_waves;
3750
3751 if (esgs_ring_bo != queue->esgs_ring_bo) {
3752 if (queue->esgs_ring_bo)
3753 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
3754 queue->esgs_ring_bo = esgs_ring_bo;
3755 queue->esgs_ring_size = esgs_ring_size;
3756 }
3757
3758 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
3759 if (queue->gsvs_ring_bo)
3760 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
3761 queue->gsvs_ring_bo = gsvs_ring_bo;
3762 queue->gsvs_ring_size = gsvs_ring_size;
3763 }
3764
3765 if (tess_rings_bo != queue->tess_rings_bo) {
3766 queue->tess_rings_bo = tess_rings_bo;
3767 queue->has_tess_rings = true;
3768 }
3769
3770 if (gds_bo != queue->gds_bo) {
3771 queue->gds_bo = gds_bo;
3772 queue->has_gds = true;
3773 }
3774
3775 if (gds_oa_bo != queue->gds_oa_bo)
3776 queue->gds_oa_bo = gds_oa_bo;
3777
3778 if (descriptor_bo != queue->descriptor_bo) {
3779 if (queue->descriptor_bo)
3780 queue->device->ws->buffer_destroy(queue->descriptor_bo);
3781
3782 queue->descriptor_bo = descriptor_bo;
3783 }
3784
3785 if (add_sample_positions)
3786 queue->has_sample_positions = true;
3787
3788 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3789 *initial_preamble_cs = queue->initial_preamble_cs;
3790 *continue_preamble_cs = queue->continue_preamble_cs;
3791 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
3792 *continue_preamble_cs = NULL;
3793 return VK_SUCCESS;
3794 fail:
3795 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
3796 if (dest_cs[i])
3797 queue->device->ws->cs_destroy(dest_cs[i]);
3798 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
3799 queue->device->ws->buffer_destroy(descriptor_bo);
3800 if (scratch_bo && scratch_bo != queue->scratch_bo)
3801 queue->device->ws->buffer_destroy(scratch_bo);
3802 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
3803 queue->device->ws->buffer_destroy(compute_scratch_bo);
3804 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
3805 queue->device->ws->buffer_destroy(esgs_ring_bo);
3806 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
3807 queue->device->ws->buffer_destroy(gsvs_ring_bo);
3808 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
3809 queue->device->ws->buffer_destroy(tess_rings_bo);
3810 if (gds_bo && gds_bo != queue->gds_bo)
3811 queue->device->ws->buffer_destroy(gds_bo);
3812 if (gds_oa_bo && gds_oa_bo != queue->gds_oa_bo)
3813 queue->device->ws->buffer_destroy(gds_oa_bo);
3814
3815 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3816 }
3817
3818 static VkResult radv_alloc_sem_counts(struct radv_device *device,
3819 struct radv_winsys_sem_counts *counts,
3820 int num_sems,
3821 struct radv_semaphore_part **sems,
3822 const uint64_t *timeline_values,
3823 VkFence _fence,
3824 bool is_signal)
3825 {
3826 int syncobj_idx = 0, sem_idx = 0;
3827
3828 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
3829 return VK_SUCCESS;
3830
3831 for (uint32_t i = 0; i < num_sems; i++) {
3832 switch(sems[i]->kind) {
3833 case RADV_SEMAPHORE_SYNCOBJ:
3834 counts->syncobj_count++;
3835 break;
3836 case RADV_SEMAPHORE_WINSYS:
3837 counts->sem_count++;
3838 break;
3839 case RADV_SEMAPHORE_NONE:
3840 break;
3841 case RADV_SEMAPHORE_TIMELINE:
3842 counts->syncobj_count++;
3843 break;
3844 }
3845 }
3846
3847 if (_fence != VK_NULL_HANDLE) {
3848 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3849 if (fence->temp_syncobj || fence->syncobj)
3850 counts->syncobj_count++;
3851 }
3852
3853 if (counts->syncobj_count) {
3854 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
3855 if (!counts->syncobj)
3856 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3857 }
3858
3859 if (counts->sem_count) {
3860 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
3861 if (!counts->sem) {
3862 free(counts->syncobj);
3863 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3864 }
3865 }
3866
3867 for (uint32_t i = 0; i < num_sems; i++) {
3868 switch(sems[i]->kind) {
3869 case RADV_SEMAPHORE_NONE:
3870 unreachable("Empty semaphore");
3871 break;
3872 case RADV_SEMAPHORE_SYNCOBJ:
3873 counts->syncobj[syncobj_idx++] = sems[i]->syncobj;
3874 break;
3875 case RADV_SEMAPHORE_WINSYS:
3876 counts->sem[sem_idx++] = sems[i]->ws_sem;
3877 break;
3878 case RADV_SEMAPHORE_TIMELINE: {
3879 pthread_mutex_lock(&sems[i]->timeline.mutex);
3880 struct radv_timeline_point *point = NULL;
3881 if (is_signal) {
3882 point = radv_timeline_add_point_locked(device, &sems[i]->timeline, timeline_values[i]);
3883 } else {
3884 point = radv_timeline_find_point_at_least_locked(device, &sems[i]->timeline, timeline_values[i]);
3885 }
3886
3887 pthread_mutex_unlock(&sems[i]->timeline.mutex);
3888
3889 if (point) {
3890 counts->syncobj[syncobj_idx++] = point->syncobj;
3891 } else {
3892 /* Explicitly remove the semaphore so we might not find
3893 * a point later post-submit. */
3894 sems[i] = NULL;
3895 }
3896 break;
3897 }
3898 }
3899 }
3900
3901 if (_fence != VK_NULL_HANDLE) {
3902 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3903 if (fence->temp_syncobj)
3904 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
3905 else if (fence->syncobj)
3906 counts->syncobj[syncobj_idx++] = fence->syncobj;
3907 }
3908
3909 assert(syncobj_idx <= counts->syncobj_count);
3910 counts->syncobj_count = syncobj_idx;
3911
3912 return VK_SUCCESS;
3913 }
3914
3915 static void
3916 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
3917 {
3918 free(sem_info->wait.syncobj);
3919 free(sem_info->wait.sem);
3920 free(sem_info->signal.syncobj);
3921 free(sem_info->signal.sem);
3922 }
3923
3924
3925 static void radv_free_temp_syncobjs(struct radv_device *device,
3926 int num_sems,
3927 struct radv_semaphore_part *sems)
3928 {
3929 for (uint32_t i = 0; i < num_sems; i++) {
3930 radv_destroy_semaphore_part(device, sems + i);
3931 }
3932 }
3933
3934 static VkResult
3935 radv_alloc_sem_info(struct radv_device *device,
3936 struct radv_winsys_sem_info *sem_info,
3937 int num_wait_sems,
3938 struct radv_semaphore_part **wait_sems,
3939 const uint64_t *wait_values,
3940 int num_signal_sems,
3941 struct radv_semaphore_part **signal_sems,
3942 const uint64_t *signal_values,
3943 VkFence fence)
3944 {
3945 VkResult ret;
3946 memset(sem_info, 0, sizeof(*sem_info));
3947
3948 ret = radv_alloc_sem_counts(device, &sem_info->wait, num_wait_sems, wait_sems, wait_values, VK_NULL_HANDLE, false);
3949 if (ret)
3950 return ret;
3951 ret = radv_alloc_sem_counts(device, &sem_info->signal, num_signal_sems, signal_sems, signal_values, fence, true);
3952 if (ret)
3953 radv_free_sem_info(sem_info);
3954
3955 /* caller can override these */
3956 sem_info->cs_emit_wait = true;
3957 sem_info->cs_emit_signal = true;
3958 return ret;
3959 }
3960
3961 static void
3962 radv_finalize_timelines(struct radv_device *device,
3963 uint32_t num_wait_sems,
3964 struct radv_semaphore_part **wait_sems,
3965 const uint64_t *wait_values,
3966 uint32_t num_signal_sems,
3967 struct radv_semaphore_part **signal_sems,
3968 const uint64_t *signal_values,
3969 struct list_head *processing_list)
3970 {
3971 for (uint32_t i = 0; i < num_wait_sems; ++i) {
3972 if (wait_sems[i] && wait_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
3973 pthread_mutex_lock(&wait_sems[i]->timeline.mutex);
3974 struct radv_timeline_point *point =
3975 radv_timeline_find_point_at_least_locked(device, &wait_sems[i]->timeline, wait_values[i]);
3976 point->wait_count -= 2;
3977 pthread_mutex_unlock(&wait_sems[i]->timeline.mutex);
3978 }
3979 }
3980 for (uint32_t i = 0; i < num_signal_sems; ++i) {
3981 if (signal_sems[i] && signal_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
3982 pthread_mutex_lock(&signal_sems[i]->timeline.mutex);
3983 struct radv_timeline_point *point =
3984 radv_timeline_find_point_at_least_locked(device, &signal_sems[i]->timeline, signal_values[i]);
3985 signal_sems[i]->timeline.highest_submitted =
3986 MAX2(signal_sems[i]->timeline.highest_submitted, point->value);
3987 point->wait_count -= 2;
3988 radv_timeline_trigger_waiters_locked(&signal_sems[i]->timeline, processing_list);
3989 pthread_mutex_unlock(&signal_sems[i]->timeline.mutex);
3990 }
3991 }
3992 }
3993
3994 static void
3995 radv_sparse_buffer_bind_memory(struct radv_device *device,
3996 const VkSparseBufferMemoryBindInfo *bind)
3997 {
3998 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3999
4000 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4001 struct radv_device_memory *mem = NULL;
4002
4003 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4004 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4005
4006 device->ws->buffer_virtual_bind(buffer->bo,
4007 bind->pBinds[i].resourceOffset,
4008 bind->pBinds[i].size,
4009 mem ? mem->bo : NULL,
4010 bind->pBinds[i].memoryOffset);
4011 }
4012 }
4013
4014 static void
4015 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
4016 const VkSparseImageOpaqueMemoryBindInfo *bind)
4017 {
4018 RADV_FROM_HANDLE(radv_image, image, bind->image);
4019
4020 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4021 struct radv_device_memory *mem = NULL;
4022
4023 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4024 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4025
4026 device->ws->buffer_virtual_bind(image->bo,
4027 bind->pBinds[i].resourceOffset,
4028 bind->pBinds[i].size,
4029 mem ? mem->bo : NULL,
4030 bind->pBinds[i].memoryOffset);
4031 }
4032 }
4033
4034 static VkResult
4035 radv_get_preambles(struct radv_queue *queue,
4036 const VkCommandBuffer *cmd_buffers,
4037 uint32_t cmd_buffer_count,
4038 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
4039 struct radeon_cmdbuf **initial_preamble_cs,
4040 struct radeon_cmdbuf **continue_preamble_cs)
4041 {
4042 uint32_t scratch_size_per_wave = 0, waves_wanted = 0;
4043 uint32_t compute_scratch_size_per_wave = 0, compute_waves_wanted = 0;
4044 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
4045 bool tess_rings_needed = false;
4046 bool gds_needed = false;
4047 bool sample_positions_needed = false;
4048
4049 for (uint32_t j = 0; j < cmd_buffer_count; j++) {
4050 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
4051 cmd_buffers[j]);
4052
4053 scratch_size_per_wave = MAX2(scratch_size_per_wave, cmd_buffer->scratch_size_per_wave_needed);
4054 waves_wanted = MAX2(waves_wanted, cmd_buffer->scratch_waves_wanted);
4055 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave,
4056 cmd_buffer->compute_scratch_size_per_wave_needed);
4057 compute_waves_wanted = MAX2(compute_waves_wanted,
4058 cmd_buffer->compute_scratch_waves_wanted);
4059 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
4060 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
4061 tess_rings_needed |= cmd_buffer->tess_rings_needed;
4062 gds_needed |= cmd_buffer->gds_needed;
4063 sample_positions_needed |= cmd_buffer->sample_positions_needed;
4064 }
4065
4066 return radv_get_preamble_cs(queue, scratch_size_per_wave, waves_wanted,
4067 compute_scratch_size_per_wave, compute_waves_wanted,
4068 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
4069 gds_needed, sample_positions_needed,
4070 initial_full_flush_preamble_cs,
4071 initial_preamble_cs, continue_preamble_cs);
4072 }
4073
4074 struct radv_deferred_queue_submission {
4075 struct radv_queue *queue;
4076 VkCommandBuffer *cmd_buffers;
4077 uint32_t cmd_buffer_count;
4078
4079 /* Sparse bindings that happen on a queue. */
4080 VkSparseBufferMemoryBindInfo *buffer_binds;
4081 uint32_t buffer_bind_count;
4082 VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4083 uint32_t image_opaque_bind_count;
4084
4085 bool flush_caches;
4086 VkShaderStageFlags wait_dst_stage_mask;
4087 struct radv_semaphore_part **wait_semaphores;
4088 uint32_t wait_semaphore_count;
4089 struct radv_semaphore_part **signal_semaphores;
4090 uint32_t signal_semaphore_count;
4091 VkFence fence;
4092
4093 uint64_t *wait_values;
4094 uint64_t *signal_values;
4095
4096 struct radv_semaphore_part *temporary_semaphore_parts;
4097 uint32_t temporary_semaphore_part_count;
4098
4099 struct list_head queue_pending_list;
4100 uint32_t submission_wait_count;
4101 struct radv_timeline_waiter *wait_nodes;
4102
4103 struct list_head processing_list;
4104 };
4105
4106 struct radv_queue_submission {
4107 const VkCommandBuffer *cmd_buffers;
4108 uint32_t cmd_buffer_count;
4109
4110 /* Sparse bindings that happen on a queue. */
4111 const VkSparseBufferMemoryBindInfo *buffer_binds;
4112 uint32_t buffer_bind_count;
4113 const VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4114 uint32_t image_opaque_bind_count;
4115
4116 bool flush_caches;
4117 VkPipelineStageFlags wait_dst_stage_mask;
4118 const VkSemaphore *wait_semaphores;
4119 uint32_t wait_semaphore_count;
4120 const VkSemaphore *signal_semaphores;
4121 uint32_t signal_semaphore_count;
4122 VkFence fence;
4123
4124 const uint64_t *wait_values;
4125 uint32_t wait_value_count;
4126 const uint64_t *signal_values;
4127 uint32_t signal_value_count;
4128 };
4129
4130 static VkResult
4131 radv_create_deferred_submission(struct radv_queue *queue,
4132 const struct radv_queue_submission *submission,
4133 struct radv_deferred_queue_submission **out)
4134 {
4135 struct radv_deferred_queue_submission *deferred = NULL;
4136 size_t size = sizeof(struct radv_deferred_queue_submission);
4137
4138 uint32_t temporary_count = 0;
4139 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4140 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4141 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE)
4142 ++temporary_count;
4143 }
4144
4145 size += submission->cmd_buffer_count * sizeof(VkCommandBuffer);
4146 size += submission->buffer_bind_count * sizeof(VkSparseBufferMemoryBindInfo);
4147 size += submission->image_opaque_bind_count * sizeof(VkSparseImageOpaqueMemoryBindInfo);
4148 size += submission->wait_semaphore_count * sizeof(struct radv_semaphore_part *);
4149 size += temporary_count * sizeof(struct radv_semaphore_part);
4150 size += submission->signal_semaphore_count * sizeof(struct radv_semaphore_part *);
4151 size += submission->wait_value_count * sizeof(uint64_t);
4152 size += submission->signal_value_count * sizeof(uint64_t);
4153 size += submission->wait_semaphore_count * sizeof(struct radv_timeline_waiter);
4154
4155 deferred = calloc(1, size);
4156 if (!deferred)
4157 return VK_ERROR_OUT_OF_HOST_MEMORY;
4158
4159 deferred->queue = queue;
4160
4161 deferred->cmd_buffers = (void*)(deferred + 1);
4162 deferred->cmd_buffer_count = submission->cmd_buffer_count;
4163 memcpy(deferred->cmd_buffers, submission->cmd_buffers,
4164 submission->cmd_buffer_count * sizeof(*deferred->cmd_buffers));
4165
4166 deferred->buffer_binds = (void*)(deferred->cmd_buffers + submission->cmd_buffer_count);
4167 deferred->buffer_bind_count = submission->buffer_bind_count;
4168 memcpy(deferred->buffer_binds, submission->buffer_binds,
4169 submission->buffer_bind_count * sizeof(*deferred->buffer_binds));
4170
4171 deferred->image_opaque_binds = (void*)(deferred->buffer_binds + submission->buffer_bind_count);
4172 deferred->image_opaque_bind_count = submission->image_opaque_bind_count;
4173 memcpy(deferred->image_opaque_binds, submission->image_opaque_binds,
4174 submission->image_opaque_bind_count * sizeof(*deferred->image_opaque_binds));
4175
4176 deferred->flush_caches = submission->flush_caches;
4177 deferred->wait_dst_stage_mask = submission->wait_dst_stage_mask;
4178
4179 deferred->wait_semaphores = (void*)(deferred->image_opaque_binds + deferred->image_opaque_bind_count);
4180 deferred->wait_semaphore_count = submission->wait_semaphore_count;
4181
4182 deferred->signal_semaphores = (void*)(deferred->wait_semaphores + deferred->wait_semaphore_count);
4183 deferred->signal_semaphore_count = submission->signal_semaphore_count;
4184
4185 deferred->fence = submission->fence;
4186
4187 deferred->temporary_semaphore_parts = (void*)(deferred->signal_semaphores + deferred->signal_semaphore_count);
4188 deferred->temporary_semaphore_part_count = temporary_count;
4189
4190 uint32_t temporary_idx = 0;
4191 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4192 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4193 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4194 deferred->wait_semaphores[i] = &deferred->temporary_semaphore_parts[temporary_idx];
4195 deferred->temporary_semaphore_parts[temporary_idx] = semaphore->temporary;
4196 semaphore->temporary.kind = RADV_SEMAPHORE_NONE;
4197 ++temporary_idx;
4198 } else
4199 deferred->wait_semaphores[i] = &semaphore->permanent;
4200 }
4201
4202 for (uint32_t i = 0; i < submission->signal_semaphore_count; ++i) {
4203 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->signal_semaphores[i]);
4204 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4205 deferred->signal_semaphores[i] = &semaphore->temporary;
4206 } else {
4207 deferred->signal_semaphores[i] = &semaphore->permanent;
4208 }
4209 }
4210
4211 deferred->wait_values = (void*)(deferred->temporary_semaphore_parts + temporary_count);
4212 memcpy(deferred->wait_values, submission->wait_values, submission->wait_value_count * sizeof(uint64_t));
4213 deferred->signal_values = deferred->wait_values + submission->wait_value_count;
4214 memcpy(deferred->signal_values, submission->signal_values, submission->signal_value_count * sizeof(uint64_t));
4215
4216 deferred->wait_nodes = (void*)(deferred->signal_values + submission->signal_value_count);
4217 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4218 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4219 deferred->submission_wait_count = 1 + submission->wait_semaphore_count;
4220
4221 *out = deferred;
4222 return VK_SUCCESS;
4223 }
4224
4225 static void
4226 radv_queue_enqueue_submission(struct radv_deferred_queue_submission *submission,
4227 struct list_head *processing_list)
4228 {
4229 uint32_t wait_cnt = 0;
4230 struct radv_timeline_waiter *waiter = submission->wait_nodes;
4231 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4232 if (submission->wait_semaphores[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4233 pthread_mutex_lock(&submission->wait_semaphores[i]->timeline.mutex);
4234 if (submission->wait_semaphores[i]->timeline.highest_submitted < submission->wait_values[i]) {
4235 ++wait_cnt;
4236 waiter->value = submission->wait_values[i];
4237 waiter->submission = submission;
4238 list_addtail(&waiter->list, &submission->wait_semaphores[i]->timeline.waiters);
4239 ++waiter;
4240 }
4241 pthread_mutex_unlock(&submission->wait_semaphores[i]->timeline.mutex);
4242 }
4243 }
4244
4245 pthread_mutex_lock(&submission->queue->pending_mutex);
4246
4247 bool is_first = list_is_empty(&submission->queue->pending_submissions);
4248 list_addtail(&submission->queue_pending_list, &submission->queue->pending_submissions);
4249
4250 pthread_mutex_unlock(&submission->queue->pending_mutex);
4251
4252 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4253 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4254 * submission. */
4255 uint32_t decrement = submission->wait_semaphore_count - wait_cnt + (is_first ? 1 : 0);
4256 if (__atomic_sub_fetch(&submission->submission_wait_count, decrement, __ATOMIC_ACQ_REL) == 0) {
4257 list_addtail(&submission->processing_list, processing_list);
4258 }
4259 }
4260
4261 static void
4262 radv_queue_submission_update_queue(struct radv_deferred_queue_submission *submission,
4263 struct list_head *processing_list)
4264 {
4265 pthread_mutex_lock(&submission->queue->pending_mutex);
4266 list_del(&submission->queue_pending_list);
4267
4268 /* trigger the next submission in the queue. */
4269 if (!list_is_empty(&submission->queue->pending_submissions)) {
4270 struct radv_deferred_queue_submission *next_submission =
4271 list_first_entry(&submission->queue->pending_submissions,
4272 struct radv_deferred_queue_submission,
4273 queue_pending_list);
4274 if (p_atomic_dec_zero(&next_submission->submission_wait_count)) {
4275 list_addtail(&next_submission->processing_list, processing_list);
4276 }
4277 }
4278 pthread_mutex_unlock(&submission->queue->pending_mutex);
4279
4280 pthread_cond_broadcast(&submission->queue->device->timeline_cond);
4281 }
4282
4283 static VkResult
4284 radv_queue_submit_deferred(struct radv_deferred_queue_submission *submission,
4285 struct list_head *processing_list)
4286 {
4287 RADV_FROM_HANDLE(radv_fence, fence, submission->fence);
4288 struct radv_queue *queue = submission->queue;
4289 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4290 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
4291 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
4292 bool do_flush = submission->flush_caches || submission->wait_dst_stage_mask;
4293 bool can_patch = true;
4294 uint32_t advance;
4295 struct radv_winsys_sem_info sem_info;
4296 VkResult result;
4297 int ret;
4298 struct radeon_cmdbuf *initial_preamble_cs = NULL;
4299 struct radeon_cmdbuf *initial_flush_preamble_cs = NULL;
4300 struct radeon_cmdbuf *continue_preamble_cs = NULL;
4301
4302 result = radv_get_preambles(queue, submission->cmd_buffers,
4303 submission->cmd_buffer_count,
4304 &initial_preamble_cs,
4305 &initial_flush_preamble_cs,
4306 &continue_preamble_cs);
4307 if (result != VK_SUCCESS)
4308 goto fail;
4309
4310 result = radv_alloc_sem_info(queue->device,
4311 &sem_info,
4312 submission->wait_semaphore_count,
4313 submission->wait_semaphores,
4314 submission->wait_values,
4315 submission->signal_semaphore_count,
4316 submission->signal_semaphores,
4317 submission->signal_values,
4318 submission->fence);
4319 if (result != VK_SUCCESS)
4320 goto fail;
4321
4322 for (uint32_t i = 0; i < submission->buffer_bind_count; ++i) {
4323 radv_sparse_buffer_bind_memory(queue->device,
4324 submission->buffer_binds + i);
4325 }
4326
4327 for (uint32_t i = 0; i < submission->image_opaque_bind_count; ++i) {
4328 radv_sparse_image_opaque_bind_memory(queue->device,
4329 submission->image_opaque_binds + i);
4330 }
4331
4332 if (!submission->cmd_buffer_count) {
4333 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
4334 &queue->device->empty_cs[queue->queue_family_index],
4335 1, NULL, NULL,
4336 &sem_info, NULL,
4337 false, base_fence);
4338 if (ret) {
4339 radv_loge("failed to submit CS\n");
4340 abort();
4341 }
4342
4343 goto success;
4344 } else {
4345 struct radeon_cmdbuf **cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
4346 (submission->cmd_buffer_count));
4347
4348 for (uint32_t j = 0; j < submission->cmd_buffer_count; j++) {
4349 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, submission->cmd_buffers[j]);
4350 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
4351
4352 cs_array[j] = cmd_buffer->cs;
4353 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
4354 can_patch = false;
4355
4356 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
4357 }
4358
4359 for (uint32_t j = 0; j < submission->cmd_buffer_count; j += advance) {
4360 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
4361 const struct radv_winsys_bo_list *bo_list = NULL;
4362
4363 advance = MIN2(max_cs_submission,
4364 submission->cmd_buffer_count - j);
4365
4366 if (queue->device->trace_bo)
4367 *queue->device->trace_id_ptr = 0;
4368
4369 sem_info.cs_emit_wait = j == 0;
4370 sem_info.cs_emit_signal = j + advance == submission->cmd_buffer_count;
4371
4372 if (unlikely(queue->device->use_global_bo_list)) {
4373 pthread_mutex_lock(&queue->device->bo_list.mutex);
4374 bo_list = &queue->device->bo_list.list;
4375 }
4376
4377 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
4378 advance, initial_preamble, continue_preamble_cs,
4379 &sem_info, bo_list,
4380 can_patch, base_fence);
4381
4382 if (unlikely(queue->device->use_global_bo_list))
4383 pthread_mutex_unlock(&queue->device->bo_list.mutex);
4384
4385 if (ret) {
4386 radv_loge("failed to submit CS\n");
4387 abort();
4388 }
4389 if (queue->device->trace_bo) {
4390 radv_check_gpu_hangs(queue, cs_array[j]);
4391 }
4392 }
4393
4394 free(cs_array);
4395 }
4396
4397 success:
4398 radv_free_temp_syncobjs(queue->device,
4399 submission->temporary_semaphore_part_count,
4400 submission->temporary_semaphore_parts);
4401 radv_finalize_timelines(queue->device,
4402 submission->wait_semaphore_count,
4403 submission->wait_semaphores,
4404 submission->wait_values,
4405 submission->signal_semaphore_count,
4406 submission->signal_semaphores,
4407 submission->signal_values,
4408 processing_list);
4409 /* Has to happen after timeline finalization to make sure the
4410 * condition variable is only triggered when timelines and queue have
4411 * been updated. */
4412 radv_queue_submission_update_queue(submission, processing_list);
4413 radv_free_sem_info(&sem_info);
4414 free(submission);
4415 return VK_SUCCESS;
4416
4417 fail:
4418 radv_free_temp_syncobjs(queue->device,
4419 submission->temporary_semaphore_part_count,
4420 submission->temporary_semaphore_parts);
4421 free(submission);
4422 return VK_ERROR_DEVICE_LOST;
4423 }
4424
4425 static VkResult
4426 radv_process_submissions(struct list_head *processing_list)
4427 {
4428 while(!list_is_empty(processing_list)) {
4429 struct radv_deferred_queue_submission *submission =
4430 list_first_entry(processing_list, struct radv_deferred_queue_submission, processing_list);
4431 list_del(&submission->processing_list);
4432
4433 VkResult result = radv_queue_submit_deferred(submission, processing_list);
4434 if (result != VK_SUCCESS)
4435 return result;
4436 }
4437 return VK_SUCCESS;
4438 }
4439
4440 static VkResult radv_queue_submit(struct radv_queue *queue,
4441 const struct radv_queue_submission *submission)
4442 {
4443 struct radv_deferred_queue_submission *deferred = NULL;
4444
4445 VkResult result = radv_create_deferred_submission(queue, submission, &deferred);
4446 if (result != VK_SUCCESS)
4447 return result;
4448
4449 struct list_head processing_list;
4450 list_inithead(&processing_list);
4451
4452 radv_queue_enqueue_submission(deferred, &processing_list);
4453 return radv_process_submissions(&processing_list);
4454 }
4455
4456 /* Signals fence as soon as all the work currently put on queue is done. */
4457 static VkResult radv_signal_fence(struct radv_queue *queue,
4458 VkFence fence)
4459 {
4460 return radv_queue_submit(queue, &(struct radv_queue_submission) {
4461 .fence = fence
4462 });
4463 }
4464
4465 static bool radv_submit_has_effects(const VkSubmitInfo *info)
4466 {
4467 return info->commandBufferCount ||
4468 info->waitSemaphoreCount ||
4469 info->signalSemaphoreCount;
4470 }
4471
4472 VkResult radv_QueueSubmit(
4473 VkQueue _queue,
4474 uint32_t submitCount,
4475 const VkSubmitInfo* pSubmits,
4476 VkFence fence)
4477 {
4478 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4479 VkResult result;
4480 uint32_t fence_idx = 0;
4481 bool flushed_caches = false;
4482
4483 if (fence != VK_NULL_HANDLE) {
4484 for (uint32_t i = 0; i < submitCount; ++i)
4485 if (radv_submit_has_effects(pSubmits + i))
4486 fence_idx = i;
4487 } else
4488 fence_idx = UINT32_MAX;
4489
4490 for (uint32_t i = 0; i < submitCount; i++) {
4491 if (!radv_submit_has_effects(pSubmits + i) && fence_idx != i)
4492 continue;
4493
4494 VkPipelineStageFlags wait_dst_stage_mask = 0;
4495 for (unsigned j = 0; j < pSubmits[i].waitSemaphoreCount; ++j) {
4496 wait_dst_stage_mask |= pSubmits[i].pWaitDstStageMask[j];
4497 }
4498
4499 const VkTimelineSemaphoreSubmitInfoKHR *timeline_info =
4500 vk_find_struct_const(pSubmits[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO_KHR);
4501
4502 result = radv_queue_submit(queue, &(struct radv_queue_submission) {
4503 .cmd_buffers = pSubmits[i].pCommandBuffers,
4504 .cmd_buffer_count = pSubmits[i].commandBufferCount,
4505 .wait_dst_stage_mask = wait_dst_stage_mask,
4506 .flush_caches = !flushed_caches,
4507 .wait_semaphores = pSubmits[i].pWaitSemaphores,
4508 .wait_semaphore_count = pSubmits[i].waitSemaphoreCount,
4509 .signal_semaphores = pSubmits[i].pSignalSemaphores,
4510 .signal_semaphore_count = pSubmits[i].signalSemaphoreCount,
4511 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
4512 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
4513 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
4514 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
4515 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
4516 });
4517 if (result != VK_SUCCESS)
4518 return result;
4519
4520 flushed_caches = true;
4521 }
4522
4523 if (fence != VK_NULL_HANDLE && !submitCount) {
4524 result = radv_signal_fence(queue, fence);
4525 if (result != VK_SUCCESS)
4526 return result;
4527 }
4528
4529 return VK_SUCCESS;
4530 }
4531
4532 VkResult radv_QueueWaitIdle(
4533 VkQueue _queue)
4534 {
4535 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4536
4537 pthread_mutex_lock(&queue->pending_mutex);
4538 while (!list_is_empty(&queue->pending_submissions)) {
4539 pthread_cond_wait(&queue->device->timeline_cond, &queue->pending_mutex);
4540 }
4541 pthread_mutex_unlock(&queue->pending_mutex);
4542
4543 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
4544 radv_queue_family_to_ring(queue->queue_family_index),
4545 queue->queue_idx);
4546 return VK_SUCCESS;
4547 }
4548
4549 VkResult radv_DeviceWaitIdle(
4550 VkDevice _device)
4551 {
4552 RADV_FROM_HANDLE(radv_device, device, _device);
4553
4554 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
4555 for (unsigned q = 0; q < device->queue_count[i]; q++) {
4556 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
4557 }
4558 }
4559 return VK_SUCCESS;
4560 }
4561
4562 VkResult radv_EnumerateInstanceExtensionProperties(
4563 const char* pLayerName,
4564 uint32_t* pPropertyCount,
4565 VkExtensionProperties* pProperties)
4566 {
4567 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4568
4569 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
4570 if (radv_supported_instance_extensions.extensions[i]) {
4571 vk_outarray_append(&out, prop) {
4572 *prop = radv_instance_extensions[i];
4573 }
4574 }
4575 }
4576
4577 return vk_outarray_status(&out);
4578 }
4579
4580 VkResult radv_EnumerateDeviceExtensionProperties(
4581 VkPhysicalDevice physicalDevice,
4582 const char* pLayerName,
4583 uint32_t* pPropertyCount,
4584 VkExtensionProperties* pProperties)
4585 {
4586 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
4587 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4588
4589 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
4590 if (device->supported_extensions.extensions[i]) {
4591 vk_outarray_append(&out, prop) {
4592 *prop = radv_device_extensions[i];
4593 }
4594 }
4595 }
4596
4597 return vk_outarray_status(&out);
4598 }
4599
4600 PFN_vkVoidFunction radv_GetInstanceProcAddr(
4601 VkInstance _instance,
4602 const char* pName)
4603 {
4604 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4605 bool unchecked = instance ? instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS : false;
4606
4607 if (unchecked) {
4608 return radv_lookup_entrypoint_unchecked(pName);
4609 } else {
4610 return radv_lookup_entrypoint_checked(pName,
4611 instance ? instance->apiVersion : 0,
4612 instance ? &instance->enabled_extensions : NULL,
4613 NULL);
4614 }
4615 }
4616
4617 /* The loader wants us to expose a second GetInstanceProcAddr function
4618 * to work around certain LD_PRELOAD issues seen in apps.
4619 */
4620 PUBLIC
4621 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4622 VkInstance instance,
4623 const char* pName);
4624
4625 PUBLIC
4626 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4627 VkInstance instance,
4628 const char* pName)
4629 {
4630 return radv_GetInstanceProcAddr(instance, pName);
4631 }
4632
4633 PUBLIC
4634 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
4635 VkInstance _instance,
4636 const char* pName);
4637
4638 PUBLIC
4639 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
4640 VkInstance _instance,
4641 const char* pName)
4642 {
4643 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4644
4645 return radv_lookup_physical_device_entrypoint_checked(pName,
4646 instance ? instance->apiVersion : 0,
4647 instance ? &instance->enabled_extensions : NULL);
4648 }
4649
4650 PFN_vkVoidFunction radv_GetDeviceProcAddr(
4651 VkDevice _device,
4652 const char* pName)
4653 {
4654 RADV_FROM_HANDLE(radv_device, device, _device);
4655 bool unchecked = device ? device->instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS : false;
4656
4657 if (unchecked) {
4658 return radv_lookup_entrypoint_unchecked(pName);
4659 } else {
4660 return radv_lookup_entrypoint_checked(pName,
4661 device->instance->apiVersion,
4662 &device->instance->enabled_extensions,
4663 &device->enabled_extensions);
4664 }
4665 }
4666
4667 bool radv_get_memory_fd(struct radv_device *device,
4668 struct radv_device_memory *memory,
4669 int *pFD)
4670 {
4671 struct radeon_bo_metadata metadata;
4672
4673 if (memory->image) {
4674 radv_init_metadata(device, memory->image, &metadata);
4675 device->ws->buffer_set_metadata(memory->bo, &metadata);
4676 }
4677
4678 return device->ws->buffer_get_fd(device->ws, memory->bo,
4679 pFD);
4680 }
4681
4682
4683 static void radv_free_memory(struct radv_device *device,
4684 const VkAllocationCallbacks* pAllocator,
4685 struct radv_device_memory *mem)
4686 {
4687 if (mem == NULL)
4688 return;
4689
4690 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4691 if (mem->android_hardware_buffer)
4692 AHardwareBuffer_release(mem->android_hardware_buffer);
4693 #endif
4694
4695 if (mem->bo) {
4696 radv_bo_list_remove(device, mem->bo);
4697 device->ws->buffer_destroy(mem->bo);
4698 mem->bo = NULL;
4699 }
4700
4701 vk_free2(&device->alloc, pAllocator, mem);
4702 }
4703
4704 static VkResult radv_alloc_memory(struct radv_device *device,
4705 const VkMemoryAllocateInfo* pAllocateInfo,
4706 const VkAllocationCallbacks* pAllocator,
4707 VkDeviceMemory* pMem)
4708 {
4709 struct radv_device_memory *mem;
4710 VkResult result;
4711 enum radeon_bo_domain domain;
4712 uint32_t flags = 0;
4713 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
4714
4715 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
4716
4717 const VkImportMemoryFdInfoKHR *import_info =
4718 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
4719 const VkMemoryDedicatedAllocateInfo *dedicate_info =
4720 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
4721 const VkExportMemoryAllocateInfo *export_info =
4722 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
4723 const struct VkImportAndroidHardwareBufferInfoANDROID *ahb_import_info =
4724 vk_find_struct_const(pAllocateInfo->pNext,
4725 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID);
4726 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
4727 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
4728
4729 const struct wsi_memory_allocate_info *wsi_info =
4730 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
4731
4732 if (pAllocateInfo->allocationSize == 0 && !ahb_import_info &&
4733 !(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID))) {
4734 /* Apparently, this is allowed */
4735 *pMem = VK_NULL_HANDLE;
4736 return VK_SUCCESS;
4737 }
4738
4739 mem = vk_zalloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
4740 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4741 if (mem == NULL)
4742 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4743
4744 if (wsi_info && wsi_info->implicit_sync)
4745 flags |= RADEON_FLAG_IMPLICIT_SYNC;
4746
4747 if (dedicate_info) {
4748 mem->image = radv_image_from_handle(dedicate_info->image);
4749 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
4750 } else {
4751 mem->image = NULL;
4752 mem->buffer = NULL;
4753 }
4754
4755 float priority_float = 0.5;
4756 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
4757 vk_find_struct_const(pAllocateInfo->pNext,
4758 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
4759 if (priority_ext)
4760 priority_float = priority_ext->priority;
4761
4762 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
4763 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
4764
4765 mem->user_ptr = NULL;
4766 mem->bo = NULL;
4767
4768 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4769 mem->android_hardware_buffer = NULL;
4770 #endif
4771
4772 if (ahb_import_info) {
4773 result = radv_import_ahb_memory(device, mem, priority, ahb_import_info);
4774 if (result != VK_SUCCESS)
4775 goto fail;
4776 } else if(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID)) {
4777 result = radv_create_ahb_memory(device, mem, priority, pAllocateInfo);
4778 if (result != VK_SUCCESS)
4779 goto fail;
4780 } else if (import_info) {
4781 assert(import_info->handleType ==
4782 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4783 import_info->handleType ==
4784 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4785 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
4786 priority, NULL);
4787 if (!mem->bo) {
4788 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
4789 goto fail;
4790 } else {
4791 close(import_info->fd);
4792 }
4793 } else if (host_ptr_info) {
4794 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
4795 assert(radv_is_mem_type_gtt_cached(mem_type_index));
4796 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
4797 pAllocateInfo->allocationSize,
4798 priority);
4799 if (!mem->bo) {
4800 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
4801 goto fail;
4802 } else {
4803 mem->user_ptr = host_ptr_info->pHostPointer;
4804 }
4805 } else {
4806 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
4807 if (radv_is_mem_type_gtt_wc(mem_type_index) ||
4808 radv_is_mem_type_gtt_cached(mem_type_index))
4809 domain = RADEON_DOMAIN_GTT;
4810 else
4811 domain = RADEON_DOMAIN_VRAM;
4812
4813 if (radv_is_mem_type_vram(mem_type_index))
4814 flags |= RADEON_FLAG_NO_CPU_ACCESS;
4815 else
4816 flags |= RADEON_FLAG_CPU_ACCESS;
4817
4818 if (radv_is_mem_type_gtt_wc(mem_type_index))
4819 flags |= RADEON_FLAG_GTT_WC;
4820
4821 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
4822 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
4823 if (device->use_global_bo_list) {
4824 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
4825 }
4826 }
4827
4828 if (radv_is_mem_type_uncached(mem_type_index)) {
4829 assert(device->physical_device->rad_info.has_l2_uncached);
4830 flags |= RADEON_FLAG_VA_UNCACHED;
4831 }
4832
4833 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
4834 domain, flags, priority);
4835
4836 if (!mem->bo) {
4837 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
4838 goto fail;
4839 }
4840 mem->type_index = mem_type_index;
4841 }
4842
4843 result = radv_bo_list_add(device, mem->bo);
4844 if (result != VK_SUCCESS)
4845 goto fail;
4846
4847 *pMem = radv_device_memory_to_handle(mem);
4848
4849 return VK_SUCCESS;
4850
4851 fail:
4852 radv_free_memory(device, pAllocator,mem);
4853 vk_free2(&device->alloc, pAllocator, mem);
4854
4855 return result;
4856 }
4857
4858 VkResult radv_AllocateMemory(
4859 VkDevice _device,
4860 const VkMemoryAllocateInfo* pAllocateInfo,
4861 const VkAllocationCallbacks* pAllocator,
4862 VkDeviceMemory* pMem)
4863 {
4864 RADV_FROM_HANDLE(radv_device, device, _device);
4865 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
4866 }
4867
4868 void radv_FreeMemory(
4869 VkDevice _device,
4870 VkDeviceMemory _mem,
4871 const VkAllocationCallbacks* pAllocator)
4872 {
4873 RADV_FROM_HANDLE(radv_device, device, _device);
4874 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
4875
4876 radv_free_memory(device, pAllocator, mem);
4877 }
4878
4879 VkResult radv_MapMemory(
4880 VkDevice _device,
4881 VkDeviceMemory _memory,
4882 VkDeviceSize offset,
4883 VkDeviceSize size,
4884 VkMemoryMapFlags flags,
4885 void** ppData)
4886 {
4887 RADV_FROM_HANDLE(radv_device, device, _device);
4888 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
4889
4890 if (mem == NULL) {
4891 *ppData = NULL;
4892 return VK_SUCCESS;
4893 }
4894
4895 if (mem->user_ptr)
4896 *ppData = mem->user_ptr;
4897 else
4898 *ppData = device->ws->buffer_map(mem->bo);
4899
4900 if (*ppData) {
4901 *ppData += offset;
4902 return VK_SUCCESS;
4903 }
4904
4905 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
4906 }
4907
4908 void radv_UnmapMemory(
4909 VkDevice _device,
4910 VkDeviceMemory _memory)
4911 {
4912 RADV_FROM_HANDLE(radv_device, device, _device);
4913 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
4914
4915 if (mem == NULL)
4916 return;
4917
4918 if (mem->user_ptr == NULL)
4919 device->ws->buffer_unmap(mem->bo);
4920 }
4921
4922 VkResult radv_FlushMappedMemoryRanges(
4923 VkDevice _device,
4924 uint32_t memoryRangeCount,
4925 const VkMappedMemoryRange* pMemoryRanges)
4926 {
4927 return VK_SUCCESS;
4928 }
4929
4930 VkResult radv_InvalidateMappedMemoryRanges(
4931 VkDevice _device,
4932 uint32_t memoryRangeCount,
4933 const VkMappedMemoryRange* pMemoryRanges)
4934 {
4935 return VK_SUCCESS;
4936 }
4937
4938 void radv_GetBufferMemoryRequirements(
4939 VkDevice _device,
4940 VkBuffer _buffer,
4941 VkMemoryRequirements* pMemoryRequirements)
4942 {
4943 RADV_FROM_HANDLE(radv_device, device, _device);
4944 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4945
4946 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
4947
4948 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4949 pMemoryRequirements->alignment = 4096;
4950 else
4951 pMemoryRequirements->alignment = 16;
4952
4953 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
4954 }
4955
4956 void radv_GetBufferMemoryRequirements2(
4957 VkDevice device,
4958 const VkBufferMemoryRequirementsInfo2 *pInfo,
4959 VkMemoryRequirements2 *pMemoryRequirements)
4960 {
4961 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
4962 &pMemoryRequirements->memoryRequirements);
4963 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4964 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
4965 switch (ext->sType) {
4966 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
4967 VkMemoryDedicatedRequirements *req =
4968 (VkMemoryDedicatedRequirements *) ext;
4969 req->requiresDedicatedAllocation = buffer->shareable;
4970 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
4971 break;
4972 }
4973 default:
4974 break;
4975 }
4976 }
4977 }
4978
4979 void radv_GetImageMemoryRequirements(
4980 VkDevice _device,
4981 VkImage _image,
4982 VkMemoryRequirements* pMemoryRequirements)
4983 {
4984 RADV_FROM_HANDLE(radv_device, device, _device);
4985 RADV_FROM_HANDLE(radv_image, image, _image);
4986
4987 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
4988
4989 pMemoryRequirements->size = image->size;
4990 pMemoryRequirements->alignment = image->alignment;
4991 }
4992
4993 void radv_GetImageMemoryRequirements2(
4994 VkDevice device,
4995 const VkImageMemoryRequirementsInfo2 *pInfo,
4996 VkMemoryRequirements2 *pMemoryRequirements)
4997 {
4998 radv_GetImageMemoryRequirements(device, pInfo->image,
4999 &pMemoryRequirements->memoryRequirements);
5000
5001 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
5002
5003 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5004 switch (ext->sType) {
5005 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5006 VkMemoryDedicatedRequirements *req =
5007 (VkMemoryDedicatedRequirements *) ext;
5008 req->requiresDedicatedAllocation = image->shareable;
5009 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5010 break;
5011 }
5012 default:
5013 break;
5014 }
5015 }
5016 }
5017
5018 void radv_GetImageSparseMemoryRequirements(
5019 VkDevice device,
5020 VkImage image,
5021 uint32_t* pSparseMemoryRequirementCount,
5022 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
5023 {
5024 stub();
5025 }
5026
5027 void radv_GetImageSparseMemoryRequirements2(
5028 VkDevice device,
5029 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
5030 uint32_t* pSparseMemoryRequirementCount,
5031 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
5032 {
5033 stub();
5034 }
5035
5036 void radv_GetDeviceMemoryCommitment(
5037 VkDevice device,
5038 VkDeviceMemory memory,
5039 VkDeviceSize* pCommittedMemoryInBytes)
5040 {
5041 *pCommittedMemoryInBytes = 0;
5042 }
5043
5044 VkResult radv_BindBufferMemory2(VkDevice device,
5045 uint32_t bindInfoCount,
5046 const VkBindBufferMemoryInfo *pBindInfos)
5047 {
5048 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5049 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5050 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
5051
5052 if (mem) {
5053 buffer->bo = mem->bo;
5054 buffer->offset = pBindInfos[i].memoryOffset;
5055 } else {
5056 buffer->bo = NULL;
5057 }
5058 }
5059 return VK_SUCCESS;
5060 }
5061
5062 VkResult radv_BindBufferMemory(
5063 VkDevice device,
5064 VkBuffer buffer,
5065 VkDeviceMemory memory,
5066 VkDeviceSize memoryOffset)
5067 {
5068 const VkBindBufferMemoryInfo info = {
5069 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5070 .buffer = buffer,
5071 .memory = memory,
5072 .memoryOffset = memoryOffset
5073 };
5074
5075 return radv_BindBufferMemory2(device, 1, &info);
5076 }
5077
5078 VkResult radv_BindImageMemory2(VkDevice device,
5079 uint32_t bindInfoCount,
5080 const VkBindImageMemoryInfo *pBindInfos)
5081 {
5082 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5083 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5084 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
5085
5086 if (mem) {
5087 image->bo = mem->bo;
5088 image->offset = pBindInfos[i].memoryOffset;
5089 } else {
5090 image->bo = NULL;
5091 image->offset = 0;
5092 }
5093 }
5094 return VK_SUCCESS;
5095 }
5096
5097
5098 VkResult radv_BindImageMemory(
5099 VkDevice device,
5100 VkImage image,
5101 VkDeviceMemory memory,
5102 VkDeviceSize memoryOffset)
5103 {
5104 const VkBindImageMemoryInfo info = {
5105 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5106 .image = image,
5107 .memory = memory,
5108 .memoryOffset = memoryOffset
5109 };
5110
5111 return radv_BindImageMemory2(device, 1, &info);
5112 }
5113
5114 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo *info)
5115 {
5116 return info->bufferBindCount ||
5117 info->imageOpaqueBindCount ||
5118 info->imageBindCount ||
5119 info->waitSemaphoreCount ||
5120 info->signalSemaphoreCount;
5121 }
5122
5123 VkResult radv_QueueBindSparse(
5124 VkQueue _queue,
5125 uint32_t bindInfoCount,
5126 const VkBindSparseInfo* pBindInfo,
5127 VkFence fence)
5128 {
5129 RADV_FROM_HANDLE(radv_queue, queue, _queue);
5130 VkResult result;
5131 uint32_t fence_idx = 0;
5132
5133 if (fence != VK_NULL_HANDLE) {
5134 for (uint32_t i = 0; i < bindInfoCount; ++i)
5135 if (radv_sparse_bind_has_effects(pBindInfo + i))
5136 fence_idx = i;
5137 } else
5138 fence_idx = UINT32_MAX;
5139
5140 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5141 if (i != fence_idx && !radv_sparse_bind_has_effects(pBindInfo + i))
5142 continue;
5143
5144 const VkTimelineSemaphoreSubmitInfoKHR *timeline_info =
5145 vk_find_struct_const(pBindInfo[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO_KHR);
5146
5147 VkResult result = radv_queue_submit(queue, &(struct radv_queue_submission) {
5148 .buffer_binds = pBindInfo[i].pBufferBinds,
5149 .buffer_bind_count = pBindInfo[i].bufferBindCount,
5150 .image_opaque_binds = pBindInfo[i].pImageOpaqueBinds,
5151 .image_opaque_bind_count = pBindInfo[i].imageOpaqueBindCount,
5152 .wait_semaphores = pBindInfo[i].pWaitSemaphores,
5153 .wait_semaphore_count = pBindInfo[i].waitSemaphoreCount,
5154 .signal_semaphores = pBindInfo[i].pSignalSemaphores,
5155 .signal_semaphore_count = pBindInfo[i].signalSemaphoreCount,
5156 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
5157 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
5158 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
5159 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
5160 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
5161 });
5162
5163 if (result != VK_SUCCESS)
5164 return result;
5165 }
5166
5167 if (fence != VK_NULL_HANDLE && !bindInfoCount) {
5168 result = radv_signal_fence(queue, fence);
5169 if (result != VK_SUCCESS)
5170 return result;
5171 }
5172
5173 return VK_SUCCESS;
5174 }
5175
5176 VkResult radv_CreateFence(
5177 VkDevice _device,
5178 const VkFenceCreateInfo* pCreateInfo,
5179 const VkAllocationCallbacks* pAllocator,
5180 VkFence* pFence)
5181 {
5182 RADV_FROM_HANDLE(radv_device, device, _device);
5183 const VkExportFenceCreateInfo *export =
5184 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
5185 VkExternalFenceHandleTypeFlags handleTypes =
5186 export ? export->handleTypes : 0;
5187
5188 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
5189 sizeof(*fence), 8,
5190 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5191
5192 if (!fence)
5193 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5194
5195 fence->fence_wsi = NULL;
5196 fence->temp_syncobj = 0;
5197 if (device->always_use_syncobj || handleTypes) {
5198 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
5199 if (ret) {
5200 vk_free2(&device->alloc, pAllocator, fence);
5201 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5202 }
5203 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
5204 device->ws->signal_syncobj(device->ws, fence->syncobj);
5205 }
5206 fence->fence = NULL;
5207 } else {
5208 fence->fence = device->ws->create_fence();
5209 if (!fence->fence) {
5210 vk_free2(&device->alloc, pAllocator, fence);
5211 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5212 }
5213 fence->syncobj = 0;
5214 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5215 device->ws->signal_fence(fence->fence);
5216 }
5217
5218 *pFence = radv_fence_to_handle(fence);
5219
5220 return VK_SUCCESS;
5221 }
5222
5223 void radv_DestroyFence(
5224 VkDevice _device,
5225 VkFence _fence,
5226 const VkAllocationCallbacks* pAllocator)
5227 {
5228 RADV_FROM_HANDLE(radv_device, device, _device);
5229 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5230
5231 if (!fence)
5232 return;
5233
5234 if (fence->temp_syncobj)
5235 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
5236 if (fence->syncobj)
5237 device->ws->destroy_syncobj(device->ws, fence->syncobj);
5238 if (fence->fence)
5239 device->ws->destroy_fence(fence->fence);
5240 if (fence->fence_wsi)
5241 fence->fence_wsi->destroy(fence->fence_wsi);
5242 vk_free2(&device->alloc, pAllocator, fence);
5243 }
5244
5245
5246 uint64_t radv_get_current_time(void)
5247 {
5248 struct timespec tv;
5249 clock_gettime(CLOCK_MONOTONIC, &tv);
5250 return tv.tv_nsec + tv.tv_sec*1000000000ull;
5251 }
5252
5253 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
5254 {
5255 uint64_t current_time = radv_get_current_time();
5256
5257 timeout = MIN2(UINT64_MAX - current_time, timeout);
5258
5259 return current_time + timeout;
5260 }
5261
5262
5263 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
5264 uint32_t fenceCount, const VkFence *pFences)
5265 {
5266 for (uint32_t i = 0; i < fenceCount; ++i) {
5267 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5268 if (fence->fence == NULL || fence->syncobj ||
5269 fence->temp_syncobj || fence->fence_wsi ||
5270 (!device->ws->is_fence_waitable(fence->fence)))
5271 return false;
5272 }
5273 return true;
5274 }
5275
5276 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
5277 {
5278 for (uint32_t i = 0; i < fenceCount; ++i) {
5279 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5280 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
5281 return false;
5282 }
5283 return true;
5284 }
5285
5286 VkResult radv_WaitForFences(
5287 VkDevice _device,
5288 uint32_t fenceCount,
5289 const VkFence* pFences,
5290 VkBool32 waitAll,
5291 uint64_t timeout)
5292 {
5293 RADV_FROM_HANDLE(radv_device, device, _device);
5294 timeout = radv_get_absolute_timeout(timeout);
5295
5296 if (device->always_use_syncobj &&
5297 radv_all_fences_syncobj(fenceCount, pFences))
5298 {
5299 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
5300 if (!handles)
5301 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5302
5303 for (uint32_t i = 0; i < fenceCount; ++i) {
5304 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5305 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
5306 }
5307
5308 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
5309
5310 free(handles);
5311 return success ? VK_SUCCESS : VK_TIMEOUT;
5312 }
5313
5314 if (!waitAll && fenceCount > 1) {
5315 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5316 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
5317 uint32_t wait_count = 0;
5318 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
5319 if (!fences)
5320 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5321
5322 for (uint32_t i = 0; i < fenceCount; ++i) {
5323 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5324
5325 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
5326 free(fences);
5327 return VK_SUCCESS;
5328 }
5329
5330 fences[wait_count++] = fence->fence;
5331 }
5332
5333 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
5334 waitAll, timeout - radv_get_current_time());
5335
5336 free(fences);
5337 return success ? VK_SUCCESS : VK_TIMEOUT;
5338 }
5339
5340 while(radv_get_current_time() <= timeout) {
5341 for (uint32_t i = 0; i < fenceCount; ++i) {
5342 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
5343 return VK_SUCCESS;
5344 }
5345 }
5346 return VK_TIMEOUT;
5347 }
5348
5349 for (uint32_t i = 0; i < fenceCount; ++i) {
5350 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5351 bool expired = false;
5352
5353 if (fence->temp_syncobj) {
5354 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
5355 return VK_TIMEOUT;
5356 continue;
5357 }
5358
5359 if (fence->syncobj) {
5360 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
5361 return VK_TIMEOUT;
5362 continue;
5363 }
5364
5365 if (fence->fence) {
5366 if (!device->ws->is_fence_waitable(fence->fence)) {
5367 while(!device->ws->is_fence_waitable(fence->fence) &&
5368 radv_get_current_time() <= timeout)
5369 /* Do nothing */;
5370 }
5371
5372 expired = device->ws->fence_wait(device->ws,
5373 fence->fence,
5374 true, timeout);
5375 if (!expired)
5376 return VK_TIMEOUT;
5377 }
5378
5379 if (fence->fence_wsi) {
5380 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
5381 if (result != VK_SUCCESS)
5382 return result;
5383 }
5384 }
5385
5386 return VK_SUCCESS;
5387 }
5388
5389 VkResult radv_ResetFences(VkDevice _device,
5390 uint32_t fenceCount,
5391 const VkFence *pFences)
5392 {
5393 RADV_FROM_HANDLE(radv_device, device, _device);
5394
5395 for (unsigned i = 0; i < fenceCount; ++i) {
5396 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5397 if (fence->fence)
5398 device->ws->reset_fence(fence->fence);
5399
5400 /* Per spec, we first restore the permanent payload, and then reset, so
5401 * having a temp syncobj should not skip resetting the permanent syncobj. */
5402 if (fence->temp_syncobj) {
5403 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
5404 fence->temp_syncobj = 0;
5405 }
5406
5407 if (fence->syncobj) {
5408 device->ws->reset_syncobj(device->ws, fence->syncobj);
5409 }
5410 }
5411
5412 return VK_SUCCESS;
5413 }
5414
5415 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
5416 {
5417 RADV_FROM_HANDLE(radv_device, device, _device);
5418 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5419
5420 if (fence->temp_syncobj) {
5421 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
5422 return success ? VK_SUCCESS : VK_NOT_READY;
5423 }
5424
5425 if (fence->syncobj) {
5426 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
5427 return success ? VK_SUCCESS : VK_NOT_READY;
5428 }
5429
5430 if (fence->fence) {
5431 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
5432 return VK_NOT_READY;
5433 }
5434 if (fence->fence_wsi) {
5435 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
5436
5437 if (result != VK_SUCCESS) {
5438 if (result == VK_TIMEOUT)
5439 return VK_NOT_READY;
5440 return result;
5441 }
5442 }
5443 return VK_SUCCESS;
5444 }
5445
5446
5447 // Queue semaphore functions
5448
5449 static void
5450 radv_create_timeline(struct radv_timeline *timeline, uint64_t value)
5451 {
5452 timeline->highest_signaled = value;
5453 timeline->highest_submitted = value;
5454 list_inithead(&timeline->points);
5455 list_inithead(&timeline->free_points);
5456 list_inithead(&timeline->waiters);
5457 pthread_mutex_init(&timeline->mutex, NULL);
5458 }
5459
5460 static void
5461 radv_destroy_timeline(struct radv_device *device,
5462 struct radv_timeline *timeline)
5463 {
5464 list_for_each_entry_safe(struct radv_timeline_point, point,
5465 &timeline->free_points, list) {
5466 list_del(&point->list);
5467 device->ws->destroy_syncobj(device->ws, point->syncobj);
5468 free(point);
5469 }
5470 list_for_each_entry_safe(struct radv_timeline_point, point,
5471 &timeline->points, list) {
5472 list_del(&point->list);
5473 device->ws->destroy_syncobj(device->ws, point->syncobj);
5474 free(point);
5475 }
5476 pthread_mutex_destroy(&timeline->mutex);
5477 }
5478
5479 static void
5480 radv_timeline_gc_locked(struct radv_device *device,
5481 struct radv_timeline *timeline)
5482 {
5483 list_for_each_entry_safe(struct radv_timeline_point, point,
5484 &timeline->points, list) {
5485 if (point->wait_count || point->value > timeline->highest_submitted)
5486 return;
5487
5488 if (device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, 0)) {
5489 timeline->highest_signaled = point->value;
5490 list_del(&point->list);
5491 list_add(&point->list, &timeline->free_points);
5492 }
5493 }
5494 }
5495
5496 static struct radv_timeline_point *
5497 radv_timeline_find_point_at_least_locked(struct radv_device *device,
5498 struct radv_timeline *timeline,
5499 uint64_t p)
5500 {
5501 radv_timeline_gc_locked(device, timeline);
5502
5503 if (p <= timeline->highest_signaled)
5504 return NULL;
5505
5506 list_for_each_entry(struct radv_timeline_point, point,
5507 &timeline->points, list) {
5508 if (point->value >= p) {
5509 ++point->wait_count;
5510 return point;
5511 }
5512 }
5513 return NULL;
5514 }
5515
5516 static struct radv_timeline_point *
5517 radv_timeline_add_point_locked(struct radv_device *device,
5518 struct radv_timeline *timeline,
5519 uint64_t p)
5520 {
5521 radv_timeline_gc_locked(device, timeline);
5522
5523 struct radv_timeline_point *ret = NULL;
5524 struct radv_timeline_point *prev = NULL;
5525
5526 if (p <= timeline->highest_signaled)
5527 return NULL;
5528
5529 list_for_each_entry(struct radv_timeline_point, point,
5530 &timeline->points, list) {
5531 if (point->value == p) {
5532 return NULL;
5533 }
5534
5535 if (point->value < p)
5536 prev = point;
5537 }
5538
5539 if (list_is_empty(&timeline->free_points)) {
5540 ret = malloc(sizeof(struct radv_timeline_point));
5541 device->ws->create_syncobj(device->ws, &ret->syncobj);
5542 } else {
5543 ret = list_first_entry(&timeline->free_points, struct radv_timeline_point, list);
5544 list_del(&ret->list);
5545
5546 device->ws->reset_syncobj(device->ws, ret->syncobj);
5547 }
5548
5549 ret->value = p;
5550 ret->wait_count = 1;
5551
5552 if (prev) {
5553 list_add(&ret->list, &prev->list);
5554 } else {
5555 list_addtail(&ret->list, &timeline->points);
5556 }
5557 return ret;
5558 }
5559
5560
5561 static VkResult
5562 radv_timeline_wait_locked(struct radv_device *device,
5563 struct radv_timeline *timeline,
5564 uint64_t value,
5565 uint64_t abs_timeout)
5566 {
5567 while(timeline->highest_submitted < value) {
5568 struct timespec abstime;
5569 timespec_from_nsec(&abstime, abs_timeout);
5570
5571 pthread_cond_timedwait(&device->timeline_cond, &timeline->mutex, &abstime);
5572
5573 if (radv_get_current_time() >= abs_timeout && timeline->highest_submitted < value)
5574 return VK_TIMEOUT;
5575 }
5576
5577 struct radv_timeline_point *point = radv_timeline_find_point_at_least_locked(device, timeline, value);
5578 if (!point)
5579 return VK_SUCCESS;
5580
5581 pthread_mutex_unlock(&timeline->mutex);
5582
5583 bool success = device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, abs_timeout);
5584
5585 pthread_mutex_lock(&timeline->mutex);
5586 point->wait_count--;
5587 return success ? VK_SUCCESS : VK_TIMEOUT;
5588 }
5589
5590 static void
5591 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
5592 struct list_head *processing_list)
5593 {
5594 list_for_each_entry_safe(struct radv_timeline_waiter, waiter,
5595 &timeline->waiters, list) {
5596 if (waiter->value > timeline->highest_submitted)
5597 continue;
5598
5599 if (p_atomic_dec_zero(&waiter->submission->submission_wait_count)) {
5600 list_addtail(&waiter->submission->processing_list, processing_list);
5601 }
5602 list_del(&waiter->list);
5603 }
5604 }
5605
5606 static
5607 void radv_destroy_semaphore_part(struct radv_device *device,
5608 struct radv_semaphore_part *part)
5609 {
5610 switch(part->kind) {
5611 case RADV_SEMAPHORE_NONE:
5612 break;
5613 case RADV_SEMAPHORE_WINSYS:
5614 device->ws->destroy_sem(part->ws_sem);
5615 break;
5616 case RADV_SEMAPHORE_TIMELINE:
5617 radv_destroy_timeline(device, &part->timeline);
5618 break;
5619 case RADV_SEMAPHORE_SYNCOBJ:
5620 device->ws->destroy_syncobj(device->ws, part->syncobj);
5621 break;
5622 }
5623 part->kind = RADV_SEMAPHORE_NONE;
5624 }
5625
5626 static VkSemaphoreTypeKHR
5627 radv_get_semaphore_type(const void *pNext, uint64_t *initial_value)
5628 {
5629 const VkSemaphoreTypeCreateInfoKHR *type_info =
5630 vk_find_struct_const(pNext, SEMAPHORE_TYPE_CREATE_INFO_KHR);
5631
5632 if (!type_info)
5633 return VK_SEMAPHORE_TYPE_BINARY_KHR;
5634
5635 if (initial_value)
5636 *initial_value = type_info->initialValue;
5637 return type_info->semaphoreType;
5638 }
5639
5640 VkResult radv_CreateSemaphore(
5641 VkDevice _device,
5642 const VkSemaphoreCreateInfo* pCreateInfo,
5643 const VkAllocationCallbacks* pAllocator,
5644 VkSemaphore* pSemaphore)
5645 {
5646 RADV_FROM_HANDLE(radv_device, device, _device);
5647 const VkExportSemaphoreCreateInfo *export =
5648 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
5649 VkExternalSemaphoreHandleTypeFlags handleTypes =
5650 export ? export->handleTypes : 0;
5651 uint64_t initial_value = 0;
5652 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pCreateInfo->pNext, &initial_value);
5653
5654 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
5655 sizeof(*sem), 8,
5656 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5657 if (!sem)
5658 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5659
5660 sem->temporary.kind = RADV_SEMAPHORE_NONE;
5661 sem->permanent.kind = RADV_SEMAPHORE_NONE;
5662
5663 if (type == VK_SEMAPHORE_TYPE_TIMELINE_KHR) {
5664 radv_create_timeline(&sem->permanent.timeline, initial_value);
5665 sem->permanent.kind = RADV_SEMAPHORE_TIMELINE;
5666 } else if (device->always_use_syncobj || handleTypes) {
5667 assert (device->physical_device->rad_info.has_syncobj);
5668 int ret = device->ws->create_syncobj(device->ws, &sem->permanent.syncobj);
5669 if (ret) {
5670 vk_free2(&device->alloc, pAllocator, sem);
5671 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5672 }
5673 sem->permanent.kind = RADV_SEMAPHORE_SYNCOBJ;
5674 } else {
5675 sem->permanent.ws_sem = device->ws->create_sem(device->ws);
5676 if (!sem->permanent.ws_sem) {
5677 vk_free2(&device->alloc, pAllocator, sem);
5678 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5679 }
5680 sem->permanent.kind = RADV_SEMAPHORE_WINSYS;
5681 }
5682
5683 *pSemaphore = radv_semaphore_to_handle(sem);
5684 return VK_SUCCESS;
5685 }
5686
5687 void radv_DestroySemaphore(
5688 VkDevice _device,
5689 VkSemaphore _semaphore,
5690 const VkAllocationCallbacks* pAllocator)
5691 {
5692 RADV_FROM_HANDLE(radv_device, device, _device);
5693 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
5694 if (!_semaphore)
5695 return;
5696
5697 radv_destroy_semaphore_part(device, &sem->temporary);
5698 radv_destroy_semaphore_part(device, &sem->permanent);
5699 vk_free2(&device->alloc, pAllocator, sem);
5700 }
5701
5702 VkResult
5703 radv_GetSemaphoreCounterValueKHR(VkDevice _device,
5704 VkSemaphore _semaphore,
5705 uint64_t* pValue)
5706 {
5707 RADV_FROM_HANDLE(radv_device, device, _device);
5708 RADV_FROM_HANDLE(radv_semaphore, semaphore, _semaphore);
5709
5710 struct radv_semaphore_part *part =
5711 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
5712
5713 switch (part->kind) {
5714 case RADV_SEMAPHORE_TIMELINE: {
5715 pthread_mutex_lock(&part->timeline.mutex);
5716 radv_timeline_gc_locked(device, &part->timeline);
5717 *pValue = part->timeline.highest_signaled;
5718 pthread_mutex_unlock(&part->timeline.mutex);
5719 return VK_SUCCESS;
5720 }
5721 case RADV_SEMAPHORE_NONE:
5722 case RADV_SEMAPHORE_SYNCOBJ:
5723 case RADV_SEMAPHORE_WINSYS:
5724 unreachable("Invalid semaphore type");
5725 }
5726 unreachable("Unhandled semaphore type");
5727 }
5728
5729
5730 static VkResult
5731 radv_wait_timelines(struct radv_device *device,
5732 const VkSemaphoreWaitInfoKHR* pWaitInfo,
5733 uint64_t abs_timeout)
5734 {
5735 if ((pWaitInfo->flags & VK_SEMAPHORE_WAIT_ANY_BIT_KHR) && pWaitInfo->semaphoreCount > 1) {
5736 for (;;) {
5737 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
5738 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
5739 pthread_mutex_lock(&semaphore->permanent.timeline.mutex);
5740 VkResult result = radv_timeline_wait_locked(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], 0);
5741 pthread_mutex_unlock(&semaphore->permanent.timeline.mutex);
5742
5743 if (result == VK_SUCCESS)
5744 return VK_SUCCESS;
5745 }
5746 if (radv_get_current_time() > abs_timeout)
5747 return VK_TIMEOUT;
5748 }
5749 }
5750
5751 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
5752 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
5753 pthread_mutex_lock(&semaphore->permanent.timeline.mutex);
5754 VkResult result = radv_timeline_wait_locked(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], abs_timeout);
5755 pthread_mutex_unlock(&semaphore->permanent.timeline.mutex);
5756
5757 if (result != VK_SUCCESS)
5758 return result;
5759 }
5760 return VK_SUCCESS;
5761 }
5762 VkResult
5763 radv_WaitSemaphoresKHR(VkDevice _device,
5764 const VkSemaphoreWaitInfoKHR* pWaitInfo,
5765 uint64_t timeout)
5766 {
5767 RADV_FROM_HANDLE(radv_device, device, _device);
5768 uint64_t abs_timeout = radv_get_absolute_timeout(timeout);
5769 return radv_wait_timelines(device, pWaitInfo, abs_timeout);
5770 }
5771
5772 VkResult
5773 radv_SignalSemaphoreKHR(VkDevice _device,
5774 const VkSemaphoreSignalInfoKHR* pSignalInfo)
5775 {
5776 RADV_FROM_HANDLE(radv_device, device, _device);
5777 RADV_FROM_HANDLE(radv_semaphore, semaphore, pSignalInfo->semaphore);
5778
5779 struct radv_semaphore_part *part =
5780 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
5781
5782 switch(part->kind) {
5783 case RADV_SEMAPHORE_TIMELINE: {
5784 pthread_mutex_lock(&part->timeline.mutex);
5785 radv_timeline_gc_locked(device, &part->timeline);
5786 part->timeline.highest_submitted = MAX2(part->timeline.highest_submitted, pSignalInfo->value);
5787 part->timeline.highest_signaled = MAX2(part->timeline.highest_signaled, pSignalInfo->value);
5788
5789 struct list_head processing_list;
5790 list_inithead(&processing_list);
5791 radv_timeline_trigger_waiters_locked(&part->timeline, &processing_list);
5792 pthread_mutex_unlock(&part->timeline.mutex);
5793
5794 return radv_process_submissions(&processing_list);
5795 }
5796 case RADV_SEMAPHORE_NONE:
5797 case RADV_SEMAPHORE_SYNCOBJ:
5798 case RADV_SEMAPHORE_WINSYS:
5799 unreachable("Invalid semaphore type");
5800 }
5801 return VK_SUCCESS;
5802 }
5803
5804
5805
5806 VkResult radv_CreateEvent(
5807 VkDevice _device,
5808 const VkEventCreateInfo* pCreateInfo,
5809 const VkAllocationCallbacks* pAllocator,
5810 VkEvent* pEvent)
5811 {
5812 RADV_FROM_HANDLE(radv_device, device, _device);
5813 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
5814 sizeof(*event), 8,
5815 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5816
5817 if (!event)
5818 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5819
5820 event->bo = device->ws->buffer_create(device->ws, 8, 8,
5821 RADEON_DOMAIN_GTT,
5822 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
5823 RADV_BO_PRIORITY_FENCE);
5824 if (!event->bo) {
5825 vk_free2(&device->alloc, pAllocator, event);
5826 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5827 }
5828
5829 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
5830
5831 *pEvent = radv_event_to_handle(event);
5832
5833 return VK_SUCCESS;
5834 }
5835
5836 void radv_DestroyEvent(
5837 VkDevice _device,
5838 VkEvent _event,
5839 const VkAllocationCallbacks* pAllocator)
5840 {
5841 RADV_FROM_HANDLE(radv_device, device, _device);
5842 RADV_FROM_HANDLE(radv_event, event, _event);
5843
5844 if (!event)
5845 return;
5846 device->ws->buffer_destroy(event->bo);
5847 vk_free2(&device->alloc, pAllocator, event);
5848 }
5849
5850 VkResult radv_GetEventStatus(
5851 VkDevice _device,
5852 VkEvent _event)
5853 {
5854 RADV_FROM_HANDLE(radv_event, event, _event);
5855
5856 if (*event->map == 1)
5857 return VK_EVENT_SET;
5858 return VK_EVENT_RESET;
5859 }
5860
5861 VkResult radv_SetEvent(
5862 VkDevice _device,
5863 VkEvent _event)
5864 {
5865 RADV_FROM_HANDLE(radv_event, event, _event);
5866 *event->map = 1;
5867
5868 return VK_SUCCESS;
5869 }
5870
5871 VkResult radv_ResetEvent(
5872 VkDevice _device,
5873 VkEvent _event)
5874 {
5875 RADV_FROM_HANDLE(radv_event, event, _event);
5876 *event->map = 0;
5877
5878 return VK_SUCCESS;
5879 }
5880
5881 VkResult radv_CreateBuffer(
5882 VkDevice _device,
5883 const VkBufferCreateInfo* pCreateInfo,
5884 const VkAllocationCallbacks* pAllocator,
5885 VkBuffer* pBuffer)
5886 {
5887 RADV_FROM_HANDLE(radv_device, device, _device);
5888 struct radv_buffer *buffer;
5889
5890 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
5891
5892 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
5893 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5894 if (buffer == NULL)
5895 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5896
5897 buffer->size = pCreateInfo->size;
5898 buffer->usage = pCreateInfo->usage;
5899 buffer->bo = NULL;
5900 buffer->offset = 0;
5901 buffer->flags = pCreateInfo->flags;
5902
5903 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
5904 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
5905
5906 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
5907 buffer->bo = device->ws->buffer_create(device->ws,
5908 align64(buffer->size, 4096),
5909 4096, 0, RADEON_FLAG_VIRTUAL,
5910 RADV_BO_PRIORITY_VIRTUAL);
5911 if (!buffer->bo) {
5912 vk_free2(&device->alloc, pAllocator, buffer);
5913 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5914 }
5915 }
5916
5917 *pBuffer = radv_buffer_to_handle(buffer);
5918
5919 return VK_SUCCESS;
5920 }
5921
5922 void radv_DestroyBuffer(
5923 VkDevice _device,
5924 VkBuffer _buffer,
5925 const VkAllocationCallbacks* pAllocator)
5926 {
5927 RADV_FROM_HANDLE(radv_device, device, _device);
5928 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5929
5930 if (!buffer)
5931 return;
5932
5933 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
5934 device->ws->buffer_destroy(buffer->bo);
5935
5936 vk_free2(&device->alloc, pAllocator, buffer);
5937 }
5938
5939 VkDeviceAddress radv_GetBufferDeviceAddressKHR(
5940 VkDevice device,
5941 const VkBufferDeviceAddressInfoKHR* pInfo)
5942 {
5943 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
5944 return radv_buffer_get_va(buffer->bo) + buffer->offset;
5945 }
5946
5947
5948 uint64_t radv_GetBufferOpaqueCaptureAddressKHR(VkDevice device,
5949 const VkBufferDeviceAddressInfoKHR* pInfo)
5950 {
5951 return 0;
5952 }
5953
5954 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddressKHR(VkDevice device,
5955 const VkDeviceMemoryOpaqueCaptureAddressInfoKHR* pInfo)
5956 {
5957 return 0;
5958 }
5959
5960 static inline unsigned
5961 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
5962 {
5963 if (stencil)
5964 return plane->surface.u.legacy.stencil_tiling_index[level];
5965 else
5966 return plane->surface.u.legacy.tiling_index[level];
5967 }
5968
5969 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
5970 {
5971 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
5972 }
5973
5974 static uint32_t
5975 radv_init_dcc_control_reg(struct radv_device *device,
5976 struct radv_image_view *iview)
5977 {
5978 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
5979 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
5980 unsigned max_compressed_block_size;
5981 unsigned independent_128b_blocks;
5982 unsigned independent_64b_blocks;
5983
5984 if (!radv_dcc_enabled(iview->image, iview->base_mip))
5985 return 0;
5986
5987 if (!device->physical_device->rad_info.has_dedicated_vram) {
5988 /* amdvlk: [min-compressed-block-size] should be set to 32 for
5989 * dGPU and 64 for APU because all of our APUs to date use
5990 * DIMMs which have a request granularity size of 64B while all
5991 * other chips have a 32B request size.
5992 */
5993 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
5994 }
5995
5996 if (device->physical_device->rad_info.chip_class >= GFX10) {
5997 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
5998 independent_64b_blocks = 0;
5999 independent_128b_blocks = 1;
6000 } else {
6001 independent_128b_blocks = 0;
6002
6003 if (iview->image->info.samples > 1) {
6004 if (iview->image->planes[0].surface.bpe == 1)
6005 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6006 else if (iview->image->planes[0].surface.bpe == 2)
6007 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6008 }
6009
6010 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
6011 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
6012 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
6013 /* If this DCC image is potentially going to be used in texture
6014 * fetches, we need some special settings.
6015 */
6016 independent_64b_blocks = 1;
6017 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6018 } else {
6019 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6020 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6021 * big as possible for better compression state.
6022 */
6023 independent_64b_blocks = 0;
6024 max_compressed_block_size = max_uncompressed_block_size;
6025 }
6026 }
6027
6028 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
6029 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
6030 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
6031 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
6032 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
6033 }
6034
6035 void
6036 radv_initialise_color_surface(struct radv_device *device,
6037 struct radv_color_buffer_info *cb,
6038 struct radv_image_view *iview)
6039 {
6040 const struct vk_format_description *desc;
6041 unsigned ntype, format, swap, endian;
6042 unsigned blend_clamp = 0, blend_bypass = 0;
6043 uint64_t va;
6044 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
6045 const struct radeon_surf *surf = &plane->surface;
6046
6047 desc = vk_format_description(iview->vk_format);
6048
6049 memset(cb, 0, sizeof(*cb));
6050
6051 /* Intensity is implemented as Red, so treat it that way. */
6052 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
6053
6054 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
6055
6056 cb->cb_color_base = va >> 8;
6057
6058 if (device->physical_device->rad_info.chip_class >= GFX9) {
6059 struct gfx9_surf_meta_flags meta;
6060 if (iview->image->dcc_offset)
6061 meta = surf->u.gfx9.dcc;
6062 else
6063 meta = surf->u.gfx9.cmask;
6064
6065 if (device->physical_device->rad_info.chip_class >= GFX10) {
6066 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6067 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6068 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
6069 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
6070 } else {
6071 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6072 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6073 S_028C74_RB_ALIGNED(meta.rb_aligned) |
6074 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
6075 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
6076 }
6077
6078 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
6079 cb->cb_color_base |= surf->tile_swizzle;
6080 } else {
6081 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
6082 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
6083
6084 cb->cb_color_base += level_info->offset >> 8;
6085 if (level_info->mode == RADEON_SURF_MODE_2D)
6086 cb->cb_color_base |= surf->tile_swizzle;
6087
6088 pitch_tile_max = level_info->nblk_x / 8 - 1;
6089 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
6090 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
6091
6092 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
6093 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
6094 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
6095
6096 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
6097
6098 if (radv_image_has_fmask(iview->image)) {
6099 if (device->physical_device->rad_info.chip_class >= GFX7)
6100 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
6101 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
6102 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
6103 } else {
6104 /* This must be set for fast clear to work without FMASK. */
6105 if (device->physical_device->rad_info.chip_class >= GFX7)
6106 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
6107 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
6108 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
6109 }
6110 }
6111
6112 /* CMASK variables */
6113 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6114 va += iview->image->cmask_offset;
6115 cb->cb_color_cmask = va >> 8;
6116
6117 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6118 va += iview->image->dcc_offset;
6119
6120 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
6121 device->physical_device->rad_info.chip_class <= GFX8)
6122 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
6123
6124 unsigned dcc_tile_swizzle = surf->tile_swizzle;
6125 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
6126
6127 cb->cb_dcc_base = va >> 8;
6128 cb->cb_dcc_base |= dcc_tile_swizzle;
6129
6130 /* GFX10 field has the same base shift as the GFX6 field. */
6131 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6132 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
6133 S_028C6C_SLICE_MAX_GFX10(max_slice);
6134
6135 if (iview->image->info.samples > 1) {
6136 unsigned log_samples = util_logbase2(iview->image->info.samples);
6137
6138 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
6139 S_028C74_NUM_FRAGMENTS(log_samples);
6140 }
6141
6142 if (radv_image_has_fmask(iview->image)) {
6143 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask_offset;
6144 cb->cb_color_fmask = va >> 8;
6145 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
6146 } else {
6147 cb->cb_color_fmask = cb->cb_color_base;
6148 }
6149
6150 ntype = radv_translate_color_numformat(iview->vk_format,
6151 desc,
6152 vk_format_get_first_non_void_channel(iview->vk_format));
6153 format = radv_translate_colorformat(iview->vk_format);
6154 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
6155 radv_finishme("Illegal color\n");
6156 swap = radv_translate_colorswap(iview->vk_format, false);
6157 endian = radv_colorformat_endian_swap(format);
6158
6159 /* blend clamp should be set for all NORM/SRGB types */
6160 if (ntype == V_028C70_NUMBER_UNORM ||
6161 ntype == V_028C70_NUMBER_SNORM ||
6162 ntype == V_028C70_NUMBER_SRGB)
6163 blend_clamp = 1;
6164
6165 /* set blend bypass according to docs if SINT/UINT or
6166 8/24 COLOR variants */
6167 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
6168 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
6169 format == V_028C70_COLOR_X24_8_32_FLOAT) {
6170 blend_clamp = 0;
6171 blend_bypass = 1;
6172 }
6173 #if 0
6174 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
6175 (format == V_028C70_COLOR_8 ||
6176 format == V_028C70_COLOR_8_8 ||
6177 format == V_028C70_COLOR_8_8_8_8))
6178 ->color_is_int8 = true;
6179 #endif
6180 cb->cb_color_info = S_028C70_FORMAT(format) |
6181 S_028C70_COMP_SWAP(swap) |
6182 S_028C70_BLEND_CLAMP(blend_clamp) |
6183 S_028C70_BLEND_BYPASS(blend_bypass) |
6184 S_028C70_SIMPLE_FLOAT(1) |
6185 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
6186 ntype != V_028C70_NUMBER_SNORM &&
6187 ntype != V_028C70_NUMBER_SRGB &&
6188 format != V_028C70_COLOR_8_24 &&
6189 format != V_028C70_COLOR_24_8) |
6190 S_028C70_NUMBER_TYPE(ntype) |
6191 S_028C70_ENDIAN(endian);
6192 if (radv_image_has_fmask(iview->image)) {
6193 cb->cb_color_info |= S_028C70_COMPRESSION(1);
6194 if (device->physical_device->rad_info.chip_class == GFX6) {
6195 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
6196 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
6197 }
6198
6199 if (radv_image_is_tc_compat_cmask(iview->image)) {
6200 /* Allow the texture block to read FMASK directly
6201 * without decompressing it. This bit must be cleared
6202 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6203 * otherwise the operation doesn't happen.
6204 */
6205 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6206
6207 /* Set CMASK into a tiling format that allows the
6208 * texture block to read it.
6209 */
6210 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
6211 }
6212 }
6213
6214 if (radv_image_has_cmask(iview->image) &&
6215 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
6216 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
6217
6218 if (radv_dcc_enabled(iview->image, iview->base_mip))
6219 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
6220
6221 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
6222
6223 /* This must be set for fast clear to work without FMASK. */
6224 if (!radv_image_has_fmask(iview->image) &&
6225 device->physical_device->rad_info.chip_class == GFX6) {
6226 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
6227 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
6228 }
6229
6230 if (device->physical_device->rad_info.chip_class >= GFX9) {
6231 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
6232
6233 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
6234 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
6235 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
6236 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
6237
6238 if (device->physical_device->rad_info.chip_class >= GFX10) {
6239 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
6240
6241 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
6242 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
6243 S_028EE0_RESOURCE_LEVEL(1);
6244 } else {
6245 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
6246 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
6247 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
6248 }
6249
6250 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
6251 S_028C68_MIP0_HEIGHT(height - 1) |
6252 S_028C68_MAX_MIP(iview->image->info.levels - 1);
6253 }
6254 }
6255
6256 static unsigned
6257 radv_calc_decompress_on_z_planes(struct radv_device *device,
6258 struct radv_image_view *iview)
6259 {
6260 unsigned max_zplanes = 0;
6261
6262 assert(radv_image_is_tc_compat_htile(iview->image));
6263
6264 if (device->physical_device->rad_info.chip_class >= GFX9) {
6265 /* Default value for 32-bit depth surfaces. */
6266 max_zplanes = 4;
6267
6268 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
6269 iview->image->info.samples > 1)
6270 max_zplanes = 2;
6271
6272 max_zplanes = max_zplanes + 1;
6273 } else {
6274 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
6275 /* Do not enable Z plane compression for 16-bit depth
6276 * surfaces because isn't supported on GFX8. Only
6277 * 32-bit depth surfaces are supported by the hardware.
6278 * This allows to maintain shader compatibility and to
6279 * reduce the number of depth decompressions.
6280 */
6281 max_zplanes = 1;
6282 } else {
6283 if (iview->image->info.samples <= 1)
6284 max_zplanes = 5;
6285 else if (iview->image->info.samples <= 4)
6286 max_zplanes = 3;
6287 else
6288 max_zplanes = 2;
6289 }
6290 }
6291
6292 return max_zplanes;
6293 }
6294
6295 void
6296 radv_initialise_ds_surface(struct radv_device *device,
6297 struct radv_ds_buffer_info *ds,
6298 struct radv_image_view *iview)
6299 {
6300 unsigned level = iview->base_mip;
6301 unsigned format, stencil_format;
6302 uint64_t va, s_offs, z_offs;
6303 bool stencil_only = false;
6304 const struct radv_image_plane *plane = &iview->image->planes[0];
6305 const struct radeon_surf *surf = &plane->surface;
6306
6307 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
6308
6309 memset(ds, 0, sizeof(*ds));
6310 switch (iview->image->vk_format) {
6311 case VK_FORMAT_D24_UNORM_S8_UINT:
6312 case VK_FORMAT_X8_D24_UNORM_PACK32:
6313 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6314 ds->offset_scale = 2.0f;
6315 break;
6316 case VK_FORMAT_D16_UNORM:
6317 case VK_FORMAT_D16_UNORM_S8_UINT:
6318 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6319 ds->offset_scale = 4.0f;
6320 break;
6321 case VK_FORMAT_D32_SFLOAT:
6322 case VK_FORMAT_D32_SFLOAT_S8_UINT:
6323 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6324 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6325 ds->offset_scale = 1.0f;
6326 break;
6327 case VK_FORMAT_S8_UINT:
6328 stencil_only = true;
6329 break;
6330 default:
6331 break;
6332 }
6333
6334 format = radv_translate_dbformat(iview->image->vk_format);
6335 stencil_format = surf->has_stencil ?
6336 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
6337
6338 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6339 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
6340 S_028008_SLICE_MAX(max_slice);
6341 if (device->physical_device->rad_info.chip_class >= GFX10) {
6342 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
6343 S_028008_SLICE_MAX_HI(max_slice >> 11);
6344 }
6345
6346 ds->db_htile_data_base = 0;
6347 ds->db_htile_surface = 0;
6348
6349 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6350 s_offs = z_offs = va;
6351
6352 if (device->physical_device->rad_info.chip_class >= GFX9) {
6353 assert(surf->u.gfx9.surf_offset == 0);
6354 s_offs += surf->u.gfx9.stencil_offset;
6355
6356 ds->db_z_info = S_028038_FORMAT(format) |
6357 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
6358 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6359 S_028038_MAXMIP(iview->image->info.levels - 1) |
6360 S_028038_ZRANGE_PRECISION(1);
6361 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
6362 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
6363
6364 if (device->physical_device->rad_info.chip_class == GFX9) {
6365 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
6366 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
6367 }
6368
6369 ds->db_depth_view |= S_028008_MIPID(level);
6370 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
6371 S_02801C_Y_MAX(iview->image->info.height - 1);
6372
6373 if (radv_htile_enabled(iview->image, level)) {
6374 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
6375
6376 if (radv_image_is_tc_compat_htile(iview->image)) {
6377 unsigned max_zplanes =
6378 radv_calc_decompress_on_z_planes(device, iview);
6379
6380 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6381
6382 if (device->physical_device->rad_info.chip_class >= GFX10) {
6383 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
6384 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
6385 } else {
6386 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
6387 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
6388 }
6389 }
6390
6391 if (!surf->has_stencil)
6392 /* Use all of the htile_buffer for depth if there's no stencil. */
6393 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
6394 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
6395 iview->image->htile_offset;
6396 ds->db_htile_data_base = va >> 8;
6397 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
6398 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
6399
6400 if (device->physical_device->rad_info.chip_class == GFX9) {
6401 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
6402 }
6403 }
6404 } else {
6405 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
6406
6407 if (stencil_only)
6408 level_info = &surf->u.legacy.stencil_level[level];
6409
6410 z_offs += surf->u.legacy.level[level].offset;
6411 s_offs += surf->u.legacy.stencil_level[level].offset;
6412
6413 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
6414 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
6415 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
6416
6417 if (iview->image->info.samples > 1)
6418 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
6419
6420 if (device->physical_device->rad_info.chip_class >= GFX7) {
6421 struct radeon_info *info = &device->physical_device->rad_info;
6422 unsigned tiling_index = surf->u.legacy.tiling_index[level];
6423 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
6424 unsigned macro_index = surf->u.legacy.macro_tile_index;
6425 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
6426 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
6427 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
6428
6429 if (stencil_only)
6430 tile_mode = stencil_tile_mode;
6431
6432 ds->db_depth_info |=
6433 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
6434 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
6435 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
6436 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
6437 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
6438 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
6439 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
6440 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
6441 } else {
6442 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
6443 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6444 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
6445 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
6446 if (stencil_only)
6447 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6448 }
6449
6450 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
6451 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
6452 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
6453
6454 if (radv_htile_enabled(iview->image, level)) {
6455 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
6456
6457 if (!surf->has_stencil &&
6458 !radv_image_is_tc_compat_htile(iview->image))
6459 /* Use all of the htile_buffer for depth if there's no stencil. */
6460 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
6461
6462 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
6463 iview->image->htile_offset;
6464 ds->db_htile_data_base = va >> 8;
6465 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
6466
6467 if (radv_image_is_tc_compat_htile(iview->image)) {
6468 unsigned max_zplanes =
6469 radv_calc_decompress_on_z_planes(device, iview);
6470
6471 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
6472 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6473 }
6474 }
6475 }
6476
6477 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
6478 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
6479 }
6480
6481 VkResult radv_CreateFramebuffer(
6482 VkDevice _device,
6483 const VkFramebufferCreateInfo* pCreateInfo,
6484 const VkAllocationCallbacks* pAllocator,
6485 VkFramebuffer* pFramebuffer)
6486 {
6487 RADV_FROM_HANDLE(radv_device, device, _device);
6488 struct radv_framebuffer *framebuffer;
6489 const VkFramebufferAttachmentsCreateInfoKHR *imageless_create_info =
6490 vk_find_struct_const(pCreateInfo->pNext,
6491 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO_KHR);
6492
6493 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
6494
6495 size_t size = sizeof(*framebuffer);
6496 if (!imageless_create_info)
6497 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
6498 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
6499 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6500 if (framebuffer == NULL)
6501 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6502
6503 framebuffer->attachment_count = pCreateInfo->attachmentCount;
6504 framebuffer->width = pCreateInfo->width;
6505 framebuffer->height = pCreateInfo->height;
6506 framebuffer->layers = pCreateInfo->layers;
6507 if (imageless_create_info) {
6508 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
6509 const VkFramebufferAttachmentImageInfoKHR *attachment =
6510 imageless_create_info->pAttachmentImageInfos + i;
6511 framebuffer->width = MIN2(framebuffer->width, attachment->width);
6512 framebuffer->height = MIN2(framebuffer->height, attachment->height);
6513 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
6514 }
6515 } else {
6516 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
6517 VkImageView _iview = pCreateInfo->pAttachments[i];
6518 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
6519 framebuffer->attachments[i] = iview;
6520 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
6521 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
6522 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
6523 }
6524 }
6525
6526 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
6527 return VK_SUCCESS;
6528 }
6529
6530 void radv_DestroyFramebuffer(
6531 VkDevice _device,
6532 VkFramebuffer _fb,
6533 const VkAllocationCallbacks* pAllocator)
6534 {
6535 RADV_FROM_HANDLE(radv_device, device, _device);
6536 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
6537
6538 if (!fb)
6539 return;
6540 vk_free2(&device->alloc, pAllocator, fb);
6541 }
6542
6543 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
6544 {
6545 switch (address_mode) {
6546 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
6547 return V_008F30_SQ_TEX_WRAP;
6548 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
6549 return V_008F30_SQ_TEX_MIRROR;
6550 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
6551 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
6552 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
6553 return V_008F30_SQ_TEX_CLAMP_BORDER;
6554 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
6555 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
6556 default:
6557 unreachable("illegal tex wrap mode");
6558 break;
6559 }
6560 }
6561
6562 static unsigned
6563 radv_tex_compare(VkCompareOp op)
6564 {
6565 switch (op) {
6566 case VK_COMPARE_OP_NEVER:
6567 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
6568 case VK_COMPARE_OP_LESS:
6569 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
6570 case VK_COMPARE_OP_EQUAL:
6571 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
6572 case VK_COMPARE_OP_LESS_OR_EQUAL:
6573 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
6574 case VK_COMPARE_OP_GREATER:
6575 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
6576 case VK_COMPARE_OP_NOT_EQUAL:
6577 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
6578 case VK_COMPARE_OP_GREATER_OR_EQUAL:
6579 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
6580 case VK_COMPARE_OP_ALWAYS:
6581 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
6582 default:
6583 unreachable("illegal compare mode");
6584 break;
6585 }
6586 }
6587
6588 static unsigned
6589 radv_tex_filter(VkFilter filter, unsigned max_ansio)
6590 {
6591 switch (filter) {
6592 case VK_FILTER_NEAREST:
6593 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
6594 V_008F38_SQ_TEX_XY_FILTER_POINT);
6595 case VK_FILTER_LINEAR:
6596 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
6597 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
6598 case VK_FILTER_CUBIC_IMG:
6599 default:
6600 fprintf(stderr, "illegal texture filter");
6601 return 0;
6602 }
6603 }
6604
6605 static unsigned
6606 radv_tex_mipfilter(VkSamplerMipmapMode mode)
6607 {
6608 switch (mode) {
6609 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
6610 return V_008F38_SQ_TEX_Z_FILTER_POINT;
6611 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
6612 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
6613 default:
6614 return V_008F38_SQ_TEX_Z_FILTER_NONE;
6615 }
6616 }
6617
6618 static unsigned
6619 radv_tex_bordercolor(VkBorderColor bcolor)
6620 {
6621 switch (bcolor) {
6622 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
6623 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
6624 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
6625 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
6626 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
6627 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
6628 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
6629 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
6630 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
6631 default:
6632 break;
6633 }
6634 return 0;
6635 }
6636
6637 static unsigned
6638 radv_tex_aniso_filter(unsigned filter)
6639 {
6640 if (filter < 2)
6641 return 0;
6642 if (filter < 4)
6643 return 1;
6644 if (filter < 8)
6645 return 2;
6646 if (filter < 16)
6647 return 3;
6648 return 4;
6649 }
6650
6651 static unsigned
6652 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
6653 {
6654 switch (mode) {
6655 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
6656 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
6657 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
6658 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
6659 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
6660 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
6661 default:
6662 break;
6663 }
6664 return 0;
6665 }
6666
6667 static uint32_t
6668 radv_get_max_anisotropy(struct radv_device *device,
6669 const VkSamplerCreateInfo *pCreateInfo)
6670 {
6671 if (device->force_aniso >= 0)
6672 return device->force_aniso;
6673
6674 if (pCreateInfo->anisotropyEnable &&
6675 pCreateInfo->maxAnisotropy > 1.0f)
6676 return (uint32_t)pCreateInfo->maxAnisotropy;
6677
6678 return 0;
6679 }
6680
6681 static void
6682 radv_init_sampler(struct radv_device *device,
6683 struct radv_sampler *sampler,
6684 const VkSamplerCreateInfo *pCreateInfo)
6685 {
6686 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
6687 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
6688 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
6689 device->physical_device->rad_info.chip_class == GFX9;
6690 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
6691
6692 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
6693 vk_find_struct_const(pCreateInfo->pNext,
6694 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
6695 if (sampler_reduction)
6696 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
6697
6698 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
6699 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
6700 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
6701 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
6702 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
6703 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
6704 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
6705 S_008F30_ANISO_BIAS(max_aniso_ratio) |
6706 S_008F30_DISABLE_CUBE_WRAP(0) |
6707 S_008F30_COMPAT_MODE(compat_mode) |
6708 S_008F30_FILTER_MODE(filter_mode));
6709 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
6710 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
6711 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
6712 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
6713 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
6714 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
6715 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
6716 S_008F38_MIP_POINT_PRECLAMP(0));
6717 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
6718 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
6719
6720 if (device->physical_device->rad_info.chip_class >= GFX10) {
6721 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
6722 } else {
6723 sampler->state[2] |=
6724 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
6725 S_008F38_FILTER_PREC_FIX(1) |
6726 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
6727 }
6728 }
6729
6730 VkResult radv_CreateSampler(
6731 VkDevice _device,
6732 const VkSamplerCreateInfo* pCreateInfo,
6733 const VkAllocationCallbacks* pAllocator,
6734 VkSampler* pSampler)
6735 {
6736 RADV_FROM_HANDLE(radv_device, device, _device);
6737 struct radv_sampler *sampler;
6738
6739 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
6740 vk_find_struct_const(pCreateInfo->pNext,
6741 SAMPLER_YCBCR_CONVERSION_INFO);
6742
6743 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
6744
6745 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
6746 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6747 if (!sampler)
6748 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6749
6750 radv_init_sampler(device, sampler, pCreateInfo);
6751
6752 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
6753 *pSampler = radv_sampler_to_handle(sampler);
6754
6755 return VK_SUCCESS;
6756 }
6757
6758 void radv_DestroySampler(
6759 VkDevice _device,
6760 VkSampler _sampler,
6761 const VkAllocationCallbacks* pAllocator)
6762 {
6763 RADV_FROM_HANDLE(radv_device, device, _device);
6764 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
6765
6766 if (!sampler)
6767 return;
6768 vk_free2(&device->alloc, pAllocator, sampler);
6769 }
6770
6771 /* vk_icd.h does not declare this function, so we declare it here to
6772 * suppress Wmissing-prototypes.
6773 */
6774 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
6775 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
6776
6777 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
6778 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
6779 {
6780 /* For the full details on loader interface versioning, see
6781 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
6782 * What follows is a condensed summary, to help you navigate the large and
6783 * confusing official doc.
6784 *
6785 * - Loader interface v0 is incompatible with later versions. We don't
6786 * support it.
6787 *
6788 * - In loader interface v1:
6789 * - The first ICD entrypoint called by the loader is
6790 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
6791 * entrypoint.
6792 * - The ICD must statically expose no other Vulkan symbol unless it is
6793 * linked with -Bsymbolic.
6794 * - Each dispatchable Vulkan handle created by the ICD must be
6795 * a pointer to a struct whose first member is VK_LOADER_DATA. The
6796 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
6797 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
6798 * vkDestroySurfaceKHR(). The ICD must be capable of working with
6799 * such loader-managed surfaces.
6800 *
6801 * - Loader interface v2 differs from v1 in:
6802 * - The first ICD entrypoint called by the loader is
6803 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
6804 * statically expose this entrypoint.
6805 *
6806 * - Loader interface v3 differs from v2 in:
6807 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
6808 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
6809 * because the loader no longer does so.
6810 */
6811 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
6812 return VK_SUCCESS;
6813 }
6814
6815 VkResult radv_GetMemoryFdKHR(VkDevice _device,
6816 const VkMemoryGetFdInfoKHR *pGetFdInfo,
6817 int *pFD)
6818 {
6819 RADV_FROM_HANDLE(radv_device, device, _device);
6820 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
6821
6822 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
6823
6824 /* At the moment, we support only the below handle types. */
6825 assert(pGetFdInfo->handleType ==
6826 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
6827 pGetFdInfo->handleType ==
6828 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
6829
6830 bool ret = radv_get_memory_fd(device, memory, pFD);
6831 if (ret == false)
6832 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6833 return VK_SUCCESS;
6834 }
6835
6836 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
6837 VkExternalMemoryHandleTypeFlagBits handleType,
6838 int fd,
6839 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
6840 {
6841 RADV_FROM_HANDLE(radv_device, device, _device);
6842
6843 switch (handleType) {
6844 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
6845 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
6846 return VK_SUCCESS;
6847
6848 default:
6849 /* The valid usage section for this function says:
6850 *
6851 * "handleType must not be one of the handle types defined as
6852 * opaque."
6853 *
6854 * So opaque handle types fall into the default "unsupported" case.
6855 */
6856 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
6857 }
6858 }
6859
6860 static VkResult radv_import_opaque_fd(struct radv_device *device,
6861 int fd,
6862 uint32_t *syncobj)
6863 {
6864 uint32_t syncobj_handle = 0;
6865 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
6866 if (ret != 0)
6867 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
6868
6869 if (*syncobj)
6870 device->ws->destroy_syncobj(device->ws, *syncobj);
6871
6872 *syncobj = syncobj_handle;
6873 close(fd);
6874
6875 return VK_SUCCESS;
6876 }
6877
6878 static VkResult radv_import_sync_fd(struct radv_device *device,
6879 int fd,
6880 uint32_t *syncobj)
6881 {
6882 /* If we create a syncobj we do it locally so that if we have an error, we don't
6883 * leave a syncobj in an undetermined state in the fence. */
6884 uint32_t syncobj_handle = *syncobj;
6885 if (!syncobj_handle) {
6886 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
6887 if (ret) {
6888 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
6889 }
6890 }
6891
6892 if (fd == -1) {
6893 device->ws->signal_syncobj(device->ws, syncobj_handle);
6894 } else {
6895 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
6896 if (ret != 0)
6897 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
6898 }
6899
6900 *syncobj = syncobj_handle;
6901 if (fd != -1)
6902 close(fd);
6903
6904 return VK_SUCCESS;
6905 }
6906
6907 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
6908 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
6909 {
6910 RADV_FROM_HANDLE(radv_device, device, _device);
6911 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
6912 VkResult result;
6913 struct radv_semaphore_part *dst = NULL;
6914
6915 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
6916 dst = &sem->temporary;
6917 } else {
6918 dst = &sem->permanent;
6919 }
6920
6921 uint32_t syncobj = dst->kind == RADV_SEMAPHORE_SYNCOBJ ? dst->syncobj : 0;
6922
6923 switch(pImportSemaphoreFdInfo->handleType) {
6924 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
6925 result = radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
6926 break;
6927 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
6928 result = radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
6929 break;
6930 default:
6931 unreachable("Unhandled semaphore handle type");
6932 }
6933
6934 if (result == VK_SUCCESS) {
6935 dst->syncobj = syncobj;
6936 dst->kind = RADV_SEMAPHORE_SYNCOBJ;
6937 }
6938
6939 return result;
6940 }
6941
6942 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
6943 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
6944 int *pFd)
6945 {
6946 RADV_FROM_HANDLE(radv_device, device, _device);
6947 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
6948 int ret;
6949 uint32_t syncobj_handle;
6950
6951 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
6952 assert(sem->temporary.kind == RADV_SEMAPHORE_SYNCOBJ);
6953 syncobj_handle = sem->temporary.syncobj;
6954 } else {
6955 assert(sem->permanent.kind == RADV_SEMAPHORE_SYNCOBJ);
6956 syncobj_handle = sem->permanent.syncobj;
6957 }
6958
6959 switch(pGetFdInfo->handleType) {
6960 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
6961 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
6962 break;
6963 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
6964 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
6965 if (!ret) {
6966 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
6967 radv_destroy_semaphore_part(device, &sem->temporary);
6968 } else {
6969 device->ws->reset_syncobj(device->ws, syncobj_handle);
6970 }
6971 }
6972 break;
6973 default:
6974 unreachable("Unhandled semaphore handle type");
6975 }
6976
6977 if (ret)
6978 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
6979 return VK_SUCCESS;
6980 }
6981
6982 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
6983 VkPhysicalDevice physicalDevice,
6984 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
6985 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
6986 {
6987 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
6988 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pExternalSemaphoreInfo->pNext, NULL);
6989
6990 if (type == VK_SEMAPHORE_TYPE_TIMELINE_KHR) {
6991 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
6992 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
6993 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
6994
6995 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
6996 } else if (pdevice->rad_info.has_syncobj_wait_for_submit &&
6997 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
6998 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
6999 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7000 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7001 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7002 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7003 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
7004 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7005 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7006 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7007 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7008 } else {
7009 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7010 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7011 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7012 }
7013 }
7014
7015 VkResult radv_ImportFenceFdKHR(VkDevice _device,
7016 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
7017 {
7018 RADV_FROM_HANDLE(radv_device, device, _device);
7019 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
7020 uint32_t *syncobj_dst = NULL;
7021
7022
7023 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
7024 syncobj_dst = &fence->temp_syncobj;
7025 } else {
7026 syncobj_dst = &fence->syncobj;
7027 }
7028
7029 switch(pImportFenceFdInfo->handleType) {
7030 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7031 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
7032 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7033 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
7034 default:
7035 unreachable("Unhandled fence handle type");
7036 }
7037 }
7038
7039 VkResult radv_GetFenceFdKHR(VkDevice _device,
7040 const VkFenceGetFdInfoKHR *pGetFdInfo,
7041 int *pFd)
7042 {
7043 RADV_FROM_HANDLE(radv_device, device, _device);
7044 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
7045 int ret;
7046 uint32_t syncobj_handle;
7047
7048 if (fence->temp_syncobj)
7049 syncobj_handle = fence->temp_syncobj;
7050 else
7051 syncobj_handle = fence->syncobj;
7052
7053 switch(pGetFdInfo->handleType) {
7054 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7055 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
7056 break;
7057 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7058 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
7059 if (!ret) {
7060 if (fence->temp_syncobj) {
7061 close (fence->temp_syncobj);
7062 fence->temp_syncobj = 0;
7063 } else {
7064 device->ws->reset_syncobj(device->ws, syncobj_handle);
7065 }
7066 }
7067 break;
7068 default:
7069 unreachable("Unhandled fence handle type");
7070 }
7071
7072 if (ret)
7073 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7074 return VK_SUCCESS;
7075 }
7076
7077 void radv_GetPhysicalDeviceExternalFenceProperties(
7078 VkPhysicalDevice physicalDevice,
7079 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
7080 VkExternalFenceProperties *pExternalFenceProperties)
7081 {
7082 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7083
7084 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7085 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7086 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
7087 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7088 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7089 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
7090 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7091 } else {
7092 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
7093 pExternalFenceProperties->compatibleHandleTypes = 0;
7094 pExternalFenceProperties->externalFenceFeatures = 0;
7095 }
7096 }
7097
7098 VkResult
7099 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
7100 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
7101 const VkAllocationCallbacks* pAllocator,
7102 VkDebugReportCallbackEXT* pCallback)
7103 {
7104 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7105 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
7106 pCreateInfo, pAllocator, &instance->alloc,
7107 pCallback);
7108 }
7109
7110 void
7111 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
7112 VkDebugReportCallbackEXT _callback,
7113 const VkAllocationCallbacks* pAllocator)
7114 {
7115 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7116 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
7117 _callback, pAllocator, &instance->alloc);
7118 }
7119
7120 void
7121 radv_DebugReportMessageEXT(VkInstance _instance,
7122 VkDebugReportFlagsEXT flags,
7123 VkDebugReportObjectTypeEXT objectType,
7124 uint64_t object,
7125 size_t location,
7126 int32_t messageCode,
7127 const char* pLayerPrefix,
7128 const char* pMessage)
7129 {
7130 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7131 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
7132 object, location, messageCode, pLayerPrefix, pMessage);
7133 }
7134
7135 void
7136 radv_GetDeviceGroupPeerMemoryFeatures(
7137 VkDevice device,
7138 uint32_t heapIndex,
7139 uint32_t localDeviceIndex,
7140 uint32_t remoteDeviceIndex,
7141 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
7142 {
7143 assert(localDeviceIndex == remoteDeviceIndex);
7144
7145 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
7146 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
7147 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
7148 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
7149 }
7150
7151 static const VkTimeDomainEXT radv_time_domains[] = {
7152 VK_TIME_DOMAIN_DEVICE_EXT,
7153 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
7154 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
7155 };
7156
7157 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7158 VkPhysicalDevice physicalDevice,
7159 uint32_t *pTimeDomainCount,
7160 VkTimeDomainEXT *pTimeDomains)
7161 {
7162 int d;
7163 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
7164
7165 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
7166 vk_outarray_append(&out, i) {
7167 *i = radv_time_domains[d];
7168 }
7169 }
7170
7171 return vk_outarray_status(&out);
7172 }
7173
7174 static uint64_t
7175 radv_clock_gettime(clockid_t clock_id)
7176 {
7177 struct timespec current;
7178 int ret;
7179
7180 ret = clock_gettime(clock_id, &current);
7181 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
7182 ret = clock_gettime(CLOCK_MONOTONIC, &current);
7183 if (ret < 0)
7184 return 0;
7185
7186 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
7187 }
7188
7189 VkResult radv_GetCalibratedTimestampsEXT(
7190 VkDevice _device,
7191 uint32_t timestampCount,
7192 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
7193 uint64_t *pTimestamps,
7194 uint64_t *pMaxDeviation)
7195 {
7196 RADV_FROM_HANDLE(radv_device, device, _device);
7197 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
7198 int d;
7199 uint64_t begin, end;
7200 uint64_t max_clock_period = 0;
7201
7202 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7203
7204 for (d = 0; d < timestampCount; d++) {
7205 switch (pTimestampInfos[d].timeDomain) {
7206 case VK_TIME_DOMAIN_DEVICE_EXT:
7207 pTimestamps[d] = device->ws->query_value(device->ws,
7208 RADEON_TIMESTAMP);
7209 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
7210 max_clock_period = MAX2(max_clock_period, device_period);
7211 break;
7212 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
7213 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
7214 max_clock_period = MAX2(max_clock_period, 1);
7215 break;
7216
7217 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
7218 pTimestamps[d] = begin;
7219 break;
7220 default:
7221 pTimestamps[d] = 0;
7222 break;
7223 }
7224 }
7225
7226 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7227
7228 /*
7229 * The maximum deviation is the sum of the interval over which we
7230 * perform the sampling and the maximum period of any sampled
7231 * clock. That's because the maximum skew between any two sampled
7232 * clock edges is when the sampled clock with the largest period is
7233 * sampled at the end of that period but right at the beginning of the
7234 * sampling interval and some other clock is sampled right at the
7235 * begining of its sampling period and right at the end of the
7236 * sampling interval. Let's assume the GPU has the longest clock
7237 * period and that the application is sampling GPU and monotonic:
7238 *
7239 * s e
7240 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
7241 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7242 *
7243 * g
7244 * 0 1 2 3
7245 * GPU -----_____-----_____-----_____-----_____
7246 *
7247 * m
7248 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
7249 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7250 *
7251 * Interval <----------------->
7252 * Deviation <-------------------------->
7253 *
7254 * s = read(raw) 2
7255 * g = read(GPU) 1
7256 * m = read(monotonic) 2
7257 * e = read(raw) b
7258 *
7259 * We round the sample interval up by one tick to cover sampling error
7260 * in the interval clock
7261 */
7262
7263 uint64_t sample_interval = end - begin + 1;
7264
7265 *pMaxDeviation = sample_interval + max_clock_period;
7266
7267 return VK_SUCCESS;
7268 }
7269
7270 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
7271 VkPhysicalDevice physicalDevice,
7272 VkSampleCountFlagBits samples,
7273 VkMultisamplePropertiesEXT* pMultisampleProperties)
7274 {
7275 if (samples & (VK_SAMPLE_COUNT_2_BIT |
7276 VK_SAMPLE_COUNT_4_BIT |
7277 VK_SAMPLE_COUNT_8_BIT)) {
7278 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
7279 } else {
7280 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
7281 }
7282 }