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radv: Use enum for memory heaps.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <dlfcn.h>
29 #include <stdbool.h>
30 #include <string.h>
31 #include <unistd.h>
32 #include <fcntl.h>
33 #include <sys/stat.h>
34 #include "radv_private.h"
35 #include "util/strtod.h"
36
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "util/debug.h"
46 struct radv_dispatch_table dtable;
47
48 static int
49 radv_get_function_timestamp(void *ptr, uint32_t* timestamp)
50 {
51 Dl_info info;
52 struct stat st;
53 if (!dladdr(ptr, &info) || !info.dli_fname) {
54 return -1;
55 }
56 if (stat(info.dli_fname, &st)) {
57 return -1;
58 }
59 *timestamp = st.st_mtim.tv_sec;
60 return 0;
61 }
62
63 static int
64 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
65 {
66 uint32_t mesa_timestamp, llvm_timestamp;
67 uint16_t f = family;
68 memset(uuid, 0, VK_UUID_SIZE);
69 if (radv_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
70 radv_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
71 return -1;
72
73 memcpy(uuid, &mesa_timestamp, 4);
74 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
75 memcpy((char*)uuid + 8, &f, 2);
76 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
77 return 0;
78 }
79
80 static VkResult
81 radv_physical_device_init(struct radv_physical_device *device,
82 struct radv_instance *instance,
83 const char *path)
84 {
85 VkResult result;
86 drmVersionPtr version;
87 int fd;
88
89 fd = open(path, O_RDWR | O_CLOEXEC);
90 if (fd < 0)
91 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
92 "failed to open %s: %m", path);
93
94 version = drmGetVersion(fd);
95 if (!version) {
96 close(fd);
97 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
98 "failed to get version %s: %m", path);
99 }
100
101 if (strcmp(version->name, "amdgpu")) {
102 drmFreeVersion(version);
103 close(fd);
104 return VK_ERROR_INCOMPATIBLE_DRIVER;
105 }
106 drmFreeVersion(version);
107
108 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
109 device->instance = instance;
110 assert(strlen(path) < ARRAY_SIZE(device->path));
111 strncpy(device->path, path, ARRAY_SIZE(device->path));
112
113 device->ws = radv_amdgpu_winsys_create(fd);
114 if (!device->ws) {
115 result = VK_ERROR_INCOMPATIBLE_DRIVER;
116 goto fail;
117 }
118 device->ws->query_info(device->ws, &device->rad_info);
119 result = radv_init_wsi(device);
120 if (result != VK_SUCCESS) {
121 device->ws->destroy(device->ws);
122 goto fail;
123 }
124
125 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
126 radv_finish_wsi(device);
127 device->ws->destroy(device->ws);
128 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
129 "cannot generate UUID");
130 goto fail;
131 }
132
133 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
134 device->name = device->rad_info.name;
135 close(fd);
136 return VK_SUCCESS;
137
138 fail:
139 close(fd);
140 return result;
141 }
142
143 static void
144 radv_physical_device_finish(struct radv_physical_device *device)
145 {
146 radv_finish_wsi(device);
147 device->ws->destroy(device->ws);
148 }
149
150 static const VkExtensionProperties global_extensions[] = {
151 {
152 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
153 .specVersion = 25,
154 },
155 #ifdef VK_USE_PLATFORM_XCB_KHR
156 {
157 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
158 .specVersion = 6,
159 },
160 #endif
161 #ifdef VK_USE_PLATFORM_XLIB_KHR
162 {
163 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
164 .specVersion = 6,
165 },
166 #endif
167 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
168 {
169 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
170 .specVersion = 5,
171 },
172 #endif
173 };
174
175 static const VkExtensionProperties device_extensions[] = {
176 {
177 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
178 .specVersion = 1,
179 },
180 {
181 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
182 .specVersion = 68,
183 },
184 {
185 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
186 .specVersion = 1,
187 },
188 {
189 .extensionName = VK_AMD_NEGATIVE_VIEWPORT_HEIGHT_EXTENSION_NAME,
190 .specVersion = 1,
191 },
192 };
193
194 static void *
195 default_alloc_func(void *pUserData, size_t size, size_t align,
196 VkSystemAllocationScope allocationScope)
197 {
198 return malloc(size);
199 }
200
201 static void *
202 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
203 size_t align, VkSystemAllocationScope allocationScope)
204 {
205 return realloc(pOriginal, size);
206 }
207
208 static void
209 default_free_func(void *pUserData, void *pMemory)
210 {
211 free(pMemory);
212 }
213
214 static const VkAllocationCallbacks default_alloc = {
215 .pUserData = NULL,
216 .pfnAllocation = default_alloc_func,
217 .pfnReallocation = default_realloc_func,
218 .pfnFree = default_free_func,
219 };
220
221 VkResult radv_CreateInstance(
222 const VkInstanceCreateInfo* pCreateInfo,
223 const VkAllocationCallbacks* pAllocator,
224 VkInstance* pInstance)
225 {
226 struct radv_instance *instance;
227
228 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
229
230 uint32_t client_version;
231 if (pCreateInfo->pApplicationInfo &&
232 pCreateInfo->pApplicationInfo->apiVersion != 0) {
233 client_version = pCreateInfo->pApplicationInfo->apiVersion;
234 } else {
235 client_version = VK_MAKE_VERSION(1, 0, 0);
236 }
237
238 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
239 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
240 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
241 "Client requested version %d.%d.%d",
242 VK_VERSION_MAJOR(client_version),
243 VK_VERSION_MINOR(client_version),
244 VK_VERSION_PATCH(client_version));
245 }
246
247 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
248 bool found = false;
249 for (uint32_t j = 0; j < ARRAY_SIZE(global_extensions); j++) {
250 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
251 global_extensions[j].extensionName) == 0) {
252 found = true;
253 break;
254 }
255 }
256 if (!found)
257 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
258 }
259
260 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
262 if (!instance)
263 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
264
265 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266
267 if (pAllocator)
268 instance->alloc = *pAllocator;
269 else
270 instance->alloc = default_alloc;
271
272 instance->apiVersion = client_version;
273 instance->physicalDeviceCount = -1;
274
275 _mesa_locale_init();
276
277 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
278
279 *pInstance = radv_instance_to_handle(instance);
280
281 return VK_SUCCESS;
282 }
283
284 void radv_DestroyInstance(
285 VkInstance _instance,
286 const VkAllocationCallbacks* pAllocator)
287 {
288 RADV_FROM_HANDLE(radv_instance, instance, _instance);
289
290 if (instance->physicalDeviceCount > 0) {
291 /* We support at most one physical device. */
292 assert(instance->physicalDeviceCount == 1);
293 radv_physical_device_finish(&instance->physicalDevice);
294 }
295
296 VG(VALGRIND_DESTROY_MEMPOOL(instance));
297
298 _mesa_locale_fini();
299
300 vk_free(&instance->alloc, instance);
301 }
302
303 VkResult radv_EnumeratePhysicalDevices(
304 VkInstance _instance,
305 uint32_t* pPhysicalDeviceCount,
306 VkPhysicalDevice* pPhysicalDevices)
307 {
308 RADV_FROM_HANDLE(radv_instance, instance, _instance);
309 VkResult result;
310
311 if (instance->physicalDeviceCount < 0) {
312 char path[20];
313 for (unsigned i = 0; i < 8; i++) {
314 snprintf(path, sizeof(path), "/dev/dri/renderD%d", 128 + i);
315 result = radv_physical_device_init(&instance->physicalDevice,
316 instance, path);
317 if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
318 break;
319 }
320
321 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
322 instance->physicalDeviceCount = 0;
323 } else if (result == VK_SUCCESS) {
324 instance->physicalDeviceCount = 1;
325 } else {
326 return result;
327 }
328 }
329
330 /* pPhysicalDeviceCount is an out parameter if pPhysicalDevices is NULL;
331 * otherwise it's an inout parameter.
332 *
333 * The Vulkan spec (git aaed022) says:
334 *
335 * pPhysicalDeviceCount is a pointer to an unsigned integer variable
336 * that is initialized with the number of devices the application is
337 * prepared to receive handles to. pname:pPhysicalDevices is pointer to
338 * an array of at least this many VkPhysicalDevice handles [...].
339 *
340 * Upon success, if pPhysicalDevices is NULL, vkEnumeratePhysicalDevices
341 * overwrites the contents of the variable pointed to by
342 * pPhysicalDeviceCount with the number of physical devices in in the
343 * instance; otherwise, vkEnumeratePhysicalDevices overwrites
344 * pPhysicalDeviceCount with the number of physical handles written to
345 * pPhysicalDevices.
346 */
347 if (!pPhysicalDevices) {
348 *pPhysicalDeviceCount = instance->physicalDeviceCount;
349 } else if (*pPhysicalDeviceCount >= 1) {
350 pPhysicalDevices[0] = radv_physical_device_to_handle(&instance->physicalDevice);
351 *pPhysicalDeviceCount = 1;
352 } else if (*pPhysicalDeviceCount < instance->physicalDeviceCount) {
353 return VK_INCOMPLETE;
354 } else {
355 *pPhysicalDeviceCount = 0;
356 }
357
358 return VK_SUCCESS;
359 }
360
361 void radv_GetPhysicalDeviceFeatures(
362 VkPhysicalDevice physicalDevice,
363 VkPhysicalDeviceFeatures* pFeatures)
364 {
365 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
366
367 memset(pFeatures, 0, sizeof(*pFeatures));
368
369 *pFeatures = (VkPhysicalDeviceFeatures) {
370 .robustBufferAccess = true,
371 .fullDrawIndexUint32 = true,
372 .imageCubeArray = true,
373 .independentBlend = true,
374 .geometryShader = false,
375 .tessellationShader = false,
376 .sampleRateShading = false,
377 .dualSrcBlend = true,
378 .logicOp = true,
379 .multiDrawIndirect = true,
380 .drawIndirectFirstInstance = true,
381 .depthClamp = true,
382 .depthBiasClamp = true,
383 .fillModeNonSolid = true,
384 .depthBounds = true,
385 .wideLines = true,
386 .largePoints = true,
387 .alphaToOne = true,
388 .multiViewport = false,
389 .samplerAnisotropy = true,
390 .textureCompressionETC2 = false,
391 .textureCompressionASTC_LDR = false,
392 .textureCompressionBC = true,
393 .occlusionQueryPrecise = true,
394 .pipelineStatisticsQuery = false,
395 .vertexPipelineStoresAndAtomics = true,
396 .fragmentStoresAndAtomics = true,
397 .shaderTessellationAndGeometryPointSize = true,
398 .shaderImageGatherExtended = false,
399 .shaderStorageImageExtendedFormats = false,
400 .shaderStorageImageMultisample = false,
401 .shaderUniformBufferArrayDynamicIndexing = true,
402 .shaderSampledImageArrayDynamicIndexing = true,
403 .shaderStorageBufferArrayDynamicIndexing = true,
404 .shaderStorageImageArrayDynamicIndexing = true,
405 .shaderStorageImageReadWithoutFormat = false,
406 .shaderStorageImageWriteWithoutFormat = true,
407 .shaderClipDistance = true,
408 .shaderCullDistance = true,
409 .shaderFloat64 = false,
410 .shaderInt64 = false,
411 .shaderInt16 = false,
412 .alphaToOne = true,
413 .variableMultisampleRate = false,
414 .inheritedQueries = false,
415 };
416 }
417
418 void radv_GetPhysicalDeviceProperties(
419 VkPhysicalDevice physicalDevice,
420 VkPhysicalDeviceProperties* pProperties)
421 {
422 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
423 VkSampleCountFlags sample_counts = 0xf;
424 VkPhysicalDeviceLimits limits = {
425 .maxImageDimension1D = (1 << 14),
426 .maxImageDimension2D = (1 << 14),
427 .maxImageDimension3D = (1 << 11),
428 .maxImageDimensionCube = (1 << 14),
429 .maxImageArrayLayers = (1 << 11),
430 .maxTexelBufferElements = 128 * 1024 * 1024,
431 .maxUniformBufferRange = UINT32_MAX,
432 .maxStorageBufferRange = UINT32_MAX,
433 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
434 .maxMemoryAllocationCount = UINT32_MAX,
435 .maxSamplerAllocationCount = 64 * 1024,
436 .bufferImageGranularity = 64, /* A cache line */
437 .sparseAddressSpaceSize = 0,
438 .maxBoundDescriptorSets = MAX_SETS,
439 .maxPerStageDescriptorSamplers = 64,
440 .maxPerStageDescriptorUniformBuffers = 64,
441 .maxPerStageDescriptorStorageBuffers = 64,
442 .maxPerStageDescriptorSampledImages = 64,
443 .maxPerStageDescriptorStorageImages = 64,
444 .maxPerStageDescriptorInputAttachments = 64,
445 .maxPerStageResources = 128,
446 .maxDescriptorSetSamplers = 256,
447 .maxDescriptorSetUniformBuffers = 256,
448 .maxDescriptorSetUniformBuffersDynamic = 256,
449 .maxDescriptorSetStorageBuffers = 256,
450 .maxDescriptorSetStorageBuffersDynamic = 256,
451 .maxDescriptorSetSampledImages = 256,
452 .maxDescriptorSetStorageImages = 256,
453 .maxDescriptorSetInputAttachments = 256,
454 .maxVertexInputAttributes = 32,
455 .maxVertexInputBindings = 32,
456 .maxVertexInputAttributeOffset = 2047,
457 .maxVertexInputBindingStride = 2048,
458 .maxVertexOutputComponents = 128,
459 .maxTessellationGenerationLevel = 0,
460 .maxTessellationPatchSize = 0,
461 .maxTessellationControlPerVertexInputComponents = 0,
462 .maxTessellationControlPerVertexOutputComponents = 0,
463 .maxTessellationControlPerPatchOutputComponents = 0,
464 .maxTessellationControlTotalOutputComponents = 0,
465 .maxTessellationEvaluationInputComponents = 0,
466 .maxTessellationEvaluationOutputComponents = 0,
467 .maxGeometryShaderInvocations = 32,
468 .maxGeometryInputComponents = 64,
469 .maxGeometryOutputComponents = 128,
470 .maxGeometryOutputVertices = 256,
471 .maxGeometryTotalOutputComponents = 1024,
472 .maxFragmentInputComponents = 128,
473 .maxFragmentOutputAttachments = 8,
474 .maxFragmentDualSrcAttachments = 1,
475 .maxFragmentCombinedOutputResources = 8,
476 .maxComputeSharedMemorySize = 32768,
477 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
478 .maxComputeWorkGroupInvocations = 16 * 1024,
479 .maxComputeWorkGroupSize = {
480 16 * 1024/*devinfo->max_cs_threads*/,
481 16 * 1024,
482 16 * 1024
483 },
484 .subPixelPrecisionBits = 4 /* FIXME */,
485 .subTexelPrecisionBits = 4 /* FIXME */,
486 .mipmapPrecisionBits = 4 /* FIXME */,
487 .maxDrawIndexedIndexValue = UINT32_MAX,
488 .maxDrawIndirectCount = UINT32_MAX,
489 .maxSamplerLodBias = 16,
490 .maxSamplerAnisotropy = 16,
491 .maxViewports = MAX_VIEWPORTS,
492 .maxViewportDimensions = { (1 << 14), (1 << 14) },
493 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
494 .viewportSubPixelBits = 13, /* We take a float? */
495 .minMemoryMapAlignment = 4096, /* A page */
496 .minTexelBufferOffsetAlignment = 1,
497 .minUniformBufferOffsetAlignment = 4,
498 .minStorageBufferOffsetAlignment = 4,
499 .minTexelOffset = -8,
500 .maxTexelOffset = 7,
501 .minTexelGatherOffset = -8,
502 .maxTexelGatherOffset = 7,
503 .minInterpolationOffset = 0, /* FIXME */
504 .maxInterpolationOffset = 0, /* FIXME */
505 .subPixelInterpolationOffsetBits = 0, /* FIXME */
506 .maxFramebufferWidth = (1 << 14),
507 .maxFramebufferHeight = (1 << 14),
508 .maxFramebufferLayers = (1 << 10),
509 .framebufferColorSampleCounts = sample_counts,
510 .framebufferDepthSampleCounts = sample_counts,
511 .framebufferStencilSampleCounts = sample_counts,
512 .framebufferNoAttachmentsSampleCounts = sample_counts,
513 .maxColorAttachments = MAX_RTS,
514 .sampledImageColorSampleCounts = sample_counts,
515 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
516 .sampledImageDepthSampleCounts = sample_counts,
517 .sampledImageStencilSampleCounts = sample_counts,
518 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
519 .maxSampleMaskWords = 1,
520 .timestampComputeAndGraphics = false,
521 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
522 .maxClipDistances = 8,
523 .maxCullDistances = 8,
524 .maxCombinedClipAndCullDistances = 8,
525 .discreteQueuePriorities = 1,
526 .pointSizeRange = { 0.125, 255.875 },
527 .lineWidthRange = { 0.0, 7.9921875 },
528 .pointSizeGranularity = (1.0 / 8.0),
529 .lineWidthGranularity = (1.0 / 128.0),
530 .strictLines = false, /* FINISHME */
531 .standardSampleLocations = true,
532 .optimalBufferCopyOffsetAlignment = 128,
533 .optimalBufferCopyRowPitchAlignment = 128,
534 .nonCoherentAtomSize = 64,
535 };
536
537 *pProperties = (VkPhysicalDeviceProperties) {
538 .apiVersion = VK_MAKE_VERSION(1, 0, 5),
539 .driverVersion = 1,
540 .vendorID = 0x1002,
541 .deviceID = pdevice->rad_info.pci_id,
542 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
543 .limits = limits,
544 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
545 };
546
547 strcpy(pProperties->deviceName, pdevice->name);
548 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
549 }
550
551 void radv_GetPhysicalDeviceQueueFamilyProperties(
552 VkPhysicalDevice physicalDevice,
553 uint32_t* pCount,
554 VkQueueFamilyProperties* pQueueFamilyProperties)
555 {
556 if (pQueueFamilyProperties == NULL) {
557 *pCount = 1;
558 return;
559 }
560 assert(*pCount >= 1);
561
562 *pQueueFamilyProperties = (VkQueueFamilyProperties) {
563 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
564 VK_QUEUE_COMPUTE_BIT |
565 VK_QUEUE_TRANSFER_BIT,
566 .queueCount = 1,
567 .timestampValidBits = 64,
568 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
569 };
570 }
571
572 void radv_GetPhysicalDeviceMemoryProperties(
573 VkPhysicalDevice physicalDevice,
574 VkPhysicalDeviceMemoryProperties* pMemoryProperties)
575 {
576 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
577
578 pMemoryProperties->memoryTypeCount = 4;
579 pMemoryProperties->memoryTypes[0] = (VkMemoryType) {
580 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
581 .heapIndex = RADV_MEM_HEAP_VRAM,
582 };
583 pMemoryProperties->memoryTypes[1] = (VkMemoryType) {
584 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
585 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
586 .heapIndex = RADV_MEM_HEAP_GTT,
587 };
588 pMemoryProperties->memoryTypes[2] = (VkMemoryType) {
589 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
590 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
591 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
592 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
593 };
594 pMemoryProperties->memoryTypes[3] = (VkMemoryType) {
595 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
596 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
597 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
598 .heapIndex = RADV_MEM_HEAP_GTT,
599 };
600
601 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
602
603 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
604 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
605 .size = physical_device->rad_info.vram_size -
606 physical_device->rad_info.visible_vram_size,
607 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
608 };
609 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
610 .size = physical_device->rad_info.visible_vram_size,
611 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
612 };
613 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
614 .size = physical_device->rad_info.gart_size,
615 .flags = 0,
616 };
617 }
618
619 static void
620 radv_queue_init(struct radv_device *device, struct radv_queue *queue)
621 {
622 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
623 queue->device = device;
624 }
625
626 static void
627 radv_queue_finish(struct radv_queue *queue)
628 {
629 }
630
631 VkResult radv_CreateDevice(
632 VkPhysicalDevice physicalDevice,
633 const VkDeviceCreateInfo* pCreateInfo,
634 const VkAllocationCallbacks* pAllocator,
635 VkDevice* pDevice)
636 {
637 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
638 VkResult result;
639 struct radv_device *device;
640
641 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
642 bool found = false;
643 for (uint32_t j = 0; j < ARRAY_SIZE(device_extensions); j++) {
644 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
645 device_extensions[j].extensionName) == 0) {
646 found = true;
647 break;
648 }
649 }
650 if (!found)
651 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
652 }
653
654 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
655 sizeof(*device), 8,
656 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
657 if (!device)
658 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
659
660 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
661 device->instance = physical_device->instance;
662 device->shader_stats_dump = false;
663
664 device->ws = physical_device->ws;
665 if (pAllocator)
666 device->alloc = *pAllocator;
667 else
668 device->alloc = physical_device->instance->alloc;
669
670 device->hw_ctx = device->ws->ctx_create(device->ws);
671 if (!device->hw_ctx) {
672 result = VK_ERROR_OUT_OF_HOST_MEMORY;
673 goto fail_free;
674 }
675
676 radv_queue_init(device, &device->queue);
677
678 result = radv_device_init_meta(device);
679 if (result != VK_SUCCESS) {
680 device->ws->ctx_destroy(device->hw_ctx);
681 goto fail_free;
682 }
683 device->allow_fast_clears = env_var_as_boolean("RADV_FAST_CLEARS", false);
684 device->allow_dcc = !env_var_as_boolean("RADV_DCC_DISABLE", false);
685 device->shader_stats_dump = env_var_as_boolean("RADV_SHADER_STATS", false);
686
687 if (device->allow_fast_clears && device->allow_dcc)
688 radv_finishme("DCC fast clears have not been tested\n");
689
690 radv_device_init_msaa(device);
691 device->empty_cs = device->ws->cs_create(device->ws, RING_GFX);
692 radeon_emit(device->empty_cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
693 radeon_emit(device->empty_cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
694 radeon_emit(device->empty_cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
695 device->ws->cs_finalize(device->empty_cs);
696 *pDevice = radv_device_to_handle(device);
697 return VK_SUCCESS;
698 fail_free:
699 vk_free(&device->alloc, device);
700 return result;
701 }
702
703 void radv_DestroyDevice(
704 VkDevice _device,
705 const VkAllocationCallbacks* pAllocator)
706 {
707 RADV_FROM_HANDLE(radv_device, device, _device);
708
709 device->ws->ctx_destroy(device->hw_ctx);
710 radv_queue_finish(&device->queue);
711 radv_device_finish_meta(device);
712
713 vk_free(&device->alloc, device);
714 }
715
716 VkResult radv_EnumerateInstanceExtensionProperties(
717 const char* pLayerName,
718 uint32_t* pPropertyCount,
719 VkExtensionProperties* pProperties)
720 {
721 if (pProperties == NULL) {
722 *pPropertyCount = ARRAY_SIZE(global_extensions);
723 return VK_SUCCESS;
724 }
725
726 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(global_extensions));
727 typed_memcpy(pProperties, global_extensions, *pPropertyCount);
728
729 if (*pPropertyCount < ARRAY_SIZE(global_extensions))
730 return VK_INCOMPLETE;
731
732 return VK_SUCCESS;
733 }
734
735 VkResult radv_EnumerateDeviceExtensionProperties(
736 VkPhysicalDevice physicalDevice,
737 const char* pLayerName,
738 uint32_t* pPropertyCount,
739 VkExtensionProperties* pProperties)
740 {
741 if (pProperties == NULL) {
742 *pPropertyCount = ARRAY_SIZE(device_extensions);
743 return VK_SUCCESS;
744 }
745
746 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(device_extensions));
747 typed_memcpy(pProperties, device_extensions, *pPropertyCount);
748
749 if (*pPropertyCount < ARRAY_SIZE(device_extensions))
750 return VK_INCOMPLETE;
751
752 return VK_SUCCESS;
753 }
754
755 VkResult radv_EnumerateInstanceLayerProperties(
756 uint32_t* pPropertyCount,
757 VkLayerProperties* pProperties)
758 {
759 if (pProperties == NULL) {
760 *pPropertyCount = 0;
761 return VK_SUCCESS;
762 }
763
764 /* None supported at this time */
765 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
766 }
767
768 VkResult radv_EnumerateDeviceLayerProperties(
769 VkPhysicalDevice physicalDevice,
770 uint32_t* pPropertyCount,
771 VkLayerProperties* pProperties)
772 {
773 if (pProperties == NULL) {
774 *pPropertyCount = 0;
775 return VK_SUCCESS;
776 }
777
778 /* None supported at this time */
779 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
780 }
781
782 void radv_GetDeviceQueue(
783 VkDevice _device,
784 uint32_t queueNodeIndex,
785 uint32_t queueIndex,
786 VkQueue* pQueue)
787 {
788 RADV_FROM_HANDLE(radv_device, device, _device);
789
790 assert(queueIndex == 0);
791
792 *pQueue = radv_queue_to_handle(&device->queue);
793 }
794
795 VkResult radv_QueueSubmit(
796 VkQueue _queue,
797 uint32_t submitCount,
798 const VkSubmitInfo* pSubmits,
799 VkFence _fence)
800 {
801 RADV_FROM_HANDLE(radv_queue, queue, _queue);
802 RADV_FROM_HANDLE(radv_fence, fence, _fence);
803 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
804 struct radeon_winsys_ctx *ctx = queue->device->hw_ctx;
805 int ret;
806
807 for (uint32_t i = 0; i < submitCount; i++) {
808 struct radeon_winsys_cs **cs_array;
809 bool can_patch = true;
810
811 if (!pSubmits[i].commandBufferCount)
812 continue;
813
814 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
815 pSubmits[i].commandBufferCount);
816
817 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
818 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
819 pSubmits[i].pCommandBuffers[j]);
820 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
821
822 cs_array[j] = cmd_buffer->cs;
823 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
824 can_patch = false;
825 }
826 ret = queue->device->ws->cs_submit(ctx, cs_array,
827 pSubmits[i].commandBufferCount,
828 can_patch, base_fence);
829 if (ret)
830 radv_loge("failed to submit CS %d\n", i);
831 free(cs_array);
832 }
833
834 if (fence) {
835 if (!submitCount)
836 ret = queue->device->ws->cs_submit(ctx, &queue->device->empty_cs,
837 1, false, base_fence);
838
839 fence->submitted = true;
840 }
841
842 return VK_SUCCESS;
843 }
844
845 VkResult radv_QueueWaitIdle(
846 VkQueue _queue)
847 {
848 RADV_FROM_HANDLE(radv_queue, queue, _queue);
849
850 queue->device->ws->ctx_wait_idle(queue->device->hw_ctx);
851 return VK_SUCCESS;
852 }
853
854 VkResult radv_DeviceWaitIdle(
855 VkDevice _device)
856 {
857 RADV_FROM_HANDLE(radv_device, device, _device);
858
859 device->ws->ctx_wait_idle(device->hw_ctx);
860 return VK_SUCCESS;
861 }
862
863 PFN_vkVoidFunction radv_GetInstanceProcAddr(
864 VkInstance instance,
865 const char* pName)
866 {
867 return radv_lookup_entrypoint(pName);
868 }
869
870 /* The loader wants us to expose a second GetInstanceProcAddr function
871 * to work around certain LD_PRELOAD issues seen in apps.
872 */
873 PUBLIC
874 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
875 VkInstance instance,
876 const char* pName);
877
878 PUBLIC
879 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
880 VkInstance instance,
881 const char* pName)
882 {
883 return radv_GetInstanceProcAddr(instance, pName);
884 }
885
886 PFN_vkVoidFunction radv_GetDeviceProcAddr(
887 VkDevice device,
888 const char* pName)
889 {
890 return radv_lookup_entrypoint(pName);
891 }
892
893 VkResult radv_AllocateMemory(
894 VkDevice _device,
895 const VkMemoryAllocateInfo* pAllocateInfo,
896 const VkAllocationCallbacks* pAllocator,
897 VkDeviceMemory* pMem)
898 {
899 RADV_FROM_HANDLE(radv_device, device, _device);
900 struct radv_device_memory *mem;
901 VkResult result;
902 enum radeon_bo_domain domain;
903 uint32_t flags = 0;
904 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
905
906 if (pAllocateInfo->allocationSize == 0) {
907 /* Apparently, this is allowed */
908 *pMem = VK_NULL_HANDLE;
909 return VK_SUCCESS;
910 }
911
912 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
913 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
914 if (mem == NULL)
915 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
916
917 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
918 if (pAllocateInfo->memoryTypeIndex == 1 || pAllocateInfo->memoryTypeIndex == 3)
919 domain = RADEON_DOMAIN_GTT;
920 else
921 domain = RADEON_DOMAIN_VRAM;
922
923 if (pAllocateInfo->memoryTypeIndex == 0)
924 flags |= RADEON_FLAG_NO_CPU_ACCESS;
925 else
926 flags |= RADEON_FLAG_CPU_ACCESS;
927
928 if (pAllocateInfo->memoryTypeIndex == 1)
929 flags |= RADEON_FLAG_GTT_WC;
930
931 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 32768,
932 domain, flags);
933
934 if (!mem->bo) {
935 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
936 goto fail;
937 }
938 mem->type_index = pAllocateInfo->memoryTypeIndex;
939
940 *pMem = radv_device_memory_to_handle(mem);
941
942 return VK_SUCCESS;
943
944 fail:
945 vk_free2(&device->alloc, pAllocator, mem);
946
947 return result;
948 }
949
950 void radv_FreeMemory(
951 VkDevice _device,
952 VkDeviceMemory _mem,
953 const VkAllocationCallbacks* pAllocator)
954 {
955 RADV_FROM_HANDLE(radv_device, device, _device);
956 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
957
958 if (mem == NULL)
959 return;
960
961 device->ws->buffer_destroy(mem->bo);
962 mem->bo = NULL;
963
964 vk_free2(&device->alloc, pAllocator, mem);
965 }
966
967 VkResult radv_MapMemory(
968 VkDevice _device,
969 VkDeviceMemory _memory,
970 VkDeviceSize offset,
971 VkDeviceSize size,
972 VkMemoryMapFlags flags,
973 void** ppData)
974 {
975 RADV_FROM_HANDLE(radv_device, device, _device);
976 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
977
978 if (mem == NULL) {
979 *ppData = NULL;
980 return VK_SUCCESS;
981 }
982
983 *ppData = device->ws->buffer_map(mem->bo);
984 if (*ppData) {
985 *ppData += offset;
986 return VK_SUCCESS;
987 }
988
989 return VK_ERROR_MEMORY_MAP_FAILED;
990 }
991
992 void radv_UnmapMemory(
993 VkDevice _device,
994 VkDeviceMemory _memory)
995 {
996 RADV_FROM_HANDLE(radv_device, device, _device);
997 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
998
999 if (mem == NULL)
1000 return;
1001
1002 device->ws->buffer_unmap(mem->bo);
1003 }
1004
1005 VkResult radv_FlushMappedMemoryRanges(
1006 VkDevice _device,
1007 uint32_t memoryRangeCount,
1008 const VkMappedMemoryRange* pMemoryRanges)
1009 {
1010 return VK_SUCCESS;
1011 }
1012
1013 VkResult radv_InvalidateMappedMemoryRanges(
1014 VkDevice _device,
1015 uint32_t memoryRangeCount,
1016 const VkMappedMemoryRange* pMemoryRanges)
1017 {
1018 return VK_SUCCESS;
1019 }
1020
1021 void radv_GetBufferMemoryRequirements(
1022 VkDevice device,
1023 VkBuffer _buffer,
1024 VkMemoryRequirements* pMemoryRequirements)
1025 {
1026 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1027
1028 /* The Vulkan spec (git aaed022) says:
1029 *
1030 * memoryTypeBits is a bitfield and contains one bit set for every
1031 * supported memory type for the resource. The bit `1<<i` is set if and
1032 * only if the memory type `i` in the VkPhysicalDeviceMemoryProperties
1033 * structure for the physical device is supported.
1034 *
1035 * We support exactly one memory type.
1036 */
1037 pMemoryRequirements->memoryTypeBits = 0x7;
1038
1039 pMemoryRequirements->size = buffer->size;
1040 pMemoryRequirements->alignment = 16;
1041 }
1042
1043 void radv_GetImageMemoryRequirements(
1044 VkDevice device,
1045 VkImage _image,
1046 VkMemoryRequirements* pMemoryRequirements)
1047 {
1048 RADV_FROM_HANDLE(radv_image, image, _image);
1049
1050 /* The Vulkan spec (git aaed022) says:
1051 *
1052 * memoryTypeBits is a bitfield and contains one bit set for every
1053 * supported memory type for the resource. The bit `1<<i` is set if and
1054 * only if the memory type `i` in the VkPhysicalDeviceMemoryProperties
1055 * structure for the physical device is supported.
1056 *
1057 * We support exactly one memory type.
1058 */
1059 pMemoryRequirements->memoryTypeBits = 0x7;
1060
1061 pMemoryRequirements->size = image->size;
1062 pMemoryRequirements->alignment = image->alignment;
1063 }
1064
1065 void radv_GetImageSparseMemoryRequirements(
1066 VkDevice device,
1067 VkImage image,
1068 uint32_t* pSparseMemoryRequirementCount,
1069 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
1070 {
1071 stub();
1072 }
1073
1074 void radv_GetDeviceMemoryCommitment(
1075 VkDevice device,
1076 VkDeviceMemory memory,
1077 VkDeviceSize* pCommittedMemoryInBytes)
1078 {
1079 *pCommittedMemoryInBytes = 0;
1080 }
1081
1082 VkResult radv_BindBufferMemory(
1083 VkDevice device,
1084 VkBuffer _buffer,
1085 VkDeviceMemory _memory,
1086 VkDeviceSize memoryOffset)
1087 {
1088 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1089 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1090
1091 if (mem) {
1092 buffer->bo = mem->bo;
1093 buffer->offset = memoryOffset;
1094 } else {
1095 buffer->bo = NULL;
1096 buffer->offset = 0;
1097 }
1098
1099 return VK_SUCCESS;
1100 }
1101
1102 VkResult radv_BindImageMemory(
1103 VkDevice device,
1104 VkImage _image,
1105 VkDeviceMemory _memory,
1106 VkDeviceSize memoryOffset)
1107 {
1108 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1109 RADV_FROM_HANDLE(radv_image, image, _image);
1110
1111 if (mem) {
1112 image->bo = mem->bo;
1113 image->offset = memoryOffset;
1114 } else {
1115 image->bo = NULL;
1116 image->offset = 0;
1117 }
1118
1119 return VK_SUCCESS;
1120 }
1121
1122 VkResult radv_QueueBindSparse(
1123 VkQueue queue,
1124 uint32_t bindInfoCount,
1125 const VkBindSparseInfo* pBindInfo,
1126 VkFence fence)
1127 {
1128 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER);
1129 }
1130
1131 VkResult radv_CreateFence(
1132 VkDevice _device,
1133 const VkFenceCreateInfo* pCreateInfo,
1134 const VkAllocationCallbacks* pAllocator,
1135 VkFence* pFence)
1136 {
1137 RADV_FROM_HANDLE(radv_device, device, _device);
1138 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
1139 sizeof(*fence), 8,
1140 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1141
1142 if (!fence)
1143 return VK_ERROR_OUT_OF_HOST_MEMORY;
1144
1145 memset(fence, 0, sizeof(*fence));
1146 fence->submitted = false;
1147 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
1148 fence->fence = device->ws->create_fence();
1149
1150
1151 *pFence = radv_fence_to_handle(fence);
1152
1153 return VK_SUCCESS;
1154 }
1155
1156 void radv_DestroyFence(
1157 VkDevice _device,
1158 VkFence _fence,
1159 const VkAllocationCallbacks* pAllocator)
1160 {
1161 RADV_FROM_HANDLE(radv_device, device, _device);
1162 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1163
1164 if (!fence)
1165 return;
1166 device->ws->destroy_fence(fence->fence);
1167 vk_free2(&device->alloc, pAllocator, fence);
1168 }
1169
1170 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
1171 {
1172 uint64_t current_time;
1173 struct timespec tv;
1174
1175 clock_gettime(CLOCK_MONOTONIC, &tv);
1176 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
1177
1178 timeout = MIN2(UINT64_MAX - current_time, timeout);
1179
1180 return current_time + timeout;
1181 }
1182
1183 VkResult radv_WaitForFences(
1184 VkDevice _device,
1185 uint32_t fenceCount,
1186 const VkFence* pFences,
1187 VkBool32 waitAll,
1188 uint64_t timeout)
1189 {
1190 RADV_FROM_HANDLE(radv_device, device, _device);
1191 timeout = radv_get_absolute_timeout(timeout);
1192
1193 if (!waitAll && fenceCount > 1) {
1194 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
1195 }
1196
1197 for (uint32_t i = 0; i < fenceCount; ++i) {
1198 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1199 bool expired = false;
1200
1201 if (fence->signalled)
1202 continue;
1203
1204 if (!fence->submitted)
1205 return VK_TIMEOUT;
1206
1207 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
1208 if (!expired)
1209 return VK_TIMEOUT;
1210
1211 fence->signalled = true;
1212 }
1213
1214 return VK_SUCCESS;
1215 }
1216
1217 VkResult radv_ResetFences(VkDevice device,
1218 uint32_t fenceCount,
1219 const VkFence *pFences)
1220 {
1221 for (unsigned i = 0; i < fenceCount; ++i) {
1222 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1223 fence->submitted = fence->signalled = false;
1224 }
1225
1226 return VK_SUCCESS;
1227 }
1228
1229 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
1230 {
1231 RADV_FROM_HANDLE(radv_device, device, _device);
1232 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1233
1234 if (fence->signalled)
1235 return VK_SUCCESS;
1236 if (!fence->submitted)
1237 return VK_NOT_READY;
1238
1239 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
1240 return VK_NOT_READY;
1241
1242 return VK_SUCCESS;
1243 }
1244
1245
1246 // Queue semaphore functions
1247
1248 VkResult radv_CreateSemaphore(
1249 VkDevice device,
1250 const VkSemaphoreCreateInfo* pCreateInfo,
1251 const VkAllocationCallbacks* pAllocator,
1252 VkSemaphore* pSemaphore)
1253 {
1254 /* The DRM execbuffer ioctl always execute in-oder, even between different
1255 * rings. As such, there's nothing to do for the user space semaphore.
1256 */
1257
1258 *pSemaphore = (VkSemaphore)1;
1259
1260 return VK_SUCCESS;
1261 }
1262
1263 void radv_DestroySemaphore(
1264 VkDevice device,
1265 VkSemaphore semaphore,
1266 const VkAllocationCallbacks* pAllocator)
1267 {
1268 }
1269
1270 VkResult radv_CreateEvent(
1271 VkDevice _device,
1272 const VkEventCreateInfo* pCreateInfo,
1273 const VkAllocationCallbacks* pAllocator,
1274 VkEvent* pEvent)
1275 {
1276 RADV_FROM_HANDLE(radv_device, device, _device);
1277 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
1278 sizeof(*event), 8,
1279 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1280
1281 if (!event)
1282 return VK_ERROR_OUT_OF_HOST_MEMORY;
1283
1284 event->bo = device->ws->buffer_create(device->ws, 8, 8,
1285 RADEON_DOMAIN_GTT,
1286 RADEON_FLAG_CPU_ACCESS);
1287 if (!event->bo) {
1288 vk_free2(&device->alloc, pAllocator, event);
1289 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1290 }
1291
1292 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
1293
1294 *pEvent = radv_event_to_handle(event);
1295
1296 return VK_SUCCESS;
1297 }
1298
1299 void radv_DestroyEvent(
1300 VkDevice _device,
1301 VkEvent _event,
1302 const VkAllocationCallbacks* pAllocator)
1303 {
1304 RADV_FROM_HANDLE(radv_device, device, _device);
1305 RADV_FROM_HANDLE(radv_event, event, _event);
1306
1307 if (!event)
1308 return;
1309 device->ws->buffer_destroy(event->bo);
1310 vk_free2(&device->alloc, pAllocator, event);
1311 }
1312
1313 VkResult radv_GetEventStatus(
1314 VkDevice _device,
1315 VkEvent _event)
1316 {
1317 RADV_FROM_HANDLE(radv_event, event, _event);
1318
1319 if (*event->map == 1)
1320 return VK_EVENT_SET;
1321 return VK_EVENT_RESET;
1322 }
1323
1324 VkResult radv_SetEvent(
1325 VkDevice _device,
1326 VkEvent _event)
1327 {
1328 RADV_FROM_HANDLE(radv_event, event, _event);
1329 *event->map = 1;
1330
1331 return VK_SUCCESS;
1332 }
1333
1334 VkResult radv_ResetEvent(
1335 VkDevice _device,
1336 VkEvent _event)
1337 {
1338 RADV_FROM_HANDLE(radv_event, event, _event);
1339 *event->map = 0;
1340
1341 return VK_SUCCESS;
1342 }
1343
1344 VkResult radv_CreateBuffer(
1345 VkDevice _device,
1346 const VkBufferCreateInfo* pCreateInfo,
1347 const VkAllocationCallbacks* pAllocator,
1348 VkBuffer* pBuffer)
1349 {
1350 RADV_FROM_HANDLE(radv_device, device, _device);
1351 struct radv_buffer *buffer;
1352
1353 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
1354
1355 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
1356 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1357 if (buffer == NULL)
1358 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1359
1360 buffer->size = pCreateInfo->size;
1361 buffer->usage = pCreateInfo->usage;
1362 buffer->bo = NULL;
1363 buffer->offset = 0;
1364
1365 *pBuffer = radv_buffer_to_handle(buffer);
1366
1367 return VK_SUCCESS;
1368 }
1369
1370 void radv_DestroyBuffer(
1371 VkDevice _device,
1372 VkBuffer _buffer,
1373 const VkAllocationCallbacks* pAllocator)
1374 {
1375 RADV_FROM_HANDLE(radv_device, device, _device);
1376 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1377
1378 if (!buffer)
1379 return;
1380
1381 vk_free2(&device->alloc, pAllocator, buffer);
1382 }
1383
1384 static inline unsigned
1385 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
1386 {
1387 if (stencil)
1388 return image->surface.stencil_tiling_index[level];
1389 else
1390 return image->surface.tiling_index[level];
1391 }
1392
1393 static void
1394 radv_initialise_color_surface(struct radv_device *device,
1395 struct radv_color_buffer_info *cb,
1396 struct radv_image_view *iview)
1397 {
1398 const struct vk_format_description *desc;
1399 unsigned ntype, format, swap, endian;
1400 unsigned blend_clamp = 0, blend_bypass = 0;
1401 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
1402 uint64_t va;
1403 const struct radeon_surf *surf = &iview->image->surface;
1404 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
1405
1406 desc = vk_format_description(iview->vk_format);
1407
1408 memset(cb, 0, sizeof(*cb));
1409
1410 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1411 va += level_info->offset;
1412 cb->cb_color_base = va >> 8;
1413
1414 /* CMASK variables */
1415 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1416 va += iview->image->cmask.offset;
1417 cb->cb_color_cmask = va >> 8;
1418 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
1419
1420 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1421 va += iview->image->dcc_offset;
1422 cb->cb_dcc_base = va >> 8;
1423
1424 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
1425 S_028C6C_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1426
1427 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
1428 pitch_tile_max = level_info->nblk_x / 8 - 1;
1429 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
1430 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
1431
1432 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
1433 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
1434
1435 /* Intensity is implemented as Red, so treat it that way. */
1436 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
1437 S_028C74_TILE_MODE_INDEX(tile_mode_index);
1438
1439 if (iview->image->samples > 1) {
1440 unsigned log_samples = util_logbase2(iview->image->samples);
1441
1442 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1443 S_028C74_NUM_FRAGMENTS(log_samples);
1444 }
1445
1446 if (iview->image->fmask.size) {
1447 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
1448 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1449 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
1450 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
1451 cb->cb_color_fmask = va >> 8;
1452 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
1453 } else {
1454 /* This must be set for fast clear to work without FMASK. */
1455 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1456 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
1457 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1458 cb->cb_color_fmask = cb->cb_color_base;
1459 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
1460 }
1461
1462 ntype = radv_translate_color_numformat(iview->vk_format,
1463 desc,
1464 vk_format_get_first_non_void_channel(iview->vk_format));
1465 format = radv_translate_colorformat(iview->vk_format);
1466 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
1467 radv_finishme("Illegal color\n");
1468 swap = radv_translate_colorswap(iview->vk_format, FALSE);
1469 endian = radv_colorformat_endian_swap(format);
1470
1471 /* blend clamp should be set for all NORM/SRGB types */
1472 if (ntype == V_028C70_NUMBER_UNORM ||
1473 ntype == V_028C70_NUMBER_SNORM ||
1474 ntype == V_028C70_NUMBER_SRGB)
1475 blend_clamp = 1;
1476
1477 /* set blend bypass according to docs if SINT/UINT or
1478 8/24 COLOR variants */
1479 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1480 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1481 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1482 blend_clamp = 0;
1483 blend_bypass = 1;
1484 }
1485 #if 0
1486 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
1487 (format == V_028C70_COLOR_8 ||
1488 format == V_028C70_COLOR_8_8 ||
1489 format == V_028C70_COLOR_8_8_8_8))
1490 ->color_is_int8 = true;
1491 #endif
1492 cb->cb_color_info = S_028C70_FORMAT(format) |
1493 S_028C70_COMP_SWAP(swap) |
1494 S_028C70_BLEND_CLAMP(blend_clamp) |
1495 S_028C70_BLEND_BYPASS(blend_bypass) |
1496 S_028C70_SIMPLE_FLOAT(1) |
1497 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
1498 ntype != V_028C70_NUMBER_SNORM &&
1499 ntype != V_028C70_NUMBER_SRGB &&
1500 format != V_028C70_COLOR_8_24 &&
1501 format != V_028C70_COLOR_24_8) |
1502 S_028C70_NUMBER_TYPE(ntype) |
1503 S_028C70_ENDIAN(endian);
1504 if (iview->image->samples > 1)
1505 if (iview->image->fmask.size)
1506 cb->cb_color_info |= S_028C70_COMPRESSION(1);
1507
1508 if (iview->image->cmask.size && device->allow_fast_clears)
1509 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
1510
1511 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
1512 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
1513
1514 if (device->instance->physicalDevice.rad_info.chip_class >= VI) {
1515 unsigned max_uncompressed_block_size = 2;
1516 if (iview->image->samples > 1) {
1517 if (iview->image->surface.bpe == 1)
1518 max_uncompressed_block_size = 0;
1519 else if (iview->image->surface.bpe == 2)
1520 max_uncompressed_block_size = 1;
1521 }
1522
1523 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
1524 S_028C78_INDEPENDENT_64B_BLOCKS(1);
1525 }
1526
1527 /* This must be set for fast clear to work without FMASK. */
1528 if (!iview->image->fmask.size &&
1529 device->instance->physicalDevice.rad_info.chip_class == SI) {
1530 unsigned bankh = util_logbase2(iview->image->surface.bankh);
1531 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1532 }
1533 }
1534
1535 static void
1536 radv_initialise_ds_surface(struct radv_device *device,
1537 struct radv_ds_buffer_info *ds,
1538 struct radv_image_view *iview)
1539 {
1540 unsigned level = iview->base_mip;
1541 unsigned format;
1542 uint64_t va, s_offs, z_offs;
1543 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
1544 memset(ds, 0, sizeof(*ds));
1545 switch (iview->vk_format) {
1546 case VK_FORMAT_D24_UNORM_S8_UINT:
1547 case VK_FORMAT_X8_D24_UNORM_PACK32:
1548 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1549 ds->offset_scale = 2.0f;
1550 break;
1551 case VK_FORMAT_D16_UNORM:
1552 case VK_FORMAT_D16_UNORM_S8_UINT:
1553 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1554 ds->offset_scale = 4.0f;
1555 break;
1556 case VK_FORMAT_D32_SFLOAT:
1557 case VK_FORMAT_D32_SFLOAT_S8_UINT:
1558 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1559 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1560 ds->offset_scale = 1.0f;
1561 break;
1562 default:
1563 break;
1564 }
1565
1566 format = radv_translate_dbformat(iview->vk_format);
1567 if (format == V_028040_Z_INVALID) {
1568 fprintf(stderr, "Invalid DB format: %d, disabling DB.\n", iview->vk_format);
1569 }
1570
1571 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1572 s_offs = z_offs = va;
1573 z_offs += iview->image->surface.level[level].offset;
1574 s_offs += iview->image->surface.stencil_level[level].offset;
1575
1576 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
1577 S_028008_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1578 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1579 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
1580
1581 if (iview->image->samples > 1)
1582 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
1583
1584 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
1585 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
1586 else
1587 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1588
1589 if (device->instance->physicalDevice.rad_info.chip_class >= CIK) {
1590 struct radeon_info *info = &device->instance->physicalDevice.rad_info;
1591 unsigned tiling_index = iview->image->surface.tiling_index[level];
1592 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
1593 unsigned macro_index = iview->image->surface.macro_tile_index;
1594 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
1595 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
1596 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
1597
1598 ds->db_depth_info |=
1599 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
1600 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
1601 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
1602 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
1603 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
1604 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
1605 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
1606 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
1607 } else {
1608 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
1609 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1610 tile_mode_index = si_tile_mode_index(iview->image, level, true);
1611 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1612 }
1613
1614 if (iview->image->htile.size && !level) {
1615 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1616 S_028040_ALLOW_EXPCLEAR(1);
1617
1618 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
1619 /* Workaround: For a not yet understood reason, the
1620 * combination of MSAA, fast stencil clear and stencil
1621 * decompress messes with subsequent stencil buffer
1622 * uses. Problem was reproduced on Verde, Bonaire,
1623 * Tonga, and Carrizo.
1624 *
1625 * Disabling EXPCLEAR works around the problem.
1626 *
1627 * Check piglit's arb_texture_multisample-stencil-clear
1628 * test if you want to try changing this.
1629 */
1630 if (iview->image->samples <= 1)
1631 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
1632 } else
1633 /* Use all of the htile_buffer for depth if there's no stencil. */
1634 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1635
1636 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
1637 iview->image->htile.offset;
1638 ds->db_htile_data_base = va >> 8;
1639 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
1640 } else {
1641 ds->db_htile_data_base = 0;
1642 ds->db_htile_surface = 0;
1643 }
1644
1645 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
1646 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
1647
1648 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
1649 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
1650 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
1651 }
1652
1653 VkResult radv_CreateFramebuffer(
1654 VkDevice _device,
1655 const VkFramebufferCreateInfo* pCreateInfo,
1656 const VkAllocationCallbacks* pAllocator,
1657 VkFramebuffer* pFramebuffer)
1658 {
1659 RADV_FROM_HANDLE(radv_device, device, _device);
1660 struct radv_framebuffer *framebuffer;
1661
1662 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
1663
1664 size_t size = sizeof(*framebuffer) +
1665 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
1666 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
1667 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1668 if (framebuffer == NULL)
1669 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1670
1671 framebuffer->attachment_count = pCreateInfo->attachmentCount;
1672 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
1673 VkImageView _iview = pCreateInfo->pAttachments[i];
1674 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
1675 framebuffer->attachments[i].attachment = iview;
1676 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
1677 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
1678 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
1679 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
1680 }
1681 }
1682
1683 framebuffer->width = pCreateInfo->width;
1684 framebuffer->height = pCreateInfo->height;
1685 framebuffer->layers = pCreateInfo->layers;
1686
1687 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
1688 return VK_SUCCESS;
1689 }
1690
1691 void radv_DestroyFramebuffer(
1692 VkDevice _device,
1693 VkFramebuffer _fb,
1694 const VkAllocationCallbacks* pAllocator)
1695 {
1696 RADV_FROM_HANDLE(radv_device, device, _device);
1697 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
1698
1699 if (!fb)
1700 return;
1701 vk_free2(&device->alloc, pAllocator, fb);
1702 }
1703
1704 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
1705 {
1706 switch (address_mode) {
1707 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
1708 return V_008F30_SQ_TEX_WRAP;
1709 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
1710 return V_008F30_SQ_TEX_MIRROR;
1711 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
1712 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1713 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
1714 return V_008F30_SQ_TEX_CLAMP_BORDER;
1715 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
1716 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1717 default:
1718 unreachable("illegal tex wrap mode");
1719 break;
1720 }
1721 }
1722
1723 static unsigned
1724 radv_tex_compare(VkCompareOp op)
1725 {
1726 switch (op) {
1727 case VK_COMPARE_OP_NEVER:
1728 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1729 case VK_COMPARE_OP_LESS:
1730 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1731 case VK_COMPARE_OP_EQUAL:
1732 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1733 case VK_COMPARE_OP_LESS_OR_EQUAL:
1734 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1735 case VK_COMPARE_OP_GREATER:
1736 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1737 case VK_COMPARE_OP_NOT_EQUAL:
1738 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1739 case VK_COMPARE_OP_GREATER_OR_EQUAL:
1740 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1741 case VK_COMPARE_OP_ALWAYS:
1742 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1743 default:
1744 unreachable("illegal compare mode");
1745 break;
1746 }
1747 }
1748
1749 static unsigned
1750 radv_tex_filter(VkFilter filter, unsigned max_ansio)
1751 {
1752 switch (filter) {
1753 case VK_FILTER_NEAREST:
1754 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
1755 V_008F38_SQ_TEX_XY_FILTER_POINT);
1756 case VK_FILTER_LINEAR:
1757 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
1758 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
1759 case VK_FILTER_CUBIC_IMG:
1760 default:
1761 fprintf(stderr, "illegal texture filter");
1762 return 0;
1763 }
1764 }
1765
1766 static unsigned
1767 radv_tex_mipfilter(VkSamplerMipmapMode mode)
1768 {
1769 switch (mode) {
1770 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
1771 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1772 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
1773 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1774 default:
1775 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1776 }
1777 }
1778
1779 static unsigned
1780 radv_tex_bordercolor(VkBorderColor bcolor)
1781 {
1782 switch (bcolor) {
1783 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
1784 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
1785 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
1786 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
1787 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
1788 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
1789 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
1790 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
1791 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
1792 default:
1793 break;
1794 }
1795 return 0;
1796 }
1797
1798 static unsigned
1799 radv_tex_aniso_filter(unsigned filter)
1800 {
1801 if (filter < 2)
1802 return 0;
1803 if (filter < 4)
1804 return 1;
1805 if (filter < 8)
1806 return 2;
1807 if (filter < 16)
1808 return 3;
1809 return 4;
1810 }
1811
1812 static void
1813 radv_init_sampler(struct radv_device *device,
1814 struct radv_sampler *sampler,
1815 const VkSamplerCreateInfo *pCreateInfo)
1816 {
1817 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
1818 (uint32_t) pCreateInfo->maxAnisotropy : 0;
1819 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
1820 bool is_vi = (device->instance->physicalDevice.rad_info.chip_class >= VI);
1821
1822 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
1823 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
1824 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
1825 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
1826 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
1827 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
1828 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
1829 S_008F30_ANISO_BIAS(max_aniso_ratio) |
1830 S_008F30_DISABLE_CUBE_WRAP(0) |
1831 S_008F30_COMPAT_MODE(is_vi));
1832 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
1833 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
1834 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
1835 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
1836 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
1837 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
1838 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
1839 S_008F38_MIP_POINT_PRECLAMP(1) |
1840 S_008F38_DISABLE_LSB_CEIL(1) |
1841 S_008F38_FILTER_PREC_FIX(1) |
1842 S_008F38_ANISO_OVERRIDE(is_vi));
1843 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
1844 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
1845 }
1846
1847 VkResult radv_CreateSampler(
1848 VkDevice _device,
1849 const VkSamplerCreateInfo* pCreateInfo,
1850 const VkAllocationCallbacks* pAllocator,
1851 VkSampler* pSampler)
1852 {
1853 RADV_FROM_HANDLE(radv_device, device, _device);
1854 struct radv_sampler *sampler;
1855
1856 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
1857
1858 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
1859 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1860 if (!sampler)
1861 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1862
1863 radv_init_sampler(device, sampler, pCreateInfo);
1864 *pSampler = radv_sampler_to_handle(sampler);
1865
1866 return VK_SUCCESS;
1867 }
1868
1869 void radv_DestroySampler(
1870 VkDevice _device,
1871 VkSampler _sampler,
1872 const VkAllocationCallbacks* pAllocator)
1873 {
1874 RADV_FROM_HANDLE(radv_device, device, _device);
1875 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
1876
1877 if (!sampler)
1878 return;
1879 vk_free2(&device->alloc, pAllocator, sampler);
1880 }