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radv: expose the compute queue
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <dlfcn.h>
29 #include <stdbool.h>
30 #include <string.h>
31 #include <unistd.h>
32 #include <fcntl.h>
33 #include <sys/stat.h>
34 #include "radv_private.h"
35 #include "util/strtod.h"
36
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "util/debug.h"
46 struct radv_dispatch_table dtable;
47
48 static int
49 radv_get_function_timestamp(void *ptr, uint32_t* timestamp)
50 {
51 Dl_info info;
52 struct stat st;
53 if (!dladdr(ptr, &info) || !info.dli_fname) {
54 return -1;
55 }
56 if (stat(info.dli_fname, &st)) {
57 return -1;
58 }
59 *timestamp = st.st_mtim.tv_sec;
60 return 0;
61 }
62
63 static int
64 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
65 {
66 uint32_t mesa_timestamp, llvm_timestamp;
67 uint16_t f = family;
68 memset(uuid, 0, VK_UUID_SIZE);
69 if (radv_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
70 radv_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
71 return -1;
72
73 memcpy(uuid, &mesa_timestamp, 4);
74 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
75 memcpy((char*)uuid + 8, &f, 2);
76 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
77 return 0;
78 }
79
80 static VkResult
81 radv_physical_device_init(struct radv_physical_device *device,
82 struct radv_instance *instance,
83 const char *path)
84 {
85 VkResult result;
86 drmVersionPtr version;
87 int fd;
88
89 fd = open(path, O_RDWR | O_CLOEXEC);
90 if (fd < 0)
91 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
92 "failed to open %s: %m", path);
93
94 version = drmGetVersion(fd);
95 if (!version) {
96 close(fd);
97 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
98 "failed to get version %s: %m", path);
99 }
100
101 if (strcmp(version->name, "amdgpu")) {
102 drmFreeVersion(version);
103 close(fd);
104 return VK_ERROR_INCOMPATIBLE_DRIVER;
105 }
106 drmFreeVersion(version);
107
108 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
109 device->instance = instance;
110 assert(strlen(path) < ARRAY_SIZE(device->path));
111 strncpy(device->path, path, ARRAY_SIZE(device->path));
112
113 device->ws = radv_amdgpu_winsys_create(fd);
114 if (!device->ws) {
115 result = VK_ERROR_INCOMPATIBLE_DRIVER;
116 goto fail;
117 }
118 device->ws->query_info(device->ws, &device->rad_info);
119 result = radv_init_wsi(device);
120 if (result != VK_SUCCESS) {
121 device->ws->destroy(device->ws);
122 goto fail;
123 }
124
125 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
126 radv_finish_wsi(device);
127 device->ws->destroy(device->ws);
128 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
129 "cannot generate UUID");
130 goto fail;
131 }
132
133 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
134 device->name = device->rad_info.name;
135 close(fd);
136 return VK_SUCCESS;
137
138 fail:
139 close(fd);
140 return result;
141 }
142
143 static void
144 radv_physical_device_finish(struct radv_physical_device *device)
145 {
146 radv_finish_wsi(device);
147 device->ws->destroy(device->ws);
148 }
149
150 static const VkExtensionProperties global_extensions[] = {
151 {
152 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
153 .specVersion = 25,
154 },
155 #ifdef VK_USE_PLATFORM_XCB_KHR
156 {
157 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
158 .specVersion = 6,
159 },
160 #endif
161 #ifdef VK_USE_PLATFORM_XLIB_KHR
162 {
163 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
164 .specVersion = 6,
165 },
166 #endif
167 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
168 {
169 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
170 .specVersion = 5,
171 },
172 #endif
173 };
174
175 static const VkExtensionProperties device_extensions[] = {
176 {
177 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
178 .specVersion = 1,
179 },
180 {
181 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
182 .specVersion = 68,
183 },
184 {
185 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
186 .specVersion = 1,
187 },
188 {
189 .extensionName = VK_AMD_NEGATIVE_VIEWPORT_HEIGHT_EXTENSION_NAME,
190 .specVersion = 1,
191 },
192 };
193
194 static void *
195 default_alloc_func(void *pUserData, size_t size, size_t align,
196 VkSystemAllocationScope allocationScope)
197 {
198 return malloc(size);
199 }
200
201 static void *
202 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
203 size_t align, VkSystemAllocationScope allocationScope)
204 {
205 return realloc(pOriginal, size);
206 }
207
208 static void
209 default_free_func(void *pUserData, void *pMemory)
210 {
211 free(pMemory);
212 }
213
214 static const VkAllocationCallbacks default_alloc = {
215 .pUserData = NULL,
216 .pfnAllocation = default_alloc_func,
217 .pfnReallocation = default_realloc_func,
218 .pfnFree = default_free_func,
219 };
220
221 VkResult radv_CreateInstance(
222 const VkInstanceCreateInfo* pCreateInfo,
223 const VkAllocationCallbacks* pAllocator,
224 VkInstance* pInstance)
225 {
226 struct radv_instance *instance;
227
228 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
229
230 uint32_t client_version;
231 if (pCreateInfo->pApplicationInfo &&
232 pCreateInfo->pApplicationInfo->apiVersion != 0) {
233 client_version = pCreateInfo->pApplicationInfo->apiVersion;
234 } else {
235 client_version = VK_MAKE_VERSION(1, 0, 0);
236 }
237
238 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
239 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
240 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
241 "Client requested version %d.%d.%d",
242 VK_VERSION_MAJOR(client_version),
243 VK_VERSION_MINOR(client_version),
244 VK_VERSION_PATCH(client_version));
245 }
246
247 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
248 bool found = false;
249 for (uint32_t j = 0; j < ARRAY_SIZE(global_extensions); j++) {
250 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
251 global_extensions[j].extensionName) == 0) {
252 found = true;
253 break;
254 }
255 }
256 if (!found)
257 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
258 }
259
260 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
262 if (!instance)
263 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
264
265 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266
267 if (pAllocator)
268 instance->alloc = *pAllocator;
269 else
270 instance->alloc = default_alloc;
271
272 instance->apiVersion = client_version;
273 instance->physicalDeviceCount = -1;
274
275 _mesa_locale_init();
276
277 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
278
279 *pInstance = radv_instance_to_handle(instance);
280
281 return VK_SUCCESS;
282 }
283
284 void radv_DestroyInstance(
285 VkInstance _instance,
286 const VkAllocationCallbacks* pAllocator)
287 {
288 RADV_FROM_HANDLE(radv_instance, instance, _instance);
289
290 if (instance->physicalDeviceCount > 0) {
291 /* We support at most one physical device. */
292 assert(instance->physicalDeviceCount == 1);
293 radv_physical_device_finish(&instance->physicalDevice);
294 }
295
296 VG(VALGRIND_DESTROY_MEMPOOL(instance));
297
298 _mesa_locale_fini();
299
300 vk_free(&instance->alloc, instance);
301 }
302
303 VkResult radv_EnumeratePhysicalDevices(
304 VkInstance _instance,
305 uint32_t* pPhysicalDeviceCount,
306 VkPhysicalDevice* pPhysicalDevices)
307 {
308 RADV_FROM_HANDLE(radv_instance, instance, _instance);
309 VkResult result;
310
311 if (instance->physicalDeviceCount < 0) {
312 char path[20];
313 for (unsigned i = 0; i < 8; i++) {
314 snprintf(path, sizeof(path), "/dev/dri/renderD%d", 128 + i);
315 result = radv_physical_device_init(&instance->physicalDevice,
316 instance, path);
317 if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
318 break;
319 }
320
321 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
322 instance->physicalDeviceCount = 0;
323 } else if (result == VK_SUCCESS) {
324 instance->physicalDeviceCount = 1;
325 } else {
326 return result;
327 }
328 }
329
330 /* pPhysicalDeviceCount is an out parameter if pPhysicalDevices is NULL;
331 * otherwise it's an inout parameter.
332 *
333 * The Vulkan spec (git aaed022) says:
334 *
335 * pPhysicalDeviceCount is a pointer to an unsigned integer variable
336 * that is initialized with the number of devices the application is
337 * prepared to receive handles to. pname:pPhysicalDevices is pointer to
338 * an array of at least this many VkPhysicalDevice handles [...].
339 *
340 * Upon success, if pPhysicalDevices is NULL, vkEnumeratePhysicalDevices
341 * overwrites the contents of the variable pointed to by
342 * pPhysicalDeviceCount with the number of physical devices in in the
343 * instance; otherwise, vkEnumeratePhysicalDevices overwrites
344 * pPhysicalDeviceCount with the number of physical handles written to
345 * pPhysicalDevices.
346 */
347 if (!pPhysicalDevices) {
348 *pPhysicalDeviceCount = instance->physicalDeviceCount;
349 } else if (*pPhysicalDeviceCount >= 1) {
350 pPhysicalDevices[0] = radv_physical_device_to_handle(&instance->physicalDevice);
351 *pPhysicalDeviceCount = 1;
352 } else if (*pPhysicalDeviceCount < instance->physicalDeviceCount) {
353 return VK_INCOMPLETE;
354 } else {
355 *pPhysicalDeviceCount = 0;
356 }
357
358 return VK_SUCCESS;
359 }
360
361 void radv_GetPhysicalDeviceFeatures(
362 VkPhysicalDevice physicalDevice,
363 VkPhysicalDeviceFeatures* pFeatures)
364 {
365 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
366
367 memset(pFeatures, 0, sizeof(*pFeatures));
368
369 *pFeatures = (VkPhysicalDeviceFeatures) {
370 .robustBufferAccess = true,
371 .fullDrawIndexUint32 = true,
372 .imageCubeArray = true,
373 .independentBlend = true,
374 .geometryShader = false,
375 .tessellationShader = false,
376 .sampleRateShading = false,
377 .dualSrcBlend = true,
378 .logicOp = true,
379 .multiDrawIndirect = true,
380 .drawIndirectFirstInstance = true,
381 .depthClamp = true,
382 .depthBiasClamp = true,
383 .fillModeNonSolid = true,
384 .depthBounds = true,
385 .wideLines = true,
386 .largePoints = true,
387 .alphaToOne = true,
388 .multiViewport = false,
389 .samplerAnisotropy = true,
390 .textureCompressionETC2 = false,
391 .textureCompressionASTC_LDR = false,
392 .textureCompressionBC = true,
393 .occlusionQueryPrecise = true,
394 .pipelineStatisticsQuery = false,
395 .vertexPipelineStoresAndAtomics = true,
396 .fragmentStoresAndAtomics = true,
397 .shaderTessellationAndGeometryPointSize = true,
398 .shaderImageGatherExtended = false,
399 .shaderStorageImageExtendedFormats = false,
400 .shaderStorageImageMultisample = false,
401 .shaderUniformBufferArrayDynamicIndexing = true,
402 .shaderSampledImageArrayDynamicIndexing = true,
403 .shaderStorageBufferArrayDynamicIndexing = true,
404 .shaderStorageImageArrayDynamicIndexing = true,
405 .shaderStorageImageReadWithoutFormat = false,
406 .shaderStorageImageWriteWithoutFormat = true,
407 .shaderClipDistance = true,
408 .shaderCullDistance = true,
409 .shaderFloat64 = false,
410 .shaderInt64 = false,
411 .shaderInt16 = false,
412 .alphaToOne = true,
413 .variableMultisampleRate = false,
414 .inheritedQueries = false,
415 };
416 }
417
418 void radv_GetPhysicalDeviceProperties(
419 VkPhysicalDevice physicalDevice,
420 VkPhysicalDeviceProperties* pProperties)
421 {
422 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
423 VkSampleCountFlags sample_counts = 0xf;
424 VkPhysicalDeviceLimits limits = {
425 .maxImageDimension1D = (1 << 14),
426 .maxImageDimension2D = (1 << 14),
427 .maxImageDimension3D = (1 << 11),
428 .maxImageDimensionCube = (1 << 14),
429 .maxImageArrayLayers = (1 << 11),
430 .maxTexelBufferElements = 128 * 1024 * 1024,
431 .maxUniformBufferRange = UINT32_MAX,
432 .maxStorageBufferRange = UINT32_MAX,
433 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
434 .maxMemoryAllocationCount = UINT32_MAX,
435 .maxSamplerAllocationCount = 64 * 1024,
436 .bufferImageGranularity = 64, /* A cache line */
437 .sparseAddressSpaceSize = 0,
438 .maxBoundDescriptorSets = MAX_SETS,
439 .maxPerStageDescriptorSamplers = 64,
440 .maxPerStageDescriptorUniformBuffers = 64,
441 .maxPerStageDescriptorStorageBuffers = 64,
442 .maxPerStageDescriptorSampledImages = 64,
443 .maxPerStageDescriptorStorageImages = 64,
444 .maxPerStageDescriptorInputAttachments = 64,
445 .maxPerStageResources = 128,
446 .maxDescriptorSetSamplers = 256,
447 .maxDescriptorSetUniformBuffers = 256,
448 .maxDescriptorSetUniformBuffersDynamic = 256,
449 .maxDescriptorSetStorageBuffers = 256,
450 .maxDescriptorSetStorageBuffersDynamic = 256,
451 .maxDescriptorSetSampledImages = 256,
452 .maxDescriptorSetStorageImages = 256,
453 .maxDescriptorSetInputAttachments = 256,
454 .maxVertexInputAttributes = 32,
455 .maxVertexInputBindings = 32,
456 .maxVertexInputAttributeOffset = 2047,
457 .maxVertexInputBindingStride = 2048,
458 .maxVertexOutputComponents = 128,
459 .maxTessellationGenerationLevel = 0,
460 .maxTessellationPatchSize = 0,
461 .maxTessellationControlPerVertexInputComponents = 0,
462 .maxTessellationControlPerVertexOutputComponents = 0,
463 .maxTessellationControlPerPatchOutputComponents = 0,
464 .maxTessellationControlTotalOutputComponents = 0,
465 .maxTessellationEvaluationInputComponents = 0,
466 .maxTessellationEvaluationOutputComponents = 0,
467 .maxGeometryShaderInvocations = 32,
468 .maxGeometryInputComponents = 64,
469 .maxGeometryOutputComponents = 128,
470 .maxGeometryOutputVertices = 256,
471 .maxGeometryTotalOutputComponents = 1024,
472 .maxFragmentInputComponents = 128,
473 .maxFragmentOutputAttachments = 8,
474 .maxFragmentDualSrcAttachments = 1,
475 .maxFragmentCombinedOutputResources = 8,
476 .maxComputeSharedMemorySize = 32768,
477 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
478 .maxComputeWorkGroupInvocations = 16 * 1024,
479 .maxComputeWorkGroupSize = {
480 16 * 1024/*devinfo->max_cs_threads*/,
481 16 * 1024,
482 16 * 1024
483 },
484 .subPixelPrecisionBits = 4 /* FIXME */,
485 .subTexelPrecisionBits = 4 /* FIXME */,
486 .mipmapPrecisionBits = 4 /* FIXME */,
487 .maxDrawIndexedIndexValue = UINT32_MAX,
488 .maxDrawIndirectCount = UINT32_MAX,
489 .maxSamplerLodBias = 16,
490 .maxSamplerAnisotropy = 16,
491 .maxViewports = MAX_VIEWPORTS,
492 .maxViewportDimensions = { (1 << 14), (1 << 14) },
493 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
494 .viewportSubPixelBits = 13, /* We take a float? */
495 .minMemoryMapAlignment = 4096, /* A page */
496 .minTexelBufferOffsetAlignment = 1,
497 .minUniformBufferOffsetAlignment = 4,
498 .minStorageBufferOffsetAlignment = 4,
499 .minTexelOffset = -8,
500 .maxTexelOffset = 7,
501 .minTexelGatherOffset = -8,
502 .maxTexelGatherOffset = 7,
503 .minInterpolationOffset = 0, /* FIXME */
504 .maxInterpolationOffset = 0, /* FIXME */
505 .subPixelInterpolationOffsetBits = 0, /* FIXME */
506 .maxFramebufferWidth = (1 << 14),
507 .maxFramebufferHeight = (1 << 14),
508 .maxFramebufferLayers = (1 << 10),
509 .framebufferColorSampleCounts = sample_counts,
510 .framebufferDepthSampleCounts = sample_counts,
511 .framebufferStencilSampleCounts = sample_counts,
512 .framebufferNoAttachmentsSampleCounts = sample_counts,
513 .maxColorAttachments = MAX_RTS,
514 .sampledImageColorSampleCounts = sample_counts,
515 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
516 .sampledImageDepthSampleCounts = sample_counts,
517 .sampledImageStencilSampleCounts = sample_counts,
518 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
519 .maxSampleMaskWords = 1,
520 .timestampComputeAndGraphics = false,
521 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
522 .maxClipDistances = 8,
523 .maxCullDistances = 8,
524 .maxCombinedClipAndCullDistances = 8,
525 .discreteQueuePriorities = 1,
526 .pointSizeRange = { 0.125, 255.875 },
527 .lineWidthRange = { 0.0, 7.9921875 },
528 .pointSizeGranularity = (1.0 / 8.0),
529 .lineWidthGranularity = (1.0 / 128.0),
530 .strictLines = false, /* FINISHME */
531 .standardSampleLocations = true,
532 .optimalBufferCopyOffsetAlignment = 128,
533 .optimalBufferCopyRowPitchAlignment = 128,
534 .nonCoherentAtomSize = 64,
535 };
536
537 *pProperties = (VkPhysicalDeviceProperties) {
538 .apiVersion = VK_MAKE_VERSION(1, 0, 5),
539 .driverVersion = 1,
540 .vendorID = 0x1002,
541 .deviceID = pdevice->rad_info.pci_id,
542 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
543 .limits = limits,
544 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
545 };
546
547 strcpy(pProperties->deviceName, pdevice->name);
548 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
549 }
550
551 void radv_GetPhysicalDeviceQueueFamilyProperties(
552 VkPhysicalDevice physicalDevice,
553 uint32_t* pCount,
554 VkQueueFamilyProperties* pQueueFamilyProperties)
555 {
556 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
557 int num_queue_families = 1;
558 bool all_queues = env_var_as_boolean("RADV_SHOW_QUEUES", true);
559 int idx;
560 if (all_queues && pdevice->rad_info.chip_class >= CIK) {
561 if (pdevice->rad_info.compute_rings > 0)
562 num_queue_families++;
563 }
564
565 if (pQueueFamilyProperties == NULL) {
566 *pCount = num_queue_families;
567 return;
568 }
569
570 if (!*pCount)
571 return;
572
573 idx = 0;
574 if (*pCount >= 1) {
575 pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
576 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
577 VK_QUEUE_COMPUTE_BIT |
578 VK_QUEUE_TRANSFER_BIT,
579 .queueCount = 1,
580 .timestampValidBits = 64,
581 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
582 };
583 idx++;
584 }
585
586 if (!all_queues)
587 return;
588
589 if (pdevice->rad_info.compute_rings > 0 && pdevice->rad_info.chip_class >= CIK) {
590 if (*pCount > idx) {
591 pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
592 .queueFlags = VK_QUEUE_COMPUTE_BIT | VK_QUEUE_TRANSFER_BIT,
593 .queueCount = pdevice->rad_info.compute_rings,
594 .timestampValidBits = 64,
595 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
596 };
597 idx++;
598 }
599 }
600 }
601
602 void radv_GetPhysicalDeviceMemoryProperties(
603 VkPhysicalDevice physicalDevice,
604 VkPhysicalDeviceMemoryProperties* pMemoryProperties)
605 {
606 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
607
608 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
609
610 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
611 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
612 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
613 .heapIndex = RADV_MEM_HEAP_VRAM,
614 };
615 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
616 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
617 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
618 .heapIndex = RADV_MEM_HEAP_GTT,
619 };
620 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
621 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
622 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
623 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
624 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
625 };
626 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
627 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
628 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
629 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
630 .heapIndex = RADV_MEM_HEAP_GTT,
631 };
632
633 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
634
635 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
636 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
637 .size = physical_device->rad_info.vram_size -
638 physical_device->rad_info.visible_vram_size,
639 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
640 };
641 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
642 .size = physical_device->rad_info.visible_vram_size,
643 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
644 };
645 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
646 .size = physical_device->rad_info.gart_size,
647 .flags = 0,
648 };
649 }
650
651 static void
652 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
653 int queue_family_index, int idx)
654 {
655 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
656 queue->device = device;
657 queue->queue_family_index = queue_family_index;
658 queue->queue_idx = idx;
659 }
660
661 static void
662 radv_queue_finish(struct radv_queue *queue)
663 {
664 }
665
666 VkResult radv_CreateDevice(
667 VkPhysicalDevice physicalDevice,
668 const VkDeviceCreateInfo* pCreateInfo,
669 const VkAllocationCallbacks* pAllocator,
670 VkDevice* pDevice)
671 {
672 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
673 VkResult result;
674 struct radv_device *device;
675
676 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
677 bool found = false;
678 for (uint32_t j = 0; j < ARRAY_SIZE(device_extensions); j++) {
679 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
680 device_extensions[j].extensionName) == 0) {
681 found = true;
682 break;
683 }
684 }
685 if (!found)
686 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
687 }
688
689 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
690 sizeof(*device), 8,
691 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
692 if (!device)
693 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
694
695 memset(device, 0, sizeof(*device));
696
697 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
698 device->instance = physical_device->instance;
699 device->shader_stats_dump = false;
700
701 device->ws = physical_device->ws;
702 if (pAllocator)
703 device->alloc = *pAllocator;
704 else
705 device->alloc = physical_device->instance->alloc;
706
707 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
708 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
709 uint32_t qfi = queue_create->queueFamilyIndex;
710
711 device->queues[qfi] = vk_alloc(&device->alloc,
712 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
713 if (!device->queues[qfi]) {
714 result = VK_ERROR_OUT_OF_HOST_MEMORY;
715 goto fail;
716 }
717
718 device->queue_count[qfi] = queue_create->queueCount;
719
720 for (unsigned q = 0; q < queue_create->queueCount; q++)
721 radv_queue_init(device, &device->queues[qfi][q], qfi, q);
722 }
723
724 device->hw_ctx = device->ws->ctx_create(device->ws);
725 if (!device->hw_ctx) {
726 result = VK_ERROR_OUT_OF_HOST_MEMORY;
727 goto fail;
728 }
729
730 result = radv_device_init_meta(device);
731 if (result != VK_SUCCESS) {
732 device->ws->ctx_destroy(device->hw_ctx);
733 goto fail;
734 }
735 device->allow_fast_clears = env_var_as_boolean("RADV_FAST_CLEARS", false);
736 device->allow_dcc = !env_var_as_boolean("RADV_DCC_DISABLE", false);
737 device->shader_stats_dump = env_var_as_boolean("RADV_SHADER_STATS", false);
738
739 if (device->allow_fast_clears && device->allow_dcc)
740 radv_finishme("DCC fast clears have not been tested\n");
741
742 radv_device_init_msaa(device);
743
744 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
745 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
746 switch (family) {
747 case RADV_QUEUE_GENERAL:
748 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
749 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
750 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
751 break;
752 case RADV_QUEUE_COMPUTE:
753 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
754 radeon_emit(device->empty_cs[family], 0);
755 break;
756 }
757 device->ws->cs_finalize(device->empty_cs[family]);
758 }
759
760 *pDevice = radv_device_to_handle(device);
761 return VK_SUCCESS;
762
763 fail:
764 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
765 for (unsigned q = 0; q < device->queue_count[i]; q++)
766 radv_queue_finish(&device->queues[i][q]);
767 if (device->queue_count[i])
768 vk_free(&device->alloc, device->queues[i]);
769 }
770 vk_free(&device->alloc, device);
771 return result;
772 }
773
774 void radv_DestroyDevice(
775 VkDevice _device,
776 const VkAllocationCallbacks* pAllocator)
777 {
778 RADV_FROM_HANDLE(radv_device, device, _device);
779
780 device->ws->ctx_destroy(device->hw_ctx);
781 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
782 for (unsigned q = 0; q < device->queue_count[i]; q++)
783 radv_queue_finish(&device->queues[i][q]);
784 if (device->queue_count[i])
785 vk_free(&device->alloc, device->queues[i]);
786 }
787 radv_device_finish_meta(device);
788
789 vk_free(&device->alloc, device);
790 }
791
792 VkResult radv_EnumerateInstanceExtensionProperties(
793 const char* pLayerName,
794 uint32_t* pPropertyCount,
795 VkExtensionProperties* pProperties)
796 {
797 if (pProperties == NULL) {
798 *pPropertyCount = ARRAY_SIZE(global_extensions);
799 return VK_SUCCESS;
800 }
801
802 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(global_extensions));
803 typed_memcpy(pProperties, global_extensions, *pPropertyCount);
804
805 if (*pPropertyCount < ARRAY_SIZE(global_extensions))
806 return VK_INCOMPLETE;
807
808 return VK_SUCCESS;
809 }
810
811 VkResult radv_EnumerateDeviceExtensionProperties(
812 VkPhysicalDevice physicalDevice,
813 const char* pLayerName,
814 uint32_t* pPropertyCount,
815 VkExtensionProperties* pProperties)
816 {
817 if (pProperties == NULL) {
818 *pPropertyCount = ARRAY_SIZE(device_extensions);
819 return VK_SUCCESS;
820 }
821
822 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(device_extensions));
823 typed_memcpy(pProperties, device_extensions, *pPropertyCount);
824
825 if (*pPropertyCount < ARRAY_SIZE(device_extensions))
826 return VK_INCOMPLETE;
827
828 return VK_SUCCESS;
829 }
830
831 VkResult radv_EnumerateInstanceLayerProperties(
832 uint32_t* pPropertyCount,
833 VkLayerProperties* pProperties)
834 {
835 if (pProperties == NULL) {
836 *pPropertyCount = 0;
837 return VK_SUCCESS;
838 }
839
840 /* None supported at this time */
841 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
842 }
843
844 VkResult radv_EnumerateDeviceLayerProperties(
845 VkPhysicalDevice physicalDevice,
846 uint32_t* pPropertyCount,
847 VkLayerProperties* pProperties)
848 {
849 if (pProperties == NULL) {
850 *pPropertyCount = 0;
851 return VK_SUCCESS;
852 }
853
854 /* None supported at this time */
855 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
856 }
857
858 void radv_GetDeviceQueue(
859 VkDevice _device,
860 uint32_t queueFamilyIndex,
861 uint32_t queueIndex,
862 VkQueue* pQueue)
863 {
864 RADV_FROM_HANDLE(radv_device, device, _device);
865
866 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
867 }
868
869 VkResult radv_QueueSubmit(
870 VkQueue _queue,
871 uint32_t submitCount,
872 const VkSubmitInfo* pSubmits,
873 VkFence _fence)
874 {
875 RADV_FROM_HANDLE(radv_queue, queue, _queue);
876 RADV_FROM_HANDLE(radv_fence, fence, _fence);
877 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
878 struct radeon_winsys_ctx *ctx = queue->device->hw_ctx;
879 int ret;
880
881 for (uint32_t i = 0; i < submitCount; i++) {
882 struct radeon_winsys_cs **cs_array;
883 bool can_patch = true;
884
885 if (!pSubmits[i].commandBufferCount)
886 continue;
887
888 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
889 pSubmits[i].commandBufferCount);
890
891 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
892 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
893 pSubmits[i].pCommandBuffers[j]);
894 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
895
896 cs_array[j] = cmd_buffer->cs;
897 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
898 can_patch = false;
899 }
900 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array,
901 pSubmits[i].commandBufferCount,
902 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
903 pSubmits[i].waitSemaphoreCount,
904 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
905 pSubmits[i].signalSemaphoreCount,
906 can_patch, base_fence);
907 if (ret)
908 radv_loge("failed to submit CS %d\n", i);
909 free(cs_array);
910 }
911
912 if (fence) {
913 if (!submitCount)
914 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
915 &queue->device->empty_cs[queue->queue_family_index],
916 1, NULL, 0, NULL, 0, false, base_fence);
917
918 fence->submitted = true;
919 }
920
921 return VK_SUCCESS;
922 }
923
924 VkResult radv_QueueWaitIdle(
925 VkQueue _queue)
926 {
927 RADV_FROM_HANDLE(radv_queue, queue, _queue);
928
929 queue->device->ws->ctx_wait_idle(queue->device->hw_ctx,
930 radv_queue_family_to_ring(queue->queue_family_index),
931 queue->queue_idx);
932 return VK_SUCCESS;
933 }
934
935 VkResult radv_DeviceWaitIdle(
936 VkDevice _device)
937 {
938 RADV_FROM_HANDLE(radv_device, device, _device);
939
940 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
941 for (unsigned q = 0; q < device->queue_count[i]; q++) {
942 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
943 }
944 }
945 return VK_SUCCESS;
946 }
947
948 PFN_vkVoidFunction radv_GetInstanceProcAddr(
949 VkInstance instance,
950 const char* pName)
951 {
952 return radv_lookup_entrypoint(pName);
953 }
954
955 /* The loader wants us to expose a second GetInstanceProcAddr function
956 * to work around certain LD_PRELOAD issues seen in apps.
957 */
958 PUBLIC
959 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
960 VkInstance instance,
961 const char* pName);
962
963 PUBLIC
964 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
965 VkInstance instance,
966 const char* pName)
967 {
968 return radv_GetInstanceProcAddr(instance, pName);
969 }
970
971 PFN_vkVoidFunction radv_GetDeviceProcAddr(
972 VkDevice device,
973 const char* pName)
974 {
975 return radv_lookup_entrypoint(pName);
976 }
977
978 VkResult radv_AllocateMemory(
979 VkDevice _device,
980 const VkMemoryAllocateInfo* pAllocateInfo,
981 const VkAllocationCallbacks* pAllocator,
982 VkDeviceMemory* pMem)
983 {
984 RADV_FROM_HANDLE(radv_device, device, _device);
985 struct radv_device_memory *mem;
986 VkResult result;
987 enum radeon_bo_domain domain;
988 uint32_t flags = 0;
989 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
990
991 if (pAllocateInfo->allocationSize == 0) {
992 /* Apparently, this is allowed */
993 *pMem = VK_NULL_HANDLE;
994 return VK_SUCCESS;
995 }
996
997 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
998 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
999 if (mem == NULL)
1000 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1001
1002 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
1003 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
1004 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
1005 domain = RADEON_DOMAIN_GTT;
1006 else
1007 domain = RADEON_DOMAIN_VRAM;
1008
1009 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
1010 flags |= RADEON_FLAG_NO_CPU_ACCESS;
1011 else
1012 flags |= RADEON_FLAG_CPU_ACCESS;
1013
1014 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
1015 flags |= RADEON_FLAG_GTT_WC;
1016
1017 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 32768,
1018 domain, flags);
1019
1020 if (!mem->bo) {
1021 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
1022 goto fail;
1023 }
1024 mem->type_index = pAllocateInfo->memoryTypeIndex;
1025
1026 *pMem = radv_device_memory_to_handle(mem);
1027
1028 return VK_SUCCESS;
1029
1030 fail:
1031 vk_free2(&device->alloc, pAllocator, mem);
1032
1033 return result;
1034 }
1035
1036 void radv_FreeMemory(
1037 VkDevice _device,
1038 VkDeviceMemory _mem,
1039 const VkAllocationCallbacks* pAllocator)
1040 {
1041 RADV_FROM_HANDLE(radv_device, device, _device);
1042 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
1043
1044 if (mem == NULL)
1045 return;
1046
1047 device->ws->buffer_destroy(mem->bo);
1048 mem->bo = NULL;
1049
1050 vk_free2(&device->alloc, pAllocator, mem);
1051 }
1052
1053 VkResult radv_MapMemory(
1054 VkDevice _device,
1055 VkDeviceMemory _memory,
1056 VkDeviceSize offset,
1057 VkDeviceSize size,
1058 VkMemoryMapFlags flags,
1059 void** ppData)
1060 {
1061 RADV_FROM_HANDLE(radv_device, device, _device);
1062 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1063
1064 if (mem == NULL) {
1065 *ppData = NULL;
1066 return VK_SUCCESS;
1067 }
1068
1069 *ppData = device->ws->buffer_map(mem->bo);
1070 if (*ppData) {
1071 *ppData += offset;
1072 return VK_SUCCESS;
1073 }
1074
1075 return VK_ERROR_MEMORY_MAP_FAILED;
1076 }
1077
1078 void radv_UnmapMemory(
1079 VkDevice _device,
1080 VkDeviceMemory _memory)
1081 {
1082 RADV_FROM_HANDLE(radv_device, device, _device);
1083 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1084
1085 if (mem == NULL)
1086 return;
1087
1088 device->ws->buffer_unmap(mem->bo);
1089 }
1090
1091 VkResult radv_FlushMappedMemoryRanges(
1092 VkDevice _device,
1093 uint32_t memoryRangeCount,
1094 const VkMappedMemoryRange* pMemoryRanges)
1095 {
1096 return VK_SUCCESS;
1097 }
1098
1099 VkResult radv_InvalidateMappedMemoryRanges(
1100 VkDevice _device,
1101 uint32_t memoryRangeCount,
1102 const VkMappedMemoryRange* pMemoryRanges)
1103 {
1104 return VK_SUCCESS;
1105 }
1106
1107 void radv_GetBufferMemoryRequirements(
1108 VkDevice device,
1109 VkBuffer _buffer,
1110 VkMemoryRequirements* pMemoryRequirements)
1111 {
1112 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1113
1114 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1115
1116 pMemoryRequirements->size = buffer->size;
1117 pMemoryRequirements->alignment = 16;
1118 }
1119
1120 void radv_GetImageMemoryRequirements(
1121 VkDevice device,
1122 VkImage _image,
1123 VkMemoryRequirements* pMemoryRequirements)
1124 {
1125 RADV_FROM_HANDLE(radv_image, image, _image);
1126
1127 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1128
1129 pMemoryRequirements->size = image->size;
1130 pMemoryRequirements->alignment = image->alignment;
1131 }
1132
1133 void radv_GetImageSparseMemoryRequirements(
1134 VkDevice device,
1135 VkImage image,
1136 uint32_t* pSparseMemoryRequirementCount,
1137 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
1138 {
1139 stub();
1140 }
1141
1142 void radv_GetDeviceMemoryCommitment(
1143 VkDevice device,
1144 VkDeviceMemory memory,
1145 VkDeviceSize* pCommittedMemoryInBytes)
1146 {
1147 *pCommittedMemoryInBytes = 0;
1148 }
1149
1150 VkResult radv_BindBufferMemory(
1151 VkDevice device,
1152 VkBuffer _buffer,
1153 VkDeviceMemory _memory,
1154 VkDeviceSize memoryOffset)
1155 {
1156 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1157 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1158
1159 if (mem) {
1160 buffer->bo = mem->bo;
1161 buffer->offset = memoryOffset;
1162 } else {
1163 buffer->bo = NULL;
1164 buffer->offset = 0;
1165 }
1166
1167 return VK_SUCCESS;
1168 }
1169
1170 VkResult radv_BindImageMemory(
1171 VkDevice device,
1172 VkImage _image,
1173 VkDeviceMemory _memory,
1174 VkDeviceSize memoryOffset)
1175 {
1176 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1177 RADV_FROM_HANDLE(radv_image, image, _image);
1178
1179 if (mem) {
1180 image->bo = mem->bo;
1181 image->offset = memoryOffset;
1182 } else {
1183 image->bo = NULL;
1184 image->offset = 0;
1185 }
1186
1187 return VK_SUCCESS;
1188 }
1189
1190 VkResult radv_QueueBindSparse(
1191 VkQueue queue,
1192 uint32_t bindInfoCount,
1193 const VkBindSparseInfo* pBindInfo,
1194 VkFence fence)
1195 {
1196 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER);
1197 }
1198
1199 VkResult radv_CreateFence(
1200 VkDevice _device,
1201 const VkFenceCreateInfo* pCreateInfo,
1202 const VkAllocationCallbacks* pAllocator,
1203 VkFence* pFence)
1204 {
1205 RADV_FROM_HANDLE(radv_device, device, _device);
1206 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
1207 sizeof(*fence), 8,
1208 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1209
1210 if (!fence)
1211 return VK_ERROR_OUT_OF_HOST_MEMORY;
1212
1213 memset(fence, 0, sizeof(*fence));
1214 fence->submitted = false;
1215 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
1216 fence->fence = device->ws->create_fence();
1217 if (!fence->fence) {
1218 vk_free2(&device->alloc, pAllocator, fence);
1219 return VK_ERROR_OUT_OF_HOST_MEMORY;
1220 }
1221
1222 *pFence = radv_fence_to_handle(fence);
1223
1224 return VK_SUCCESS;
1225 }
1226
1227 void radv_DestroyFence(
1228 VkDevice _device,
1229 VkFence _fence,
1230 const VkAllocationCallbacks* pAllocator)
1231 {
1232 RADV_FROM_HANDLE(radv_device, device, _device);
1233 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1234
1235 if (!fence)
1236 return;
1237 device->ws->destroy_fence(fence->fence);
1238 vk_free2(&device->alloc, pAllocator, fence);
1239 }
1240
1241 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
1242 {
1243 uint64_t current_time;
1244 struct timespec tv;
1245
1246 clock_gettime(CLOCK_MONOTONIC, &tv);
1247 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
1248
1249 timeout = MIN2(UINT64_MAX - current_time, timeout);
1250
1251 return current_time + timeout;
1252 }
1253
1254 VkResult radv_WaitForFences(
1255 VkDevice _device,
1256 uint32_t fenceCount,
1257 const VkFence* pFences,
1258 VkBool32 waitAll,
1259 uint64_t timeout)
1260 {
1261 RADV_FROM_HANDLE(radv_device, device, _device);
1262 timeout = radv_get_absolute_timeout(timeout);
1263
1264 if (!waitAll && fenceCount > 1) {
1265 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
1266 }
1267
1268 for (uint32_t i = 0; i < fenceCount; ++i) {
1269 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1270 bool expired = false;
1271
1272 if (fence->signalled)
1273 continue;
1274
1275 if (!fence->submitted)
1276 return VK_TIMEOUT;
1277
1278 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
1279 if (!expired)
1280 return VK_TIMEOUT;
1281
1282 fence->signalled = true;
1283 }
1284
1285 return VK_SUCCESS;
1286 }
1287
1288 VkResult radv_ResetFences(VkDevice device,
1289 uint32_t fenceCount,
1290 const VkFence *pFences)
1291 {
1292 for (unsigned i = 0; i < fenceCount; ++i) {
1293 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1294 fence->submitted = fence->signalled = false;
1295 }
1296
1297 return VK_SUCCESS;
1298 }
1299
1300 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
1301 {
1302 RADV_FROM_HANDLE(radv_device, device, _device);
1303 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1304
1305 if (fence->signalled)
1306 return VK_SUCCESS;
1307 if (!fence->submitted)
1308 return VK_NOT_READY;
1309
1310 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
1311 return VK_NOT_READY;
1312
1313 return VK_SUCCESS;
1314 }
1315
1316
1317 // Queue semaphore functions
1318
1319 VkResult radv_CreateSemaphore(
1320 VkDevice _device,
1321 const VkSemaphoreCreateInfo* pCreateInfo,
1322 const VkAllocationCallbacks* pAllocator,
1323 VkSemaphore* pSemaphore)
1324 {
1325 RADV_FROM_HANDLE(radv_device, device, _device);
1326 struct radeon_winsys_sem *sem;
1327
1328 sem = device->ws->create_sem(device->ws);
1329 if (!sem)
1330 return VK_ERROR_OUT_OF_HOST_MEMORY;
1331
1332 *pSemaphore = (VkSemaphore)sem;
1333 return VK_SUCCESS;
1334 }
1335
1336 void radv_DestroySemaphore(
1337 VkDevice _device,
1338 VkSemaphore _semaphore,
1339 const VkAllocationCallbacks* pAllocator)
1340 {
1341 RADV_FROM_HANDLE(radv_device, device, _device);
1342 struct radeon_winsys_sem *sem;
1343 if (!_semaphore)
1344 return;
1345
1346 sem = (struct radeon_winsys_sem *)_semaphore;
1347 device->ws->destroy_sem(sem);
1348 }
1349
1350 VkResult radv_CreateEvent(
1351 VkDevice _device,
1352 const VkEventCreateInfo* pCreateInfo,
1353 const VkAllocationCallbacks* pAllocator,
1354 VkEvent* pEvent)
1355 {
1356 RADV_FROM_HANDLE(radv_device, device, _device);
1357 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
1358 sizeof(*event), 8,
1359 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1360
1361 if (!event)
1362 return VK_ERROR_OUT_OF_HOST_MEMORY;
1363
1364 event->bo = device->ws->buffer_create(device->ws, 8, 8,
1365 RADEON_DOMAIN_GTT,
1366 RADEON_FLAG_CPU_ACCESS);
1367 if (!event->bo) {
1368 vk_free2(&device->alloc, pAllocator, event);
1369 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1370 }
1371
1372 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
1373
1374 *pEvent = radv_event_to_handle(event);
1375
1376 return VK_SUCCESS;
1377 }
1378
1379 void radv_DestroyEvent(
1380 VkDevice _device,
1381 VkEvent _event,
1382 const VkAllocationCallbacks* pAllocator)
1383 {
1384 RADV_FROM_HANDLE(radv_device, device, _device);
1385 RADV_FROM_HANDLE(radv_event, event, _event);
1386
1387 if (!event)
1388 return;
1389 device->ws->buffer_destroy(event->bo);
1390 vk_free2(&device->alloc, pAllocator, event);
1391 }
1392
1393 VkResult radv_GetEventStatus(
1394 VkDevice _device,
1395 VkEvent _event)
1396 {
1397 RADV_FROM_HANDLE(radv_event, event, _event);
1398
1399 if (*event->map == 1)
1400 return VK_EVENT_SET;
1401 return VK_EVENT_RESET;
1402 }
1403
1404 VkResult radv_SetEvent(
1405 VkDevice _device,
1406 VkEvent _event)
1407 {
1408 RADV_FROM_HANDLE(radv_event, event, _event);
1409 *event->map = 1;
1410
1411 return VK_SUCCESS;
1412 }
1413
1414 VkResult radv_ResetEvent(
1415 VkDevice _device,
1416 VkEvent _event)
1417 {
1418 RADV_FROM_HANDLE(radv_event, event, _event);
1419 *event->map = 0;
1420
1421 return VK_SUCCESS;
1422 }
1423
1424 VkResult radv_CreateBuffer(
1425 VkDevice _device,
1426 const VkBufferCreateInfo* pCreateInfo,
1427 const VkAllocationCallbacks* pAllocator,
1428 VkBuffer* pBuffer)
1429 {
1430 RADV_FROM_HANDLE(radv_device, device, _device);
1431 struct radv_buffer *buffer;
1432
1433 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
1434
1435 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
1436 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1437 if (buffer == NULL)
1438 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1439
1440 buffer->size = pCreateInfo->size;
1441 buffer->usage = pCreateInfo->usage;
1442 buffer->bo = NULL;
1443 buffer->offset = 0;
1444
1445 *pBuffer = radv_buffer_to_handle(buffer);
1446
1447 return VK_SUCCESS;
1448 }
1449
1450 void radv_DestroyBuffer(
1451 VkDevice _device,
1452 VkBuffer _buffer,
1453 const VkAllocationCallbacks* pAllocator)
1454 {
1455 RADV_FROM_HANDLE(radv_device, device, _device);
1456 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1457
1458 if (!buffer)
1459 return;
1460
1461 vk_free2(&device->alloc, pAllocator, buffer);
1462 }
1463
1464 static inline unsigned
1465 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
1466 {
1467 if (stencil)
1468 return image->surface.stencil_tiling_index[level];
1469 else
1470 return image->surface.tiling_index[level];
1471 }
1472
1473 static void
1474 radv_initialise_color_surface(struct radv_device *device,
1475 struct radv_color_buffer_info *cb,
1476 struct radv_image_view *iview)
1477 {
1478 const struct vk_format_description *desc;
1479 unsigned ntype, format, swap, endian;
1480 unsigned blend_clamp = 0, blend_bypass = 0;
1481 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
1482 uint64_t va;
1483 const struct radeon_surf *surf = &iview->image->surface;
1484 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
1485
1486 desc = vk_format_description(iview->vk_format);
1487
1488 memset(cb, 0, sizeof(*cb));
1489
1490 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1491 va += level_info->offset;
1492 cb->cb_color_base = va >> 8;
1493
1494 /* CMASK variables */
1495 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1496 va += iview->image->cmask.offset;
1497 cb->cb_color_cmask = va >> 8;
1498 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
1499
1500 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1501 va += iview->image->dcc_offset;
1502 cb->cb_dcc_base = va >> 8;
1503
1504 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
1505 S_028C6C_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1506
1507 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
1508 pitch_tile_max = level_info->nblk_x / 8 - 1;
1509 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
1510 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
1511
1512 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
1513 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
1514
1515 /* Intensity is implemented as Red, so treat it that way. */
1516 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
1517 S_028C74_TILE_MODE_INDEX(tile_mode_index);
1518
1519 if (iview->image->samples > 1) {
1520 unsigned log_samples = util_logbase2(iview->image->samples);
1521
1522 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1523 S_028C74_NUM_FRAGMENTS(log_samples);
1524 }
1525
1526 if (iview->image->fmask.size) {
1527 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
1528 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1529 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
1530 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
1531 cb->cb_color_fmask = va >> 8;
1532 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
1533 } else {
1534 /* This must be set for fast clear to work without FMASK. */
1535 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1536 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
1537 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1538 cb->cb_color_fmask = cb->cb_color_base;
1539 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
1540 }
1541
1542 ntype = radv_translate_color_numformat(iview->vk_format,
1543 desc,
1544 vk_format_get_first_non_void_channel(iview->vk_format));
1545 format = radv_translate_colorformat(iview->vk_format);
1546 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
1547 radv_finishme("Illegal color\n");
1548 swap = radv_translate_colorswap(iview->vk_format, FALSE);
1549 endian = radv_colorformat_endian_swap(format);
1550
1551 /* blend clamp should be set for all NORM/SRGB types */
1552 if (ntype == V_028C70_NUMBER_UNORM ||
1553 ntype == V_028C70_NUMBER_SNORM ||
1554 ntype == V_028C70_NUMBER_SRGB)
1555 blend_clamp = 1;
1556
1557 /* set blend bypass according to docs if SINT/UINT or
1558 8/24 COLOR variants */
1559 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1560 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1561 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1562 blend_clamp = 0;
1563 blend_bypass = 1;
1564 }
1565 #if 0
1566 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
1567 (format == V_028C70_COLOR_8 ||
1568 format == V_028C70_COLOR_8_8 ||
1569 format == V_028C70_COLOR_8_8_8_8))
1570 ->color_is_int8 = true;
1571 #endif
1572 cb->cb_color_info = S_028C70_FORMAT(format) |
1573 S_028C70_COMP_SWAP(swap) |
1574 S_028C70_BLEND_CLAMP(blend_clamp) |
1575 S_028C70_BLEND_BYPASS(blend_bypass) |
1576 S_028C70_SIMPLE_FLOAT(1) |
1577 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
1578 ntype != V_028C70_NUMBER_SNORM &&
1579 ntype != V_028C70_NUMBER_SRGB &&
1580 format != V_028C70_COLOR_8_24 &&
1581 format != V_028C70_COLOR_24_8) |
1582 S_028C70_NUMBER_TYPE(ntype) |
1583 S_028C70_ENDIAN(endian);
1584 if (iview->image->samples > 1)
1585 if (iview->image->fmask.size)
1586 cb->cb_color_info |= S_028C70_COMPRESSION(1);
1587
1588 if (iview->image->cmask.size && device->allow_fast_clears)
1589 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
1590
1591 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
1592 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
1593
1594 if (device->instance->physicalDevice.rad_info.chip_class >= VI) {
1595 unsigned max_uncompressed_block_size = 2;
1596 if (iview->image->samples > 1) {
1597 if (iview->image->surface.bpe == 1)
1598 max_uncompressed_block_size = 0;
1599 else if (iview->image->surface.bpe == 2)
1600 max_uncompressed_block_size = 1;
1601 }
1602
1603 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
1604 S_028C78_INDEPENDENT_64B_BLOCKS(1);
1605 }
1606
1607 /* This must be set for fast clear to work without FMASK. */
1608 if (!iview->image->fmask.size &&
1609 device->instance->physicalDevice.rad_info.chip_class == SI) {
1610 unsigned bankh = util_logbase2(iview->image->surface.bankh);
1611 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1612 }
1613 }
1614
1615 static void
1616 radv_initialise_ds_surface(struct radv_device *device,
1617 struct radv_ds_buffer_info *ds,
1618 struct radv_image_view *iview)
1619 {
1620 unsigned level = iview->base_mip;
1621 unsigned format;
1622 uint64_t va, s_offs, z_offs;
1623 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
1624 memset(ds, 0, sizeof(*ds));
1625 switch (iview->vk_format) {
1626 case VK_FORMAT_D24_UNORM_S8_UINT:
1627 case VK_FORMAT_X8_D24_UNORM_PACK32:
1628 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1629 ds->offset_scale = 2.0f;
1630 break;
1631 case VK_FORMAT_D16_UNORM:
1632 case VK_FORMAT_D16_UNORM_S8_UINT:
1633 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1634 ds->offset_scale = 4.0f;
1635 break;
1636 case VK_FORMAT_D32_SFLOAT:
1637 case VK_FORMAT_D32_SFLOAT_S8_UINT:
1638 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1639 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1640 ds->offset_scale = 1.0f;
1641 break;
1642 default:
1643 break;
1644 }
1645
1646 format = radv_translate_dbformat(iview->vk_format);
1647 if (format == V_028040_Z_INVALID) {
1648 fprintf(stderr, "Invalid DB format: %d, disabling DB.\n", iview->vk_format);
1649 }
1650
1651 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1652 s_offs = z_offs = va;
1653 z_offs += iview->image->surface.level[level].offset;
1654 s_offs += iview->image->surface.stencil_level[level].offset;
1655
1656 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
1657 S_028008_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1658 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1659 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
1660
1661 if (iview->image->samples > 1)
1662 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
1663
1664 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
1665 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
1666 else
1667 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1668
1669 if (device->instance->physicalDevice.rad_info.chip_class >= CIK) {
1670 struct radeon_info *info = &device->instance->physicalDevice.rad_info;
1671 unsigned tiling_index = iview->image->surface.tiling_index[level];
1672 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
1673 unsigned macro_index = iview->image->surface.macro_tile_index;
1674 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
1675 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
1676 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
1677
1678 ds->db_depth_info |=
1679 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
1680 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
1681 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
1682 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
1683 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
1684 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
1685 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
1686 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
1687 } else {
1688 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
1689 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1690 tile_mode_index = si_tile_mode_index(iview->image, level, true);
1691 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1692 }
1693
1694 if (iview->image->htile.size && !level) {
1695 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1696 S_028040_ALLOW_EXPCLEAR(1);
1697
1698 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
1699 /* Workaround: For a not yet understood reason, the
1700 * combination of MSAA, fast stencil clear and stencil
1701 * decompress messes with subsequent stencil buffer
1702 * uses. Problem was reproduced on Verde, Bonaire,
1703 * Tonga, and Carrizo.
1704 *
1705 * Disabling EXPCLEAR works around the problem.
1706 *
1707 * Check piglit's arb_texture_multisample-stencil-clear
1708 * test if you want to try changing this.
1709 */
1710 if (iview->image->samples <= 1)
1711 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
1712 } else
1713 /* Use all of the htile_buffer for depth if there's no stencil. */
1714 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1715
1716 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
1717 iview->image->htile.offset;
1718 ds->db_htile_data_base = va >> 8;
1719 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
1720 } else {
1721 ds->db_htile_data_base = 0;
1722 ds->db_htile_surface = 0;
1723 }
1724
1725 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
1726 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
1727
1728 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
1729 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
1730 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
1731 }
1732
1733 VkResult radv_CreateFramebuffer(
1734 VkDevice _device,
1735 const VkFramebufferCreateInfo* pCreateInfo,
1736 const VkAllocationCallbacks* pAllocator,
1737 VkFramebuffer* pFramebuffer)
1738 {
1739 RADV_FROM_HANDLE(radv_device, device, _device);
1740 struct radv_framebuffer *framebuffer;
1741
1742 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
1743
1744 size_t size = sizeof(*framebuffer) +
1745 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
1746 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
1747 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1748 if (framebuffer == NULL)
1749 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1750
1751 framebuffer->attachment_count = pCreateInfo->attachmentCount;
1752 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
1753 VkImageView _iview = pCreateInfo->pAttachments[i];
1754 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
1755 framebuffer->attachments[i].attachment = iview;
1756 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
1757 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
1758 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
1759 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
1760 }
1761 }
1762
1763 framebuffer->width = pCreateInfo->width;
1764 framebuffer->height = pCreateInfo->height;
1765 framebuffer->layers = pCreateInfo->layers;
1766
1767 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
1768 return VK_SUCCESS;
1769 }
1770
1771 void radv_DestroyFramebuffer(
1772 VkDevice _device,
1773 VkFramebuffer _fb,
1774 const VkAllocationCallbacks* pAllocator)
1775 {
1776 RADV_FROM_HANDLE(radv_device, device, _device);
1777 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
1778
1779 if (!fb)
1780 return;
1781 vk_free2(&device->alloc, pAllocator, fb);
1782 }
1783
1784 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
1785 {
1786 switch (address_mode) {
1787 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
1788 return V_008F30_SQ_TEX_WRAP;
1789 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
1790 return V_008F30_SQ_TEX_MIRROR;
1791 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
1792 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1793 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
1794 return V_008F30_SQ_TEX_CLAMP_BORDER;
1795 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
1796 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1797 default:
1798 unreachable("illegal tex wrap mode");
1799 break;
1800 }
1801 }
1802
1803 static unsigned
1804 radv_tex_compare(VkCompareOp op)
1805 {
1806 switch (op) {
1807 case VK_COMPARE_OP_NEVER:
1808 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1809 case VK_COMPARE_OP_LESS:
1810 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1811 case VK_COMPARE_OP_EQUAL:
1812 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1813 case VK_COMPARE_OP_LESS_OR_EQUAL:
1814 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1815 case VK_COMPARE_OP_GREATER:
1816 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1817 case VK_COMPARE_OP_NOT_EQUAL:
1818 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1819 case VK_COMPARE_OP_GREATER_OR_EQUAL:
1820 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1821 case VK_COMPARE_OP_ALWAYS:
1822 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1823 default:
1824 unreachable("illegal compare mode");
1825 break;
1826 }
1827 }
1828
1829 static unsigned
1830 radv_tex_filter(VkFilter filter, unsigned max_ansio)
1831 {
1832 switch (filter) {
1833 case VK_FILTER_NEAREST:
1834 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
1835 V_008F38_SQ_TEX_XY_FILTER_POINT);
1836 case VK_FILTER_LINEAR:
1837 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
1838 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
1839 case VK_FILTER_CUBIC_IMG:
1840 default:
1841 fprintf(stderr, "illegal texture filter");
1842 return 0;
1843 }
1844 }
1845
1846 static unsigned
1847 radv_tex_mipfilter(VkSamplerMipmapMode mode)
1848 {
1849 switch (mode) {
1850 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
1851 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1852 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
1853 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1854 default:
1855 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1856 }
1857 }
1858
1859 static unsigned
1860 radv_tex_bordercolor(VkBorderColor bcolor)
1861 {
1862 switch (bcolor) {
1863 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
1864 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
1865 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
1866 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
1867 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
1868 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
1869 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
1870 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
1871 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
1872 default:
1873 break;
1874 }
1875 return 0;
1876 }
1877
1878 static unsigned
1879 radv_tex_aniso_filter(unsigned filter)
1880 {
1881 if (filter < 2)
1882 return 0;
1883 if (filter < 4)
1884 return 1;
1885 if (filter < 8)
1886 return 2;
1887 if (filter < 16)
1888 return 3;
1889 return 4;
1890 }
1891
1892 static void
1893 radv_init_sampler(struct radv_device *device,
1894 struct radv_sampler *sampler,
1895 const VkSamplerCreateInfo *pCreateInfo)
1896 {
1897 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
1898 (uint32_t) pCreateInfo->maxAnisotropy : 0;
1899 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
1900 bool is_vi = (device->instance->physicalDevice.rad_info.chip_class >= VI);
1901
1902 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
1903 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
1904 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
1905 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
1906 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
1907 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
1908 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
1909 S_008F30_ANISO_BIAS(max_aniso_ratio) |
1910 S_008F30_DISABLE_CUBE_WRAP(0) |
1911 S_008F30_COMPAT_MODE(is_vi));
1912 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
1913 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
1914 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
1915 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
1916 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
1917 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
1918 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
1919 S_008F38_MIP_POINT_PRECLAMP(1) |
1920 S_008F38_DISABLE_LSB_CEIL(1) |
1921 S_008F38_FILTER_PREC_FIX(1) |
1922 S_008F38_ANISO_OVERRIDE(is_vi));
1923 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
1924 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
1925 }
1926
1927 VkResult radv_CreateSampler(
1928 VkDevice _device,
1929 const VkSamplerCreateInfo* pCreateInfo,
1930 const VkAllocationCallbacks* pAllocator,
1931 VkSampler* pSampler)
1932 {
1933 RADV_FROM_HANDLE(radv_device, device, _device);
1934 struct radv_sampler *sampler;
1935
1936 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
1937
1938 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
1939 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1940 if (!sampler)
1941 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1942
1943 radv_init_sampler(device, sampler, pCreateInfo);
1944 *pSampler = radv_sampler_to_handle(sampler);
1945
1946 return VK_SUCCESS;
1947 }
1948
1949 void radv_DestroySampler(
1950 VkDevice _device,
1951 VkSampler _sampler,
1952 const VkAllocationCallbacks* pAllocator)
1953 {
1954 RADV_FROM_HANDLE(radv_device, device, _device);
1955 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
1956
1957 if (!sampler)
1958 return;
1959 vk_free2(&device->alloc, pAllocator, sampler);
1960 }