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radv: add semaphore support
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <dlfcn.h>
29 #include <stdbool.h>
30 #include <string.h>
31 #include <unistd.h>
32 #include <fcntl.h>
33 #include <sys/stat.h>
34 #include "radv_private.h"
35 #include "util/strtod.h"
36
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "util/debug.h"
46 struct radv_dispatch_table dtable;
47
48 static int
49 radv_get_function_timestamp(void *ptr, uint32_t* timestamp)
50 {
51 Dl_info info;
52 struct stat st;
53 if (!dladdr(ptr, &info) || !info.dli_fname) {
54 return -1;
55 }
56 if (stat(info.dli_fname, &st)) {
57 return -1;
58 }
59 *timestamp = st.st_mtim.tv_sec;
60 return 0;
61 }
62
63 static int
64 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
65 {
66 uint32_t mesa_timestamp, llvm_timestamp;
67 uint16_t f = family;
68 memset(uuid, 0, VK_UUID_SIZE);
69 if (radv_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
70 radv_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
71 return -1;
72
73 memcpy(uuid, &mesa_timestamp, 4);
74 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
75 memcpy((char*)uuid + 8, &f, 2);
76 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
77 return 0;
78 }
79
80 static VkResult
81 radv_physical_device_init(struct radv_physical_device *device,
82 struct radv_instance *instance,
83 const char *path)
84 {
85 VkResult result;
86 drmVersionPtr version;
87 int fd;
88
89 fd = open(path, O_RDWR | O_CLOEXEC);
90 if (fd < 0)
91 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
92 "failed to open %s: %m", path);
93
94 version = drmGetVersion(fd);
95 if (!version) {
96 close(fd);
97 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
98 "failed to get version %s: %m", path);
99 }
100
101 if (strcmp(version->name, "amdgpu")) {
102 drmFreeVersion(version);
103 close(fd);
104 return VK_ERROR_INCOMPATIBLE_DRIVER;
105 }
106 drmFreeVersion(version);
107
108 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
109 device->instance = instance;
110 assert(strlen(path) < ARRAY_SIZE(device->path));
111 strncpy(device->path, path, ARRAY_SIZE(device->path));
112
113 device->ws = radv_amdgpu_winsys_create(fd);
114 if (!device->ws) {
115 result = VK_ERROR_INCOMPATIBLE_DRIVER;
116 goto fail;
117 }
118 device->ws->query_info(device->ws, &device->rad_info);
119 result = radv_init_wsi(device);
120 if (result != VK_SUCCESS) {
121 device->ws->destroy(device->ws);
122 goto fail;
123 }
124
125 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
126 radv_finish_wsi(device);
127 device->ws->destroy(device->ws);
128 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
129 "cannot generate UUID");
130 goto fail;
131 }
132
133 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
134 device->name = device->rad_info.name;
135 close(fd);
136 return VK_SUCCESS;
137
138 fail:
139 close(fd);
140 return result;
141 }
142
143 static void
144 radv_physical_device_finish(struct radv_physical_device *device)
145 {
146 radv_finish_wsi(device);
147 device->ws->destroy(device->ws);
148 }
149
150 static const VkExtensionProperties global_extensions[] = {
151 {
152 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
153 .specVersion = 25,
154 },
155 #ifdef VK_USE_PLATFORM_XCB_KHR
156 {
157 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
158 .specVersion = 6,
159 },
160 #endif
161 #ifdef VK_USE_PLATFORM_XLIB_KHR
162 {
163 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
164 .specVersion = 6,
165 },
166 #endif
167 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
168 {
169 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
170 .specVersion = 5,
171 },
172 #endif
173 };
174
175 static const VkExtensionProperties device_extensions[] = {
176 {
177 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
178 .specVersion = 1,
179 },
180 {
181 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
182 .specVersion = 68,
183 },
184 {
185 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
186 .specVersion = 1,
187 },
188 {
189 .extensionName = VK_AMD_NEGATIVE_VIEWPORT_HEIGHT_EXTENSION_NAME,
190 .specVersion = 1,
191 },
192 };
193
194 static void *
195 default_alloc_func(void *pUserData, size_t size, size_t align,
196 VkSystemAllocationScope allocationScope)
197 {
198 return malloc(size);
199 }
200
201 static void *
202 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
203 size_t align, VkSystemAllocationScope allocationScope)
204 {
205 return realloc(pOriginal, size);
206 }
207
208 static void
209 default_free_func(void *pUserData, void *pMemory)
210 {
211 free(pMemory);
212 }
213
214 static const VkAllocationCallbacks default_alloc = {
215 .pUserData = NULL,
216 .pfnAllocation = default_alloc_func,
217 .pfnReallocation = default_realloc_func,
218 .pfnFree = default_free_func,
219 };
220
221 VkResult radv_CreateInstance(
222 const VkInstanceCreateInfo* pCreateInfo,
223 const VkAllocationCallbacks* pAllocator,
224 VkInstance* pInstance)
225 {
226 struct radv_instance *instance;
227
228 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
229
230 uint32_t client_version;
231 if (pCreateInfo->pApplicationInfo &&
232 pCreateInfo->pApplicationInfo->apiVersion != 0) {
233 client_version = pCreateInfo->pApplicationInfo->apiVersion;
234 } else {
235 client_version = VK_MAKE_VERSION(1, 0, 0);
236 }
237
238 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
239 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
240 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
241 "Client requested version %d.%d.%d",
242 VK_VERSION_MAJOR(client_version),
243 VK_VERSION_MINOR(client_version),
244 VK_VERSION_PATCH(client_version));
245 }
246
247 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
248 bool found = false;
249 for (uint32_t j = 0; j < ARRAY_SIZE(global_extensions); j++) {
250 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
251 global_extensions[j].extensionName) == 0) {
252 found = true;
253 break;
254 }
255 }
256 if (!found)
257 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
258 }
259
260 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
262 if (!instance)
263 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
264
265 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266
267 if (pAllocator)
268 instance->alloc = *pAllocator;
269 else
270 instance->alloc = default_alloc;
271
272 instance->apiVersion = client_version;
273 instance->physicalDeviceCount = -1;
274
275 _mesa_locale_init();
276
277 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
278
279 *pInstance = radv_instance_to_handle(instance);
280
281 return VK_SUCCESS;
282 }
283
284 void radv_DestroyInstance(
285 VkInstance _instance,
286 const VkAllocationCallbacks* pAllocator)
287 {
288 RADV_FROM_HANDLE(radv_instance, instance, _instance);
289
290 if (instance->physicalDeviceCount > 0) {
291 /* We support at most one physical device. */
292 assert(instance->physicalDeviceCount == 1);
293 radv_physical_device_finish(&instance->physicalDevice);
294 }
295
296 VG(VALGRIND_DESTROY_MEMPOOL(instance));
297
298 _mesa_locale_fini();
299
300 vk_free(&instance->alloc, instance);
301 }
302
303 VkResult radv_EnumeratePhysicalDevices(
304 VkInstance _instance,
305 uint32_t* pPhysicalDeviceCount,
306 VkPhysicalDevice* pPhysicalDevices)
307 {
308 RADV_FROM_HANDLE(radv_instance, instance, _instance);
309 VkResult result;
310
311 if (instance->physicalDeviceCount < 0) {
312 char path[20];
313 for (unsigned i = 0; i < 8; i++) {
314 snprintf(path, sizeof(path), "/dev/dri/renderD%d", 128 + i);
315 result = radv_physical_device_init(&instance->physicalDevice,
316 instance, path);
317 if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
318 break;
319 }
320
321 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
322 instance->physicalDeviceCount = 0;
323 } else if (result == VK_SUCCESS) {
324 instance->physicalDeviceCount = 1;
325 } else {
326 return result;
327 }
328 }
329
330 /* pPhysicalDeviceCount is an out parameter if pPhysicalDevices is NULL;
331 * otherwise it's an inout parameter.
332 *
333 * The Vulkan spec (git aaed022) says:
334 *
335 * pPhysicalDeviceCount is a pointer to an unsigned integer variable
336 * that is initialized with the number of devices the application is
337 * prepared to receive handles to. pname:pPhysicalDevices is pointer to
338 * an array of at least this many VkPhysicalDevice handles [...].
339 *
340 * Upon success, if pPhysicalDevices is NULL, vkEnumeratePhysicalDevices
341 * overwrites the contents of the variable pointed to by
342 * pPhysicalDeviceCount with the number of physical devices in in the
343 * instance; otherwise, vkEnumeratePhysicalDevices overwrites
344 * pPhysicalDeviceCount with the number of physical handles written to
345 * pPhysicalDevices.
346 */
347 if (!pPhysicalDevices) {
348 *pPhysicalDeviceCount = instance->physicalDeviceCount;
349 } else if (*pPhysicalDeviceCount >= 1) {
350 pPhysicalDevices[0] = radv_physical_device_to_handle(&instance->physicalDevice);
351 *pPhysicalDeviceCount = 1;
352 } else if (*pPhysicalDeviceCount < instance->physicalDeviceCount) {
353 return VK_INCOMPLETE;
354 } else {
355 *pPhysicalDeviceCount = 0;
356 }
357
358 return VK_SUCCESS;
359 }
360
361 void radv_GetPhysicalDeviceFeatures(
362 VkPhysicalDevice physicalDevice,
363 VkPhysicalDeviceFeatures* pFeatures)
364 {
365 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
366
367 memset(pFeatures, 0, sizeof(*pFeatures));
368
369 *pFeatures = (VkPhysicalDeviceFeatures) {
370 .robustBufferAccess = true,
371 .fullDrawIndexUint32 = true,
372 .imageCubeArray = true,
373 .independentBlend = true,
374 .geometryShader = false,
375 .tessellationShader = false,
376 .sampleRateShading = false,
377 .dualSrcBlend = true,
378 .logicOp = true,
379 .multiDrawIndirect = true,
380 .drawIndirectFirstInstance = true,
381 .depthClamp = true,
382 .depthBiasClamp = true,
383 .fillModeNonSolid = true,
384 .depthBounds = true,
385 .wideLines = true,
386 .largePoints = true,
387 .alphaToOne = true,
388 .multiViewport = false,
389 .samplerAnisotropy = true,
390 .textureCompressionETC2 = false,
391 .textureCompressionASTC_LDR = false,
392 .textureCompressionBC = true,
393 .occlusionQueryPrecise = true,
394 .pipelineStatisticsQuery = false,
395 .vertexPipelineStoresAndAtomics = true,
396 .fragmentStoresAndAtomics = true,
397 .shaderTessellationAndGeometryPointSize = true,
398 .shaderImageGatherExtended = false,
399 .shaderStorageImageExtendedFormats = false,
400 .shaderStorageImageMultisample = false,
401 .shaderUniformBufferArrayDynamicIndexing = true,
402 .shaderSampledImageArrayDynamicIndexing = true,
403 .shaderStorageBufferArrayDynamicIndexing = true,
404 .shaderStorageImageArrayDynamicIndexing = true,
405 .shaderStorageImageReadWithoutFormat = false,
406 .shaderStorageImageWriteWithoutFormat = true,
407 .shaderClipDistance = true,
408 .shaderCullDistance = true,
409 .shaderFloat64 = false,
410 .shaderInt64 = false,
411 .shaderInt16 = false,
412 .alphaToOne = true,
413 .variableMultisampleRate = false,
414 .inheritedQueries = false,
415 };
416 }
417
418 void radv_GetPhysicalDeviceProperties(
419 VkPhysicalDevice physicalDevice,
420 VkPhysicalDeviceProperties* pProperties)
421 {
422 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
423 VkSampleCountFlags sample_counts = 0xf;
424 VkPhysicalDeviceLimits limits = {
425 .maxImageDimension1D = (1 << 14),
426 .maxImageDimension2D = (1 << 14),
427 .maxImageDimension3D = (1 << 11),
428 .maxImageDimensionCube = (1 << 14),
429 .maxImageArrayLayers = (1 << 11),
430 .maxTexelBufferElements = 128 * 1024 * 1024,
431 .maxUniformBufferRange = UINT32_MAX,
432 .maxStorageBufferRange = UINT32_MAX,
433 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
434 .maxMemoryAllocationCount = UINT32_MAX,
435 .maxSamplerAllocationCount = 64 * 1024,
436 .bufferImageGranularity = 64, /* A cache line */
437 .sparseAddressSpaceSize = 0,
438 .maxBoundDescriptorSets = MAX_SETS,
439 .maxPerStageDescriptorSamplers = 64,
440 .maxPerStageDescriptorUniformBuffers = 64,
441 .maxPerStageDescriptorStorageBuffers = 64,
442 .maxPerStageDescriptorSampledImages = 64,
443 .maxPerStageDescriptorStorageImages = 64,
444 .maxPerStageDescriptorInputAttachments = 64,
445 .maxPerStageResources = 128,
446 .maxDescriptorSetSamplers = 256,
447 .maxDescriptorSetUniformBuffers = 256,
448 .maxDescriptorSetUniformBuffersDynamic = 256,
449 .maxDescriptorSetStorageBuffers = 256,
450 .maxDescriptorSetStorageBuffersDynamic = 256,
451 .maxDescriptorSetSampledImages = 256,
452 .maxDescriptorSetStorageImages = 256,
453 .maxDescriptorSetInputAttachments = 256,
454 .maxVertexInputAttributes = 32,
455 .maxVertexInputBindings = 32,
456 .maxVertexInputAttributeOffset = 2047,
457 .maxVertexInputBindingStride = 2048,
458 .maxVertexOutputComponents = 128,
459 .maxTessellationGenerationLevel = 0,
460 .maxTessellationPatchSize = 0,
461 .maxTessellationControlPerVertexInputComponents = 0,
462 .maxTessellationControlPerVertexOutputComponents = 0,
463 .maxTessellationControlPerPatchOutputComponents = 0,
464 .maxTessellationControlTotalOutputComponents = 0,
465 .maxTessellationEvaluationInputComponents = 0,
466 .maxTessellationEvaluationOutputComponents = 0,
467 .maxGeometryShaderInvocations = 32,
468 .maxGeometryInputComponents = 64,
469 .maxGeometryOutputComponents = 128,
470 .maxGeometryOutputVertices = 256,
471 .maxGeometryTotalOutputComponents = 1024,
472 .maxFragmentInputComponents = 128,
473 .maxFragmentOutputAttachments = 8,
474 .maxFragmentDualSrcAttachments = 1,
475 .maxFragmentCombinedOutputResources = 8,
476 .maxComputeSharedMemorySize = 32768,
477 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
478 .maxComputeWorkGroupInvocations = 16 * 1024,
479 .maxComputeWorkGroupSize = {
480 16 * 1024/*devinfo->max_cs_threads*/,
481 16 * 1024,
482 16 * 1024
483 },
484 .subPixelPrecisionBits = 4 /* FIXME */,
485 .subTexelPrecisionBits = 4 /* FIXME */,
486 .mipmapPrecisionBits = 4 /* FIXME */,
487 .maxDrawIndexedIndexValue = UINT32_MAX,
488 .maxDrawIndirectCount = UINT32_MAX,
489 .maxSamplerLodBias = 16,
490 .maxSamplerAnisotropy = 16,
491 .maxViewports = MAX_VIEWPORTS,
492 .maxViewportDimensions = { (1 << 14), (1 << 14) },
493 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
494 .viewportSubPixelBits = 13, /* We take a float? */
495 .minMemoryMapAlignment = 4096, /* A page */
496 .minTexelBufferOffsetAlignment = 1,
497 .minUniformBufferOffsetAlignment = 4,
498 .minStorageBufferOffsetAlignment = 4,
499 .minTexelOffset = -8,
500 .maxTexelOffset = 7,
501 .minTexelGatherOffset = -8,
502 .maxTexelGatherOffset = 7,
503 .minInterpolationOffset = 0, /* FIXME */
504 .maxInterpolationOffset = 0, /* FIXME */
505 .subPixelInterpolationOffsetBits = 0, /* FIXME */
506 .maxFramebufferWidth = (1 << 14),
507 .maxFramebufferHeight = (1 << 14),
508 .maxFramebufferLayers = (1 << 10),
509 .framebufferColorSampleCounts = sample_counts,
510 .framebufferDepthSampleCounts = sample_counts,
511 .framebufferStencilSampleCounts = sample_counts,
512 .framebufferNoAttachmentsSampleCounts = sample_counts,
513 .maxColorAttachments = MAX_RTS,
514 .sampledImageColorSampleCounts = sample_counts,
515 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
516 .sampledImageDepthSampleCounts = sample_counts,
517 .sampledImageStencilSampleCounts = sample_counts,
518 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
519 .maxSampleMaskWords = 1,
520 .timestampComputeAndGraphics = false,
521 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
522 .maxClipDistances = 8,
523 .maxCullDistances = 8,
524 .maxCombinedClipAndCullDistances = 8,
525 .discreteQueuePriorities = 1,
526 .pointSizeRange = { 0.125, 255.875 },
527 .lineWidthRange = { 0.0, 7.9921875 },
528 .pointSizeGranularity = (1.0 / 8.0),
529 .lineWidthGranularity = (1.0 / 128.0),
530 .strictLines = false, /* FINISHME */
531 .standardSampleLocations = true,
532 .optimalBufferCopyOffsetAlignment = 128,
533 .optimalBufferCopyRowPitchAlignment = 128,
534 .nonCoherentAtomSize = 64,
535 };
536
537 *pProperties = (VkPhysicalDeviceProperties) {
538 .apiVersion = VK_MAKE_VERSION(1, 0, 5),
539 .driverVersion = 1,
540 .vendorID = 0x1002,
541 .deviceID = pdevice->rad_info.pci_id,
542 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
543 .limits = limits,
544 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
545 };
546
547 strcpy(pProperties->deviceName, pdevice->name);
548 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
549 }
550
551 void radv_GetPhysicalDeviceQueueFamilyProperties(
552 VkPhysicalDevice physicalDevice,
553 uint32_t* pCount,
554 VkQueueFamilyProperties* pQueueFamilyProperties)
555 {
556 if (pQueueFamilyProperties == NULL) {
557 *pCount = 1;
558 return;
559 }
560 assert(*pCount >= 1);
561
562 *pQueueFamilyProperties = (VkQueueFamilyProperties) {
563 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
564 VK_QUEUE_COMPUTE_BIT |
565 VK_QUEUE_TRANSFER_BIT,
566 .queueCount = 1,
567 .timestampValidBits = 64,
568 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
569 };
570 }
571
572 void radv_GetPhysicalDeviceMemoryProperties(
573 VkPhysicalDevice physicalDevice,
574 VkPhysicalDeviceMemoryProperties* pMemoryProperties)
575 {
576 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
577
578 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
579
580 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
581 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
582 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
583 .heapIndex = RADV_MEM_HEAP_VRAM,
584 };
585 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
586 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
587 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
588 .heapIndex = RADV_MEM_HEAP_GTT,
589 };
590 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
591 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
592 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
593 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
594 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
595 };
596 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
597 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
598 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
599 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
600 .heapIndex = RADV_MEM_HEAP_GTT,
601 };
602
603 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
604
605 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
606 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
607 .size = physical_device->rad_info.vram_size -
608 physical_device->rad_info.visible_vram_size,
609 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
610 };
611 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
612 .size = physical_device->rad_info.visible_vram_size,
613 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
614 };
615 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
616 .size = physical_device->rad_info.gart_size,
617 .flags = 0,
618 };
619 }
620
621 static void
622 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
623 int queue_family_index, int idx)
624 {
625 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
626 queue->device = device;
627 queue->queue_family_index = queue_family_index;
628 queue->queue_idx = idx;
629 }
630
631 static void
632 radv_queue_finish(struct radv_queue *queue)
633 {
634 }
635
636 VkResult radv_CreateDevice(
637 VkPhysicalDevice physicalDevice,
638 const VkDeviceCreateInfo* pCreateInfo,
639 const VkAllocationCallbacks* pAllocator,
640 VkDevice* pDevice)
641 {
642 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
643 VkResult result;
644 struct radv_device *device;
645
646 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
647 bool found = false;
648 for (uint32_t j = 0; j < ARRAY_SIZE(device_extensions); j++) {
649 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
650 device_extensions[j].extensionName) == 0) {
651 found = true;
652 break;
653 }
654 }
655 if (!found)
656 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
657 }
658
659 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
660 sizeof(*device), 8,
661 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
662 if (!device)
663 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
664
665 memset(device, 0, sizeof(*device));
666
667 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
668 device->instance = physical_device->instance;
669 device->shader_stats_dump = false;
670
671 device->ws = physical_device->ws;
672 if (pAllocator)
673 device->alloc = *pAllocator;
674 else
675 device->alloc = physical_device->instance->alloc;
676
677 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
678 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
679 uint32_t qfi = queue_create->queueFamilyIndex;
680
681 device->queues[qfi] = vk_alloc(&device->alloc,
682 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
683 if (!device->queues[qfi]) {
684 result = VK_ERROR_OUT_OF_HOST_MEMORY;
685 goto fail;
686 }
687
688 device->queue_count[qfi] = queue_create->queueCount;
689
690 for (unsigned q = 0; q < queue_create->queueCount; q++)
691 radv_queue_init(device, &device->queues[qfi][q], qfi, q);
692 }
693
694 device->hw_ctx = device->ws->ctx_create(device->ws);
695 if (!device->hw_ctx) {
696 result = VK_ERROR_OUT_OF_HOST_MEMORY;
697 goto fail;
698 }
699
700 result = radv_device_init_meta(device);
701 if (result != VK_SUCCESS) {
702 device->ws->ctx_destroy(device->hw_ctx);
703 goto fail;
704 }
705 device->allow_fast_clears = env_var_as_boolean("RADV_FAST_CLEARS", false);
706 device->allow_dcc = !env_var_as_boolean("RADV_DCC_DISABLE", false);
707 device->shader_stats_dump = env_var_as_boolean("RADV_SHADER_STATS", false);
708
709 if (device->allow_fast_clears && device->allow_dcc)
710 radv_finishme("DCC fast clears have not been tested\n");
711
712 radv_device_init_msaa(device);
713 device->empty_cs = device->ws->cs_create(device->ws, RING_GFX);
714 radeon_emit(device->empty_cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
715 radeon_emit(device->empty_cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
716 radeon_emit(device->empty_cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
717 device->ws->cs_finalize(device->empty_cs);
718 *pDevice = radv_device_to_handle(device);
719 return VK_SUCCESS;
720
721 fail:
722 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
723 for (unsigned q = 0; q < device->queue_count[i]; q++)
724 radv_queue_finish(&device->queues[i][q]);
725 if (device->queue_count[i])
726 vk_free(&device->alloc, device->queues[i]);
727 }
728 vk_free(&device->alloc, device);
729 return result;
730 }
731
732 void radv_DestroyDevice(
733 VkDevice _device,
734 const VkAllocationCallbacks* pAllocator)
735 {
736 RADV_FROM_HANDLE(radv_device, device, _device);
737
738 device->ws->ctx_destroy(device->hw_ctx);
739 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
740 for (unsigned q = 0; q < device->queue_count[i]; q++)
741 radv_queue_finish(&device->queues[i][q]);
742 if (device->queue_count[i])
743 vk_free(&device->alloc, device->queues[i]);
744 }
745 radv_device_finish_meta(device);
746
747 vk_free(&device->alloc, device);
748 }
749
750 VkResult radv_EnumerateInstanceExtensionProperties(
751 const char* pLayerName,
752 uint32_t* pPropertyCount,
753 VkExtensionProperties* pProperties)
754 {
755 if (pProperties == NULL) {
756 *pPropertyCount = ARRAY_SIZE(global_extensions);
757 return VK_SUCCESS;
758 }
759
760 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(global_extensions));
761 typed_memcpy(pProperties, global_extensions, *pPropertyCount);
762
763 if (*pPropertyCount < ARRAY_SIZE(global_extensions))
764 return VK_INCOMPLETE;
765
766 return VK_SUCCESS;
767 }
768
769 VkResult radv_EnumerateDeviceExtensionProperties(
770 VkPhysicalDevice physicalDevice,
771 const char* pLayerName,
772 uint32_t* pPropertyCount,
773 VkExtensionProperties* pProperties)
774 {
775 if (pProperties == NULL) {
776 *pPropertyCount = ARRAY_SIZE(device_extensions);
777 return VK_SUCCESS;
778 }
779
780 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(device_extensions));
781 typed_memcpy(pProperties, device_extensions, *pPropertyCount);
782
783 if (*pPropertyCount < ARRAY_SIZE(device_extensions))
784 return VK_INCOMPLETE;
785
786 return VK_SUCCESS;
787 }
788
789 VkResult radv_EnumerateInstanceLayerProperties(
790 uint32_t* pPropertyCount,
791 VkLayerProperties* pProperties)
792 {
793 if (pProperties == NULL) {
794 *pPropertyCount = 0;
795 return VK_SUCCESS;
796 }
797
798 /* None supported at this time */
799 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
800 }
801
802 VkResult radv_EnumerateDeviceLayerProperties(
803 VkPhysicalDevice physicalDevice,
804 uint32_t* pPropertyCount,
805 VkLayerProperties* pProperties)
806 {
807 if (pProperties == NULL) {
808 *pPropertyCount = 0;
809 return VK_SUCCESS;
810 }
811
812 /* None supported at this time */
813 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
814 }
815
816 void radv_GetDeviceQueue(
817 VkDevice _device,
818 uint32_t queueFamilyIndex,
819 uint32_t queueIndex,
820 VkQueue* pQueue)
821 {
822 RADV_FROM_HANDLE(radv_device, device, _device);
823
824 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
825 }
826
827 VkResult radv_QueueSubmit(
828 VkQueue _queue,
829 uint32_t submitCount,
830 const VkSubmitInfo* pSubmits,
831 VkFence _fence)
832 {
833 RADV_FROM_HANDLE(radv_queue, queue, _queue);
834 RADV_FROM_HANDLE(radv_fence, fence, _fence);
835 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
836 struct radeon_winsys_ctx *ctx = queue->device->hw_ctx;
837 int ret;
838
839 for (uint32_t i = 0; i < submitCount; i++) {
840 struct radeon_winsys_cs **cs_array;
841 bool can_patch = true;
842
843 if (!pSubmits[i].commandBufferCount)
844 continue;
845
846 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
847 pSubmits[i].commandBufferCount);
848
849 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
850 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
851 pSubmits[i].pCommandBuffers[j]);
852 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
853
854 cs_array[j] = cmd_buffer->cs;
855 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
856 can_patch = false;
857 }
858 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array,
859 pSubmits[i].commandBufferCount,
860 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
861 pSubmits[i].waitSemaphoreCount,
862 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
863 pSubmits[i].signalSemaphoreCount,
864 can_patch, base_fence);
865 if (ret)
866 radv_loge("failed to submit CS %d\n", i);
867 free(cs_array);
868 }
869
870 if (fence) {
871 if (!submitCount)
872 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, &queue->device->empty_cs,
873 1, NULL, 0, NULL, 0, false, base_fence);
874
875 fence->submitted = true;
876 }
877
878 return VK_SUCCESS;
879 }
880
881 VkResult radv_QueueWaitIdle(
882 VkQueue _queue)
883 {
884 RADV_FROM_HANDLE(radv_queue, queue, _queue);
885
886 queue->device->ws->ctx_wait_idle(queue->device->hw_ctx,
887 radv_queue_family_to_ring(queue->queue_family_index),
888 queue->queue_idx);
889 return VK_SUCCESS;
890 }
891
892 VkResult radv_DeviceWaitIdle(
893 VkDevice _device)
894 {
895 RADV_FROM_HANDLE(radv_device, device, _device);
896
897 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
898 for (unsigned q = 0; q < device->queue_count[i]; q++) {
899 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
900 }
901 }
902 return VK_SUCCESS;
903 }
904
905 PFN_vkVoidFunction radv_GetInstanceProcAddr(
906 VkInstance instance,
907 const char* pName)
908 {
909 return radv_lookup_entrypoint(pName);
910 }
911
912 /* The loader wants us to expose a second GetInstanceProcAddr function
913 * to work around certain LD_PRELOAD issues seen in apps.
914 */
915 PUBLIC
916 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
917 VkInstance instance,
918 const char* pName);
919
920 PUBLIC
921 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
922 VkInstance instance,
923 const char* pName)
924 {
925 return radv_GetInstanceProcAddr(instance, pName);
926 }
927
928 PFN_vkVoidFunction radv_GetDeviceProcAddr(
929 VkDevice device,
930 const char* pName)
931 {
932 return radv_lookup_entrypoint(pName);
933 }
934
935 VkResult radv_AllocateMemory(
936 VkDevice _device,
937 const VkMemoryAllocateInfo* pAllocateInfo,
938 const VkAllocationCallbacks* pAllocator,
939 VkDeviceMemory* pMem)
940 {
941 RADV_FROM_HANDLE(radv_device, device, _device);
942 struct radv_device_memory *mem;
943 VkResult result;
944 enum radeon_bo_domain domain;
945 uint32_t flags = 0;
946 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
947
948 if (pAllocateInfo->allocationSize == 0) {
949 /* Apparently, this is allowed */
950 *pMem = VK_NULL_HANDLE;
951 return VK_SUCCESS;
952 }
953
954 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
955 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
956 if (mem == NULL)
957 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
958
959 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
960 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
961 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
962 domain = RADEON_DOMAIN_GTT;
963 else
964 domain = RADEON_DOMAIN_VRAM;
965
966 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
967 flags |= RADEON_FLAG_NO_CPU_ACCESS;
968 else
969 flags |= RADEON_FLAG_CPU_ACCESS;
970
971 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
972 flags |= RADEON_FLAG_GTT_WC;
973
974 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 32768,
975 domain, flags);
976
977 if (!mem->bo) {
978 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
979 goto fail;
980 }
981 mem->type_index = pAllocateInfo->memoryTypeIndex;
982
983 *pMem = radv_device_memory_to_handle(mem);
984
985 return VK_SUCCESS;
986
987 fail:
988 vk_free2(&device->alloc, pAllocator, mem);
989
990 return result;
991 }
992
993 void radv_FreeMemory(
994 VkDevice _device,
995 VkDeviceMemory _mem,
996 const VkAllocationCallbacks* pAllocator)
997 {
998 RADV_FROM_HANDLE(radv_device, device, _device);
999 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
1000
1001 if (mem == NULL)
1002 return;
1003
1004 device->ws->buffer_destroy(mem->bo);
1005 mem->bo = NULL;
1006
1007 vk_free2(&device->alloc, pAllocator, mem);
1008 }
1009
1010 VkResult radv_MapMemory(
1011 VkDevice _device,
1012 VkDeviceMemory _memory,
1013 VkDeviceSize offset,
1014 VkDeviceSize size,
1015 VkMemoryMapFlags flags,
1016 void** ppData)
1017 {
1018 RADV_FROM_HANDLE(radv_device, device, _device);
1019 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1020
1021 if (mem == NULL) {
1022 *ppData = NULL;
1023 return VK_SUCCESS;
1024 }
1025
1026 *ppData = device->ws->buffer_map(mem->bo);
1027 if (*ppData) {
1028 *ppData += offset;
1029 return VK_SUCCESS;
1030 }
1031
1032 return VK_ERROR_MEMORY_MAP_FAILED;
1033 }
1034
1035 void radv_UnmapMemory(
1036 VkDevice _device,
1037 VkDeviceMemory _memory)
1038 {
1039 RADV_FROM_HANDLE(radv_device, device, _device);
1040 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1041
1042 if (mem == NULL)
1043 return;
1044
1045 device->ws->buffer_unmap(mem->bo);
1046 }
1047
1048 VkResult radv_FlushMappedMemoryRanges(
1049 VkDevice _device,
1050 uint32_t memoryRangeCount,
1051 const VkMappedMemoryRange* pMemoryRanges)
1052 {
1053 return VK_SUCCESS;
1054 }
1055
1056 VkResult radv_InvalidateMappedMemoryRanges(
1057 VkDevice _device,
1058 uint32_t memoryRangeCount,
1059 const VkMappedMemoryRange* pMemoryRanges)
1060 {
1061 return VK_SUCCESS;
1062 }
1063
1064 void radv_GetBufferMemoryRequirements(
1065 VkDevice device,
1066 VkBuffer _buffer,
1067 VkMemoryRequirements* pMemoryRequirements)
1068 {
1069 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1070
1071 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1072
1073 pMemoryRequirements->size = buffer->size;
1074 pMemoryRequirements->alignment = 16;
1075 }
1076
1077 void radv_GetImageMemoryRequirements(
1078 VkDevice device,
1079 VkImage _image,
1080 VkMemoryRequirements* pMemoryRequirements)
1081 {
1082 RADV_FROM_HANDLE(radv_image, image, _image);
1083
1084 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1085
1086 pMemoryRequirements->size = image->size;
1087 pMemoryRequirements->alignment = image->alignment;
1088 }
1089
1090 void radv_GetImageSparseMemoryRequirements(
1091 VkDevice device,
1092 VkImage image,
1093 uint32_t* pSparseMemoryRequirementCount,
1094 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
1095 {
1096 stub();
1097 }
1098
1099 void radv_GetDeviceMemoryCommitment(
1100 VkDevice device,
1101 VkDeviceMemory memory,
1102 VkDeviceSize* pCommittedMemoryInBytes)
1103 {
1104 *pCommittedMemoryInBytes = 0;
1105 }
1106
1107 VkResult radv_BindBufferMemory(
1108 VkDevice device,
1109 VkBuffer _buffer,
1110 VkDeviceMemory _memory,
1111 VkDeviceSize memoryOffset)
1112 {
1113 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1114 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1115
1116 if (mem) {
1117 buffer->bo = mem->bo;
1118 buffer->offset = memoryOffset;
1119 } else {
1120 buffer->bo = NULL;
1121 buffer->offset = 0;
1122 }
1123
1124 return VK_SUCCESS;
1125 }
1126
1127 VkResult radv_BindImageMemory(
1128 VkDevice device,
1129 VkImage _image,
1130 VkDeviceMemory _memory,
1131 VkDeviceSize memoryOffset)
1132 {
1133 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1134 RADV_FROM_HANDLE(radv_image, image, _image);
1135
1136 if (mem) {
1137 image->bo = mem->bo;
1138 image->offset = memoryOffset;
1139 } else {
1140 image->bo = NULL;
1141 image->offset = 0;
1142 }
1143
1144 return VK_SUCCESS;
1145 }
1146
1147 VkResult radv_QueueBindSparse(
1148 VkQueue queue,
1149 uint32_t bindInfoCount,
1150 const VkBindSparseInfo* pBindInfo,
1151 VkFence fence)
1152 {
1153 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER);
1154 }
1155
1156 VkResult radv_CreateFence(
1157 VkDevice _device,
1158 const VkFenceCreateInfo* pCreateInfo,
1159 const VkAllocationCallbacks* pAllocator,
1160 VkFence* pFence)
1161 {
1162 RADV_FROM_HANDLE(radv_device, device, _device);
1163 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
1164 sizeof(*fence), 8,
1165 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1166
1167 if (!fence)
1168 return VK_ERROR_OUT_OF_HOST_MEMORY;
1169
1170 memset(fence, 0, sizeof(*fence));
1171 fence->submitted = false;
1172 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
1173 fence->fence = device->ws->create_fence();
1174 if (!fence->fence) {
1175 vk_free2(&device->alloc, pAllocator, fence);
1176 return VK_ERROR_OUT_OF_HOST_MEMORY;
1177 }
1178
1179 *pFence = radv_fence_to_handle(fence);
1180
1181 return VK_SUCCESS;
1182 }
1183
1184 void radv_DestroyFence(
1185 VkDevice _device,
1186 VkFence _fence,
1187 const VkAllocationCallbacks* pAllocator)
1188 {
1189 RADV_FROM_HANDLE(radv_device, device, _device);
1190 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1191
1192 if (!fence)
1193 return;
1194 device->ws->destroy_fence(fence->fence);
1195 vk_free2(&device->alloc, pAllocator, fence);
1196 }
1197
1198 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
1199 {
1200 uint64_t current_time;
1201 struct timespec tv;
1202
1203 clock_gettime(CLOCK_MONOTONIC, &tv);
1204 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
1205
1206 timeout = MIN2(UINT64_MAX - current_time, timeout);
1207
1208 return current_time + timeout;
1209 }
1210
1211 VkResult radv_WaitForFences(
1212 VkDevice _device,
1213 uint32_t fenceCount,
1214 const VkFence* pFences,
1215 VkBool32 waitAll,
1216 uint64_t timeout)
1217 {
1218 RADV_FROM_HANDLE(radv_device, device, _device);
1219 timeout = radv_get_absolute_timeout(timeout);
1220
1221 if (!waitAll && fenceCount > 1) {
1222 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
1223 }
1224
1225 for (uint32_t i = 0; i < fenceCount; ++i) {
1226 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1227 bool expired = false;
1228
1229 if (fence->signalled)
1230 continue;
1231
1232 if (!fence->submitted)
1233 return VK_TIMEOUT;
1234
1235 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
1236 if (!expired)
1237 return VK_TIMEOUT;
1238
1239 fence->signalled = true;
1240 }
1241
1242 return VK_SUCCESS;
1243 }
1244
1245 VkResult radv_ResetFences(VkDevice device,
1246 uint32_t fenceCount,
1247 const VkFence *pFences)
1248 {
1249 for (unsigned i = 0; i < fenceCount; ++i) {
1250 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1251 fence->submitted = fence->signalled = false;
1252 }
1253
1254 return VK_SUCCESS;
1255 }
1256
1257 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
1258 {
1259 RADV_FROM_HANDLE(radv_device, device, _device);
1260 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1261
1262 if (fence->signalled)
1263 return VK_SUCCESS;
1264 if (!fence->submitted)
1265 return VK_NOT_READY;
1266
1267 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
1268 return VK_NOT_READY;
1269
1270 return VK_SUCCESS;
1271 }
1272
1273
1274 // Queue semaphore functions
1275
1276 VkResult radv_CreateSemaphore(
1277 VkDevice _device,
1278 const VkSemaphoreCreateInfo* pCreateInfo,
1279 const VkAllocationCallbacks* pAllocator,
1280 VkSemaphore* pSemaphore)
1281 {
1282 RADV_FROM_HANDLE(radv_device, device, _device);
1283 struct radeon_winsys_sem *sem;
1284
1285 sem = device->ws->create_sem(device->ws);
1286 if (!sem)
1287 return VK_ERROR_OUT_OF_HOST_MEMORY;
1288
1289 *pSemaphore = (VkSemaphore)sem;
1290 return VK_SUCCESS;
1291 }
1292
1293 void radv_DestroySemaphore(
1294 VkDevice _device,
1295 VkSemaphore _semaphore,
1296 const VkAllocationCallbacks* pAllocator)
1297 {
1298 RADV_FROM_HANDLE(radv_device, device, _device);
1299 struct radeon_winsys_sem *sem;
1300 if (!_semaphore)
1301 return;
1302
1303 sem = (struct radeon_winsys_sem *)_semaphore;
1304 device->ws->destroy_sem(sem);
1305 }
1306
1307 VkResult radv_CreateEvent(
1308 VkDevice _device,
1309 const VkEventCreateInfo* pCreateInfo,
1310 const VkAllocationCallbacks* pAllocator,
1311 VkEvent* pEvent)
1312 {
1313 RADV_FROM_HANDLE(radv_device, device, _device);
1314 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
1315 sizeof(*event), 8,
1316 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1317
1318 if (!event)
1319 return VK_ERROR_OUT_OF_HOST_MEMORY;
1320
1321 event->bo = device->ws->buffer_create(device->ws, 8, 8,
1322 RADEON_DOMAIN_GTT,
1323 RADEON_FLAG_CPU_ACCESS);
1324 if (!event->bo) {
1325 vk_free2(&device->alloc, pAllocator, event);
1326 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1327 }
1328
1329 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
1330
1331 *pEvent = radv_event_to_handle(event);
1332
1333 return VK_SUCCESS;
1334 }
1335
1336 void radv_DestroyEvent(
1337 VkDevice _device,
1338 VkEvent _event,
1339 const VkAllocationCallbacks* pAllocator)
1340 {
1341 RADV_FROM_HANDLE(radv_device, device, _device);
1342 RADV_FROM_HANDLE(radv_event, event, _event);
1343
1344 if (!event)
1345 return;
1346 device->ws->buffer_destroy(event->bo);
1347 vk_free2(&device->alloc, pAllocator, event);
1348 }
1349
1350 VkResult radv_GetEventStatus(
1351 VkDevice _device,
1352 VkEvent _event)
1353 {
1354 RADV_FROM_HANDLE(radv_event, event, _event);
1355
1356 if (*event->map == 1)
1357 return VK_EVENT_SET;
1358 return VK_EVENT_RESET;
1359 }
1360
1361 VkResult radv_SetEvent(
1362 VkDevice _device,
1363 VkEvent _event)
1364 {
1365 RADV_FROM_HANDLE(radv_event, event, _event);
1366 *event->map = 1;
1367
1368 return VK_SUCCESS;
1369 }
1370
1371 VkResult radv_ResetEvent(
1372 VkDevice _device,
1373 VkEvent _event)
1374 {
1375 RADV_FROM_HANDLE(radv_event, event, _event);
1376 *event->map = 0;
1377
1378 return VK_SUCCESS;
1379 }
1380
1381 VkResult radv_CreateBuffer(
1382 VkDevice _device,
1383 const VkBufferCreateInfo* pCreateInfo,
1384 const VkAllocationCallbacks* pAllocator,
1385 VkBuffer* pBuffer)
1386 {
1387 RADV_FROM_HANDLE(radv_device, device, _device);
1388 struct radv_buffer *buffer;
1389
1390 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
1391
1392 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
1393 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1394 if (buffer == NULL)
1395 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1396
1397 buffer->size = pCreateInfo->size;
1398 buffer->usage = pCreateInfo->usage;
1399 buffer->bo = NULL;
1400 buffer->offset = 0;
1401
1402 *pBuffer = radv_buffer_to_handle(buffer);
1403
1404 return VK_SUCCESS;
1405 }
1406
1407 void radv_DestroyBuffer(
1408 VkDevice _device,
1409 VkBuffer _buffer,
1410 const VkAllocationCallbacks* pAllocator)
1411 {
1412 RADV_FROM_HANDLE(radv_device, device, _device);
1413 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1414
1415 if (!buffer)
1416 return;
1417
1418 vk_free2(&device->alloc, pAllocator, buffer);
1419 }
1420
1421 static inline unsigned
1422 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
1423 {
1424 if (stencil)
1425 return image->surface.stencil_tiling_index[level];
1426 else
1427 return image->surface.tiling_index[level];
1428 }
1429
1430 static void
1431 radv_initialise_color_surface(struct radv_device *device,
1432 struct radv_color_buffer_info *cb,
1433 struct radv_image_view *iview)
1434 {
1435 const struct vk_format_description *desc;
1436 unsigned ntype, format, swap, endian;
1437 unsigned blend_clamp = 0, blend_bypass = 0;
1438 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
1439 uint64_t va;
1440 const struct radeon_surf *surf = &iview->image->surface;
1441 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
1442
1443 desc = vk_format_description(iview->vk_format);
1444
1445 memset(cb, 0, sizeof(*cb));
1446
1447 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1448 va += level_info->offset;
1449 cb->cb_color_base = va >> 8;
1450
1451 /* CMASK variables */
1452 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1453 va += iview->image->cmask.offset;
1454 cb->cb_color_cmask = va >> 8;
1455 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
1456
1457 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1458 va += iview->image->dcc_offset;
1459 cb->cb_dcc_base = va >> 8;
1460
1461 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
1462 S_028C6C_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1463
1464 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
1465 pitch_tile_max = level_info->nblk_x / 8 - 1;
1466 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
1467 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
1468
1469 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
1470 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
1471
1472 /* Intensity is implemented as Red, so treat it that way. */
1473 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
1474 S_028C74_TILE_MODE_INDEX(tile_mode_index);
1475
1476 if (iview->image->samples > 1) {
1477 unsigned log_samples = util_logbase2(iview->image->samples);
1478
1479 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1480 S_028C74_NUM_FRAGMENTS(log_samples);
1481 }
1482
1483 if (iview->image->fmask.size) {
1484 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
1485 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1486 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
1487 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
1488 cb->cb_color_fmask = va >> 8;
1489 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
1490 } else {
1491 /* This must be set for fast clear to work without FMASK. */
1492 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1493 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
1494 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1495 cb->cb_color_fmask = cb->cb_color_base;
1496 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
1497 }
1498
1499 ntype = radv_translate_color_numformat(iview->vk_format,
1500 desc,
1501 vk_format_get_first_non_void_channel(iview->vk_format));
1502 format = radv_translate_colorformat(iview->vk_format);
1503 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
1504 radv_finishme("Illegal color\n");
1505 swap = radv_translate_colorswap(iview->vk_format, FALSE);
1506 endian = radv_colorformat_endian_swap(format);
1507
1508 /* blend clamp should be set for all NORM/SRGB types */
1509 if (ntype == V_028C70_NUMBER_UNORM ||
1510 ntype == V_028C70_NUMBER_SNORM ||
1511 ntype == V_028C70_NUMBER_SRGB)
1512 blend_clamp = 1;
1513
1514 /* set blend bypass according to docs if SINT/UINT or
1515 8/24 COLOR variants */
1516 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1517 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1518 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1519 blend_clamp = 0;
1520 blend_bypass = 1;
1521 }
1522 #if 0
1523 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
1524 (format == V_028C70_COLOR_8 ||
1525 format == V_028C70_COLOR_8_8 ||
1526 format == V_028C70_COLOR_8_8_8_8))
1527 ->color_is_int8 = true;
1528 #endif
1529 cb->cb_color_info = S_028C70_FORMAT(format) |
1530 S_028C70_COMP_SWAP(swap) |
1531 S_028C70_BLEND_CLAMP(blend_clamp) |
1532 S_028C70_BLEND_BYPASS(blend_bypass) |
1533 S_028C70_SIMPLE_FLOAT(1) |
1534 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
1535 ntype != V_028C70_NUMBER_SNORM &&
1536 ntype != V_028C70_NUMBER_SRGB &&
1537 format != V_028C70_COLOR_8_24 &&
1538 format != V_028C70_COLOR_24_8) |
1539 S_028C70_NUMBER_TYPE(ntype) |
1540 S_028C70_ENDIAN(endian);
1541 if (iview->image->samples > 1)
1542 if (iview->image->fmask.size)
1543 cb->cb_color_info |= S_028C70_COMPRESSION(1);
1544
1545 if (iview->image->cmask.size && device->allow_fast_clears)
1546 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
1547
1548 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
1549 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
1550
1551 if (device->instance->physicalDevice.rad_info.chip_class >= VI) {
1552 unsigned max_uncompressed_block_size = 2;
1553 if (iview->image->samples > 1) {
1554 if (iview->image->surface.bpe == 1)
1555 max_uncompressed_block_size = 0;
1556 else if (iview->image->surface.bpe == 2)
1557 max_uncompressed_block_size = 1;
1558 }
1559
1560 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
1561 S_028C78_INDEPENDENT_64B_BLOCKS(1);
1562 }
1563
1564 /* This must be set for fast clear to work without FMASK. */
1565 if (!iview->image->fmask.size &&
1566 device->instance->physicalDevice.rad_info.chip_class == SI) {
1567 unsigned bankh = util_logbase2(iview->image->surface.bankh);
1568 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1569 }
1570 }
1571
1572 static void
1573 radv_initialise_ds_surface(struct radv_device *device,
1574 struct radv_ds_buffer_info *ds,
1575 struct radv_image_view *iview)
1576 {
1577 unsigned level = iview->base_mip;
1578 unsigned format;
1579 uint64_t va, s_offs, z_offs;
1580 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
1581 memset(ds, 0, sizeof(*ds));
1582 switch (iview->vk_format) {
1583 case VK_FORMAT_D24_UNORM_S8_UINT:
1584 case VK_FORMAT_X8_D24_UNORM_PACK32:
1585 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1586 ds->offset_scale = 2.0f;
1587 break;
1588 case VK_FORMAT_D16_UNORM:
1589 case VK_FORMAT_D16_UNORM_S8_UINT:
1590 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1591 ds->offset_scale = 4.0f;
1592 break;
1593 case VK_FORMAT_D32_SFLOAT:
1594 case VK_FORMAT_D32_SFLOAT_S8_UINT:
1595 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1596 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1597 ds->offset_scale = 1.0f;
1598 break;
1599 default:
1600 break;
1601 }
1602
1603 format = radv_translate_dbformat(iview->vk_format);
1604 if (format == V_028040_Z_INVALID) {
1605 fprintf(stderr, "Invalid DB format: %d, disabling DB.\n", iview->vk_format);
1606 }
1607
1608 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1609 s_offs = z_offs = va;
1610 z_offs += iview->image->surface.level[level].offset;
1611 s_offs += iview->image->surface.stencil_level[level].offset;
1612
1613 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
1614 S_028008_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1615 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1616 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
1617
1618 if (iview->image->samples > 1)
1619 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
1620
1621 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
1622 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
1623 else
1624 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1625
1626 if (device->instance->physicalDevice.rad_info.chip_class >= CIK) {
1627 struct radeon_info *info = &device->instance->physicalDevice.rad_info;
1628 unsigned tiling_index = iview->image->surface.tiling_index[level];
1629 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
1630 unsigned macro_index = iview->image->surface.macro_tile_index;
1631 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
1632 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
1633 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
1634
1635 ds->db_depth_info |=
1636 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
1637 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
1638 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
1639 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
1640 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
1641 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
1642 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
1643 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
1644 } else {
1645 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
1646 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1647 tile_mode_index = si_tile_mode_index(iview->image, level, true);
1648 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1649 }
1650
1651 if (iview->image->htile.size && !level) {
1652 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1653 S_028040_ALLOW_EXPCLEAR(1);
1654
1655 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
1656 /* Workaround: For a not yet understood reason, the
1657 * combination of MSAA, fast stencil clear and stencil
1658 * decompress messes with subsequent stencil buffer
1659 * uses. Problem was reproduced on Verde, Bonaire,
1660 * Tonga, and Carrizo.
1661 *
1662 * Disabling EXPCLEAR works around the problem.
1663 *
1664 * Check piglit's arb_texture_multisample-stencil-clear
1665 * test if you want to try changing this.
1666 */
1667 if (iview->image->samples <= 1)
1668 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
1669 } else
1670 /* Use all of the htile_buffer for depth if there's no stencil. */
1671 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1672
1673 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
1674 iview->image->htile.offset;
1675 ds->db_htile_data_base = va >> 8;
1676 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
1677 } else {
1678 ds->db_htile_data_base = 0;
1679 ds->db_htile_surface = 0;
1680 }
1681
1682 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
1683 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
1684
1685 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
1686 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
1687 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
1688 }
1689
1690 VkResult radv_CreateFramebuffer(
1691 VkDevice _device,
1692 const VkFramebufferCreateInfo* pCreateInfo,
1693 const VkAllocationCallbacks* pAllocator,
1694 VkFramebuffer* pFramebuffer)
1695 {
1696 RADV_FROM_HANDLE(radv_device, device, _device);
1697 struct radv_framebuffer *framebuffer;
1698
1699 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
1700
1701 size_t size = sizeof(*framebuffer) +
1702 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
1703 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
1704 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1705 if (framebuffer == NULL)
1706 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1707
1708 framebuffer->attachment_count = pCreateInfo->attachmentCount;
1709 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
1710 VkImageView _iview = pCreateInfo->pAttachments[i];
1711 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
1712 framebuffer->attachments[i].attachment = iview;
1713 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
1714 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
1715 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
1716 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
1717 }
1718 }
1719
1720 framebuffer->width = pCreateInfo->width;
1721 framebuffer->height = pCreateInfo->height;
1722 framebuffer->layers = pCreateInfo->layers;
1723
1724 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
1725 return VK_SUCCESS;
1726 }
1727
1728 void radv_DestroyFramebuffer(
1729 VkDevice _device,
1730 VkFramebuffer _fb,
1731 const VkAllocationCallbacks* pAllocator)
1732 {
1733 RADV_FROM_HANDLE(radv_device, device, _device);
1734 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
1735
1736 if (!fb)
1737 return;
1738 vk_free2(&device->alloc, pAllocator, fb);
1739 }
1740
1741 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
1742 {
1743 switch (address_mode) {
1744 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
1745 return V_008F30_SQ_TEX_WRAP;
1746 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
1747 return V_008F30_SQ_TEX_MIRROR;
1748 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
1749 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1750 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
1751 return V_008F30_SQ_TEX_CLAMP_BORDER;
1752 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
1753 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1754 default:
1755 unreachable("illegal tex wrap mode");
1756 break;
1757 }
1758 }
1759
1760 static unsigned
1761 radv_tex_compare(VkCompareOp op)
1762 {
1763 switch (op) {
1764 case VK_COMPARE_OP_NEVER:
1765 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1766 case VK_COMPARE_OP_LESS:
1767 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1768 case VK_COMPARE_OP_EQUAL:
1769 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1770 case VK_COMPARE_OP_LESS_OR_EQUAL:
1771 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1772 case VK_COMPARE_OP_GREATER:
1773 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1774 case VK_COMPARE_OP_NOT_EQUAL:
1775 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1776 case VK_COMPARE_OP_GREATER_OR_EQUAL:
1777 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1778 case VK_COMPARE_OP_ALWAYS:
1779 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1780 default:
1781 unreachable("illegal compare mode");
1782 break;
1783 }
1784 }
1785
1786 static unsigned
1787 radv_tex_filter(VkFilter filter, unsigned max_ansio)
1788 {
1789 switch (filter) {
1790 case VK_FILTER_NEAREST:
1791 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
1792 V_008F38_SQ_TEX_XY_FILTER_POINT);
1793 case VK_FILTER_LINEAR:
1794 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
1795 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
1796 case VK_FILTER_CUBIC_IMG:
1797 default:
1798 fprintf(stderr, "illegal texture filter");
1799 return 0;
1800 }
1801 }
1802
1803 static unsigned
1804 radv_tex_mipfilter(VkSamplerMipmapMode mode)
1805 {
1806 switch (mode) {
1807 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
1808 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1809 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
1810 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1811 default:
1812 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1813 }
1814 }
1815
1816 static unsigned
1817 radv_tex_bordercolor(VkBorderColor bcolor)
1818 {
1819 switch (bcolor) {
1820 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
1821 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
1822 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
1823 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
1824 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
1825 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
1826 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
1827 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
1828 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
1829 default:
1830 break;
1831 }
1832 return 0;
1833 }
1834
1835 static unsigned
1836 radv_tex_aniso_filter(unsigned filter)
1837 {
1838 if (filter < 2)
1839 return 0;
1840 if (filter < 4)
1841 return 1;
1842 if (filter < 8)
1843 return 2;
1844 if (filter < 16)
1845 return 3;
1846 return 4;
1847 }
1848
1849 static void
1850 radv_init_sampler(struct radv_device *device,
1851 struct radv_sampler *sampler,
1852 const VkSamplerCreateInfo *pCreateInfo)
1853 {
1854 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
1855 (uint32_t) pCreateInfo->maxAnisotropy : 0;
1856 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
1857 bool is_vi = (device->instance->physicalDevice.rad_info.chip_class >= VI);
1858
1859 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
1860 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
1861 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
1862 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
1863 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
1864 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
1865 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
1866 S_008F30_ANISO_BIAS(max_aniso_ratio) |
1867 S_008F30_DISABLE_CUBE_WRAP(0) |
1868 S_008F30_COMPAT_MODE(is_vi));
1869 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
1870 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
1871 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
1872 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
1873 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
1874 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
1875 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
1876 S_008F38_MIP_POINT_PRECLAMP(1) |
1877 S_008F38_DISABLE_LSB_CEIL(1) |
1878 S_008F38_FILTER_PREC_FIX(1) |
1879 S_008F38_ANISO_OVERRIDE(is_vi));
1880 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
1881 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
1882 }
1883
1884 VkResult radv_CreateSampler(
1885 VkDevice _device,
1886 const VkSamplerCreateInfo* pCreateInfo,
1887 const VkAllocationCallbacks* pAllocator,
1888 VkSampler* pSampler)
1889 {
1890 RADV_FROM_HANDLE(radv_device, device, _device);
1891 struct radv_sampler *sampler;
1892
1893 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
1894
1895 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
1896 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1897 if (!sampler)
1898 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1899
1900 radv_init_sampler(device, sampler, pCreateInfo);
1901 *pSampler = radv_sampler_to_handle(sampler);
1902
1903 return VK_SUCCESS;
1904 }
1905
1906 void radv_DestroySampler(
1907 VkDevice _device,
1908 VkSampler _sampler,
1909 const VkAllocationCallbacks* pAllocator)
1910 {
1911 RADV_FROM_HANDLE(radv_device, device, _device);
1912 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
1913
1914 if (!sampler)
1915 return;
1916 vk_free2(&device->alloc, pAllocator, sampler);
1917 }