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radv: do not open random render node(s)
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "util/disk_cache.h"
35 #include "util/strtod.h"
36 #include "util/vk_util.h"
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "util/debug.h"
46
47 static int
48 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
49 {
50 uint32_t mesa_timestamp, llvm_timestamp;
51 uint16_t f = family;
52 memset(uuid, 0, VK_UUID_SIZE);
53 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
54 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
55 return -1;
56
57 memcpy(uuid, &mesa_timestamp, 4);
58 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
59 memcpy((char*)uuid + 8, &f, 2);
60 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
61 return 0;
62 }
63
64 static const VkExtensionProperties instance_extensions[] = {
65 {
66 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
67 .specVersion = 25,
68 },
69 #ifdef VK_USE_PLATFORM_XCB_KHR
70 {
71 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
72 .specVersion = 6,
73 },
74 #endif
75 #ifdef VK_USE_PLATFORM_XLIB_KHR
76 {
77 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
78 .specVersion = 6,
79 },
80 #endif
81 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
82 {
83 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
84 .specVersion = 5,
85 },
86 #endif
87 };
88
89 static const VkExtensionProperties common_device_extensions[] = {
90 {
91 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
92 .specVersion = 1,
93 },
94 {
95 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
96 .specVersion = 1,
97 },
98 {
99 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
100 .specVersion = 68,
101 },
102 {
103 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
104 .specVersion = 1,
105 },
106 {
107 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
108 .specVersion = 1,
109 },
110 {
111 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
112 .specVersion = 1,
113 },
114 {
115 .extensionName = VK_NV_DEDICATED_ALLOCATION_EXTENSION_NAME,
116 .specVersion = 1,
117 },
118 };
119
120 static VkResult
121 radv_extensions_register(struct radv_instance *instance,
122 struct radv_extensions *extensions,
123 const VkExtensionProperties *new_ext,
124 uint32_t num_ext)
125 {
126 size_t new_size;
127 VkExtensionProperties *new_ptr;
128
129 assert(new_ext && num_ext > 0);
130
131 if (!new_ext)
132 return VK_ERROR_INITIALIZATION_FAILED;
133
134 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
135 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
136 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
137
138 /* Old array continues to be valid, update nothing */
139 if (!new_ptr)
140 return VK_ERROR_OUT_OF_HOST_MEMORY;
141
142 memcpy(&new_ptr[extensions->num_ext], new_ext,
143 num_ext * sizeof(VkExtensionProperties));
144 extensions->ext_array = new_ptr;
145 extensions->num_ext += num_ext;
146
147 return VK_SUCCESS;
148 }
149
150 static void
151 radv_extensions_finish(struct radv_instance *instance,
152 struct radv_extensions *extensions)
153 {
154 assert(extensions);
155
156 if (!extensions)
157 radv_loge("Attemted to free invalid extension struct\n");
158
159 if (extensions->ext_array)
160 vk_free(&instance->alloc, extensions->ext_array);
161 }
162
163 static bool
164 is_extension_enabled(const VkExtensionProperties *extensions,
165 size_t num_ext,
166 const char *name)
167 {
168 assert(extensions && name);
169
170 for (uint32_t i = 0; i < num_ext; i++) {
171 if (strcmp(name, extensions[i].extensionName) == 0)
172 return true;
173 }
174
175 return false;
176 }
177
178 static VkResult
179 radv_physical_device_init(struct radv_physical_device *device,
180 struct radv_instance *instance,
181 const char *path)
182 {
183 VkResult result;
184 drmVersionPtr version;
185 int fd;
186
187 fd = open(path, O_RDWR | O_CLOEXEC);
188 if (fd < 0)
189 return VK_ERROR_INCOMPATIBLE_DRIVER;
190
191 version = drmGetVersion(fd);
192 if (!version) {
193 close(fd);
194 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
195 "failed to get version %s: %m", path);
196 }
197
198 if (strcmp(version->name, "amdgpu")) {
199 drmFreeVersion(version);
200 close(fd);
201 return VK_ERROR_INCOMPATIBLE_DRIVER;
202 }
203 drmFreeVersion(version);
204
205 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
206 device->instance = instance;
207 assert(strlen(path) < ARRAY_SIZE(device->path));
208 strncpy(device->path, path, ARRAY_SIZE(device->path));
209
210 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags);
211 if (!device->ws) {
212 result = VK_ERROR_INCOMPATIBLE_DRIVER;
213 goto fail;
214 }
215
216 device->local_fd = fd;
217 device->ws->query_info(device->ws, &device->rad_info);
218 result = radv_init_wsi(device);
219 if (result != VK_SUCCESS) {
220 device->ws->destroy(device->ws);
221 goto fail;
222 }
223
224 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
225 radv_finish_wsi(device);
226 device->ws->destroy(device->ws);
227 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
228 "cannot generate UUID");
229 goto fail;
230 }
231
232 result = radv_extensions_register(instance,
233 &device->extensions,
234 common_device_extensions,
235 ARRAY_SIZE(common_device_extensions));
236 if (result != VK_SUCCESS)
237 goto fail;
238
239 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
240 device->name = device->rad_info.name;
241
242 return VK_SUCCESS;
243
244 fail:
245 close(fd);
246 return result;
247 }
248
249 static void
250 radv_physical_device_finish(struct radv_physical_device *device)
251 {
252 radv_extensions_finish(device->instance, &device->extensions);
253 radv_finish_wsi(device);
254 device->ws->destroy(device->ws);
255 close(device->local_fd);
256 }
257
258
259 static void *
260 default_alloc_func(void *pUserData, size_t size, size_t align,
261 VkSystemAllocationScope allocationScope)
262 {
263 return malloc(size);
264 }
265
266 static void *
267 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
268 size_t align, VkSystemAllocationScope allocationScope)
269 {
270 return realloc(pOriginal, size);
271 }
272
273 static void
274 default_free_func(void *pUserData, void *pMemory)
275 {
276 free(pMemory);
277 }
278
279 static const VkAllocationCallbacks default_alloc = {
280 .pUserData = NULL,
281 .pfnAllocation = default_alloc_func,
282 .pfnReallocation = default_realloc_func,
283 .pfnFree = default_free_func,
284 };
285
286 static const struct debug_control radv_debug_options[] = {
287 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
288 {"nodcc", RADV_DEBUG_NO_DCC},
289 {"shaders", RADV_DEBUG_DUMP_SHADERS},
290 {"nocache", RADV_DEBUG_NO_CACHE},
291 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
292 {"nohiz", RADV_DEBUG_NO_HIZ},
293 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
294 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
295 {"allbos", RADV_DEBUG_ALL_BOS},
296 {"noibs", RADV_DEBUG_NO_IBS},
297 {NULL, 0}
298 };
299
300 VkResult radv_CreateInstance(
301 const VkInstanceCreateInfo* pCreateInfo,
302 const VkAllocationCallbacks* pAllocator,
303 VkInstance* pInstance)
304 {
305 struct radv_instance *instance;
306
307 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
308
309 uint32_t client_version;
310 if (pCreateInfo->pApplicationInfo &&
311 pCreateInfo->pApplicationInfo->apiVersion != 0) {
312 client_version = pCreateInfo->pApplicationInfo->apiVersion;
313 } else {
314 client_version = VK_MAKE_VERSION(1, 0, 0);
315 }
316
317 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
318 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
319 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
320 "Client requested version %d.%d.%d",
321 VK_VERSION_MAJOR(client_version),
322 VK_VERSION_MINOR(client_version),
323 VK_VERSION_PATCH(client_version));
324 }
325
326 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
327 if (!is_extension_enabled(instance_extensions,
328 ARRAY_SIZE(instance_extensions),
329 pCreateInfo->ppEnabledExtensionNames[i]))
330 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
331 }
332
333 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
334 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
335 if (!instance)
336 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
337
338 memset(instance, 0, sizeof(*instance));
339
340 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
341
342 if (pAllocator)
343 instance->alloc = *pAllocator;
344 else
345 instance->alloc = default_alloc;
346
347 instance->apiVersion = client_version;
348 instance->physicalDeviceCount = -1;
349
350 _mesa_locale_init();
351
352 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
353
354 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
355 radv_debug_options);
356
357 *pInstance = radv_instance_to_handle(instance);
358
359 return VK_SUCCESS;
360 }
361
362 void radv_DestroyInstance(
363 VkInstance _instance,
364 const VkAllocationCallbacks* pAllocator)
365 {
366 RADV_FROM_HANDLE(radv_instance, instance, _instance);
367
368 if (!instance)
369 return;
370
371 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
372 radv_physical_device_finish(instance->physicalDevices + i);
373 }
374
375 VG(VALGRIND_DESTROY_MEMPOOL(instance));
376
377 _mesa_locale_fini();
378
379 vk_free(&instance->alloc, instance);
380 }
381
382 static VkResult
383 radv_enumerate_devices(struct radv_instance *instance)
384 {
385 /* TODO: Check for more devices ? */
386 drmDevicePtr devices[8];
387 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
388 int max_devices;
389
390 instance->physicalDeviceCount = 0;
391
392 max_devices = drmGetDevices2(0, devices, sizeof(devices));
393 if (max_devices < 1)
394 return VK_ERROR_INCOMPATIBLE_DRIVER;
395
396 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
397 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
398 devices[i]->bustype == DRM_BUS_PCI &&
399 devices[i]->deviceinfo.pci->vendor_id == 0x1002) {
400
401 result = radv_physical_device_init(instance->physicalDevices +
402 instance->physicalDeviceCount,
403 instance,
404 devices[i]->nodes[DRM_NODE_RENDER]);
405 if (result == VK_SUCCESS)
406 ++instance->physicalDeviceCount;
407 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
408 return result;
409 }
410 }
411 return result;
412 }
413
414 VkResult radv_EnumeratePhysicalDevices(
415 VkInstance _instance,
416 uint32_t* pPhysicalDeviceCount,
417 VkPhysicalDevice* pPhysicalDevices)
418 {
419 RADV_FROM_HANDLE(radv_instance, instance, _instance);
420 VkResult result;
421
422 if (instance->physicalDeviceCount < 0) {
423 result = radv_enumerate_devices(instance);
424 if (result != VK_SUCCESS &&
425 result != VK_ERROR_INCOMPATIBLE_DRIVER)
426 return result;
427 }
428
429 if (!pPhysicalDevices) {
430 *pPhysicalDeviceCount = instance->physicalDeviceCount;
431 } else {
432 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
433 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
434 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
435 }
436
437 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
438 : VK_SUCCESS;
439 }
440
441 void radv_GetPhysicalDeviceFeatures(
442 VkPhysicalDevice physicalDevice,
443 VkPhysicalDeviceFeatures* pFeatures)
444 {
445 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
446
447 memset(pFeatures, 0, sizeof(*pFeatures));
448
449 *pFeatures = (VkPhysicalDeviceFeatures) {
450 .robustBufferAccess = true,
451 .fullDrawIndexUint32 = true,
452 .imageCubeArray = true,
453 .independentBlend = true,
454 .geometryShader = true,
455 .tessellationShader = false,
456 .sampleRateShading = false,
457 .dualSrcBlend = true,
458 .logicOp = true,
459 .multiDrawIndirect = true,
460 .drawIndirectFirstInstance = true,
461 .depthClamp = true,
462 .depthBiasClamp = true,
463 .fillModeNonSolid = true,
464 .depthBounds = true,
465 .wideLines = true,
466 .largePoints = true,
467 .alphaToOne = true,
468 .multiViewport = true,
469 .samplerAnisotropy = true,
470 .textureCompressionETC2 = false,
471 .textureCompressionASTC_LDR = false,
472 .textureCompressionBC = true,
473 .occlusionQueryPrecise = true,
474 .pipelineStatisticsQuery = false,
475 .vertexPipelineStoresAndAtomics = true,
476 .fragmentStoresAndAtomics = true,
477 .shaderTessellationAndGeometryPointSize = true,
478 .shaderImageGatherExtended = true,
479 .shaderStorageImageExtendedFormats = true,
480 .shaderStorageImageMultisample = false,
481 .shaderUniformBufferArrayDynamicIndexing = true,
482 .shaderSampledImageArrayDynamicIndexing = true,
483 .shaderStorageBufferArrayDynamicIndexing = true,
484 .shaderStorageImageArrayDynamicIndexing = true,
485 .shaderStorageImageReadWithoutFormat = true,
486 .shaderStorageImageWriteWithoutFormat = true,
487 .shaderClipDistance = true,
488 .shaderCullDistance = true,
489 .shaderFloat64 = true,
490 .shaderInt64 = false,
491 .shaderInt16 = false,
492 .variableMultisampleRate = false,
493 .inheritedQueries = false,
494 };
495 }
496
497 void radv_GetPhysicalDeviceFeatures2KHR(
498 VkPhysicalDevice physicalDevice,
499 VkPhysicalDeviceFeatures2KHR *pFeatures)
500 {
501 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
502 }
503
504 static uint32_t radv_get_driver_version()
505 {
506 const char *minor_string = strchr(VERSION, '.');
507 const char *patch_string = minor_string ? strchr(minor_string + 1, ','): NULL;
508 int major = atoi(VERSION);
509 int minor = minor_string ? atoi(minor_string + 1) : 0;
510 int patch = patch_string ? atoi(patch_string + 1) : 0;
511 if (strstr(VERSION, "devel")) {
512 if (patch == 0) {
513 patch = 99;
514 if (minor == 0) {
515 minor = 99;
516 --major;
517 } else
518 --minor;
519 } else
520 --patch;
521 }
522 uint32_t version = VK_MAKE_VERSION(major, minor, patch);
523 return version;
524 }
525
526 void radv_GetPhysicalDeviceProperties(
527 VkPhysicalDevice physicalDevice,
528 VkPhysicalDeviceProperties* pProperties)
529 {
530 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
531 VkSampleCountFlags sample_counts = 0xf;
532 VkPhysicalDeviceLimits limits = {
533 .maxImageDimension1D = (1 << 14),
534 .maxImageDimension2D = (1 << 14),
535 .maxImageDimension3D = (1 << 11),
536 .maxImageDimensionCube = (1 << 14),
537 .maxImageArrayLayers = (1 << 11),
538 .maxTexelBufferElements = 128 * 1024 * 1024,
539 .maxUniformBufferRange = UINT32_MAX,
540 .maxStorageBufferRange = UINT32_MAX,
541 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
542 .maxMemoryAllocationCount = UINT32_MAX,
543 .maxSamplerAllocationCount = 64 * 1024,
544 .bufferImageGranularity = 64, /* A cache line */
545 .sparseAddressSpaceSize = 0,
546 .maxBoundDescriptorSets = MAX_SETS,
547 .maxPerStageDescriptorSamplers = 64,
548 .maxPerStageDescriptorUniformBuffers = 64,
549 .maxPerStageDescriptorStorageBuffers = 64,
550 .maxPerStageDescriptorSampledImages = 64,
551 .maxPerStageDescriptorStorageImages = 64,
552 .maxPerStageDescriptorInputAttachments = 64,
553 .maxPerStageResources = 128,
554 .maxDescriptorSetSamplers = 256,
555 .maxDescriptorSetUniformBuffers = 256,
556 .maxDescriptorSetUniformBuffersDynamic = 256,
557 .maxDescriptorSetStorageBuffers = 256,
558 .maxDescriptorSetStorageBuffersDynamic = 256,
559 .maxDescriptorSetSampledImages = 256,
560 .maxDescriptorSetStorageImages = 256,
561 .maxDescriptorSetInputAttachments = 256,
562 .maxVertexInputAttributes = 32,
563 .maxVertexInputBindings = 32,
564 .maxVertexInputAttributeOffset = 2047,
565 .maxVertexInputBindingStride = 2048,
566 .maxVertexOutputComponents = 128,
567 .maxTessellationGenerationLevel = 0,
568 .maxTessellationPatchSize = 0,
569 .maxTessellationControlPerVertexInputComponents = 0,
570 .maxTessellationControlPerVertexOutputComponents = 0,
571 .maxTessellationControlPerPatchOutputComponents = 0,
572 .maxTessellationControlTotalOutputComponents = 0,
573 .maxTessellationEvaluationInputComponents = 0,
574 .maxTessellationEvaluationOutputComponents = 0,
575 .maxGeometryShaderInvocations = 32,
576 .maxGeometryInputComponents = 64,
577 .maxGeometryOutputComponents = 128,
578 .maxGeometryOutputVertices = 256,
579 .maxGeometryTotalOutputComponents = 1024,
580 .maxFragmentInputComponents = 128,
581 .maxFragmentOutputAttachments = 8,
582 .maxFragmentDualSrcAttachments = 1,
583 .maxFragmentCombinedOutputResources = 8,
584 .maxComputeSharedMemorySize = 32768,
585 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
586 .maxComputeWorkGroupInvocations = 2048,
587 .maxComputeWorkGroupSize = {
588 2048,
589 2048,
590 2048
591 },
592 .subPixelPrecisionBits = 4 /* FIXME */,
593 .subTexelPrecisionBits = 4 /* FIXME */,
594 .mipmapPrecisionBits = 4 /* FIXME */,
595 .maxDrawIndexedIndexValue = UINT32_MAX,
596 .maxDrawIndirectCount = UINT32_MAX,
597 .maxSamplerLodBias = 16,
598 .maxSamplerAnisotropy = 16,
599 .maxViewports = MAX_VIEWPORTS,
600 .maxViewportDimensions = { (1 << 14), (1 << 14) },
601 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
602 .viewportSubPixelBits = 13, /* We take a float? */
603 .minMemoryMapAlignment = 4096, /* A page */
604 .minTexelBufferOffsetAlignment = 1,
605 .minUniformBufferOffsetAlignment = 4,
606 .minStorageBufferOffsetAlignment = 4,
607 .minTexelOffset = -32,
608 .maxTexelOffset = 31,
609 .minTexelGatherOffset = -32,
610 .maxTexelGatherOffset = 31,
611 .minInterpolationOffset = -2,
612 .maxInterpolationOffset = 2,
613 .subPixelInterpolationOffsetBits = 8,
614 .maxFramebufferWidth = (1 << 14),
615 .maxFramebufferHeight = (1 << 14),
616 .maxFramebufferLayers = (1 << 10),
617 .framebufferColorSampleCounts = sample_counts,
618 .framebufferDepthSampleCounts = sample_counts,
619 .framebufferStencilSampleCounts = sample_counts,
620 .framebufferNoAttachmentsSampleCounts = sample_counts,
621 .maxColorAttachments = MAX_RTS,
622 .sampledImageColorSampleCounts = sample_counts,
623 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
624 .sampledImageDepthSampleCounts = sample_counts,
625 .sampledImageStencilSampleCounts = sample_counts,
626 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
627 .maxSampleMaskWords = 1,
628 .timestampComputeAndGraphics = false,
629 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
630 .maxClipDistances = 8,
631 .maxCullDistances = 8,
632 .maxCombinedClipAndCullDistances = 8,
633 .discreteQueuePriorities = 1,
634 .pointSizeRange = { 0.125, 255.875 },
635 .lineWidthRange = { 0.0, 7.9921875 },
636 .pointSizeGranularity = (1.0 / 8.0),
637 .lineWidthGranularity = (1.0 / 128.0),
638 .strictLines = false, /* FINISHME */
639 .standardSampleLocations = true,
640 .optimalBufferCopyOffsetAlignment = 128,
641 .optimalBufferCopyRowPitchAlignment = 128,
642 .nonCoherentAtomSize = 64,
643 };
644
645 *pProperties = (VkPhysicalDeviceProperties) {
646 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
647 .driverVersion = radv_get_driver_version(),
648 .vendorID = 0x1002,
649 .deviceID = pdevice->rad_info.pci_id,
650 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
651 .limits = limits,
652 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
653 };
654
655 strcpy(pProperties->deviceName, pdevice->name);
656 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
657 }
658
659 void radv_GetPhysicalDeviceProperties2KHR(
660 VkPhysicalDevice physicalDevice,
661 VkPhysicalDeviceProperties2KHR *pProperties)
662 {
663 return radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
664 }
665
666 static void radv_get_physical_device_queue_family_properties(
667 struct radv_physical_device* pdevice,
668 uint32_t* pCount,
669 VkQueueFamilyProperties** pQueueFamilyProperties)
670 {
671 int num_queue_families = 1;
672 int idx;
673 if (pdevice->rad_info.compute_rings > 0 &&
674 pdevice->rad_info.chip_class >= CIK &&
675 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
676 num_queue_families++;
677
678 if (pQueueFamilyProperties == NULL) {
679 *pCount = num_queue_families;
680 return;
681 }
682
683 if (!*pCount)
684 return;
685
686 idx = 0;
687 if (*pCount >= 1) {
688 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
689 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
690 VK_QUEUE_COMPUTE_BIT |
691 VK_QUEUE_TRANSFER_BIT,
692 .queueCount = 1,
693 .timestampValidBits = 64,
694 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
695 };
696 idx++;
697 }
698
699 if (pdevice->rad_info.compute_rings > 0 &&
700 pdevice->rad_info.chip_class >= CIK &&
701 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
702 if (*pCount > idx) {
703 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
704 .queueFlags = VK_QUEUE_COMPUTE_BIT | VK_QUEUE_TRANSFER_BIT,
705 .queueCount = pdevice->rad_info.compute_rings,
706 .timestampValidBits = 64,
707 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
708 };
709 idx++;
710 }
711 }
712 *pCount = idx;
713 }
714
715 void radv_GetPhysicalDeviceQueueFamilyProperties(
716 VkPhysicalDevice physicalDevice,
717 uint32_t* pCount,
718 VkQueueFamilyProperties* pQueueFamilyProperties)
719 {
720 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
721 if (!pQueueFamilyProperties) {
722 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
723 return;
724 }
725 VkQueueFamilyProperties *properties[] = {
726 pQueueFamilyProperties + 0,
727 pQueueFamilyProperties + 1,
728 pQueueFamilyProperties + 2,
729 };
730 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
731 assert(*pCount <= 3);
732 }
733
734 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
735 VkPhysicalDevice physicalDevice,
736 uint32_t* pCount,
737 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
738 {
739 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
740 if (!pQueueFamilyProperties) {
741 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
742 return;
743 }
744 VkQueueFamilyProperties *properties[] = {
745 &pQueueFamilyProperties[0].queueFamilyProperties,
746 &pQueueFamilyProperties[1].queueFamilyProperties,
747 &pQueueFamilyProperties[2].queueFamilyProperties,
748 };
749 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
750 assert(*pCount <= 3);
751 }
752
753 void radv_GetPhysicalDeviceMemoryProperties(
754 VkPhysicalDevice physicalDevice,
755 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
756 {
757 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
758
759 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
760
761 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
762 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
763 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
764 .heapIndex = RADV_MEM_HEAP_VRAM,
765 };
766 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
767 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
768 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
769 .heapIndex = RADV_MEM_HEAP_GTT,
770 };
771 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
772 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
773 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
774 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
775 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
776 };
777 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
778 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
779 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
780 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
781 .heapIndex = RADV_MEM_HEAP_GTT,
782 };
783
784 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
785
786 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
787 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
788 .size = physical_device->rad_info.vram_size -
789 physical_device->rad_info.visible_vram_size,
790 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
791 };
792 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
793 .size = physical_device->rad_info.visible_vram_size,
794 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
795 };
796 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
797 .size = physical_device->rad_info.gart_size,
798 .flags = 0,
799 };
800 }
801
802 void radv_GetPhysicalDeviceMemoryProperties2KHR(
803 VkPhysicalDevice physicalDevice,
804 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
805 {
806 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
807 &pMemoryProperties->memoryProperties);
808 }
809
810 static int
811 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
812 int queue_family_index, int idx)
813 {
814 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
815 queue->device = device;
816 queue->queue_family_index = queue_family_index;
817 queue->queue_idx = idx;
818
819 queue->hw_ctx = device->ws->ctx_create(device->ws);
820 if (!queue->hw_ctx)
821 return VK_ERROR_OUT_OF_HOST_MEMORY;
822
823 return VK_SUCCESS;
824 }
825
826 static void
827 radv_queue_finish(struct radv_queue *queue)
828 {
829 if (queue->hw_ctx)
830 queue->device->ws->ctx_destroy(queue->hw_ctx);
831
832 if (queue->initial_preamble_cs)
833 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
834 if (queue->continue_preamble_cs)
835 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
836 if (queue->descriptor_bo)
837 queue->device->ws->buffer_destroy(queue->descriptor_bo);
838 if (queue->scratch_bo)
839 queue->device->ws->buffer_destroy(queue->scratch_bo);
840 if (queue->esgs_ring_bo)
841 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
842 if (queue->gsvs_ring_bo)
843 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
844 if (queue->compute_scratch_bo)
845 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
846 }
847
848 static void
849 radv_device_init_gs_info(struct radv_device *device)
850 {
851 switch (device->physical_device->rad_info.family) {
852 case CHIP_OLAND:
853 case CHIP_HAINAN:
854 case CHIP_KAVERI:
855 case CHIP_KABINI:
856 case CHIP_MULLINS:
857 case CHIP_ICELAND:
858 case CHIP_CARRIZO:
859 case CHIP_STONEY:
860 device->gs_table_depth = 16;
861 return;
862 case CHIP_TAHITI:
863 case CHIP_PITCAIRN:
864 case CHIP_VERDE:
865 case CHIP_BONAIRE:
866 case CHIP_HAWAII:
867 case CHIP_TONGA:
868 case CHIP_FIJI:
869 case CHIP_POLARIS10:
870 case CHIP_POLARIS11:
871 device->gs_table_depth = 32;
872 return;
873 default:
874 unreachable("unknown GPU");
875 }
876 }
877
878 VkResult radv_CreateDevice(
879 VkPhysicalDevice physicalDevice,
880 const VkDeviceCreateInfo* pCreateInfo,
881 const VkAllocationCallbacks* pAllocator,
882 VkDevice* pDevice)
883 {
884 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
885 VkResult result;
886 struct radv_device *device;
887
888 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
889 if (!is_extension_enabled(physical_device->extensions.ext_array,
890 physical_device->extensions.num_ext,
891 pCreateInfo->ppEnabledExtensionNames[i]))
892 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
893 }
894
895 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
896 sizeof(*device), 8,
897 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
898 if (!device)
899 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
900
901 memset(device, 0, sizeof(*device));
902
903 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
904 device->instance = physical_device->instance;
905 device->physical_device = physical_device;
906
907 device->debug_flags = device->instance->debug_flags;
908
909 device->ws = physical_device->ws;
910 if (pAllocator)
911 device->alloc = *pAllocator;
912 else
913 device->alloc = physical_device->instance->alloc;
914
915 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
916 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
917 uint32_t qfi = queue_create->queueFamilyIndex;
918
919 device->queues[qfi] = vk_alloc(&device->alloc,
920 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
921 if (!device->queues[qfi]) {
922 result = VK_ERROR_OUT_OF_HOST_MEMORY;
923 goto fail;
924 }
925
926 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
927
928 device->queue_count[qfi] = queue_create->queueCount;
929
930 for (unsigned q = 0; q < queue_create->queueCount; q++) {
931 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
932 if (result != VK_SUCCESS)
933 goto fail;
934 }
935 }
936
937 #if HAVE_LLVM < 0x0400
938 device->llvm_supports_spill = false;
939 #else
940 device->llvm_supports_spill = true;
941 #endif
942
943 /* The maximum number of scratch waves. Scratch space isn't divided
944 * evenly between CUs. The number is only a function of the number of CUs.
945 * We can decrease the constant to decrease the scratch buffer size.
946 *
947 * sctx->scratch_waves must be >= the maximum posible size of
948 * 1 threadgroup, so that the hw doesn't hang from being unable
949 * to start any.
950 *
951 * The recommended value is 4 per CU at most. Higher numbers don't
952 * bring much benefit, but they still occupy chip resources (think
953 * async compute). I've seen ~2% performance difference between 4 and 32.
954 */
955 uint32_t max_threads_per_block = 2048;
956 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
957 max_threads_per_block / 64);
958
959 radv_device_init_gs_info(device);
960
961 result = radv_device_init_meta(device);
962 if (result != VK_SUCCESS)
963 goto fail;
964
965 radv_device_init_msaa(device);
966
967 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
968 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
969 switch (family) {
970 case RADV_QUEUE_GENERAL:
971 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
972 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
973 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
974 break;
975 case RADV_QUEUE_COMPUTE:
976 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
977 radeon_emit(device->empty_cs[family], 0);
978 break;
979 }
980 device->ws->cs_finalize(device->empty_cs[family]);
981
982 device->flush_cs[family] = device->ws->cs_create(device->ws, family);
983 switch (family) {
984 case RADV_QUEUE_GENERAL:
985 case RADV_QUEUE_COMPUTE:
986 si_cs_emit_cache_flush(device->flush_cs[family],
987 device->physical_device->rad_info.chip_class,
988 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
989 RADV_CMD_FLAG_INV_ICACHE |
990 RADV_CMD_FLAG_INV_SMEM_L1 |
991 RADV_CMD_FLAG_INV_VMEM_L1 |
992 RADV_CMD_FLAG_INV_GLOBAL_L2);
993 break;
994 }
995 device->ws->cs_finalize(device->flush_cs[family]);
996 }
997
998 if (getenv("RADV_TRACE_FILE")) {
999 device->trace_bo = device->ws->buffer_create(device->ws, 4096, 8,
1000 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
1001 if (!device->trace_bo)
1002 goto fail;
1003
1004 device->trace_id_ptr = device->ws->buffer_map(device->trace_bo);
1005 if (!device->trace_id_ptr)
1006 goto fail;
1007 }
1008
1009 if (device->physical_device->rad_info.chip_class >= CIK)
1010 cik_create_gfx_config(device);
1011
1012 *pDevice = radv_device_to_handle(device);
1013 return VK_SUCCESS;
1014
1015 fail:
1016 if (device->trace_bo)
1017 device->ws->buffer_destroy(device->trace_bo);
1018
1019 if (device->gfx_init)
1020 device->ws->buffer_destroy(device->gfx_init);
1021
1022 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1023 for (unsigned q = 0; q < device->queue_count[i]; q++)
1024 radv_queue_finish(&device->queues[i][q]);
1025 if (device->queue_count[i])
1026 vk_free(&device->alloc, device->queues[i]);
1027 }
1028
1029 vk_free(&device->alloc, device);
1030 return result;
1031 }
1032
1033 void radv_DestroyDevice(
1034 VkDevice _device,
1035 const VkAllocationCallbacks* pAllocator)
1036 {
1037 RADV_FROM_HANDLE(radv_device, device, _device);
1038
1039 if (!device)
1040 return;
1041
1042 if (device->trace_bo)
1043 device->ws->buffer_destroy(device->trace_bo);
1044
1045 if (device->gfx_init)
1046 device->ws->buffer_destroy(device->gfx_init);
1047
1048 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1049 for (unsigned q = 0; q < device->queue_count[i]; q++)
1050 radv_queue_finish(&device->queues[i][q]);
1051 if (device->queue_count[i])
1052 vk_free(&device->alloc, device->queues[i]);
1053 if (device->empty_cs[i])
1054 device->ws->cs_destroy(device->empty_cs[i]);
1055 if (device->flush_cs[i])
1056 device->ws->cs_destroy(device->flush_cs[i]);
1057 }
1058 radv_device_finish_meta(device);
1059
1060 vk_free(&device->alloc, device);
1061 }
1062
1063 VkResult radv_EnumerateInstanceExtensionProperties(
1064 const char* pLayerName,
1065 uint32_t* pPropertyCount,
1066 VkExtensionProperties* pProperties)
1067 {
1068 if (pProperties == NULL) {
1069 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1070 return VK_SUCCESS;
1071 }
1072
1073 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1074 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1075
1076 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1077 return VK_INCOMPLETE;
1078
1079 return VK_SUCCESS;
1080 }
1081
1082 VkResult radv_EnumerateDeviceExtensionProperties(
1083 VkPhysicalDevice physicalDevice,
1084 const char* pLayerName,
1085 uint32_t* pPropertyCount,
1086 VkExtensionProperties* pProperties)
1087 {
1088 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1089
1090 if (pProperties == NULL) {
1091 *pPropertyCount = pdevice->extensions.num_ext;
1092 return VK_SUCCESS;
1093 }
1094
1095 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1096 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1097
1098 if (*pPropertyCount < pdevice->extensions.num_ext)
1099 return VK_INCOMPLETE;
1100
1101 return VK_SUCCESS;
1102 }
1103
1104 VkResult radv_EnumerateInstanceLayerProperties(
1105 uint32_t* pPropertyCount,
1106 VkLayerProperties* pProperties)
1107 {
1108 if (pProperties == NULL) {
1109 *pPropertyCount = 0;
1110 return VK_SUCCESS;
1111 }
1112
1113 /* None supported at this time */
1114 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1115 }
1116
1117 VkResult radv_EnumerateDeviceLayerProperties(
1118 VkPhysicalDevice physicalDevice,
1119 uint32_t* pPropertyCount,
1120 VkLayerProperties* pProperties)
1121 {
1122 if (pProperties == NULL) {
1123 *pPropertyCount = 0;
1124 return VK_SUCCESS;
1125 }
1126
1127 /* None supported at this time */
1128 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1129 }
1130
1131 void radv_GetDeviceQueue(
1132 VkDevice _device,
1133 uint32_t queueFamilyIndex,
1134 uint32_t queueIndex,
1135 VkQueue* pQueue)
1136 {
1137 RADV_FROM_HANDLE(radv_device, device, _device);
1138
1139 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1140 }
1141
1142 static void radv_dump_trace(struct radv_device *device,
1143 struct radeon_winsys_cs *cs)
1144 {
1145 const char *filename = getenv("RADV_TRACE_FILE");
1146 FILE *f = fopen(filename, "w");
1147 if (!f) {
1148 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
1149 return;
1150 }
1151
1152 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
1153 device->ws->cs_dump(cs, f, *device->trace_id_ptr);
1154 fclose(f);
1155 }
1156
1157 static void
1158 fill_geom_rings(struct radv_queue *queue,
1159 uint32_t *map,
1160 uint32_t esgs_ring_size,
1161 struct radeon_winsys_bo *esgs_ring_bo,
1162 uint32_t gsvs_ring_size,
1163 struct radeon_winsys_bo *gsvs_ring_bo)
1164 {
1165 uint64_t esgs_va = 0, gsvs_va = 0;
1166 uint32_t *desc = &map[4];
1167
1168 if (esgs_ring_bo)
1169 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1170 if (gsvs_ring_bo)
1171 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1172
1173 /* stride 0, num records - size, add tid, swizzle, elsize4,
1174 index stride 64 */
1175 desc[0] = esgs_va;
1176 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1177 S_008F04_STRIDE(0) |
1178 S_008F04_SWIZZLE_ENABLE(true);
1179 desc[2] = esgs_ring_size;
1180 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1181 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1182 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1183 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1184 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1185 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1186 S_008F0C_ELEMENT_SIZE(1) |
1187 S_008F0C_INDEX_STRIDE(3) |
1188 S_008F0C_ADD_TID_ENABLE(true);
1189
1190 desc += 4;
1191 /* GS entry for ES->GS ring */
1192 /* stride 0, num records - size, elsize0,
1193 index stride 0 */
1194 desc[0] = esgs_va;
1195 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1196 S_008F04_STRIDE(0) |
1197 S_008F04_SWIZZLE_ENABLE(false);
1198 desc[2] = esgs_ring_size;
1199 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1200 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1201 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1202 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1203 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1204 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1205 S_008F0C_ELEMENT_SIZE(0) |
1206 S_008F0C_INDEX_STRIDE(0) |
1207 S_008F0C_ADD_TID_ENABLE(false);
1208
1209 desc += 4;
1210 /* VS entry for GS->VS ring */
1211 /* stride 0, num records - size, elsize0,
1212 index stride 0 */
1213 desc[0] = gsvs_va;
1214 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1215 S_008F04_STRIDE(0) |
1216 S_008F04_SWIZZLE_ENABLE(false);
1217 desc[2] = gsvs_ring_size;
1218 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1219 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1220 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1221 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1222 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1223 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1224 S_008F0C_ELEMENT_SIZE(0) |
1225 S_008F0C_INDEX_STRIDE(0) |
1226 S_008F0C_ADD_TID_ENABLE(false);
1227 desc += 4;
1228
1229 /* stride gsvs_itemsize, num records 64
1230 elsize 4, index stride 16 */
1231 /* shader will patch stride and desc[2] */
1232 desc[0] = gsvs_va;
1233 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1234 S_008F04_STRIDE(0) |
1235 S_008F04_SWIZZLE_ENABLE(true);
1236 desc[2] = 0;
1237 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1238 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1239 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1240 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1241 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1242 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1243 S_008F0C_ELEMENT_SIZE(1) |
1244 S_008F0C_INDEX_STRIDE(1) |
1245 S_008F0C_ADD_TID_ENABLE(true);
1246 }
1247
1248 static VkResult
1249 radv_get_preamble_cs(struct radv_queue *queue,
1250 uint32_t scratch_size,
1251 uint32_t compute_scratch_size,
1252 uint32_t esgs_ring_size,
1253 uint32_t gsvs_ring_size,
1254 struct radeon_winsys_cs **initial_preamble_cs,
1255 struct radeon_winsys_cs **continue_preamble_cs)
1256 {
1257 struct radeon_winsys_bo *scratch_bo = NULL;
1258 struct radeon_winsys_bo *descriptor_bo = NULL;
1259 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1260 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1261 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1262 struct radeon_winsys_cs *dest_cs[2] = {0};
1263
1264 if (scratch_size <= queue->scratch_size &&
1265 compute_scratch_size <= queue->compute_scratch_size &&
1266 esgs_ring_size <= queue->esgs_ring_size &&
1267 gsvs_ring_size <= queue->gsvs_ring_size &&
1268 queue->initial_preamble_cs) {
1269 *initial_preamble_cs = queue->initial_preamble_cs;
1270 *continue_preamble_cs = queue->continue_preamble_cs;
1271 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1272 *continue_preamble_cs = NULL;
1273 return VK_SUCCESS;
1274 }
1275
1276 if (scratch_size > queue->scratch_size) {
1277 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1278 scratch_size,
1279 4096,
1280 RADEON_DOMAIN_VRAM,
1281 RADEON_FLAG_NO_CPU_ACCESS);
1282 if (!scratch_bo)
1283 goto fail;
1284 } else
1285 scratch_bo = queue->scratch_bo;
1286
1287 if (compute_scratch_size > queue->compute_scratch_size) {
1288 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1289 compute_scratch_size,
1290 4096,
1291 RADEON_DOMAIN_VRAM,
1292 RADEON_FLAG_NO_CPU_ACCESS);
1293 if (!compute_scratch_bo)
1294 goto fail;
1295
1296 } else
1297 compute_scratch_bo = queue->compute_scratch_bo;
1298
1299 if (esgs_ring_size > queue->esgs_ring_size) {
1300 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1301 esgs_ring_size,
1302 4096,
1303 RADEON_DOMAIN_VRAM,
1304 RADEON_FLAG_NO_CPU_ACCESS);
1305 if (!esgs_ring_bo)
1306 goto fail;
1307 } else {
1308 esgs_ring_bo = queue->esgs_ring_bo;
1309 esgs_ring_size = queue->esgs_ring_size;
1310 }
1311
1312 if (gsvs_ring_size > queue->gsvs_ring_size) {
1313 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1314 gsvs_ring_size,
1315 4096,
1316 RADEON_DOMAIN_VRAM,
1317 RADEON_FLAG_NO_CPU_ACCESS);
1318 if (!gsvs_ring_bo)
1319 goto fail;
1320 } else {
1321 gsvs_ring_bo = queue->gsvs_ring_bo;
1322 gsvs_ring_size = queue->gsvs_ring_size;
1323 }
1324
1325 if (scratch_bo != queue->scratch_bo ||
1326 esgs_ring_bo != queue->esgs_ring_bo ||
1327 gsvs_ring_bo != queue->gsvs_ring_bo) {
1328 uint32_t size = 0;
1329 if (gsvs_ring_bo || esgs_ring_bo)
1330 size = 80; /* 2 dword + 2 padding + 4 dword * 4 */
1331 else if (scratch_bo)
1332 size = 8; /* 2 dword */
1333
1334 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1335 size,
1336 4096,
1337 RADEON_DOMAIN_VRAM,
1338 RADEON_FLAG_CPU_ACCESS);
1339 if (!descriptor_bo)
1340 goto fail;
1341 } else
1342 descriptor_bo = queue->descriptor_bo;
1343
1344 for(int i = 0; i < 2; ++i) {
1345 struct radeon_winsys_cs *cs = NULL;
1346 cs = queue->device->ws->cs_create(queue->device->ws,
1347 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1348 if (!cs)
1349 goto fail;
1350
1351 dest_cs[i] = cs;
1352
1353 if (scratch_bo)
1354 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1355
1356 if (esgs_ring_bo)
1357 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1358
1359 if (gsvs_ring_bo)
1360 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1361
1362 if (descriptor_bo)
1363 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1364
1365 if (descriptor_bo != queue->descriptor_bo) {
1366 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1367
1368 if (scratch_bo) {
1369 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1370 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1371 S_008F04_SWIZZLE_ENABLE(1);
1372 map[0] = scratch_va;
1373 map[1] = rsrc1;
1374 }
1375
1376 if (esgs_ring_bo || gsvs_ring_bo)
1377 fill_geom_rings(queue, map, esgs_ring_size, esgs_ring_bo, gsvs_ring_size, gsvs_ring_bo);
1378
1379 queue->device->ws->buffer_unmap(descriptor_bo);
1380 }
1381
1382 if (esgs_ring_bo || gsvs_ring_bo) {
1383 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1384 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1385 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1386 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1387
1388 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1389 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1390 radeon_emit(cs, esgs_ring_size >> 8);
1391 radeon_emit(cs, gsvs_ring_size >> 8);
1392 } else {
1393 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1394 radeon_emit(cs, esgs_ring_size >> 8);
1395 radeon_emit(cs, gsvs_ring_size >> 8);
1396 }
1397 }
1398
1399 if (descriptor_bo) {
1400 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1401 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1402 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1403 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1404 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1405 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1406
1407 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1408
1409 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1410 radeon_set_sh_reg_seq(cs, regs[i], 2);
1411 radeon_emit(cs, va);
1412 radeon_emit(cs, va >> 32);
1413 }
1414 }
1415
1416 if (compute_scratch_bo) {
1417 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1418 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1419 S_008F04_SWIZZLE_ENABLE(1);
1420
1421 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1422
1423 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1424 radeon_emit(cs, scratch_va);
1425 radeon_emit(cs, rsrc1);
1426 }
1427
1428 if (!i) {
1429 si_cs_emit_cache_flush(cs,
1430 queue->device->physical_device->rad_info.chip_class,
1431 queue->queue_family_index == RING_COMPUTE &&
1432 queue->device->physical_device->rad_info.chip_class >= CIK,
1433 RADV_CMD_FLAG_INV_ICACHE |
1434 RADV_CMD_FLAG_INV_SMEM_L1 |
1435 RADV_CMD_FLAG_INV_VMEM_L1 |
1436 RADV_CMD_FLAG_INV_GLOBAL_L2);
1437 }
1438
1439 if (!queue->device->ws->cs_finalize(cs))
1440 goto fail;
1441 }
1442
1443 if (queue->initial_preamble_cs)
1444 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1445
1446 if (queue->continue_preamble_cs)
1447 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1448
1449 queue->initial_preamble_cs = dest_cs[0];
1450 queue->continue_preamble_cs = dest_cs[1];
1451
1452 if (scratch_bo != queue->scratch_bo) {
1453 if (queue->scratch_bo)
1454 queue->device->ws->buffer_destroy(queue->scratch_bo);
1455 queue->scratch_bo = scratch_bo;
1456 queue->scratch_size = scratch_size;
1457 }
1458
1459 if (compute_scratch_bo != queue->compute_scratch_bo) {
1460 if (queue->compute_scratch_bo)
1461 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1462 queue->compute_scratch_bo = compute_scratch_bo;
1463 queue->compute_scratch_size = compute_scratch_size;
1464 }
1465
1466 if (esgs_ring_bo != queue->esgs_ring_bo) {
1467 if (queue->esgs_ring_bo)
1468 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1469 queue->esgs_ring_bo = esgs_ring_bo;
1470 queue->esgs_ring_size = esgs_ring_size;
1471 }
1472
1473 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1474 if (queue->gsvs_ring_bo)
1475 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1476 queue->gsvs_ring_bo = gsvs_ring_bo;
1477 queue->gsvs_ring_size = gsvs_ring_size;
1478 }
1479
1480 if (descriptor_bo != queue->descriptor_bo) {
1481 if (queue->descriptor_bo)
1482 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1483
1484 queue->descriptor_bo = descriptor_bo;
1485 }
1486
1487 *initial_preamble_cs = queue->initial_preamble_cs;
1488 *continue_preamble_cs = queue->continue_preamble_cs;
1489 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1490 *continue_preamble_cs = NULL;
1491 return VK_SUCCESS;
1492 fail:
1493 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1494 if (dest_cs[i])
1495 queue->device->ws->cs_destroy(dest_cs[i]);
1496 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1497 queue->device->ws->buffer_destroy(descriptor_bo);
1498 if (scratch_bo && scratch_bo != queue->scratch_bo)
1499 queue->device->ws->buffer_destroy(scratch_bo);
1500 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1501 queue->device->ws->buffer_destroy(compute_scratch_bo);
1502 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1503 queue->device->ws->buffer_destroy(esgs_ring_bo);
1504 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1505 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1506 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1507 }
1508
1509 VkResult radv_QueueSubmit(
1510 VkQueue _queue,
1511 uint32_t submitCount,
1512 const VkSubmitInfo* pSubmits,
1513 VkFence _fence)
1514 {
1515 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1516 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1517 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1518 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1519 int ret;
1520 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1521 uint32_t scratch_size = 0;
1522 uint32_t compute_scratch_size = 0;
1523 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1524 struct radeon_winsys_cs *initial_preamble_cs = NULL, *continue_preamble_cs = NULL;
1525 VkResult result;
1526 bool fence_emitted = false;
1527
1528 /* Do this first so failing to allocate scratch buffers can't result in
1529 * partially executed submissions. */
1530 for (uint32_t i = 0; i < submitCount; i++) {
1531 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1532 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1533 pSubmits[i].pCommandBuffers[j]);
1534
1535 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
1536 compute_scratch_size = MAX2(compute_scratch_size,
1537 cmd_buffer->compute_scratch_size_needed);
1538 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
1539 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
1540 }
1541 }
1542
1543 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
1544 esgs_ring_size, gsvs_ring_size,
1545 &initial_preamble_cs, &continue_preamble_cs);
1546 if (result != VK_SUCCESS)
1547 return result;
1548
1549 for (uint32_t i = 0; i < submitCount; i++) {
1550 struct radeon_winsys_cs **cs_array;
1551 bool has_flush = !submitCount;
1552 bool can_patch = !has_flush;
1553 uint32_t advance;
1554
1555 if (!pSubmits[i].commandBufferCount) {
1556 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
1557 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1558 &queue->device->empty_cs[queue->queue_family_index],
1559 1, NULL, NULL,
1560 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1561 pSubmits[i].waitSemaphoreCount,
1562 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1563 pSubmits[i].signalSemaphoreCount,
1564 false, base_fence);
1565 if (ret) {
1566 radv_loge("failed to submit CS %d\n", i);
1567 abort();
1568 }
1569 fence_emitted = true;
1570 }
1571 continue;
1572 }
1573
1574 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
1575 (pSubmits[i].commandBufferCount + has_flush));
1576
1577 if(has_flush)
1578 cs_array[0] = queue->device->flush_cs[queue->queue_family_index];
1579
1580 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1581 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1582 pSubmits[i].pCommandBuffers[j]);
1583 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1584
1585 cs_array[j + has_flush] = cmd_buffer->cs;
1586 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
1587 can_patch = false;
1588 }
1589
1590 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount + has_flush; j += advance) {
1591 advance = MIN2(max_cs_submission,
1592 pSubmits[i].commandBufferCount + has_flush - j);
1593 bool b = j == 0;
1594 bool e = j + advance == pSubmits[i].commandBufferCount + has_flush;
1595
1596 if (queue->device->trace_bo)
1597 *queue->device->trace_id_ptr = 0;
1598
1599 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
1600 advance, initial_preamble_cs, continue_preamble_cs,
1601 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1602 b ? pSubmits[i].waitSemaphoreCount : 0,
1603 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1604 e ? pSubmits[i].signalSemaphoreCount : 0,
1605 can_patch, base_fence);
1606
1607 if (ret) {
1608 radv_loge("failed to submit CS %d\n", i);
1609 abort();
1610 }
1611 fence_emitted = true;
1612 if (queue->device->trace_bo) {
1613 bool success = queue->device->ws->ctx_wait_idle(
1614 queue->hw_ctx,
1615 radv_queue_family_to_ring(
1616 queue->queue_family_index),
1617 queue->queue_idx);
1618
1619 if (!success) { /* Hang */
1620 radv_dump_trace(queue->device, cs_array[j]);
1621 abort();
1622 }
1623 }
1624 }
1625 free(cs_array);
1626 }
1627
1628 if (fence) {
1629 if (!fence_emitted)
1630 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1631 &queue->device->empty_cs[queue->queue_family_index],
1632 1, NULL, NULL, NULL, 0, NULL, 0,
1633 false, base_fence);
1634
1635 fence->submitted = true;
1636 }
1637
1638 return VK_SUCCESS;
1639 }
1640
1641 VkResult radv_QueueWaitIdle(
1642 VkQueue _queue)
1643 {
1644 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1645
1646 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
1647 radv_queue_family_to_ring(queue->queue_family_index),
1648 queue->queue_idx);
1649 return VK_SUCCESS;
1650 }
1651
1652 VkResult radv_DeviceWaitIdle(
1653 VkDevice _device)
1654 {
1655 RADV_FROM_HANDLE(radv_device, device, _device);
1656
1657 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1658 for (unsigned q = 0; q < device->queue_count[i]; q++) {
1659 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
1660 }
1661 }
1662 return VK_SUCCESS;
1663 }
1664
1665 PFN_vkVoidFunction radv_GetInstanceProcAddr(
1666 VkInstance instance,
1667 const char* pName)
1668 {
1669 return radv_lookup_entrypoint(pName);
1670 }
1671
1672 /* The loader wants us to expose a second GetInstanceProcAddr function
1673 * to work around certain LD_PRELOAD issues seen in apps.
1674 */
1675 PUBLIC
1676 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1677 VkInstance instance,
1678 const char* pName);
1679
1680 PUBLIC
1681 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1682 VkInstance instance,
1683 const char* pName)
1684 {
1685 return radv_GetInstanceProcAddr(instance, pName);
1686 }
1687
1688 PFN_vkVoidFunction radv_GetDeviceProcAddr(
1689 VkDevice device,
1690 const char* pName)
1691 {
1692 return radv_lookup_entrypoint(pName);
1693 }
1694
1695 bool radv_get_memory_fd(struct radv_device *device,
1696 struct radv_device_memory *memory,
1697 int *pFD)
1698 {
1699 struct radeon_bo_metadata metadata;
1700
1701 if (memory->image) {
1702 radv_init_metadata(device, memory->image, &metadata);
1703 device->ws->buffer_set_metadata(memory->bo, &metadata);
1704 }
1705
1706 return device->ws->buffer_get_fd(device->ws, memory->bo,
1707 pFD);
1708 }
1709
1710 VkResult radv_AllocateMemory(
1711 VkDevice _device,
1712 const VkMemoryAllocateInfo* pAllocateInfo,
1713 const VkAllocationCallbacks* pAllocator,
1714 VkDeviceMemory* pMem)
1715 {
1716 RADV_FROM_HANDLE(radv_device, device, _device);
1717 struct radv_device_memory *mem;
1718 VkResult result;
1719 enum radeon_bo_domain domain;
1720 uint32_t flags = 0;
1721 const VkDedicatedAllocationMemoryAllocateInfoNV *dedicate_info = NULL;
1722 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
1723
1724 if (pAllocateInfo->allocationSize == 0) {
1725 /* Apparently, this is allowed */
1726 *pMem = VK_NULL_HANDLE;
1727 return VK_SUCCESS;
1728 }
1729
1730 vk_foreach_struct(ext, pAllocateInfo->pNext) {
1731 switch (ext->sType) {
1732 case VK_STRUCTURE_TYPE_DEDICATED_ALLOCATION_MEMORY_ALLOCATE_INFO_NV:
1733 dedicate_info = (const VkDedicatedAllocationMemoryAllocateInfoNV *)ext;
1734 break;
1735 default:
1736 break;
1737 }
1738 }
1739
1740 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
1741 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1742 if (mem == NULL)
1743 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1744
1745 if (dedicate_info) {
1746 mem->image = radv_image_from_handle(dedicate_info->image);
1747 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
1748 } else {
1749 mem->image = NULL;
1750 mem->buffer = NULL;
1751 }
1752
1753 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
1754 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
1755 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
1756 domain = RADEON_DOMAIN_GTT;
1757 else
1758 domain = RADEON_DOMAIN_VRAM;
1759
1760 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
1761 flags |= RADEON_FLAG_NO_CPU_ACCESS;
1762 else
1763 flags |= RADEON_FLAG_CPU_ACCESS;
1764
1765 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
1766 flags |= RADEON_FLAG_GTT_WC;
1767
1768 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 65536,
1769 domain, flags);
1770
1771 if (!mem->bo) {
1772 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
1773 goto fail;
1774 }
1775 mem->type_index = pAllocateInfo->memoryTypeIndex;
1776
1777 *pMem = radv_device_memory_to_handle(mem);
1778
1779 return VK_SUCCESS;
1780
1781 fail:
1782 vk_free2(&device->alloc, pAllocator, mem);
1783
1784 return result;
1785 }
1786
1787 void radv_FreeMemory(
1788 VkDevice _device,
1789 VkDeviceMemory _mem,
1790 const VkAllocationCallbacks* pAllocator)
1791 {
1792 RADV_FROM_HANDLE(radv_device, device, _device);
1793 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
1794
1795 if (mem == NULL)
1796 return;
1797
1798 device->ws->buffer_destroy(mem->bo);
1799 mem->bo = NULL;
1800
1801 vk_free2(&device->alloc, pAllocator, mem);
1802 }
1803
1804 VkResult radv_MapMemory(
1805 VkDevice _device,
1806 VkDeviceMemory _memory,
1807 VkDeviceSize offset,
1808 VkDeviceSize size,
1809 VkMemoryMapFlags flags,
1810 void** ppData)
1811 {
1812 RADV_FROM_HANDLE(radv_device, device, _device);
1813 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1814
1815 if (mem == NULL) {
1816 *ppData = NULL;
1817 return VK_SUCCESS;
1818 }
1819
1820 *ppData = device->ws->buffer_map(mem->bo);
1821 if (*ppData) {
1822 *ppData += offset;
1823 return VK_SUCCESS;
1824 }
1825
1826 return VK_ERROR_MEMORY_MAP_FAILED;
1827 }
1828
1829 void radv_UnmapMemory(
1830 VkDevice _device,
1831 VkDeviceMemory _memory)
1832 {
1833 RADV_FROM_HANDLE(radv_device, device, _device);
1834 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1835
1836 if (mem == NULL)
1837 return;
1838
1839 device->ws->buffer_unmap(mem->bo);
1840 }
1841
1842 VkResult radv_FlushMappedMemoryRanges(
1843 VkDevice _device,
1844 uint32_t memoryRangeCount,
1845 const VkMappedMemoryRange* pMemoryRanges)
1846 {
1847 return VK_SUCCESS;
1848 }
1849
1850 VkResult radv_InvalidateMappedMemoryRanges(
1851 VkDevice _device,
1852 uint32_t memoryRangeCount,
1853 const VkMappedMemoryRange* pMemoryRanges)
1854 {
1855 return VK_SUCCESS;
1856 }
1857
1858 void radv_GetBufferMemoryRequirements(
1859 VkDevice device,
1860 VkBuffer _buffer,
1861 VkMemoryRequirements* pMemoryRequirements)
1862 {
1863 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1864
1865 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1866
1867 pMemoryRequirements->size = buffer->size;
1868 pMemoryRequirements->alignment = 16;
1869 }
1870
1871 void radv_GetImageMemoryRequirements(
1872 VkDevice device,
1873 VkImage _image,
1874 VkMemoryRequirements* pMemoryRequirements)
1875 {
1876 RADV_FROM_HANDLE(radv_image, image, _image);
1877
1878 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1879
1880 pMemoryRequirements->size = image->size;
1881 pMemoryRequirements->alignment = image->alignment;
1882 }
1883
1884 void radv_GetImageSparseMemoryRequirements(
1885 VkDevice device,
1886 VkImage image,
1887 uint32_t* pSparseMemoryRequirementCount,
1888 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
1889 {
1890 stub();
1891 }
1892
1893 void radv_GetDeviceMemoryCommitment(
1894 VkDevice device,
1895 VkDeviceMemory memory,
1896 VkDeviceSize* pCommittedMemoryInBytes)
1897 {
1898 *pCommittedMemoryInBytes = 0;
1899 }
1900
1901 VkResult radv_BindBufferMemory(
1902 VkDevice device,
1903 VkBuffer _buffer,
1904 VkDeviceMemory _memory,
1905 VkDeviceSize memoryOffset)
1906 {
1907 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1908 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1909
1910 if (mem) {
1911 buffer->bo = mem->bo;
1912 buffer->offset = memoryOffset;
1913 } else {
1914 buffer->bo = NULL;
1915 buffer->offset = 0;
1916 }
1917
1918 return VK_SUCCESS;
1919 }
1920
1921 VkResult radv_BindImageMemory(
1922 VkDevice device,
1923 VkImage _image,
1924 VkDeviceMemory _memory,
1925 VkDeviceSize memoryOffset)
1926 {
1927 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1928 RADV_FROM_HANDLE(radv_image, image, _image);
1929
1930 if (mem) {
1931 image->bo = mem->bo;
1932 image->offset = memoryOffset;
1933 } else {
1934 image->bo = NULL;
1935 image->offset = 0;
1936 }
1937
1938 return VK_SUCCESS;
1939 }
1940
1941 VkResult radv_QueueBindSparse(
1942 VkQueue queue,
1943 uint32_t bindInfoCount,
1944 const VkBindSparseInfo* pBindInfo,
1945 VkFence fence)
1946 {
1947 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER);
1948 }
1949
1950 VkResult radv_CreateFence(
1951 VkDevice _device,
1952 const VkFenceCreateInfo* pCreateInfo,
1953 const VkAllocationCallbacks* pAllocator,
1954 VkFence* pFence)
1955 {
1956 RADV_FROM_HANDLE(radv_device, device, _device);
1957 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
1958 sizeof(*fence), 8,
1959 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1960
1961 if (!fence)
1962 return VK_ERROR_OUT_OF_HOST_MEMORY;
1963
1964 memset(fence, 0, sizeof(*fence));
1965 fence->submitted = false;
1966 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
1967 fence->fence = device->ws->create_fence();
1968 if (!fence->fence) {
1969 vk_free2(&device->alloc, pAllocator, fence);
1970 return VK_ERROR_OUT_OF_HOST_MEMORY;
1971 }
1972
1973 *pFence = radv_fence_to_handle(fence);
1974
1975 return VK_SUCCESS;
1976 }
1977
1978 void radv_DestroyFence(
1979 VkDevice _device,
1980 VkFence _fence,
1981 const VkAllocationCallbacks* pAllocator)
1982 {
1983 RADV_FROM_HANDLE(radv_device, device, _device);
1984 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1985
1986 if (!fence)
1987 return;
1988 device->ws->destroy_fence(fence->fence);
1989 vk_free2(&device->alloc, pAllocator, fence);
1990 }
1991
1992 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
1993 {
1994 uint64_t current_time;
1995 struct timespec tv;
1996
1997 clock_gettime(CLOCK_MONOTONIC, &tv);
1998 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
1999
2000 timeout = MIN2(UINT64_MAX - current_time, timeout);
2001
2002 return current_time + timeout;
2003 }
2004
2005 VkResult radv_WaitForFences(
2006 VkDevice _device,
2007 uint32_t fenceCount,
2008 const VkFence* pFences,
2009 VkBool32 waitAll,
2010 uint64_t timeout)
2011 {
2012 RADV_FROM_HANDLE(radv_device, device, _device);
2013 timeout = radv_get_absolute_timeout(timeout);
2014
2015 if (!waitAll && fenceCount > 1) {
2016 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2017 }
2018
2019 for (uint32_t i = 0; i < fenceCount; ++i) {
2020 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2021 bool expired = false;
2022
2023 if (fence->signalled)
2024 continue;
2025
2026 if (!fence->submitted)
2027 return VK_TIMEOUT;
2028
2029 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2030 if (!expired)
2031 return VK_TIMEOUT;
2032
2033 fence->signalled = true;
2034 }
2035
2036 return VK_SUCCESS;
2037 }
2038
2039 VkResult radv_ResetFences(VkDevice device,
2040 uint32_t fenceCount,
2041 const VkFence *pFences)
2042 {
2043 for (unsigned i = 0; i < fenceCount; ++i) {
2044 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2045 fence->submitted = fence->signalled = false;
2046 }
2047
2048 return VK_SUCCESS;
2049 }
2050
2051 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2052 {
2053 RADV_FROM_HANDLE(radv_device, device, _device);
2054 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2055
2056 if (fence->signalled)
2057 return VK_SUCCESS;
2058 if (!fence->submitted)
2059 return VK_NOT_READY;
2060
2061 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2062 return VK_NOT_READY;
2063
2064 return VK_SUCCESS;
2065 }
2066
2067
2068 // Queue semaphore functions
2069
2070 VkResult radv_CreateSemaphore(
2071 VkDevice _device,
2072 const VkSemaphoreCreateInfo* pCreateInfo,
2073 const VkAllocationCallbacks* pAllocator,
2074 VkSemaphore* pSemaphore)
2075 {
2076 RADV_FROM_HANDLE(radv_device, device, _device);
2077 struct radeon_winsys_sem *sem;
2078
2079 sem = device->ws->create_sem(device->ws);
2080 if (!sem)
2081 return VK_ERROR_OUT_OF_HOST_MEMORY;
2082
2083 *pSemaphore = radeon_winsys_sem_to_handle(sem);
2084 return VK_SUCCESS;
2085 }
2086
2087 void radv_DestroySemaphore(
2088 VkDevice _device,
2089 VkSemaphore _semaphore,
2090 const VkAllocationCallbacks* pAllocator)
2091 {
2092 RADV_FROM_HANDLE(radv_device, device, _device);
2093 RADV_FROM_HANDLE(radeon_winsys_sem, sem, _semaphore);
2094 if (!_semaphore)
2095 return;
2096
2097 device->ws->destroy_sem(sem);
2098 }
2099
2100 VkResult radv_CreateEvent(
2101 VkDevice _device,
2102 const VkEventCreateInfo* pCreateInfo,
2103 const VkAllocationCallbacks* pAllocator,
2104 VkEvent* pEvent)
2105 {
2106 RADV_FROM_HANDLE(radv_device, device, _device);
2107 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2108 sizeof(*event), 8,
2109 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2110
2111 if (!event)
2112 return VK_ERROR_OUT_OF_HOST_MEMORY;
2113
2114 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2115 RADEON_DOMAIN_GTT,
2116 RADEON_FLAG_CPU_ACCESS);
2117 if (!event->bo) {
2118 vk_free2(&device->alloc, pAllocator, event);
2119 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2120 }
2121
2122 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2123
2124 *pEvent = radv_event_to_handle(event);
2125
2126 return VK_SUCCESS;
2127 }
2128
2129 void radv_DestroyEvent(
2130 VkDevice _device,
2131 VkEvent _event,
2132 const VkAllocationCallbacks* pAllocator)
2133 {
2134 RADV_FROM_HANDLE(radv_device, device, _device);
2135 RADV_FROM_HANDLE(radv_event, event, _event);
2136
2137 if (!event)
2138 return;
2139 device->ws->buffer_destroy(event->bo);
2140 vk_free2(&device->alloc, pAllocator, event);
2141 }
2142
2143 VkResult radv_GetEventStatus(
2144 VkDevice _device,
2145 VkEvent _event)
2146 {
2147 RADV_FROM_HANDLE(radv_event, event, _event);
2148
2149 if (*event->map == 1)
2150 return VK_EVENT_SET;
2151 return VK_EVENT_RESET;
2152 }
2153
2154 VkResult radv_SetEvent(
2155 VkDevice _device,
2156 VkEvent _event)
2157 {
2158 RADV_FROM_HANDLE(radv_event, event, _event);
2159 *event->map = 1;
2160
2161 return VK_SUCCESS;
2162 }
2163
2164 VkResult radv_ResetEvent(
2165 VkDevice _device,
2166 VkEvent _event)
2167 {
2168 RADV_FROM_HANDLE(radv_event, event, _event);
2169 *event->map = 0;
2170
2171 return VK_SUCCESS;
2172 }
2173
2174 VkResult radv_CreateBuffer(
2175 VkDevice _device,
2176 const VkBufferCreateInfo* pCreateInfo,
2177 const VkAllocationCallbacks* pAllocator,
2178 VkBuffer* pBuffer)
2179 {
2180 RADV_FROM_HANDLE(radv_device, device, _device);
2181 struct radv_buffer *buffer;
2182
2183 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2184
2185 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2186 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2187 if (buffer == NULL)
2188 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2189
2190 buffer->size = pCreateInfo->size;
2191 buffer->usage = pCreateInfo->usage;
2192 buffer->bo = NULL;
2193 buffer->offset = 0;
2194
2195 *pBuffer = radv_buffer_to_handle(buffer);
2196
2197 return VK_SUCCESS;
2198 }
2199
2200 void radv_DestroyBuffer(
2201 VkDevice _device,
2202 VkBuffer _buffer,
2203 const VkAllocationCallbacks* pAllocator)
2204 {
2205 RADV_FROM_HANDLE(radv_device, device, _device);
2206 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2207
2208 if (!buffer)
2209 return;
2210
2211 vk_free2(&device->alloc, pAllocator, buffer);
2212 }
2213
2214 static inline unsigned
2215 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2216 {
2217 if (stencil)
2218 return image->surface.stencil_tiling_index[level];
2219 else
2220 return image->surface.tiling_index[level];
2221 }
2222
2223 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2224 {
2225 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2226 }
2227
2228 static void
2229 radv_initialise_color_surface(struct radv_device *device,
2230 struct radv_color_buffer_info *cb,
2231 struct radv_image_view *iview)
2232 {
2233 const struct vk_format_description *desc;
2234 unsigned ntype, format, swap, endian;
2235 unsigned blend_clamp = 0, blend_bypass = 0;
2236 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2237 uint64_t va;
2238 const struct radeon_surf *surf = &iview->image->surface;
2239 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
2240
2241 desc = vk_format_description(iview->vk_format);
2242
2243 memset(cb, 0, sizeof(*cb));
2244
2245 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2246 va += level_info->offset;
2247 cb->cb_color_base = va >> 8;
2248
2249 /* CMASK variables */
2250 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2251 va += iview->image->cmask.offset;
2252 cb->cb_color_cmask = va >> 8;
2253 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2254
2255 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2256 va += iview->image->dcc_offset;
2257 cb->cb_dcc_base = va >> 8;
2258
2259 uint32_t max_slice = radv_surface_layer_count(iview);
2260 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
2261 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
2262
2263 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2264 pitch_tile_max = level_info->nblk_x / 8 - 1;
2265 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2266 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2267
2268 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2269 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2270
2271 /* Intensity is implemented as Red, so treat it that way. */
2272 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
2273 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2274
2275 if (iview->image->samples > 1) {
2276 unsigned log_samples = util_logbase2(iview->image->samples);
2277
2278 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2279 S_028C74_NUM_FRAGMENTS(log_samples);
2280 }
2281
2282 if (iview->image->fmask.size) {
2283 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
2284 if (device->physical_device->rad_info.chip_class >= CIK)
2285 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2286 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2287 cb->cb_color_fmask = va >> 8;
2288 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2289 } else {
2290 /* This must be set for fast clear to work without FMASK. */
2291 if (device->physical_device->rad_info.chip_class >= CIK)
2292 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2293 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2294 cb->cb_color_fmask = cb->cb_color_base;
2295 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2296 }
2297
2298 ntype = radv_translate_color_numformat(iview->vk_format,
2299 desc,
2300 vk_format_get_first_non_void_channel(iview->vk_format));
2301 format = radv_translate_colorformat(iview->vk_format);
2302 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
2303 radv_finishme("Illegal color\n");
2304 swap = radv_translate_colorswap(iview->vk_format, FALSE);
2305 endian = radv_colorformat_endian_swap(format);
2306
2307 /* blend clamp should be set for all NORM/SRGB types */
2308 if (ntype == V_028C70_NUMBER_UNORM ||
2309 ntype == V_028C70_NUMBER_SNORM ||
2310 ntype == V_028C70_NUMBER_SRGB)
2311 blend_clamp = 1;
2312
2313 /* set blend bypass according to docs if SINT/UINT or
2314 8/24 COLOR variants */
2315 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2316 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2317 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2318 blend_clamp = 0;
2319 blend_bypass = 1;
2320 }
2321 #if 0
2322 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2323 (format == V_028C70_COLOR_8 ||
2324 format == V_028C70_COLOR_8_8 ||
2325 format == V_028C70_COLOR_8_8_8_8))
2326 ->color_is_int8 = true;
2327 #endif
2328 cb->cb_color_info = S_028C70_FORMAT(format) |
2329 S_028C70_COMP_SWAP(swap) |
2330 S_028C70_BLEND_CLAMP(blend_clamp) |
2331 S_028C70_BLEND_BYPASS(blend_bypass) |
2332 S_028C70_SIMPLE_FLOAT(1) |
2333 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2334 ntype != V_028C70_NUMBER_SNORM &&
2335 ntype != V_028C70_NUMBER_SRGB &&
2336 format != V_028C70_COLOR_8_24 &&
2337 format != V_028C70_COLOR_24_8) |
2338 S_028C70_NUMBER_TYPE(ntype) |
2339 S_028C70_ENDIAN(endian);
2340 if (iview->image->samples > 1)
2341 if (iview->image->fmask.size)
2342 cb->cb_color_info |= S_028C70_COMPRESSION(1);
2343
2344 if (iview->image->cmask.size &&
2345 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
2346 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
2347
2348 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
2349 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
2350
2351 if (device->physical_device->rad_info.chip_class >= VI) {
2352 unsigned max_uncompressed_block_size = 2;
2353 if (iview->image->samples > 1) {
2354 if (iview->image->surface.bpe == 1)
2355 max_uncompressed_block_size = 0;
2356 else if (iview->image->surface.bpe == 2)
2357 max_uncompressed_block_size = 1;
2358 }
2359
2360 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2361 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2362 }
2363
2364 /* This must be set for fast clear to work without FMASK. */
2365 if (!iview->image->fmask.size &&
2366 device->physical_device->rad_info.chip_class == SI) {
2367 unsigned bankh = util_logbase2(iview->image->surface.bankh);
2368 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2369 }
2370 }
2371
2372 static void
2373 radv_initialise_ds_surface(struct radv_device *device,
2374 struct radv_ds_buffer_info *ds,
2375 struct radv_image_view *iview)
2376 {
2377 unsigned level = iview->base_mip;
2378 unsigned format;
2379 uint64_t va, s_offs, z_offs;
2380 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
2381 memset(ds, 0, sizeof(*ds));
2382 switch (iview->vk_format) {
2383 case VK_FORMAT_D24_UNORM_S8_UINT:
2384 case VK_FORMAT_X8_D24_UNORM_PACK32:
2385 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2386 ds->offset_scale = 2.0f;
2387 break;
2388 case VK_FORMAT_D16_UNORM:
2389 case VK_FORMAT_D16_UNORM_S8_UINT:
2390 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2391 ds->offset_scale = 4.0f;
2392 break;
2393 case VK_FORMAT_D32_SFLOAT:
2394 case VK_FORMAT_D32_SFLOAT_S8_UINT:
2395 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2396 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2397 ds->offset_scale = 1.0f;
2398 break;
2399 default:
2400 break;
2401 }
2402
2403 format = radv_translate_dbformat(iview->vk_format);
2404 if (format == V_028040_Z_INVALID) {
2405 fprintf(stderr, "Invalid DB format: %d, disabling DB.\n", iview->vk_format);
2406 }
2407
2408 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2409 s_offs = z_offs = va;
2410 z_offs += iview->image->surface.level[level].offset;
2411 s_offs += iview->image->surface.stencil_level[level].offset;
2412
2413 uint32_t max_slice = radv_surface_layer_count(iview);
2414 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
2415 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
2416 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2417 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
2418
2419 if (iview->image->samples > 1)
2420 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
2421
2422 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
2423 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
2424 else
2425 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2426
2427 if (device->physical_device->rad_info.chip_class >= CIK) {
2428 struct radeon_info *info = &device->physical_device->rad_info;
2429 unsigned tiling_index = iview->image->surface.tiling_index[level];
2430 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
2431 unsigned macro_index = iview->image->surface.macro_tile_index;
2432 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
2433 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2434 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2435
2436 ds->db_depth_info |=
2437 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2438 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2439 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2440 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2441 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2442 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2443 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2444 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2445 } else {
2446 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
2447 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2448 tile_mode_index = si_tile_mode_index(iview->image, level, true);
2449 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2450 }
2451
2452 if (iview->image->surface.htile_size && !level) {
2453 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2454 S_028040_ALLOW_EXPCLEAR(1);
2455
2456 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
2457 /* Workaround: For a not yet understood reason, the
2458 * combination of MSAA, fast stencil clear and stencil
2459 * decompress messes with subsequent stencil buffer
2460 * uses. Problem was reproduced on Verde, Bonaire,
2461 * Tonga, and Carrizo.
2462 *
2463 * Disabling EXPCLEAR works around the problem.
2464 *
2465 * Check piglit's arb_texture_multisample-stencil-clear
2466 * test if you want to try changing this.
2467 */
2468 if (iview->image->samples <= 1)
2469 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
2470 } else
2471 /* Use all of the htile_buffer for depth if there's no stencil. */
2472 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
2473
2474 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
2475 iview->image->htile_offset;
2476 ds->db_htile_data_base = va >> 8;
2477 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
2478 } else {
2479 ds->db_htile_data_base = 0;
2480 ds->db_htile_surface = 0;
2481 }
2482
2483 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
2484 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
2485
2486 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
2487 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
2488 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
2489 }
2490
2491 VkResult radv_CreateFramebuffer(
2492 VkDevice _device,
2493 const VkFramebufferCreateInfo* pCreateInfo,
2494 const VkAllocationCallbacks* pAllocator,
2495 VkFramebuffer* pFramebuffer)
2496 {
2497 RADV_FROM_HANDLE(radv_device, device, _device);
2498 struct radv_framebuffer *framebuffer;
2499
2500 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
2501
2502 size_t size = sizeof(*framebuffer) +
2503 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
2504 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
2505 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2506 if (framebuffer == NULL)
2507 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2508
2509 framebuffer->attachment_count = pCreateInfo->attachmentCount;
2510 framebuffer->width = pCreateInfo->width;
2511 framebuffer->height = pCreateInfo->height;
2512 framebuffer->layers = pCreateInfo->layers;
2513 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
2514 VkImageView _iview = pCreateInfo->pAttachments[i];
2515 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
2516 framebuffer->attachments[i].attachment = iview;
2517 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
2518 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
2519 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
2520 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
2521 }
2522 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
2523 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
2524 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
2525 }
2526
2527 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
2528 return VK_SUCCESS;
2529 }
2530
2531 void radv_DestroyFramebuffer(
2532 VkDevice _device,
2533 VkFramebuffer _fb,
2534 const VkAllocationCallbacks* pAllocator)
2535 {
2536 RADV_FROM_HANDLE(radv_device, device, _device);
2537 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
2538
2539 if (!fb)
2540 return;
2541 vk_free2(&device->alloc, pAllocator, fb);
2542 }
2543
2544 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
2545 {
2546 switch (address_mode) {
2547 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
2548 return V_008F30_SQ_TEX_WRAP;
2549 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
2550 return V_008F30_SQ_TEX_MIRROR;
2551 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
2552 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
2553 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
2554 return V_008F30_SQ_TEX_CLAMP_BORDER;
2555 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
2556 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2557 default:
2558 unreachable("illegal tex wrap mode");
2559 break;
2560 }
2561 }
2562
2563 static unsigned
2564 radv_tex_compare(VkCompareOp op)
2565 {
2566 switch (op) {
2567 case VK_COMPARE_OP_NEVER:
2568 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
2569 case VK_COMPARE_OP_LESS:
2570 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
2571 case VK_COMPARE_OP_EQUAL:
2572 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
2573 case VK_COMPARE_OP_LESS_OR_EQUAL:
2574 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2575 case VK_COMPARE_OP_GREATER:
2576 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
2577 case VK_COMPARE_OP_NOT_EQUAL:
2578 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2579 case VK_COMPARE_OP_GREATER_OR_EQUAL:
2580 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2581 case VK_COMPARE_OP_ALWAYS:
2582 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2583 default:
2584 unreachable("illegal compare mode");
2585 break;
2586 }
2587 }
2588
2589 static unsigned
2590 radv_tex_filter(VkFilter filter, unsigned max_ansio)
2591 {
2592 switch (filter) {
2593 case VK_FILTER_NEAREST:
2594 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
2595 V_008F38_SQ_TEX_XY_FILTER_POINT);
2596 case VK_FILTER_LINEAR:
2597 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
2598 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
2599 case VK_FILTER_CUBIC_IMG:
2600 default:
2601 fprintf(stderr, "illegal texture filter");
2602 return 0;
2603 }
2604 }
2605
2606 static unsigned
2607 radv_tex_mipfilter(VkSamplerMipmapMode mode)
2608 {
2609 switch (mode) {
2610 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
2611 return V_008F38_SQ_TEX_Z_FILTER_POINT;
2612 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
2613 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
2614 default:
2615 return V_008F38_SQ_TEX_Z_FILTER_NONE;
2616 }
2617 }
2618
2619 static unsigned
2620 radv_tex_bordercolor(VkBorderColor bcolor)
2621 {
2622 switch (bcolor) {
2623 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
2624 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
2625 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2626 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
2627 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
2628 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2629 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
2630 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
2631 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2632 default:
2633 break;
2634 }
2635 return 0;
2636 }
2637
2638 static unsigned
2639 radv_tex_aniso_filter(unsigned filter)
2640 {
2641 if (filter < 2)
2642 return 0;
2643 if (filter < 4)
2644 return 1;
2645 if (filter < 8)
2646 return 2;
2647 if (filter < 16)
2648 return 3;
2649 return 4;
2650 }
2651
2652 static void
2653 radv_init_sampler(struct radv_device *device,
2654 struct radv_sampler *sampler,
2655 const VkSamplerCreateInfo *pCreateInfo)
2656 {
2657 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
2658 (uint32_t) pCreateInfo->maxAnisotropy : 0;
2659 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
2660 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
2661
2662 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
2663 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
2664 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
2665 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
2666 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
2667 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
2668 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
2669 S_008F30_ANISO_BIAS(max_aniso_ratio) |
2670 S_008F30_DISABLE_CUBE_WRAP(0) |
2671 S_008F30_COMPAT_MODE(is_vi));
2672 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
2673 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
2674 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
2675 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
2676 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
2677 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
2678 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
2679 S_008F38_MIP_POINT_PRECLAMP(0) |
2680 S_008F38_DISABLE_LSB_CEIL(1) |
2681 S_008F38_FILTER_PREC_FIX(1) |
2682 S_008F38_ANISO_OVERRIDE(is_vi));
2683 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
2684 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
2685 }
2686
2687 VkResult radv_CreateSampler(
2688 VkDevice _device,
2689 const VkSamplerCreateInfo* pCreateInfo,
2690 const VkAllocationCallbacks* pAllocator,
2691 VkSampler* pSampler)
2692 {
2693 RADV_FROM_HANDLE(radv_device, device, _device);
2694 struct radv_sampler *sampler;
2695
2696 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
2697
2698 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
2699 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2700 if (!sampler)
2701 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2702
2703 radv_init_sampler(device, sampler, pCreateInfo);
2704 *pSampler = radv_sampler_to_handle(sampler);
2705
2706 return VK_SUCCESS;
2707 }
2708
2709 void radv_DestroySampler(
2710 VkDevice _device,
2711 VkSampler _sampler,
2712 const VkAllocationCallbacks* pAllocator)
2713 {
2714 RADV_FROM_HANDLE(radv_device, device, _device);
2715 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
2716
2717 if (!sampler)
2718 return;
2719 vk_free2(&device->alloc, pAllocator, sampler);
2720 }
2721
2722
2723 /* vk_icd.h does not declare this function, so we declare it here to
2724 * suppress Wmissing-prototypes.
2725 */
2726 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
2727 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
2728
2729 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
2730 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
2731 {
2732 /* For the full details on loader interface versioning, see
2733 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
2734 * What follows is a condensed summary, to help you navigate the large and
2735 * confusing official doc.
2736 *
2737 * - Loader interface v0 is incompatible with later versions. We don't
2738 * support it.
2739 *
2740 * - In loader interface v1:
2741 * - The first ICD entrypoint called by the loader is
2742 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
2743 * entrypoint.
2744 * - The ICD must statically expose no other Vulkan symbol unless it is
2745 * linked with -Bsymbolic.
2746 * - Each dispatchable Vulkan handle created by the ICD must be
2747 * a pointer to a struct whose first member is VK_LOADER_DATA. The
2748 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
2749 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
2750 * vkDestroySurfaceKHR(). The ICD must be capable of working with
2751 * such loader-managed surfaces.
2752 *
2753 * - Loader interface v2 differs from v1 in:
2754 * - The first ICD entrypoint called by the loader is
2755 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
2756 * statically expose this entrypoint.
2757 *
2758 * - Loader interface v3 differs from v2 in:
2759 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
2760 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
2761 * because the loader no longer does so.
2762 */
2763 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
2764 return VK_SUCCESS;
2765 }