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radv: honour the number of properties available
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <dlfcn.h>
29 #include <stdbool.h>
30 #include <string.h>
31 #include <unistd.h>
32 #include <fcntl.h>
33 #include <sys/stat.h>
34 #include "radv_private.h"
35 #include "util/strtod.h"
36
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "util/debug.h"
46 struct radv_dispatch_table dtable;
47
48 static int
49 radv_get_function_timestamp(void *ptr, uint32_t* timestamp)
50 {
51 Dl_info info;
52 struct stat st;
53 if (!dladdr(ptr, &info) || !info.dli_fname) {
54 return -1;
55 }
56 if (stat(info.dli_fname, &st)) {
57 return -1;
58 }
59 *timestamp = st.st_mtim.tv_sec;
60 return 0;
61 }
62
63 static int
64 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
65 {
66 uint32_t mesa_timestamp, llvm_timestamp;
67 uint16_t f = family;
68 memset(uuid, 0, VK_UUID_SIZE);
69 if (radv_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
70 radv_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
71 return -1;
72
73 memcpy(uuid, &mesa_timestamp, 4);
74 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
75 memcpy((char*)uuid + 8, &f, 2);
76 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
77 return 0;
78 }
79
80 static VkResult
81 radv_physical_device_init(struct radv_physical_device *device,
82 struct radv_instance *instance,
83 const char *path)
84 {
85 VkResult result;
86 drmVersionPtr version;
87 int fd;
88
89 fd = open(path, O_RDWR | O_CLOEXEC);
90 if (fd < 0)
91 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
92 "failed to open %s: %m", path);
93
94 version = drmGetVersion(fd);
95 if (!version) {
96 close(fd);
97 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
98 "failed to get version %s: %m", path);
99 }
100
101 if (strcmp(version->name, "amdgpu")) {
102 drmFreeVersion(version);
103 close(fd);
104 return VK_ERROR_INCOMPATIBLE_DRIVER;
105 }
106 drmFreeVersion(version);
107
108 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
109 device->instance = instance;
110 assert(strlen(path) < ARRAY_SIZE(device->path));
111 strncpy(device->path, path, ARRAY_SIZE(device->path));
112
113 device->ws = radv_amdgpu_winsys_create(fd);
114 if (!device->ws) {
115 result = VK_ERROR_INCOMPATIBLE_DRIVER;
116 goto fail;
117 }
118 device->ws->query_info(device->ws, &device->rad_info);
119 result = radv_init_wsi(device);
120 if (result != VK_SUCCESS) {
121 device->ws->destroy(device->ws);
122 goto fail;
123 }
124
125 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
126 radv_finish_wsi(device);
127 device->ws->destroy(device->ws);
128 goto fail;
129 }
130
131 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
132 device->name = device->rad_info.name;
133 return VK_SUCCESS;
134
135 fail:
136 close(fd);
137 return result;
138 }
139
140 static void
141 radv_physical_device_finish(struct radv_physical_device *device)
142 {
143 radv_finish_wsi(device);
144 device->ws->destroy(device->ws);
145 }
146
147 static const VkExtensionProperties global_extensions[] = {
148 {
149 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
150 .specVersion = 25,
151 },
152 #ifdef VK_USE_PLATFORM_XCB_KHR
153 {
154 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
155 .specVersion = 6,
156 },
157 #endif
158 #ifdef VK_USE_PLATFORM_XLIB_KHR
159 {
160 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
161 .specVersion = 6,
162 },
163 #endif
164 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
165 {
166 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
167 .specVersion = 5,
168 },
169 #endif
170 };
171
172 static const VkExtensionProperties device_extensions[] = {
173 {
174 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
175 .specVersion = 1,
176 },
177 {
178 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
179 .specVersion = 68,
180 },
181 {
182 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
183 .specVersion = 1,
184 },
185 {
186 .extensionName = VK_AMD_NEGATIVE_VIEWPORT_HEIGHT_EXTENSION_NAME,
187 .specVersion = 1,
188 },
189 };
190
191 static void *
192 default_alloc_func(void *pUserData, size_t size, size_t align,
193 VkSystemAllocationScope allocationScope)
194 {
195 return malloc(size);
196 }
197
198 static void *
199 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
200 size_t align, VkSystemAllocationScope allocationScope)
201 {
202 return realloc(pOriginal, size);
203 }
204
205 static void
206 default_free_func(void *pUserData, void *pMemory)
207 {
208 free(pMemory);
209 }
210
211 static const VkAllocationCallbacks default_alloc = {
212 .pUserData = NULL,
213 .pfnAllocation = default_alloc_func,
214 .pfnReallocation = default_realloc_func,
215 .pfnFree = default_free_func,
216 };
217
218 VkResult radv_CreateInstance(
219 const VkInstanceCreateInfo* pCreateInfo,
220 const VkAllocationCallbacks* pAllocator,
221 VkInstance* pInstance)
222 {
223 struct radv_instance *instance;
224
225 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
226
227 uint32_t client_version;
228 if (pCreateInfo->pApplicationInfo &&
229 pCreateInfo->pApplicationInfo->apiVersion != 0) {
230 client_version = pCreateInfo->pApplicationInfo->apiVersion;
231 } else {
232 client_version = VK_MAKE_VERSION(1, 0, 0);
233 }
234
235 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
236 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
237 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
238 "Client requested version %d.%d.%d",
239 VK_VERSION_MAJOR(client_version),
240 VK_VERSION_MINOR(client_version),
241 VK_VERSION_PATCH(client_version));
242 }
243
244 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
245 bool found = false;
246 for (uint32_t j = 0; j < ARRAY_SIZE(global_extensions); j++) {
247 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
248 global_extensions[j].extensionName) == 0) {
249 found = true;
250 break;
251 }
252 }
253 if (!found)
254 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
255 }
256
257 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
258 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
259 if (!instance)
260 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
261
262 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
263
264 if (pAllocator)
265 instance->alloc = *pAllocator;
266 else
267 instance->alloc = default_alloc;
268
269 instance->apiVersion = client_version;
270 instance->physicalDeviceCount = -1;
271
272 _mesa_locale_init();
273
274 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
275
276 *pInstance = radv_instance_to_handle(instance);
277
278 return VK_SUCCESS;
279 }
280
281 void radv_DestroyInstance(
282 VkInstance _instance,
283 const VkAllocationCallbacks* pAllocator)
284 {
285 RADV_FROM_HANDLE(radv_instance, instance, _instance);
286
287 if (instance->physicalDeviceCount > 0) {
288 /* We support at most one physical device. */
289 assert(instance->physicalDeviceCount == 1);
290 radv_physical_device_finish(&instance->physicalDevice);
291 }
292
293 VG(VALGRIND_DESTROY_MEMPOOL(instance));
294
295 _mesa_locale_fini();
296
297 vk_free(&instance->alloc, instance);
298 }
299
300 VkResult radv_EnumeratePhysicalDevices(
301 VkInstance _instance,
302 uint32_t* pPhysicalDeviceCount,
303 VkPhysicalDevice* pPhysicalDevices)
304 {
305 RADV_FROM_HANDLE(radv_instance, instance, _instance);
306 VkResult result;
307
308 if (instance->physicalDeviceCount < 0) {
309 char path[20];
310 for (unsigned i = 0; i < 8; i++) {
311 snprintf(path, sizeof(path), "/dev/dri/renderD%d", 128 + i);
312 result = radv_physical_device_init(&instance->physicalDevice,
313 instance, path);
314 if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
315 break;
316 }
317
318 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
319 instance->physicalDeviceCount = 0;
320 } else if (result == VK_SUCCESS) {
321 instance->physicalDeviceCount = 1;
322 } else {
323 return result;
324 }
325 }
326
327 /* pPhysicalDeviceCount is an out parameter if pPhysicalDevices is NULL;
328 * otherwise it's an inout parameter.
329 *
330 * The Vulkan spec (git aaed022) says:
331 *
332 * pPhysicalDeviceCount is a pointer to an unsigned integer variable
333 * that is initialized with the number of devices the application is
334 * prepared to receive handles to. pname:pPhysicalDevices is pointer to
335 * an array of at least this many VkPhysicalDevice handles [...].
336 *
337 * Upon success, if pPhysicalDevices is NULL, vkEnumeratePhysicalDevices
338 * overwrites the contents of the variable pointed to by
339 * pPhysicalDeviceCount with the number of physical devices in in the
340 * instance; otherwise, vkEnumeratePhysicalDevices overwrites
341 * pPhysicalDeviceCount with the number of physical handles written to
342 * pPhysicalDevices.
343 */
344 if (!pPhysicalDevices) {
345 *pPhysicalDeviceCount = instance->physicalDeviceCount;
346 } else if (*pPhysicalDeviceCount >= 1) {
347 pPhysicalDevices[0] = radv_physical_device_to_handle(&instance->physicalDevice);
348 *pPhysicalDeviceCount = 1;
349 } else if (*pPhysicalDeviceCount < instance->physicalDeviceCount) {
350 return VK_INCOMPLETE;
351 } else {
352 *pPhysicalDeviceCount = 0;
353 }
354
355 return VK_SUCCESS;
356 }
357
358 void radv_GetPhysicalDeviceFeatures(
359 VkPhysicalDevice physicalDevice,
360 VkPhysicalDeviceFeatures* pFeatures)
361 {
362 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
363
364 memset(pFeatures, 0, sizeof(*pFeatures));
365
366 *pFeatures = (VkPhysicalDeviceFeatures) {
367 .robustBufferAccess = true,
368 .fullDrawIndexUint32 = true,
369 .imageCubeArray = true,
370 .independentBlend = true,
371 .geometryShader = false,
372 .tessellationShader = false,
373 .sampleRateShading = false,
374 .dualSrcBlend = true,
375 .logicOp = true,
376 .multiDrawIndirect = true,
377 .drawIndirectFirstInstance = true,
378 .depthClamp = true,
379 .depthBiasClamp = true,
380 .fillModeNonSolid = true,
381 .depthBounds = true,
382 .wideLines = true,
383 .largePoints = true,
384 .alphaToOne = true,
385 .multiViewport = false,
386 .samplerAnisotropy = true,
387 .textureCompressionETC2 = false,
388 .textureCompressionASTC_LDR = false,
389 .textureCompressionBC = true,
390 .occlusionQueryPrecise = true,
391 .pipelineStatisticsQuery = false,
392 .vertexPipelineStoresAndAtomics = true,
393 .fragmentStoresAndAtomics = true,
394 .shaderTessellationAndGeometryPointSize = true,
395 .shaderImageGatherExtended = false,
396 .shaderStorageImageExtendedFormats = false,
397 .shaderStorageImageMultisample = false,
398 .shaderUniformBufferArrayDynamicIndexing = true,
399 .shaderSampledImageArrayDynamicIndexing = true,
400 .shaderStorageBufferArrayDynamicIndexing = true,
401 .shaderStorageImageArrayDynamicIndexing = true,
402 .shaderStorageImageReadWithoutFormat = false,
403 .shaderStorageImageWriteWithoutFormat = true,
404 .shaderClipDistance = true,
405 .shaderCullDistance = true,
406 .shaderFloat64 = false,
407 .shaderInt64 = false,
408 .shaderInt16 = false,
409 .alphaToOne = true,
410 .variableMultisampleRate = false,
411 .inheritedQueries = false,
412 };
413 }
414
415 void radv_GetPhysicalDeviceProperties(
416 VkPhysicalDevice physicalDevice,
417 VkPhysicalDeviceProperties* pProperties)
418 {
419 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
420 VkSampleCountFlags sample_counts = 0xf;
421 VkPhysicalDeviceLimits limits = {
422 .maxImageDimension1D = (1 << 14),
423 .maxImageDimension2D = (1 << 14),
424 .maxImageDimension3D = (1 << 11),
425 .maxImageDimensionCube = (1 << 14),
426 .maxImageArrayLayers = (1 << 11),
427 .maxTexelBufferElements = 128 * 1024 * 1024,
428 .maxUniformBufferRange = UINT32_MAX,
429 .maxStorageBufferRange = UINT32_MAX,
430 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
431 .maxMemoryAllocationCount = UINT32_MAX,
432 .maxSamplerAllocationCount = 64 * 1024,
433 .bufferImageGranularity = 64, /* A cache line */
434 .sparseAddressSpaceSize = 0,
435 .maxBoundDescriptorSets = MAX_SETS,
436 .maxPerStageDescriptorSamplers = 64,
437 .maxPerStageDescriptorUniformBuffers = 64,
438 .maxPerStageDescriptorStorageBuffers = 64,
439 .maxPerStageDescriptorSampledImages = 64,
440 .maxPerStageDescriptorStorageImages = 64,
441 .maxPerStageDescriptorInputAttachments = 64,
442 .maxPerStageResources = 128,
443 .maxDescriptorSetSamplers = 256,
444 .maxDescriptorSetUniformBuffers = 256,
445 .maxDescriptorSetUniformBuffersDynamic = 256,
446 .maxDescriptorSetStorageBuffers = 256,
447 .maxDescriptorSetStorageBuffersDynamic = 256,
448 .maxDescriptorSetSampledImages = 256,
449 .maxDescriptorSetStorageImages = 256,
450 .maxDescriptorSetInputAttachments = 256,
451 .maxVertexInputAttributes = 32,
452 .maxVertexInputBindings = 32,
453 .maxVertexInputAttributeOffset = 2047,
454 .maxVertexInputBindingStride = 2048,
455 .maxVertexOutputComponents = 128,
456 .maxTessellationGenerationLevel = 0,
457 .maxTessellationPatchSize = 0,
458 .maxTessellationControlPerVertexInputComponents = 0,
459 .maxTessellationControlPerVertexOutputComponents = 0,
460 .maxTessellationControlPerPatchOutputComponents = 0,
461 .maxTessellationControlTotalOutputComponents = 0,
462 .maxTessellationEvaluationInputComponents = 0,
463 .maxTessellationEvaluationOutputComponents = 0,
464 .maxGeometryShaderInvocations = 32,
465 .maxGeometryInputComponents = 64,
466 .maxGeometryOutputComponents = 128,
467 .maxGeometryOutputVertices = 256,
468 .maxGeometryTotalOutputComponents = 1024,
469 .maxFragmentInputComponents = 128,
470 .maxFragmentOutputAttachments = 8,
471 .maxFragmentDualSrcAttachments = 2,
472 .maxFragmentCombinedOutputResources = 8,
473 .maxComputeSharedMemorySize = 32768,
474 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
475 .maxComputeWorkGroupInvocations = 16 * 1024,
476 .maxComputeWorkGroupSize = {
477 16 * 1024/*devinfo->max_cs_threads*/,
478 16 * 1024,
479 16 * 1024
480 },
481 .subPixelPrecisionBits = 4 /* FIXME */,
482 .subTexelPrecisionBits = 4 /* FIXME */,
483 .mipmapPrecisionBits = 4 /* FIXME */,
484 .maxDrawIndexedIndexValue = UINT32_MAX,
485 .maxDrawIndirectCount = UINT32_MAX,
486 .maxSamplerLodBias = 16,
487 .maxSamplerAnisotropy = 16,
488 .maxViewports = MAX_VIEWPORTS,
489 .maxViewportDimensions = { (1 << 14), (1 << 14) },
490 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
491 .viewportSubPixelBits = 13, /* We take a float? */
492 .minMemoryMapAlignment = 4096, /* A page */
493 .minTexelBufferOffsetAlignment = 1,
494 .minUniformBufferOffsetAlignment = 4,
495 .minStorageBufferOffsetAlignment = 4,
496 .minTexelOffset = -8,
497 .maxTexelOffset = 7,
498 .minTexelGatherOffset = -8,
499 .maxTexelGatherOffset = 7,
500 .minInterpolationOffset = 0, /* FIXME */
501 .maxInterpolationOffset = 0, /* FIXME */
502 .subPixelInterpolationOffsetBits = 0, /* FIXME */
503 .maxFramebufferWidth = (1 << 14),
504 .maxFramebufferHeight = (1 << 14),
505 .maxFramebufferLayers = (1 << 10),
506 .framebufferColorSampleCounts = sample_counts,
507 .framebufferDepthSampleCounts = sample_counts,
508 .framebufferStencilSampleCounts = sample_counts,
509 .framebufferNoAttachmentsSampleCounts = sample_counts,
510 .maxColorAttachments = MAX_RTS,
511 .sampledImageColorSampleCounts = sample_counts,
512 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
513 .sampledImageDepthSampleCounts = sample_counts,
514 .sampledImageStencilSampleCounts = sample_counts,
515 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
516 .maxSampleMaskWords = 1,
517 .timestampComputeAndGraphics = false,
518 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
519 .maxClipDistances = 8,
520 .maxCullDistances = 8,
521 .maxCombinedClipAndCullDistances = 8,
522 .discreteQueuePriorities = 1,
523 .pointSizeRange = { 0.125, 255.875 },
524 .lineWidthRange = { 0.0, 7.9921875 },
525 .pointSizeGranularity = (1.0 / 8.0),
526 .lineWidthGranularity = (1.0 / 128.0),
527 .strictLines = false, /* FINISHME */
528 .standardSampleLocations = true,
529 .optimalBufferCopyOffsetAlignment = 128,
530 .optimalBufferCopyRowPitchAlignment = 128,
531 .nonCoherentAtomSize = 64,
532 };
533
534 *pProperties = (VkPhysicalDeviceProperties) {
535 .apiVersion = VK_MAKE_VERSION(1, 0, 5),
536 .driverVersion = 1,
537 .vendorID = 0x1002,
538 .deviceID = pdevice->rad_info.pci_id,
539 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
540 .limits = limits,
541 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
542 };
543
544 strcpy(pProperties->deviceName, pdevice->name);
545 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
546 }
547
548 void radv_GetPhysicalDeviceQueueFamilyProperties(
549 VkPhysicalDevice physicalDevice,
550 uint32_t* pCount,
551 VkQueueFamilyProperties* pQueueFamilyProperties)
552 {
553 if (pQueueFamilyProperties == NULL) {
554 *pCount = 1;
555 return;
556 }
557 assert(*pCount >= 1);
558
559 *pQueueFamilyProperties = (VkQueueFamilyProperties) {
560 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
561 VK_QUEUE_COMPUTE_BIT |
562 VK_QUEUE_TRANSFER_BIT,
563 .queueCount = 1,
564 .timestampValidBits = 64,
565 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
566 };
567 }
568
569 void radv_GetPhysicalDeviceMemoryProperties(
570 VkPhysicalDevice physicalDevice,
571 VkPhysicalDeviceMemoryProperties* pMemoryProperties)
572 {
573 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
574
575 pMemoryProperties->memoryTypeCount = 4;
576 pMemoryProperties->memoryTypes[0] = (VkMemoryType) {
577 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
578 .heapIndex = 0,
579 };
580 pMemoryProperties->memoryTypes[1] = (VkMemoryType) {
581 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
582 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
583 .heapIndex = 2,
584 };
585 pMemoryProperties->memoryTypes[2] = (VkMemoryType) {
586 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
587 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
588 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
589 .heapIndex = 1,
590 };
591 pMemoryProperties->memoryTypes[3] = (VkMemoryType) {
592 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
593 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
594 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
595 .heapIndex = 2,
596 };
597
598 pMemoryProperties->memoryHeapCount = 3;
599 pMemoryProperties->memoryHeaps[0] = (VkMemoryHeap) {
600 .size = physical_device->rad_info.vram_size -
601 physical_device->rad_info.visible_vram_size,
602 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
603 };
604 pMemoryProperties->memoryHeaps[1] = (VkMemoryHeap) {
605 .size = physical_device->rad_info.visible_vram_size,
606 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
607 };
608 pMemoryProperties->memoryHeaps[2] = (VkMemoryHeap) {
609 .size = physical_device->rad_info.gart_size,
610 .flags = 0,
611 };
612 }
613
614 static void
615 radv_queue_init(struct radv_device *device, struct radv_queue *queue)
616 {
617 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
618 queue->device = device;
619 }
620
621 static void
622 radv_queue_finish(struct radv_queue *queue)
623 {
624 }
625
626 VkResult radv_CreateDevice(
627 VkPhysicalDevice physicalDevice,
628 const VkDeviceCreateInfo* pCreateInfo,
629 const VkAllocationCallbacks* pAllocator,
630 VkDevice* pDevice)
631 {
632 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
633 VkResult result;
634 struct radv_device *device;
635
636 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
637 bool found = false;
638 for (uint32_t j = 0; j < ARRAY_SIZE(device_extensions); j++) {
639 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
640 device_extensions[j].extensionName) == 0) {
641 found = true;
642 break;
643 }
644 }
645 if (!found)
646 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
647 }
648
649 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
650 sizeof(*device), 8,
651 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
652 if (!device)
653 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
654
655 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
656 device->instance = physical_device->instance;
657
658 device->ws = physical_device->ws;
659 if (pAllocator)
660 device->alloc = *pAllocator;
661 else
662 device->alloc = physical_device->instance->alloc;
663
664 device->hw_ctx = device->ws->ctx_create(device->ws);
665 if (!device->hw_ctx) {
666 result = VK_ERROR_OUT_OF_HOST_MEMORY;
667 goto fail_free;
668 }
669
670 radv_queue_init(device, &device->queue);
671
672 result = radv_device_init_meta(device);
673 if (result != VK_SUCCESS) {
674 device->ws->ctx_destroy(device->hw_ctx);
675 goto fail_free;
676 }
677 device->allow_fast_clears = env_var_as_boolean("RADV_FAST_CLEARS", false);
678 device->allow_dcc = !env_var_as_boolean("RADV_DCC_DISABLE", false);
679 device->shader_stats_dump = env_var_as_boolean("RADV_SHADER_STATS", false);
680
681 if (device->allow_fast_clears && device->allow_dcc)
682 radv_finishme("DCC fast clears have not been tested\n");
683
684 radv_device_init_msaa(device);
685 device->empty_cs = device->ws->cs_create(device->ws, RING_GFX);
686 radeon_emit(device->empty_cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
687 radeon_emit(device->empty_cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
688 radeon_emit(device->empty_cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
689 device->ws->cs_finalize(device->empty_cs);
690 *pDevice = radv_device_to_handle(device);
691 return VK_SUCCESS;
692 fail_free:
693 vk_free(&device->alloc, device);
694 return result;
695 }
696
697 void radv_DestroyDevice(
698 VkDevice _device,
699 const VkAllocationCallbacks* pAllocator)
700 {
701 RADV_FROM_HANDLE(radv_device, device, _device);
702
703 device->ws->ctx_destroy(device->hw_ctx);
704 radv_queue_finish(&device->queue);
705 radv_device_finish_meta(device);
706
707 vk_free(&device->alloc, device);
708 }
709
710 VkResult radv_EnumerateInstanceExtensionProperties(
711 const char* pLayerName,
712 uint32_t* pPropertyCount,
713 VkExtensionProperties* pProperties)
714 {
715 if (pProperties == NULL) {
716 *pPropertyCount = ARRAY_SIZE(global_extensions);
717 return VK_SUCCESS;
718 }
719
720 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(global_extensions));
721 typed_memcpy(pProperties, global_extensions, *pPropertyCount);
722
723 if (*pPropertyCount < ARRAY_SIZE(global_extensions))
724 return VK_INCOMPLETE;
725
726 return VK_SUCCESS;
727 }
728
729 VkResult radv_EnumerateDeviceExtensionProperties(
730 VkPhysicalDevice physicalDevice,
731 const char* pLayerName,
732 uint32_t* pPropertyCount,
733 VkExtensionProperties* pProperties)
734 {
735 if (pProperties == NULL) {
736 *pPropertyCount = ARRAY_SIZE(device_extensions);
737 return VK_SUCCESS;
738 }
739
740 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(device_extensions));
741 typed_memcpy(pProperties, device_extensions, *pPropertyCount);
742
743 if (*pPropertyCount < ARRAY_SIZE(device_extensions))
744 return VK_INCOMPLETE;
745
746 return VK_SUCCESS;
747 }
748
749 VkResult radv_EnumerateInstanceLayerProperties(
750 uint32_t* pPropertyCount,
751 VkLayerProperties* pProperties)
752 {
753 if (pProperties == NULL) {
754 *pPropertyCount = 0;
755 return VK_SUCCESS;
756 }
757
758 /* None supported at this time */
759 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
760 }
761
762 VkResult radv_EnumerateDeviceLayerProperties(
763 VkPhysicalDevice physicalDevice,
764 uint32_t* pPropertyCount,
765 VkLayerProperties* pProperties)
766 {
767 if (pProperties == NULL) {
768 *pPropertyCount = 0;
769 return VK_SUCCESS;
770 }
771
772 /* None supported at this time */
773 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
774 }
775
776 void radv_GetDeviceQueue(
777 VkDevice _device,
778 uint32_t queueNodeIndex,
779 uint32_t queueIndex,
780 VkQueue* pQueue)
781 {
782 RADV_FROM_HANDLE(radv_device, device, _device);
783
784 assert(queueIndex == 0);
785
786 *pQueue = radv_queue_to_handle(&device->queue);
787 }
788
789 VkResult radv_QueueSubmit(
790 VkQueue _queue,
791 uint32_t submitCount,
792 const VkSubmitInfo* pSubmits,
793 VkFence _fence)
794 {
795 RADV_FROM_HANDLE(radv_queue, queue, _queue);
796 RADV_FROM_HANDLE(radv_fence, fence, _fence);
797 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
798 struct radeon_winsys_ctx *ctx = queue->device->hw_ctx;
799 int ret;
800
801 for (uint32_t i = 0; i < submitCount; i++) {
802 struct radeon_winsys_cs **cs_array;
803 bool can_patch = true;
804
805 if (!pSubmits[i].commandBufferCount)
806 continue;
807
808 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
809 pSubmits[i].commandBufferCount);
810
811 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
812 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
813 pSubmits[i].pCommandBuffers[j]);
814 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
815
816 cs_array[j] = cmd_buffer->cs;
817 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
818 can_patch = false;
819 }
820 ret = queue->device->ws->cs_submit(ctx, cs_array,
821 pSubmits[i].commandBufferCount,
822 can_patch, base_fence);
823 if (ret)
824 radv_loge("failed to submit CS %d\n", i);
825 free(cs_array);
826 }
827
828 if (fence) {
829 if (!submitCount)
830 ret = queue->device->ws->cs_submit(ctx, &queue->device->empty_cs,
831 1, false, base_fence);
832
833 fence->submitted = true;
834 }
835
836 return VK_SUCCESS;
837 }
838
839 VkResult radv_QueueWaitIdle(
840 VkQueue _queue)
841 {
842 RADV_FROM_HANDLE(radv_queue, queue, _queue);
843
844 queue->device->ws->ctx_wait_idle(queue->device->hw_ctx);
845 return VK_SUCCESS;
846 }
847
848 VkResult radv_DeviceWaitIdle(
849 VkDevice _device)
850 {
851 RADV_FROM_HANDLE(radv_device, device, _device);
852
853 device->ws->ctx_wait_idle(device->hw_ctx);
854 return VK_SUCCESS;
855 }
856
857 PFN_vkVoidFunction radv_GetInstanceProcAddr(
858 VkInstance instance,
859 const char* pName)
860 {
861 return radv_lookup_entrypoint(pName);
862 }
863
864 /* The loader wants us to expose a second GetInstanceProcAddr function
865 * to work around certain LD_PRELOAD issues seen in apps.
866 */
867 PUBLIC
868 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
869 VkInstance instance,
870 const char* pName);
871
872 PUBLIC
873 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
874 VkInstance instance,
875 const char* pName)
876 {
877 return radv_GetInstanceProcAddr(instance, pName);
878 }
879
880 PFN_vkVoidFunction radv_GetDeviceProcAddr(
881 VkDevice device,
882 const char* pName)
883 {
884 return radv_lookup_entrypoint(pName);
885 }
886
887 VkResult radv_AllocateMemory(
888 VkDevice _device,
889 const VkMemoryAllocateInfo* pAllocateInfo,
890 const VkAllocationCallbacks* pAllocator,
891 VkDeviceMemory* pMem)
892 {
893 RADV_FROM_HANDLE(radv_device, device, _device);
894 struct radv_device_memory *mem;
895 VkResult result;
896 enum radeon_bo_domain domain;
897 uint32_t flags = 0;
898 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
899
900 if (pAllocateInfo->allocationSize == 0) {
901 /* Apparently, this is allowed */
902 *pMem = VK_NULL_HANDLE;
903 return VK_SUCCESS;
904 }
905
906 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
907 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
908 if (mem == NULL)
909 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
910
911 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
912 if (pAllocateInfo->memoryTypeIndex == 1 || pAllocateInfo->memoryTypeIndex == 3)
913 domain = RADEON_DOMAIN_GTT;
914 else
915 domain = RADEON_DOMAIN_VRAM;
916
917 if (pAllocateInfo->memoryTypeIndex == 0)
918 flags |= RADEON_FLAG_NO_CPU_ACCESS;
919 else
920 flags |= RADEON_FLAG_CPU_ACCESS;
921
922 if (pAllocateInfo->memoryTypeIndex == 1)
923 flags |= RADEON_FLAG_GTT_WC;
924
925 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 32768,
926 domain, flags);
927
928 if (!mem->bo) {
929 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
930 goto fail;
931 }
932 mem->type_index = pAllocateInfo->memoryTypeIndex;
933
934 *pMem = radv_device_memory_to_handle(mem);
935
936 return VK_SUCCESS;
937
938 fail:
939 vk_free2(&device->alloc, pAllocator, mem);
940
941 return result;
942 }
943
944 void radv_FreeMemory(
945 VkDevice _device,
946 VkDeviceMemory _mem,
947 const VkAllocationCallbacks* pAllocator)
948 {
949 RADV_FROM_HANDLE(radv_device, device, _device);
950 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
951
952 if (mem == NULL)
953 return;
954
955 device->ws->buffer_destroy(mem->bo);
956 mem->bo = NULL;
957
958 vk_free2(&device->alloc, pAllocator, mem);
959 }
960
961 VkResult radv_MapMemory(
962 VkDevice _device,
963 VkDeviceMemory _memory,
964 VkDeviceSize offset,
965 VkDeviceSize size,
966 VkMemoryMapFlags flags,
967 void** ppData)
968 {
969 RADV_FROM_HANDLE(radv_device, device, _device);
970 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
971
972 if (mem == NULL) {
973 *ppData = NULL;
974 return VK_SUCCESS;
975 }
976
977 *ppData = device->ws->buffer_map(mem->bo);
978 if (*ppData) {
979 *ppData += offset;
980 return VK_SUCCESS;
981 }
982
983 return VK_ERROR_MEMORY_MAP_FAILED;
984 }
985
986 void radv_UnmapMemory(
987 VkDevice _device,
988 VkDeviceMemory _memory)
989 {
990 RADV_FROM_HANDLE(radv_device, device, _device);
991 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
992
993 if (mem == NULL)
994 return;
995
996 device->ws->buffer_unmap(mem->bo);
997 }
998
999 VkResult radv_FlushMappedMemoryRanges(
1000 VkDevice _device,
1001 uint32_t memoryRangeCount,
1002 const VkMappedMemoryRange* pMemoryRanges)
1003 {
1004 return VK_SUCCESS;
1005 }
1006
1007 VkResult radv_InvalidateMappedMemoryRanges(
1008 VkDevice _device,
1009 uint32_t memoryRangeCount,
1010 const VkMappedMemoryRange* pMemoryRanges)
1011 {
1012 return VK_SUCCESS;
1013 }
1014
1015 void radv_GetBufferMemoryRequirements(
1016 VkDevice device,
1017 VkBuffer _buffer,
1018 VkMemoryRequirements* pMemoryRequirements)
1019 {
1020 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1021
1022 /* The Vulkan spec (git aaed022) says:
1023 *
1024 * memoryTypeBits is a bitfield and contains one bit set for every
1025 * supported memory type for the resource. The bit `1<<i` is set if and
1026 * only if the memory type `i` in the VkPhysicalDeviceMemoryProperties
1027 * structure for the physical device is supported.
1028 *
1029 * We support exactly one memory type.
1030 */
1031 pMemoryRequirements->memoryTypeBits = 0x7;
1032
1033 pMemoryRequirements->size = buffer->size;
1034 pMemoryRequirements->alignment = 16;
1035 }
1036
1037 void radv_GetImageMemoryRequirements(
1038 VkDevice device,
1039 VkImage _image,
1040 VkMemoryRequirements* pMemoryRequirements)
1041 {
1042 RADV_FROM_HANDLE(radv_image, image, _image);
1043
1044 /* The Vulkan spec (git aaed022) says:
1045 *
1046 * memoryTypeBits is a bitfield and contains one bit set for every
1047 * supported memory type for the resource. The bit `1<<i` is set if and
1048 * only if the memory type `i` in the VkPhysicalDeviceMemoryProperties
1049 * structure for the physical device is supported.
1050 *
1051 * We support exactly one memory type.
1052 */
1053 pMemoryRequirements->memoryTypeBits = 0x7;
1054
1055 pMemoryRequirements->size = image->size;
1056 pMemoryRequirements->alignment = image->alignment;
1057 }
1058
1059 void radv_GetImageSparseMemoryRequirements(
1060 VkDevice device,
1061 VkImage image,
1062 uint32_t* pSparseMemoryRequirementCount,
1063 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
1064 {
1065 stub();
1066 }
1067
1068 void radv_GetDeviceMemoryCommitment(
1069 VkDevice device,
1070 VkDeviceMemory memory,
1071 VkDeviceSize* pCommittedMemoryInBytes)
1072 {
1073 *pCommittedMemoryInBytes = 0;
1074 }
1075
1076 VkResult radv_BindBufferMemory(
1077 VkDevice device,
1078 VkBuffer _buffer,
1079 VkDeviceMemory _memory,
1080 VkDeviceSize memoryOffset)
1081 {
1082 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1083 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1084
1085 if (mem) {
1086 buffer->bo = mem->bo;
1087 buffer->offset = memoryOffset;
1088 } else {
1089 buffer->bo = NULL;
1090 buffer->offset = 0;
1091 }
1092
1093 return VK_SUCCESS;
1094 }
1095
1096 VkResult radv_BindImageMemory(
1097 VkDevice device,
1098 VkImage _image,
1099 VkDeviceMemory _memory,
1100 VkDeviceSize memoryOffset)
1101 {
1102 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1103 RADV_FROM_HANDLE(radv_image, image, _image);
1104
1105 if (mem) {
1106 image->bo = mem->bo;
1107 image->offset = memoryOffset;
1108 } else {
1109 image->bo = NULL;
1110 image->offset = 0;
1111 }
1112
1113 return VK_SUCCESS;
1114 }
1115
1116 VkResult radv_QueueBindSparse(
1117 VkQueue queue,
1118 uint32_t bindInfoCount,
1119 const VkBindSparseInfo* pBindInfo,
1120 VkFence fence)
1121 {
1122 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER);
1123 }
1124
1125 VkResult radv_CreateFence(
1126 VkDevice _device,
1127 const VkFenceCreateInfo* pCreateInfo,
1128 const VkAllocationCallbacks* pAllocator,
1129 VkFence* pFence)
1130 {
1131 RADV_FROM_HANDLE(radv_device, device, _device);
1132 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
1133 sizeof(*fence), 8,
1134 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1135
1136 if (!fence)
1137 return VK_ERROR_OUT_OF_HOST_MEMORY;
1138
1139 memset(fence, 0, sizeof(*fence));
1140 fence->submitted = false;
1141 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
1142 fence->fence = device->ws->create_fence();
1143
1144
1145 *pFence = radv_fence_to_handle(fence);
1146
1147 return VK_SUCCESS;
1148 }
1149
1150 void radv_DestroyFence(
1151 VkDevice _device,
1152 VkFence _fence,
1153 const VkAllocationCallbacks* pAllocator)
1154 {
1155 RADV_FROM_HANDLE(radv_device, device, _device);
1156 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1157
1158 if (!fence)
1159 return;
1160 device->ws->destroy_fence(fence->fence);
1161 vk_free2(&device->alloc, pAllocator, fence);
1162 }
1163
1164 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
1165 {
1166 uint64_t current_time;
1167 struct timespec tv;
1168
1169 clock_gettime(CLOCK_MONOTONIC, &tv);
1170 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
1171
1172 timeout = MIN2(UINT64_MAX - current_time, timeout);
1173
1174 return current_time + timeout;
1175 }
1176
1177 VkResult radv_WaitForFences(
1178 VkDevice _device,
1179 uint32_t fenceCount,
1180 const VkFence* pFences,
1181 VkBool32 waitAll,
1182 uint64_t timeout)
1183 {
1184 RADV_FROM_HANDLE(radv_device, device, _device);
1185 timeout = radv_get_absolute_timeout(timeout);
1186
1187 if (!waitAll && fenceCount > 1) {
1188 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
1189 }
1190
1191 for (uint32_t i = 0; i < fenceCount; ++i) {
1192 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1193 bool expired = false;
1194
1195 if (fence->signalled)
1196 continue;
1197
1198 if (!fence->submitted)
1199 return VK_TIMEOUT;
1200
1201 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
1202 if (!expired)
1203 return VK_TIMEOUT;
1204
1205 fence->signalled = true;
1206 }
1207
1208 return VK_SUCCESS;
1209 }
1210
1211 VkResult radv_ResetFences(VkDevice device,
1212 uint32_t fenceCount,
1213 const VkFence *pFences)
1214 {
1215 for (unsigned i = 0; i < fenceCount; ++i) {
1216 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1217 fence->submitted = fence->signalled = false;
1218 }
1219
1220 return VK_SUCCESS;
1221 }
1222
1223 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
1224 {
1225 RADV_FROM_HANDLE(radv_device, device, _device);
1226 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1227
1228 if (fence->signalled)
1229 return VK_SUCCESS;
1230 if (!fence->submitted)
1231 return VK_NOT_READY;
1232
1233 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
1234 return VK_NOT_READY;
1235
1236 return VK_SUCCESS;
1237 }
1238
1239
1240 // Queue semaphore functions
1241
1242 VkResult radv_CreateSemaphore(
1243 VkDevice device,
1244 const VkSemaphoreCreateInfo* pCreateInfo,
1245 const VkAllocationCallbacks* pAllocator,
1246 VkSemaphore* pSemaphore)
1247 {
1248 /* The DRM execbuffer ioctl always execute in-oder, even between different
1249 * rings. As such, there's nothing to do for the user space semaphore.
1250 */
1251
1252 *pSemaphore = (VkSemaphore)1;
1253
1254 return VK_SUCCESS;
1255 }
1256
1257 void radv_DestroySemaphore(
1258 VkDevice device,
1259 VkSemaphore semaphore,
1260 const VkAllocationCallbacks* pAllocator)
1261 {
1262 }
1263
1264 VkResult radv_CreateEvent(
1265 VkDevice _device,
1266 const VkEventCreateInfo* pCreateInfo,
1267 const VkAllocationCallbacks* pAllocator,
1268 VkEvent* pEvent)
1269 {
1270 RADV_FROM_HANDLE(radv_device, device, _device);
1271 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
1272 sizeof(*event), 8,
1273 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1274
1275 if (!event)
1276 return VK_ERROR_OUT_OF_HOST_MEMORY;
1277
1278 event->bo = device->ws->buffer_create(device->ws, 8, 8,
1279 RADEON_DOMAIN_GTT,
1280 RADEON_FLAG_CPU_ACCESS);
1281 if (!event->bo) {
1282 vk_free2(&device->alloc, pAllocator, event);
1283 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1284 }
1285
1286 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
1287
1288 *pEvent = radv_event_to_handle(event);
1289
1290 return VK_SUCCESS;
1291 }
1292
1293 void radv_DestroyEvent(
1294 VkDevice _device,
1295 VkEvent _event,
1296 const VkAllocationCallbacks* pAllocator)
1297 {
1298 RADV_FROM_HANDLE(radv_device, device, _device);
1299 RADV_FROM_HANDLE(radv_event, event, _event);
1300
1301 if (!event)
1302 return;
1303 device->ws->buffer_destroy(event->bo);
1304 vk_free2(&device->alloc, pAllocator, event);
1305 }
1306
1307 VkResult radv_GetEventStatus(
1308 VkDevice _device,
1309 VkEvent _event)
1310 {
1311 RADV_FROM_HANDLE(radv_event, event, _event);
1312
1313 if (*event->map == 1)
1314 return VK_EVENT_SET;
1315 return VK_EVENT_RESET;
1316 }
1317
1318 VkResult radv_SetEvent(
1319 VkDevice _device,
1320 VkEvent _event)
1321 {
1322 RADV_FROM_HANDLE(radv_event, event, _event);
1323 *event->map = 1;
1324
1325 return VK_SUCCESS;
1326 }
1327
1328 VkResult radv_ResetEvent(
1329 VkDevice _device,
1330 VkEvent _event)
1331 {
1332 RADV_FROM_HANDLE(radv_event, event, _event);
1333 *event->map = 0;
1334
1335 return VK_SUCCESS;
1336 }
1337
1338 VkResult radv_CreateBuffer(
1339 VkDevice _device,
1340 const VkBufferCreateInfo* pCreateInfo,
1341 const VkAllocationCallbacks* pAllocator,
1342 VkBuffer* pBuffer)
1343 {
1344 RADV_FROM_HANDLE(radv_device, device, _device);
1345 struct radv_buffer *buffer;
1346
1347 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
1348
1349 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
1350 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1351 if (buffer == NULL)
1352 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1353
1354 buffer->size = pCreateInfo->size;
1355 buffer->usage = pCreateInfo->usage;
1356 buffer->bo = NULL;
1357 buffer->offset = 0;
1358
1359 *pBuffer = radv_buffer_to_handle(buffer);
1360
1361 return VK_SUCCESS;
1362 }
1363
1364 void radv_DestroyBuffer(
1365 VkDevice _device,
1366 VkBuffer _buffer,
1367 const VkAllocationCallbacks* pAllocator)
1368 {
1369 RADV_FROM_HANDLE(radv_device, device, _device);
1370 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1371
1372 if (!buffer)
1373 return;
1374
1375 vk_free2(&device->alloc, pAllocator, buffer);
1376 }
1377
1378 static inline unsigned
1379 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
1380 {
1381 if (stencil)
1382 return image->surface.stencil_tiling_index[level];
1383 else
1384 return image->surface.tiling_index[level];
1385 }
1386
1387 static void
1388 radv_initialise_color_surface(struct radv_device *device,
1389 struct radv_color_buffer_info *cb,
1390 struct radv_image_view *iview)
1391 {
1392 const struct vk_format_description *desc;
1393 unsigned ntype, format, swap, endian;
1394 unsigned blend_clamp = 0, blend_bypass = 0;
1395 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
1396 uint64_t va;
1397 const struct radeon_surf *surf = &iview->image->surface;
1398 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
1399
1400 desc = vk_format_description(iview->vk_format);
1401
1402 memset(cb, 0, sizeof(*cb));
1403
1404 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1405 va += level_info->offset;
1406 cb->cb_color_base = va >> 8;
1407
1408 /* CMASK variables */
1409 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1410 va += iview->image->cmask.offset;
1411 cb->cb_color_cmask = va >> 8;
1412 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
1413
1414 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1415 va += iview->image->dcc_offset;
1416 cb->cb_dcc_base = va >> 8;
1417
1418 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
1419 S_028C6C_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1420
1421 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
1422 pitch_tile_max = level_info->nblk_x / 8 - 1;
1423 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
1424 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
1425
1426 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
1427 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
1428
1429 /* Intensity is implemented as Red, so treat it that way. */
1430 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
1431 S_028C74_TILE_MODE_INDEX(tile_mode_index);
1432
1433 if (iview->image->samples > 1) {
1434 unsigned log_samples = util_logbase2(iview->image->samples);
1435
1436 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1437 S_028C74_NUM_FRAGMENTS(log_samples);
1438 }
1439
1440 if (iview->image->fmask.size) {
1441 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
1442 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1443 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
1444 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
1445 cb->cb_color_fmask = va >> 8;
1446 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
1447 } else {
1448 /* This must be set for fast clear to work without FMASK. */
1449 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1450 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
1451 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1452 cb->cb_color_fmask = cb->cb_color_base;
1453 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
1454 }
1455
1456 ntype = radv_translate_color_numformat(iview->vk_format,
1457 desc,
1458 vk_format_get_first_non_void_channel(iview->vk_format));
1459 format = radv_translate_colorformat(iview->vk_format);
1460 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
1461 radv_finishme("Illegal color\n");
1462 swap = radv_translate_colorswap(iview->vk_format, FALSE);
1463 endian = radv_colorformat_endian_swap(format);
1464
1465 /* blend clamp should be set for all NORM/SRGB types */
1466 if (ntype == V_028C70_NUMBER_UNORM ||
1467 ntype == V_028C70_NUMBER_SNORM ||
1468 ntype == V_028C70_NUMBER_SRGB)
1469 blend_clamp = 1;
1470
1471 /* set blend bypass according to docs if SINT/UINT or
1472 8/24 COLOR variants */
1473 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1474 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1475 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1476 blend_clamp = 0;
1477 blend_bypass = 1;
1478 }
1479 #if 0
1480 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
1481 (format == V_028C70_COLOR_8 ||
1482 format == V_028C70_COLOR_8_8 ||
1483 format == V_028C70_COLOR_8_8_8_8))
1484 ->color_is_int8 = true;
1485 #endif
1486 cb->cb_color_info = S_028C70_FORMAT(format) |
1487 S_028C70_COMP_SWAP(swap) |
1488 S_028C70_BLEND_CLAMP(blend_clamp) |
1489 S_028C70_BLEND_BYPASS(blend_bypass) |
1490 S_028C70_SIMPLE_FLOAT(1) |
1491 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
1492 ntype != V_028C70_NUMBER_SNORM &&
1493 ntype != V_028C70_NUMBER_SRGB &&
1494 format != V_028C70_COLOR_8_24 &&
1495 format != V_028C70_COLOR_24_8) |
1496 S_028C70_NUMBER_TYPE(ntype) |
1497 S_028C70_ENDIAN(endian);
1498 if (iview->image->samples > 1)
1499 if (iview->image->fmask.size)
1500 cb->cb_color_info |= S_028C70_COMPRESSION(1);
1501
1502 if (iview->image->cmask.size && device->allow_fast_clears)
1503 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
1504
1505 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
1506 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
1507
1508 if (device->instance->physicalDevice.rad_info.chip_class >= VI) {
1509 unsigned max_uncompressed_block_size = 2;
1510 if (iview->image->samples > 1) {
1511 if (iview->image->surface.bpe == 1)
1512 max_uncompressed_block_size = 0;
1513 else if (iview->image->surface.bpe == 2)
1514 max_uncompressed_block_size = 1;
1515 }
1516
1517 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
1518 S_028C78_INDEPENDENT_64B_BLOCKS(1);
1519 }
1520
1521 /* This must be set for fast clear to work without FMASK. */
1522 if (!iview->image->fmask.size &&
1523 device->instance->physicalDevice.rad_info.chip_class == SI) {
1524 unsigned bankh = util_logbase2(iview->image->surface.bankh);
1525 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1526 }
1527 }
1528
1529 static void
1530 radv_initialise_ds_surface(struct radv_device *device,
1531 struct radv_ds_buffer_info *ds,
1532 struct radv_image_view *iview)
1533 {
1534 unsigned level = iview->base_mip;
1535 unsigned format;
1536 uint64_t va, s_offs, z_offs;
1537 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
1538 memset(ds, 0, sizeof(*ds));
1539 switch (iview->vk_format) {
1540 case VK_FORMAT_D24_UNORM_S8_UINT:
1541 case VK_FORMAT_X8_D24_UNORM_PACK32:
1542 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1543 ds->offset_scale = 2.0f;
1544 break;
1545 case VK_FORMAT_D16_UNORM:
1546 case VK_FORMAT_D16_UNORM_S8_UINT:
1547 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1548 ds->offset_scale = 4.0f;
1549 break;
1550 case VK_FORMAT_D32_SFLOAT:
1551 case VK_FORMAT_D32_SFLOAT_S8_UINT:
1552 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1553 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1554 ds->offset_scale = 1.0f;
1555 break;
1556 default:
1557 break;
1558 }
1559
1560 format = radv_translate_dbformat(iview->vk_format);
1561 if (format == V_028040_Z_INVALID) {
1562 fprintf(stderr, "Invalid DB format: %d, disabling DB.\n", iview->vk_format);
1563 }
1564
1565 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1566 s_offs = z_offs = va;
1567 z_offs += iview->image->surface.level[level].offset;
1568 s_offs += iview->image->surface.stencil_level[level].offset;
1569
1570 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
1571 S_028008_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1572 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1573 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
1574
1575 if (iview->image->samples > 1)
1576 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
1577
1578 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
1579 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
1580 else
1581 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1582
1583 if (device->instance->physicalDevice.rad_info.chip_class >= CIK) {
1584 struct radeon_info *info = &device->instance->physicalDevice.rad_info;
1585 unsigned tiling_index = iview->image->surface.tiling_index[level];
1586 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
1587 unsigned macro_index = iview->image->surface.macro_tile_index;
1588 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
1589 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
1590 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
1591
1592 ds->db_depth_info |=
1593 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
1594 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
1595 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
1596 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
1597 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
1598 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
1599 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
1600 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
1601 } else {
1602 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
1603 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1604 tile_mode_index = si_tile_mode_index(iview->image, level, true);
1605 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1606 }
1607
1608 if (iview->image->htile.size && !level) {
1609 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1610 S_028040_ALLOW_EXPCLEAR(1);
1611
1612 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
1613 /* Workaround: For a not yet understood reason, the
1614 * combination of MSAA, fast stencil clear and stencil
1615 * decompress messes with subsequent stencil buffer
1616 * uses. Problem was reproduced on Verde, Bonaire,
1617 * Tonga, and Carrizo.
1618 *
1619 * Disabling EXPCLEAR works around the problem.
1620 *
1621 * Check piglit's arb_texture_multisample-stencil-clear
1622 * test if you want to try changing this.
1623 */
1624 if (iview->image->samples <= 1)
1625 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
1626 } else
1627 /* Use all of the htile_buffer for depth if there's no stencil. */
1628 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1629
1630 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
1631 iview->image->htile.offset;
1632 ds->db_htile_data_base = va >> 8;
1633 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
1634 } else {
1635 ds->db_htile_data_base = 0;
1636 ds->db_htile_surface = 0;
1637 }
1638
1639 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
1640 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
1641
1642 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
1643 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
1644 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
1645 }
1646
1647 VkResult radv_CreateFramebuffer(
1648 VkDevice _device,
1649 const VkFramebufferCreateInfo* pCreateInfo,
1650 const VkAllocationCallbacks* pAllocator,
1651 VkFramebuffer* pFramebuffer)
1652 {
1653 RADV_FROM_HANDLE(radv_device, device, _device);
1654 struct radv_framebuffer *framebuffer;
1655
1656 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
1657
1658 size_t size = sizeof(*framebuffer) +
1659 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
1660 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
1661 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1662 if (framebuffer == NULL)
1663 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1664
1665 framebuffer->attachment_count = pCreateInfo->attachmentCount;
1666 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
1667 VkImageView _iview = pCreateInfo->pAttachments[i];
1668 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
1669 framebuffer->attachments[i].attachment = iview;
1670 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
1671 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
1672 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
1673 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
1674 }
1675 }
1676
1677 framebuffer->width = pCreateInfo->width;
1678 framebuffer->height = pCreateInfo->height;
1679 framebuffer->layers = pCreateInfo->layers;
1680
1681 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
1682 return VK_SUCCESS;
1683 }
1684
1685 void radv_DestroyFramebuffer(
1686 VkDevice _device,
1687 VkFramebuffer _fb,
1688 const VkAllocationCallbacks* pAllocator)
1689 {
1690 RADV_FROM_HANDLE(radv_device, device, _device);
1691 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
1692
1693 if (!fb)
1694 return;
1695 vk_free2(&device->alloc, pAllocator, fb);
1696 }
1697
1698 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
1699 {
1700 switch (address_mode) {
1701 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
1702 return V_008F30_SQ_TEX_WRAP;
1703 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
1704 return V_008F30_SQ_TEX_MIRROR;
1705 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
1706 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1707 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
1708 return V_008F30_SQ_TEX_CLAMP_BORDER;
1709 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
1710 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1711 default:
1712 unreachable("illegal tex wrap mode");
1713 break;
1714 }
1715 }
1716
1717 static unsigned
1718 radv_tex_compare(VkCompareOp op)
1719 {
1720 switch (op) {
1721 case VK_COMPARE_OP_NEVER:
1722 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1723 case VK_COMPARE_OP_LESS:
1724 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1725 case VK_COMPARE_OP_EQUAL:
1726 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1727 case VK_COMPARE_OP_LESS_OR_EQUAL:
1728 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1729 case VK_COMPARE_OP_GREATER:
1730 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1731 case VK_COMPARE_OP_NOT_EQUAL:
1732 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1733 case VK_COMPARE_OP_GREATER_OR_EQUAL:
1734 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1735 case VK_COMPARE_OP_ALWAYS:
1736 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1737 default:
1738 unreachable("illegal compare mode");
1739 break;
1740 }
1741 }
1742
1743 static unsigned
1744 radv_tex_filter(VkFilter filter, unsigned max_ansio)
1745 {
1746 switch (filter) {
1747 case VK_FILTER_NEAREST:
1748 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
1749 V_008F38_SQ_TEX_XY_FILTER_POINT);
1750 case VK_FILTER_LINEAR:
1751 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
1752 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
1753 case VK_FILTER_CUBIC_IMG:
1754 default:
1755 fprintf(stderr, "illegal texture filter");
1756 return 0;
1757 }
1758 }
1759
1760 static unsigned
1761 radv_tex_mipfilter(VkSamplerMipmapMode mode)
1762 {
1763 switch (mode) {
1764 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
1765 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1766 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
1767 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1768 default:
1769 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1770 }
1771 }
1772
1773 static unsigned
1774 radv_tex_bordercolor(VkBorderColor bcolor)
1775 {
1776 switch (bcolor) {
1777 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
1778 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
1779 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
1780 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
1781 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
1782 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
1783 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
1784 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
1785 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
1786 default:
1787 break;
1788 }
1789 return 0;
1790 }
1791
1792 static unsigned
1793 radv_tex_aniso_filter(unsigned filter)
1794 {
1795 if (filter < 2)
1796 return 0;
1797 if (filter < 4)
1798 return 1;
1799 if (filter < 8)
1800 return 2;
1801 if (filter < 16)
1802 return 3;
1803 return 4;
1804 }
1805
1806 static void
1807 radv_init_sampler(struct radv_device *device,
1808 struct radv_sampler *sampler,
1809 const VkSamplerCreateInfo *pCreateInfo)
1810 {
1811 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
1812 (uint32_t) pCreateInfo->maxAnisotropy : 0;
1813 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
1814 bool is_vi = (device->instance->physicalDevice.rad_info.chip_class >= VI);
1815
1816 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
1817 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
1818 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
1819 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
1820 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
1821 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
1822 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
1823 S_008F30_ANISO_BIAS(max_aniso_ratio) |
1824 S_008F30_DISABLE_CUBE_WRAP(0) |
1825 S_008F30_COMPAT_MODE(is_vi));
1826 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
1827 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
1828 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
1829 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
1830 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
1831 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
1832 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
1833 S_008F38_MIP_POINT_PRECLAMP(1) |
1834 S_008F38_DISABLE_LSB_CEIL(1) |
1835 S_008F38_FILTER_PREC_FIX(1) |
1836 S_008F38_ANISO_OVERRIDE(is_vi));
1837 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
1838 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
1839 }
1840
1841 VkResult radv_CreateSampler(
1842 VkDevice _device,
1843 const VkSamplerCreateInfo* pCreateInfo,
1844 const VkAllocationCallbacks* pAllocator,
1845 VkSampler* pSampler)
1846 {
1847 RADV_FROM_HANDLE(radv_device, device, _device);
1848 struct radv_sampler *sampler;
1849
1850 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
1851
1852 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
1853 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1854 if (!sampler)
1855 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1856
1857 radv_init_sampler(device, sampler, pCreateInfo);
1858 *pSampler = radv_sampler_to_handle(sampler);
1859
1860 return VK_SUCCESS;
1861 }
1862
1863 void radv_DestroySampler(
1864 VkDevice _device,
1865 VkSampler _sampler,
1866 const VkAllocationCallbacks* pAllocator)
1867 {
1868 RADV_FROM_HANDLE(radv_device, device, _device);
1869 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
1870
1871 if (!sampler)
1872 return;
1873 vk_free2(&device->alloc, pAllocator, sampler);
1874 }