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radv: use correct .specVersion for extensions
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_private.h"
33 #include "util/strtod.h"
34
35 #include <xf86drm.h>
36 #include <amdgpu.h>
37 #include <amdgpu_drm.h>
38 #include "amdgpu_id.h"
39 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
40 #include "ac_llvm_util.h"
41 #include "vk_format.h"
42 #include "sid.h"
43 #include "radv_timestamp.h"
44 #include "util/debug.h"
45 struct radv_dispatch_table dtable;
46
47 static VkResult
48 radv_physical_device_init(struct radv_physical_device *device,
49 struct radv_instance *instance,
50 const char *path)
51 {
52 VkResult result;
53 drmVersionPtr version;
54 int fd;
55
56 fd = open(path, O_RDWR | O_CLOEXEC);
57 if (fd < 0)
58 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
59 "failed to open %s: %m", path);
60
61 version = drmGetVersion(fd);
62 if (!version) {
63 close(fd);
64 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
65 "failed to get version %s: %m", path);
66 }
67
68 if (strcmp(version->name, "amdgpu")) {
69 drmFreeVersion(version);
70 close(fd);
71 return VK_ERROR_INCOMPATIBLE_DRIVER;
72 }
73 drmFreeVersion(version);
74
75 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
76 device->instance = instance;
77 assert(strlen(path) < ARRAY_SIZE(device->path));
78 strncpy(device->path, path, ARRAY_SIZE(device->path));
79
80 device->ws = radv_amdgpu_winsys_create(fd);
81 if (!device->ws) {
82 result = VK_ERROR_INCOMPATIBLE_DRIVER;
83 goto fail;
84 }
85 device->ws->query_info(device->ws, &device->rad_info);
86 result = radv_init_wsi(device);
87 if (result != VK_SUCCESS) {
88 device->ws->destroy(device->ws);
89 goto fail;
90 }
91
92 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
93 device->name = device->rad_info.name;
94 return VK_SUCCESS;
95
96 fail:
97 close(fd);
98 return result;
99 }
100
101 static void
102 radv_physical_device_finish(struct radv_physical_device *device)
103 {
104 radv_finish_wsi(device);
105 device->ws->destroy(device->ws);
106 }
107
108 static const VkExtensionProperties global_extensions[] = {
109 {
110 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
111 .specVersion = 25,
112 },
113 #ifdef VK_USE_PLATFORM_XCB_KHR
114 {
115 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
116 .specVersion = 6,
117 },
118 #endif
119 #ifdef VK_USE_PLATFORM_XLIB_KHR
120 {
121 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
122 .specVersion = 6,
123 },
124 #endif
125 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
126 {
127 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
128 .specVersion = 5,
129 },
130 #endif
131 };
132
133 static const VkExtensionProperties device_extensions[] = {
134 {
135 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
136 .specVersion = 68,
137 },
138 };
139
140 static void *
141 default_alloc_func(void *pUserData, size_t size, size_t align,
142 VkSystemAllocationScope allocationScope)
143 {
144 return malloc(size);
145 }
146
147 static void *
148 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
149 size_t align, VkSystemAllocationScope allocationScope)
150 {
151 return realloc(pOriginal, size);
152 }
153
154 static void
155 default_free_func(void *pUserData, void *pMemory)
156 {
157 free(pMemory);
158 }
159
160 static const VkAllocationCallbacks default_alloc = {
161 .pUserData = NULL,
162 .pfnAllocation = default_alloc_func,
163 .pfnReallocation = default_realloc_func,
164 .pfnFree = default_free_func,
165 };
166
167 VkResult radv_CreateInstance(
168 const VkInstanceCreateInfo* pCreateInfo,
169 const VkAllocationCallbacks* pAllocator,
170 VkInstance* pInstance)
171 {
172 struct radv_instance *instance;
173
174 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
175
176 uint32_t client_version;
177 if (pCreateInfo->pApplicationInfo &&
178 pCreateInfo->pApplicationInfo->apiVersion != 0) {
179 client_version = pCreateInfo->pApplicationInfo->apiVersion;
180 } else {
181 client_version = VK_MAKE_VERSION(1, 0, 0);
182 }
183
184 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
185 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
186 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
187 "Client requested version %d.%d.%d",
188 VK_VERSION_MAJOR(client_version),
189 VK_VERSION_MINOR(client_version),
190 VK_VERSION_PATCH(client_version));
191 }
192
193 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
194 bool found = false;
195 for (uint32_t j = 0; j < ARRAY_SIZE(global_extensions); j++) {
196 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
197 global_extensions[j].extensionName) == 0) {
198 found = true;
199 break;
200 }
201 }
202 if (!found)
203 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
204 }
205
206 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
207 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
208 if (!instance)
209 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
210
211 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
212
213 if (pAllocator)
214 instance->alloc = *pAllocator;
215 else
216 instance->alloc = default_alloc;
217
218 instance->apiVersion = client_version;
219 instance->physicalDeviceCount = -1;
220
221 _mesa_locale_init();
222
223 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
224
225 *pInstance = radv_instance_to_handle(instance);
226
227 return VK_SUCCESS;
228 }
229
230 void radv_DestroyInstance(
231 VkInstance _instance,
232 const VkAllocationCallbacks* pAllocator)
233 {
234 RADV_FROM_HANDLE(radv_instance, instance, _instance);
235
236 if (instance->physicalDeviceCount > 0) {
237 /* We support at most one physical device. */
238 assert(instance->physicalDeviceCount == 1);
239 radv_physical_device_finish(&instance->physicalDevice);
240 }
241
242 VG(VALGRIND_DESTROY_MEMPOOL(instance));
243
244 _mesa_locale_fini();
245
246 vk_free(&instance->alloc, instance);
247 }
248
249 VkResult radv_EnumeratePhysicalDevices(
250 VkInstance _instance,
251 uint32_t* pPhysicalDeviceCount,
252 VkPhysicalDevice* pPhysicalDevices)
253 {
254 RADV_FROM_HANDLE(radv_instance, instance, _instance);
255 VkResult result;
256
257 if (instance->physicalDeviceCount < 0) {
258 char path[20];
259 for (unsigned i = 0; i < 8; i++) {
260 snprintf(path, sizeof(path), "/dev/dri/renderD%d", 128 + i);
261 result = radv_physical_device_init(&instance->physicalDevice,
262 instance, path);
263 if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
264 break;
265 }
266
267 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
268 instance->physicalDeviceCount = 0;
269 } else if (result == VK_SUCCESS) {
270 instance->physicalDeviceCount = 1;
271 } else {
272 return result;
273 }
274 }
275
276 /* pPhysicalDeviceCount is an out parameter if pPhysicalDevices is NULL;
277 * otherwise it's an inout parameter.
278 *
279 * The Vulkan spec (git aaed022) says:
280 *
281 * pPhysicalDeviceCount is a pointer to an unsigned integer variable
282 * that is initialized with the number of devices the application is
283 * prepared to receive handles to. pname:pPhysicalDevices is pointer to
284 * an array of at least this many VkPhysicalDevice handles [...].
285 *
286 * Upon success, if pPhysicalDevices is NULL, vkEnumeratePhysicalDevices
287 * overwrites the contents of the variable pointed to by
288 * pPhysicalDeviceCount with the number of physical devices in in the
289 * instance; otherwise, vkEnumeratePhysicalDevices overwrites
290 * pPhysicalDeviceCount with the number of physical handles written to
291 * pPhysicalDevices.
292 */
293 if (!pPhysicalDevices) {
294 *pPhysicalDeviceCount = instance->physicalDeviceCount;
295 } else if (*pPhysicalDeviceCount >= 1) {
296 pPhysicalDevices[0] = radv_physical_device_to_handle(&instance->physicalDevice);
297 *pPhysicalDeviceCount = 1;
298 } else if (*pPhysicalDeviceCount < instance->physicalDeviceCount) {
299 return VK_INCOMPLETE;
300 } else {
301 *pPhysicalDeviceCount = 0;
302 }
303
304 return VK_SUCCESS;
305 }
306
307 void radv_GetPhysicalDeviceFeatures(
308 VkPhysicalDevice physicalDevice,
309 VkPhysicalDeviceFeatures* pFeatures)
310 {
311 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
312
313 memset(pFeatures, 0, sizeof(*pFeatures));
314
315 *pFeatures = (VkPhysicalDeviceFeatures) {
316 .robustBufferAccess = true,
317 .fullDrawIndexUint32 = true,
318 .imageCubeArray = true,
319 .independentBlend = true,
320 .geometryShader = false,
321 .tessellationShader = false,
322 .sampleRateShading = false,
323 .dualSrcBlend = true,
324 .logicOp = true,
325 .multiDrawIndirect = true,
326 .drawIndirectFirstInstance = true,
327 .depthClamp = true,
328 .depthBiasClamp = true,
329 .fillModeNonSolid = true,
330 .depthBounds = true,
331 .wideLines = true,
332 .largePoints = true,
333 .alphaToOne = true,
334 .multiViewport = false,
335 .samplerAnisotropy = false, /* FINISHME */
336 .textureCompressionETC2 = false,
337 .textureCompressionASTC_LDR = false,
338 .textureCompressionBC = true,
339 .occlusionQueryPrecise = true,
340 .pipelineStatisticsQuery = false,
341 .vertexPipelineStoresAndAtomics = true,
342 .fragmentStoresAndAtomics = true,
343 .shaderTessellationAndGeometryPointSize = true,
344 .shaderImageGatherExtended = false,
345 .shaderStorageImageExtendedFormats = false,
346 .shaderStorageImageMultisample = false,
347 .shaderUniformBufferArrayDynamicIndexing = true,
348 .shaderSampledImageArrayDynamicIndexing = true,
349 .shaderStorageBufferArrayDynamicIndexing = true,
350 .shaderStorageImageArrayDynamicIndexing = true,
351 .shaderStorageImageReadWithoutFormat = false,
352 .shaderStorageImageWriteWithoutFormat = true,
353 .shaderClipDistance = true,
354 .shaderCullDistance = true,
355 .shaderFloat64 = false,
356 .shaderInt64 = false,
357 .shaderInt16 = false,
358 .alphaToOne = true,
359 .variableMultisampleRate = false,
360 .inheritedQueries = false,
361 };
362 }
363
364 void
365 radv_device_get_cache_uuid(void *uuid)
366 {
367 memset(uuid, 0, VK_UUID_SIZE);
368 snprintf(uuid, VK_UUID_SIZE, "radv-%s", RADV_TIMESTAMP);
369 }
370
371 void radv_GetPhysicalDeviceProperties(
372 VkPhysicalDevice physicalDevice,
373 VkPhysicalDeviceProperties* pProperties)
374 {
375 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
376 VkSampleCountFlags sample_counts = 0xf;
377 VkPhysicalDeviceLimits limits = {
378 .maxImageDimension1D = (1 << 14),
379 .maxImageDimension2D = (1 << 14),
380 .maxImageDimension3D = (1 << 11),
381 .maxImageDimensionCube = (1 << 14),
382 .maxImageArrayLayers = (1 << 11),
383 .maxTexelBufferElements = 128 * 1024 * 1024,
384 .maxUniformBufferRange = UINT32_MAX,
385 .maxStorageBufferRange = UINT32_MAX,
386 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
387 .maxMemoryAllocationCount = UINT32_MAX,
388 .maxSamplerAllocationCount = 64 * 1024,
389 .bufferImageGranularity = 64, /* A cache line */
390 .sparseAddressSpaceSize = 0,
391 .maxBoundDescriptorSets = MAX_SETS,
392 .maxPerStageDescriptorSamplers = 64,
393 .maxPerStageDescriptorUniformBuffers = 64,
394 .maxPerStageDescriptorStorageBuffers = 64,
395 .maxPerStageDescriptorSampledImages = 64,
396 .maxPerStageDescriptorStorageImages = 64,
397 .maxPerStageDescriptorInputAttachments = 64,
398 .maxPerStageResources = 128,
399 .maxDescriptorSetSamplers = 256,
400 .maxDescriptorSetUniformBuffers = 256,
401 .maxDescriptorSetUniformBuffersDynamic = 256,
402 .maxDescriptorSetStorageBuffers = 256,
403 .maxDescriptorSetStorageBuffersDynamic = 256,
404 .maxDescriptorSetSampledImages = 256,
405 .maxDescriptorSetStorageImages = 256,
406 .maxDescriptorSetInputAttachments = 256,
407 .maxVertexInputAttributes = 32,
408 .maxVertexInputBindings = 32,
409 .maxVertexInputAttributeOffset = 2047,
410 .maxVertexInputBindingStride = 2048,
411 .maxVertexOutputComponents = 128,
412 .maxTessellationGenerationLevel = 0,
413 .maxTessellationPatchSize = 0,
414 .maxTessellationControlPerVertexInputComponents = 0,
415 .maxTessellationControlPerVertexOutputComponents = 0,
416 .maxTessellationControlPerPatchOutputComponents = 0,
417 .maxTessellationControlTotalOutputComponents = 0,
418 .maxTessellationEvaluationInputComponents = 0,
419 .maxTessellationEvaluationOutputComponents = 0,
420 .maxGeometryShaderInvocations = 32,
421 .maxGeometryInputComponents = 64,
422 .maxGeometryOutputComponents = 128,
423 .maxGeometryOutputVertices = 256,
424 .maxGeometryTotalOutputComponents = 1024,
425 .maxFragmentInputComponents = 128,
426 .maxFragmentOutputAttachments = 8,
427 .maxFragmentDualSrcAttachments = 2,
428 .maxFragmentCombinedOutputResources = 8,
429 .maxComputeSharedMemorySize = 32768,
430 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
431 .maxComputeWorkGroupInvocations = 16 * 1024,
432 .maxComputeWorkGroupSize = {
433 16 * 1024/*devinfo->max_cs_threads*/,
434 16 * 1024,
435 16 * 1024
436 },
437 .subPixelPrecisionBits = 4 /* FIXME */,
438 .subTexelPrecisionBits = 4 /* FIXME */,
439 .mipmapPrecisionBits = 4 /* FIXME */,
440 .maxDrawIndexedIndexValue = UINT32_MAX,
441 .maxDrawIndirectCount = UINT32_MAX,
442 .maxSamplerLodBias = 16,
443 .maxSamplerAnisotropy = 16,
444 .maxViewports = MAX_VIEWPORTS,
445 .maxViewportDimensions = { (1 << 14), (1 << 14) },
446 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
447 .viewportSubPixelBits = 13, /* We take a float? */
448 .minMemoryMapAlignment = 4096, /* A page */
449 .minTexelBufferOffsetAlignment = 1,
450 .minUniformBufferOffsetAlignment = 4,
451 .minStorageBufferOffsetAlignment = 4,
452 .minTexelOffset = -8,
453 .maxTexelOffset = 7,
454 .minTexelGatherOffset = -8,
455 .maxTexelGatherOffset = 7,
456 .minInterpolationOffset = 0, /* FIXME */
457 .maxInterpolationOffset = 0, /* FIXME */
458 .subPixelInterpolationOffsetBits = 0, /* FIXME */
459 .maxFramebufferWidth = (1 << 14),
460 .maxFramebufferHeight = (1 << 14),
461 .maxFramebufferLayers = (1 << 10),
462 .framebufferColorSampleCounts = sample_counts,
463 .framebufferDepthSampleCounts = sample_counts,
464 .framebufferStencilSampleCounts = sample_counts,
465 .framebufferNoAttachmentsSampleCounts = sample_counts,
466 .maxColorAttachments = MAX_RTS,
467 .sampledImageColorSampleCounts = sample_counts,
468 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
469 .sampledImageDepthSampleCounts = sample_counts,
470 .sampledImageStencilSampleCounts = sample_counts,
471 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
472 .maxSampleMaskWords = 1,
473 .timestampComputeAndGraphics = false,
474 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
475 .maxClipDistances = 8,
476 .maxCullDistances = 8,
477 .maxCombinedClipAndCullDistances = 8,
478 .discreteQueuePriorities = 1,
479 .pointSizeRange = { 0.125, 255.875 },
480 .lineWidthRange = { 0.0, 7.9921875 },
481 .pointSizeGranularity = (1.0 / 8.0),
482 .lineWidthGranularity = (1.0 / 128.0),
483 .strictLines = false, /* FINISHME */
484 .standardSampleLocations = true,
485 .optimalBufferCopyOffsetAlignment = 128,
486 .optimalBufferCopyRowPitchAlignment = 128,
487 .nonCoherentAtomSize = 64,
488 };
489
490 *pProperties = (VkPhysicalDeviceProperties) {
491 .apiVersion = VK_MAKE_VERSION(1, 0, 5),
492 .driverVersion = 1,
493 .vendorID = 0x1002,
494 .deviceID = pdevice->rad_info.pci_id,
495 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
496 .limits = limits,
497 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
498 };
499
500 strcpy(pProperties->deviceName, pdevice->name);
501 radv_device_get_cache_uuid(pProperties->pipelineCacheUUID);
502 }
503
504 void radv_GetPhysicalDeviceQueueFamilyProperties(
505 VkPhysicalDevice physicalDevice,
506 uint32_t* pCount,
507 VkQueueFamilyProperties* pQueueFamilyProperties)
508 {
509 if (pQueueFamilyProperties == NULL) {
510 *pCount = 1;
511 return;
512 }
513 assert(*pCount >= 1);
514
515 *pQueueFamilyProperties = (VkQueueFamilyProperties) {
516 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
517 VK_QUEUE_COMPUTE_BIT |
518 VK_QUEUE_TRANSFER_BIT,
519 .queueCount = 1,
520 .timestampValidBits = 64,
521 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
522 };
523 }
524
525 void radv_GetPhysicalDeviceMemoryProperties(
526 VkPhysicalDevice physicalDevice,
527 VkPhysicalDeviceMemoryProperties* pMemoryProperties)
528 {
529 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
530
531 pMemoryProperties->memoryTypeCount = 4;
532 pMemoryProperties->memoryTypes[0] = (VkMemoryType) {
533 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
534 .heapIndex = 0,
535 };
536 pMemoryProperties->memoryTypes[1] = (VkMemoryType) {
537 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
538 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
539 .heapIndex = 2,
540 };
541 pMemoryProperties->memoryTypes[2] = (VkMemoryType) {
542 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
543 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
544 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
545 .heapIndex = 1,
546 };
547 pMemoryProperties->memoryTypes[3] = (VkMemoryType) {
548 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
549 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
550 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
551 .heapIndex = 2,
552 };
553
554 pMemoryProperties->memoryHeapCount = 3;
555 pMemoryProperties->memoryHeaps[0] = (VkMemoryHeap) {
556 .size = physical_device->rad_info.vram_size -
557 physical_device->rad_info.visible_vram_size,
558 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
559 };
560 pMemoryProperties->memoryHeaps[1] = (VkMemoryHeap) {
561 .size = physical_device->rad_info.visible_vram_size,
562 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
563 };
564 pMemoryProperties->memoryHeaps[2] = (VkMemoryHeap) {
565 .size = physical_device->rad_info.gart_size,
566 .flags = 0,
567 };
568 }
569
570 static VkResult
571 radv_queue_init(struct radv_device *device, struct radv_queue *queue)
572 {
573 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
574 queue->device = device;
575
576 return VK_SUCCESS;
577 }
578
579 static void
580 radv_queue_finish(struct radv_queue *queue)
581 {
582 }
583
584 VkResult radv_CreateDevice(
585 VkPhysicalDevice physicalDevice,
586 const VkDeviceCreateInfo* pCreateInfo,
587 const VkAllocationCallbacks* pAllocator,
588 VkDevice* pDevice)
589 {
590 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
591 VkResult result;
592 struct radv_device *device;
593
594 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
595 bool found = false;
596 for (uint32_t j = 0; j < ARRAY_SIZE(device_extensions); j++) {
597 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
598 device_extensions[j].extensionName) == 0) {
599 found = true;
600 break;
601 }
602 }
603 if (!found)
604 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
605 }
606
607 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
608 sizeof(*device), 8,
609 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
610 if (!device)
611 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
612
613 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
614 device->instance = physical_device->instance;
615
616 device->ws = physical_device->ws;
617 if (pAllocator)
618 device->alloc = *pAllocator;
619 else
620 device->alloc = physical_device->instance->alloc;
621
622 device->hw_ctx = device->ws->ctx_create(device->ws);
623 if (!device->hw_ctx) {
624 result = VK_ERROR_OUT_OF_HOST_MEMORY;
625 goto fail_free;
626 }
627
628 radv_queue_init(device, &device->queue);
629
630 result = radv_device_init_meta(device);
631 if (result != VK_SUCCESS) {
632 device->ws->ctx_destroy(device->hw_ctx);
633 goto fail_free;
634 }
635 device->allow_fast_clears = env_var_as_boolean("RADV_FAST_CLEARS", false);
636 device->allow_dcc = !env_var_as_boolean("RADV_DCC_DISABLE", false);
637
638 if (device->allow_fast_clears && device->allow_dcc)
639 radv_finishme("DCC fast clears have not been tested\n");
640
641 radv_device_init_msaa(device);
642 device->empty_cs = device->ws->cs_create(device->ws, RING_GFX);
643 radeon_emit(device->empty_cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
644 radeon_emit(device->empty_cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
645 radeon_emit(device->empty_cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
646 device->ws->cs_finalize(device->empty_cs);
647 *pDevice = radv_device_to_handle(device);
648 return VK_SUCCESS;
649 fail_free:
650 vk_free(&device->alloc, device);
651 return result;
652 }
653
654 void radv_DestroyDevice(
655 VkDevice _device,
656 const VkAllocationCallbacks* pAllocator)
657 {
658 RADV_FROM_HANDLE(radv_device, device, _device);
659
660 device->ws->ctx_destroy(device->hw_ctx);
661 radv_queue_finish(&device->queue);
662 radv_device_finish_meta(device);
663
664 vk_free(&device->alloc, device);
665 }
666
667 VkResult radv_EnumerateInstanceExtensionProperties(
668 const char* pLayerName,
669 uint32_t* pPropertyCount,
670 VkExtensionProperties* pProperties)
671 {
672 unsigned i;
673 if (pProperties == NULL) {
674 *pPropertyCount = ARRAY_SIZE(global_extensions);
675 return VK_SUCCESS;
676 }
677
678 for (i = 0; i < *pPropertyCount; i++)
679 memcpy(&pProperties[i], &global_extensions[i], sizeof(VkExtensionProperties));
680
681 *pPropertyCount = i;
682 if (i < ARRAY_SIZE(global_extensions))
683 return VK_INCOMPLETE;
684
685 return VK_SUCCESS;
686 }
687
688 VkResult radv_EnumerateDeviceExtensionProperties(
689 VkPhysicalDevice physicalDevice,
690 const char* pLayerName,
691 uint32_t* pPropertyCount,
692 VkExtensionProperties* pProperties)
693 {
694 unsigned i;
695
696 if (pProperties == NULL) {
697 *pPropertyCount = ARRAY_SIZE(device_extensions);
698 return VK_SUCCESS;
699 }
700
701 for (i = 0; i < *pPropertyCount; i++)
702 memcpy(&pProperties[i], &device_extensions[i], sizeof(VkExtensionProperties));
703
704 *pPropertyCount = i;
705 if (i < ARRAY_SIZE(device_extensions))
706 return VK_INCOMPLETE;
707 return VK_SUCCESS;
708 }
709
710 VkResult radv_EnumerateInstanceLayerProperties(
711 uint32_t* pPropertyCount,
712 VkLayerProperties* pProperties)
713 {
714 if (pProperties == NULL) {
715 *pPropertyCount = 0;
716 return VK_SUCCESS;
717 }
718
719 /* None supported at this time */
720 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
721 }
722
723 VkResult radv_EnumerateDeviceLayerProperties(
724 VkPhysicalDevice physicalDevice,
725 uint32_t* pPropertyCount,
726 VkLayerProperties* pProperties)
727 {
728 if (pProperties == NULL) {
729 *pPropertyCount = 0;
730 return VK_SUCCESS;
731 }
732
733 /* None supported at this time */
734 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
735 }
736
737 void radv_GetDeviceQueue(
738 VkDevice _device,
739 uint32_t queueNodeIndex,
740 uint32_t queueIndex,
741 VkQueue* pQueue)
742 {
743 RADV_FROM_HANDLE(radv_device, device, _device);
744
745 assert(queueIndex == 0);
746
747 *pQueue = radv_queue_to_handle(&device->queue);
748 }
749
750 VkResult radv_QueueSubmit(
751 VkQueue _queue,
752 uint32_t submitCount,
753 const VkSubmitInfo* pSubmits,
754 VkFence _fence)
755 {
756 RADV_FROM_HANDLE(radv_queue, queue, _queue);
757 RADV_FROM_HANDLE(radv_fence, fence, _fence);
758 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
759 struct radeon_winsys_ctx *ctx = queue->device->hw_ctx;
760 int ret;
761
762 for (uint32_t i = 0; i < submitCount; i++) {
763 struct radeon_winsys_cs **cs_array;
764 bool can_patch = true;
765
766 if (!pSubmits[i].commandBufferCount)
767 continue;
768
769 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
770 pSubmits[i].commandBufferCount);
771
772 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
773 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
774 pSubmits[i].pCommandBuffers[j]);
775 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
776
777 cs_array[j] = cmd_buffer->cs;
778 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
779 can_patch = false;
780 }
781 ret = queue->device->ws->cs_submit(ctx, cs_array,
782 pSubmits[i].commandBufferCount,
783 can_patch, base_fence);
784 if (ret)
785 radv_loge("failed to submit CS %d\n", i);
786 free(cs_array);
787 }
788
789 if (fence) {
790 if (!submitCount)
791 ret = queue->device->ws->cs_submit(ctx, &queue->device->empty_cs,
792 1, false, base_fence);
793
794 fence->submitted = true;
795 }
796
797 return VK_SUCCESS;
798 }
799
800 VkResult radv_QueueWaitIdle(
801 VkQueue _queue)
802 {
803 RADV_FROM_HANDLE(radv_queue, queue, _queue);
804
805 queue->device->ws->ctx_wait_idle(queue->device->hw_ctx);
806 return VK_SUCCESS;
807 }
808
809 VkResult radv_DeviceWaitIdle(
810 VkDevice _device)
811 {
812 RADV_FROM_HANDLE(radv_device, device, _device);
813
814 device->ws->ctx_wait_idle(device->hw_ctx);
815 return VK_SUCCESS;
816 }
817
818 PFN_vkVoidFunction radv_GetInstanceProcAddr(
819 VkInstance instance,
820 const char* pName)
821 {
822 return radv_lookup_entrypoint(pName);
823 }
824
825 /* The loader wants us to expose a second GetInstanceProcAddr function
826 * to work around certain LD_PRELOAD issues seen in apps.
827 */
828 PUBLIC
829 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
830 VkInstance instance,
831 const char* pName);
832
833 PUBLIC
834 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
835 VkInstance instance,
836 const char* pName)
837 {
838 return radv_GetInstanceProcAddr(instance, pName);
839 }
840
841 PFN_vkVoidFunction radv_GetDeviceProcAddr(
842 VkDevice device,
843 const char* pName)
844 {
845 return radv_lookup_entrypoint(pName);
846 }
847
848 VkResult radv_AllocateMemory(
849 VkDevice _device,
850 const VkMemoryAllocateInfo* pAllocateInfo,
851 const VkAllocationCallbacks* pAllocator,
852 VkDeviceMemory* pMem)
853 {
854 RADV_FROM_HANDLE(radv_device, device, _device);
855 struct radv_device_memory *mem;
856 VkResult result;
857 enum radeon_bo_domain domain;
858 uint32_t flags = 0;
859 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
860
861 if (pAllocateInfo->allocationSize == 0) {
862 /* Apparently, this is allowed */
863 *pMem = VK_NULL_HANDLE;
864 return VK_SUCCESS;
865 }
866
867 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
868 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
869 if (mem == NULL)
870 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
871
872 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
873 if (pAllocateInfo->memoryTypeIndex == 1 || pAllocateInfo->memoryTypeIndex == 3)
874 domain = RADEON_DOMAIN_GTT;
875 else
876 domain = RADEON_DOMAIN_VRAM;
877
878 if (pAllocateInfo->memoryTypeIndex == 0)
879 flags |= RADEON_FLAG_NO_CPU_ACCESS;
880 else
881 flags |= RADEON_FLAG_CPU_ACCESS;
882
883 if (pAllocateInfo->memoryTypeIndex == 1)
884 flags |= RADEON_FLAG_GTT_WC;
885
886 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 32768,
887 domain, flags);
888
889 if (!mem->bo) {
890 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
891 goto fail;
892 }
893 mem->type_index = pAllocateInfo->memoryTypeIndex;
894
895 *pMem = radv_device_memory_to_handle(mem);
896
897 return VK_SUCCESS;
898
899 fail:
900 vk_free2(&device->alloc, pAllocator, mem);
901
902 return result;
903 }
904
905 void radv_FreeMemory(
906 VkDevice _device,
907 VkDeviceMemory _mem,
908 const VkAllocationCallbacks* pAllocator)
909 {
910 RADV_FROM_HANDLE(radv_device, device, _device);
911 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
912
913 if (mem == NULL)
914 return;
915
916 device->ws->buffer_destroy(mem->bo);
917 mem->bo = NULL;
918
919 vk_free2(&device->alloc, pAllocator, mem);
920 }
921
922 VkResult radv_MapMemory(
923 VkDevice _device,
924 VkDeviceMemory _memory,
925 VkDeviceSize offset,
926 VkDeviceSize size,
927 VkMemoryMapFlags flags,
928 void** ppData)
929 {
930 RADV_FROM_HANDLE(radv_device, device, _device);
931 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
932
933 if (mem == NULL) {
934 *ppData = NULL;
935 return VK_SUCCESS;
936 }
937
938 *ppData = device->ws->buffer_map(mem->bo);
939 if (*ppData) {
940 *ppData += offset;
941 return VK_SUCCESS;
942 }
943
944 return VK_ERROR_MEMORY_MAP_FAILED;
945 }
946
947 void radv_UnmapMemory(
948 VkDevice _device,
949 VkDeviceMemory _memory)
950 {
951 RADV_FROM_HANDLE(radv_device, device, _device);
952 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
953
954 if (mem == NULL)
955 return;
956
957 device->ws->buffer_unmap(mem->bo);
958 }
959
960 VkResult radv_FlushMappedMemoryRanges(
961 VkDevice _device,
962 uint32_t memoryRangeCount,
963 const VkMappedMemoryRange* pMemoryRanges)
964 {
965 return VK_SUCCESS;
966 }
967
968 VkResult radv_InvalidateMappedMemoryRanges(
969 VkDevice _device,
970 uint32_t memoryRangeCount,
971 const VkMappedMemoryRange* pMemoryRanges)
972 {
973 return VK_SUCCESS;
974 }
975
976 void radv_GetBufferMemoryRequirements(
977 VkDevice device,
978 VkBuffer _buffer,
979 VkMemoryRequirements* pMemoryRequirements)
980 {
981 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
982
983 /* The Vulkan spec (git aaed022) says:
984 *
985 * memoryTypeBits is a bitfield and contains one bit set for every
986 * supported memory type for the resource. The bit `1<<i` is set if and
987 * only if the memory type `i` in the VkPhysicalDeviceMemoryProperties
988 * structure for the physical device is supported.
989 *
990 * We support exactly one memory type.
991 */
992 pMemoryRequirements->memoryTypeBits = 0x7;
993
994 pMemoryRequirements->size = buffer->size;
995 pMemoryRequirements->alignment = 16;
996 }
997
998 void radv_GetImageMemoryRequirements(
999 VkDevice device,
1000 VkImage _image,
1001 VkMemoryRequirements* pMemoryRequirements)
1002 {
1003 RADV_FROM_HANDLE(radv_image, image, _image);
1004
1005 /* The Vulkan spec (git aaed022) says:
1006 *
1007 * memoryTypeBits is a bitfield and contains one bit set for every
1008 * supported memory type for the resource. The bit `1<<i` is set if and
1009 * only if the memory type `i` in the VkPhysicalDeviceMemoryProperties
1010 * structure for the physical device is supported.
1011 *
1012 * We support exactly one memory type.
1013 */
1014 pMemoryRequirements->memoryTypeBits = 0x7;
1015
1016 pMemoryRequirements->size = image->size;
1017 pMemoryRequirements->alignment = image->alignment;
1018 }
1019
1020 void radv_GetImageSparseMemoryRequirements(
1021 VkDevice device,
1022 VkImage image,
1023 uint32_t* pSparseMemoryRequirementCount,
1024 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
1025 {
1026 stub();
1027 }
1028
1029 void radv_GetDeviceMemoryCommitment(
1030 VkDevice device,
1031 VkDeviceMemory memory,
1032 VkDeviceSize* pCommittedMemoryInBytes)
1033 {
1034 *pCommittedMemoryInBytes = 0;
1035 }
1036
1037 VkResult radv_BindBufferMemory(
1038 VkDevice device,
1039 VkBuffer _buffer,
1040 VkDeviceMemory _memory,
1041 VkDeviceSize memoryOffset)
1042 {
1043 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1044 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1045
1046 if (mem) {
1047 buffer->bo = mem->bo;
1048 buffer->offset = memoryOffset;
1049 } else {
1050 buffer->bo = NULL;
1051 buffer->offset = 0;
1052 }
1053
1054 return VK_SUCCESS;
1055 }
1056
1057 VkResult radv_BindImageMemory(
1058 VkDevice device,
1059 VkImage _image,
1060 VkDeviceMemory _memory,
1061 VkDeviceSize memoryOffset)
1062 {
1063 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1064 RADV_FROM_HANDLE(radv_image, image, _image);
1065
1066 if (mem) {
1067 image->bo = mem->bo;
1068 image->offset = memoryOffset;
1069 } else {
1070 image->bo = NULL;
1071 image->offset = 0;
1072 }
1073
1074 return VK_SUCCESS;
1075 }
1076
1077 VkResult radv_QueueBindSparse(
1078 VkQueue queue,
1079 uint32_t bindInfoCount,
1080 const VkBindSparseInfo* pBindInfo,
1081 VkFence fence)
1082 {
1083 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER);
1084 }
1085
1086 VkResult radv_CreateFence(
1087 VkDevice _device,
1088 const VkFenceCreateInfo* pCreateInfo,
1089 const VkAllocationCallbacks* pAllocator,
1090 VkFence* pFence)
1091 {
1092 RADV_FROM_HANDLE(radv_device, device, _device);
1093 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
1094 sizeof(*fence), 8,
1095 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1096
1097 if (!fence)
1098 return VK_ERROR_OUT_OF_HOST_MEMORY;
1099
1100 memset(fence, 0, sizeof(*fence));
1101 fence->submitted = false;
1102 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
1103 fence->fence = device->ws->create_fence();
1104
1105
1106 *pFence = radv_fence_to_handle(fence);
1107
1108 return VK_SUCCESS;
1109 }
1110
1111 void radv_DestroyFence(
1112 VkDevice _device,
1113 VkFence _fence,
1114 const VkAllocationCallbacks* pAllocator)
1115 {
1116 RADV_FROM_HANDLE(radv_device, device, _device);
1117 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1118
1119 if (!fence)
1120 return;
1121 device->ws->destroy_fence(fence->fence);
1122 vk_free2(&device->alloc, pAllocator, fence);
1123 }
1124
1125 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
1126 {
1127 uint64_t current_time;
1128 struct timespec tv;
1129
1130 clock_gettime(CLOCK_MONOTONIC, &tv);
1131 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
1132
1133 timeout = MIN2(UINT64_MAX - current_time, timeout);
1134
1135 return current_time + timeout;
1136 }
1137
1138 VkResult radv_WaitForFences(
1139 VkDevice _device,
1140 uint32_t fenceCount,
1141 const VkFence* pFences,
1142 VkBool32 waitAll,
1143 uint64_t timeout)
1144 {
1145 RADV_FROM_HANDLE(radv_device, device, _device);
1146 timeout = radv_get_absolute_timeout(timeout);
1147
1148 if (!waitAll && fenceCount > 1) {
1149 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
1150 }
1151
1152 for (uint32_t i = 0; i < fenceCount; ++i) {
1153 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1154 bool expired = false;
1155
1156 if (fence->signalled)
1157 continue;
1158
1159 if (!fence->submitted)
1160 return VK_TIMEOUT;
1161
1162 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
1163 if (!expired)
1164 return VK_TIMEOUT;
1165
1166 fence->signalled = true;
1167 }
1168
1169 return VK_SUCCESS;
1170 }
1171
1172 VkResult radv_ResetFences(VkDevice device,
1173 uint32_t fenceCount,
1174 const VkFence *pFences)
1175 {
1176 for (unsigned i = 0; i < fenceCount; ++i) {
1177 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1178 fence->submitted = fence->signalled = false;
1179 }
1180
1181 return VK_SUCCESS;
1182 }
1183
1184 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
1185 {
1186 RADV_FROM_HANDLE(radv_device, device, _device);
1187 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1188
1189 if (fence->signalled)
1190 return VK_SUCCESS;
1191 if (!fence->submitted)
1192 return VK_NOT_READY;
1193
1194 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
1195 return VK_NOT_READY;
1196
1197 return VK_SUCCESS;
1198 }
1199
1200
1201 // Queue semaphore functions
1202
1203 VkResult radv_CreateSemaphore(
1204 VkDevice device,
1205 const VkSemaphoreCreateInfo* pCreateInfo,
1206 const VkAllocationCallbacks* pAllocator,
1207 VkSemaphore* pSemaphore)
1208 {
1209 /* The DRM execbuffer ioctl always execute in-oder, even between different
1210 * rings. As such, there's nothing to do for the user space semaphore.
1211 */
1212
1213 *pSemaphore = (VkSemaphore)1;
1214
1215 return VK_SUCCESS;
1216 }
1217
1218 void radv_DestroySemaphore(
1219 VkDevice device,
1220 VkSemaphore semaphore,
1221 const VkAllocationCallbacks* pAllocator)
1222 {
1223 }
1224
1225 VkResult radv_CreateEvent(
1226 VkDevice _device,
1227 const VkEventCreateInfo* pCreateInfo,
1228 const VkAllocationCallbacks* pAllocator,
1229 VkEvent* pEvent)
1230 {
1231 RADV_FROM_HANDLE(radv_device, device, _device);
1232 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
1233 sizeof(*event), 8,
1234 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1235
1236 if (!event)
1237 return VK_ERROR_OUT_OF_HOST_MEMORY;
1238
1239 event->bo = device->ws->buffer_create(device->ws, 8, 8,
1240 RADEON_DOMAIN_GTT,
1241 RADEON_FLAG_CPU_ACCESS);
1242 if (!event->bo) {
1243 vk_free2(&device->alloc, pAllocator, event);
1244 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1245 }
1246
1247 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
1248
1249 *pEvent = radv_event_to_handle(event);
1250
1251 return VK_SUCCESS;
1252 }
1253
1254 void radv_DestroyEvent(
1255 VkDevice _device,
1256 VkEvent _event,
1257 const VkAllocationCallbacks* pAllocator)
1258 {
1259 RADV_FROM_HANDLE(radv_device, device, _device);
1260 RADV_FROM_HANDLE(radv_event, event, _event);
1261
1262 if (!event)
1263 return;
1264 device->ws->buffer_destroy(event->bo);
1265 vk_free2(&device->alloc, pAllocator, event);
1266 }
1267
1268 VkResult radv_GetEventStatus(
1269 VkDevice _device,
1270 VkEvent _event)
1271 {
1272 RADV_FROM_HANDLE(radv_event, event, _event);
1273
1274 if (*event->map == 1)
1275 return VK_EVENT_SET;
1276 return VK_EVENT_RESET;
1277 }
1278
1279 VkResult radv_SetEvent(
1280 VkDevice _device,
1281 VkEvent _event)
1282 {
1283 RADV_FROM_HANDLE(radv_event, event, _event);
1284 *event->map = 1;
1285
1286 return VK_SUCCESS;
1287 }
1288
1289 VkResult radv_ResetEvent(
1290 VkDevice _device,
1291 VkEvent _event)
1292 {
1293 RADV_FROM_HANDLE(radv_event, event, _event);
1294 *event->map = 0;
1295
1296 return VK_SUCCESS;
1297 }
1298
1299 VkResult radv_CreateBuffer(
1300 VkDevice _device,
1301 const VkBufferCreateInfo* pCreateInfo,
1302 const VkAllocationCallbacks* pAllocator,
1303 VkBuffer* pBuffer)
1304 {
1305 RADV_FROM_HANDLE(radv_device, device, _device);
1306 struct radv_buffer *buffer;
1307
1308 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
1309
1310 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
1311 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1312 if (buffer == NULL)
1313 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1314
1315 buffer->size = pCreateInfo->size;
1316 buffer->usage = pCreateInfo->usage;
1317 buffer->bo = NULL;
1318 buffer->offset = 0;
1319
1320 *pBuffer = radv_buffer_to_handle(buffer);
1321
1322 return VK_SUCCESS;
1323 }
1324
1325 void radv_DestroyBuffer(
1326 VkDevice _device,
1327 VkBuffer _buffer,
1328 const VkAllocationCallbacks* pAllocator)
1329 {
1330 RADV_FROM_HANDLE(radv_device, device, _device);
1331 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1332
1333 if (!buffer)
1334 return;
1335
1336 vk_free2(&device->alloc, pAllocator, buffer);
1337 }
1338
1339 static inline unsigned
1340 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
1341 {
1342 if (stencil)
1343 return image->surface.stencil_tiling_index[level];
1344 else
1345 return image->surface.tiling_index[level];
1346 }
1347
1348 static void
1349 radv_initialise_color_surface(struct radv_device *device,
1350 struct radv_color_buffer_info *cb,
1351 struct radv_image_view *iview)
1352 {
1353 const struct vk_format_description *desc;
1354 unsigned ntype, format, swap, endian;
1355 unsigned blend_clamp = 0, blend_bypass = 0;
1356 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
1357 uint64_t va;
1358 const struct radeon_surf *surf = &iview->image->surface;
1359 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
1360
1361 desc = vk_format_description(iview->vk_format);
1362
1363 memset(cb, 0, sizeof(*cb));
1364
1365 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1366 va += level_info->offset;
1367 cb->cb_color_base = va >> 8;
1368
1369 /* CMASK variables */
1370 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1371 va += iview->image->cmask.offset;
1372 cb->cb_color_cmask = va >> 8;
1373 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
1374
1375 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1376 va += iview->image->dcc_offset;
1377 cb->cb_dcc_base = va >> 8;
1378
1379 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
1380 S_028C6C_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1381
1382 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
1383 pitch_tile_max = level_info->nblk_x / 8 - 1;
1384 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
1385 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
1386
1387 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
1388 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
1389
1390 /* Intensity is implemented as Red, so treat it that way. */
1391 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
1392 S_028C74_TILE_MODE_INDEX(tile_mode_index);
1393
1394 if (iview->image->samples > 1) {
1395 unsigned log_samples = util_logbase2(iview->image->samples);
1396
1397 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1398 S_028C74_NUM_FRAGMENTS(log_samples);
1399 }
1400
1401 if (iview->image->fmask.size) {
1402 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
1403 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1404 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
1405 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
1406 cb->cb_color_fmask = va >> 8;
1407 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
1408 } else {
1409 /* This must be set for fast clear to work without FMASK. */
1410 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1411 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
1412 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1413 cb->cb_color_fmask = cb->cb_color_base;
1414 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
1415 }
1416
1417 ntype = radv_translate_color_numformat(iview->vk_format,
1418 desc,
1419 vk_format_get_first_non_void_channel(iview->vk_format));
1420 format = radv_translate_colorformat(iview->vk_format);
1421 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
1422 radv_finishme("Illegal color\n");
1423 swap = radv_translate_colorswap(iview->vk_format, FALSE);
1424 endian = radv_colorformat_endian_swap(format);
1425
1426 /* blend clamp should be set for all NORM/SRGB types */
1427 if (ntype == V_028C70_NUMBER_UNORM ||
1428 ntype == V_028C70_NUMBER_SNORM ||
1429 ntype == V_028C70_NUMBER_SRGB)
1430 blend_clamp = 1;
1431
1432 /* set blend bypass according to docs if SINT/UINT or
1433 8/24 COLOR variants */
1434 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1435 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1436 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1437 blend_clamp = 0;
1438 blend_bypass = 1;
1439 }
1440 #if 0
1441 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
1442 (format == V_028C70_COLOR_8 ||
1443 format == V_028C70_COLOR_8_8 ||
1444 format == V_028C70_COLOR_8_8_8_8))
1445 ->color_is_int8 = true;
1446 #endif
1447 cb->cb_color_info = S_028C70_FORMAT(format) |
1448 S_028C70_COMP_SWAP(swap) |
1449 S_028C70_BLEND_CLAMP(blend_clamp) |
1450 S_028C70_BLEND_BYPASS(blend_bypass) |
1451 S_028C70_SIMPLE_FLOAT(1) |
1452 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
1453 ntype != V_028C70_NUMBER_SNORM &&
1454 ntype != V_028C70_NUMBER_SRGB &&
1455 format != V_028C70_COLOR_8_24 &&
1456 format != V_028C70_COLOR_24_8) |
1457 S_028C70_NUMBER_TYPE(ntype) |
1458 S_028C70_ENDIAN(endian);
1459 if (iview->image->samples > 1)
1460 if (iview->image->fmask.size)
1461 cb->cb_color_info |= S_028C70_COMPRESSION(1);
1462
1463 if (iview->image->cmask.size && device->allow_fast_clears)
1464 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
1465
1466 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
1467 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
1468
1469 if (device->instance->physicalDevice.rad_info.chip_class >= VI) {
1470 unsigned max_uncompressed_block_size = 2;
1471 if (iview->image->samples > 1) {
1472 if (iview->image->surface.bpe == 1)
1473 max_uncompressed_block_size = 0;
1474 else if (iview->image->surface.bpe == 2)
1475 max_uncompressed_block_size = 1;
1476 }
1477
1478 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
1479 S_028C78_INDEPENDENT_64B_BLOCKS(1);
1480 }
1481
1482 /* This must be set for fast clear to work without FMASK. */
1483 if (!iview->image->fmask.size &&
1484 device->instance->physicalDevice.rad_info.chip_class == SI) {
1485 unsigned bankh = util_logbase2(iview->image->surface.bankh);
1486 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1487 }
1488 }
1489
1490 static void
1491 radv_initialise_ds_surface(struct radv_device *device,
1492 struct radv_ds_buffer_info *ds,
1493 struct radv_image_view *iview)
1494 {
1495 unsigned level = iview->base_mip;
1496 unsigned format;
1497 uint64_t va, s_offs, z_offs;
1498 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
1499 memset(ds, 0, sizeof(*ds));
1500 switch (iview->vk_format) {
1501 case VK_FORMAT_D24_UNORM_S8_UINT:
1502 case VK_FORMAT_X8_D24_UNORM_PACK32:
1503 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1504 ds->offset_scale = 2.0f;
1505 break;
1506 case VK_FORMAT_D16_UNORM:
1507 case VK_FORMAT_D16_UNORM_S8_UINT:
1508 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1509 ds->offset_scale = 4.0f;
1510 break;
1511 case VK_FORMAT_D32_SFLOAT:
1512 case VK_FORMAT_D32_SFLOAT_S8_UINT:
1513 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1514 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1515 ds->offset_scale = 1.0f;
1516 break;
1517 default:
1518 break;
1519 }
1520
1521 format = radv_translate_dbformat(iview->vk_format);
1522 if (format == V_028040_Z_INVALID) {
1523 fprintf(stderr, "Invalid DB format: %d, disabling DB.\n", iview->vk_format);
1524 }
1525
1526 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1527 s_offs = z_offs = va;
1528 z_offs += iview->image->surface.level[level].offset;
1529 s_offs += iview->image->surface.stencil_level[level].offset;
1530
1531 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
1532 S_028008_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1533 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1534 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
1535
1536 if (iview->image->samples > 1)
1537 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
1538
1539 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
1540 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
1541 else
1542 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1543
1544 if (device->instance->physicalDevice.rad_info.chip_class >= CIK) {
1545 struct radeon_info *info = &device->instance->physicalDevice.rad_info;
1546 unsigned tiling_index = iview->image->surface.tiling_index[level];
1547 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
1548 unsigned macro_index = iview->image->surface.macro_tile_index;
1549 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
1550 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
1551 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
1552
1553 ds->db_depth_info |=
1554 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
1555 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
1556 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
1557 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
1558 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
1559 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
1560 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
1561 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
1562 } else {
1563 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
1564 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1565 tile_mode_index = si_tile_mode_index(iview->image, level, true);
1566 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1567 }
1568
1569 if (iview->image->htile.size && !level) {
1570 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1571 S_028040_ALLOW_EXPCLEAR(1);
1572
1573 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
1574 /* Workaround: For a not yet understood reason, the
1575 * combination of MSAA, fast stencil clear and stencil
1576 * decompress messes with subsequent stencil buffer
1577 * uses. Problem was reproduced on Verde, Bonaire,
1578 * Tonga, and Carrizo.
1579 *
1580 * Disabling EXPCLEAR works around the problem.
1581 *
1582 * Check piglit's arb_texture_multisample-stencil-clear
1583 * test if you want to try changing this.
1584 */
1585 if (iview->image->samples <= 1)
1586 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
1587 } else
1588 /* Use all of the htile_buffer for depth if there's no stencil. */
1589 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1590
1591 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
1592 iview->image->htile.offset;
1593 ds->db_htile_data_base = va >> 8;
1594 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
1595 } else {
1596 ds->db_htile_data_base = 0;
1597 ds->db_htile_surface = 0;
1598 }
1599
1600 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
1601 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
1602
1603 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
1604 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
1605 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
1606 }
1607
1608 VkResult radv_CreateFramebuffer(
1609 VkDevice _device,
1610 const VkFramebufferCreateInfo* pCreateInfo,
1611 const VkAllocationCallbacks* pAllocator,
1612 VkFramebuffer* pFramebuffer)
1613 {
1614 RADV_FROM_HANDLE(radv_device, device, _device);
1615 struct radv_framebuffer *framebuffer;
1616
1617 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
1618
1619 size_t size = sizeof(*framebuffer) +
1620 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
1621 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
1622 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1623 if (framebuffer == NULL)
1624 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1625
1626 framebuffer->attachment_count = pCreateInfo->attachmentCount;
1627 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
1628 VkImageView _iview = pCreateInfo->pAttachments[i];
1629 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
1630 framebuffer->attachments[i].attachment = iview;
1631 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
1632 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
1633 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
1634 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
1635 }
1636 }
1637
1638 framebuffer->width = pCreateInfo->width;
1639 framebuffer->height = pCreateInfo->height;
1640 framebuffer->layers = pCreateInfo->layers;
1641
1642 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
1643 return VK_SUCCESS;
1644 }
1645
1646 void radv_DestroyFramebuffer(
1647 VkDevice _device,
1648 VkFramebuffer _fb,
1649 const VkAllocationCallbacks* pAllocator)
1650 {
1651 RADV_FROM_HANDLE(radv_device, device, _device);
1652 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
1653
1654 if (!fb)
1655 return;
1656 vk_free2(&device->alloc, pAllocator, fb);
1657 }
1658
1659 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
1660 {
1661 switch (address_mode) {
1662 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
1663 return V_008F30_SQ_TEX_WRAP;
1664 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
1665 return V_008F30_SQ_TEX_MIRROR;
1666 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
1667 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1668 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
1669 return V_008F30_SQ_TEX_CLAMP_BORDER;
1670 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
1671 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1672 default:
1673 unreachable("illegal tex wrap mode");
1674 break;
1675 }
1676 }
1677
1678 static unsigned
1679 radv_tex_compare(VkCompareOp op)
1680 {
1681 switch (op) {
1682 case VK_COMPARE_OP_NEVER:
1683 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1684 case VK_COMPARE_OP_LESS:
1685 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1686 case VK_COMPARE_OP_EQUAL:
1687 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1688 case VK_COMPARE_OP_LESS_OR_EQUAL:
1689 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1690 case VK_COMPARE_OP_GREATER:
1691 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1692 case VK_COMPARE_OP_NOT_EQUAL:
1693 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1694 case VK_COMPARE_OP_GREATER_OR_EQUAL:
1695 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1696 case VK_COMPARE_OP_ALWAYS:
1697 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1698 default:
1699 unreachable("illegal compare mode");
1700 break;
1701 }
1702 }
1703
1704 static unsigned
1705 radv_tex_filter(VkFilter filter, unsigned max_ansio)
1706 {
1707 switch (filter) {
1708 case VK_FILTER_NEAREST:
1709 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
1710 V_008F38_SQ_TEX_XY_FILTER_POINT);
1711 case VK_FILTER_LINEAR:
1712 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
1713 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
1714 case VK_FILTER_CUBIC_IMG:
1715 default:
1716 fprintf(stderr, "illegal texture filter");
1717 return 0;
1718 }
1719 }
1720
1721 static unsigned
1722 radv_tex_mipfilter(VkSamplerMipmapMode mode)
1723 {
1724 switch (mode) {
1725 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
1726 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1727 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
1728 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1729 default:
1730 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1731 }
1732 }
1733
1734 static unsigned
1735 radv_tex_bordercolor(VkBorderColor bcolor)
1736 {
1737 switch (bcolor) {
1738 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
1739 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
1740 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
1741 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
1742 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
1743 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
1744 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
1745 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
1746 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
1747 default:
1748 break;
1749 }
1750 return 0;
1751 }
1752
1753 static unsigned
1754 radv_tex_aniso_filter(unsigned filter)
1755 {
1756 if (filter < 2)
1757 return 0;
1758 if (filter < 4)
1759 return 1;
1760 if (filter < 8)
1761 return 2;
1762 if (filter < 16)
1763 return 3;
1764 return 4;
1765 }
1766
1767 static void
1768 radv_init_sampler(struct radv_device *device,
1769 struct radv_sampler *sampler,
1770 const VkSamplerCreateInfo *pCreateInfo)
1771 {
1772 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
1773 (uint32_t) pCreateInfo->maxAnisotropy : 0;
1774 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
1775 bool is_vi;
1776 is_vi = (device->instance->physicalDevice.rad_info.chip_class >= VI);
1777
1778 if (!is_vi && max_aniso > 0) {
1779 radv_finishme("Anisotropic filtering must be disabled manually "
1780 "by the shader on SI-CI when BASE_LEVEL == LAST_LEVEL\n");
1781 max_aniso = max_aniso_ratio = 0;
1782 }
1783
1784 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
1785 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
1786 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
1787 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
1788 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
1789 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
1790 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
1791 S_008F30_ANISO_BIAS(max_aniso_ratio) |
1792 S_008F30_DISABLE_CUBE_WRAP(0) |
1793 S_008F30_COMPAT_MODE(is_vi));
1794 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
1795 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
1796 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
1797 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
1798 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
1799 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
1800 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
1801 S_008F38_MIP_POINT_PRECLAMP(1) |
1802 S_008F38_DISABLE_LSB_CEIL(1) |
1803 S_008F38_FILTER_PREC_FIX(1) |
1804 S_008F38_ANISO_OVERRIDE(is_vi));
1805 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
1806 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
1807 }
1808
1809 VkResult radv_CreateSampler(
1810 VkDevice _device,
1811 const VkSamplerCreateInfo* pCreateInfo,
1812 const VkAllocationCallbacks* pAllocator,
1813 VkSampler* pSampler)
1814 {
1815 RADV_FROM_HANDLE(radv_device, device, _device);
1816 struct radv_sampler *sampler;
1817
1818 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
1819
1820 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
1821 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1822 if (!sampler)
1823 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1824
1825 radv_init_sampler(device, sampler, pCreateInfo);
1826 *pSampler = radv_sampler_to_handle(sampler);
1827
1828 return VK_SUCCESS;
1829 }
1830
1831 void radv_DestroySampler(
1832 VkDevice _device,
1833 VkSampler _sampler,
1834 const VkAllocationCallbacks* pAllocator)
1835 {
1836 RADV_FROM_HANDLE(radv_device, device, _device);
1837 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
1838
1839 if (!sampler)
1840 return;
1841 vk_free2(&device->alloc, pAllocator, sampler);
1842 }