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radv: for external memory imports close the fd on import success
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "util/disk_cache.h"
35 #include "util/strtod.h"
36 #include "vk_util.h"
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "gfx9d.h"
46 #include "util/debug.h"
47
48 static int
49 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
50 {
51 uint32_t mesa_timestamp, llvm_timestamp;
52 uint16_t f = family;
53 memset(uuid, 0, VK_UUID_SIZE);
54 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
55 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
56 return -1;
57
58 memcpy(uuid, &mesa_timestamp, 4);
59 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
60 memcpy((char*)uuid + 8, &f, 2);
61 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
62 return 0;
63 }
64
65 static void
66 radv_get_device_uuid(drmDevicePtr device, void *uuid) {
67 memset(uuid, 0, VK_UUID_SIZE);
68 memcpy((char*)uuid + 0, &device->businfo.pci->domain, 2);
69 memcpy((char*)uuid + 2, &device->businfo.pci->bus, 1);
70 memcpy((char*)uuid + 3, &device->businfo.pci->dev, 1);
71 memcpy((char*)uuid + 4, &device->businfo.pci->func, 1);
72 }
73
74 static const VkExtensionProperties instance_extensions[] = {
75 {
76 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
77 .specVersion = 25,
78 },
79 #ifdef VK_USE_PLATFORM_XCB_KHR
80 {
81 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
82 .specVersion = 6,
83 },
84 #endif
85 #ifdef VK_USE_PLATFORM_XLIB_KHR
86 {
87 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
88 .specVersion = 6,
89 },
90 #endif
91 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
92 {
93 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
94 .specVersion = 6,
95 },
96 #endif
97 {
98 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
99 .specVersion = 1,
100 },
101 {
102 .extensionName = VK_KHR_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME,
103 .specVersion = 1,
104 },
105 {
106 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_CAPABILITIES_EXTENSION_NAME,
107 .specVersion = 1,
108 },
109 };
110
111 static const VkExtensionProperties common_device_extensions[] = {
112 {
113 .extensionName = VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME,
114 .specVersion = 1,
115 },
116 {
117 .extensionName = VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME,
118 .specVersion = 1,
119 },
120 {
121 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
122 .specVersion = 1,
123 },
124 {
125 .extensionName = VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME,
126 .specVersion = 1,
127 },
128 {
129 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
130 .specVersion = 1,
131 },
132 {
133 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
134 .specVersion = 68,
135 },
136 {
137 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
138 .specVersion = 1,
139 },
140 {
141 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
142 .specVersion = 1,
143 },
144 {
145 .extensionName = VK_KHR_GET_MEMORY_REQUIREMENTS_2_EXTENSION_NAME,
146 .specVersion = 1,
147 },
148 {
149 .extensionName = VK_KHR_DEDICATED_ALLOCATION_EXTENSION_NAME,
150 .specVersion = 1,
151 },
152 {
153 .extensionName = VK_KHR_EXTERNAL_MEMORY_EXTENSION_NAME,
154 .specVersion = 1,
155 },
156 {
157 .extensionName = VK_KHR_EXTERNAL_MEMORY_FD_EXTENSION_NAME,
158 .specVersion = 1,
159 },
160 {
161 .extensionName = VK_KHR_STORAGE_BUFFER_STORAGE_CLASS_EXTENSION_NAME,
162 .specVersion = 1,
163 },
164 {
165 .extensionName = VK_KHR_VARIABLE_POINTERS_EXTENSION_NAME,
166 .specVersion = 1,
167 },
168 };
169 static const VkExtensionProperties ext_sema_device_extensions[] = {
170 {
171 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_EXTENSION_NAME,
172 .specVersion = 1,
173 },
174 {
175 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_FD_EXTENSION_NAME,
176 .specVersion = 1,
177 },
178 };
179
180 static VkResult
181 radv_extensions_register(struct radv_instance *instance,
182 struct radv_extensions *extensions,
183 const VkExtensionProperties *new_ext,
184 uint32_t num_ext)
185 {
186 size_t new_size;
187 VkExtensionProperties *new_ptr;
188
189 assert(new_ext && num_ext > 0);
190
191 if (!new_ext)
192 return VK_ERROR_INITIALIZATION_FAILED;
193
194 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
195 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
196 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
197
198 /* Old array continues to be valid, update nothing */
199 if (!new_ptr)
200 return VK_ERROR_OUT_OF_HOST_MEMORY;
201
202 memcpy(&new_ptr[extensions->num_ext], new_ext,
203 num_ext * sizeof(VkExtensionProperties));
204 extensions->ext_array = new_ptr;
205 extensions->num_ext += num_ext;
206
207 return VK_SUCCESS;
208 }
209
210 static void
211 radv_extensions_finish(struct radv_instance *instance,
212 struct radv_extensions *extensions)
213 {
214 assert(extensions);
215
216 if (!extensions)
217 radv_loge("Attemted to free invalid extension struct\n");
218
219 if (extensions->ext_array)
220 vk_free(&instance->alloc, extensions->ext_array);
221 }
222
223 static bool
224 is_extension_enabled(const VkExtensionProperties *extensions,
225 size_t num_ext,
226 const char *name)
227 {
228 assert(extensions && name);
229
230 for (uint32_t i = 0; i < num_ext; i++) {
231 if (strcmp(name, extensions[i].extensionName) == 0)
232 return true;
233 }
234
235 return false;
236 }
237
238 static const char *
239 get_chip_name(enum radeon_family family)
240 {
241 switch (family) {
242 case CHIP_TAHITI: return "AMD RADV TAHITI";
243 case CHIP_PITCAIRN: return "AMD RADV PITCAIRN";
244 case CHIP_VERDE: return "AMD RADV CAPE VERDE";
245 case CHIP_OLAND: return "AMD RADV OLAND";
246 case CHIP_HAINAN: return "AMD RADV HAINAN";
247 case CHIP_BONAIRE: return "AMD RADV BONAIRE";
248 case CHIP_KAVERI: return "AMD RADV KAVERI";
249 case CHIP_KABINI: return "AMD RADV KABINI";
250 case CHIP_HAWAII: return "AMD RADV HAWAII";
251 case CHIP_MULLINS: return "AMD RADV MULLINS";
252 case CHIP_TONGA: return "AMD RADV TONGA";
253 case CHIP_ICELAND: return "AMD RADV ICELAND";
254 case CHIP_CARRIZO: return "AMD RADV CARRIZO";
255 case CHIP_FIJI: return "AMD RADV FIJI";
256 case CHIP_POLARIS10: return "AMD RADV POLARIS10";
257 case CHIP_POLARIS11: return "AMD RADV POLARIS11";
258 case CHIP_POLARIS12: return "AMD RADV POLARIS12";
259 case CHIP_STONEY: return "AMD RADV STONEY";
260 case CHIP_VEGA10: return "AMD RADV VEGA";
261 case CHIP_RAVEN: return "AMD RADV RAVEN";
262 default: return "AMD RADV unknown";
263 }
264 }
265
266 static VkResult
267 radv_physical_device_init(struct radv_physical_device *device,
268 struct radv_instance *instance,
269 drmDevicePtr drm_device)
270 {
271 const char *path = drm_device->nodes[DRM_NODE_RENDER];
272 VkResult result;
273 drmVersionPtr version;
274 int fd;
275
276 fd = open(path, O_RDWR | O_CLOEXEC);
277 if (fd < 0)
278 return VK_ERROR_INCOMPATIBLE_DRIVER;
279
280 version = drmGetVersion(fd);
281 if (!version) {
282 close(fd);
283 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
284 "failed to get version %s: %m", path);
285 }
286
287 if (strcmp(version->name, "amdgpu")) {
288 drmFreeVersion(version);
289 close(fd);
290 return VK_ERROR_INCOMPATIBLE_DRIVER;
291 }
292 drmFreeVersion(version);
293
294 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
295 device->instance = instance;
296 assert(strlen(path) < ARRAY_SIZE(device->path));
297 strncpy(device->path, path, ARRAY_SIZE(device->path));
298
299 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
300 instance->perftest_flags);
301 if (!device->ws) {
302 result = VK_ERROR_INCOMPATIBLE_DRIVER;
303 goto fail;
304 }
305
306 device->local_fd = fd;
307 device->ws->query_info(device->ws, &device->rad_info);
308 result = radv_init_wsi(device);
309 if (result != VK_SUCCESS) {
310 device->ws->destroy(device->ws);
311 goto fail;
312 }
313
314 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
315 radv_finish_wsi(device);
316 device->ws->destroy(device->ws);
317 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
318 "cannot generate UUID");
319 goto fail;
320 }
321
322 result = radv_extensions_register(instance,
323 &device->extensions,
324 common_device_extensions,
325 ARRAY_SIZE(common_device_extensions));
326 if (result != VK_SUCCESS)
327 goto fail;
328
329 if (device->rad_info.has_syncobj) {
330 result = radv_extensions_register(instance,
331 &device->extensions,
332 ext_sema_device_extensions,
333 ARRAY_SIZE(ext_sema_device_extensions));
334 if (result != VK_SUCCESS)
335 goto fail;
336 }
337
338 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
339 device->name = get_chip_name(device->rad_info.family);
340
341 radv_get_device_uuid(drm_device, device->device_uuid);
342
343 if (device->rad_info.family == CHIP_STONEY ||
344 device->rad_info.chip_class >= GFX9) {
345 device->has_rbplus = true;
346 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
347 }
348
349 return VK_SUCCESS;
350
351 fail:
352 close(fd);
353 return result;
354 }
355
356 static void
357 radv_physical_device_finish(struct radv_physical_device *device)
358 {
359 radv_extensions_finish(device->instance, &device->extensions);
360 radv_finish_wsi(device);
361 device->ws->destroy(device->ws);
362 close(device->local_fd);
363 }
364
365 static void *
366 default_alloc_func(void *pUserData, size_t size, size_t align,
367 VkSystemAllocationScope allocationScope)
368 {
369 return malloc(size);
370 }
371
372 static void *
373 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
374 size_t align, VkSystemAllocationScope allocationScope)
375 {
376 return realloc(pOriginal, size);
377 }
378
379 static void
380 default_free_func(void *pUserData, void *pMemory)
381 {
382 free(pMemory);
383 }
384
385 static const VkAllocationCallbacks default_alloc = {
386 .pUserData = NULL,
387 .pfnAllocation = default_alloc_func,
388 .pfnReallocation = default_realloc_func,
389 .pfnFree = default_free_func,
390 };
391
392 static const struct debug_control radv_debug_options[] = {
393 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
394 {"nodcc", RADV_DEBUG_NO_DCC},
395 {"shaders", RADV_DEBUG_DUMP_SHADERS},
396 {"nocache", RADV_DEBUG_NO_CACHE},
397 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
398 {"nohiz", RADV_DEBUG_NO_HIZ},
399 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
400 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
401 {"allbos", RADV_DEBUG_ALL_BOS},
402 {"noibs", RADV_DEBUG_NO_IBS},
403 {NULL, 0}
404 };
405
406 static const struct debug_control radv_perftest_options[] = {
407 {"batchchain", RADV_PERFTEST_BATCHCHAIN},
408 {"sisched", RADV_PERFTEST_SISCHED},
409 {NULL, 0}
410 };
411
412 VkResult radv_CreateInstance(
413 const VkInstanceCreateInfo* pCreateInfo,
414 const VkAllocationCallbacks* pAllocator,
415 VkInstance* pInstance)
416 {
417 struct radv_instance *instance;
418
419 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
420
421 uint32_t client_version;
422 if (pCreateInfo->pApplicationInfo &&
423 pCreateInfo->pApplicationInfo->apiVersion != 0) {
424 client_version = pCreateInfo->pApplicationInfo->apiVersion;
425 } else {
426 client_version = VK_MAKE_VERSION(1, 0, 0);
427 }
428
429 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
430 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
431 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
432 "Client requested version %d.%d.%d",
433 VK_VERSION_MAJOR(client_version),
434 VK_VERSION_MINOR(client_version),
435 VK_VERSION_PATCH(client_version));
436 }
437
438 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
439 if (!is_extension_enabled(instance_extensions,
440 ARRAY_SIZE(instance_extensions),
441 pCreateInfo->ppEnabledExtensionNames[i]))
442 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
443 }
444
445 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
446 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
447 if (!instance)
448 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
449
450 memset(instance, 0, sizeof(*instance));
451
452 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
453
454 if (pAllocator)
455 instance->alloc = *pAllocator;
456 else
457 instance->alloc = default_alloc;
458
459 instance->apiVersion = client_version;
460 instance->physicalDeviceCount = -1;
461
462 _mesa_locale_init();
463
464 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
465
466 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
467 radv_debug_options);
468
469 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
470 radv_perftest_options);
471
472 *pInstance = radv_instance_to_handle(instance);
473
474 return VK_SUCCESS;
475 }
476
477 void radv_DestroyInstance(
478 VkInstance _instance,
479 const VkAllocationCallbacks* pAllocator)
480 {
481 RADV_FROM_HANDLE(radv_instance, instance, _instance);
482
483 if (!instance)
484 return;
485
486 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
487 radv_physical_device_finish(instance->physicalDevices + i);
488 }
489
490 VG(VALGRIND_DESTROY_MEMPOOL(instance));
491
492 _mesa_locale_fini();
493
494 vk_free(&instance->alloc, instance);
495 }
496
497 static VkResult
498 radv_enumerate_devices(struct radv_instance *instance)
499 {
500 /* TODO: Check for more devices ? */
501 drmDevicePtr devices[8];
502 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
503 int max_devices;
504
505 instance->physicalDeviceCount = 0;
506
507 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
508 if (max_devices < 1)
509 return VK_ERROR_INCOMPATIBLE_DRIVER;
510
511 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
512 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
513 devices[i]->bustype == DRM_BUS_PCI &&
514 devices[i]->deviceinfo.pci->vendor_id == 0x1002) {
515
516 result = radv_physical_device_init(instance->physicalDevices +
517 instance->physicalDeviceCount,
518 instance,
519 devices[i]);
520 if (result == VK_SUCCESS)
521 ++instance->physicalDeviceCount;
522 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
523 break;
524 }
525 }
526 drmFreeDevices(devices, max_devices);
527
528 return result;
529 }
530
531 VkResult radv_EnumeratePhysicalDevices(
532 VkInstance _instance,
533 uint32_t* pPhysicalDeviceCount,
534 VkPhysicalDevice* pPhysicalDevices)
535 {
536 RADV_FROM_HANDLE(radv_instance, instance, _instance);
537 VkResult result;
538
539 if (instance->physicalDeviceCount < 0) {
540 result = radv_enumerate_devices(instance);
541 if (result != VK_SUCCESS &&
542 result != VK_ERROR_INCOMPATIBLE_DRIVER)
543 return result;
544 }
545
546 if (!pPhysicalDevices) {
547 *pPhysicalDeviceCount = instance->physicalDeviceCount;
548 } else {
549 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
550 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
551 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
552 }
553
554 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
555 : VK_SUCCESS;
556 }
557
558 void radv_GetPhysicalDeviceFeatures(
559 VkPhysicalDevice physicalDevice,
560 VkPhysicalDeviceFeatures* pFeatures)
561 {
562 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
563 bool is_gfx9 = pdevice->rad_info.chip_class >= GFX9;
564 memset(pFeatures, 0, sizeof(*pFeatures));
565
566 *pFeatures = (VkPhysicalDeviceFeatures) {
567 .robustBufferAccess = true,
568 .fullDrawIndexUint32 = true,
569 .imageCubeArray = true,
570 .independentBlend = true,
571 .geometryShader = !is_gfx9,
572 .tessellationShader = !is_gfx9,
573 .sampleRateShading = false,
574 .dualSrcBlend = true,
575 .logicOp = true,
576 .multiDrawIndirect = true,
577 .drawIndirectFirstInstance = true,
578 .depthClamp = true,
579 .depthBiasClamp = true,
580 .fillModeNonSolid = true,
581 .depthBounds = true,
582 .wideLines = true,
583 .largePoints = true,
584 .alphaToOne = true,
585 .multiViewport = true,
586 .samplerAnisotropy = true,
587 .textureCompressionETC2 = false,
588 .textureCompressionASTC_LDR = false,
589 .textureCompressionBC = true,
590 .occlusionQueryPrecise = true,
591 .pipelineStatisticsQuery = true,
592 .vertexPipelineStoresAndAtomics = true,
593 .fragmentStoresAndAtomics = true,
594 .shaderTessellationAndGeometryPointSize = true,
595 .shaderImageGatherExtended = true,
596 .shaderStorageImageExtendedFormats = true,
597 .shaderStorageImageMultisample = false,
598 .shaderUniformBufferArrayDynamicIndexing = true,
599 .shaderSampledImageArrayDynamicIndexing = true,
600 .shaderStorageBufferArrayDynamicIndexing = true,
601 .shaderStorageImageArrayDynamicIndexing = true,
602 .shaderStorageImageReadWithoutFormat = true,
603 .shaderStorageImageWriteWithoutFormat = true,
604 .shaderClipDistance = true,
605 .shaderCullDistance = true,
606 .shaderFloat64 = true,
607 .shaderInt64 = true,
608 .shaderInt16 = false,
609 .sparseBinding = true,
610 .variableMultisampleRate = true,
611 .inheritedQueries = true,
612 };
613 }
614
615 void radv_GetPhysicalDeviceFeatures2KHR(
616 VkPhysicalDevice physicalDevice,
617 VkPhysicalDeviceFeatures2KHR *pFeatures)
618 {
619 vk_foreach_struct(ext, pFeatures->pNext) {
620 switch (ext->sType) {
621 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
622 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
623 features->variablePointersStorageBuffer = true;
624 features->variablePointers = false;
625 break;
626 }
627 default:
628 break;
629 }
630 }
631 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
632 }
633
634 void radv_GetPhysicalDeviceProperties(
635 VkPhysicalDevice physicalDevice,
636 VkPhysicalDeviceProperties* pProperties)
637 {
638 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
639 VkSampleCountFlags sample_counts = 0xf;
640
641 /* make sure that the entire descriptor set is addressable with a signed
642 * 32-bit int. So the sum of all limits scaled by descriptor size has to
643 * be at most 2 GiB. the combined image & samples object count as one of
644 * both. This limit is for the pipeline layout, not for the set layout, but
645 * there is no set limit, so we just set a pipeline limit. I don't think
646 * any app is going to hit this soon. */
647 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
648 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
649 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
650 32 /* sampler, largest when combined with image */ +
651 64 /* sampled image */ +
652 64 /* storage image */);
653
654 VkPhysicalDeviceLimits limits = {
655 .maxImageDimension1D = (1 << 14),
656 .maxImageDimension2D = (1 << 14),
657 .maxImageDimension3D = (1 << 11),
658 .maxImageDimensionCube = (1 << 14),
659 .maxImageArrayLayers = (1 << 11),
660 .maxTexelBufferElements = 128 * 1024 * 1024,
661 .maxUniformBufferRange = UINT32_MAX,
662 .maxStorageBufferRange = UINT32_MAX,
663 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
664 .maxMemoryAllocationCount = UINT32_MAX,
665 .maxSamplerAllocationCount = 64 * 1024,
666 .bufferImageGranularity = 64, /* A cache line */
667 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
668 .maxBoundDescriptorSets = MAX_SETS,
669 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
670 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
671 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
672 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
673 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
674 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
675 .maxPerStageResources = max_descriptor_set_size,
676 .maxDescriptorSetSamplers = max_descriptor_set_size,
677 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
678 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
679 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
680 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
681 .maxDescriptorSetSampledImages = max_descriptor_set_size,
682 .maxDescriptorSetStorageImages = max_descriptor_set_size,
683 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
684 .maxVertexInputAttributes = 32,
685 .maxVertexInputBindings = 32,
686 .maxVertexInputAttributeOffset = 2047,
687 .maxVertexInputBindingStride = 2048,
688 .maxVertexOutputComponents = 128,
689 .maxTessellationGenerationLevel = 64,
690 .maxTessellationPatchSize = 32,
691 .maxTessellationControlPerVertexInputComponents = 128,
692 .maxTessellationControlPerVertexOutputComponents = 128,
693 .maxTessellationControlPerPatchOutputComponents = 120,
694 .maxTessellationControlTotalOutputComponents = 4096,
695 .maxTessellationEvaluationInputComponents = 128,
696 .maxTessellationEvaluationOutputComponents = 128,
697 .maxGeometryShaderInvocations = 127,
698 .maxGeometryInputComponents = 64,
699 .maxGeometryOutputComponents = 128,
700 .maxGeometryOutputVertices = 256,
701 .maxGeometryTotalOutputComponents = 1024,
702 .maxFragmentInputComponents = 128,
703 .maxFragmentOutputAttachments = 8,
704 .maxFragmentDualSrcAttachments = 1,
705 .maxFragmentCombinedOutputResources = 8,
706 .maxComputeSharedMemorySize = 32768,
707 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
708 .maxComputeWorkGroupInvocations = 2048,
709 .maxComputeWorkGroupSize = {
710 2048,
711 2048,
712 2048
713 },
714 .subPixelPrecisionBits = 4 /* FIXME */,
715 .subTexelPrecisionBits = 4 /* FIXME */,
716 .mipmapPrecisionBits = 4 /* FIXME */,
717 .maxDrawIndexedIndexValue = UINT32_MAX,
718 .maxDrawIndirectCount = UINT32_MAX,
719 .maxSamplerLodBias = 16,
720 .maxSamplerAnisotropy = 16,
721 .maxViewports = MAX_VIEWPORTS,
722 .maxViewportDimensions = { (1 << 14), (1 << 14) },
723 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
724 .viewportSubPixelBits = 13, /* We take a float? */
725 .minMemoryMapAlignment = 4096, /* A page */
726 .minTexelBufferOffsetAlignment = 1,
727 .minUniformBufferOffsetAlignment = 4,
728 .minStorageBufferOffsetAlignment = 4,
729 .minTexelOffset = -32,
730 .maxTexelOffset = 31,
731 .minTexelGatherOffset = -32,
732 .maxTexelGatherOffset = 31,
733 .minInterpolationOffset = -2,
734 .maxInterpolationOffset = 2,
735 .subPixelInterpolationOffsetBits = 8,
736 .maxFramebufferWidth = (1 << 14),
737 .maxFramebufferHeight = (1 << 14),
738 .maxFramebufferLayers = (1 << 10),
739 .framebufferColorSampleCounts = sample_counts,
740 .framebufferDepthSampleCounts = sample_counts,
741 .framebufferStencilSampleCounts = sample_counts,
742 .framebufferNoAttachmentsSampleCounts = sample_counts,
743 .maxColorAttachments = MAX_RTS,
744 .sampledImageColorSampleCounts = sample_counts,
745 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
746 .sampledImageDepthSampleCounts = sample_counts,
747 .sampledImageStencilSampleCounts = sample_counts,
748 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
749 .maxSampleMaskWords = 1,
750 .timestampComputeAndGraphics = true,
751 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
752 .maxClipDistances = 8,
753 .maxCullDistances = 8,
754 .maxCombinedClipAndCullDistances = 8,
755 .discreteQueuePriorities = 1,
756 .pointSizeRange = { 0.125, 255.875 },
757 .lineWidthRange = { 0.0, 7.9921875 },
758 .pointSizeGranularity = (1.0 / 8.0),
759 .lineWidthGranularity = (1.0 / 128.0),
760 .strictLines = false, /* FINISHME */
761 .standardSampleLocations = true,
762 .optimalBufferCopyOffsetAlignment = 128,
763 .optimalBufferCopyRowPitchAlignment = 128,
764 .nonCoherentAtomSize = 64,
765 };
766
767 *pProperties = (VkPhysicalDeviceProperties) {
768 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
769 .driverVersion = vk_get_driver_version(),
770 .vendorID = 0x1002,
771 .deviceID = pdevice->rad_info.pci_id,
772 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
773 .limits = limits,
774 .sparseProperties = {0},
775 };
776
777 strcpy(pProperties->deviceName, pdevice->name);
778 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
779 }
780
781 void radv_GetPhysicalDeviceProperties2KHR(
782 VkPhysicalDevice physicalDevice,
783 VkPhysicalDeviceProperties2KHR *pProperties)
784 {
785 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
786 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
787
788 vk_foreach_struct(ext, pProperties->pNext) {
789 switch (ext->sType) {
790 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
791 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
792 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
793 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
794 break;
795 }
796 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
797 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
798 radv_device_get_cache_uuid(0, properties->driverUUID);
799 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
800 properties->deviceLUIDValid = false;
801 break;
802 }
803 default:
804 break;
805 }
806 }
807 }
808
809 static void radv_get_physical_device_queue_family_properties(
810 struct radv_physical_device* pdevice,
811 uint32_t* pCount,
812 VkQueueFamilyProperties** pQueueFamilyProperties)
813 {
814 int num_queue_families = 1;
815 int idx;
816 if (pdevice->rad_info.num_compute_rings > 0 &&
817 pdevice->rad_info.chip_class >= CIK &&
818 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
819 num_queue_families++;
820
821 if (pQueueFamilyProperties == NULL) {
822 *pCount = num_queue_families;
823 return;
824 }
825
826 if (!*pCount)
827 return;
828
829 idx = 0;
830 if (*pCount >= 1) {
831 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
832 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
833 VK_QUEUE_COMPUTE_BIT |
834 VK_QUEUE_TRANSFER_BIT |
835 VK_QUEUE_SPARSE_BINDING_BIT,
836 .queueCount = 1,
837 .timestampValidBits = 64,
838 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
839 };
840 idx++;
841 }
842
843 if (pdevice->rad_info.num_compute_rings > 0 &&
844 pdevice->rad_info.chip_class >= CIK &&
845 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
846 if (*pCount > idx) {
847 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
848 .queueFlags = VK_QUEUE_COMPUTE_BIT |
849 VK_QUEUE_TRANSFER_BIT |
850 VK_QUEUE_SPARSE_BINDING_BIT,
851 .queueCount = pdevice->rad_info.num_compute_rings,
852 .timestampValidBits = 64,
853 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
854 };
855 idx++;
856 }
857 }
858 *pCount = idx;
859 }
860
861 void radv_GetPhysicalDeviceQueueFamilyProperties(
862 VkPhysicalDevice physicalDevice,
863 uint32_t* pCount,
864 VkQueueFamilyProperties* pQueueFamilyProperties)
865 {
866 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
867 if (!pQueueFamilyProperties) {
868 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
869 return;
870 }
871 VkQueueFamilyProperties *properties[] = {
872 pQueueFamilyProperties + 0,
873 pQueueFamilyProperties + 1,
874 pQueueFamilyProperties + 2,
875 };
876 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
877 assert(*pCount <= 3);
878 }
879
880 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
881 VkPhysicalDevice physicalDevice,
882 uint32_t* pCount,
883 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
884 {
885 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
886 if (!pQueueFamilyProperties) {
887 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
888 return;
889 }
890 VkQueueFamilyProperties *properties[] = {
891 &pQueueFamilyProperties[0].queueFamilyProperties,
892 &pQueueFamilyProperties[1].queueFamilyProperties,
893 &pQueueFamilyProperties[2].queueFamilyProperties,
894 };
895 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
896 assert(*pCount <= 3);
897 }
898
899 void radv_GetPhysicalDeviceMemoryProperties(
900 VkPhysicalDevice physicalDevice,
901 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
902 {
903 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
904
905 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
906
907 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
908 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
909 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
910 .heapIndex = RADV_MEM_HEAP_VRAM,
911 };
912 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
913 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
914 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
915 .heapIndex = RADV_MEM_HEAP_GTT,
916 };
917 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
918 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
919 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
920 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
921 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
922 };
923 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
924 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
925 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
926 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
927 .heapIndex = RADV_MEM_HEAP_GTT,
928 };
929
930 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
931
932 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
933 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
934 .size = physical_device->rad_info.vram_size -
935 physical_device->rad_info.vram_vis_size,
936 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
937 };
938 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
939 .size = physical_device->rad_info.vram_vis_size,
940 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
941 };
942 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
943 .size = physical_device->rad_info.gart_size,
944 .flags = 0,
945 };
946 }
947
948 void radv_GetPhysicalDeviceMemoryProperties2KHR(
949 VkPhysicalDevice physicalDevice,
950 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
951 {
952 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
953 &pMemoryProperties->memoryProperties);
954 }
955
956 static int
957 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
958 int queue_family_index, int idx)
959 {
960 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
961 queue->device = device;
962 queue->queue_family_index = queue_family_index;
963 queue->queue_idx = idx;
964
965 queue->hw_ctx = device->ws->ctx_create(device->ws);
966 if (!queue->hw_ctx)
967 return VK_ERROR_OUT_OF_HOST_MEMORY;
968
969 return VK_SUCCESS;
970 }
971
972 static void
973 radv_queue_finish(struct radv_queue *queue)
974 {
975 if (queue->hw_ctx)
976 queue->device->ws->ctx_destroy(queue->hw_ctx);
977
978 if (queue->initial_preamble_cs)
979 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
980 if (queue->continue_preamble_cs)
981 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
982 if (queue->descriptor_bo)
983 queue->device->ws->buffer_destroy(queue->descriptor_bo);
984 if (queue->scratch_bo)
985 queue->device->ws->buffer_destroy(queue->scratch_bo);
986 if (queue->esgs_ring_bo)
987 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
988 if (queue->gsvs_ring_bo)
989 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
990 if (queue->tess_factor_ring_bo)
991 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
992 if (queue->tess_offchip_ring_bo)
993 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
994 if (queue->compute_scratch_bo)
995 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
996 }
997
998 static void
999 radv_device_init_gs_info(struct radv_device *device)
1000 {
1001 switch (device->physical_device->rad_info.family) {
1002 case CHIP_OLAND:
1003 case CHIP_HAINAN:
1004 case CHIP_KAVERI:
1005 case CHIP_KABINI:
1006 case CHIP_MULLINS:
1007 case CHIP_ICELAND:
1008 case CHIP_CARRIZO:
1009 case CHIP_STONEY:
1010 device->gs_table_depth = 16;
1011 return;
1012 case CHIP_TAHITI:
1013 case CHIP_PITCAIRN:
1014 case CHIP_VERDE:
1015 case CHIP_BONAIRE:
1016 case CHIP_HAWAII:
1017 case CHIP_TONGA:
1018 case CHIP_FIJI:
1019 case CHIP_POLARIS10:
1020 case CHIP_POLARIS11:
1021 case CHIP_POLARIS12:
1022 case CHIP_VEGA10:
1023 case CHIP_RAVEN:
1024 device->gs_table_depth = 32;
1025 return;
1026 default:
1027 unreachable("unknown GPU");
1028 }
1029 }
1030
1031 VkResult radv_CreateDevice(
1032 VkPhysicalDevice physicalDevice,
1033 const VkDeviceCreateInfo* pCreateInfo,
1034 const VkAllocationCallbacks* pAllocator,
1035 VkDevice* pDevice)
1036 {
1037 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1038 VkResult result;
1039 struct radv_device *device;
1040
1041 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1042 if (!is_extension_enabled(physical_device->extensions.ext_array,
1043 physical_device->extensions.num_ext,
1044 pCreateInfo->ppEnabledExtensionNames[i]))
1045 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1046 }
1047
1048 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
1049 sizeof(*device), 8,
1050 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1051 if (!device)
1052 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1053
1054 memset(device, 0, sizeof(*device));
1055
1056 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1057 device->instance = physical_device->instance;
1058 device->physical_device = physical_device;
1059
1060 device->debug_flags = device->instance->debug_flags;
1061
1062 device->ws = physical_device->ws;
1063 if (pAllocator)
1064 device->alloc = *pAllocator;
1065 else
1066 device->alloc = physical_device->instance->alloc;
1067
1068 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1069 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1070 uint32_t qfi = queue_create->queueFamilyIndex;
1071
1072 device->queues[qfi] = vk_alloc(&device->alloc,
1073 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1074 if (!device->queues[qfi]) {
1075 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1076 goto fail;
1077 }
1078
1079 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1080
1081 device->queue_count[qfi] = queue_create->queueCount;
1082
1083 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1084 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
1085 if (result != VK_SUCCESS)
1086 goto fail;
1087 }
1088 }
1089
1090 #if HAVE_LLVM < 0x0400
1091 device->llvm_supports_spill = false;
1092 #else
1093 device->llvm_supports_spill = true;
1094 #endif
1095
1096 /* The maximum number of scratch waves. Scratch space isn't divided
1097 * evenly between CUs. The number is only a function of the number of CUs.
1098 * We can decrease the constant to decrease the scratch buffer size.
1099 *
1100 * sctx->scratch_waves must be >= the maximum posible size of
1101 * 1 threadgroup, so that the hw doesn't hang from being unable
1102 * to start any.
1103 *
1104 * The recommended value is 4 per CU at most. Higher numbers don't
1105 * bring much benefit, but they still occupy chip resources (think
1106 * async compute). I've seen ~2% performance difference between 4 and 32.
1107 */
1108 uint32_t max_threads_per_block = 2048;
1109 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1110 max_threads_per_block / 64);
1111
1112 radv_device_init_gs_info(device);
1113
1114 device->tess_offchip_block_dw_size =
1115 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1116 device->has_distributed_tess =
1117 device->physical_device->rad_info.chip_class >= VI &&
1118 device->physical_device->rad_info.max_se >= 2;
1119
1120 result = radv_device_init_meta(device);
1121 if (result != VK_SUCCESS)
1122 goto fail;
1123
1124 radv_device_init_msaa(device);
1125
1126 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1127 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1128 switch (family) {
1129 case RADV_QUEUE_GENERAL:
1130 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1131 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1132 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1133 break;
1134 case RADV_QUEUE_COMPUTE:
1135 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1136 radeon_emit(device->empty_cs[family], 0);
1137 break;
1138 }
1139 device->ws->cs_finalize(device->empty_cs[family]);
1140
1141 device->flush_cs[family] = device->ws->cs_create(device->ws, family);
1142 switch (family) {
1143 case RADV_QUEUE_GENERAL:
1144 case RADV_QUEUE_COMPUTE:
1145 si_cs_emit_cache_flush(device->flush_cs[family],
1146 false,
1147 device->physical_device->rad_info.chip_class,
1148 NULL, 0,
1149 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1150 RADV_CMD_FLAG_INV_ICACHE |
1151 RADV_CMD_FLAG_INV_SMEM_L1 |
1152 RADV_CMD_FLAG_INV_VMEM_L1 |
1153 RADV_CMD_FLAG_INV_GLOBAL_L2);
1154 break;
1155 }
1156 device->ws->cs_finalize(device->flush_cs[family]);
1157
1158 device->flush_shader_cs[family] = device->ws->cs_create(device->ws, family);
1159 switch (family) {
1160 case RADV_QUEUE_GENERAL:
1161 case RADV_QUEUE_COMPUTE:
1162 si_cs_emit_cache_flush(device->flush_shader_cs[family],
1163 false,
1164 device->physical_device->rad_info.chip_class,
1165 NULL, 0,
1166 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1167 family == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH) |
1168 RADV_CMD_FLAG_INV_ICACHE |
1169 RADV_CMD_FLAG_INV_SMEM_L1 |
1170 RADV_CMD_FLAG_INV_VMEM_L1 |
1171 RADV_CMD_FLAG_INV_GLOBAL_L2);
1172 break;
1173 }
1174 device->ws->cs_finalize(device->flush_shader_cs[family]);
1175 }
1176
1177 if (getenv("RADV_TRACE_FILE")) {
1178 device->trace_bo = device->ws->buffer_create(device->ws, 4096, 8,
1179 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
1180 if (!device->trace_bo)
1181 goto fail;
1182
1183 device->trace_id_ptr = device->ws->buffer_map(device->trace_bo);
1184 if (!device->trace_id_ptr)
1185 goto fail;
1186 }
1187
1188 if (device->physical_device->rad_info.chip_class >= CIK)
1189 cik_create_gfx_config(device);
1190
1191 VkPipelineCacheCreateInfo ci;
1192 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1193 ci.pNext = NULL;
1194 ci.flags = 0;
1195 ci.pInitialData = NULL;
1196 ci.initialDataSize = 0;
1197 VkPipelineCache pc;
1198 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1199 &ci, NULL, &pc);
1200 if (result != VK_SUCCESS)
1201 goto fail;
1202
1203 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1204
1205 *pDevice = radv_device_to_handle(device);
1206 return VK_SUCCESS;
1207
1208 fail:
1209 if (device->trace_bo)
1210 device->ws->buffer_destroy(device->trace_bo);
1211
1212 if (device->gfx_init)
1213 device->ws->buffer_destroy(device->gfx_init);
1214
1215 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1216 for (unsigned q = 0; q < device->queue_count[i]; q++)
1217 radv_queue_finish(&device->queues[i][q]);
1218 if (device->queue_count[i])
1219 vk_free(&device->alloc, device->queues[i]);
1220 }
1221
1222 vk_free(&device->alloc, device);
1223 return result;
1224 }
1225
1226 void radv_DestroyDevice(
1227 VkDevice _device,
1228 const VkAllocationCallbacks* pAllocator)
1229 {
1230 RADV_FROM_HANDLE(radv_device, device, _device);
1231
1232 if (!device)
1233 return;
1234
1235 if (device->trace_bo)
1236 device->ws->buffer_destroy(device->trace_bo);
1237
1238 if (device->gfx_init)
1239 device->ws->buffer_destroy(device->gfx_init);
1240
1241 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1242 for (unsigned q = 0; q < device->queue_count[i]; q++)
1243 radv_queue_finish(&device->queues[i][q]);
1244 if (device->queue_count[i])
1245 vk_free(&device->alloc, device->queues[i]);
1246 if (device->empty_cs[i])
1247 device->ws->cs_destroy(device->empty_cs[i]);
1248 if (device->flush_cs[i])
1249 device->ws->cs_destroy(device->flush_cs[i]);
1250 if (device->flush_shader_cs[i])
1251 device->ws->cs_destroy(device->flush_shader_cs[i]);
1252 }
1253 radv_device_finish_meta(device);
1254
1255 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1256 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1257
1258 vk_free(&device->alloc, device);
1259 }
1260
1261 VkResult radv_EnumerateInstanceExtensionProperties(
1262 const char* pLayerName,
1263 uint32_t* pPropertyCount,
1264 VkExtensionProperties* pProperties)
1265 {
1266 if (pProperties == NULL) {
1267 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1268 return VK_SUCCESS;
1269 }
1270
1271 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1272 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1273
1274 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1275 return VK_INCOMPLETE;
1276
1277 return VK_SUCCESS;
1278 }
1279
1280 VkResult radv_EnumerateDeviceExtensionProperties(
1281 VkPhysicalDevice physicalDevice,
1282 const char* pLayerName,
1283 uint32_t* pPropertyCount,
1284 VkExtensionProperties* pProperties)
1285 {
1286 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1287
1288 if (pProperties == NULL) {
1289 *pPropertyCount = pdevice->extensions.num_ext;
1290 return VK_SUCCESS;
1291 }
1292
1293 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1294 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1295
1296 if (*pPropertyCount < pdevice->extensions.num_ext)
1297 return VK_INCOMPLETE;
1298
1299 return VK_SUCCESS;
1300 }
1301
1302 VkResult radv_EnumerateInstanceLayerProperties(
1303 uint32_t* pPropertyCount,
1304 VkLayerProperties* pProperties)
1305 {
1306 if (pProperties == NULL) {
1307 *pPropertyCount = 0;
1308 return VK_SUCCESS;
1309 }
1310
1311 /* None supported at this time */
1312 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1313 }
1314
1315 VkResult radv_EnumerateDeviceLayerProperties(
1316 VkPhysicalDevice physicalDevice,
1317 uint32_t* pPropertyCount,
1318 VkLayerProperties* pProperties)
1319 {
1320 if (pProperties == NULL) {
1321 *pPropertyCount = 0;
1322 return VK_SUCCESS;
1323 }
1324
1325 /* None supported at this time */
1326 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1327 }
1328
1329 void radv_GetDeviceQueue(
1330 VkDevice _device,
1331 uint32_t queueFamilyIndex,
1332 uint32_t queueIndex,
1333 VkQueue* pQueue)
1334 {
1335 RADV_FROM_HANDLE(radv_device, device, _device);
1336
1337 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1338 }
1339
1340 static void radv_dump_trace(struct radv_device *device,
1341 struct radeon_winsys_cs *cs)
1342 {
1343 const char *filename = getenv("RADV_TRACE_FILE");
1344 FILE *f = fopen(filename, "w");
1345 if (!f) {
1346 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
1347 return;
1348 }
1349
1350 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
1351 device->ws->cs_dump(cs, f, *device->trace_id_ptr);
1352 fclose(f);
1353 }
1354
1355 static void
1356 fill_geom_tess_rings(struct radv_queue *queue,
1357 uint32_t *map,
1358 bool add_sample_positions,
1359 uint32_t esgs_ring_size,
1360 struct radeon_winsys_bo *esgs_ring_bo,
1361 uint32_t gsvs_ring_size,
1362 struct radeon_winsys_bo *gsvs_ring_bo,
1363 uint32_t tess_factor_ring_size,
1364 struct radeon_winsys_bo *tess_factor_ring_bo,
1365 uint32_t tess_offchip_ring_size,
1366 struct radeon_winsys_bo *tess_offchip_ring_bo)
1367 {
1368 uint64_t esgs_va = 0, gsvs_va = 0;
1369 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1370 uint32_t *desc = &map[4];
1371
1372 if (esgs_ring_bo)
1373 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1374 if (gsvs_ring_bo)
1375 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1376 if (tess_factor_ring_bo)
1377 tess_factor_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1378 if (tess_offchip_ring_bo)
1379 tess_offchip_va = queue->device->ws->buffer_get_va(tess_offchip_ring_bo);
1380
1381 /* stride 0, num records - size, add tid, swizzle, elsize4,
1382 index stride 64 */
1383 desc[0] = esgs_va;
1384 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1385 S_008F04_STRIDE(0) |
1386 S_008F04_SWIZZLE_ENABLE(true);
1387 desc[2] = esgs_ring_size;
1388 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1389 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1390 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1391 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1392 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1393 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1394 S_008F0C_ELEMENT_SIZE(1) |
1395 S_008F0C_INDEX_STRIDE(3) |
1396 S_008F0C_ADD_TID_ENABLE(true);
1397
1398 desc += 4;
1399 /* GS entry for ES->GS ring */
1400 /* stride 0, num records - size, elsize0,
1401 index stride 0 */
1402 desc[0] = esgs_va;
1403 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1404 S_008F04_STRIDE(0) |
1405 S_008F04_SWIZZLE_ENABLE(false);
1406 desc[2] = esgs_ring_size;
1407 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1408 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1409 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1410 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1411 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1412 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1413 S_008F0C_ELEMENT_SIZE(0) |
1414 S_008F0C_INDEX_STRIDE(0) |
1415 S_008F0C_ADD_TID_ENABLE(false);
1416
1417 desc += 4;
1418 /* VS entry for GS->VS ring */
1419 /* stride 0, num records - size, elsize0,
1420 index stride 0 */
1421 desc[0] = gsvs_va;
1422 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1423 S_008F04_STRIDE(0) |
1424 S_008F04_SWIZZLE_ENABLE(false);
1425 desc[2] = gsvs_ring_size;
1426 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1427 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1428 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1429 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1430 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1431 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1432 S_008F0C_ELEMENT_SIZE(0) |
1433 S_008F0C_INDEX_STRIDE(0) |
1434 S_008F0C_ADD_TID_ENABLE(false);
1435 desc += 4;
1436
1437 /* stride gsvs_itemsize, num records 64
1438 elsize 4, index stride 16 */
1439 /* shader will patch stride and desc[2] */
1440 desc[0] = gsvs_va;
1441 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1442 S_008F04_STRIDE(0) |
1443 S_008F04_SWIZZLE_ENABLE(true);
1444 desc[2] = 0;
1445 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1446 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1447 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1448 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1449 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1450 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1451 S_008F0C_ELEMENT_SIZE(1) |
1452 S_008F0C_INDEX_STRIDE(1) |
1453 S_008F0C_ADD_TID_ENABLE(true);
1454 desc += 4;
1455
1456 desc[0] = tess_factor_va;
1457 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1458 S_008F04_STRIDE(0) |
1459 S_008F04_SWIZZLE_ENABLE(false);
1460 desc[2] = tess_factor_ring_size;
1461 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1462 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1463 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1464 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1465 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1466 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1467 S_008F0C_ELEMENT_SIZE(0) |
1468 S_008F0C_INDEX_STRIDE(0) |
1469 S_008F0C_ADD_TID_ENABLE(false);
1470 desc += 4;
1471
1472 desc[0] = tess_offchip_va;
1473 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1474 S_008F04_STRIDE(0) |
1475 S_008F04_SWIZZLE_ENABLE(false);
1476 desc[2] = tess_offchip_ring_size;
1477 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1478 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1479 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1480 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1481 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1482 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1483 S_008F0C_ELEMENT_SIZE(0) |
1484 S_008F0C_INDEX_STRIDE(0) |
1485 S_008F0C_ADD_TID_ENABLE(false);
1486 desc += 4;
1487
1488 /* add sample positions after all rings */
1489 memcpy(desc, queue->device->sample_locations_1x, 8);
1490 desc += 2;
1491 memcpy(desc, queue->device->sample_locations_2x, 16);
1492 desc += 4;
1493 memcpy(desc, queue->device->sample_locations_4x, 32);
1494 desc += 8;
1495 memcpy(desc, queue->device->sample_locations_8x, 64);
1496 desc += 16;
1497 memcpy(desc, queue->device->sample_locations_16x, 128);
1498 }
1499
1500 static unsigned
1501 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1502 {
1503 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1504 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1505 device->physical_device->rad_info.family != CHIP_STONEY;
1506 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1507 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1508 device->physical_device->rad_info.max_se;
1509 unsigned offchip_granularity;
1510 unsigned hs_offchip_param;
1511 switch (device->tess_offchip_block_dw_size) {
1512 default:
1513 assert(0);
1514 /* fall through */
1515 case 8192:
1516 offchip_granularity = V_03093C_X_8K_DWORDS;
1517 break;
1518 case 4096:
1519 offchip_granularity = V_03093C_X_4K_DWORDS;
1520 break;
1521 }
1522
1523 switch (device->physical_device->rad_info.chip_class) {
1524 case SI:
1525 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1526 break;
1527 case CIK:
1528 case VI:
1529 case GFX9:
1530 default:
1531 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1532 break;
1533 }
1534
1535 *max_offchip_buffers_p = max_offchip_buffers;
1536 if (device->physical_device->rad_info.chip_class >= CIK) {
1537 if (device->physical_device->rad_info.chip_class >= VI)
1538 --max_offchip_buffers;
1539 hs_offchip_param =
1540 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1541 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1542 } else {
1543 hs_offchip_param =
1544 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1545 }
1546 return hs_offchip_param;
1547 }
1548
1549 static VkResult
1550 radv_get_preamble_cs(struct radv_queue *queue,
1551 uint32_t scratch_size,
1552 uint32_t compute_scratch_size,
1553 uint32_t esgs_ring_size,
1554 uint32_t gsvs_ring_size,
1555 bool needs_tess_rings,
1556 bool needs_sample_positions,
1557 struct radeon_winsys_cs **initial_preamble_cs,
1558 struct radeon_winsys_cs **continue_preamble_cs)
1559 {
1560 struct radeon_winsys_bo *scratch_bo = NULL;
1561 struct radeon_winsys_bo *descriptor_bo = NULL;
1562 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1563 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1564 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1565 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1566 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1567 struct radeon_winsys_cs *dest_cs[2] = {0};
1568 bool add_tess_rings = false, add_sample_positions = false;
1569 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1570 unsigned max_offchip_buffers;
1571 unsigned hs_offchip_param = 0;
1572 if (!queue->has_tess_rings) {
1573 if (needs_tess_rings)
1574 add_tess_rings = true;
1575 }
1576 if (!queue->has_sample_positions) {
1577 if (needs_sample_positions)
1578 add_sample_positions = true;
1579 }
1580 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1581 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1582 &max_offchip_buffers);
1583 tess_offchip_ring_size = max_offchip_buffers *
1584 queue->device->tess_offchip_block_dw_size * 4;
1585
1586 if (scratch_size <= queue->scratch_size &&
1587 compute_scratch_size <= queue->compute_scratch_size &&
1588 esgs_ring_size <= queue->esgs_ring_size &&
1589 gsvs_ring_size <= queue->gsvs_ring_size &&
1590 !add_tess_rings && !add_sample_positions &&
1591 queue->initial_preamble_cs) {
1592 *initial_preamble_cs = queue->initial_preamble_cs;
1593 *continue_preamble_cs = queue->continue_preamble_cs;
1594 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1595 *continue_preamble_cs = NULL;
1596 return VK_SUCCESS;
1597 }
1598
1599 if (scratch_size > queue->scratch_size) {
1600 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1601 scratch_size,
1602 4096,
1603 RADEON_DOMAIN_VRAM,
1604 RADEON_FLAG_NO_CPU_ACCESS);
1605 if (!scratch_bo)
1606 goto fail;
1607 } else
1608 scratch_bo = queue->scratch_bo;
1609
1610 if (compute_scratch_size > queue->compute_scratch_size) {
1611 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1612 compute_scratch_size,
1613 4096,
1614 RADEON_DOMAIN_VRAM,
1615 RADEON_FLAG_NO_CPU_ACCESS);
1616 if (!compute_scratch_bo)
1617 goto fail;
1618
1619 } else
1620 compute_scratch_bo = queue->compute_scratch_bo;
1621
1622 if (esgs_ring_size > queue->esgs_ring_size) {
1623 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1624 esgs_ring_size,
1625 4096,
1626 RADEON_DOMAIN_VRAM,
1627 RADEON_FLAG_NO_CPU_ACCESS);
1628 if (!esgs_ring_bo)
1629 goto fail;
1630 } else {
1631 esgs_ring_bo = queue->esgs_ring_bo;
1632 esgs_ring_size = queue->esgs_ring_size;
1633 }
1634
1635 if (gsvs_ring_size > queue->gsvs_ring_size) {
1636 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1637 gsvs_ring_size,
1638 4096,
1639 RADEON_DOMAIN_VRAM,
1640 RADEON_FLAG_NO_CPU_ACCESS);
1641 if (!gsvs_ring_bo)
1642 goto fail;
1643 } else {
1644 gsvs_ring_bo = queue->gsvs_ring_bo;
1645 gsvs_ring_size = queue->gsvs_ring_size;
1646 }
1647
1648 if (add_tess_rings) {
1649 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1650 tess_factor_ring_size,
1651 256,
1652 RADEON_DOMAIN_VRAM,
1653 RADEON_FLAG_NO_CPU_ACCESS);
1654 if (!tess_factor_ring_bo)
1655 goto fail;
1656 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1657 tess_offchip_ring_size,
1658 256,
1659 RADEON_DOMAIN_VRAM,
1660 RADEON_FLAG_NO_CPU_ACCESS);
1661 if (!tess_offchip_ring_bo)
1662 goto fail;
1663 } else {
1664 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1665 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1666 }
1667
1668 if (scratch_bo != queue->scratch_bo ||
1669 esgs_ring_bo != queue->esgs_ring_bo ||
1670 gsvs_ring_bo != queue->gsvs_ring_bo ||
1671 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1672 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1673 uint32_t size = 0;
1674 if (gsvs_ring_bo || esgs_ring_bo ||
1675 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1676 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1677 if (add_sample_positions)
1678 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1679 }
1680 else if (scratch_bo)
1681 size = 8; /* 2 dword */
1682
1683 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1684 size,
1685 4096,
1686 RADEON_DOMAIN_VRAM,
1687 RADEON_FLAG_CPU_ACCESS);
1688 if (!descriptor_bo)
1689 goto fail;
1690 } else
1691 descriptor_bo = queue->descriptor_bo;
1692
1693 for(int i = 0; i < 2; ++i) {
1694 struct radeon_winsys_cs *cs = NULL;
1695 cs = queue->device->ws->cs_create(queue->device->ws,
1696 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1697 if (!cs)
1698 goto fail;
1699
1700 dest_cs[i] = cs;
1701
1702 if (scratch_bo)
1703 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1704
1705 if (esgs_ring_bo)
1706 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1707
1708 if (gsvs_ring_bo)
1709 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1710
1711 if (tess_factor_ring_bo)
1712 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1713
1714 if (tess_offchip_ring_bo)
1715 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1716
1717 if (descriptor_bo)
1718 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1719
1720 if (descriptor_bo != queue->descriptor_bo) {
1721 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1722
1723 if (scratch_bo) {
1724 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1725 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1726 S_008F04_SWIZZLE_ENABLE(1);
1727 map[0] = scratch_va;
1728 map[1] = rsrc1;
1729 }
1730
1731 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1732 add_sample_positions)
1733 fill_geom_tess_rings(queue, map, add_sample_positions,
1734 esgs_ring_size, esgs_ring_bo,
1735 gsvs_ring_size, gsvs_ring_bo,
1736 tess_factor_ring_size, tess_factor_ring_bo,
1737 tess_offchip_ring_size, tess_offchip_ring_bo);
1738
1739 queue->device->ws->buffer_unmap(descriptor_bo);
1740 }
1741
1742 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1743 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1744 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1745 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1746 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1747 }
1748
1749 if (esgs_ring_bo || gsvs_ring_bo) {
1750 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1751 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1752 radeon_emit(cs, esgs_ring_size >> 8);
1753 radeon_emit(cs, gsvs_ring_size >> 8);
1754 } else {
1755 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1756 radeon_emit(cs, esgs_ring_size >> 8);
1757 radeon_emit(cs, gsvs_ring_size >> 8);
1758 }
1759 }
1760
1761 if (tess_factor_ring_bo) {
1762 uint64_t tf_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1763 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1764 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1765 S_030938_SIZE(tess_factor_ring_size / 4));
1766 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1767 tf_va >> 8);
1768 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1769 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1770 tf_va >> 40);
1771 }
1772 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1773 } else {
1774 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1775 S_008988_SIZE(tess_factor_ring_size / 4));
1776 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1777 tf_va >> 8);
1778 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1779 hs_offchip_param);
1780 }
1781 }
1782
1783 if (descriptor_bo) {
1784 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1785 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1786 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1787 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1788 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1789 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1790
1791 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1792
1793 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1794 radeon_set_sh_reg_seq(cs, regs[i], 2);
1795 radeon_emit(cs, va);
1796 radeon_emit(cs, va >> 32);
1797 }
1798 }
1799
1800 if (compute_scratch_bo) {
1801 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1802 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1803 S_008F04_SWIZZLE_ENABLE(1);
1804
1805 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1806
1807 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1808 radeon_emit(cs, scratch_va);
1809 radeon_emit(cs, rsrc1);
1810 }
1811
1812 if (!i) {
1813 si_cs_emit_cache_flush(cs,
1814 false,
1815 queue->device->physical_device->rad_info.chip_class,
1816 NULL, 0,
1817 queue->queue_family_index == RING_COMPUTE &&
1818 queue->device->physical_device->rad_info.chip_class >= CIK,
1819 RADV_CMD_FLAG_INV_ICACHE |
1820 RADV_CMD_FLAG_INV_SMEM_L1 |
1821 RADV_CMD_FLAG_INV_VMEM_L1 |
1822 RADV_CMD_FLAG_INV_GLOBAL_L2);
1823 }
1824
1825 if (!queue->device->ws->cs_finalize(cs))
1826 goto fail;
1827 }
1828
1829 if (queue->initial_preamble_cs)
1830 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1831
1832 if (queue->continue_preamble_cs)
1833 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1834
1835 queue->initial_preamble_cs = dest_cs[0];
1836 queue->continue_preamble_cs = dest_cs[1];
1837
1838 if (scratch_bo != queue->scratch_bo) {
1839 if (queue->scratch_bo)
1840 queue->device->ws->buffer_destroy(queue->scratch_bo);
1841 queue->scratch_bo = scratch_bo;
1842 queue->scratch_size = scratch_size;
1843 }
1844
1845 if (compute_scratch_bo != queue->compute_scratch_bo) {
1846 if (queue->compute_scratch_bo)
1847 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1848 queue->compute_scratch_bo = compute_scratch_bo;
1849 queue->compute_scratch_size = compute_scratch_size;
1850 }
1851
1852 if (esgs_ring_bo != queue->esgs_ring_bo) {
1853 if (queue->esgs_ring_bo)
1854 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1855 queue->esgs_ring_bo = esgs_ring_bo;
1856 queue->esgs_ring_size = esgs_ring_size;
1857 }
1858
1859 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1860 if (queue->gsvs_ring_bo)
1861 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1862 queue->gsvs_ring_bo = gsvs_ring_bo;
1863 queue->gsvs_ring_size = gsvs_ring_size;
1864 }
1865
1866 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1867 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1868 }
1869
1870 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1871 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1872 queue->has_tess_rings = true;
1873 }
1874
1875 if (descriptor_bo != queue->descriptor_bo) {
1876 if (queue->descriptor_bo)
1877 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1878
1879 queue->descriptor_bo = descriptor_bo;
1880 }
1881
1882 if (add_sample_positions)
1883 queue->has_sample_positions = true;
1884
1885 *initial_preamble_cs = queue->initial_preamble_cs;
1886 *continue_preamble_cs = queue->continue_preamble_cs;
1887 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1888 *continue_preamble_cs = NULL;
1889 return VK_SUCCESS;
1890 fail:
1891 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1892 if (dest_cs[i])
1893 queue->device->ws->cs_destroy(dest_cs[i]);
1894 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1895 queue->device->ws->buffer_destroy(descriptor_bo);
1896 if (scratch_bo && scratch_bo != queue->scratch_bo)
1897 queue->device->ws->buffer_destroy(scratch_bo);
1898 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1899 queue->device->ws->buffer_destroy(compute_scratch_bo);
1900 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1901 queue->device->ws->buffer_destroy(esgs_ring_bo);
1902 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1903 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1904 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1905 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1906 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1907 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1908 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1909 }
1910
1911 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1912 int num_sems,
1913 const VkSemaphore *sems,
1914 bool reset_temp)
1915 {
1916 int syncobj_idx = 0, sem_idx = 0;
1917
1918 if (num_sems == 0)
1919 return VK_SUCCESS;
1920 for (uint32_t i = 0; i < num_sems; i++) {
1921 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1922
1923 if (sem->temp_syncobj || sem->syncobj)
1924 counts->syncobj_count++;
1925 else
1926 counts->sem_count++;
1927 }
1928
1929 if (counts->syncobj_count) {
1930 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1931 if (!counts->syncobj)
1932 return VK_ERROR_OUT_OF_HOST_MEMORY;
1933 }
1934
1935 if (counts->sem_count) {
1936 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1937 if (!counts->sem) {
1938 free(counts->syncobj);
1939 return VK_ERROR_OUT_OF_HOST_MEMORY;
1940 }
1941 }
1942
1943 for (uint32_t i = 0; i < num_sems; i++) {
1944 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1945
1946 if (sem->temp_syncobj) {
1947 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1948 if (reset_temp) {
1949 /* after we wait on a temp import - drop it */
1950 sem->temp_syncobj = 0;
1951 }
1952 }
1953 else if (sem->syncobj)
1954 counts->syncobj[syncobj_idx++] = sem->syncobj;
1955 else {
1956 assert(sem->sem);
1957 counts->sem[sem_idx++] = sem->sem;
1958 }
1959 }
1960
1961 return VK_SUCCESS;
1962 }
1963
1964 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
1965 {
1966 free(sem_info->wait.syncobj);
1967 free(sem_info->wait.sem);
1968 free(sem_info->signal.syncobj);
1969 free(sem_info->signal.sem);
1970 }
1971
1972 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1973 int num_wait_sems,
1974 const VkSemaphore *wait_sems,
1975 int num_signal_sems,
1976 const VkSemaphore *signal_sems)
1977 {
1978 VkResult ret;
1979 memset(sem_info, 0, sizeof(*sem_info));
1980
1981 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, true);
1982 if (ret)
1983 return ret;
1984 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, false);
1985 if (ret)
1986 radv_free_sem_info(sem_info);
1987
1988 /* caller can override these */
1989 sem_info->cs_emit_wait = true;
1990 sem_info->cs_emit_signal = true;
1991 return ret;
1992 }
1993
1994 VkResult radv_QueueSubmit(
1995 VkQueue _queue,
1996 uint32_t submitCount,
1997 const VkSubmitInfo* pSubmits,
1998 VkFence _fence)
1999 {
2000 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2001 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2002 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2003 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2004 int ret;
2005 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2006 uint32_t scratch_size = 0;
2007 uint32_t compute_scratch_size = 0;
2008 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2009 struct radeon_winsys_cs *initial_preamble_cs = NULL, *continue_preamble_cs = NULL;
2010 VkResult result;
2011 bool fence_emitted = false;
2012 bool tess_rings_needed = false;
2013 bool sample_positions_needed = false;
2014
2015 /* Do this first so failing to allocate scratch buffers can't result in
2016 * partially executed submissions. */
2017 for (uint32_t i = 0; i < submitCount; i++) {
2018 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2019 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2020 pSubmits[i].pCommandBuffers[j]);
2021
2022 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2023 compute_scratch_size = MAX2(compute_scratch_size,
2024 cmd_buffer->compute_scratch_size_needed);
2025 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2026 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2027 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2028 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2029 }
2030 }
2031
2032 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2033 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2034 sample_positions_needed,
2035 &initial_preamble_cs, &continue_preamble_cs);
2036 if (result != VK_SUCCESS)
2037 return result;
2038
2039 for (uint32_t i = 0; i < submitCount; i++) {
2040 struct radeon_winsys_cs **cs_array;
2041 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2042 bool can_patch = !do_flush;
2043 uint32_t advance;
2044 struct radv_winsys_sem_info sem_info;
2045
2046 result = radv_alloc_sem_info(&sem_info,
2047 pSubmits[i].waitSemaphoreCount,
2048 pSubmits[i].pWaitSemaphores,
2049 pSubmits[i].signalSemaphoreCount,
2050 pSubmits[i].pSignalSemaphores);
2051 if (result != VK_SUCCESS)
2052 return result;
2053
2054 if (!pSubmits[i].commandBufferCount) {
2055 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2056 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2057 &queue->device->empty_cs[queue->queue_family_index],
2058 1, NULL, NULL,
2059 &sem_info,
2060 false, base_fence);
2061 if (ret) {
2062 radv_loge("failed to submit CS %d\n", i);
2063 abort();
2064 }
2065 fence_emitted = true;
2066 }
2067 radv_free_sem_info(&sem_info);
2068 continue;
2069 }
2070
2071 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2072 (pSubmits[i].commandBufferCount + do_flush));
2073
2074 if(do_flush)
2075 cs_array[0] = pSubmits[i].waitSemaphoreCount ?
2076 queue->device->flush_shader_cs[queue->queue_family_index] :
2077 queue->device->flush_cs[queue->queue_family_index];
2078
2079 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2080 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2081 pSubmits[i].pCommandBuffers[j]);
2082 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2083
2084 cs_array[j + do_flush] = cmd_buffer->cs;
2085 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2086 can_patch = false;
2087 }
2088
2089 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount + do_flush; j += advance) {
2090 advance = MIN2(max_cs_submission,
2091 pSubmits[i].commandBufferCount + do_flush - j);
2092
2093 if (queue->device->trace_bo)
2094 *queue->device->trace_id_ptr = 0;
2095
2096 sem_info.cs_emit_wait = j == 0;
2097 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount + do_flush;
2098
2099 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2100 advance, initial_preamble_cs, continue_preamble_cs,
2101 &sem_info,
2102 can_patch, base_fence);
2103
2104 if (ret) {
2105 radv_loge("failed to submit CS %d\n", i);
2106 abort();
2107 }
2108 fence_emitted = true;
2109 if (queue->device->trace_bo) {
2110 bool success = queue->device->ws->ctx_wait_idle(
2111 queue->hw_ctx,
2112 radv_queue_family_to_ring(
2113 queue->queue_family_index),
2114 queue->queue_idx);
2115
2116 if (!success) { /* Hang */
2117 radv_dump_trace(queue->device, cs_array[j]);
2118 abort();
2119 }
2120 }
2121 }
2122
2123 radv_free_sem_info(&sem_info);
2124 free(cs_array);
2125 }
2126
2127 if (fence) {
2128 if (!fence_emitted) {
2129 struct radv_winsys_sem_info sem_info = {0};
2130 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2131 &queue->device->empty_cs[queue->queue_family_index],
2132 1, NULL, NULL, &sem_info,
2133 false, base_fence);
2134 }
2135 fence->submitted = true;
2136 }
2137
2138 return VK_SUCCESS;
2139 }
2140
2141 VkResult radv_QueueWaitIdle(
2142 VkQueue _queue)
2143 {
2144 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2145
2146 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2147 radv_queue_family_to_ring(queue->queue_family_index),
2148 queue->queue_idx);
2149 return VK_SUCCESS;
2150 }
2151
2152 VkResult radv_DeviceWaitIdle(
2153 VkDevice _device)
2154 {
2155 RADV_FROM_HANDLE(radv_device, device, _device);
2156
2157 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2158 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2159 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2160 }
2161 }
2162 return VK_SUCCESS;
2163 }
2164
2165 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2166 VkInstance instance,
2167 const char* pName)
2168 {
2169 return radv_lookup_entrypoint(pName);
2170 }
2171
2172 /* The loader wants us to expose a second GetInstanceProcAddr function
2173 * to work around certain LD_PRELOAD issues seen in apps.
2174 */
2175 PUBLIC
2176 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2177 VkInstance instance,
2178 const char* pName);
2179
2180 PUBLIC
2181 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2182 VkInstance instance,
2183 const char* pName)
2184 {
2185 return radv_GetInstanceProcAddr(instance, pName);
2186 }
2187
2188 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2189 VkDevice device,
2190 const char* pName)
2191 {
2192 return radv_lookup_entrypoint(pName);
2193 }
2194
2195 bool radv_get_memory_fd(struct radv_device *device,
2196 struct radv_device_memory *memory,
2197 int *pFD)
2198 {
2199 struct radeon_bo_metadata metadata;
2200
2201 if (memory->image) {
2202 radv_init_metadata(device, memory->image, &metadata);
2203 device->ws->buffer_set_metadata(memory->bo, &metadata);
2204 }
2205
2206 return device->ws->buffer_get_fd(device->ws, memory->bo,
2207 pFD);
2208 }
2209
2210 VkResult radv_AllocateMemory(
2211 VkDevice _device,
2212 const VkMemoryAllocateInfo* pAllocateInfo,
2213 const VkAllocationCallbacks* pAllocator,
2214 VkDeviceMemory* pMem)
2215 {
2216 RADV_FROM_HANDLE(radv_device, device, _device);
2217 struct radv_device_memory *mem;
2218 VkResult result;
2219 enum radeon_bo_domain domain;
2220 uint32_t flags = 0;
2221
2222 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2223
2224 if (pAllocateInfo->allocationSize == 0) {
2225 /* Apparently, this is allowed */
2226 *pMem = VK_NULL_HANDLE;
2227 return VK_SUCCESS;
2228 }
2229
2230 const VkImportMemoryFdInfoKHR *import_info =
2231 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2232 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2233 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2234
2235 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2236 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2237 if (mem == NULL)
2238 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2239
2240 if (dedicate_info) {
2241 mem->image = radv_image_from_handle(dedicate_info->image);
2242 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2243 } else {
2244 mem->image = NULL;
2245 mem->buffer = NULL;
2246 }
2247
2248 if (import_info) {
2249 assert(import_info->handleType ==
2250 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2251 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2252 NULL, NULL);
2253 if (!mem->bo) {
2254 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2255 goto fail;
2256 } else {
2257 close(import_info->fd);
2258 goto out_success;
2259 }
2260 }
2261
2262 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2263 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2264 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2265 domain = RADEON_DOMAIN_GTT;
2266 else
2267 domain = RADEON_DOMAIN_VRAM;
2268
2269 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2270 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2271 else
2272 flags |= RADEON_FLAG_CPU_ACCESS;
2273
2274 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2275 flags |= RADEON_FLAG_GTT_WC;
2276
2277 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2278 domain, flags);
2279
2280 if (!mem->bo) {
2281 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2282 goto fail;
2283 }
2284 mem->type_index = pAllocateInfo->memoryTypeIndex;
2285 out_success:
2286 *pMem = radv_device_memory_to_handle(mem);
2287
2288 return VK_SUCCESS;
2289
2290 fail:
2291 vk_free2(&device->alloc, pAllocator, mem);
2292
2293 return result;
2294 }
2295
2296 void radv_FreeMemory(
2297 VkDevice _device,
2298 VkDeviceMemory _mem,
2299 const VkAllocationCallbacks* pAllocator)
2300 {
2301 RADV_FROM_HANDLE(radv_device, device, _device);
2302 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2303
2304 if (mem == NULL)
2305 return;
2306
2307 device->ws->buffer_destroy(mem->bo);
2308 mem->bo = NULL;
2309
2310 vk_free2(&device->alloc, pAllocator, mem);
2311 }
2312
2313 VkResult radv_MapMemory(
2314 VkDevice _device,
2315 VkDeviceMemory _memory,
2316 VkDeviceSize offset,
2317 VkDeviceSize size,
2318 VkMemoryMapFlags flags,
2319 void** ppData)
2320 {
2321 RADV_FROM_HANDLE(radv_device, device, _device);
2322 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2323
2324 if (mem == NULL) {
2325 *ppData = NULL;
2326 return VK_SUCCESS;
2327 }
2328
2329 *ppData = device->ws->buffer_map(mem->bo);
2330 if (*ppData) {
2331 *ppData += offset;
2332 return VK_SUCCESS;
2333 }
2334
2335 return VK_ERROR_MEMORY_MAP_FAILED;
2336 }
2337
2338 void radv_UnmapMemory(
2339 VkDevice _device,
2340 VkDeviceMemory _memory)
2341 {
2342 RADV_FROM_HANDLE(radv_device, device, _device);
2343 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2344
2345 if (mem == NULL)
2346 return;
2347
2348 device->ws->buffer_unmap(mem->bo);
2349 }
2350
2351 VkResult radv_FlushMappedMemoryRanges(
2352 VkDevice _device,
2353 uint32_t memoryRangeCount,
2354 const VkMappedMemoryRange* pMemoryRanges)
2355 {
2356 return VK_SUCCESS;
2357 }
2358
2359 VkResult radv_InvalidateMappedMemoryRanges(
2360 VkDevice _device,
2361 uint32_t memoryRangeCount,
2362 const VkMappedMemoryRange* pMemoryRanges)
2363 {
2364 return VK_SUCCESS;
2365 }
2366
2367 void radv_GetBufferMemoryRequirements(
2368 VkDevice device,
2369 VkBuffer _buffer,
2370 VkMemoryRequirements* pMemoryRequirements)
2371 {
2372 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2373
2374 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2375
2376 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2377 pMemoryRequirements->alignment = 4096;
2378 else
2379 pMemoryRequirements->alignment = 16;
2380
2381 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2382 }
2383
2384 void radv_GetBufferMemoryRequirements2KHR(
2385 VkDevice device,
2386 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2387 VkMemoryRequirements2KHR* pMemoryRequirements)
2388 {
2389 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2390 &pMemoryRequirements->memoryRequirements);
2391
2392 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2393 switch (ext->sType) {
2394 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2395 VkMemoryDedicatedRequirementsKHR *req =
2396 (VkMemoryDedicatedRequirementsKHR *) ext;
2397 req->requiresDedicatedAllocation = false;
2398 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2399 break;
2400 }
2401 default:
2402 break;
2403 }
2404 }
2405 }
2406
2407 void radv_GetImageMemoryRequirements(
2408 VkDevice device,
2409 VkImage _image,
2410 VkMemoryRequirements* pMemoryRequirements)
2411 {
2412 RADV_FROM_HANDLE(radv_image, image, _image);
2413
2414 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2415
2416 pMemoryRequirements->size = image->size;
2417 pMemoryRequirements->alignment = image->alignment;
2418 }
2419
2420 void radv_GetImageMemoryRequirements2KHR(
2421 VkDevice device,
2422 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2423 VkMemoryRequirements2KHR* pMemoryRequirements)
2424 {
2425 radv_GetImageMemoryRequirements(device, pInfo->image,
2426 &pMemoryRequirements->memoryRequirements);
2427
2428 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2429
2430 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2431 switch (ext->sType) {
2432 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2433 VkMemoryDedicatedRequirementsKHR *req =
2434 (VkMemoryDedicatedRequirementsKHR *) ext;
2435 req->requiresDedicatedAllocation = image->shareable;
2436 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2437 break;
2438 }
2439 default:
2440 break;
2441 }
2442 }
2443 }
2444
2445 void radv_GetImageSparseMemoryRequirements(
2446 VkDevice device,
2447 VkImage image,
2448 uint32_t* pSparseMemoryRequirementCount,
2449 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2450 {
2451 stub();
2452 }
2453
2454 void radv_GetImageSparseMemoryRequirements2KHR(
2455 VkDevice device,
2456 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2457 uint32_t* pSparseMemoryRequirementCount,
2458 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2459 {
2460 stub();
2461 }
2462
2463 void radv_GetDeviceMemoryCommitment(
2464 VkDevice device,
2465 VkDeviceMemory memory,
2466 VkDeviceSize* pCommittedMemoryInBytes)
2467 {
2468 *pCommittedMemoryInBytes = 0;
2469 }
2470
2471 VkResult radv_BindBufferMemory(
2472 VkDevice device,
2473 VkBuffer _buffer,
2474 VkDeviceMemory _memory,
2475 VkDeviceSize memoryOffset)
2476 {
2477 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2478 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2479
2480 if (mem) {
2481 buffer->bo = mem->bo;
2482 buffer->offset = memoryOffset;
2483 } else {
2484 buffer->bo = NULL;
2485 buffer->offset = 0;
2486 }
2487
2488 return VK_SUCCESS;
2489 }
2490
2491 VkResult radv_BindImageMemory(
2492 VkDevice device,
2493 VkImage _image,
2494 VkDeviceMemory _memory,
2495 VkDeviceSize memoryOffset)
2496 {
2497 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2498 RADV_FROM_HANDLE(radv_image, image, _image);
2499
2500 if (mem) {
2501 image->bo = mem->bo;
2502 image->offset = memoryOffset;
2503 } else {
2504 image->bo = NULL;
2505 image->offset = 0;
2506 }
2507
2508 return VK_SUCCESS;
2509 }
2510
2511
2512 static void
2513 radv_sparse_buffer_bind_memory(struct radv_device *device,
2514 const VkSparseBufferMemoryBindInfo *bind)
2515 {
2516 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2517
2518 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2519 struct radv_device_memory *mem = NULL;
2520
2521 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2522 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2523
2524 device->ws->buffer_virtual_bind(buffer->bo,
2525 bind->pBinds[i].resourceOffset,
2526 bind->pBinds[i].size,
2527 mem ? mem->bo : NULL,
2528 bind->pBinds[i].memoryOffset);
2529 }
2530 }
2531
2532 static void
2533 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2534 const VkSparseImageOpaqueMemoryBindInfo *bind)
2535 {
2536 RADV_FROM_HANDLE(radv_image, image, bind->image);
2537
2538 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2539 struct radv_device_memory *mem = NULL;
2540
2541 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2542 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2543
2544 device->ws->buffer_virtual_bind(image->bo,
2545 bind->pBinds[i].resourceOffset,
2546 bind->pBinds[i].size,
2547 mem ? mem->bo : NULL,
2548 bind->pBinds[i].memoryOffset);
2549 }
2550 }
2551
2552 VkResult radv_QueueBindSparse(
2553 VkQueue _queue,
2554 uint32_t bindInfoCount,
2555 const VkBindSparseInfo* pBindInfo,
2556 VkFence _fence)
2557 {
2558 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2559 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2560 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2561 bool fence_emitted = false;
2562
2563 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2564 struct radv_winsys_sem_info sem_info;
2565 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2566 radv_sparse_buffer_bind_memory(queue->device,
2567 pBindInfo[i].pBufferBinds + j);
2568 }
2569
2570 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2571 radv_sparse_image_opaque_bind_memory(queue->device,
2572 pBindInfo[i].pImageOpaqueBinds + j);
2573 }
2574
2575 VkResult result;
2576 result = radv_alloc_sem_info(&sem_info,
2577 pBindInfo[i].waitSemaphoreCount,
2578 pBindInfo[i].pWaitSemaphores,
2579 pBindInfo[i].signalSemaphoreCount,
2580 pBindInfo[i].pSignalSemaphores);
2581 if (result != VK_SUCCESS)
2582 return result;
2583
2584 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2585 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2586 &queue->device->empty_cs[queue->queue_family_index],
2587 1, NULL, NULL,
2588 &sem_info,
2589 false, base_fence);
2590 fence_emitted = true;
2591 if (fence)
2592 fence->submitted = true;
2593 }
2594
2595 radv_free_sem_info(&sem_info);
2596
2597 }
2598
2599 if (fence && !fence_emitted) {
2600 fence->signalled = true;
2601 }
2602
2603 return VK_SUCCESS;
2604 }
2605
2606 VkResult radv_CreateFence(
2607 VkDevice _device,
2608 const VkFenceCreateInfo* pCreateInfo,
2609 const VkAllocationCallbacks* pAllocator,
2610 VkFence* pFence)
2611 {
2612 RADV_FROM_HANDLE(radv_device, device, _device);
2613 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2614 sizeof(*fence), 8,
2615 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2616
2617 if (!fence)
2618 return VK_ERROR_OUT_OF_HOST_MEMORY;
2619
2620 memset(fence, 0, sizeof(*fence));
2621 fence->submitted = false;
2622 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2623 fence->fence = device->ws->create_fence();
2624 if (!fence->fence) {
2625 vk_free2(&device->alloc, pAllocator, fence);
2626 return VK_ERROR_OUT_OF_HOST_MEMORY;
2627 }
2628
2629 *pFence = radv_fence_to_handle(fence);
2630
2631 return VK_SUCCESS;
2632 }
2633
2634 void radv_DestroyFence(
2635 VkDevice _device,
2636 VkFence _fence,
2637 const VkAllocationCallbacks* pAllocator)
2638 {
2639 RADV_FROM_HANDLE(radv_device, device, _device);
2640 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2641
2642 if (!fence)
2643 return;
2644 device->ws->destroy_fence(fence->fence);
2645 vk_free2(&device->alloc, pAllocator, fence);
2646 }
2647
2648 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2649 {
2650 uint64_t current_time;
2651 struct timespec tv;
2652
2653 clock_gettime(CLOCK_MONOTONIC, &tv);
2654 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2655
2656 timeout = MIN2(UINT64_MAX - current_time, timeout);
2657
2658 return current_time + timeout;
2659 }
2660
2661 VkResult radv_WaitForFences(
2662 VkDevice _device,
2663 uint32_t fenceCount,
2664 const VkFence* pFences,
2665 VkBool32 waitAll,
2666 uint64_t timeout)
2667 {
2668 RADV_FROM_HANDLE(radv_device, device, _device);
2669 timeout = radv_get_absolute_timeout(timeout);
2670
2671 if (!waitAll && fenceCount > 1) {
2672 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2673 }
2674
2675 for (uint32_t i = 0; i < fenceCount; ++i) {
2676 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2677 bool expired = false;
2678
2679 if (fence->signalled)
2680 continue;
2681
2682 if (!fence->submitted)
2683 return VK_TIMEOUT;
2684
2685 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2686 if (!expired)
2687 return VK_TIMEOUT;
2688
2689 fence->signalled = true;
2690 }
2691
2692 return VK_SUCCESS;
2693 }
2694
2695 VkResult radv_ResetFences(VkDevice device,
2696 uint32_t fenceCount,
2697 const VkFence *pFences)
2698 {
2699 for (unsigned i = 0; i < fenceCount; ++i) {
2700 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2701 fence->submitted = fence->signalled = false;
2702 }
2703
2704 return VK_SUCCESS;
2705 }
2706
2707 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2708 {
2709 RADV_FROM_HANDLE(radv_device, device, _device);
2710 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2711
2712 if (fence->signalled)
2713 return VK_SUCCESS;
2714 if (!fence->submitted)
2715 return VK_NOT_READY;
2716
2717 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2718 return VK_NOT_READY;
2719
2720 return VK_SUCCESS;
2721 }
2722
2723
2724 // Queue semaphore functions
2725
2726 VkResult radv_CreateSemaphore(
2727 VkDevice _device,
2728 const VkSemaphoreCreateInfo* pCreateInfo,
2729 const VkAllocationCallbacks* pAllocator,
2730 VkSemaphore* pSemaphore)
2731 {
2732 RADV_FROM_HANDLE(radv_device, device, _device);
2733 const VkExportSemaphoreCreateInfoKHR *export =
2734 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2735 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2736 export ? export->handleTypes : 0;
2737
2738 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2739 sizeof(*sem), 8,
2740 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2741 if (!sem)
2742 return VK_ERROR_OUT_OF_HOST_MEMORY;
2743
2744 sem->temp_syncobj = 0;
2745 /* create a syncobject if we are going to export this semaphore */
2746 if (handleTypes) {
2747 assert (device->physical_device->rad_info.has_syncobj);
2748 assert (handleTypes == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2749 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2750 if (ret) {
2751 vk_free2(&device->alloc, pAllocator, sem);
2752 return VK_ERROR_OUT_OF_HOST_MEMORY;
2753 }
2754 sem->sem = NULL;
2755 } else {
2756 sem->sem = device->ws->create_sem(device->ws);
2757 if (!sem->sem) {
2758 vk_free2(&device->alloc, pAllocator, sem);
2759 return VK_ERROR_OUT_OF_HOST_MEMORY;
2760 }
2761 sem->syncobj = 0;
2762 }
2763
2764 *pSemaphore = radv_semaphore_to_handle(sem);
2765 return VK_SUCCESS;
2766 }
2767
2768 void radv_DestroySemaphore(
2769 VkDevice _device,
2770 VkSemaphore _semaphore,
2771 const VkAllocationCallbacks* pAllocator)
2772 {
2773 RADV_FROM_HANDLE(radv_device, device, _device);
2774 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2775 if (!_semaphore)
2776 return;
2777
2778 if (sem->syncobj)
2779 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2780 else
2781 device->ws->destroy_sem(sem->sem);
2782 vk_free2(&device->alloc, pAllocator, sem);
2783 }
2784
2785 VkResult radv_CreateEvent(
2786 VkDevice _device,
2787 const VkEventCreateInfo* pCreateInfo,
2788 const VkAllocationCallbacks* pAllocator,
2789 VkEvent* pEvent)
2790 {
2791 RADV_FROM_HANDLE(radv_device, device, _device);
2792 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2793 sizeof(*event), 8,
2794 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2795
2796 if (!event)
2797 return VK_ERROR_OUT_OF_HOST_MEMORY;
2798
2799 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2800 RADEON_DOMAIN_GTT,
2801 RADEON_FLAG_CPU_ACCESS);
2802 if (!event->bo) {
2803 vk_free2(&device->alloc, pAllocator, event);
2804 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2805 }
2806
2807 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2808
2809 *pEvent = radv_event_to_handle(event);
2810
2811 return VK_SUCCESS;
2812 }
2813
2814 void radv_DestroyEvent(
2815 VkDevice _device,
2816 VkEvent _event,
2817 const VkAllocationCallbacks* pAllocator)
2818 {
2819 RADV_FROM_HANDLE(radv_device, device, _device);
2820 RADV_FROM_HANDLE(radv_event, event, _event);
2821
2822 if (!event)
2823 return;
2824 device->ws->buffer_destroy(event->bo);
2825 vk_free2(&device->alloc, pAllocator, event);
2826 }
2827
2828 VkResult radv_GetEventStatus(
2829 VkDevice _device,
2830 VkEvent _event)
2831 {
2832 RADV_FROM_HANDLE(radv_event, event, _event);
2833
2834 if (*event->map == 1)
2835 return VK_EVENT_SET;
2836 return VK_EVENT_RESET;
2837 }
2838
2839 VkResult radv_SetEvent(
2840 VkDevice _device,
2841 VkEvent _event)
2842 {
2843 RADV_FROM_HANDLE(radv_event, event, _event);
2844 *event->map = 1;
2845
2846 return VK_SUCCESS;
2847 }
2848
2849 VkResult radv_ResetEvent(
2850 VkDevice _device,
2851 VkEvent _event)
2852 {
2853 RADV_FROM_HANDLE(radv_event, event, _event);
2854 *event->map = 0;
2855
2856 return VK_SUCCESS;
2857 }
2858
2859 VkResult radv_CreateBuffer(
2860 VkDevice _device,
2861 const VkBufferCreateInfo* pCreateInfo,
2862 const VkAllocationCallbacks* pAllocator,
2863 VkBuffer* pBuffer)
2864 {
2865 RADV_FROM_HANDLE(radv_device, device, _device);
2866 struct radv_buffer *buffer;
2867
2868 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2869
2870 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2871 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2872 if (buffer == NULL)
2873 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2874
2875 buffer->size = pCreateInfo->size;
2876 buffer->usage = pCreateInfo->usage;
2877 buffer->bo = NULL;
2878 buffer->offset = 0;
2879 buffer->flags = pCreateInfo->flags;
2880
2881 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2882 buffer->bo = device->ws->buffer_create(device->ws,
2883 align64(buffer->size, 4096),
2884 4096, 0, RADEON_FLAG_VIRTUAL);
2885 if (!buffer->bo) {
2886 vk_free2(&device->alloc, pAllocator, buffer);
2887 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2888 }
2889 }
2890
2891 *pBuffer = radv_buffer_to_handle(buffer);
2892
2893 return VK_SUCCESS;
2894 }
2895
2896 void radv_DestroyBuffer(
2897 VkDevice _device,
2898 VkBuffer _buffer,
2899 const VkAllocationCallbacks* pAllocator)
2900 {
2901 RADV_FROM_HANDLE(radv_device, device, _device);
2902 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2903
2904 if (!buffer)
2905 return;
2906
2907 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2908 device->ws->buffer_destroy(buffer->bo);
2909
2910 vk_free2(&device->alloc, pAllocator, buffer);
2911 }
2912
2913 static inline unsigned
2914 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2915 {
2916 if (stencil)
2917 return image->surface.u.legacy.stencil_tiling_index[level];
2918 else
2919 return image->surface.u.legacy.tiling_index[level];
2920 }
2921
2922 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2923 {
2924 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2925 }
2926
2927 static void
2928 radv_initialise_color_surface(struct radv_device *device,
2929 struct radv_color_buffer_info *cb,
2930 struct radv_image_view *iview)
2931 {
2932 const struct vk_format_description *desc;
2933 unsigned ntype, format, swap, endian;
2934 unsigned blend_clamp = 0, blend_bypass = 0;
2935 uint64_t va;
2936 const struct radeon_surf *surf = &iview->image->surface;
2937
2938 desc = vk_format_description(iview->vk_format);
2939
2940 memset(cb, 0, sizeof(*cb));
2941
2942 /* Intensity is implemented as Red, so treat it that way. */
2943 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
2944
2945 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2946
2947 if (device->physical_device->rad_info.chip_class >= GFX9) {
2948 struct gfx9_surf_meta_flags meta;
2949 if (iview->image->dcc_offset)
2950 meta = iview->image->surface.u.gfx9.dcc;
2951 else
2952 meta = iview->image->surface.u.gfx9.cmask;
2953
2954 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
2955 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
2956 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2957 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2958
2959 va += iview->image->surface.u.gfx9.surf_offset >> 8;
2960 } else {
2961 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
2962 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2963
2964 va += level_info->offset;
2965
2966 pitch_tile_max = level_info->nblk_x / 8 - 1;
2967 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2968 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2969
2970 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2971 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2972 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2973
2974 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2975 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2976
2977 if (iview->image->fmask.size) {
2978 if (device->physical_device->rad_info.chip_class >= CIK)
2979 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2980 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2981 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2982 } else {
2983 /* This must be set for fast clear to work without FMASK. */
2984 if (device->physical_device->rad_info.chip_class >= CIK)
2985 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2986 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2987 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2988 }
2989 }
2990
2991 cb->cb_color_base = va >> 8;
2992 if (device->physical_device->rad_info.chip_class < GFX9)
2993 cb->cb_color_base |= iview->image->surface.u.legacy.tile_swizzle;
2994 /* CMASK variables */
2995 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2996 va += iview->image->cmask.offset;
2997 cb->cb_color_cmask = va >> 8;
2998
2999 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3000 va += iview->image->dcc_offset;
3001 cb->cb_dcc_base = va >> 8;
3002 if (device->physical_device->rad_info.chip_class < GFX9)
3003 cb->cb_dcc_base |= iview->image->surface.u.legacy.tile_swizzle;
3004
3005 uint32_t max_slice = radv_surface_layer_count(iview);
3006 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3007 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
3008
3009 if (iview->image->info.samples > 1) {
3010 unsigned log_samples = util_logbase2(iview->image->info.samples);
3011
3012 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3013 S_028C74_NUM_FRAGMENTS(log_samples);
3014 }
3015
3016 if (iview->image->fmask.size) {
3017 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3018 cb->cb_color_fmask = va >> 8;
3019 if (device->physical_device->rad_info.chip_class < GFX9)
3020 cb->cb_color_fmask |= iview->image->surface.u.legacy.tile_swizzle;
3021 } else {
3022 cb->cb_color_fmask = cb->cb_color_base;
3023 }
3024
3025 ntype = radv_translate_color_numformat(iview->vk_format,
3026 desc,
3027 vk_format_get_first_non_void_channel(iview->vk_format));
3028 format = radv_translate_colorformat(iview->vk_format);
3029 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3030 radv_finishme("Illegal color\n");
3031 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3032 endian = radv_colorformat_endian_swap(format);
3033
3034 /* blend clamp should be set for all NORM/SRGB types */
3035 if (ntype == V_028C70_NUMBER_UNORM ||
3036 ntype == V_028C70_NUMBER_SNORM ||
3037 ntype == V_028C70_NUMBER_SRGB)
3038 blend_clamp = 1;
3039
3040 /* set blend bypass according to docs if SINT/UINT or
3041 8/24 COLOR variants */
3042 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3043 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3044 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3045 blend_clamp = 0;
3046 blend_bypass = 1;
3047 }
3048 #if 0
3049 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3050 (format == V_028C70_COLOR_8 ||
3051 format == V_028C70_COLOR_8_8 ||
3052 format == V_028C70_COLOR_8_8_8_8))
3053 ->color_is_int8 = true;
3054 #endif
3055 cb->cb_color_info = S_028C70_FORMAT(format) |
3056 S_028C70_COMP_SWAP(swap) |
3057 S_028C70_BLEND_CLAMP(blend_clamp) |
3058 S_028C70_BLEND_BYPASS(blend_bypass) |
3059 S_028C70_SIMPLE_FLOAT(1) |
3060 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3061 ntype != V_028C70_NUMBER_SNORM &&
3062 ntype != V_028C70_NUMBER_SRGB &&
3063 format != V_028C70_COLOR_8_24 &&
3064 format != V_028C70_COLOR_24_8) |
3065 S_028C70_NUMBER_TYPE(ntype) |
3066 S_028C70_ENDIAN(endian);
3067 if (iview->image->info.samples > 1)
3068 if (iview->image->fmask.size)
3069 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3070
3071 if (iview->image->cmask.size &&
3072 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3073 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3074
3075 if (iview->image->surface.dcc_size && iview->base_mip < surf->num_dcc_levels)
3076 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3077
3078 if (device->physical_device->rad_info.chip_class >= VI) {
3079 unsigned max_uncompressed_block_size = 2;
3080 if (iview->image->info.samples > 1) {
3081 if (iview->image->surface.bpe == 1)
3082 max_uncompressed_block_size = 0;
3083 else if (iview->image->surface.bpe == 2)
3084 max_uncompressed_block_size = 1;
3085 }
3086
3087 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3088 S_028C78_INDEPENDENT_64B_BLOCKS(1);
3089 }
3090
3091 /* This must be set for fast clear to work without FMASK. */
3092 if (!iview->image->fmask.size &&
3093 device->physical_device->rad_info.chip_class == SI) {
3094 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3095 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3096 }
3097
3098 if (device->physical_device->rad_info.chip_class >= GFX9) {
3099 uint32_t max_slice = radv_surface_layer_count(iview);
3100 unsigned mip0_depth = iview->base_layer + max_slice - 1;
3101
3102 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3103 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3104 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3105 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->image->info.width - 1) |
3106 S_028C68_MIP0_HEIGHT(iview->image->info.height - 1) |
3107 S_028C68_MAX_MIP(iview->image->info.levels);
3108
3109 cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3110
3111 }
3112 }
3113
3114 static void
3115 radv_initialise_ds_surface(struct radv_device *device,
3116 struct radv_ds_buffer_info *ds,
3117 struct radv_image_view *iview)
3118 {
3119 unsigned level = iview->base_mip;
3120 unsigned format, stencil_format;
3121 uint64_t va, s_offs, z_offs;
3122 bool stencil_only = false;
3123 memset(ds, 0, sizeof(*ds));
3124 switch (iview->image->vk_format) {
3125 case VK_FORMAT_D24_UNORM_S8_UINT:
3126 case VK_FORMAT_X8_D24_UNORM_PACK32:
3127 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3128 ds->offset_scale = 2.0f;
3129 break;
3130 case VK_FORMAT_D16_UNORM:
3131 case VK_FORMAT_D16_UNORM_S8_UINT:
3132 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3133 ds->offset_scale = 4.0f;
3134 break;
3135 case VK_FORMAT_D32_SFLOAT:
3136 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3137 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3138 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3139 ds->offset_scale = 1.0f;
3140 break;
3141 case VK_FORMAT_S8_UINT:
3142 stencil_only = true;
3143 break;
3144 default:
3145 break;
3146 }
3147
3148 format = radv_translate_dbformat(iview->image->vk_format);
3149 stencil_format = iview->image->surface.flags & RADEON_SURF_SBUFFER ?
3150 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3151
3152 uint32_t max_slice = radv_surface_layer_count(iview);
3153 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3154 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
3155
3156 ds->db_htile_data_base = 0;
3157 ds->db_htile_surface = 0;
3158
3159 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3160 s_offs = z_offs = va;
3161
3162 if (device->physical_device->rad_info.chip_class >= GFX9) {
3163 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3164 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3165
3166 ds->db_z_info = S_028038_FORMAT(format) |
3167 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3168 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3169 S_028038_MAXMIP(iview->image->info.levels - 1);
3170 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3171 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3172
3173 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3174 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3175 ds->db_depth_view |= S_028008_MIPID(level);
3176
3177 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3178 S_02801C_Y_MAX(iview->image->info.height - 1);
3179
3180 /* Only use HTILE for the first level. */
3181 if (iview->image->surface.htile_size && !level) {
3182 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3183
3184 if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
3185 /* Use all of the htile_buffer for depth if there's no stencil. */
3186 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3187 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
3188 iview->image->htile_offset;
3189 ds->db_htile_data_base = va >> 8;
3190 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3191 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3192 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3193 }
3194 } else {
3195 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3196
3197 if (stencil_only)
3198 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3199
3200 z_offs += iview->image->surface.u.legacy.level[level].offset;
3201 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3202
3203 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
3204 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3205 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3206
3207 if (iview->image->info.samples > 1)
3208 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3209
3210 if (device->physical_device->rad_info.chip_class >= CIK) {
3211 struct radeon_info *info = &device->physical_device->rad_info;
3212 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3213 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3214 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3215 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3216 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3217 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3218
3219 if (stencil_only)
3220 tile_mode = stencil_tile_mode;
3221
3222 ds->db_depth_info |=
3223 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3224 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3225 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3226 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3227 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3228 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3229 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3230 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3231 } else {
3232 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3233 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3234 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3235 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3236 }
3237
3238 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3239 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3240 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3241
3242 if (iview->image->surface.htile_size && !level) {
3243 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3244
3245 if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
3246 /* Use all of the htile_buffer for depth if there's no stencil. */
3247 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3248
3249 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
3250 iview->image->htile_offset;
3251 ds->db_htile_data_base = va >> 8;
3252 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3253 }
3254 }
3255
3256 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3257 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3258 }
3259
3260 VkResult radv_CreateFramebuffer(
3261 VkDevice _device,
3262 const VkFramebufferCreateInfo* pCreateInfo,
3263 const VkAllocationCallbacks* pAllocator,
3264 VkFramebuffer* pFramebuffer)
3265 {
3266 RADV_FROM_HANDLE(radv_device, device, _device);
3267 struct radv_framebuffer *framebuffer;
3268
3269 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3270
3271 size_t size = sizeof(*framebuffer) +
3272 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3273 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3274 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3275 if (framebuffer == NULL)
3276 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3277
3278 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3279 framebuffer->width = pCreateInfo->width;
3280 framebuffer->height = pCreateInfo->height;
3281 framebuffer->layers = pCreateInfo->layers;
3282 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3283 VkImageView _iview = pCreateInfo->pAttachments[i];
3284 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3285 framebuffer->attachments[i].attachment = iview;
3286 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3287 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3288 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3289 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3290 }
3291 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3292 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3293 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
3294 }
3295
3296 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3297 return VK_SUCCESS;
3298 }
3299
3300 void radv_DestroyFramebuffer(
3301 VkDevice _device,
3302 VkFramebuffer _fb,
3303 const VkAllocationCallbacks* pAllocator)
3304 {
3305 RADV_FROM_HANDLE(radv_device, device, _device);
3306 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3307
3308 if (!fb)
3309 return;
3310 vk_free2(&device->alloc, pAllocator, fb);
3311 }
3312
3313 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3314 {
3315 switch (address_mode) {
3316 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3317 return V_008F30_SQ_TEX_WRAP;
3318 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3319 return V_008F30_SQ_TEX_MIRROR;
3320 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3321 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3322 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3323 return V_008F30_SQ_TEX_CLAMP_BORDER;
3324 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3325 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3326 default:
3327 unreachable("illegal tex wrap mode");
3328 break;
3329 }
3330 }
3331
3332 static unsigned
3333 radv_tex_compare(VkCompareOp op)
3334 {
3335 switch (op) {
3336 case VK_COMPARE_OP_NEVER:
3337 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3338 case VK_COMPARE_OP_LESS:
3339 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3340 case VK_COMPARE_OP_EQUAL:
3341 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3342 case VK_COMPARE_OP_LESS_OR_EQUAL:
3343 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3344 case VK_COMPARE_OP_GREATER:
3345 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3346 case VK_COMPARE_OP_NOT_EQUAL:
3347 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3348 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3349 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3350 case VK_COMPARE_OP_ALWAYS:
3351 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3352 default:
3353 unreachable("illegal compare mode");
3354 break;
3355 }
3356 }
3357
3358 static unsigned
3359 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3360 {
3361 switch (filter) {
3362 case VK_FILTER_NEAREST:
3363 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3364 V_008F38_SQ_TEX_XY_FILTER_POINT);
3365 case VK_FILTER_LINEAR:
3366 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3367 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3368 case VK_FILTER_CUBIC_IMG:
3369 default:
3370 fprintf(stderr, "illegal texture filter");
3371 return 0;
3372 }
3373 }
3374
3375 static unsigned
3376 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3377 {
3378 switch (mode) {
3379 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3380 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3381 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3382 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3383 default:
3384 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3385 }
3386 }
3387
3388 static unsigned
3389 radv_tex_bordercolor(VkBorderColor bcolor)
3390 {
3391 switch (bcolor) {
3392 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3393 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3394 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3395 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3396 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3397 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3398 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3399 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3400 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3401 default:
3402 break;
3403 }
3404 return 0;
3405 }
3406
3407 static unsigned
3408 radv_tex_aniso_filter(unsigned filter)
3409 {
3410 if (filter < 2)
3411 return 0;
3412 if (filter < 4)
3413 return 1;
3414 if (filter < 8)
3415 return 2;
3416 if (filter < 16)
3417 return 3;
3418 return 4;
3419 }
3420
3421 static void
3422 radv_init_sampler(struct radv_device *device,
3423 struct radv_sampler *sampler,
3424 const VkSamplerCreateInfo *pCreateInfo)
3425 {
3426 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3427 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3428 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3429 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3430
3431 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3432 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3433 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3434 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3435 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3436 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3437 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3438 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3439 S_008F30_DISABLE_CUBE_WRAP(0) |
3440 S_008F30_COMPAT_MODE(is_vi));
3441 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3442 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3443 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3444 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3445 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3446 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3447 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3448 S_008F38_MIP_POINT_PRECLAMP(0) |
3449 S_008F38_DISABLE_LSB_CEIL(1) |
3450 S_008F38_FILTER_PREC_FIX(1) |
3451 S_008F38_ANISO_OVERRIDE(is_vi));
3452 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3453 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3454 }
3455
3456 VkResult radv_CreateSampler(
3457 VkDevice _device,
3458 const VkSamplerCreateInfo* pCreateInfo,
3459 const VkAllocationCallbacks* pAllocator,
3460 VkSampler* pSampler)
3461 {
3462 RADV_FROM_HANDLE(radv_device, device, _device);
3463 struct radv_sampler *sampler;
3464
3465 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3466
3467 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3468 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3469 if (!sampler)
3470 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3471
3472 radv_init_sampler(device, sampler, pCreateInfo);
3473 *pSampler = radv_sampler_to_handle(sampler);
3474
3475 return VK_SUCCESS;
3476 }
3477
3478 void radv_DestroySampler(
3479 VkDevice _device,
3480 VkSampler _sampler,
3481 const VkAllocationCallbacks* pAllocator)
3482 {
3483 RADV_FROM_HANDLE(radv_device, device, _device);
3484 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3485
3486 if (!sampler)
3487 return;
3488 vk_free2(&device->alloc, pAllocator, sampler);
3489 }
3490
3491 /* vk_icd.h does not declare this function, so we declare it here to
3492 * suppress Wmissing-prototypes.
3493 */
3494 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3495 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3496
3497 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3498 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3499 {
3500 /* For the full details on loader interface versioning, see
3501 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3502 * What follows is a condensed summary, to help you navigate the large and
3503 * confusing official doc.
3504 *
3505 * - Loader interface v0 is incompatible with later versions. We don't
3506 * support it.
3507 *
3508 * - In loader interface v1:
3509 * - The first ICD entrypoint called by the loader is
3510 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3511 * entrypoint.
3512 * - The ICD must statically expose no other Vulkan symbol unless it is
3513 * linked with -Bsymbolic.
3514 * - Each dispatchable Vulkan handle created by the ICD must be
3515 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3516 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3517 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3518 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3519 * such loader-managed surfaces.
3520 *
3521 * - Loader interface v2 differs from v1 in:
3522 * - The first ICD entrypoint called by the loader is
3523 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3524 * statically expose this entrypoint.
3525 *
3526 * - Loader interface v3 differs from v2 in:
3527 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3528 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3529 * because the loader no longer does so.
3530 */
3531 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3532 return VK_SUCCESS;
3533 }
3534
3535 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3536 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3537 int *pFD)
3538 {
3539 RADV_FROM_HANDLE(radv_device, device, _device);
3540 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3541
3542 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3543
3544 /* We support only one handle type. */
3545 assert(pGetFdInfo->handleType ==
3546 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3547
3548 bool ret = radv_get_memory_fd(device, memory, pFD);
3549 if (ret == false)
3550 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
3551 return VK_SUCCESS;
3552 }
3553
3554 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3555 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3556 int fd,
3557 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3558 {
3559 /* The valid usage section for this function says:
3560 *
3561 * "handleType must not be one of the handle types defined as opaque."
3562 *
3563 * Since we only handle opaque handles for now, there are no FD properties.
3564 */
3565 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3566 }
3567
3568 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3569 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3570 {
3571 RADV_FROM_HANDLE(radv_device, device, _device);
3572 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3573 uint32_t syncobj_handle = 0;
3574 assert(pImportSemaphoreFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3575
3576 int ret = device->ws->import_syncobj(device->ws, pImportSemaphoreFdInfo->fd, &syncobj_handle);
3577 if (ret != 0)
3578 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3579
3580 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3581 sem->temp_syncobj = syncobj_handle;
3582 } else {
3583 sem->syncobj = syncobj_handle;
3584 }
3585 close(pImportSemaphoreFdInfo->fd);
3586 return VK_SUCCESS;
3587 }
3588
3589 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3590 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3591 int *pFd)
3592 {
3593 RADV_FROM_HANDLE(radv_device, device, _device);
3594 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3595 int ret;
3596 uint32_t syncobj_handle;
3597
3598 assert(pGetFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3599 if (sem->temp_syncobj)
3600 syncobj_handle = sem->temp_syncobj;
3601 else
3602 syncobj_handle = sem->syncobj;
3603 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3604 if (ret)
3605 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3606 return VK_SUCCESS;
3607 }
3608
3609 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3610 VkPhysicalDevice physicalDevice,
3611 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3612 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3613 {
3614 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3615 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3616 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3617 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3618
3619 }