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radv: disable subgroup shuffle operations on GFX10
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "dirent.h"
29 #include <errno.h>
30 #include <fcntl.h>
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
36 #include <stdbool.h>
37 #include <stddef.h>
38 #include <stdio.h>
39 #include <string.h>
40 #include <sys/prctl.h>
41 #include <sys/wait.h>
42 #include <unistd.h>
43 #include <fcntl.h>
44 #include <llvm/Config/llvm-config.h>
45
46 #include "radv_debug.h"
47 #include "radv_private.h"
48 #include "radv_shader.h"
49 #include "radv_cs.h"
50 #include "util/disk_cache.h"
51 #include "vk_util.h"
52 #include <xf86drm.h>
53 #include <amdgpu.h>
54 #include <amdgpu_drm.h>
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "ac_llvm_util.h"
57 #include "vk_format.h"
58 #include "sid.h"
59 #include "git_sha1.h"
60 #include "util/build_id.h"
61 #include "util/debug.h"
62 #include "util/mesa-sha1.h"
63 #include "util/timespec.h"
64 #include "util/u_atomic.h"
65 #include "compiler/glsl_types.h"
66 #include "util/xmlpool.h"
67
68 static struct radv_timeline_point *
69 radv_timeline_find_point_at_least_locked(struct radv_device *device,
70 struct radv_timeline *timeline,
71 uint64_t p);
72
73 static struct radv_timeline_point *
74 radv_timeline_add_point_locked(struct radv_device *device,
75 struct radv_timeline *timeline,
76 uint64_t p);
77
78 static void
79 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
80 struct list_head *processing_list);
81
82 static
83 void radv_destroy_semaphore_part(struct radv_device *device,
84 struct radv_semaphore_part *part);
85
86 static int
87 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
88 {
89 struct mesa_sha1 ctx;
90 unsigned char sha1[20];
91 unsigned ptr_size = sizeof(void*);
92
93 memset(uuid, 0, VK_UUID_SIZE);
94 _mesa_sha1_init(&ctx);
95
96 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
97 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
98 return -1;
99
100 _mesa_sha1_update(&ctx, &family, sizeof(family));
101 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
102 _mesa_sha1_final(&ctx, sha1);
103
104 memcpy(uuid, sha1, VK_UUID_SIZE);
105 return 0;
106 }
107
108 static void
109 radv_get_driver_uuid(void *uuid)
110 {
111 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
112 }
113
114 static void
115 radv_get_device_uuid(struct radeon_info *info, void *uuid)
116 {
117 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
118 }
119
120 static uint64_t
121 radv_get_visible_vram_size(struct radv_physical_device *device)
122 {
123 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
124 }
125
126 static uint64_t
127 radv_get_vram_size(struct radv_physical_device *device)
128 {
129 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
130 }
131
132 static bool
133 radv_is_mem_type_vram(enum radv_mem_type type)
134 {
135 return type == RADV_MEM_TYPE_VRAM ||
136 type == RADV_MEM_TYPE_VRAM_UNCACHED;
137 }
138
139 static bool
140 radv_is_mem_type_vram_visible(enum radv_mem_type type)
141 {
142 return type == RADV_MEM_TYPE_VRAM_CPU_ACCESS ||
143 type == RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED;
144 }
145 static bool
146 radv_is_mem_type_gtt_wc(enum radv_mem_type type)
147 {
148 return type == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
149 type == RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED;
150 }
151
152 static bool
153 radv_is_mem_type_gtt_cached(enum radv_mem_type type)
154 {
155 return type == RADV_MEM_TYPE_GTT_CACHED ||
156 type == RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED;
157 }
158
159 static bool
160 radv_is_mem_type_uncached(enum radv_mem_type type)
161 {
162 return type == RADV_MEM_TYPE_VRAM_UNCACHED ||
163 type == RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED ||
164 type == RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED ||
165 type == RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED;
166 }
167
168 static void
169 radv_physical_device_init_mem_types(struct radv_physical_device *device)
170 {
171 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
172 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
173 uint64_t vram_size = radv_get_vram_size(device);
174 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
175 device->memory_properties.memoryHeapCount = 0;
176 if (vram_size > 0) {
177 vram_index = device->memory_properties.memoryHeapCount++;
178 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
179 .size = vram_size,
180 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
181 };
182 }
183 if (visible_vram_size) {
184 visible_vram_index = device->memory_properties.memoryHeapCount++;
185 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
186 .size = visible_vram_size,
187 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
188 };
189 }
190 if (device->rad_info.gart_size > 0) {
191 gart_index = device->memory_properties.memoryHeapCount++;
192 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
193 .size = device->rad_info.gart_size,
194 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
195 };
196 }
197
198 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
199 unsigned type_count = 0;
200 if (vram_index >= 0) {
201 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
202 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
203 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
204 .heapIndex = vram_index,
205 };
206 }
207 if (gart_index >= 0 && device->rad_info.has_dedicated_vram) {
208 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
209 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
210 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
211 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
212 .heapIndex = gart_index,
213 };
214 }
215 if (visible_vram_index >= 0) {
216 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
217 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
218 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
219 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
220 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
221 .heapIndex = visible_vram_index,
222 };
223 }
224 if (gart_index >= 0 && !device->rad_info.has_dedicated_vram) {
225 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
226 * as they have identical property flags, and according to the
227 * spec, for types with identical flags, the one with greater
228 * performance must be given a lower index. */
229 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
230 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
231 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
232 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
233 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
234 .heapIndex = gart_index,
235 };
236 }
237 if (gart_index >= 0) {
238 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
239 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
240 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
241 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
242 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
243 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
244 .heapIndex = gart_index,
245 };
246 }
247 device->memory_properties.memoryTypeCount = type_count;
248
249 if (device->rad_info.has_l2_uncached) {
250 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
251 VkMemoryType mem_type = device->memory_properties.memoryTypes[i];
252
253 if ((mem_type.propertyFlags & (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
254 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)) ||
255 mem_type.propertyFlags == VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) {
256 enum radv_mem_type mem_type_id;
257
258 switch (device->mem_type_indices[i]) {
259 case RADV_MEM_TYPE_VRAM:
260 mem_type_id = RADV_MEM_TYPE_VRAM_UNCACHED;
261 break;
262 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
263 mem_type_id = RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED;
264 break;
265 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
266 mem_type_id = RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED;
267 break;
268 case RADV_MEM_TYPE_GTT_CACHED:
269 mem_type_id = RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED;
270 break;
271 default:
272 unreachable("invalid memory type");
273 }
274
275 VkMemoryPropertyFlags property_flags = mem_type.propertyFlags |
276 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD |
277 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD;
278
279 device->mem_type_indices[type_count] = mem_type_id;
280 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
281 .propertyFlags = property_flags,
282 .heapIndex = mem_type.heapIndex,
283 };
284 }
285 }
286 device->memory_properties.memoryTypeCount = type_count;
287 }
288 }
289
290 static void
291 radv_handle_env_var_force_family(struct radv_physical_device *device)
292 {
293 const char *family = getenv("RADV_FORCE_FAMILY");
294 unsigned i;
295
296 if (!family)
297 return;
298
299 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
300 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
301 /* Override family and chip_class. */
302 device->rad_info.family = i;
303
304 if (i >= CHIP_NAVI10)
305 device->rad_info.chip_class = GFX10;
306 else if (i >= CHIP_VEGA10)
307 device->rad_info.chip_class = GFX9;
308 else if (i >= CHIP_TONGA)
309 device->rad_info.chip_class = GFX8;
310 else if (i >= CHIP_BONAIRE)
311 device->rad_info.chip_class = GFX7;
312 else
313 device->rad_info.chip_class = GFX6;
314
315 return;
316 }
317 }
318
319 fprintf(stderr, "radv: Unknown family: %s\n", family);
320 exit(1);
321 }
322
323 static VkResult
324 radv_physical_device_init(struct radv_physical_device *device,
325 struct radv_instance *instance,
326 drmDevicePtr drm_device)
327 {
328 const char *path = drm_device->nodes[DRM_NODE_RENDER];
329 VkResult result;
330 drmVersionPtr version;
331 int fd;
332 int master_fd = -1;
333
334 fd = open(path, O_RDWR | O_CLOEXEC);
335 if (fd < 0) {
336 if (instance->debug_flags & RADV_DEBUG_STARTUP)
337 radv_logi("Could not open device '%s'", path);
338
339 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
340 }
341
342 version = drmGetVersion(fd);
343 if (!version) {
344 close(fd);
345
346 if (instance->debug_flags & RADV_DEBUG_STARTUP)
347 radv_logi("Could not get the kernel driver version for device '%s'", path);
348
349 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
350 "failed to get version %s: %m", path);
351 }
352
353 if (strcmp(version->name, "amdgpu")) {
354 drmFreeVersion(version);
355 close(fd);
356
357 if (instance->debug_flags & RADV_DEBUG_STARTUP)
358 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
359
360 return VK_ERROR_INCOMPATIBLE_DRIVER;
361 }
362 drmFreeVersion(version);
363
364 if (instance->debug_flags & RADV_DEBUG_STARTUP)
365 radv_logi("Found compatible device '%s'.", path);
366
367 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
368 device->instance = instance;
369
370 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
371 instance->perftest_flags);
372 if (!device->ws) {
373 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
374 goto fail;
375 }
376
377 if (instance->enabled_extensions.KHR_display) {
378 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
379 if (master_fd >= 0) {
380 uint32_t accel_working = 0;
381 struct drm_amdgpu_info request = {
382 .return_pointer = (uintptr_t)&accel_working,
383 .return_size = sizeof(accel_working),
384 .query = AMDGPU_INFO_ACCEL_WORKING
385 };
386
387 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
388 close(master_fd);
389 master_fd = -1;
390 }
391 }
392 }
393
394 device->master_fd = master_fd;
395 device->local_fd = fd;
396 device->ws->query_info(device->ws, &device->rad_info);
397
398 radv_handle_env_var_force_family(device);
399
400 device->use_aco = instance->perftest_flags & RADV_PERFTEST_ACO;
401 if (device->rad_info.chip_class < GFX8 && device->use_aco) {
402 fprintf(stderr, "WARNING: disabling ACO on unsupported GPUs.\n");
403 device->use_aco = false;
404 }
405
406 snprintf(device->name, sizeof(device->name),
407 "AMD RADV%s %s (LLVM " MESA_LLVM_VERSION_STRING ")", device->use_aco ? "/ACO" : "",
408 device->rad_info.name);
409
410 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
411 device->ws->destroy(device->ws);
412 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
413 "cannot generate UUID");
414 goto fail;
415 }
416
417 /* These flags affect shader compilation. */
418 uint64_t shader_env_flags =
419 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
420 (device->use_aco ? 0x2 : 0);
421
422 /* The gpu id is already embedded in the uuid so we just pass "radv"
423 * when creating the cache.
424 */
425 char buf[VK_UUID_SIZE * 2 + 1];
426 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
427 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
428
429 if (device->rad_info.chip_class < GFX8 ||
430 device->rad_info.chip_class > GFX9)
431 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
432
433 radv_get_driver_uuid(&device->driver_uuid);
434 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
435
436 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
437 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
438
439 device->dcc_msaa_allowed =
440 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
441
442 device->use_shader_ballot = device->use_aco || (device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT);
443
444 device->use_ngg = device->rad_info.chip_class >= GFX10 &&
445 device->rad_info.family != CHIP_NAVI14 &&
446 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
447 if (device->use_aco && device->use_ngg) {
448 fprintf(stderr, "WARNING: disabling NGG because ACO is used.\n");
449 device->use_ngg = false;
450 }
451
452 device->use_ngg_streamout = false;
453
454 /* Determine the number of threads per wave for all stages. */
455 device->cs_wave_size = 64;
456 device->ps_wave_size = 64;
457 device->ge_wave_size = 64;
458
459 if (device->rad_info.chip_class >= GFX10) {
460 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
461 device->cs_wave_size = 32;
462
463 /* For pixel shaders, wave64 is recommanded. */
464 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
465 device->ps_wave_size = 32;
466
467 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
468 device->ge_wave_size = 32;
469 }
470
471 radv_physical_device_init_mem_types(device);
472 radv_fill_device_extension_table(device, &device->supported_extensions);
473
474 device->bus_info = *drm_device->businfo.pci;
475
476 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
477 ac_print_gpu_info(&device->rad_info);
478
479 /* The WSI is structured as a layer on top of the driver, so this has
480 * to be the last part of initialization (at least until we get other
481 * semi-layers).
482 */
483 result = radv_init_wsi(device);
484 if (result != VK_SUCCESS) {
485 device->ws->destroy(device->ws);
486 vk_error(instance, result);
487 goto fail;
488 }
489
490 return VK_SUCCESS;
491
492 fail:
493 close(fd);
494 if (master_fd != -1)
495 close(master_fd);
496 return result;
497 }
498
499 static void
500 radv_physical_device_finish(struct radv_physical_device *device)
501 {
502 radv_finish_wsi(device);
503 device->ws->destroy(device->ws);
504 disk_cache_destroy(device->disk_cache);
505 close(device->local_fd);
506 if (device->master_fd != -1)
507 close(device->master_fd);
508 }
509
510 static void *
511 default_alloc_func(void *pUserData, size_t size, size_t align,
512 VkSystemAllocationScope allocationScope)
513 {
514 return malloc(size);
515 }
516
517 static void *
518 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
519 size_t align, VkSystemAllocationScope allocationScope)
520 {
521 return realloc(pOriginal, size);
522 }
523
524 static void
525 default_free_func(void *pUserData, void *pMemory)
526 {
527 free(pMemory);
528 }
529
530 static const VkAllocationCallbacks default_alloc = {
531 .pUserData = NULL,
532 .pfnAllocation = default_alloc_func,
533 .pfnReallocation = default_realloc_func,
534 .pfnFree = default_free_func,
535 };
536
537 static const struct debug_control radv_debug_options[] = {
538 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
539 {"nodcc", RADV_DEBUG_NO_DCC},
540 {"shaders", RADV_DEBUG_DUMP_SHADERS},
541 {"nocache", RADV_DEBUG_NO_CACHE},
542 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
543 {"nohiz", RADV_DEBUG_NO_HIZ},
544 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
545 {"allbos", RADV_DEBUG_ALL_BOS},
546 {"noibs", RADV_DEBUG_NO_IBS},
547 {"spirv", RADV_DEBUG_DUMP_SPIRV},
548 {"vmfaults", RADV_DEBUG_VM_FAULTS},
549 {"zerovram", RADV_DEBUG_ZERO_VRAM},
550 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
551 {"nosisched", RADV_DEBUG_NO_SISCHED},
552 {"preoptir", RADV_DEBUG_PREOPTIR},
553 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
554 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
555 {"info", RADV_DEBUG_INFO},
556 {"errors", RADV_DEBUG_ERRORS},
557 {"startup", RADV_DEBUG_STARTUP},
558 {"checkir", RADV_DEBUG_CHECKIR},
559 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
560 {"nobinning", RADV_DEBUG_NOBINNING},
561 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
562 {"nongg", RADV_DEBUG_NO_NGG},
563 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT},
564 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
565 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
566 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE},
567 {NULL, 0}
568 };
569
570 const char *
571 radv_get_debug_option_name(int id)
572 {
573 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
574 return radv_debug_options[id].string;
575 }
576
577 static const struct debug_control radv_perftest_options[] = {
578 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
579 {"sisched", RADV_PERFTEST_SISCHED},
580 {"localbos", RADV_PERFTEST_LOCAL_BOS},
581 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
582 {"bolist", RADV_PERFTEST_BO_LIST},
583 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
584 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
585 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
586 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
587 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
588 {"dfsm", RADV_PERFTEST_DFSM},
589 {"aco", RADV_PERFTEST_ACO},
590 {NULL, 0}
591 };
592
593 const char *
594 radv_get_perftest_option_name(int id)
595 {
596 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
597 return radv_perftest_options[id].string;
598 }
599
600 static void
601 radv_handle_per_app_options(struct radv_instance *instance,
602 const VkApplicationInfo *info)
603 {
604 const char *name = info ? info->pApplicationName : NULL;
605
606 if (!name)
607 return;
608
609 if (!strcmp(name, "Talos - Linux - 32bit") ||
610 !strcmp(name, "Talos - Linux - 64bit")) {
611 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
612 /* Force enable LLVM sisched for Talos because it looks
613 * safe and it gives few more FPS.
614 */
615 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
616 }
617 } else if (!strcmp(name, "DOOM_VFR")) {
618 /* Work around a Doom VFR game bug */
619 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
620 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
621 /* Workaround for a WaW hazard when LLVM moves/merges
622 * load/store memory operations.
623 * See https://reviews.llvm.org/D61313
624 */
625 if (LLVM_VERSION_MAJOR < 9)
626 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
627 } else if (!strcmp(name, "Wolfenstein: Youngblood")) {
628 if (!(instance->debug_flags & RADV_DEBUG_NO_SHADER_BALLOT)) {
629 /* Force enable VK_AMD_shader_ballot because it looks
630 * safe and it gives a nice boost (+20% on Vega 56 at
631 * this time).
632 */
633 instance->perftest_flags |= RADV_PERFTEST_SHADER_BALLOT;
634 }
635 } else if (!strcmp(name, "Fledge")) {
636 /*
637 * Zero VRAM for "The Surge 2"
638 *
639 * This avoid a hang when when rendering any level. Likely
640 * uninitialized data in an indirect draw.
641 */
642 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
643 }
644 }
645
646 static int radv_get_instance_extension_index(const char *name)
647 {
648 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
649 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
650 return i;
651 }
652 return -1;
653 }
654
655 static const char radv_dri_options_xml[] =
656 DRI_CONF_BEGIN
657 DRI_CONF_SECTION_PERFORMANCE
658 DRI_CONF_ADAPTIVE_SYNC("true")
659 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
660 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
661 DRI_CONF_SECTION_END
662 DRI_CONF_END;
663
664 static void radv_init_dri_options(struct radv_instance *instance)
665 {
666 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
667 driParseConfigFiles(&instance->dri_options,
668 &instance->available_dri_options,
669 0, "radv", NULL,
670 instance->engineName,
671 instance->engineVersion);
672 }
673
674 VkResult radv_CreateInstance(
675 const VkInstanceCreateInfo* pCreateInfo,
676 const VkAllocationCallbacks* pAllocator,
677 VkInstance* pInstance)
678 {
679 struct radv_instance *instance;
680 VkResult result;
681
682 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
683
684 uint32_t client_version;
685 if (pCreateInfo->pApplicationInfo &&
686 pCreateInfo->pApplicationInfo->apiVersion != 0) {
687 client_version = pCreateInfo->pApplicationInfo->apiVersion;
688 } else {
689 client_version = VK_API_VERSION_1_0;
690 }
691
692 const char *engine_name = NULL;
693 uint32_t engine_version = 0;
694 if (pCreateInfo->pApplicationInfo) {
695 engine_name = pCreateInfo->pApplicationInfo->pEngineName;
696 engine_version = pCreateInfo->pApplicationInfo->engineVersion;
697 }
698
699 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
700 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
701 if (!instance)
702 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
703
704 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
705
706 if (pAllocator)
707 instance->alloc = *pAllocator;
708 else
709 instance->alloc = default_alloc;
710
711 instance->apiVersion = client_version;
712 instance->physicalDeviceCount = -1;
713
714 /* Get secure compile thread count. NOTE: We cap this at 32 */
715 #define MAX_SC_PROCS 32
716 char *num_sc_threads = getenv("RADV_SECURE_COMPILE_THREADS");
717 if (num_sc_threads)
718 instance->num_sc_threads = MIN2(strtoul(num_sc_threads, NULL, 10), MAX_SC_PROCS);
719
720 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
721 radv_debug_options);
722
723 /* Disable memory cache when secure compile is set */
724 if (radv_device_use_secure_compile(instance))
725 instance->debug_flags |= RADV_DEBUG_NO_MEMORY_CACHE;
726
727 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
728 radv_perftest_options);
729
730 if (instance->perftest_flags & RADV_PERFTEST_ACO)
731 fprintf(stderr, "WARNING: Experimental compiler backend enabled. Here be dragons! Incorrect rendering, GPU hangs and/or resets are likely\n");
732
733 if (instance->debug_flags & RADV_DEBUG_STARTUP)
734 radv_logi("Created an instance");
735
736 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
737 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
738 int index = radv_get_instance_extension_index(ext_name);
739
740 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
741 vk_free2(&default_alloc, pAllocator, instance);
742 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
743 }
744
745 instance->enabled_extensions.extensions[index] = true;
746 }
747
748 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
749 if (result != VK_SUCCESS) {
750 vk_free2(&default_alloc, pAllocator, instance);
751 return vk_error(instance, result);
752 }
753
754 instance->engineName = vk_strdup(&instance->alloc, engine_name,
755 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
756 instance->engineVersion = engine_version;
757
758 glsl_type_singleton_init_or_ref();
759
760 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
761
762 radv_init_dri_options(instance);
763 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
764
765 *pInstance = radv_instance_to_handle(instance);
766
767 return VK_SUCCESS;
768 }
769
770 void radv_DestroyInstance(
771 VkInstance _instance,
772 const VkAllocationCallbacks* pAllocator)
773 {
774 RADV_FROM_HANDLE(radv_instance, instance, _instance);
775
776 if (!instance)
777 return;
778
779 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
780 radv_physical_device_finish(instance->physicalDevices + i);
781 }
782
783 vk_free(&instance->alloc, instance->engineName);
784
785 VG(VALGRIND_DESTROY_MEMPOOL(instance));
786
787 glsl_type_singleton_decref();
788
789 driDestroyOptionCache(&instance->dri_options);
790 driDestroyOptionInfo(&instance->available_dri_options);
791
792 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
793
794 vk_free(&instance->alloc, instance);
795 }
796
797 static VkResult
798 radv_enumerate_devices(struct radv_instance *instance)
799 {
800 /* TODO: Check for more devices ? */
801 drmDevicePtr devices[8];
802 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
803 int max_devices;
804
805 instance->physicalDeviceCount = 0;
806
807 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
808
809 if (instance->debug_flags & RADV_DEBUG_STARTUP)
810 radv_logi("Found %d drm nodes", max_devices);
811
812 if (max_devices < 1)
813 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
814
815 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
816 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
817 devices[i]->bustype == DRM_BUS_PCI &&
818 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
819
820 result = radv_physical_device_init(instance->physicalDevices +
821 instance->physicalDeviceCount,
822 instance,
823 devices[i]);
824 if (result == VK_SUCCESS)
825 ++instance->physicalDeviceCount;
826 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
827 break;
828 }
829 }
830 drmFreeDevices(devices, max_devices);
831
832 return result;
833 }
834
835 VkResult radv_EnumeratePhysicalDevices(
836 VkInstance _instance,
837 uint32_t* pPhysicalDeviceCount,
838 VkPhysicalDevice* pPhysicalDevices)
839 {
840 RADV_FROM_HANDLE(radv_instance, instance, _instance);
841 VkResult result;
842
843 if (instance->physicalDeviceCount < 0) {
844 result = radv_enumerate_devices(instance);
845 if (result != VK_SUCCESS &&
846 result != VK_ERROR_INCOMPATIBLE_DRIVER)
847 return result;
848 }
849
850 if (!pPhysicalDevices) {
851 *pPhysicalDeviceCount = instance->physicalDeviceCount;
852 } else {
853 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
854 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
855 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
856 }
857
858 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
859 : VK_SUCCESS;
860 }
861
862 VkResult radv_EnumeratePhysicalDeviceGroups(
863 VkInstance _instance,
864 uint32_t* pPhysicalDeviceGroupCount,
865 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
866 {
867 RADV_FROM_HANDLE(radv_instance, instance, _instance);
868 VkResult result;
869
870 if (instance->physicalDeviceCount < 0) {
871 result = radv_enumerate_devices(instance);
872 if (result != VK_SUCCESS &&
873 result != VK_ERROR_INCOMPATIBLE_DRIVER)
874 return result;
875 }
876
877 if (!pPhysicalDeviceGroupProperties) {
878 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
879 } else {
880 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
881 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
882 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
883 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
884 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
885 }
886 }
887 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
888 : VK_SUCCESS;
889 }
890
891 void radv_GetPhysicalDeviceFeatures(
892 VkPhysicalDevice physicalDevice,
893 VkPhysicalDeviceFeatures* pFeatures)
894 {
895 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
896 memset(pFeatures, 0, sizeof(*pFeatures));
897
898 *pFeatures = (VkPhysicalDeviceFeatures) {
899 .robustBufferAccess = true,
900 .fullDrawIndexUint32 = true,
901 .imageCubeArray = true,
902 .independentBlend = true,
903 .geometryShader = true,
904 .tessellationShader = true,
905 .sampleRateShading = true,
906 .dualSrcBlend = true,
907 .logicOp = true,
908 .multiDrawIndirect = true,
909 .drawIndirectFirstInstance = true,
910 .depthClamp = true,
911 .depthBiasClamp = true,
912 .fillModeNonSolid = true,
913 .depthBounds = true,
914 .wideLines = true,
915 .largePoints = true,
916 .alphaToOne = true,
917 .multiViewport = true,
918 .samplerAnisotropy = true,
919 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
920 .textureCompressionASTC_LDR = false,
921 .textureCompressionBC = true,
922 .occlusionQueryPrecise = true,
923 .pipelineStatisticsQuery = true,
924 .vertexPipelineStoresAndAtomics = true,
925 .fragmentStoresAndAtomics = true,
926 .shaderTessellationAndGeometryPointSize = true,
927 .shaderImageGatherExtended = true,
928 .shaderStorageImageExtendedFormats = true,
929 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
930 .shaderUniformBufferArrayDynamicIndexing = true,
931 .shaderSampledImageArrayDynamicIndexing = true,
932 .shaderStorageBufferArrayDynamicIndexing = true,
933 .shaderStorageImageArrayDynamicIndexing = true,
934 .shaderStorageImageReadWithoutFormat = true,
935 .shaderStorageImageWriteWithoutFormat = true,
936 .shaderClipDistance = true,
937 .shaderCullDistance = true,
938 .shaderFloat64 = true,
939 .shaderInt64 = true,
940 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9 && !pdevice->use_aco,
941 .sparseBinding = true,
942 .variableMultisampleRate = true,
943 .inheritedQueries = true,
944 };
945 }
946
947 void radv_GetPhysicalDeviceFeatures2(
948 VkPhysicalDevice physicalDevice,
949 VkPhysicalDeviceFeatures2 *pFeatures)
950 {
951 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
952 vk_foreach_struct(ext, pFeatures->pNext) {
953 switch (ext->sType) {
954 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
955 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
956 features->variablePointersStorageBuffer = true;
957 features->variablePointers = true;
958 break;
959 }
960 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
961 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
962 features->multiview = true;
963 features->multiviewGeometryShader = true;
964 features->multiviewTessellationShader = true;
965 break;
966 }
967 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
968 VkPhysicalDeviceShaderDrawParametersFeatures *features =
969 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
970 features->shaderDrawParameters = true;
971 break;
972 }
973 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
974 VkPhysicalDeviceProtectedMemoryFeatures *features =
975 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
976 features->protectedMemory = false;
977 break;
978 }
979 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
980 VkPhysicalDevice16BitStorageFeatures *features =
981 (VkPhysicalDevice16BitStorageFeatures*)ext;
982 bool enabled = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
983 features->storageBuffer16BitAccess = enabled;
984 features->uniformAndStorageBuffer16BitAccess = enabled;
985 features->storagePushConstant16 = enabled;
986 features->storageInputOutput16 = enabled && LLVM_VERSION_MAJOR >= 9;
987 break;
988 }
989 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
990 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
991 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
992 features->samplerYcbcrConversion = true;
993 break;
994 }
995 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
996 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
997 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
998 features->shaderInputAttachmentArrayDynamicIndexing = true;
999 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
1000 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
1001 features->shaderUniformBufferArrayNonUniformIndexing = true;
1002 features->shaderSampledImageArrayNonUniformIndexing = true;
1003 features->shaderStorageBufferArrayNonUniformIndexing = true;
1004 features->shaderStorageImageArrayNonUniformIndexing = true;
1005 features->shaderInputAttachmentArrayNonUniformIndexing = true;
1006 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
1007 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
1008 features->descriptorBindingUniformBufferUpdateAfterBind = true;
1009 features->descriptorBindingSampledImageUpdateAfterBind = true;
1010 features->descriptorBindingStorageImageUpdateAfterBind = true;
1011 features->descriptorBindingStorageBufferUpdateAfterBind = true;
1012 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
1013 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
1014 features->descriptorBindingUpdateUnusedWhilePending = true;
1015 features->descriptorBindingPartiallyBound = true;
1016 features->descriptorBindingVariableDescriptorCount = true;
1017 features->runtimeDescriptorArray = true;
1018 break;
1019 }
1020 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
1021 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
1022 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
1023 features->conditionalRendering = true;
1024 features->inheritedConditionalRendering = false;
1025 break;
1026 }
1027 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
1028 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
1029 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
1030 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
1031 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
1032 break;
1033 }
1034 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
1035 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
1036 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
1037 features->transformFeedback = true;
1038 features->geometryStreams = !pdevice->use_ngg_streamout;
1039 break;
1040 }
1041 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
1042 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
1043 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
1044 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
1045 break;
1046 }
1047 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
1048 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
1049 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
1050 features->memoryPriority = VK_TRUE;
1051 break;
1052 }
1053 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
1054 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
1055 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
1056 features->bufferDeviceAddress = true;
1057 features->bufferDeviceAddressCaptureReplay = false;
1058 features->bufferDeviceAddressMultiDevice = false;
1059 break;
1060 }
1061 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
1062 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
1063 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
1064 features->depthClipEnable = true;
1065 break;
1066 }
1067 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
1068 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
1069 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
1070 features->hostQueryReset = true;
1071 break;
1072 }
1073 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
1074 VkPhysicalDevice8BitStorageFeaturesKHR *features =
1075 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
1076 bool enabled = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
1077 features->storageBuffer8BitAccess = enabled;
1078 features->uniformAndStorageBuffer8BitAccess = enabled;
1079 features->storagePushConstant8 = enabled;
1080 break;
1081 }
1082 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES_KHR: {
1083 VkPhysicalDeviceShaderFloat16Int8FeaturesKHR *features =
1084 (VkPhysicalDeviceShaderFloat16Int8FeaturesKHR*)ext;
1085 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
1086 features->shaderInt8 = !pdevice->use_aco;
1087 break;
1088 }
1089 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
1090 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
1091 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
1092 features->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1093 features->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1094 break;
1095 }
1096 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
1097 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
1098 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
1099 features->shaderDemoteToHelperInvocation = pdevice->use_aco;
1100 break;
1101 }
1102 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
1103 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
1104 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
1105
1106 features->inlineUniformBlock = true;
1107 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1108 break;
1109 }
1110 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1111 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1112 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1113 features->computeDerivativeGroupQuads = false;
1114 features->computeDerivativeGroupLinear = true;
1115 break;
1116 }
1117 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1118 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1119 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1120 features->ycbcrImageArrays = true;
1121 break;
1122 }
1123 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
1124 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
1125 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
1126 features->uniformBufferStandardLayout = true;
1127 break;
1128 }
1129 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1130 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1131 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1132 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1133 break;
1134 }
1135 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES_KHR: {
1136 VkPhysicalDeviceImagelessFramebufferFeaturesKHR *features =
1137 (VkPhysicalDeviceImagelessFramebufferFeaturesKHR *)ext;
1138 features->imagelessFramebuffer = true;
1139 break;
1140 }
1141 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1142 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1143 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1144 features->pipelineExecutableInfo = true;
1145 break;
1146 }
1147 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR: {
1148 VkPhysicalDeviceShaderClockFeaturesKHR *features =
1149 (VkPhysicalDeviceShaderClockFeaturesKHR *)ext;
1150 features->shaderSubgroupClock = true;
1151 features->shaderDeviceClock = false;
1152 break;
1153 }
1154 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
1155 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
1156 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
1157 features->texelBufferAlignment = true;
1158 break;
1159 }
1160 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES_KHR: {
1161 VkPhysicalDeviceTimelineSemaphoreFeaturesKHR *features =
1162 (VkPhysicalDeviceTimelineSemaphoreFeaturesKHR *) ext;
1163 features->timelineSemaphore = true;
1164 break;
1165 }
1166 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT: {
1167 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *features =
1168 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *)ext;
1169 features->subgroupSizeControl = true;
1170 features->computeFullSubgroups = true;
1171 break;
1172 }
1173 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD: {
1174 VkPhysicalDeviceCoherentMemoryFeaturesAMD *features =
1175 (VkPhysicalDeviceCoherentMemoryFeaturesAMD *)ext;
1176 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1177 break;
1178 }
1179 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES_KHR: {
1180 VkPhysicalDeviceShaderSubgroupExtendedTypesFeaturesKHR *features =
1181 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeaturesKHR *)ext;
1182 features->shaderSubgroupExtendedTypes = true;
1183 break;
1184 }
1185 default:
1186 break;
1187 }
1188 }
1189 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1190 }
1191
1192 void radv_GetPhysicalDeviceProperties(
1193 VkPhysicalDevice physicalDevice,
1194 VkPhysicalDeviceProperties* pProperties)
1195 {
1196 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1197 VkSampleCountFlags sample_counts = 0xf;
1198
1199 /* make sure that the entire descriptor set is addressable with a signed
1200 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1201 * be at most 2 GiB. the combined image & samples object count as one of
1202 * both. This limit is for the pipeline layout, not for the set layout, but
1203 * there is no set limit, so we just set a pipeline limit. I don't think
1204 * any app is going to hit this soon. */
1205 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1206 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1207 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1208 32 /* sampler, largest when combined with image */ +
1209 64 /* sampled image */ +
1210 64 /* storage image */);
1211
1212 VkPhysicalDeviceLimits limits = {
1213 .maxImageDimension1D = (1 << 14),
1214 .maxImageDimension2D = (1 << 14),
1215 .maxImageDimension3D = (1 << 11),
1216 .maxImageDimensionCube = (1 << 14),
1217 .maxImageArrayLayers = (1 << 11),
1218 .maxTexelBufferElements = 128 * 1024 * 1024,
1219 .maxUniformBufferRange = UINT32_MAX,
1220 .maxStorageBufferRange = UINT32_MAX,
1221 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1222 .maxMemoryAllocationCount = UINT32_MAX,
1223 .maxSamplerAllocationCount = 64 * 1024,
1224 .bufferImageGranularity = 64, /* A cache line */
1225 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1226 .maxBoundDescriptorSets = MAX_SETS,
1227 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1228 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1229 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1230 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1231 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1232 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1233 .maxPerStageResources = max_descriptor_set_size,
1234 .maxDescriptorSetSamplers = max_descriptor_set_size,
1235 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1236 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1237 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1238 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1239 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1240 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1241 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1242 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1243 .maxVertexInputBindings = MAX_VBS,
1244 .maxVertexInputAttributeOffset = 2047,
1245 .maxVertexInputBindingStride = 2048,
1246 .maxVertexOutputComponents = 128,
1247 .maxTessellationGenerationLevel = 64,
1248 .maxTessellationPatchSize = 32,
1249 .maxTessellationControlPerVertexInputComponents = 128,
1250 .maxTessellationControlPerVertexOutputComponents = 128,
1251 .maxTessellationControlPerPatchOutputComponents = 120,
1252 .maxTessellationControlTotalOutputComponents = 4096,
1253 .maxTessellationEvaluationInputComponents = 128,
1254 .maxTessellationEvaluationOutputComponents = 128,
1255 .maxGeometryShaderInvocations = 127,
1256 .maxGeometryInputComponents = 64,
1257 .maxGeometryOutputComponents = 128,
1258 .maxGeometryOutputVertices = 256,
1259 .maxGeometryTotalOutputComponents = 1024,
1260 .maxFragmentInputComponents = 128,
1261 .maxFragmentOutputAttachments = 8,
1262 .maxFragmentDualSrcAttachments = 1,
1263 .maxFragmentCombinedOutputResources = 8,
1264 .maxComputeSharedMemorySize = 32768,
1265 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1266 .maxComputeWorkGroupInvocations = 2048,
1267 .maxComputeWorkGroupSize = {
1268 2048,
1269 2048,
1270 2048
1271 },
1272 .subPixelPrecisionBits = 8,
1273 .subTexelPrecisionBits = 8,
1274 .mipmapPrecisionBits = 8,
1275 .maxDrawIndexedIndexValue = UINT32_MAX,
1276 .maxDrawIndirectCount = UINT32_MAX,
1277 .maxSamplerLodBias = 16,
1278 .maxSamplerAnisotropy = 16,
1279 .maxViewports = MAX_VIEWPORTS,
1280 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1281 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1282 .viewportSubPixelBits = 8,
1283 .minMemoryMapAlignment = 4096, /* A page */
1284 .minTexelBufferOffsetAlignment = 4,
1285 .minUniformBufferOffsetAlignment = 4,
1286 .minStorageBufferOffsetAlignment = 4,
1287 .minTexelOffset = -32,
1288 .maxTexelOffset = 31,
1289 .minTexelGatherOffset = -32,
1290 .maxTexelGatherOffset = 31,
1291 .minInterpolationOffset = -2,
1292 .maxInterpolationOffset = 2,
1293 .subPixelInterpolationOffsetBits = 8,
1294 .maxFramebufferWidth = (1 << 14),
1295 .maxFramebufferHeight = (1 << 14),
1296 .maxFramebufferLayers = (1 << 10),
1297 .framebufferColorSampleCounts = sample_counts,
1298 .framebufferDepthSampleCounts = sample_counts,
1299 .framebufferStencilSampleCounts = sample_counts,
1300 .framebufferNoAttachmentsSampleCounts = sample_counts,
1301 .maxColorAttachments = MAX_RTS,
1302 .sampledImageColorSampleCounts = sample_counts,
1303 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1304 .sampledImageDepthSampleCounts = sample_counts,
1305 .sampledImageStencilSampleCounts = sample_counts,
1306 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1307 .maxSampleMaskWords = 1,
1308 .timestampComputeAndGraphics = true,
1309 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1310 .maxClipDistances = 8,
1311 .maxCullDistances = 8,
1312 .maxCombinedClipAndCullDistances = 8,
1313 .discreteQueuePriorities = 2,
1314 .pointSizeRange = { 0.0, 8192.0 },
1315 .lineWidthRange = { 0.0, 7.9921875 },
1316 .pointSizeGranularity = (1.0 / 8.0),
1317 .lineWidthGranularity = (1.0 / 128.0),
1318 .strictLines = false, /* FINISHME */
1319 .standardSampleLocations = true,
1320 .optimalBufferCopyOffsetAlignment = 128,
1321 .optimalBufferCopyRowPitchAlignment = 128,
1322 .nonCoherentAtomSize = 64,
1323 };
1324
1325 *pProperties = (VkPhysicalDeviceProperties) {
1326 .apiVersion = radv_physical_device_api_version(pdevice),
1327 .driverVersion = vk_get_driver_version(),
1328 .vendorID = ATI_VENDOR_ID,
1329 .deviceID = pdevice->rad_info.pci_id,
1330 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1331 .limits = limits,
1332 .sparseProperties = {0},
1333 };
1334
1335 strcpy(pProperties->deviceName, pdevice->name);
1336 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1337 }
1338
1339 void radv_GetPhysicalDeviceProperties2(
1340 VkPhysicalDevice physicalDevice,
1341 VkPhysicalDeviceProperties2 *pProperties)
1342 {
1343 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1344 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1345
1346 vk_foreach_struct(ext, pProperties->pNext) {
1347 switch (ext->sType) {
1348 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1349 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1350 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1351 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1352 break;
1353 }
1354 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1355 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1356 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1357 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1358 properties->deviceLUIDValid = false;
1359 break;
1360 }
1361 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1362 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1363 properties->maxMultiviewViewCount = MAX_VIEWS;
1364 properties->maxMultiviewInstanceIndex = INT_MAX;
1365 break;
1366 }
1367 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1368 VkPhysicalDevicePointClippingProperties *properties =
1369 (VkPhysicalDevicePointClippingProperties*)ext;
1370 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1371 break;
1372 }
1373 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1374 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1375 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1376 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1377 break;
1378 }
1379 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1380 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1381 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1382 properties->minImportedHostPointerAlignment = 4096;
1383 break;
1384 }
1385 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1386 VkPhysicalDeviceSubgroupProperties *properties =
1387 (VkPhysicalDeviceSubgroupProperties*)ext;
1388 properties->subgroupSize = 64;
1389 properties->supportedStages = VK_SHADER_STAGE_ALL;
1390 properties->supportedOperations =
1391 VK_SUBGROUP_FEATURE_BASIC_BIT |
1392 VK_SUBGROUP_FEATURE_VOTE_BIT |
1393 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1394 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1395 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1396 VK_SUBGROUP_FEATURE_QUAD_BIT;
1397 if (pdevice->rad_info.chip_class == GFX8 ||
1398 pdevice->rad_info.chip_class == GFX9) {
1399 properties->supportedOperations |=
1400 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1401 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1402 }
1403 properties->quadOperationsInAllStages = true;
1404 break;
1405 }
1406 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1407 VkPhysicalDeviceMaintenance3Properties *properties =
1408 (VkPhysicalDeviceMaintenance3Properties*)ext;
1409 /* Make sure everything is addressable by a signed 32-bit int, and
1410 * our largest descriptors are 96 bytes. */
1411 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1412 /* Our buffer size fields allow only this much */
1413 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1414 break;
1415 }
1416 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1417 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1418 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1419 /* GFX6-8 only support single channel min/max filter. */
1420 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1421 properties->filterMinmaxSingleComponentFormats = true;
1422 break;
1423 }
1424 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1425 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1426 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1427
1428 /* Shader engines. */
1429 properties->shaderEngineCount =
1430 pdevice->rad_info.max_se;
1431 properties->shaderArraysPerEngineCount =
1432 pdevice->rad_info.max_sh_per_se;
1433 properties->computeUnitsPerShaderArray =
1434 pdevice->rad_info.num_good_cu_per_sh;
1435 properties->simdPerComputeUnit = 4;
1436 properties->wavefrontsPerSimd =
1437 pdevice->rad_info.family == CHIP_TONGA ||
1438 pdevice->rad_info.family == CHIP_ICELAND ||
1439 pdevice->rad_info.family == CHIP_POLARIS10 ||
1440 pdevice->rad_info.family == CHIP_POLARIS11 ||
1441 pdevice->rad_info.family == CHIP_POLARIS12 ||
1442 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1443 properties->wavefrontSize = 64;
1444
1445 /* SGPR. */
1446 properties->sgprsPerSimd =
1447 pdevice->rad_info.num_physical_sgprs_per_simd;
1448 properties->minSgprAllocation =
1449 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1450 properties->maxSgprAllocation =
1451 pdevice->rad_info.family == CHIP_TONGA ||
1452 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1453 properties->sgprAllocationGranularity =
1454 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1455
1456 /* VGPR. */
1457 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1458 properties->minVgprAllocation = 4;
1459 properties->maxVgprAllocation = 256;
1460 properties->vgprAllocationGranularity = 4;
1461 break;
1462 }
1463 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1464 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1465 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1466
1467 properties->shaderCoreFeatures = 0;
1468 properties->activeComputeUnitCount =
1469 pdevice->rad_info.num_good_compute_units;
1470 break;
1471 }
1472 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1473 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1474 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1475 properties->maxVertexAttribDivisor = UINT32_MAX;
1476 break;
1477 }
1478 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1479 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1480 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1481 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1482 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1483 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1484 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1485 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1486 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1487 properties->robustBufferAccessUpdateAfterBind = false;
1488 properties->quadDivergentImplicitLod = false;
1489
1490 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1491 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1492 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1493 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1494 32 /* sampler, largest when combined with image */ +
1495 64 /* sampled image */ +
1496 64 /* storage image */);
1497 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1498 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1499 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1500 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1501 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1502 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1503 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1504 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1505 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1506 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1507 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1508 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1509 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1510 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1511 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1512 break;
1513 }
1514 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1515 VkPhysicalDeviceProtectedMemoryProperties *properties =
1516 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1517 properties->protectedNoFault = false;
1518 break;
1519 }
1520 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1521 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1522 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1523 properties->primitiveOverestimationSize = 0;
1524 properties->maxExtraPrimitiveOverestimationSize = 0;
1525 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1526 properties->primitiveUnderestimation = VK_FALSE;
1527 properties->conservativePointAndLineRasterization = VK_FALSE;
1528 properties->degenerateTrianglesRasterized = VK_FALSE;
1529 properties->degenerateLinesRasterized = VK_FALSE;
1530 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1531 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1532 break;
1533 }
1534 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1535 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1536 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1537 properties->pciDomain = pdevice->bus_info.domain;
1538 properties->pciBus = pdevice->bus_info.bus;
1539 properties->pciDevice = pdevice->bus_info.dev;
1540 properties->pciFunction = pdevice->bus_info.func;
1541 break;
1542 }
1543 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1544 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1545 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1546
1547 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1548 snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE_KHR, "radv");
1549 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1550 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1551 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1552
1553 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1554 .major = 1,
1555 .minor = 1,
1556 .subminor = 2,
1557 .patch = 0,
1558 };
1559 break;
1560 }
1561 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1562 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1563 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1564 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1565 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1566 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1567 properties->maxTransformFeedbackStreamDataSize = 512;
1568 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1569 properties->maxTransformFeedbackBufferDataStride = 512;
1570 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1571 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1572 properties->transformFeedbackRasterizationStreamSelect = false;
1573 properties->transformFeedbackDraw = true;
1574 break;
1575 }
1576 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1577 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1578 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1579
1580 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1581 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1582 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1583 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1584 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1585 break;
1586 }
1587 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1588 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1589 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1590 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1591 VK_SAMPLE_COUNT_4_BIT |
1592 VK_SAMPLE_COUNT_8_BIT;
1593 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1594 properties->sampleLocationCoordinateRange[0] = 0.0f;
1595 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1596 properties->sampleLocationSubPixelBits = 4;
1597 properties->variableSampleLocations = VK_FALSE;
1598 break;
1599 }
1600 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1601 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1602 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1603
1604 /* We support all of the depth resolve modes */
1605 properties->supportedDepthResolveModes =
1606 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1607 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1608 VK_RESOLVE_MODE_MIN_BIT_KHR |
1609 VK_RESOLVE_MODE_MAX_BIT_KHR;
1610
1611 /* Average doesn't make sense for stencil so we don't support that */
1612 properties->supportedStencilResolveModes =
1613 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1614 VK_RESOLVE_MODE_MIN_BIT_KHR |
1615 VK_RESOLVE_MODE_MAX_BIT_KHR;
1616
1617 properties->independentResolveNone = VK_TRUE;
1618 properties->independentResolve = VK_TRUE;
1619 break;
1620 }
1621 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
1622 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *properties =
1623 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *)ext;
1624 properties->storageTexelBufferOffsetAlignmentBytes = 4;
1625 properties->storageTexelBufferOffsetSingleTexelAlignment = true;
1626 properties->uniformTexelBufferOffsetAlignmentBytes = 4;
1627 properties->uniformTexelBufferOffsetSingleTexelAlignment = true;
1628 break;
1629 }
1630 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES_KHR : {
1631 VkPhysicalDeviceFloatControlsPropertiesKHR *properties =
1632 (VkPhysicalDeviceFloatControlsPropertiesKHR *)ext;
1633
1634 /* On AMD hardware, denormals and rounding modes for
1635 * fp16/fp64 are controlled by the same config
1636 * register.
1637 */
1638 properties->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1639 properties->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1640
1641 /* Do not allow both preserving and flushing denorms
1642 * because different shaders in the same pipeline can
1643 * have different settings and this won't work for
1644 * merged shaders. To make it work, this requires LLVM
1645 * support for changing the register. The same logic
1646 * applies for the rounding modes because they are
1647 * configured with the same config register.
1648 * TODO: we can enable a lot of these for ACO when it
1649 * supports all stages
1650 */
1651 properties->shaderDenormFlushToZeroFloat32 = true;
1652 properties->shaderDenormPreserveFloat32 = false;
1653 properties->shaderRoundingModeRTEFloat32 = true;
1654 properties->shaderRoundingModeRTZFloat32 = false;
1655 properties->shaderSignedZeroInfNanPreserveFloat32 = true;
1656
1657 properties->shaderDenormFlushToZeroFloat16 = false;
1658 properties->shaderDenormPreserveFloat16 = pdevice->rad_info.chip_class >= GFX8;
1659 properties->shaderRoundingModeRTEFloat16 = pdevice->rad_info.chip_class >= GFX8;
1660 properties->shaderRoundingModeRTZFloat16 = false;
1661 properties->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.chip_class >= GFX8;
1662
1663 properties->shaderDenormFlushToZeroFloat64 = false;
1664 properties->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1665 properties->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
1666 properties->shaderRoundingModeRTZFloat64 = false;
1667 properties->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1668 break;
1669 }
1670 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES_KHR: {
1671 VkPhysicalDeviceTimelineSemaphorePropertiesKHR *props =
1672 (VkPhysicalDeviceTimelineSemaphorePropertiesKHR *) ext;
1673 props->maxTimelineSemaphoreValueDifference = UINT64_MAX;
1674 break;
1675 }
1676 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT: {
1677 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *props =
1678 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *)ext;
1679 props->minSubgroupSize = 64;
1680 props->maxSubgroupSize = 64;
1681 props->maxComputeWorkgroupSubgroups = UINT32_MAX;
1682 props->requiredSubgroupSizeStages = 0;
1683
1684 if (pdevice->rad_info.chip_class >= GFX10) {
1685 /* Only GFX10+ supports wave32. */
1686 props->minSubgroupSize = 32;
1687 props->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT;
1688 }
1689 break;
1690 }
1691 default:
1692 break;
1693 }
1694 }
1695 }
1696
1697 static void radv_get_physical_device_queue_family_properties(
1698 struct radv_physical_device* pdevice,
1699 uint32_t* pCount,
1700 VkQueueFamilyProperties** pQueueFamilyProperties)
1701 {
1702 int num_queue_families = 1;
1703 int idx;
1704 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
1705 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1706 num_queue_families++;
1707
1708 if (pQueueFamilyProperties == NULL) {
1709 *pCount = num_queue_families;
1710 return;
1711 }
1712
1713 if (!*pCount)
1714 return;
1715
1716 idx = 0;
1717 if (*pCount >= 1) {
1718 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1719 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1720 VK_QUEUE_COMPUTE_BIT |
1721 VK_QUEUE_TRANSFER_BIT |
1722 VK_QUEUE_SPARSE_BINDING_BIT,
1723 .queueCount = 1,
1724 .timestampValidBits = 64,
1725 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1726 };
1727 idx++;
1728 }
1729
1730 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
1731 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1732 if (*pCount > idx) {
1733 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1734 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1735 VK_QUEUE_TRANSFER_BIT |
1736 VK_QUEUE_SPARSE_BINDING_BIT,
1737 .queueCount = pdevice->rad_info.num_rings[RING_COMPUTE],
1738 .timestampValidBits = 64,
1739 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1740 };
1741 idx++;
1742 }
1743 }
1744 *pCount = idx;
1745 }
1746
1747 void radv_GetPhysicalDeviceQueueFamilyProperties(
1748 VkPhysicalDevice physicalDevice,
1749 uint32_t* pCount,
1750 VkQueueFamilyProperties* pQueueFamilyProperties)
1751 {
1752 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1753 if (!pQueueFamilyProperties) {
1754 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1755 return;
1756 }
1757 VkQueueFamilyProperties *properties[] = {
1758 pQueueFamilyProperties + 0,
1759 pQueueFamilyProperties + 1,
1760 pQueueFamilyProperties + 2,
1761 };
1762 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1763 assert(*pCount <= 3);
1764 }
1765
1766 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1767 VkPhysicalDevice physicalDevice,
1768 uint32_t* pCount,
1769 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1770 {
1771 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1772 if (!pQueueFamilyProperties) {
1773 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1774 return;
1775 }
1776 VkQueueFamilyProperties *properties[] = {
1777 &pQueueFamilyProperties[0].queueFamilyProperties,
1778 &pQueueFamilyProperties[1].queueFamilyProperties,
1779 &pQueueFamilyProperties[2].queueFamilyProperties,
1780 };
1781 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1782 assert(*pCount <= 3);
1783 }
1784
1785 void radv_GetPhysicalDeviceMemoryProperties(
1786 VkPhysicalDevice physicalDevice,
1787 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1788 {
1789 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1790
1791 *pMemoryProperties = physical_device->memory_properties;
1792 }
1793
1794 static void
1795 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1796 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1797 {
1798 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1799 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1800 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1801 uint64_t vram_size = radv_get_vram_size(device);
1802 uint64_t gtt_size = device->rad_info.gart_size;
1803 uint64_t heap_budget, heap_usage;
1804
1805 /* For all memory heaps, the computation of budget is as follow:
1806 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1807 *
1808 * The Vulkan spec 1.1.97 says that the budget should include any
1809 * currently allocated device memory.
1810 *
1811 * Note that the application heap usages are not really accurate (eg.
1812 * in presence of shared buffers).
1813 */
1814 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1815 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1816
1817 if (radv_is_mem_type_vram(device->mem_type_indices[i])) {
1818 heap_usage = device->ws->query_value(device->ws,
1819 RADEON_ALLOCATED_VRAM);
1820
1821 heap_budget = vram_size -
1822 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1823 heap_usage;
1824
1825 memoryBudget->heapBudget[heap_index] = heap_budget;
1826 memoryBudget->heapUsage[heap_index] = heap_usage;
1827 } else if (radv_is_mem_type_vram_visible(device->mem_type_indices[i])) {
1828 heap_usage = device->ws->query_value(device->ws,
1829 RADEON_ALLOCATED_VRAM_VIS);
1830
1831 heap_budget = visible_vram_size -
1832 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1833 heap_usage;
1834
1835 memoryBudget->heapBudget[heap_index] = heap_budget;
1836 memoryBudget->heapUsage[heap_index] = heap_usage;
1837 } else if (radv_is_mem_type_gtt_wc(device->mem_type_indices[i])) {
1838 heap_usage = device->ws->query_value(device->ws,
1839 RADEON_ALLOCATED_GTT);
1840
1841 heap_budget = gtt_size -
1842 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1843 heap_usage;
1844
1845 memoryBudget->heapBudget[heap_index] = heap_budget;
1846 memoryBudget->heapUsage[heap_index] = heap_usage;
1847 }
1848 }
1849
1850 /* The heapBudget and heapUsage values must be zero for array elements
1851 * greater than or equal to
1852 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1853 */
1854 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1855 memoryBudget->heapBudget[i] = 0;
1856 memoryBudget->heapUsage[i] = 0;
1857 }
1858 }
1859
1860 void radv_GetPhysicalDeviceMemoryProperties2(
1861 VkPhysicalDevice physicalDevice,
1862 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1863 {
1864 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1865 &pMemoryProperties->memoryProperties);
1866
1867 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1868 vk_find_struct(pMemoryProperties->pNext,
1869 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1870 if (memory_budget)
1871 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1872 }
1873
1874 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1875 VkDevice _device,
1876 VkExternalMemoryHandleTypeFlagBits handleType,
1877 const void *pHostPointer,
1878 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1879 {
1880 RADV_FROM_HANDLE(radv_device, device, _device);
1881
1882 switch (handleType)
1883 {
1884 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1885 const struct radv_physical_device *physical_device = device->physical_device;
1886 uint32_t memoryTypeBits = 0;
1887 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1888 if (radv_is_mem_type_gtt_cached(physical_device->mem_type_indices[i])) {
1889 memoryTypeBits = (1 << i);
1890 break;
1891 }
1892 }
1893 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1894 return VK_SUCCESS;
1895 }
1896 default:
1897 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1898 }
1899 }
1900
1901 static enum radeon_ctx_priority
1902 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1903 {
1904 /* Default to MEDIUM when a specific global priority isn't requested */
1905 if (!pObj)
1906 return RADEON_CTX_PRIORITY_MEDIUM;
1907
1908 switch(pObj->globalPriority) {
1909 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1910 return RADEON_CTX_PRIORITY_REALTIME;
1911 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1912 return RADEON_CTX_PRIORITY_HIGH;
1913 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1914 return RADEON_CTX_PRIORITY_MEDIUM;
1915 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1916 return RADEON_CTX_PRIORITY_LOW;
1917 default:
1918 unreachable("Illegal global priority value");
1919 return RADEON_CTX_PRIORITY_INVALID;
1920 }
1921 }
1922
1923 static int
1924 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1925 uint32_t queue_family_index, int idx,
1926 VkDeviceQueueCreateFlags flags,
1927 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1928 {
1929 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1930 queue->device = device;
1931 queue->queue_family_index = queue_family_index;
1932 queue->queue_idx = idx;
1933 queue->priority = radv_get_queue_global_priority(global_priority);
1934 queue->flags = flags;
1935
1936 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1937 if (!queue->hw_ctx)
1938 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1939
1940 list_inithead(&queue->pending_submissions);
1941 pthread_mutex_init(&queue->pending_mutex, NULL);
1942
1943 return VK_SUCCESS;
1944 }
1945
1946 static void
1947 radv_queue_finish(struct radv_queue *queue)
1948 {
1949 pthread_mutex_destroy(&queue->pending_mutex);
1950
1951 if (queue->hw_ctx)
1952 queue->device->ws->ctx_destroy(queue->hw_ctx);
1953
1954 if (queue->initial_full_flush_preamble_cs)
1955 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1956 if (queue->initial_preamble_cs)
1957 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1958 if (queue->continue_preamble_cs)
1959 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1960 if (queue->descriptor_bo)
1961 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1962 if (queue->scratch_bo)
1963 queue->device->ws->buffer_destroy(queue->scratch_bo);
1964 if (queue->esgs_ring_bo)
1965 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1966 if (queue->gsvs_ring_bo)
1967 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1968 if (queue->tess_rings_bo)
1969 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1970 if (queue->gds_bo)
1971 queue->device->ws->buffer_destroy(queue->gds_bo);
1972 if (queue->gds_oa_bo)
1973 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
1974 if (queue->compute_scratch_bo)
1975 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1976 }
1977
1978 static void
1979 radv_bo_list_init(struct radv_bo_list *bo_list)
1980 {
1981 pthread_mutex_init(&bo_list->mutex, NULL);
1982 bo_list->list.count = bo_list->capacity = 0;
1983 bo_list->list.bos = NULL;
1984 }
1985
1986 static void
1987 radv_bo_list_finish(struct radv_bo_list *bo_list)
1988 {
1989 free(bo_list->list.bos);
1990 pthread_mutex_destroy(&bo_list->mutex);
1991 }
1992
1993 static VkResult radv_bo_list_add(struct radv_device *device,
1994 struct radeon_winsys_bo *bo)
1995 {
1996 struct radv_bo_list *bo_list = &device->bo_list;
1997
1998 if (bo->is_local)
1999 return VK_SUCCESS;
2000
2001 if (unlikely(!device->use_global_bo_list))
2002 return VK_SUCCESS;
2003
2004 pthread_mutex_lock(&bo_list->mutex);
2005 if (bo_list->list.count == bo_list->capacity) {
2006 unsigned capacity = MAX2(4, bo_list->capacity * 2);
2007 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
2008
2009 if (!data) {
2010 pthread_mutex_unlock(&bo_list->mutex);
2011 return VK_ERROR_OUT_OF_HOST_MEMORY;
2012 }
2013
2014 bo_list->list.bos = (struct radeon_winsys_bo**)data;
2015 bo_list->capacity = capacity;
2016 }
2017
2018 bo_list->list.bos[bo_list->list.count++] = bo;
2019 pthread_mutex_unlock(&bo_list->mutex);
2020 return VK_SUCCESS;
2021 }
2022
2023 static void radv_bo_list_remove(struct radv_device *device,
2024 struct radeon_winsys_bo *bo)
2025 {
2026 struct radv_bo_list *bo_list = &device->bo_list;
2027
2028 if (bo->is_local)
2029 return;
2030
2031 if (unlikely(!device->use_global_bo_list))
2032 return;
2033
2034 pthread_mutex_lock(&bo_list->mutex);
2035 for(unsigned i = 0; i < bo_list->list.count; ++i) {
2036 if (bo_list->list.bos[i] == bo) {
2037 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
2038 --bo_list->list.count;
2039 break;
2040 }
2041 }
2042 pthread_mutex_unlock(&bo_list->mutex);
2043 }
2044
2045 static void
2046 radv_device_init_gs_info(struct radv_device *device)
2047 {
2048 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
2049 device->physical_device->rad_info.family);
2050 }
2051
2052 static int radv_get_device_extension_index(const char *name)
2053 {
2054 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
2055 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
2056 return i;
2057 }
2058 return -1;
2059 }
2060
2061 static int
2062 radv_get_int_debug_option(const char *name, int default_value)
2063 {
2064 const char *str;
2065 int result;
2066
2067 str = getenv(name);
2068 if (!str) {
2069 result = default_value;
2070 } else {
2071 char *endptr;
2072
2073 result = strtol(str, &endptr, 0);
2074 if (str == endptr) {
2075 /* No digits founs. */
2076 result = default_value;
2077 }
2078 }
2079
2080 return result;
2081 }
2082
2083 static int install_seccomp_filter() {
2084
2085 struct sock_filter filter[] = {
2086 /* Check arch is 64bit x86 */
2087 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, arch))),
2088 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, AUDIT_ARCH_X86_64, 0, 12),
2089
2090 /* Futex is required for mutex locks */
2091 #if defined __NR__newselect
2092 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2093 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR__newselect, 11, 0),
2094 #elif defined __NR_select
2095 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2096 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_select, 11, 0),
2097 #else
2098 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2099 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_pselect6, 11, 0),
2100 #endif
2101
2102 /* Allow system exit calls for the forked process */
2103 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2104 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_exit_group, 9, 0),
2105
2106 /* Allow system read calls */
2107 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2108 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_read, 7, 0),
2109
2110 /* Allow system write calls */
2111 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2112 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_write, 5, 0),
2113
2114 /* Allow system brk calls (we need this for malloc) */
2115 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2116 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_brk, 3, 0),
2117
2118 /* Futex is required for mutex locks */
2119 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2120 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_futex, 1, 0),
2121
2122 /* Return error if we hit a system call not on the whitelist */
2123 BPF_STMT(BPF_RET + BPF_K, SECCOMP_RET_ERRNO | (EPERM & SECCOMP_RET_DATA)),
2124
2125 /* Allow whitelisted system calls */
2126 BPF_STMT(BPF_RET + BPF_K, SECCOMP_RET_ALLOW),
2127 };
2128
2129 struct sock_fprog prog = {
2130 .len = (unsigned short)(sizeof(filter) / sizeof(filter[0])),
2131 .filter = filter,
2132 };
2133
2134 if (prctl(PR_SET_NO_NEW_PRIVS, 1, 0, 0, 0))
2135 return -1;
2136
2137 if (prctl(PR_SET_SECCOMP, SECCOMP_MODE_FILTER, &prog))
2138 return -1;
2139
2140 return 0;
2141 }
2142
2143 /* Helper function with timeout support for reading from the pipe between
2144 * processes used for secure compile.
2145 */
2146 bool radv_sc_read(int fd, void *buf, size_t size, bool timeout)
2147 {
2148 fd_set fds;
2149 struct timeval tv;
2150
2151 FD_ZERO(&fds);
2152 FD_SET(fd, &fds);
2153
2154 while (true) {
2155 /* We can't rely on the value of tv after calling select() so
2156 * we must reset it on each iteration of the loop.
2157 */
2158 tv.tv_sec = 5;
2159 tv.tv_usec = 0;
2160
2161 int rval = select(fd + 1, &fds, NULL, NULL, timeout ? &tv : NULL);
2162
2163 if (rval == -1) {
2164 /* select error */
2165 return false;
2166 } else if (rval) {
2167 ssize_t bytes_read = read(fd, buf, size);
2168 if (bytes_read < 0)
2169 return false;
2170
2171 buf += bytes_read;
2172 size -= bytes_read;
2173 if (size == 0)
2174 return true;
2175 } else {
2176 /* select timeout */
2177 return false;
2178 }
2179 }
2180 }
2181
2182 static bool radv_close_all_fds(const int *keep_fds, int keep_fd_count)
2183 {
2184 DIR *d;
2185 struct dirent *dir;
2186 d = opendir("/proc/self/fd");
2187 if (!d)
2188 return false;
2189 int dir_fd = dirfd(d);
2190
2191 while ((dir = readdir(d)) != NULL) {
2192 if (dir->d_name[0] == '.')
2193 continue;
2194
2195 int fd = atoi(dir->d_name);
2196 if (fd == dir_fd)
2197 continue;
2198
2199 bool keep = false;
2200 for (int i = 0; !keep && i < keep_fd_count; ++i)
2201 if (keep_fds[i] == fd)
2202 keep = true;
2203
2204 if (keep)
2205 continue;
2206
2207 close(fd);
2208 }
2209 closedir(d);
2210 return true;
2211 }
2212
2213 static bool secure_compile_open_fifo_fds(struct radv_secure_compile_state *sc,
2214 int *fd_server, int *fd_client,
2215 unsigned process, bool make_fifo)
2216 {
2217 bool result = false;
2218 char *fifo_server_path = NULL;
2219 char *fifo_client_path = NULL;
2220
2221 if (asprintf(&fifo_server_path, "/tmp/radv_server_%s_%u", sc->uid, process) == -1)
2222 goto open_fifo_exit;
2223
2224 if (asprintf(&fifo_client_path, "/tmp/radv_client_%s_%u", sc->uid, process) == -1)
2225 goto open_fifo_exit;
2226
2227 if (make_fifo) {
2228 int file1 = mkfifo(fifo_server_path, 0666);
2229 if(file1 < 0)
2230 goto open_fifo_exit;
2231
2232 int file2 = mkfifo(fifo_client_path, 0666);
2233 if(file2 < 0)
2234 goto open_fifo_exit;
2235 }
2236
2237 *fd_server = open(fifo_server_path, O_RDWR);
2238 if(*fd_server < 1)
2239 goto open_fifo_exit;
2240
2241 *fd_client = open(fifo_client_path, O_RDWR);
2242 if(*fd_client < 1) {
2243 close(*fd_server);
2244 goto open_fifo_exit;
2245 }
2246
2247 result = true;
2248
2249 open_fifo_exit:
2250 free(fifo_server_path);
2251 free(fifo_client_path);
2252
2253 return result;
2254 }
2255
2256 static void run_secure_compile_device(struct radv_device *device, unsigned process,
2257 int fd_idle_device_output)
2258 {
2259 int fd_secure_input;
2260 int fd_secure_output;
2261 bool fifo_result = secure_compile_open_fifo_fds(device->sc_state,
2262 &fd_secure_input,
2263 &fd_secure_output,
2264 process, false);
2265
2266 enum radv_secure_compile_type sc_type;
2267
2268 const int needed_fds[] = {
2269 fd_secure_input,
2270 fd_secure_output,
2271 fd_idle_device_output,
2272 };
2273
2274 if (!fifo_result || !radv_close_all_fds(needed_fds, ARRAY_SIZE(needed_fds)) ||
2275 install_seccomp_filter() == -1) {
2276 sc_type = RADV_SC_TYPE_INIT_FAILURE;
2277 } else {
2278 sc_type = RADV_SC_TYPE_INIT_SUCCESS;
2279 device->sc_state->secure_compile_processes[process].fd_secure_input = fd_secure_input;
2280 device->sc_state->secure_compile_processes[process].fd_secure_output = fd_secure_output;
2281 }
2282
2283 write(fd_idle_device_output, &sc_type, sizeof(sc_type));
2284
2285 if (sc_type == RADV_SC_TYPE_INIT_FAILURE)
2286 goto secure_compile_exit;
2287
2288 while (true) {
2289 radv_sc_read(fd_secure_input, &sc_type, sizeof(sc_type), false);
2290
2291 if (sc_type == RADV_SC_TYPE_COMPILE_PIPELINE) {
2292 struct radv_pipeline *pipeline;
2293 bool sc_read = true;
2294
2295 pipeline = vk_zalloc2(&device->alloc, NULL, sizeof(*pipeline), 8,
2296 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2297
2298 pipeline->device = device;
2299
2300 /* Read pipeline layout */
2301 struct radv_pipeline_layout layout;
2302 sc_read = radv_sc_read(fd_secure_input, &layout, sizeof(struct radv_pipeline_layout), true);
2303 sc_read &= radv_sc_read(fd_secure_input, &layout.num_sets, sizeof(uint32_t), true);
2304 if (!sc_read)
2305 goto secure_compile_exit;
2306
2307 for (uint32_t set = 0; set < layout.num_sets; set++) {
2308 uint32_t layout_size;
2309 sc_read &= radv_sc_read(fd_secure_input, &layout_size, sizeof(uint32_t), true);
2310 if (!sc_read)
2311 goto secure_compile_exit;
2312
2313 layout.set[set].layout = malloc(layout_size);
2314 layout.set[set].layout->layout_size = layout_size;
2315 sc_read &= radv_sc_read(fd_secure_input, layout.set[set].layout,
2316 layout.set[set].layout->layout_size, true);
2317 }
2318
2319 pipeline->layout = &layout;
2320
2321 /* Read pipeline key */
2322 struct radv_pipeline_key key;
2323 sc_read &= radv_sc_read(fd_secure_input, &key, sizeof(struct radv_pipeline_key), true);
2324
2325 /* Read pipeline create flags */
2326 VkPipelineCreateFlags flags;
2327 sc_read &= radv_sc_read(fd_secure_input, &flags, sizeof(VkPipelineCreateFlags), true);
2328
2329 /* Read stage and shader information */
2330 uint32_t num_stages;
2331 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2332 sc_read &= radv_sc_read(fd_secure_input, &num_stages, sizeof(uint32_t), true);
2333 if (!sc_read)
2334 goto secure_compile_exit;
2335
2336 for (uint32_t i = 0; i < num_stages; i++) {
2337
2338 /* Read stage */
2339 gl_shader_stage stage;
2340 sc_read &= radv_sc_read(fd_secure_input, &stage, sizeof(gl_shader_stage), true);
2341
2342 VkPipelineShaderStageCreateInfo *pStage = calloc(1, sizeof(VkPipelineShaderStageCreateInfo));
2343
2344 /* Read entry point name */
2345 size_t name_size;
2346 sc_read &= radv_sc_read(fd_secure_input, &name_size, sizeof(size_t), true);
2347 if (!sc_read)
2348 goto secure_compile_exit;
2349
2350 char *ep_name = malloc(name_size);
2351 sc_read &= radv_sc_read(fd_secure_input, ep_name, name_size, true);
2352 pStage->pName = ep_name;
2353
2354 /* Read shader module */
2355 size_t module_size;
2356 sc_read &= radv_sc_read(fd_secure_input, &module_size, sizeof(size_t), true);
2357 if (!sc_read)
2358 goto secure_compile_exit;
2359
2360 struct radv_shader_module *module = malloc(module_size);
2361 sc_read &= radv_sc_read(fd_secure_input, module, module_size, true);
2362 pStage->module = radv_shader_module_to_handle(module);
2363
2364 /* Read specialization info */
2365 bool has_spec_info;
2366 sc_read &= radv_sc_read(fd_secure_input, &has_spec_info, sizeof(bool), true);
2367 if (!sc_read)
2368 goto secure_compile_exit;
2369
2370 if (has_spec_info) {
2371 VkSpecializationInfo *specInfo = malloc(sizeof(VkSpecializationInfo));
2372 pStage->pSpecializationInfo = specInfo;
2373
2374 sc_read &= radv_sc_read(fd_secure_input, &specInfo->dataSize, sizeof(size_t), true);
2375 if (!sc_read)
2376 goto secure_compile_exit;
2377
2378 void *si_data = malloc(specInfo->dataSize);
2379 sc_read &= radv_sc_read(fd_secure_input, si_data, specInfo->dataSize, true);
2380 specInfo->pData = si_data;
2381
2382 sc_read &= radv_sc_read(fd_secure_input, &specInfo->mapEntryCount, sizeof(uint32_t), true);
2383 if (!sc_read)
2384 goto secure_compile_exit;
2385
2386 VkSpecializationMapEntry *mapEntries = malloc(sizeof(VkSpecializationMapEntry) * specInfo->mapEntryCount);
2387 for (uint32_t j = 0; j < specInfo->mapEntryCount; j++) {
2388 sc_read &= radv_sc_read(fd_secure_input, &mapEntries[j], sizeof(VkSpecializationMapEntry), true);
2389 if (!sc_read)
2390 goto secure_compile_exit;
2391 }
2392
2393 specInfo->pMapEntries = mapEntries;
2394 }
2395
2396 pStages[stage] = pStage;
2397 }
2398
2399 /* Compile the shaders */
2400 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
2401 radv_create_shaders(pipeline, device, NULL, &key, pStages, flags, NULL, stage_feedbacks);
2402
2403 /* free memory allocated above */
2404 for (uint32_t set = 0; set < layout.num_sets; set++)
2405 free(layout.set[set].layout);
2406
2407 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2408 if (!pStages[i])
2409 continue;
2410
2411 free((void *) pStages[i]->pName);
2412 free(radv_shader_module_from_handle(pStages[i]->module));
2413 if (pStages[i]->pSpecializationInfo) {
2414 free((void *) pStages[i]->pSpecializationInfo->pData);
2415 free((void *) pStages[i]->pSpecializationInfo->pMapEntries);
2416 free((void *) pStages[i]->pSpecializationInfo);
2417 }
2418 free((void *) pStages[i]);
2419 }
2420
2421 vk_free(&device->alloc, pipeline);
2422
2423 sc_type = RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED;
2424 write(fd_secure_output, &sc_type, sizeof(sc_type));
2425
2426 } else if (sc_type == RADV_SC_TYPE_DESTROY_DEVICE) {
2427 goto secure_compile_exit;
2428 }
2429 }
2430
2431 secure_compile_exit:
2432 close(fd_secure_input);
2433 close(fd_secure_output);
2434 close(fd_idle_device_output);
2435 _exit(0);
2436 }
2437
2438 static enum radv_secure_compile_type fork_secure_compile_device(struct radv_device *device, unsigned process)
2439 {
2440 int fd_secure_input[2];
2441 int fd_secure_output[2];
2442
2443 /* create pipe descriptors (used to communicate between processes) */
2444 if (pipe(fd_secure_input) == -1 || pipe(fd_secure_output) == -1)
2445 return RADV_SC_TYPE_INIT_FAILURE;
2446
2447
2448 int sc_pid;
2449 if ((sc_pid = fork()) == 0) {
2450 device->sc_state->secure_compile_thread_counter = process;
2451 run_secure_compile_device(device, process, fd_secure_output[1]);
2452 } else {
2453 if (sc_pid == -1)
2454 return RADV_SC_TYPE_INIT_FAILURE;
2455
2456 /* Read the init result returned from the secure process */
2457 enum radv_secure_compile_type sc_type;
2458 bool sc_read = radv_sc_read(fd_secure_output[0], &sc_type, sizeof(sc_type), true);
2459
2460 if (sc_type == RADV_SC_TYPE_INIT_FAILURE || !sc_read) {
2461 close(fd_secure_input[0]);
2462 close(fd_secure_input[1]);
2463 close(fd_secure_output[1]);
2464 close(fd_secure_output[0]);
2465 int status;
2466 waitpid(sc_pid, &status, 0);
2467
2468 return RADV_SC_TYPE_INIT_FAILURE;
2469 } else {
2470 assert(sc_type == RADV_SC_TYPE_INIT_SUCCESS);
2471 write(device->sc_state->secure_compile_processes[process].fd_secure_output, &sc_type, sizeof(sc_type));
2472
2473 close(fd_secure_input[0]);
2474 close(fd_secure_input[1]);
2475 close(fd_secure_output[1]);
2476 close(fd_secure_output[0]);
2477
2478 int status;
2479 waitpid(sc_pid, &status, 0);
2480 }
2481 }
2482
2483 return RADV_SC_TYPE_INIT_SUCCESS;
2484 }
2485
2486 /* Run a bare bones fork of a device that was forked right after its creation.
2487 * This device will have low overhead when it is forked again before each
2488 * pipeline compilation. This device sits idle and its only job is to fork
2489 * itself.
2490 */
2491 static void run_secure_compile_idle_device(struct radv_device *device, unsigned process,
2492 int fd_secure_input, int fd_secure_output)
2493 {
2494 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_INIT_SUCCESS;
2495 device->sc_state->secure_compile_processes[process].fd_secure_input = fd_secure_input;
2496 device->sc_state->secure_compile_processes[process].fd_secure_output = fd_secure_output;
2497
2498 write(fd_secure_output, &sc_type, sizeof(sc_type));
2499
2500 while (true) {
2501 radv_sc_read(fd_secure_input, &sc_type, sizeof(sc_type), false);
2502
2503 if (sc_type == RADV_SC_TYPE_FORK_DEVICE) {
2504 sc_type = fork_secure_compile_device(device, process);
2505
2506 if (sc_type == RADV_SC_TYPE_INIT_FAILURE)
2507 goto secure_compile_exit;
2508
2509 } else if (sc_type == RADV_SC_TYPE_DESTROY_DEVICE) {
2510 goto secure_compile_exit;
2511 }
2512 }
2513
2514 secure_compile_exit:
2515 close(fd_secure_input);
2516 close(fd_secure_output);
2517 _exit(0);
2518 }
2519
2520 static void destroy_secure_compile_device(struct radv_device *device, unsigned process)
2521 {
2522 int fd_secure_input = device->sc_state->secure_compile_processes[process].fd_secure_input;
2523
2524 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_DESTROY_DEVICE;
2525 write(fd_secure_input, &sc_type, sizeof(sc_type));
2526
2527 close(device->sc_state->secure_compile_processes[process].fd_secure_input);
2528 close(device->sc_state->secure_compile_processes[process].fd_secure_output);
2529
2530 int status;
2531 waitpid(device->sc_state->secure_compile_processes[process].sc_pid, &status, 0);
2532 }
2533
2534 static VkResult fork_secure_compile_idle_device(struct radv_device *device)
2535 {
2536 device->sc_state = vk_zalloc(&device->alloc,
2537 sizeof(struct radv_secure_compile_state),
2538 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2539
2540 mtx_init(&device->sc_state->secure_compile_mutex, mtx_plain);
2541
2542 pid_t upid = getpid();
2543 time_t seconds = time(NULL);
2544
2545 char *uid;
2546 if (asprintf(&uid, "%ld_%ld", (long) upid, (long) seconds) == -1)
2547 return VK_ERROR_INITIALIZATION_FAILED;
2548
2549 device->sc_state->uid = uid;
2550
2551 uint8_t sc_threads = device->instance->num_sc_threads;
2552 int fd_secure_input[MAX_SC_PROCS][2];
2553 int fd_secure_output[MAX_SC_PROCS][2];
2554
2555 /* create pipe descriptors (used to communicate between processes) */
2556 for (unsigned i = 0; i < sc_threads; i++) {
2557 if (pipe(fd_secure_input[i]) == -1 ||
2558 pipe(fd_secure_output[i]) == -1) {
2559 return VK_ERROR_INITIALIZATION_FAILED;
2560 }
2561 }
2562
2563 device->sc_state->secure_compile_processes = vk_zalloc(&device->alloc,
2564 sizeof(struct radv_secure_compile_process) * sc_threads, 8,
2565 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2566
2567 for (unsigned process = 0; process < sc_threads; process++) {
2568 if ((device->sc_state->secure_compile_processes[process].sc_pid = fork()) == 0) {
2569 device->sc_state->secure_compile_thread_counter = process;
2570 run_secure_compile_idle_device(device, process, fd_secure_input[process][0], fd_secure_output[process][1]);
2571 } else {
2572 if (device->sc_state->secure_compile_processes[process].sc_pid == -1)
2573 return VK_ERROR_INITIALIZATION_FAILED;
2574
2575 /* Read the init result returned from the secure process */
2576 enum radv_secure_compile_type sc_type;
2577 bool sc_read = radv_sc_read(fd_secure_output[process][0], &sc_type, sizeof(sc_type), true);
2578
2579 bool fifo_result;
2580 if (sc_read && sc_type == RADV_SC_TYPE_INIT_SUCCESS) {
2581 fifo_result = secure_compile_open_fifo_fds(device->sc_state,
2582 &device->sc_state->secure_compile_processes[process].fd_server,
2583 &device->sc_state->secure_compile_processes[process].fd_client,
2584 process, true);
2585
2586 device->sc_state->secure_compile_processes[process].fd_secure_input = fd_secure_input[process][1];
2587 device->sc_state->secure_compile_processes[process].fd_secure_output = fd_secure_output[process][0];
2588 }
2589
2590 if (sc_type == RADV_SC_TYPE_INIT_FAILURE || !sc_read || !fifo_result) {
2591 close(fd_secure_input[process][0]);
2592 close(fd_secure_input[process][1]);
2593 close(fd_secure_output[process][1]);
2594 close(fd_secure_output[process][0]);
2595 int status;
2596 waitpid(device->sc_state->secure_compile_processes[process].sc_pid, &status, 0);
2597
2598 /* Destroy any forks that were created sucessfully */
2599 for (unsigned i = 0; i < process; i++) {
2600 destroy_secure_compile_device(device, i);
2601 }
2602
2603 return VK_ERROR_INITIALIZATION_FAILED;
2604 }
2605 }
2606 }
2607 return VK_SUCCESS;
2608 }
2609
2610 static VkResult
2611 radv_create_pthread_cond(pthread_cond_t *cond)
2612 {
2613 pthread_condattr_t condattr;
2614 if (pthread_condattr_init(&condattr)) {
2615 return VK_ERROR_INITIALIZATION_FAILED;
2616 }
2617
2618 if (pthread_condattr_setclock(&condattr, CLOCK_MONOTONIC)) {
2619 pthread_condattr_destroy(&condattr);
2620 return VK_ERROR_INITIALIZATION_FAILED;
2621 }
2622 if (pthread_cond_init(cond, &condattr)) {
2623 pthread_condattr_destroy(&condattr);
2624 return VK_ERROR_INITIALIZATION_FAILED;
2625 }
2626 pthread_condattr_destroy(&condattr);
2627 return VK_SUCCESS;
2628 }
2629
2630 VkResult radv_CreateDevice(
2631 VkPhysicalDevice physicalDevice,
2632 const VkDeviceCreateInfo* pCreateInfo,
2633 const VkAllocationCallbacks* pAllocator,
2634 VkDevice* pDevice)
2635 {
2636 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2637 VkResult result;
2638 struct radv_device *device;
2639
2640 bool keep_shader_info = false;
2641
2642 /* Check enabled features */
2643 if (pCreateInfo->pEnabledFeatures) {
2644 VkPhysicalDeviceFeatures supported_features;
2645 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
2646 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
2647 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
2648 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
2649 for (uint32_t i = 0; i < num_features; i++) {
2650 if (enabled_feature[i] && !supported_feature[i])
2651 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
2652 }
2653 }
2654
2655 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
2656 sizeof(*device), 8,
2657 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2658 if (!device)
2659 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2660
2661 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2662 device->instance = physical_device->instance;
2663 device->physical_device = physical_device;
2664
2665 device->ws = physical_device->ws;
2666 if (pAllocator)
2667 device->alloc = *pAllocator;
2668 else
2669 device->alloc = physical_device->instance->alloc;
2670
2671 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
2672 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
2673 int index = radv_get_device_extension_index(ext_name);
2674 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
2675 vk_free(&device->alloc, device);
2676 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
2677 }
2678
2679 device->enabled_extensions.extensions[index] = true;
2680 }
2681
2682 keep_shader_info = device->enabled_extensions.AMD_shader_info;
2683
2684 /* With update after bind we can't attach bo's to the command buffer
2685 * from the descriptor set anymore, so we have to use a global BO list.
2686 */
2687 device->use_global_bo_list =
2688 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
2689 device->enabled_extensions.EXT_descriptor_indexing ||
2690 device->enabled_extensions.EXT_buffer_device_address;
2691
2692 device->robust_buffer_access = pCreateInfo->pEnabledFeatures &&
2693 pCreateInfo->pEnabledFeatures->robustBufferAccess;
2694
2695 mtx_init(&device->shader_slab_mutex, mtx_plain);
2696 list_inithead(&device->shader_slabs);
2697
2698 radv_bo_list_init(&device->bo_list);
2699
2700 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
2701 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
2702 uint32_t qfi = queue_create->queueFamilyIndex;
2703 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
2704 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
2705
2706 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
2707
2708 device->queues[qfi] = vk_alloc(&device->alloc,
2709 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2710 if (!device->queues[qfi]) {
2711 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2712 goto fail;
2713 }
2714
2715 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
2716
2717 device->queue_count[qfi] = queue_create->queueCount;
2718
2719 for (unsigned q = 0; q < queue_create->queueCount; q++) {
2720 result = radv_queue_init(device, &device->queues[qfi][q],
2721 qfi, q, queue_create->flags,
2722 global_priority);
2723 if (result != VK_SUCCESS)
2724 goto fail;
2725 }
2726 }
2727
2728 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
2729 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
2730
2731 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2732 device->dfsm_allowed = device->pbb_allowed &&
2733 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
2734
2735 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
2736
2737 /* The maximum number of scratch waves. Scratch space isn't divided
2738 * evenly between CUs. The number is only a function of the number of CUs.
2739 * We can decrease the constant to decrease the scratch buffer size.
2740 *
2741 * sctx->scratch_waves must be >= the maximum possible size of
2742 * 1 threadgroup, so that the hw doesn't hang from being unable
2743 * to start any.
2744 *
2745 * The recommended value is 4 per CU at most. Higher numbers don't
2746 * bring much benefit, but they still occupy chip resources (think
2747 * async compute). I've seen ~2% performance difference between 4 and 32.
2748 */
2749 uint32_t max_threads_per_block = 2048;
2750 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
2751 max_threads_per_block / 64);
2752
2753 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
2754
2755 if (device->physical_device->rad_info.chip_class >= GFX7) {
2756 /* If the KMD allows it (there is a KMD hw register for it),
2757 * allow launching waves out-of-order.
2758 */
2759 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
2760 }
2761
2762 radv_device_init_gs_info(device);
2763
2764 device->tess_offchip_block_dw_size =
2765 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2766
2767 if (getenv("RADV_TRACE_FILE")) {
2768 const char *filename = getenv("RADV_TRACE_FILE");
2769
2770 keep_shader_info = true;
2771
2772 if (!radv_init_trace(device))
2773 goto fail;
2774
2775 fprintf(stderr, "*****************************************************************************\n");
2776 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2777 fprintf(stderr, "*****************************************************************************\n");
2778
2779 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2780 radv_dump_enabled_options(device, stderr);
2781 }
2782
2783 /* Temporarily disable secure compile while we create meta shaders, etc */
2784 uint8_t sc_threads = device->instance->num_sc_threads;
2785 if (sc_threads)
2786 device->instance->num_sc_threads = 0;
2787
2788 device->keep_shader_info = keep_shader_info;
2789 result = radv_device_init_meta(device);
2790 if (result != VK_SUCCESS)
2791 goto fail;
2792
2793 radv_device_init_msaa(device);
2794
2795 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2796 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2797 switch (family) {
2798 case RADV_QUEUE_GENERAL:
2799 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2800 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
2801 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
2802 break;
2803 case RADV_QUEUE_COMPUTE:
2804 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2805 radeon_emit(device->empty_cs[family], 0);
2806 break;
2807 }
2808 device->ws->cs_finalize(device->empty_cs[family]);
2809 }
2810
2811 if (device->physical_device->rad_info.chip_class >= GFX7)
2812 cik_create_gfx_config(device);
2813
2814 VkPipelineCacheCreateInfo ci;
2815 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2816 ci.pNext = NULL;
2817 ci.flags = 0;
2818 ci.pInitialData = NULL;
2819 ci.initialDataSize = 0;
2820 VkPipelineCache pc;
2821 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2822 &ci, NULL, &pc);
2823 if (result != VK_SUCCESS)
2824 goto fail_meta;
2825
2826 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2827
2828 result = radv_create_pthread_cond(&device->timeline_cond);
2829 if (result != VK_SUCCESS)
2830 goto fail_mem_cache;
2831
2832 device->force_aniso =
2833 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2834 if (device->force_aniso >= 0) {
2835 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2836 1 << util_logbase2(device->force_aniso));
2837 }
2838
2839 /* Fork device for secure compile as required */
2840 device->instance->num_sc_threads = sc_threads;
2841 if (radv_device_use_secure_compile(device->instance)) {
2842
2843 result = fork_secure_compile_idle_device(device);
2844 if (result != VK_SUCCESS)
2845 goto fail_meta;
2846 }
2847
2848 *pDevice = radv_device_to_handle(device);
2849 return VK_SUCCESS;
2850
2851 fail_mem_cache:
2852 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2853 fail_meta:
2854 radv_device_finish_meta(device);
2855 fail:
2856 radv_bo_list_finish(&device->bo_list);
2857
2858 if (device->trace_bo)
2859 device->ws->buffer_destroy(device->trace_bo);
2860
2861 if (device->gfx_init)
2862 device->ws->buffer_destroy(device->gfx_init);
2863
2864 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2865 for (unsigned q = 0; q < device->queue_count[i]; q++)
2866 radv_queue_finish(&device->queues[i][q]);
2867 if (device->queue_count[i])
2868 vk_free(&device->alloc, device->queues[i]);
2869 }
2870
2871 vk_free(&device->alloc, device);
2872 return result;
2873 }
2874
2875 void radv_DestroyDevice(
2876 VkDevice _device,
2877 const VkAllocationCallbacks* pAllocator)
2878 {
2879 RADV_FROM_HANDLE(radv_device, device, _device);
2880
2881 if (!device)
2882 return;
2883
2884 if (device->trace_bo)
2885 device->ws->buffer_destroy(device->trace_bo);
2886
2887 if (device->gfx_init)
2888 device->ws->buffer_destroy(device->gfx_init);
2889
2890 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2891 for (unsigned q = 0; q < device->queue_count[i]; q++)
2892 radv_queue_finish(&device->queues[i][q]);
2893 if (device->queue_count[i])
2894 vk_free(&device->alloc, device->queues[i]);
2895 if (device->empty_cs[i])
2896 device->ws->cs_destroy(device->empty_cs[i]);
2897 }
2898 radv_device_finish_meta(device);
2899
2900 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2901 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2902
2903 radv_destroy_shader_slabs(device);
2904
2905 pthread_cond_destroy(&device->timeline_cond);
2906 radv_bo_list_finish(&device->bo_list);
2907 if (radv_device_use_secure_compile(device->instance)) {
2908 for (unsigned i = 0; i < device->instance->num_sc_threads; i++ ) {
2909 destroy_secure_compile_device(device, i);
2910 }
2911 }
2912
2913 if (device->sc_state) {
2914 free(device->sc_state->uid);
2915 vk_free(&device->alloc, device->sc_state->secure_compile_processes);
2916 }
2917 vk_free(&device->alloc, device->sc_state);
2918 vk_free(&device->alloc, device);
2919 }
2920
2921 VkResult radv_EnumerateInstanceLayerProperties(
2922 uint32_t* pPropertyCount,
2923 VkLayerProperties* pProperties)
2924 {
2925 if (pProperties == NULL) {
2926 *pPropertyCount = 0;
2927 return VK_SUCCESS;
2928 }
2929
2930 /* None supported at this time */
2931 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2932 }
2933
2934 VkResult radv_EnumerateDeviceLayerProperties(
2935 VkPhysicalDevice physicalDevice,
2936 uint32_t* pPropertyCount,
2937 VkLayerProperties* pProperties)
2938 {
2939 if (pProperties == NULL) {
2940 *pPropertyCount = 0;
2941 return VK_SUCCESS;
2942 }
2943
2944 /* None supported at this time */
2945 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2946 }
2947
2948 void radv_GetDeviceQueue2(
2949 VkDevice _device,
2950 const VkDeviceQueueInfo2* pQueueInfo,
2951 VkQueue* pQueue)
2952 {
2953 RADV_FROM_HANDLE(radv_device, device, _device);
2954 struct radv_queue *queue;
2955
2956 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2957 if (pQueueInfo->flags != queue->flags) {
2958 /* From the Vulkan 1.1.70 spec:
2959 *
2960 * "The queue returned by vkGetDeviceQueue2 must have the same
2961 * flags value from this structure as that used at device
2962 * creation time in a VkDeviceQueueCreateInfo instance. If no
2963 * matching flags were specified at device creation time then
2964 * pQueue will return VK_NULL_HANDLE."
2965 */
2966 *pQueue = VK_NULL_HANDLE;
2967 return;
2968 }
2969
2970 *pQueue = radv_queue_to_handle(queue);
2971 }
2972
2973 void radv_GetDeviceQueue(
2974 VkDevice _device,
2975 uint32_t queueFamilyIndex,
2976 uint32_t queueIndex,
2977 VkQueue* pQueue)
2978 {
2979 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2980 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2981 .queueFamilyIndex = queueFamilyIndex,
2982 .queueIndex = queueIndex
2983 };
2984
2985 radv_GetDeviceQueue2(_device, &info, pQueue);
2986 }
2987
2988 static void
2989 fill_geom_tess_rings(struct radv_queue *queue,
2990 uint32_t *map,
2991 bool add_sample_positions,
2992 uint32_t esgs_ring_size,
2993 struct radeon_winsys_bo *esgs_ring_bo,
2994 uint32_t gsvs_ring_size,
2995 struct radeon_winsys_bo *gsvs_ring_bo,
2996 uint32_t tess_factor_ring_size,
2997 uint32_t tess_offchip_ring_offset,
2998 uint32_t tess_offchip_ring_size,
2999 struct radeon_winsys_bo *tess_rings_bo)
3000 {
3001 uint32_t *desc = &map[4];
3002
3003 if (esgs_ring_bo) {
3004 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
3005
3006 /* stride 0, num records - size, add tid, swizzle, elsize4,
3007 index stride 64 */
3008 desc[0] = esgs_va;
3009 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
3010 S_008F04_SWIZZLE_ENABLE(true);
3011 desc[2] = esgs_ring_size;
3012 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3013 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3014 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3015 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3016 S_008F0C_INDEX_STRIDE(3) |
3017 S_008F0C_ADD_TID_ENABLE(1);
3018
3019 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3020 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3021 S_008F0C_OOB_SELECT(2) |
3022 S_008F0C_RESOURCE_LEVEL(1);
3023 } else {
3024 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3025 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3026 S_008F0C_ELEMENT_SIZE(1);
3027 }
3028
3029 /* GS entry for ES->GS ring */
3030 /* stride 0, num records - size, elsize0,
3031 index stride 0 */
3032 desc[4] = esgs_va;
3033 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
3034 desc[6] = esgs_ring_size;
3035 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3036 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3037 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3038 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3039
3040 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3041 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3042 S_008F0C_OOB_SELECT(2) |
3043 S_008F0C_RESOURCE_LEVEL(1);
3044 } else {
3045 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3046 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3047 }
3048 }
3049
3050 desc += 8;
3051
3052 if (gsvs_ring_bo) {
3053 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
3054
3055 /* VS entry for GS->VS ring */
3056 /* stride 0, num records - size, elsize0,
3057 index stride 0 */
3058 desc[0] = gsvs_va;
3059 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
3060 desc[2] = gsvs_ring_size;
3061 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3062 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3063 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3064 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3065
3066 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3067 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3068 S_008F0C_OOB_SELECT(2) |
3069 S_008F0C_RESOURCE_LEVEL(1);
3070 } else {
3071 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3072 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3073 }
3074
3075 /* stride gsvs_itemsize, num records 64
3076 elsize 4, index stride 16 */
3077 /* shader will patch stride and desc[2] */
3078 desc[4] = gsvs_va;
3079 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
3080 S_008F04_SWIZZLE_ENABLE(1);
3081 desc[6] = 0;
3082 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3083 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3084 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3085 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3086 S_008F0C_INDEX_STRIDE(1) |
3087 S_008F0C_ADD_TID_ENABLE(true);
3088
3089 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3090 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3091 S_008F0C_OOB_SELECT(2) |
3092 S_008F0C_RESOURCE_LEVEL(1);
3093 } else {
3094 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3095 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3096 S_008F0C_ELEMENT_SIZE(1);
3097 }
3098
3099 }
3100
3101 desc += 8;
3102
3103 if (tess_rings_bo) {
3104 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
3105 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
3106
3107 desc[0] = tess_va;
3108 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
3109 desc[2] = tess_factor_ring_size;
3110 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3111 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3112 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3113 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3114
3115 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3116 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3117 S_008F0C_OOB_SELECT(3) |
3118 S_008F0C_RESOURCE_LEVEL(1);
3119 } else {
3120 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3121 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3122 }
3123
3124 desc[4] = tess_offchip_va;
3125 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
3126 desc[6] = tess_offchip_ring_size;
3127 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3128 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3129 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3130 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3131
3132 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3133 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3134 S_008F0C_OOB_SELECT(3) |
3135 S_008F0C_RESOURCE_LEVEL(1);
3136 } else {
3137 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3138 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3139 }
3140 }
3141
3142 desc += 8;
3143
3144 if (add_sample_positions) {
3145 /* add sample positions after all rings */
3146 memcpy(desc, queue->device->sample_locations_1x, 8);
3147 desc += 2;
3148 memcpy(desc, queue->device->sample_locations_2x, 16);
3149 desc += 4;
3150 memcpy(desc, queue->device->sample_locations_4x, 32);
3151 desc += 8;
3152 memcpy(desc, queue->device->sample_locations_8x, 64);
3153 }
3154 }
3155
3156 static unsigned
3157 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
3158 {
3159 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
3160 device->physical_device->rad_info.family != CHIP_CARRIZO &&
3161 device->physical_device->rad_info.family != CHIP_STONEY;
3162 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
3163 unsigned max_offchip_buffers;
3164 unsigned offchip_granularity;
3165 unsigned hs_offchip_param;
3166
3167 /*
3168 * Per RadeonSI:
3169 * This must be one less than the maximum number due to a hw limitation.
3170 * Various hardware bugs need thGFX7
3171 *
3172 * Per AMDVLK:
3173 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3174 * Gfx7 should limit max_offchip_buffers to 508
3175 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3176 *
3177 * Follow AMDVLK here.
3178 */
3179 if (device->physical_device->rad_info.chip_class >= GFX10) {
3180 max_offchip_buffers_per_se = 256;
3181 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
3182 device->physical_device->rad_info.chip_class == GFX7 ||
3183 device->physical_device->rad_info.chip_class == GFX6)
3184 --max_offchip_buffers_per_se;
3185
3186 max_offchip_buffers = max_offchip_buffers_per_se *
3187 device->physical_device->rad_info.max_se;
3188
3189 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3190 * around by setting 4K granularity.
3191 */
3192 if (device->tess_offchip_block_dw_size == 4096) {
3193 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
3194 offchip_granularity = V_03093C_X_4K_DWORDS;
3195 } else {
3196 assert(device->tess_offchip_block_dw_size == 8192);
3197 offchip_granularity = V_03093C_X_8K_DWORDS;
3198 }
3199
3200 switch (device->physical_device->rad_info.chip_class) {
3201 case GFX6:
3202 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
3203 break;
3204 case GFX7:
3205 case GFX8:
3206 case GFX9:
3207 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
3208 break;
3209 case GFX10:
3210 break;
3211 default:
3212 break;
3213 }
3214
3215 *max_offchip_buffers_p = max_offchip_buffers;
3216 if (device->physical_device->rad_info.chip_class >= GFX7) {
3217 if (device->physical_device->rad_info.chip_class >= GFX8)
3218 --max_offchip_buffers;
3219 hs_offchip_param =
3220 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
3221 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
3222 } else {
3223 hs_offchip_param =
3224 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
3225 }
3226 return hs_offchip_param;
3227 }
3228
3229 static void
3230 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3231 struct radeon_winsys_bo *esgs_ring_bo,
3232 uint32_t esgs_ring_size,
3233 struct radeon_winsys_bo *gsvs_ring_bo,
3234 uint32_t gsvs_ring_size)
3235 {
3236 if (!esgs_ring_bo && !gsvs_ring_bo)
3237 return;
3238
3239 if (esgs_ring_bo)
3240 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
3241
3242 if (gsvs_ring_bo)
3243 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
3244
3245 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3246 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
3247 radeon_emit(cs, esgs_ring_size >> 8);
3248 radeon_emit(cs, gsvs_ring_size >> 8);
3249 } else {
3250 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
3251 radeon_emit(cs, esgs_ring_size >> 8);
3252 radeon_emit(cs, gsvs_ring_size >> 8);
3253 }
3254 }
3255
3256 static void
3257 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3258 unsigned hs_offchip_param, unsigned tf_ring_size,
3259 struct radeon_winsys_bo *tess_rings_bo)
3260 {
3261 uint64_t tf_va;
3262
3263 if (!tess_rings_bo)
3264 return;
3265
3266 tf_va = radv_buffer_get_va(tess_rings_bo);
3267
3268 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
3269
3270 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3271 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
3272 S_030938_SIZE(tf_ring_size / 4));
3273 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
3274 tf_va >> 8);
3275
3276 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3277 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3278 S_030984_BASE_HI(tf_va >> 40));
3279 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3280 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
3281 S_030944_BASE_HI(tf_va >> 40));
3282 }
3283 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
3284 hs_offchip_param);
3285 } else {
3286 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
3287 S_008988_SIZE(tf_ring_size / 4));
3288 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
3289 tf_va >> 8);
3290 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3291 hs_offchip_param);
3292 }
3293 }
3294
3295 static void
3296 radv_emit_graphics_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3297 uint32_t size_per_wave, uint32_t waves,
3298 struct radeon_winsys_bo *scratch_bo)
3299 {
3300 if (queue->queue_family_index != RADV_QUEUE_GENERAL)
3301 return;
3302
3303 if (!scratch_bo)
3304 return;
3305
3306 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3307
3308 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3309 S_0286E8_WAVES(waves) |
3310 S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3311 }
3312
3313 static void
3314 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3315 uint32_t size_per_wave, uint32_t waves,
3316 struct radeon_winsys_bo *compute_scratch_bo)
3317 {
3318 uint64_t scratch_va;
3319
3320 if (!compute_scratch_bo)
3321 return;
3322
3323 scratch_va = radv_buffer_get_va(compute_scratch_bo);
3324
3325 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
3326
3327 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
3328 radeon_emit(cs, scratch_va);
3329 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3330 S_008F04_SWIZZLE_ENABLE(1));
3331
3332 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
3333 S_00B860_WAVES(waves) |
3334 S_00B860_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3335 }
3336
3337 static void
3338 radv_emit_global_shader_pointers(struct radv_queue *queue,
3339 struct radeon_cmdbuf *cs,
3340 struct radeon_winsys_bo *descriptor_bo)
3341 {
3342 uint64_t va;
3343
3344 if (!descriptor_bo)
3345 return;
3346
3347 va = radv_buffer_get_va(descriptor_bo);
3348
3349 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
3350
3351 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3352 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3353 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3354 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3355 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3356
3357 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3358 radv_emit_shader_pointer(queue->device, cs, regs[i],
3359 va, true);
3360 }
3361 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3362 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3363 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3364 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3365 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3366
3367 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3368 radv_emit_shader_pointer(queue->device, cs, regs[i],
3369 va, true);
3370 }
3371 } else {
3372 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3373 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3374 R_00B230_SPI_SHADER_USER_DATA_GS_0,
3375 R_00B330_SPI_SHADER_USER_DATA_ES_0,
3376 R_00B430_SPI_SHADER_USER_DATA_HS_0,
3377 R_00B530_SPI_SHADER_USER_DATA_LS_0};
3378
3379 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3380 radv_emit_shader_pointer(queue->device, cs, regs[i],
3381 va, true);
3382 }
3383 }
3384 }
3385
3386 static void
3387 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3388 {
3389 struct radv_device *device = queue->device;
3390
3391 if (device->gfx_init) {
3392 uint64_t va = radv_buffer_get_va(device->gfx_init);
3393
3394 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
3395 radeon_emit(cs, va);
3396 radeon_emit(cs, va >> 32);
3397 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
3398
3399 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
3400 } else {
3401 struct radv_physical_device *physical_device = device->physical_device;
3402 si_emit_graphics(physical_device, cs);
3403 }
3404 }
3405
3406 static void
3407 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3408 {
3409 struct radv_physical_device *physical_device = queue->device->physical_device;
3410 si_emit_compute(physical_device, cs);
3411 }
3412
3413 static VkResult
3414 radv_get_preamble_cs(struct radv_queue *queue,
3415 uint32_t scratch_size_per_wave,
3416 uint32_t scratch_waves,
3417 uint32_t compute_scratch_size_per_wave,
3418 uint32_t compute_scratch_waves,
3419 uint32_t esgs_ring_size,
3420 uint32_t gsvs_ring_size,
3421 bool needs_tess_rings,
3422 bool needs_gds,
3423 bool needs_sample_positions,
3424 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
3425 struct radeon_cmdbuf **initial_preamble_cs,
3426 struct radeon_cmdbuf **continue_preamble_cs)
3427 {
3428 struct radeon_winsys_bo *scratch_bo = NULL;
3429 struct radeon_winsys_bo *descriptor_bo = NULL;
3430 struct radeon_winsys_bo *compute_scratch_bo = NULL;
3431 struct radeon_winsys_bo *esgs_ring_bo = NULL;
3432 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
3433 struct radeon_winsys_bo *tess_rings_bo = NULL;
3434 struct radeon_winsys_bo *gds_bo = NULL;
3435 struct radeon_winsys_bo *gds_oa_bo = NULL;
3436 struct radeon_cmdbuf *dest_cs[3] = {0};
3437 bool add_tess_rings = false, add_gds = false, add_sample_positions = false;
3438 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
3439 unsigned max_offchip_buffers;
3440 unsigned hs_offchip_param = 0;
3441 unsigned tess_offchip_ring_offset;
3442 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
3443 if (!queue->has_tess_rings) {
3444 if (needs_tess_rings)
3445 add_tess_rings = true;
3446 }
3447 if (!queue->has_gds) {
3448 if (needs_gds)
3449 add_gds = true;
3450 }
3451 if (!queue->has_sample_positions) {
3452 if (needs_sample_positions)
3453 add_sample_positions = true;
3454 }
3455 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
3456 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
3457 &max_offchip_buffers);
3458 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
3459 tess_offchip_ring_size = max_offchip_buffers *
3460 queue->device->tess_offchip_block_dw_size * 4;
3461
3462 scratch_size_per_wave = MAX2(scratch_size_per_wave, queue->scratch_size_per_wave);
3463 if (scratch_size_per_wave)
3464 scratch_waves = MIN2(scratch_waves, UINT32_MAX / scratch_size_per_wave);
3465 else
3466 scratch_waves = 0;
3467
3468 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave, queue->compute_scratch_size_per_wave);
3469 if (compute_scratch_size_per_wave)
3470 compute_scratch_waves = MIN2(compute_scratch_waves, UINT32_MAX / compute_scratch_size_per_wave);
3471 else
3472 compute_scratch_waves = 0;
3473
3474 if (scratch_size_per_wave <= queue->scratch_size_per_wave &&
3475 scratch_waves <= queue->scratch_waves &&
3476 compute_scratch_size_per_wave <= queue->compute_scratch_size_per_wave &&
3477 compute_scratch_waves <= queue->compute_scratch_waves &&
3478 esgs_ring_size <= queue->esgs_ring_size &&
3479 gsvs_ring_size <= queue->gsvs_ring_size &&
3480 !add_tess_rings && !add_gds && !add_sample_positions &&
3481 queue->initial_preamble_cs) {
3482 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3483 *initial_preamble_cs = queue->initial_preamble_cs;
3484 *continue_preamble_cs = queue->continue_preamble_cs;
3485 if (!scratch_size_per_wave && !compute_scratch_size_per_wave &&
3486 !esgs_ring_size && !gsvs_ring_size && !needs_tess_rings &&
3487 !needs_gds && !needs_sample_positions)
3488 *continue_preamble_cs = NULL;
3489 return VK_SUCCESS;
3490 }
3491
3492 uint32_t scratch_size = scratch_size_per_wave * scratch_waves;
3493 uint32_t queue_scratch_size = queue->scratch_size_per_wave * queue->scratch_waves;
3494 if (scratch_size > queue_scratch_size) {
3495 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3496 scratch_size,
3497 4096,
3498 RADEON_DOMAIN_VRAM,
3499 ring_bo_flags,
3500 RADV_BO_PRIORITY_SCRATCH);
3501 if (!scratch_bo)
3502 goto fail;
3503 } else
3504 scratch_bo = queue->scratch_bo;
3505
3506 uint32_t compute_scratch_size = compute_scratch_size_per_wave * compute_scratch_waves;
3507 uint32_t compute_queue_scratch_size = queue->compute_scratch_size_per_wave * queue->compute_scratch_waves;
3508 if (compute_scratch_size > compute_queue_scratch_size) {
3509 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3510 compute_scratch_size,
3511 4096,
3512 RADEON_DOMAIN_VRAM,
3513 ring_bo_flags,
3514 RADV_BO_PRIORITY_SCRATCH);
3515 if (!compute_scratch_bo)
3516 goto fail;
3517
3518 } else
3519 compute_scratch_bo = queue->compute_scratch_bo;
3520
3521 if (esgs_ring_size > queue->esgs_ring_size) {
3522 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3523 esgs_ring_size,
3524 4096,
3525 RADEON_DOMAIN_VRAM,
3526 ring_bo_flags,
3527 RADV_BO_PRIORITY_SCRATCH);
3528 if (!esgs_ring_bo)
3529 goto fail;
3530 } else {
3531 esgs_ring_bo = queue->esgs_ring_bo;
3532 esgs_ring_size = queue->esgs_ring_size;
3533 }
3534
3535 if (gsvs_ring_size > queue->gsvs_ring_size) {
3536 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3537 gsvs_ring_size,
3538 4096,
3539 RADEON_DOMAIN_VRAM,
3540 ring_bo_flags,
3541 RADV_BO_PRIORITY_SCRATCH);
3542 if (!gsvs_ring_bo)
3543 goto fail;
3544 } else {
3545 gsvs_ring_bo = queue->gsvs_ring_bo;
3546 gsvs_ring_size = queue->gsvs_ring_size;
3547 }
3548
3549 if (add_tess_rings) {
3550 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
3551 tess_offchip_ring_offset + tess_offchip_ring_size,
3552 256,
3553 RADEON_DOMAIN_VRAM,
3554 ring_bo_flags,
3555 RADV_BO_PRIORITY_SCRATCH);
3556 if (!tess_rings_bo)
3557 goto fail;
3558 } else {
3559 tess_rings_bo = queue->tess_rings_bo;
3560 }
3561
3562 if (add_gds) {
3563 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3564
3565 /* 4 streamout GDS counters.
3566 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3567 */
3568 gds_bo = queue->device->ws->buffer_create(queue->device->ws,
3569 256, 4,
3570 RADEON_DOMAIN_GDS,
3571 ring_bo_flags,
3572 RADV_BO_PRIORITY_SCRATCH);
3573 if (!gds_bo)
3574 goto fail;
3575
3576 gds_oa_bo = queue->device->ws->buffer_create(queue->device->ws,
3577 4, 1,
3578 RADEON_DOMAIN_OA,
3579 ring_bo_flags,
3580 RADV_BO_PRIORITY_SCRATCH);
3581 if (!gds_oa_bo)
3582 goto fail;
3583 } else {
3584 gds_bo = queue->gds_bo;
3585 gds_oa_bo = queue->gds_oa_bo;
3586 }
3587
3588 if (scratch_bo != queue->scratch_bo ||
3589 esgs_ring_bo != queue->esgs_ring_bo ||
3590 gsvs_ring_bo != queue->gsvs_ring_bo ||
3591 tess_rings_bo != queue->tess_rings_bo ||
3592 add_sample_positions) {
3593 uint32_t size = 0;
3594 if (gsvs_ring_bo || esgs_ring_bo ||
3595 tess_rings_bo || add_sample_positions) {
3596 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
3597 if (add_sample_positions)
3598 size += 128; /* 64+32+16+8 = 120 bytes */
3599 }
3600 else if (scratch_bo)
3601 size = 8; /* 2 dword */
3602
3603 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
3604 size,
3605 4096,
3606 RADEON_DOMAIN_VRAM,
3607 RADEON_FLAG_CPU_ACCESS |
3608 RADEON_FLAG_NO_INTERPROCESS_SHARING |
3609 RADEON_FLAG_READ_ONLY,
3610 RADV_BO_PRIORITY_DESCRIPTOR);
3611 if (!descriptor_bo)
3612 goto fail;
3613 } else
3614 descriptor_bo = queue->descriptor_bo;
3615
3616 if (descriptor_bo != queue->descriptor_bo) {
3617 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
3618
3619 if (scratch_bo) {
3620 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
3621 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3622 S_008F04_SWIZZLE_ENABLE(1);
3623 map[0] = scratch_va;
3624 map[1] = rsrc1;
3625 }
3626
3627 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
3628 fill_geom_tess_rings(queue, map, add_sample_positions,
3629 esgs_ring_size, esgs_ring_bo,
3630 gsvs_ring_size, gsvs_ring_bo,
3631 tess_factor_ring_size,
3632 tess_offchip_ring_offset,
3633 tess_offchip_ring_size,
3634 tess_rings_bo);
3635
3636 queue->device->ws->buffer_unmap(descriptor_bo);
3637 }
3638
3639 for(int i = 0; i < 3; ++i) {
3640 struct radeon_cmdbuf *cs = NULL;
3641 cs = queue->device->ws->cs_create(queue->device->ws,
3642 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
3643 if (!cs)
3644 goto fail;
3645
3646 dest_cs[i] = cs;
3647
3648 if (scratch_bo)
3649 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3650
3651 /* Emit initial configuration. */
3652 switch (queue->queue_family_index) {
3653 case RADV_QUEUE_GENERAL:
3654 radv_init_graphics_state(cs, queue);
3655 break;
3656 case RADV_QUEUE_COMPUTE:
3657 radv_init_compute_state(cs, queue);
3658 break;
3659 case RADV_QUEUE_TRANSFER:
3660 break;
3661 }
3662
3663 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
3664 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3665 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3666
3667 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3668 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3669 }
3670
3671 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
3672 gsvs_ring_bo, gsvs_ring_size);
3673 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
3674 tess_factor_ring_size, tess_rings_bo);
3675 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
3676 radv_emit_compute_scratch(queue, cs, compute_scratch_size_per_wave,
3677 compute_scratch_waves, compute_scratch_bo);
3678 radv_emit_graphics_scratch(queue, cs, scratch_size_per_wave,
3679 scratch_waves, scratch_bo);
3680
3681 if (gds_bo)
3682 radv_cs_add_buffer(queue->device->ws, cs, gds_bo);
3683 if (gds_oa_bo)
3684 radv_cs_add_buffer(queue->device->ws, cs, gds_oa_bo);
3685
3686 if (i == 0) {
3687 si_cs_emit_cache_flush(cs,
3688 queue->device->physical_device->rad_info.chip_class,
3689 NULL, 0,
3690 queue->queue_family_index == RING_COMPUTE &&
3691 queue->device->physical_device->rad_info.chip_class >= GFX7,
3692 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
3693 RADV_CMD_FLAG_INV_ICACHE |
3694 RADV_CMD_FLAG_INV_SCACHE |
3695 RADV_CMD_FLAG_INV_VCACHE |
3696 RADV_CMD_FLAG_INV_L2 |
3697 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3698 } else if (i == 1) {
3699 si_cs_emit_cache_flush(cs,
3700 queue->device->physical_device->rad_info.chip_class,
3701 NULL, 0,
3702 queue->queue_family_index == RING_COMPUTE &&
3703 queue->device->physical_device->rad_info.chip_class >= GFX7,
3704 RADV_CMD_FLAG_INV_ICACHE |
3705 RADV_CMD_FLAG_INV_SCACHE |
3706 RADV_CMD_FLAG_INV_VCACHE |
3707 RADV_CMD_FLAG_INV_L2 |
3708 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3709 }
3710
3711 if (!queue->device->ws->cs_finalize(cs))
3712 goto fail;
3713 }
3714
3715 if (queue->initial_full_flush_preamble_cs)
3716 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
3717
3718 if (queue->initial_preamble_cs)
3719 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
3720
3721 if (queue->continue_preamble_cs)
3722 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
3723
3724 queue->initial_full_flush_preamble_cs = dest_cs[0];
3725 queue->initial_preamble_cs = dest_cs[1];
3726 queue->continue_preamble_cs = dest_cs[2];
3727
3728 if (scratch_bo != queue->scratch_bo) {
3729 if (queue->scratch_bo)
3730 queue->device->ws->buffer_destroy(queue->scratch_bo);
3731 queue->scratch_bo = scratch_bo;
3732 }
3733 queue->scratch_size_per_wave = scratch_size_per_wave;
3734 queue->scratch_waves = scratch_waves;
3735
3736 if (compute_scratch_bo != queue->compute_scratch_bo) {
3737 if (queue->compute_scratch_bo)
3738 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
3739 queue->compute_scratch_bo = compute_scratch_bo;
3740 }
3741 queue->compute_scratch_size_per_wave = compute_scratch_size_per_wave;
3742 queue->compute_scratch_waves = compute_scratch_waves;
3743
3744 if (esgs_ring_bo != queue->esgs_ring_bo) {
3745 if (queue->esgs_ring_bo)
3746 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
3747 queue->esgs_ring_bo = esgs_ring_bo;
3748 queue->esgs_ring_size = esgs_ring_size;
3749 }
3750
3751 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
3752 if (queue->gsvs_ring_bo)
3753 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
3754 queue->gsvs_ring_bo = gsvs_ring_bo;
3755 queue->gsvs_ring_size = gsvs_ring_size;
3756 }
3757
3758 if (tess_rings_bo != queue->tess_rings_bo) {
3759 queue->tess_rings_bo = tess_rings_bo;
3760 queue->has_tess_rings = true;
3761 }
3762
3763 if (gds_bo != queue->gds_bo) {
3764 queue->gds_bo = gds_bo;
3765 queue->has_gds = true;
3766 }
3767
3768 if (gds_oa_bo != queue->gds_oa_bo)
3769 queue->gds_oa_bo = gds_oa_bo;
3770
3771 if (descriptor_bo != queue->descriptor_bo) {
3772 if (queue->descriptor_bo)
3773 queue->device->ws->buffer_destroy(queue->descriptor_bo);
3774
3775 queue->descriptor_bo = descriptor_bo;
3776 }
3777
3778 if (add_sample_positions)
3779 queue->has_sample_positions = true;
3780
3781 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3782 *initial_preamble_cs = queue->initial_preamble_cs;
3783 *continue_preamble_cs = queue->continue_preamble_cs;
3784 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
3785 *continue_preamble_cs = NULL;
3786 return VK_SUCCESS;
3787 fail:
3788 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
3789 if (dest_cs[i])
3790 queue->device->ws->cs_destroy(dest_cs[i]);
3791 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
3792 queue->device->ws->buffer_destroy(descriptor_bo);
3793 if (scratch_bo && scratch_bo != queue->scratch_bo)
3794 queue->device->ws->buffer_destroy(scratch_bo);
3795 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
3796 queue->device->ws->buffer_destroy(compute_scratch_bo);
3797 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
3798 queue->device->ws->buffer_destroy(esgs_ring_bo);
3799 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
3800 queue->device->ws->buffer_destroy(gsvs_ring_bo);
3801 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
3802 queue->device->ws->buffer_destroy(tess_rings_bo);
3803 if (gds_bo && gds_bo != queue->gds_bo)
3804 queue->device->ws->buffer_destroy(gds_bo);
3805 if (gds_oa_bo && gds_oa_bo != queue->gds_oa_bo)
3806 queue->device->ws->buffer_destroy(gds_oa_bo);
3807
3808 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3809 }
3810
3811 static VkResult radv_alloc_sem_counts(struct radv_device *device,
3812 struct radv_winsys_sem_counts *counts,
3813 int num_sems,
3814 struct radv_semaphore_part **sems,
3815 const uint64_t *timeline_values,
3816 VkFence _fence,
3817 bool is_signal)
3818 {
3819 int syncobj_idx = 0, sem_idx = 0;
3820
3821 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
3822 return VK_SUCCESS;
3823
3824 for (uint32_t i = 0; i < num_sems; i++) {
3825 switch(sems[i]->kind) {
3826 case RADV_SEMAPHORE_SYNCOBJ:
3827 counts->syncobj_count++;
3828 break;
3829 case RADV_SEMAPHORE_WINSYS:
3830 counts->sem_count++;
3831 break;
3832 case RADV_SEMAPHORE_NONE:
3833 break;
3834 case RADV_SEMAPHORE_TIMELINE:
3835 counts->syncobj_count++;
3836 break;
3837 }
3838 }
3839
3840 if (_fence != VK_NULL_HANDLE) {
3841 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3842 if (fence->temp_syncobj || fence->syncobj)
3843 counts->syncobj_count++;
3844 }
3845
3846 if (counts->syncobj_count) {
3847 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
3848 if (!counts->syncobj)
3849 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3850 }
3851
3852 if (counts->sem_count) {
3853 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
3854 if (!counts->sem) {
3855 free(counts->syncobj);
3856 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3857 }
3858 }
3859
3860 for (uint32_t i = 0; i < num_sems; i++) {
3861 switch(sems[i]->kind) {
3862 case RADV_SEMAPHORE_NONE:
3863 unreachable("Empty semaphore");
3864 break;
3865 case RADV_SEMAPHORE_SYNCOBJ:
3866 counts->syncobj[syncobj_idx++] = sems[i]->syncobj;
3867 break;
3868 case RADV_SEMAPHORE_WINSYS:
3869 counts->sem[sem_idx++] = sems[i]->ws_sem;
3870 break;
3871 case RADV_SEMAPHORE_TIMELINE: {
3872 pthread_mutex_lock(&sems[i]->timeline.mutex);
3873 struct radv_timeline_point *point = NULL;
3874 if (is_signal) {
3875 point = radv_timeline_add_point_locked(device, &sems[i]->timeline, timeline_values[i]);
3876 } else {
3877 point = radv_timeline_find_point_at_least_locked(device, &sems[i]->timeline, timeline_values[i]);
3878 }
3879
3880 pthread_mutex_unlock(&sems[i]->timeline.mutex);
3881
3882 if (point) {
3883 counts->syncobj[syncobj_idx++] = point->syncobj;
3884 } else {
3885 /* Explicitly remove the semaphore so we might not find
3886 * a point later post-submit. */
3887 sems[i] = NULL;
3888 }
3889 break;
3890 }
3891 }
3892 }
3893
3894 if (_fence != VK_NULL_HANDLE) {
3895 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3896 if (fence->temp_syncobj)
3897 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
3898 else if (fence->syncobj)
3899 counts->syncobj[syncobj_idx++] = fence->syncobj;
3900 }
3901
3902 assert(syncobj_idx <= counts->syncobj_count);
3903 counts->syncobj_count = syncobj_idx;
3904
3905 return VK_SUCCESS;
3906 }
3907
3908 static void
3909 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
3910 {
3911 free(sem_info->wait.syncobj);
3912 free(sem_info->wait.sem);
3913 free(sem_info->signal.syncobj);
3914 free(sem_info->signal.sem);
3915 }
3916
3917
3918 static void radv_free_temp_syncobjs(struct radv_device *device,
3919 int num_sems,
3920 struct radv_semaphore_part *sems)
3921 {
3922 for (uint32_t i = 0; i < num_sems; i++) {
3923 radv_destroy_semaphore_part(device, sems + i);
3924 }
3925 }
3926
3927 static VkResult
3928 radv_alloc_sem_info(struct radv_device *device,
3929 struct radv_winsys_sem_info *sem_info,
3930 int num_wait_sems,
3931 struct radv_semaphore_part **wait_sems,
3932 const uint64_t *wait_values,
3933 int num_signal_sems,
3934 struct radv_semaphore_part **signal_sems,
3935 const uint64_t *signal_values,
3936 VkFence fence)
3937 {
3938 VkResult ret;
3939 memset(sem_info, 0, sizeof(*sem_info));
3940
3941 ret = radv_alloc_sem_counts(device, &sem_info->wait, num_wait_sems, wait_sems, wait_values, VK_NULL_HANDLE, false);
3942 if (ret)
3943 return ret;
3944 ret = radv_alloc_sem_counts(device, &sem_info->signal, num_signal_sems, signal_sems, signal_values, fence, true);
3945 if (ret)
3946 radv_free_sem_info(sem_info);
3947
3948 /* caller can override these */
3949 sem_info->cs_emit_wait = true;
3950 sem_info->cs_emit_signal = true;
3951 return ret;
3952 }
3953
3954 static void
3955 radv_finalize_timelines(struct radv_device *device,
3956 uint32_t num_wait_sems,
3957 struct radv_semaphore_part **wait_sems,
3958 const uint64_t *wait_values,
3959 uint32_t num_signal_sems,
3960 struct radv_semaphore_part **signal_sems,
3961 const uint64_t *signal_values,
3962 struct list_head *processing_list)
3963 {
3964 for (uint32_t i = 0; i < num_wait_sems; ++i) {
3965 if (wait_sems[i] && wait_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
3966 pthread_mutex_lock(&wait_sems[i]->timeline.mutex);
3967 struct radv_timeline_point *point =
3968 radv_timeline_find_point_at_least_locked(device, &wait_sems[i]->timeline, wait_values[i]);
3969 if (point)
3970 --point->wait_count;
3971 pthread_mutex_unlock(&wait_sems[i]->timeline.mutex);
3972 }
3973 }
3974 for (uint32_t i = 0; i < num_signal_sems; ++i) {
3975 if (signal_sems[i] && signal_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
3976 pthread_mutex_lock(&signal_sems[i]->timeline.mutex);
3977 struct radv_timeline_point *point =
3978 radv_timeline_find_point_at_least_locked(device, &signal_sems[i]->timeline, signal_values[i]);
3979 if (point) {
3980 signal_sems[i]->timeline.highest_submitted =
3981 MAX2(signal_sems[i]->timeline.highest_submitted, point->value);
3982 point->wait_count--;
3983 }
3984 radv_timeline_trigger_waiters_locked(&signal_sems[i]->timeline, processing_list);
3985 pthread_mutex_unlock(&signal_sems[i]->timeline.mutex);
3986 }
3987 }
3988 }
3989
3990 static void
3991 radv_sparse_buffer_bind_memory(struct radv_device *device,
3992 const VkSparseBufferMemoryBindInfo *bind)
3993 {
3994 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3995
3996 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3997 struct radv_device_memory *mem = NULL;
3998
3999 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4000 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4001
4002 device->ws->buffer_virtual_bind(buffer->bo,
4003 bind->pBinds[i].resourceOffset,
4004 bind->pBinds[i].size,
4005 mem ? mem->bo : NULL,
4006 bind->pBinds[i].memoryOffset);
4007 }
4008 }
4009
4010 static void
4011 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
4012 const VkSparseImageOpaqueMemoryBindInfo *bind)
4013 {
4014 RADV_FROM_HANDLE(radv_image, image, bind->image);
4015
4016 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4017 struct radv_device_memory *mem = NULL;
4018
4019 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4020 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4021
4022 device->ws->buffer_virtual_bind(image->bo,
4023 bind->pBinds[i].resourceOffset,
4024 bind->pBinds[i].size,
4025 mem ? mem->bo : NULL,
4026 bind->pBinds[i].memoryOffset);
4027 }
4028 }
4029
4030 static VkResult
4031 radv_get_preambles(struct radv_queue *queue,
4032 const VkCommandBuffer *cmd_buffers,
4033 uint32_t cmd_buffer_count,
4034 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
4035 struct radeon_cmdbuf **initial_preamble_cs,
4036 struct radeon_cmdbuf **continue_preamble_cs)
4037 {
4038 uint32_t scratch_size_per_wave = 0, waves_wanted = 0;
4039 uint32_t compute_scratch_size_per_wave = 0, compute_waves_wanted = 0;
4040 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
4041 bool tess_rings_needed = false;
4042 bool gds_needed = false;
4043 bool sample_positions_needed = false;
4044
4045 for (uint32_t j = 0; j < cmd_buffer_count; j++) {
4046 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
4047 cmd_buffers[j]);
4048
4049 scratch_size_per_wave = MAX2(scratch_size_per_wave, cmd_buffer->scratch_size_per_wave_needed);
4050 waves_wanted = MAX2(waves_wanted, cmd_buffer->scratch_waves_wanted);
4051 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave,
4052 cmd_buffer->compute_scratch_size_per_wave_needed);
4053 compute_waves_wanted = MAX2(compute_waves_wanted,
4054 cmd_buffer->compute_scratch_waves_wanted);
4055 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
4056 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
4057 tess_rings_needed |= cmd_buffer->tess_rings_needed;
4058 gds_needed |= cmd_buffer->gds_needed;
4059 sample_positions_needed |= cmd_buffer->sample_positions_needed;
4060 }
4061
4062 return radv_get_preamble_cs(queue, scratch_size_per_wave, waves_wanted,
4063 compute_scratch_size_per_wave, compute_waves_wanted,
4064 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
4065 gds_needed, sample_positions_needed,
4066 initial_full_flush_preamble_cs,
4067 initial_preamble_cs, continue_preamble_cs);
4068 }
4069
4070 struct radv_deferred_queue_submission {
4071 struct radv_queue *queue;
4072 VkCommandBuffer *cmd_buffers;
4073 uint32_t cmd_buffer_count;
4074
4075 /* Sparse bindings that happen on a queue. */
4076 VkSparseBufferMemoryBindInfo *buffer_binds;
4077 uint32_t buffer_bind_count;
4078 VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4079 uint32_t image_opaque_bind_count;
4080
4081 bool flush_caches;
4082 VkShaderStageFlags wait_dst_stage_mask;
4083 struct radv_semaphore_part **wait_semaphores;
4084 uint32_t wait_semaphore_count;
4085 struct radv_semaphore_part **signal_semaphores;
4086 uint32_t signal_semaphore_count;
4087 VkFence fence;
4088
4089 uint64_t *wait_values;
4090 uint64_t *signal_values;
4091
4092 struct radv_semaphore_part *temporary_semaphore_parts;
4093 uint32_t temporary_semaphore_part_count;
4094
4095 struct list_head queue_pending_list;
4096 uint32_t submission_wait_count;
4097 struct radv_timeline_waiter *wait_nodes;
4098
4099 struct list_head processing_list;
4100 };
4101
4102 struct radv_queue_submission {
4103 const VkCommandBuffer *cmd_buffers;
4104 uint32_t cmd_buffer_count;
4105
4106 /* Sparse bindings that happen on a queue. */
4107 const VkSparseBufferMemoryBindInfo *buffer_binds;
4108 uint32_t buffer_bind_count;
4109 const VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4110 uint32_t image_opaque_bind_count;
4111
4112 bool flush_caches;
4113 VkPipelineStageFlags wait_dst_stage_mask;
4114 const VkSemaphore *wait_semaphores;
4115 uint32_t wait_semaphore_count;
4116 const VkSemaphore *signal_semaphores;
4117 uint32_t signal_semaphore_count;
4118 VkFence fence;
4119
4120 const uint64_t *wait_values;
4121 uint32_t wait_value_count;
4122 const uint64_t *signal_values;
4123 uint32_t signal_value_count;
4124 };
4125
4126 static VkResult
4127 radv_create_deferred_submission(struct radv_queue *queue,
4128 const struct radv_queue_submission *submission,
4129 struct radv_deferred_queue_submission **out)
4130 {
4131 struct radv_deferred_queue_submission *deferred = NULL;
4132 size_t size = sizeof(struct radv_deferred_queue_submission);
4133
4134 uint32_t temporary_count = 0;
4135 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4136 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4137 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE)
4138 ++temporary_count;
4139 }
4140
4141 size += submission->cmd_buffer_count * sizeof(VkCommandBuffer);
4142 size += submission->buffer_bind_count * sizeof(VkSparseBufferMemoryBindInfo);
4143 size += submission->image_opaque_bind_count * sizeof(VkSparseImageOpaqueMemoryBindInfo);
4144 size += submission->wait_semaphore_count * sizeof(struct radv_semaphore_part *);
4145 size += temporary_count * sizeof(struct radv_semaphore_part);
4146 size += submission->signal_semaphore_count * sizeof(struct radv_semaphore_part *);
4147 size += submission->wait_value_count * sizeof(uint64_t);
4148 size += submission->signal_value_count * sizeof(uint64_t);
4149 size += submission->wait_semaphore_count * sizeof(struct radv_timeline_waiter);
4150
4151 deferred = calloc(1, size);
4152 if (!deferred)
4153 return VK_ERROR_OUT_OF_HOST_MEMORY;
4154
4155 deferred->queue = queue;
4156
4157 deferred->cmd_buffers = (void*)(deferred + 1);
4158 deferred->cmd_buffer_count = submission->cmd_buffer_count;
4159 memcpy(deferred->cmd_buffers, submission->cmd_buffers,
4160 submission->cmd_buffer_count * sizeof(*deferred->cmd_buffers));
4161
4162 deferred->buffer_binds = (void*)(deferred->cmd_buffers + submission->cmd_buffer_count);
4163 deferred->buffer_bind_count = submission->buffer_bind_count;
4164 memcpy(deferred->buffer_binds, submission->buffer_binds,
4165 submission->buffer_bind_count * sizeof(*deferred->buffer_binds));
4166
4167 deferred->image_opaque_binds = (void*)(deferred->buffer_binds + submission->buffer_bind_count);
4168 deferred->image_opaque_bind_count = submission->image_opaque_bind_count;
4169 memcpy(deferred->image_opaque_binds, submission->image_opaque_binds,
4170 submission->image_opaque_bind_count * sizeof(*deferred->image_opaque_binds));
4171
4172 deferred->flush_caches = submission->flush_caches;
4173 deferred->wait_dst_stage_mask = submission->wait_dst_stage_mask;
4174
4175 deferred->wait_semaphores = (void*)(deferred->image_opaque_binds + deferred->image_opaque_bind_count);
4176 deferred->wait_semaphore_count = submission->wait_semaphore_count;
4177
4178 deferred->signal_semaphores = (void*)(deferred->wait_semaphores + deferred->wait_semaphore_count);
4179 deferred->signal_semaphore_count = submission->signal_semaphore_count;
4180
4181 deferred->fence = submission->fence;
4182
4183 deferred->temporary_semaphore_parts = (void*)(deferred->signal_semaphores + deferred->signal_semaphore_count);
4184 deferred->temporary_semaphore_part_count = temporary_count;
4185
4186 uint32_t temporary_idx = 0;
4187 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4188 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4189 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4190 deferred->wait_semaphores[i] = &deferred->temporary_semaphore_parts[temporary_idx];
4191 deferred->temporary_semaphore_parts[temporary_idx] = semaphore->temporary;
4192 semaphore->temporary.kind = RADV_SEMAPHORE_NONE;
4193 ++temporary_idx;
4194 } else
4195 deferred->wait_semaphores[i] = &semaphore->permanent;
4196 }
4197
4198 for (uint32_t i = 0; i < submission->signal_semaphore_count; ++i) {
4199 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->signal_semaphores[i]);
4200 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4201 deferred->signal_semaphores[i] = &semaphore->temporary;
4202 } else {
4203 deferred->signal_semaphores[i] = &semaphore->permanent;
4204 }
4205 }
4206
4207 deferred->wait_values = (void*)(deferred->temporary_semaphore_parts + temporary_count);
4208 memcpy(deferred->wait_values, submission->wait_values, submission->wait_value_count * sizeof(uint64_t));
4209 deferred->signal_values = deferred->wait_values + submission->wait_value_count;
4210 memcpy(deferred->signal_values, submission->signal_values, submission->signal_value_count * sizeof(uint64_t));
4211
4212 deferred->wait_nodes = (void*)(deferred->signal_values + submission->signal_value_count);
4213 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4214 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4215 deferred->submission_wait_count = 1 + submission->wait_semaphore_count;
4216
4217 *out = deferred;
4218 return VK_SUCCESS;
4219 }
4220
4221 static void
4222 radv_queue_enqueue_submission(struct radv_deferred_queue_submission *submission,
4223 struct list_head *processing_list)
4224 {
4225 uint32_t wait_cnt = 0;
4226 struct radv_timeline_waiter *waiter = submission->wait_nodes;
4227 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4228 if (submission->wait_semaphores[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4229 pthread_mutex_lock(&submission->wait_semaphores[i]->timeline.mutex);
4230 if (submission->wait_semaphores[i]->timeline.highest_submitted < submission->wait_values[i]) {
4231 ++wait_cnt;
4232 waiter->value = submission->wait_values[i];
4233 waiter->submission = submission;
4234 list_addtail(&waiter->list, &submission->wait_semaphores[i]->timeline.waiters);
4235 ++waiter;
4236 }
4237 pthread_mutex_unlock(&submission->wait_semaphores[i]->timeline.mutex);
4238 }
4239 }
4240
4241 pthread_mutex_lock(&submission->queue->pending_mutex);
4242
4243 bool is_first = list_is_empty(&submission->queue->pending_submissions);
4244 list_addtail(&submission->queue_pending_list, &submission->queue->pending_submissions);
4245
4246 pthread_mutex_unlock(&submission->queue->pending_mutex);
4247
4248 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4249 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4250 * submission. */
4251 uint32_t decrement = submission->wait_semaphore_count - wait_cnt + (is_first ? 1 : 0);
4252 if (__atomic_sub_fetch(&submission->submission_wait_count, decrement, __ATOMIC_ACQ_REL) == 0) {
4253 list_addtail(&submission->processing_list, processing_list);
4254 }
4255 }
4256
4257 static void
4258 radv_queue_submission_update_queue(struct radv_deferred_queue_submission *submission,
4259 struct list_head *processing_list)
4260 {
4261 pthread_mutex_lock(&submission->queue->pending_mutex);
4262 list_del(&submission->queue_pending_list);
4263
4264 /* trigger the next submission in the queue. */
4265 if (!list_is_empty(&submission->queue->pending_submissions)) {
4266 struct radv_deferred_queue_submission *next_submission =
4267 list_first_entry(&submission->queue->pending_submissions,
4268 struct radv_deferred_queue_submission,
4269 queue_pending_list);
4270 if (p_atomic_dec_zero(&next_submission->submission_wait_count)) {
4271 list_addtail(&next_submission->processing_list, processing_list);
4272 }
4273 }
4274 pthread_mutex_unlock(&submission->queue->pending_mutex);
4275
4276 pthread_cond_broadcast(&submission->queue->device->timeline_cond);
4277 }
4278
4279 static VkResult
4280 radv_queue_submit_deferred(struct radv_deferred_queue_submission *submission,
4281 struct list_head *processing_list)
4282 {
4283 RADV_FROM_HANDLE(radv_fence, fence, submission->fence);
4284 struct radv_queue *queue = submission->queue;
4285 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4286 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
4287 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
4288 bool do_flush = submission->flush_caches || submission->wait_dst_stage_mask;
4289 bool can_patch = true;
4290 uint32_t advance;
4291 struct radv_winsys_sem_info sem_info;
4292 VkResult result;
4293 int ret;
4294 struct radeon_cmdbuf *initial_preamble_cs = NULL;
4295 struct radeon_cmdbuf *initial_flush_preamble_cs = NULL;
4296 struct radeon_cmdbuf *continue_preamble_cs = NULL;
4297
4298 result = radv_get_preambles(queue, submission->cmd_buffers,
4299 submission->cmd_buffer_count,
4300 &initial_preamble_cs,
4301 &initial_flush_preamble_cs,
4302 &continue_preamble_cs);
4303 if (result != VK_SUCCESS)
4304 goto fail;
4305
4306 result = radv_alloc_sem_info(queue->device,
4307 &sem_info,
4308 submission->wait_semaphore_count,
4309 submission->wait_semaphores,
4310 submission->wait_values,
4311 submission->signal_semaphore_count,
4312 submission->signal_semaphores,
4313 submission->signal_values,
4314 submission->fence);
4315 if (result != VK_SUCCESS)
4316 goto fail;
4317
4318 for (uint32_t i = 0; i < submission->buffer_bind_count; ++i) {
4319 radv_sparse_buffer_bind_memory(queue->device,
4320 submission->buffer_binds + i);
4321 }
4322
4323 for (uint32_t i = 0; i < submission->image_opaque_bind_count; ++i) {
4324 radv_sparse_image_opaque_bind_memory(queue->device,
4325 submission->image_opaque_binds + i);
4326 }
4327
4328 if (!submission->cmd_buffer_count) {
4329 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
4330 &queue->device->empty_cs[queue->queue_family_index],
4331 1, NULL, NULL,
4332 &sem_info, NULL,
4333 false, base_fence);
4334 if (ret) {
4335 radv_loge("failed to submit CS\n");
4336 abort();
4337 }
4338
4339 goto success;
4340 } else {
4341 struct radeon_cmdbuf **cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
4342 (submission->cmd_buffer_count));
4343
4344 for (uint32_t j = 0; j < submission->cmd_buffer_count; j++) {
4345 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, submission->cmd_buffers[j]);
4346 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
4347
4348 cs_array[j] = cmd_buffer->cs;
4349 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
4350 can_patch = false;
4351
4352 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
4353 }
4354
4355 for (uint32_t j = 0; j < submission->cmd_buffer_count; j += advance) {
4356 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
4357 const struct radv_winsys_bo_list *bo_list = NULL;
4358
4359 advance = MIN2(max_cs_submission,
4360 submission->cmd_buffer_count - j);
4361
4362 if (queue->device->trace_bo)
4363 *queue->device->trace_id_ptr = 0;
4364
4365 sem_info.cs_emit_wait = j == 0;
4366 sem_info.cs_emit_signal = j + advance == submission->cmd_buffer_count;
4367
4368 if (unlikely(queue->device->use_global_bo_list)) {
4369 pthread_mutex_lock(&queue->device->bo_list.mutex);
4370 bo_list = &queue->device->bo_list.list;
4371 }
4372
4373 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
4374 advance, initial_preamble, continue_preamble_cs,
4375 &sem_info, bo_list,
4376 can_patch, base_fence);
4377
4378 if (unlikely(queue->device->use_global_bo_list))
4379 pthread_mutex_unlock(&queue->device->bo_list.mutex);
4380
4381 if (ret) {
4382 radv_loge("failed to submit CS\n");
4383 abort();
4384 }
4385 if (queue->device->trace_bo) {
4386 radv_check_gpu_hangs(queue, cs_array[j]);
4387 }
4388 }
4389
4390 free(cs_array);
4391 }
4392
4393 success:
4394 radv_free_temp_syncobjs(queue->device,
4395 submission->temporary_semaphore_part_count,
4396 submission->temporary_semaphore_parts);
4397 radv_finalize_timelines(queue->device,
4398 submission->wait_semaphore_count,
4399 submission->wait_semaphores,
4400 submission->wait_values,
4401 submission->signal_semaphore_count,
4402 submission->signal_semaphores,
4403 submission->signal_values,
4404 processing_list);
4405 /* Has to happen after timeline finalization to make sure the
4406 * condition variable is only triggered when timelines and queue have
4407 * been updated. */
4408 radv_queue_submission_update_queue(submission, processing_list);
4409 radv_free_sem_info(&sem_info);
4410 free(submission);
4411 return VK_SUCCESS;
4412
4413 fail:
4414 radv_free_temp_syncobjs(queue->device,
4415 submission->temporary_semaphore_part_count,
4416 submission->temporary_semaphore_parts);
4417 free(submission);
4418 return VK_ERROR_DEVICE_LOST;
4419 }
4420
4421 static VkResult
4422 radv_process_submissions(struct list_head *processing_list)
4423 {
4424 while(!list_is_empty(processing_list)) {
4425 struct radv_deferred_queue_submission *submission =
4426 list_first_entry(processing_list, struct radv_deferred_queue_submission, processing_list);
4427 list_del(&submission->processing_list);
4428
4429 VkResult result = radv_queue_submit_deferred(submission, processing_list);
4430 if (result != VK_SUCCESS)
4431 return result;
4432 }
4433 return VK_SUCCESS;
4434 }
4435
4436 static VkResult radv_queue_submit(struct radv_queue *queue,
4437 const struct radv_queue_submission *submission)
4438 {
4439 struct radv_deferred_queue_submission *deferred = NULL;
4440
4441 VkResult result = radv_create_deferred_submission(queue, submission, &deferred);
4442 if (result != VK_SUCCESS)
4443 return result;
4444
4445 struct list_head processing_list;
4446 list_inithead(&processing_list);
4447
4448 radv_queue_enqueue_submission(deferred, &processing_list);
4449 return radv_process_submissions(&processing_list);
4450 }
4451
4452 /* Signals fence as soon as all the work currently put on queue is done. */
4453 static VkResult radv_signal_fence(struct radv_queue *queue,
4454 VkFence fence)
4455 {
4456 return radv_queue_submit(queue, &(struct radv_queue_submission) {
4457 .fence = fence
4458 });
4459 }
4460
4461 static bool radv_submit_has_effects(const VkSubmitInfo *info)
4462 {
4463 return info->commandBufferCount ||
4464 info->waitSemaphoreCount ||
4465 info->signalSemaphoreCount;
4466 }
4467
4468 VkResult radv_QueueSubmit(
4469 VkQueue _queue,
4470 uint32_t submitCount,
4471 const VkSubmitInfo* pSubmits,
4472 VkFence fence)
4473 {
4474 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4475 VkResult result;
4476 uint32_t fence_idx = 0;
4477 bool flushed_caches = false;
4478
4479 if (fence != VK_NULL_HANDLE) {
4480 for (uint32_t i = 0; i < submitCount; ++i)
4481 if (radv_submit_has_effects(pSubmits + i))
4482 fence_idx = i;
4483 } else
4484 fence_idx = UINT32_MAX;
4485
4486 for (uint32_t i = 0; i < submitCount; i++) {
4487 if (!radv_submit_has_effects(pSubmits + i) && fence_idx != i)
4488 continue;
4489
4490 VkPipelineStageFlags wait_dst_stage_mask = 0;
4491 for (unsigned j = 0; j < pSubmits[i].waitSemaphoreCount; ++j) {
4492 wait_dst_stage_mask |= pSubmits[i].pWaitDstStageMask[j];
4493 }
4494
4495 const VkTimelineSemaphoreSubmitInfoKHR *timeline_info =
4496 vk_find_struct_const(pSubmits[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO_KHR);
4497
4498 result = radv_queue_submit(queue, &(struct radv_queue_submission) {
4499 .cmd_buffers = pSubmits[i].pCommandBuffers,
4500 .cmd_buffer_count = pSubmits[i].commandBufferCount,
4501 .wait_dst_stage_mask = wait_dst_stage_mask,
4502 .flush_caches = !flushed_caches,
4503 .wait_semaphores = pSubmits[i].pWaitSemaphores,
4504 .wait_semaphore_count = pSubmits[i].waitSemaphoreCount,
4505 .signal_semaphores = pSubmits[i].pSignalSemaphores,
4506 .signal_semaphore_count = pSubmits[i].signalSemaphoreCount,
4507 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
4508 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
4509 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
4510 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
4511 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
4512 });
4513 if (result != VK_SUCCESS)
4514 return result;
4515
4516 flushed_caches = true;
4517 }
4518
4519 if (fence != VK_NULL_HANDLE && !submitCount) {
4520 result = radv_signal_fence(queue, fence);
4521 if (result != VK_SUCCESS)
4522 return result;
4523 }
4524
4525 return VK_SUCCESS;
4526 }
4527
4528 VkResult radv_QueueWaitIdle(
4529 VkQueue _queue)
4530 {
4531 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4532
4533 pthread_mutex_lock(&queue->pending_mutex);
4534 while (!list_is_empty(&queue->pending_submissions)) {
4535 pthread_cond_wait(&queue->device->timeline_cond, &queue->pending_mutex);
4536 }
4537 pthread_mutex_unlock(&queue->pending_mutex);
4538
4539 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
4540 radv_queue_family_to_ring(queue->queue_family_index),
4541 queue->queue_idx);
4542 return VK_SUCCESS;
4543 }
4544
4545 VkResult radv_DeviceWaitIdle(
4546 VkDevice _device)
4547 {
4548 RADV_FROM_HANDLE(radv_device, device, _device);
4549
4550 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
4551 for (unsigned q = 0; q < device->queue_count[i]; q++) {
4552 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
4553 }
4554 }
4555 return VK_SUCCESS;
4556 }
4557
4558 VkResult radv_EnumerateInstanceExtensionProperties(
4559 const char* pLayerName,
4560 uint32_t* pPropertyCount,
4561 VkExtensionProperties* pProperties)
4562 {
4563 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4564
4565 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
4566 if (radv_supported_instance_extensions.extensions[i]) {
4567 vk_outarray_append(&out, prop) {
4568 *prop = radv_instance_extensions[i];
4569 }
4570 }
4571 }
4572
4573 return vk_outarray_status(&out);
4574 }
4575
4576 VkResult radv_EnumerateDeviceExtensionProperties(
4577 VkPhysicalDevice physicalDevice,
4578 const char* pLayerName,
4579 uint32_t* pPropertyCount,
4580 VkExtensionProperties* pProperties)
4581 {
4582 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
4583 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4584
4585 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
4586 if (device->supported_extensions.extensions[i]) {
4587 vk_outarray_append(&out, prop) {
4588 *prop = radv_device_extensions[i];
4589 }
4590 }
4591 }
4592
4593 return vk_outarray_status(&out);
4594 }
4595
4596 PFN_vkVoidFunction radv_GetInstanceProcAddr(
4597 VkInstance _instance,
4598 const char* pName)
4599 {
4600 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4601 bool unchecked = instance ? instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS : false;
4602
4603 if (unchecked) {
4604 return radv_lookup_entrypoint_unchecked(pName);
4605 } else {
4606 return radv_lookup_entrypoint_checked(pName,
4607 instance ? instance->apiVersion : 0,
4608 instance ? &instance->enabled_extensions : NULL,
4609 NULL);
4610 }
4611 }
4612
4613 /* The loader wants us to expose a second GetInstanceProcAddr function
4614 * to work around certain LD_PRELOAD issues seen in apps.
4615 */
4616 PUBLIC
4617 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4618 VkInstance instance,
4619 const char* pName);
4620
4621 PUBLIC
4622 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4623 VkInstance instance,
4624 const char* pName)
4625 {
4626 return radv_GetInstanceProcAddr(instance, pName);
4627 }
4628
4629 PUBLIC
4630 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
4631 VkInstance _instance,
4632 const char* pName);
4633
4634 PUBLIC
4635 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
4636 VkInstance _instance,
4637 const char* pName)
4638 {
4639 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4640
4641 return radv_lookup_physical_device_entrypoint_checked(pName,
4642 instance ? instance->apiVersion : 0,
4643 instance ? &instance->enabled_extensions : NULL);
4644 }
4645
4646 PFN_vkVoidFunction radv_GetDeviceProcAddr(
4647 VkDevice _device,
4648 const char* pName)
4649 {
4650 RADV_FROM_HANDLE(radv_device, device, _device);
4651 bool unchecked = device ? device->instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS : false;
4652
4653 if (unchecked) {
4654 return radv_lookup_entrypoint_unchecked(pName);
4655 } else {
4656 return radv_lookup_entrypoint_checked(pName,
4657 device->instance->apiVersion,
4658 &device->instance->enabled_extensions,
4659 &device->enabled_extensions);
4660 }
4661 }
4662
4663 bool radv_get_memory_fd(struct radv_device *device,
4664 struct radv_device_memory *memory,
4665 int *pFD)
4666 {
4667 struct radeon_bo_metadata metadata;
4668
4669 if (memory->image) {
4670 radv_init_metadata(device, memory->image, &metadata);
4671 device->ws->buffer_set_metadata(memory->bo, &metadata);
4672 }
4673
4674 return device->ws->buffer_get_fd(device->ws, memory->bo,
4675 pFD);
4676 }
4677
4678
4679 static void radv_free_memory(struct radv_device *device,
4680 const VkAllocationCallbacks* pAllocator,
4681 struct radv_device_memory *mem)
4682 {
4683 if (mem == NULL)
4684 return;
4685
4686 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4687 if (mem->android_hardware_buffer)
4688 AHardwareBuffer_release(mem->android_hardware_buffer);
4689 #endif
4690
4691 if (mem->bo) {
4692 radv_bo_list_remove(device, mem->bo);
4693 device->ws->buffer_destroy(mem->bo);
4694 mem->bo = NULL;
4695 }
4696
4697 vk_free2(&device->alloc, pAllocator, mem);
4698 }
4699
4700 static VkResult radv_alloc_memory(struct radv_device *device,
4701 const VkMemoryAllocateInfo* pAllocateInfo,
4702 const VkAllocationCallbacks* pAllocator,
4703 VkDeviceMemory* pMem)
4704 {
4705 struct radv_device_memory *mem;
4706 VkResult result;
4707 enum radeon_bo_domain domain;
4708 uint32_t flags = 0;
4709 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
4710
4711 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
4712
4713 const VkImportMemoryFdInfoKHR *import_info =
4714 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
4715 const VkMemoryDedicatedAllocateInfo *dedicate_info =
4716 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
4717 const VkExportMemoryAllocateInfo *export_info =
4718 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
4719 const struct VkImportAndroidHardwareBufferInfoANDROID *ahb_import_info =
4720 vk_find_struct_const(pAllocateInfo->pNext,
4721 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID);
4722 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
4723 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
4724
4725 const struct wsi_memory_allocate_info *wsi_info =
4726 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
4727
4728 if (pAllocateInfo->allocationSize == 0 && !ahb_import_info &&
4729 !(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID))) {
4730 /* Apparently, this is allowed */
4731 *pMem = VK_NULL_HANDLE;
4732 return VK_SUCCESS;
4733 }
4734
4735 mem = vk_zalloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
4736 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4737 if (mem == NULL)
4738 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4739
4740 if (wsi_info && wsi_info->implicit_sync)
4741 flags |= RADEON_FLAG_IMPLICIT_SYNC;
4742
4743 if (dedicate_info) {
4744 mem->image = radv_image_from_handle(dedicate_info->image);
4745 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
4746 } else {
4747 mem->image = NULL;
4748 mem->buffer = NULL;
4749 }
4750
4751 float priority_float = 0.5;
4752 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
4753 vk_find_struct_const(pAllocateInfo->pNext,
4754 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
4755 if (priority_ext)
4756 priority_float = priority_ext->priority;
4757
4758 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
4759 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
4760
4761 mem->user_ptr = NULL;
4762 mem->bo = NULL;
4763
4764 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4765 mem->android_hardware_buffer = NULL;
4766 #endif
4767
4768 if (ahb_import_info) {
4769 result = radv_import_ahb_memory(device, mem, priority, ahb_import_info);
4770 if (result != VK_SUCCESS)
4771 goto fail;
4772 } else if(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID)) {
4773 result = radv_create_ahb_memory(device, mem, priority, pAllocateInfo);
4774 if (result != VK_SUCCESS)
4775 goto fail;
4776 } else if (import_info) {
4777 assert(import_info->handleType ==
4778 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4779 import_info->handleType ==
4780 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4781 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
4782 priority, NULL);
4783 if (!mem->bo) {
4784 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
4785 goto fail;
4786 } else {
4787 close(import_info->fd);
4788 }
4789 } else if (host_ptr_info) {
4790 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
4791 assert(radv_is_mem_type_gtt_cached(mem_type_index));
4792 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
4793 pAllocateInfo->allocationSize,
4794 priority);
4795 if (!mem->bo) {
4796 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
4797 goto fail;
4798 } else {
4799 mem->user_ptr = host_ptr_info->pHostPointer;
4800 }
4801 } else {
4802 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
4803 if (radv_is_mem_type_gtt_wc(mem_type_index) ||
4804 radv_is_mem_type_gtt_cached(mem_type_index))
4805 domain = RADEON_DOMAIN_GTT;
4806 else
4807 domain = RADEON_DOMAIN_VRAM;
4808
4809 if (radv_is_mem_type_vram(mem_type_index))
4810 flags |= RADEON_FLAG_NO_CPU_ACCESS;
4811 else
4812 flags |= RADEON_FLAG_CPU_ACCESS;
4813
4814 if (radv_is_mem_type_gtt_wc(mem_type_index))
4815 flags |= RADEON_FLAG_GTT_WC;
4816
4817 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
4818 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
4819 if (device->use_global_bo_list) {
4820 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
4821 }
4822 }
4823
4824 if (radv_is_mem_type_uncached(mem_type_index)) {
4825 assert(device->physical_device->rad_info.has_l2_uncached);
4826 flags |= RADEON_FLAG_VA_UNCACHED;
4827 }
4828
4829 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
4830 domain, flags, priority);
4831
4832 if (!mem->bo) {
4833 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
4834 goto fail;
4835 }
4836 mem->type_index = mem_type_index;
4837 }
4838
4839 result = radv_bo_list_add(device, mem->bo);
4840 if (result != VK_SUCCESS)
4841 goto fail;
4842
4843 *pMem = radv_device_memory_to_handle(mem);
4844
4845 return VK_SUCCESS;
4846
4847 fail:
4848 radv_free_memory(device, pAllocator,mem);
4849 vk_free2(&device->alloc, pAllocator, mem);
4850
4851 return result;
4852 }
4853
4854 VkResult radv_AllocateMemory(
4855 VkDevice _device,
4856 const VkMemoryAllocateInfo* pAllocateInfo,
4857 const VkAllocationCallbacks* pAllocator,
4858 VkDeviceMemory* pMem)
4859 {
4860 RADV_FROM_HANDLE(radv_device, device, _device);
4861 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
4862 }
4863
4864 void radv_FreeMemory(
4865 VkDevice _device,
4866 VkDeviceMemory _mem,
4867 const VkAllocationCallbacks* pAllocator)
4868 {
4869 RADV_FROM_HANDLE(radv_device, device, _device);
4870 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
4871
4872 radv_free_memory(device, pAllocator, mem);
4873 }
4874
4875 VkResult radv_MapMemory(
4876 VkDevice _device,
4877 VkDeviceMemory _memory,
4878 VkDeviceSize offset,
4879 VkDeviceSize size,
4880 VkMemoryMapFlags flags,
4881 void** ppData)
4882 {
4883 RADV_FROM_HANDLE(radv_device, device, _device);
4884 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
4885
4886 if (mem == NULL) {
4887 *ppData = NULL;
4888 return VK_SUCCESS;
4889 }
4890
4891 if (mem->user_ptr)
4892 *ppData = mem->user_ptr;
4893 else
4894 *ppData = device->ws->buffer_map(mem->bo);
4895
4896 if (*ppData) {
4897 *ppData += offset;
4898 return VK_SUCCESS;
4899 }
4900
4901 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
4902 }
4903
4904 void radv_UnmapMemory(
4905 VkDevice _device,
4906 VkDeviceMemory _memory)
4907 {
4908 RADV_FROM_HANDLE(radv_device, device, _device);
4909 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
4910
4911 if (mem == NULL)
4912 return;
4913
4914 if (mem->user_ptr == NULL)
4915 device->ws->buffer_unmap(mem->bo);
4916 }
4917
4918 VkResult radv_FlushMappedMemoryRanges(
4919 VkDevice _device,
4920 uint32_t memoryRangeCount,
4921 const VkMappedMemoryRange* pMemoryRanges)
4922 {
4923 return VK_SUCCESS;
4924 }
4925
4926 VkResult radv_InvalidateMappedMemoryRanges(
4927 VkDevice _device,
4928 uint32_t memoryRangeCount,
4929 const VkMappedMemoryRange* pMemoryRanges)
4930 {
4931 return VK_SUCCESS;
4932 }
4933
4934 void radv_GetBufferMemoryRequirements(
4935 VkDevice _device,
4936 VkBuffer _buffer,
4937 VkMemoryRequirements* pMemoryRequirements)
4938 {
4939 RADV_FROM_HANDLE(radv_device, device, _device);
4940 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4941
4942 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
4943
4944 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4945 pMemoryRequirements->alignment = 4096;
4946 else
4947 pMemoryRequirements->alignment = 16;
4948
4949 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
4950 }
4951
4952 void radv_GetBufferMemoryRequirements2(
4953 VkDevice device,
4954 const VkBufferMemoryRequirementsInfo2 *pInfo,
4955 VkMemoryRequirements2 *pMemoryRequirements)
4956 {
4957 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
4958 &pMemoryRequirements->memoryRequirements);
4959 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4960 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
4961 switch (ext->sType) {
4962 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
4963 VkMemoryDedicatedRequirements *req =
4964 (VkMemoryDedicatedRequirements *) ext;
4965 req->requiresDedicatedAllocation = buffer->shareable;
4966 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
4967 break;
4968 }
4969 default:
4970 break;
4971 }
4972 }
4973 }
4974
4975 void radv_GetImageMemoryRequirements(
4976 VkDevice _device,
4977 VkImage _image,
4978 VkMemoryRequirements* pMemoryRequirements)
4979 {
4980 RADV_FROM_HANDLE(radv_device, device, _device);
4981 RADV_FROM_HANDLE(radv_image, image, _image);
4982
4983 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
4984
4985 pMemoryRequirements->size = image->size;
4986 pMemoryRequirements->alignment = image->alignment;
4987 }
4988
4989 void radv_GetImageMemoryRequirements2(
4990 VkDevice device,
4991 const VkImageMemoryRequirementsInfo2 *pInfo,
4992 VkMemoryRequirements2 *pMemoryRequirements)
4993 {
4994 radv_GetImageMemoryRequirements(device, pInfo->image,
4995 &pMemoryRequirements->memoryRequirements);
4996
4997 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
4998
4999 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5000 switch (ext->sType) {
5001 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5002 VkMemoryDedicatedRequirements *req =
5003 (VkMemoryDedicatedRequirements *) ext;
5004 req->requiresDedicatedAllocation = image->shareable;
5005 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5006 break;
5007 }
5008 default:
5009 break;
5010 }
5011 }
5012 }
5013
5014 void radv_GetImageSparseMemoryRequirements(
5015 VkDevice device,
5016 VkImage image,
5017 uint32_t* pSparseMemoryRequirementCount,
5018 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
5019 {
5020 stub();
5021 }
5022
5023 void radv_GetImageSparseMemoryRequirements2(
5024 VkDevice device,
5025 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
5026 uint32_t* pSparseMemoryRequirementCount,
5027 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
5028 {
5029 stub();
5030 }
5031
5032 void radv_GetDeviceMemoryCommitment(
5033 VkDevice device,
5034 VkDeviceMemory memory,
5035 VkDeviceSize* pCommittedMemoryInBytes)
5036 {
5037 *pCommittedMemoryInBytes = 0;
5038 }
5039
5040 VkResult radv_BindBufferMemory2(VkDevice device,
5041 uint32_t bindInfoCount,
5042 const VkBindBufferMemoryInfo *pBindInfos)
5043 {
5044 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5045 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5046 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
5047
5048 if (mem) {
5049 buffer->bo = mem->bo;
5050 buffer->offset = pBindInfos[i].memoryOffset;
5051 } else {
5052 buffer->bo = NULL;
5053 }
5054 }
5055 return VK_SUCCESS;
5056 }
5057
5058 VkResult radv_BindBufferMemory(
5059 VkDevice device,
5060 VkBuffer buffer,
5061 VkDeviceMemory memory,
5062 VkDeviceSize memoryOffset)
5063 {
5064 const VkBindBufferMemoryInfo info = {
5065 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5066 .buffer = buffer,
5067 .memory = memory,
5068 .memoryOffset = memoryOffset
5069 };
5070
5071 return radv_BindBufferMemory2(device, 1, &info);
5072 }
5073
5074 VkResult radv_BindImageMemory2(VkDevice device,
5075 uint32_t bindInfoCount,
5076 const VkBindImageMemoryInfo *pBindInfos)
5077 {
5078 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5079 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5080 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
5081
5082 if (mem) {
5083 image->bo = mem->bo;
5084 image->offset = pBindInfos[i].memoryOffset;
5085 } else {
5086 image->bo = NULL;
5087 image->offset = 0;
5088 }
5089 }
5090 return VK_SUCCESS;
5091 }
5092
5093
5094 VkResult radv_BindImageMemory(
5095 VkDevice device,
5096 VkImage image,
5097 VkDeviceMemory memory,
5098 VkDeviceSize memoryOffset)
5099 {
5100 const VkBindImageMemoryInfo info = {
5101 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5102 .image = image,
5103 .memory = memory,
5104 .memoryOffset = memoryOffset
5105 };
5106
5107 return radv_BindImageMemory2(device, 1, &info);
5108 }
5109
5110 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo *info)
5111 {
5112 return info->bufferBindCount ||
5113 info->imageOpaqueBindCount ||
5114 info->imageBindCount ||
5115 info->waitSemaphoreCount ||
5116 info->signalSemaphoreCount;
5117 }
5118
5119 VkResult radv_QueueBindSparse(
5120 VkQueue _queue,
5121 uint32_t bindInfoCount,
5122 const VkBindSparseInfo* pBindInfo,
5123 VkFence fence)
5124 {
5125 RADV_FROM_HANDLE(radv_queue, queue, _queue);
5126 VkResult result;
5127 uint32_t fence_idx = 0;
5128
5129 if (fence != VK_NULL_HANDLE) {
5130 for (uint32_t i = 0; i < bindInfoCount; ++i)
5131 if (radv_sparse_bind_has_effects(pBindInfo + i))
5132 fence_idx = i;
5133 } else
5134 fence_idx = UINT32_MAX;
5135
5136 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5137 if (i != fence_idx && !radv_sparse_bind_has_effects(pBindInfo + i))
5138 continue;
5139
5140 const VkTimelineSemaphoreSubmitInfoKHR *timeline_info =
5141 vk_find_struct_const(pBindInfo[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO_KHR);
5142
5143 VkResult result = radv_queue_submit(queue, &(struct radv_queue_submission) {
5144 .buffer_binds = pBindInfo[i].pBufferBinds,
5145 .buffer_bind_count = pBindInfo[i].bufferBindCount,
5146 .image_opaque_binds = pBindInfo[i].pImageOpaqueBinds,
5147 .image_opaque_bind_count = pBindInfo[i].imageOpaqueBindCount,
5148 .wait_semaphores = pBindInfo[i].pWaitSemaphores,
5149 .wait_semaphore_count = pBindInfo[i].waitSemaphoreCount,
5150 .signal_semaphores = pBindInfo[i].pSignalSemaphores,
5151 .signal_semaphore_count = pBindInfo[i].signalSemaphoreCount,
5152 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
5153 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
5154 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
5155 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
5156 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
5157 });
5158
5159 if (result != VK_SUCCESS)
5160 return result;
5161 }
5162
5163 if (fence != VK_NULL_HANDLE && !bindInfoCount) {
5164 result = radv_signal_fence(queue, fence);
5165 if (result != VK_SUCCESS)
5166 return result;
5167 }
5168
5169 return VK_SUCCESS;
5170 }
5171
5172 VkResult radv_CreateFence(
5173 VkDevice _device,
5174 const VkFenceCreateInfo* pCreateInfo,
5175 const VkAllocationCallbacks* pAllocator,
5176 VkFence* pFence)
5177 {
5178 RADV_FROM_HANDLE(radv_device, device, _device);
5179 const VkExportFenceCreateInfo *export =
5180 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
5181 VkExternalFenceHandleTypeFlags handleTypes =
5182 export ? export->handleTypes : 0;
5183
5184 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
5185 sizeof(*fence), 8,
5186 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5187
5188 if (!fence)
5189 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5190
5191 fence->fence_wsi = NULL;
5192 fence->temp_syncobj = 0;
5193 if (device->always_use_syncobj || handleTypes) {
5194 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
5195 if (ret) {
5196 vk_free2(&device->alloc, pAllocator, fence);
5197 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5198 }
5199 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
5200 device->ws->signal_syncobj(device->ws, fence->syncobj);
5201 }
5202 fence->fence = NULL;
5203 } else {
5204 fence->fence = device->ws->create_fence();
5205 if (!fence->fence) {
5206 vk_free2(&device->alloc, pAllocator, fence);
5207 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5208 }
5209 fence->syncobj = 0;
5210 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5211 device->ws->signal_fence(fence->fence);
5212 }
5213
5214 *pFence = radv_fence_to_handle(fence);
5215
5216 return VK_SUCCESS;
5217 }
5218
5219 void radv_DestroyFence(
5220 VkDevice _device,
5221 VkFence _fence,
5222 const VkAllocationCallbacks* pAllocator)
5223 {
5224 RADV_FROM_HANDLE(radv_device, device, _device);
5225 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5226
5227 if (!fence)
5228 return;
5229
5230 if (fence->temp_syncobj)
5231 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
5232 if (fence->syncobj)
5233 device->ws->destroy_syncobj(device->ws, fence->syncobj);
5234 if (fence->fence)
5235 device->ws->destroy_fence(fence->fence);
5236 if (fence->fence_wsi)
5237 fence->fence_wsi->destroy(fence->fence_wsi);
5238 vk_free2(&device->alloc, pAllocator, fence);
5239 }
5240
5241
5242 uint64_t radv_get_current_time(void)
5243 {
5244 struct timespec tv;
5245 clock_gettime(CLOCK_MONOTONIC, &tv);
5246 return tv.tv_nsec + tv.tv_sec*1000000000ull;
5247 }
5248
5249 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
5250 {
5251 uint64_t current_time = radv_get_current_time();
5252
5253 timeout = MIN2(UINT64_MAX - current_time, timeout);
5254
5255 return current_time + timeout;
5256 }
5257
5258
5259 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
5260 uint32_t fenceCount, const VkFence *pFences)
5261 {
5262 for (uint32_t i = 0; i < fenceCount; ++i) {
5263 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5264 if (fence->fence == NULL || fence->syncobj ||
5265 fence->temp_syncobj || fence->fence_wsi ||
5266 (!device->ws->is_fence_waitable(fence->fence)))
5267 return false;
5268 }
5269 return true;
5270 }
5271
5272 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
5273 {
5274 for (uint32_t i = 0; i < fenceCount; ++i) {
5275 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5276 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
5277 return false;
5278 }
5279 return true;
5280 }
5281
5282 VkResult radv_WaitForFences(
5283 VkDevice _device,
5284 uint32_t fenceCount,
5285 const VkFence* pFences,
5286 VkBool32 waitAll,
5287 uint64_t timeout)
5288 {
5289 RADV_FROM_HANDLE(radv_device, device, _device);
5290 timeout = radv_get_absolute_timeout(timeout);
5291
5292 if (device->always_use_syncobj &&
5293 radv_all_fences_syncobj(fenceCount, pFences))
5294 {
5295 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
5296 if (!handles)
5297 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5298
5299 for (uint32_t i = 0; i < fenceCount; ++i) {
5300 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5301 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
5302 }
5303
5304 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
5305
5306 free(handles);
5307 return success ? VK_SUCCESS : VK_TIMEOUT;
5308 }
5309
5310 if (!waitAll && fenceCount > 1) {
5311 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5312 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
5313 uint32_t wait_count = 0;
5314 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
5315 if (!fences)
5316 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5317
5318 for (uint32_t i = 0; i < fenceCount; ++i) {
5319 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5320
5321 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
5322 free(fences);
5323 return VK_SUCCESS;
5324 }
5325
5326 fences[wait_count++] = fence->fence;
5327 }
5328
5329 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
5330 waitAll, timeout - radv_get_current_time());
5331
5332 free(fences);
5333 return success ? VK_SUCCESS : VK_TIMEOUT;
5334 }
5335
5336 while(radv_get_current_time() <= timeout) {
5337 for (uint32_t i = 0; i < fenceCount; ++i) {
5338 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
5339 return VK_SUCCESS;
5340 }
5341 }
5342 return VK_TIMEOUT;
5343 }
5344
5345 for (uint32_t i = 0; i < fenceCount; ++i) {
5346 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5347 bool expired = false;
5348
5349 if (fence->temp_syncobj) {
5350 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
5351 return VK_TIMEOUT;
5352 continue;
5353 }
5354
5355 if (fence->syncobj) {
5356 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
5357 return VK_TIMEOUT;
5358 continue;
5359 }
5360
5361 if (fence->fence) {
5362 if (!device->ws->is_fence_waitable(fence->fence)) {
5363 while(!device->ws->is_fence_waitable(fence->fence) &&
5364 radv_get_current_time() <= timeout)
5365 /* Do nothing */;
5366 }
5367
5368 expired = device->ws->fence_wait(device->ws,
5369 fence->fence,
5370 true, timeout);
5371 if (!expired)
5372 return VK_TIMEOUT;
5373 }
5374
5375 if (fence->fence_wsi) {
5376 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
5377 if (result != VK_SUCCESS)
5378 return result;
5379 }
5380 }
5381
5382 return VK_SUCCESS;
5383 }
5384
5385 VkResult radv_ResetFences(VkDevice _device,
5386 uint32_t fenceCount,
5387 const VkFence *pFences)
5388 {
5389 RADV_FROM_HANDLE(radv_device, device, _device);
5390
5391 for (unsigned i = 0; i < fenceCount; ++i) {
5392 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5393 if (fence->fence)
5394 device->ws->reset_fence(fence->fence);
5395
5396 /* Per spec, we first restore the permanent payload, and then reset, so
5397 * having a temp syncobj should not skip resetting the permanent syncobj. */
5398 if (fence->temp_syncobj) {
5399 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
5400 fence->temp_syncobj = 0;
5401 }
5402
5403 if (fence->syncobj) {
5404 device->ws->reset_syncobj(device->ws, fence->syncobj);
5405 }
5406 }
5407
5408 return VK_SUCCESS;
5409 }
5410
5411 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
5412 {
5413 RADV_FROM_HANDLE(radv_device, device, _device);
5414 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5415
5416 if (fence->temp_syncobj) {
5417 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
5418 return success ? VK_SUCCESS : VK_NOT_READY;
5419 }
5420
5421 if (fence->syncobj) {
5422 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
5423 return success ? VK_SUCCESS : VK_NOT_READY;
5424 }
5425
5426 if (fence->fence) {
5427 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
5428 return VK_NOT_READY;
5429 }
5430 if (fence->fence_wsi) {
5431 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
5432
5433 if (result != VK_SUCCESS) {
5434 if (result == VK_TIMEOUT)
5435 return VK_NOT_READY;
5436 return result;
5437 }
5438 }
5439 return VK_SUCCESS;
5440 }
5441
5442
5443 // Queue semaphore functions
5444
5445 static void
5446 radv_create_timeline(struct radv_timeline *timeline, uint64_t value)
5447 {
5448 timeline->highest_signaled = value;
5449 timeline->highest_submitted = value;
5450 list_inithead(&timeline->points);
5451 list_inithead(&timeline->free_points);
5452 list_inithead(&timeline->waiters);
5453 pthread_mutex_init(&timeline->mutex, NULL);
5454 }
5455
5456 static void
5457 radv_destroy_timeline(struct radv_device *device,
5458 struct radv_timeline *timeline)
5459 {
5460 list_for_each_entry_safe(struct radv_timeline_point, point,
5461 &timeline->free_points, list) {
5462 list_del(&point->list);
5463 device->ws->destroy_syncobj(device->ws, point->syncobj);
5464 free(point);
5465 }
5466 list_for_each_entry_safe(struct radv_timeline_point, point,
5467 &timeline->points, list) {
5468 list_del(&point->list);
5469 device->ws->destroy_syncobj(device->ws, point->syncobj);
5470 free(point);
5471 }
5472 pthread_mutex_destroy(&timeline->mutex);
5473 }
5474
5475 static void
5476 radv_timeline_gc_locked(struct radv_device *device,
5477 struct radv_timeline *timeline)
5478 {
5479 list_for_each_entry_safe(struct radv_timeline_point, point,
5480 &timeline->points, list) {
5481 if (point->wait_count || point->value > timeline->highest_submitted)
5482 return;
5483
5484 if (device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, 0)) {
5485 timeline->highest_signaled = point->value;
5486 list_del(&point->list);
5487 list_add(&point->list, &timeline->free_points);
5488 }
5489 }
5490 }
5491
5492 static struct radv_timeline_point *
5493 radv_timeline_find_point_at_least_locked(struct radv_device *device,
5494 struct radv_timeline *timeline,
5495 uint64_t p)
5496 {
5497 radv_timeline_gc_locked(device, timeline);
5498
5499 if (p <= timeline->highest_signaled)
5500 return NULL;
5501
5502 list_for_each_entry(struct radv_timeline_point, point,
5503 &timeline->points, list) {
5504 if (point->value >= p) {
5505 ++point->wait_count;
5506 return point;
5507 }
5508 }
5509 return NULL;
5510 }
5511
5512 static struct radv_timeline_point *
5513 radv_timeline_add_point_locked(struct radv_device *device,
5514 struct radv_timeline *timeline,
5515 uint64_t p)
5516 {
5517 radv_timeline_gc_locked(device, timeline);
5518
5519 struct radv_timeline_point *ret = NULL;
5520 struct radv_timeline_point *prev = NULL;
5521
5522 if (p <= timeline->highest_signaled)
5523 return NULL;
5524
5525 list_for_each_entry(struct radv_timeline_point, point,
5526 &timeline->points, list) {
5527 if (point->value == p) {
5528 return NULL;
5529 }
5530
5531 if (point->value < p)
5532 prev = point;
5533 }
5534
5535 if (list_is_empty(&timeline->free_points)) {
5536 ret = malloc(sizeof(struct radv_timeline_point));
5537 device->ws->create_syncobj(device->ws, &ret->syncobj);
5538 } else {
5539 ret = list_first_entry(&timeline->free_points, struct radv_timeline_point, list);
5540 list_del(&ret->list);
5541
5542 device->ws->reset_syncobj(device->ws, ret->syncobj);
5543 }
5544
5545 ret->value = p;
5546 ret->wait_count = 1;
5547
5548 if (prev) {
5549 list_add(&ret->list, &prev->list);
5550 } else {
5551 list_addtail(&ret->list, &timeline->points);
5552 }
5553 return ret;
5554 }
5555
5556
5557 static VkResult
5558 radv_timeline_wait_locked(struct radv_device *device,
5559 struct radv_timeline *timeline,
5560 uint64_t value,
5561 uint64_t abs_timeout)
5562 {
5563 while(timeline->highest_submitted < value) {
5564 struct timespec abstime;
5565 timespec_from_nsec(&abstime, abs_timeout);
5566
5567 pthread_cond_timedwait(&device->timeline_cond, &timeline->mutex, &abstime);
5568
5569 if (radv_get_current_time() >= abs_timeout && timeline->highest_submitted < value)
5570 return VK_TIMEOUT;
5571 }
5572
5573 struct radv_timeline_point *point = radv_timeline_find_point_at_least_locked(device, timeline, value);
5574 if (!point)
5575 return VK_SUCCESS;
5576
5577 point->wait_count++;
5578
5579 pthread_mutex_unlock(&timeline->mutex);
5580
5581 bool success = device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, abs_timeout);
5582
5583 pthread_mutex_lock(&timeline->mutex);
5584 point->wait_count--;
5585 return success ? VK_SUCCESS : VK_TIMEOUT;
5586 }
5587
5588 static void
5589 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
5590 struct list_head *processing_list)
5591 {
5592 list_for_each_entry_safe(struct radv_timeline_waiter, waiter,
5593 &timeline->waiters, list) {
5594 if (waiter->value > timeline->highest_submitted)
5595 continue;
5596
5597 if (p_atomic_dec_zero(&waiter->submission->submission_wait_count)) {
5598 list_addtail(&waiter->submission->processing_list, processing_list);
5599 }
5600 list_del(&waiter->list);
5601 }
5602 }
5603
5604 static
5605 void radv_destroy_semaphore_part(struct radv_device *device,
5606 struct radv_semaphore_part *part)
5607 {
5608 switch(part->kind) {
5609 case RADV_SEMAPHORE_NONE:
5610 break;
5611 case RADV_SEMAPHORE_WINSYS:
5612 device->ws->destroy_sem(part->ws_sem);
5613 break;
5614 case RADV_SEMAPHORE_TIMELINE:
5615 radv_destroy_timeline(device, &part->timeline);
5616 break;
5617 case RADV_SEMAPHORE_SYNCOBJ:
5618 device->ws->destroy_syncobj(device->ws, part->syncobj);
5619 break;
5620 }
5621 part->kind = RADV_SEMAPHORE_NONE;
5622 }
5623
5624 static VkSemaphoreTypeKHR
5625 radv_get_semaphore_type(const void *pNext, uint64_t *initial_value)
5626 {
5627 const VkSemaphoreTypeCreateInfoKHR *type_info =
5628 vk_find_struct_const(pNext, SEMAPHORE_TYPE_CREATE_INFO_KHR);
5629
5630 if (!type_info)
5631 return VK_SEMAPHORE_TYPE_BINARY_KHR;
5632
5633 if (initial_value)
5634 *initial_value = type_info->initialValue;
5635 return type_info->semaphoreType;
5636 }
5637
5638 VkResult radv_CreateSemaphore(
5639 VkDevice _device,
5640 const VkSemaphoreCreateInfo* pCreateInfo,
5641 const VkAllocationCallbacks* pAllocator,
5642 VkSemaphore* pSemaphore)
5643 {
5644 RADV_FROM_HANDLE(radv_device, device, _device);
5645 const VkExportSemaphoreCreateInfo *export =
5646 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
5647 VkExternalSemaphoreHandleTypeFlags handleTypes =
5648 export ? export->handleTypes : 0;
5649 uint64_t initial_value = 0;
5650 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pCreateInfo->pNext, &initial_value);
5651
5652 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
5653 sizeof(*sem), 8,
5654 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5655 if (!sem)
5656 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5657
5658 sem->temporary.kind = RADV_SEMAPHORE_NONE;
5659 sem->permanent.kind = RADV_SEMAPHORE_NONE;
5660
5661 if (type == VK_SEMAPHORE_TYPE_TIMELINE_KHR) {
5662 radv_create_timeline(&sem->permanent.timeline, initial_value);
5663 sem->permanent.kind = RADV_SEMAPHORE_TIMELINE;
5664 } else if (device->always_use_syncobj || handleTypes) {
5665 assert (device->physical_device->rad_info.has_syncobj);
5666 int ret = device->ws->create_syncobj(device->ws, &sem->permanent.syncobj);
5667 if (ret) {
5668 vk_free2(&device->alloc, pAllocator, sem);
5669 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5670 }
5671 sem->permanent.kind = RADV_SEMAPHORE_SYNCOBJ;
5672 } else {
5673 sem->permanent.ws_sem = device->ws->create_sem(device->ws);
5674 if (!sem->permanent.ws_sem) {
5675 vk_free2(&device->alloc, pAllocator, sem);
5676 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5677 }
5678 sem->permanent.kind = RADV_SEMAPHORE_WINSYS;
5679 }
5680
5681 *pSemaphore = radv_semaphore_to_handle(sem);
5682 return VK_SUCCESS;
5683 }
5684
5685 void radv_DestroySemaphore(
5686 VkDevice _device,
5687 VkSemaphore _semaphore,
5688 const VkAllocationCallbacks* pAllocator)
5689 {
5690 RADV_FROM_HANDLE(radv_device, device, _device);
5691 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
5692 if (!_semaphore)
5693 return;
5694
5695 radv_destroy_semaphore_part(device, &sem->temporary);
5696 radv_destroy_semaphore_part(device, &sem->permanent);
5697 vk_free2(&device->alloc, pAllocator, sem);
5698 }
5699
5700 VkResult
5701 radv_GetSemaphoreCounterValueKHR(VkDevice _device,
5702 VkSemaphore _semaphore,
5703 uint64_t* pValue)
5704 {
5705 RADV_FROM_HANDLE(radv_device, device, _device);
5706 RADV_FROM_HANDLE(radv_semaphore, semaphore, _semaphore);
5707
5708 struct radv_semaphore_part *part =
5709 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
5710
5711 switch (part->kind) {
5712 case RADV_SEMAPHORE_TIMELINE: {
5713 pthread_mutex_lock(&part->timeline.mutex);
5714 radv_timeline_gc_locked(device, &part->timeline);
5715 *pValue = part->timeline.highest_signaled;
5716 pthread_mutex_unlock(&part->timeline.mutex);
5717 return VK_SUCCESS;
5718 }
5719 case RADV_SEMAPHORE_NONE:
5720 case RADV_SEMAPHORE_SYNCOBJ:
5721 case RADV_SEMAPHORE_WINSYS:
5722 unreachable("Invalid semaphore type");
5723 }
5724 unreachable("Unhandled semaphore type");
5725 }
5726
5727
5728 static VkResult
5729 radv_wait_timelines(struct radv_device *device,
5730 const VkSemaphoreWaitInfoKHR* pWaitInfo,
5731 uint64_t abs_timeout)
5732 {
5733 if ((pWaitInfo->flags & VK_SEMAPHORE_WAIT_ANY_BIT_KHR) && pWaitInfo->semaphoreCount > 1) {
5734 for (;;) {
5735 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
5736 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
5737 pthread_mutex_lock(&semaphore->permanent.timeline.mutex);
5738 VkResult result = radv_timeline_wait_locked(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], 0);
5739 pthread_mutex_unlock(&semaphore->permanent.timeline.mutex);
5740
5741 if (result == VK_SUCCESS)
5742 return VK_SUCCESS;
5743 }
5744 if (radv_get_current_time() > abs_timeout)
5745 return VK_TIMEOUT;
5746 }
5747 }
5748
5749 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
5750 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
5751 pthread_mutex_lock(&semaphore->permanent.timeline.mutex);
5752 VkResult result = radv_timeline_wait_locked(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], abs_timeout);
5753 pthread_mutex_unlock(&semaphore->permanent.timeline.mutex);
5754
5755 if (result != VK_SUCCESS)
5756 return result;
5757 }
5758 return VK_SUCCESS;
5759 }
5760 VkResult
5761 radv_WaitSemaphoresKHR(VkDevice _device,
5762 const VkSemaphoreWaitInfoKHR* pWaitInfo,
5763 uint64_t timeout)
5764 {
5765 RADV_FROM_HANDLE(radv_device, device, _device);
5766 uint64_t abs_timeout = radv_get_absolute_timeout(timeout);
5767 return radv_wait_timelines(device, pWaitInfo, abs_timeout);
5768 }
5769
5770 VkResult
5771 radv_SignalSemaphoreKHR(VkDevice _device,
5772 const VkSemaphoreSignalInfoKHR* pSignalInfo)
5773 {
5774 RADV_FROM_HANDLE(radv_device, device, _device);
5775 RADV_FROM_HANDLE(radv_semaphore, semaphore, pSignalInfo->semaphore);
5776
5777 struct radv_semaphore_part *part =
5778 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
5779
5780 switch(part->kind) {
5781 case RADV_SEMAPHORE_TIMELINE: {
5782 pthread_mutex_lock(&part->timeline.mutex);
5783 radv_timeline_gc_locked(device, &part->timeline);
5784 part->timeline.highest_submitted = MAX2(part->timeline.highest_submitted, pSignalInfo->value);
5785 part->timeline.highest_signaled = MAX2(part->timeline.highest_signaled, pSignalInfo->value);
5786
5787 struct list_head processing_list;
5788 list_inithead(&processing_list);
5789 radv_timeline_trigger_waiters_locked(&part->timeline, &processing_list);
5790 pthread_mutex_unlock(&part->timeline.mutex);
5791
5792 return radv_process_submissions(&processing_list);
5793 }
5794 case RADV_SEMAPHORE_NONE:
5795 case RADV_SEMAPHORE_SYNCOBJ:
5796 case RADV_SEMAPHORE_WINSYS:
5797 unreachable("Invalid semaphore type");
5798 }
5799 return VK_SUCCESS;
5800 }
5801
5802
5803
5804 VkResult radv_CreateEvent(
5805 VkDevice _device,
5806 const VkEventCreateInfo* pCreateInfo,
5807 const VkAllocationCallbacks* pAllocator,
5808 VkEvent* pEvent)
5809 {
5810 RADV_FROM_HANDLE(radv_device, device, _device);
5811 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
5812 sizeof(*event), 8,
5813 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5814
5815 if (!event)
5816 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5817
5818 event->bo = device->ws->buffer_create(device->ws, 8, 8,
5819 RADEON_DOMAIN_GTT,
5820 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
5821 RADV_BO_PRIORITY_FENCE);
5822 if (!event->bo) {
5823 vk_free2(&device->alloc, pAllocator, event);
5824 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5825 }
5826
5827 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
5828
5829 *pEvent = radv_event_to_handle(event);
5830
5831 return VK_SUCCESS;
5832 }
5833
5834 void radv_DestroyEvent(
5835 VkDevice _device,
5836 VkEvent _event,
5837 const VkAllocationCallbacks* pAllocator)
5838 {
5839 RADV_FROM_HANDLE(radv_device, device, _device);
5840 RADV_FROM_HANDLE(radv_event, event, _event);
5841
5842 if (!event)
5843 return;
5844 device->ws->buffer_destroy(event->bo);
5845 vk_free2(&device->alloc, pAllocator, event);
5846 }
5847
5848 VkResult radv_GetEventStatus(
5849 VkDevice _device,
5850 VkEvent _event)
5851 {
5852 RADV_FROM_HANDLE(radv_event, event, _event);
5853
5854 if (*event->map == 1)
5855 return VK_EVENT_SET;
5856 return VK_EVENT_RESET;
5857 }
5858
5859 VkResult radv_SetEvent(
5860 VkDevice _device,
5861 VkEvent _event)
5862 {
5863 RADV_FROM_HANDLE(radv_event, event, _event);
5864 *event->map = 1;
5865
5866 return VK_SUCCESS;
5867 }
5868
5869 VkResult radv_ResetEvent(
5870 VkDevice _device,
5871 VkEvent _event)
5872 {
5873 RADV_FROM_HANDLE(radv_event, event, _event);
5874 *event->map = 0;
5875
5876 return VK_SUCCESS;
5877 }
5878
5879 VkResult radv_CreateBuffer(
5880 VkDevice _device,
5881 const VkBufferCreateInfo* pCreateInfo,
5882 const VkAllocationCallbacks* pAllocator,
5883 VkBuffer* pBuffer)
5884 {
5885 RADV_FROM_HANDLE(radv_device, device, _device);
5886 struct radv_buffer *buffer;
5887
5888 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
5889
5890 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
5891 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5892 if (buffer == NULL)
5893 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5894
5895 buffer->size = pCreateInfo->size;
5896 buffer->usage = pCreateInfo->usage;
5897 buffer->bo = NULL;
5898 buffer->offset = 0;
5899 buffer->flags = pCreateInfo->flags;
5900
5901 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
5902 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
5903
5904 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
5905 buffer->bo = device->ws->buffer_create(device->ws,
5906 align64(buffer->size, 4096),
5907 4096, 0, RADEON_FLAG_VIRTUAL,
5908 RADV_BO_PRIORITY_VIRTUAL);
5909 if (!buffer->bo) {
5910 vk_free2(&device->alloc, pAllocator, buffer);
5911 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5912 }
5913 }
5914
5915 *pBuffer = radv_buffer_to_handle(buffer);
5916
5917 return VK_SUCCESS;
5918 }
5919
5920 void radv_DestroyBuffer(
5921 VkDevice _device,
5922 VkBuffer _buffer,
5923 const VkAllocationCallbacks* pAllocator)
5924 {
5925 RADV_FROM_HANDLE(radv_device, device, _device);
5926 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5927
5928 if (!buffer)
5929 return;
5930
5931 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
5932 device->ws->buffer_destroy(buffer->bo);
5933
5934 vk_free2(&device->alloc, pAllocator, buffer);
5935 }
5936
5937 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
5938 VkDevice device,
5939 const VkBufferDeviceAddressInfoEXT* pInfo)
5940 {
5941 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
5942 return radv_buffer_get_va(buffer->bo) + buffer->offset;
5943 }
5944
5945
5946 static inline unsigned
5947 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
5948 {
5949 if (stencil)
5950 return plane->surface.u.legacy.stencil_tiling_index[level];
5951 else
5952 return plane->surface.u.legacy.tiling_index[level];
5953 }
5954
5955 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
5956 {
5957 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
5958 }
5959
5960 static uint32_t
5961 radv_init_dcc_control_reg(struct radv_device *device,
5962 struct radv_image_view *iview)
5963 {
5964 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
5965 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
5966 unsigned max_compressed_block_size;
5967 unsigned independent_128b_blocks;
5968 unsigned independent_64b_blocks;
5969
5970 if (!radv_dcc_enabled(iview->image, iview->base_mip))
5971 return 0;
5972
5973 if (!device->physical_device->rad_info.has_dedicated_vram) {
5974 /* amdvlk: [min-compressed-block-size] should be set to 32 for
5975 * dGPU and 64 for APU because all of our APUs to date use
5976 * DIMMs which have a request granularity size of 64B while all
5977 * other chips have a 32B request size.
5978 */
5979 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
5980 }
5981
5982 if (device->physical_device->rad_info.chip_class >= GFX10) {
5983 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
5984 independent_64b_blocks = 0;
5985 independent_128b_blocks = 1;
5986 } else {
5987 independent_128b_blocks = 0;
5988
5989 if (iview->image->info.samples > 1) {
5990 if (iview->image->planes[0].surface.bpe == 1)
5991 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
5992 else if (iview->image->planes[0].surface.bpe == 2)
5993 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
5994 }
5995
5996 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
5997 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
5998 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
5999 /* If this DCC image is potentially going to be used in texture
6000 * fetches, we need some special settings.
6001 */
6002 independent_64b_blocks = 1;
6003 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6004 } else {
6005 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6006 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6007 * big as possible for better compression state.
6008 */
6009 independent_64b_blocks = 0;
6010 max_compressed_block_size = max_uncompressed_block_size;
6011 }
6012 }
6013
6014 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
6015 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
6016 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
6017 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
6018 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
6019 }
6020
6021 void
6022 radv_initialise_color_surface(struct radv_device *device,
6023 struct radv_color_buffer_info *cb,
6024 struct radv_image_view *iview)
6025 {
6026 const struct vk_format_description *desc;
6027 unsigned ntype, format, swap, endian;
6028 unsigned blend_clamp = 0, blend_bypass = 0;
6029 uint64_t va;
6030 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
6031 const struct radeon_surf *surf = &plane->surface;
6032
6033 desc = vk_format_description(iview->vk_format);
6034
6035 memset(cb, 0, sizeof(*cb));
6036
6037 /* Intensity is implemented as Red, so treat it that way. */
6038 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
6039
6040 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
6041
6042 cb->cb_color_base = va >> 8;
6043
6044 if (device->physical_device->rad_info.chip_class >= GFX9) {
6045 struct gfx9_surf_meta_flags meta;
6046 if (iview->image->dcc_offset)
6047 meta = surf->u.gfx9.dcc;
6048 else
6049 meta = surf->u.gfx9.cmask;
6050
6051 if (device->physical_device->rad_info.chip_class >= GFX10) {
6052 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6053 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6054 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
6055 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
6056 } else {
6057 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6058 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6059 S_028C74_RB_ALIGNED(meta.rb_aligned) |
6060 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
6061 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
6062 }
6063
6064 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
6065 cb->cb_color_base |= surf->tile_swizzle;
6066 } else {
6067 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
6068 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
6069
6070 cb->cb_color_base += level_info->offset >> 8;
6071 if (level_info->mode == RADEON_SURF_MODE_2D)
6072 cb->cb_color_base |= surf->tile_swizzle;
6073
6074 pitch_tile_max = level_info->nblk_x / 8 - 1;
6075 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
6076 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
6077
6078 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
6079 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
6080 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
6081
6082 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
6083
6084 if (radv_image_has_fmask(iview->image)) {
6085 if (device->physical_device->rad_info.chip_class >= GFX7)
6086 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
6087 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
6088 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
6089 } else {
6090 /* This must be set for fast clear to work without FMASK. */
6091 if (device->physical_device->rad_info.chip_class >= GFX7)
6092 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
6093 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
6094 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
6095 }
6096 }
6097
6098 /* CMASK variables */
6099 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6100 va += iview->image->cmask_offset;
6101 cb->cb_color_cmask = va >> 8;
6102
6103 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6104 va += iview->image->dcc_offset;
6105
6106 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
6107 device->physical_device->rad_info.chip_class <= GFX8)
6108 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
6109
6110 unsigned dcc_tile_swizzle = surf->tile_swizzle;
6111 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
6112
6113 cb->cb_dcc_base = va >> 8;
6114 cb->cb_dcc_base |= dcc_tile_swizzle;
6115
6116 /* GFX10 field has the same base shift as the GFX6 field. */
6117 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6118 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
6119 S_028C6C_SLICE_MAX_GFX10(max_slice);
6120
6121 if (iview->image->info.samples > 1) {
6122 unsigned log_samples = util_logbase2(iview->image->info.samples);
6123
6124 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
6125 S_028C74_NUM_FRAGMENTS(log_samples);
6126 }
6127
6128 if (radv_image_has_fmask(iview->image)) {
6129 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask_offset;
6130 cb->cb_color_fmask = va >> 8;
6131 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
6132 } else {
6133 cb->cb_color_fmask = cb->cb_color_base;
6134 }
6135
6136 ntype = radv_translate_color_numformat(iview->vk_format,
6137 desc,
6138 vk_format_get_first_non_void_channel(iview->vk_format));
6139 format = radv_translate_colorformat(iview->vk_format);
6140 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
6141 radv_finishme("Illegal color\n");
6142 swap = radv_translate_colorswap(iview->vk_format, false);
6143 endian = radv_colorformat_endian_swap(format);
6144
6145 /* blend clamp should be set for all NORM/SRGB types */
6146 if (ntype == V_028C70_NUMBER_UNORM ||
6147 ntype == V_028C70_NUMBER_SNORM ||
6148 ntype == V_028C70_NUMBER_SRGB)
6149 blend_clamp = 1;
6150
6151 /* set blend bypass according to docs if SINT/UINT or
6152 8/24 COLOR variants */
6153 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
6154 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
6155 format == V_028C70_COLOR_X24_8_32_FLOAT) {
6156 blend_clamp = 0;
6157 blend_bypass = 1;
6158 }
6159 #if 0
6160 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
6161 (format == V_028C70_COLOR_8 ||
6162 format == V_028C70_COLOR_8_8 ||
6163 format == V_028C70_COLOR_8_8_8_8))
6164 ->color_is_int8 = true;
6165 #endif
6166 cb->cb_color_info = S_028C70_FORMAT(format) |
6167 S_028C70_COMP_SWAP(swap) |
6168 S_028C70_BLEND_CLAMP(blend_clamp) |
6169 S_028C70_BLEND_BYPASS(blend_bypass) |
6170 S_028C70_SIMPLE_FLOAT(1) |
6171 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
6172 ntype != V_028C70_NUMBER_SNORM &&
6173 ntype != V_028C70_NUMBER_SRGB &&
6174 format != V_028C70_COLOR_8_24 &&
6175 format != V_028C70_COLOR_24_8) |
6176 S_028C70_NUMBER_TYPE(ntype) |
6177 S_028C70_ENDIAN(endian);
6178 if (radv_image_has_fmask(iview->image)) {
6179 cb->cb_color_info |= S_028C70_COMPRESSION(1);
6180 if (device->physical_device->rad_info.chip_class == GFX6) {
6181 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
6182 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
6183 }
6184
6185 if (radv_image_is_tc_compat_cmask(iview->image)) {
6186 /* Allow the texture block to read FMASK directly
6187 * without decompressing it. This bit must be cleared
6188 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6189 * otherwise the operation doesn't happen.
6190 */
6191 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6192
6193 /* Set CMASK into a tiling format that allows the
6194 * texture block to read it.
6195 */
6196 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
6197 }
6198 }
6199
6200 if (radv_image_has_cmask(iview->image) &&
6201 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
6202 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
6203
6204 if (radv_dcc_enabled(iview->image, iview->base_mip))
6205 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
6206
6207 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
6208
6209 /* This must be set for fast clear to work without FMASK. */
6210 if (!radv_image_has_fmask(iview->image) &&
6211 device->physical_device->rad_info.chip_class == GFX6) {
6212 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
6213 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
6214 }
6215
6216 if (device->physical_device->rad_info.chip_class >= GFX9) {
6217 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
6218
6219 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
6220 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
6221 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
6222 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
6223
6224 if (device->physical_device->rad_info.chip_class >= GFX10) {
6225 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
6226
6227 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
6228 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
6229 S_028EE0_RESOURCE_LEVEL(1);
6230 } else {
6231 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
6232 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
6233 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
6234 }
6235
6236 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
6237 S_028C68_MIP0_HEIGHT(height - 1) |
6238 S_028C68_MAX_MIP(iview->image->info.levels - 1);
6239 }
6240 }
6241
6242 static unsigned
6243 radv_calc_decompress_on_z_planes(struct radv_device *device,
6244 struct radv_image_view *iview)
6245 {
6246 unsigned max_zplanes = 0;
6247
6248 assert(radv_image_is_tc_compat_htile(iview->image));
6249
6250 if (device->physical_device->rad_info.chip_class >= GFX9) {
6251 /* Default value for 32-bit depth surfaces. */
6252 max_zplanes = 4;
6253
6254 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
6255 iview->image->info.samples > 1)
6256 max_zplanes = 2;
6257
6258 max_zplanes = max_zplanes + 1;
6259 } else {
6260 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
6261 /* Do not enable Z plane compression for 16-bit depth
6262 * surfaces because isn't supported on GFX8. Only
6263 * 32-bit depth surfaces are supported by the hardware.
6264 * This allows to maintain shader compatibility and to
6265 * reduce the number of depth decompressions.
6266 */
6267 max_zplanes = 1;
6268 } else {
6269 if (iview->image->info.samples <= 1)
6270 max_zplanes = 5;
6271 else if (iview->image->info.samples <= 4)
6272 max_zplanes = 3;
6273 else
6274 max_zplanes = 2;
6275 }
6276 }
6277
6278 return max_zplanes;
6279 }
6280
6281 void
6282 radv_initialise_ds_surface(struct radv_device *device,
6283 struct radv_ds_buffer_info *ds,
6284 struct radv_image_view *iview)
6285 {
6286 unsigned level = iview->base_mip;
6287 unsigned format, stencil_format;
6288 uint64_t va, s_offs, z_offs;
6289 bool stencil_only = false;
6290 const struct radv_image_plane *plane = &iview->image->planes[0];
6291 const struct radeon_surf *surf = &plane->surface;
6292
6293 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
6294
6295 memset(ds, 0, sizeof(*ds));
6296 switch (iview->image->vk_format) {
6297 case VK_FORMAT_D24_UNORM_S8_UINT:
6298 case VK_FORMAT_X8_D24_UNORM_PACK32:
6299 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6300 ds->offset_scale = 2.0f;
6301 break;
6302 case VK_FORMAT_D16_UNORM:
6303 case VK_FORMAT_D16_UNORM_S8_UINT:
6304 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6305 ds->offset_scale = 4.0f;
6306 break;
6307 case VK_FORMAT_D32_SFLOAT:
6308 case VK_FORMAT_D32_SFLOAT_S8_UINT:
6309 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6310 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6311 ds->offset_scale = 1.0f;
6312 break;
6313 case VK_FORMAT_S8_UINT:
6314 stencil_only = true;
6315 break;
6316 default:
6317 break;
6318 }
6319
6320 format = radv_translate_dbformat(iview->image->vk_format);
6321 stencil_format = surf->has_stencil ?
6322 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
6323
6324 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6325 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
6326 S_028008_SLICE_MAX(max_slice);
6327 if (device->physical_device->rad_info.chip_class >= GFX10) {
6328 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
6329 S_028008_SLICE_MAX_HI(max_slice >> 11);
6330 }
6331
6332 ds->db_htile_data_base = 0;
6333 ds->db_htile_surface = 0;
6334
6335 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6336 s_offs = z_offs = va;
6337
6338 if (device->physical_device->rad_info.chip_class >= GFX9) {
6339 assert(surf->u.gfx9.surf_offset == 0);
6340 s_offs += surf->u.gfx9.stencil_offset;
6341
6342 ds->db_z_info = S_028038_FORMAT(format) |
6343 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
6344 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6345 S_028038_MAXMIP(iview->image->info.levels - 1) |
6346 S_028038_ZRANGE_PRECISION(1);
6347 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
6348 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
6349
6350 if (device->physical_device->rad_info.chip_class == GFX9) {
6351 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
6352 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
6353 }
6354
6355 ds->db_depth_view |= S_028008_MIPID(level);
6356 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
6357 S_02801C_Y_MAX(iview->image->info.height - 1);
6358
6359 if (radv_htile_enabled(iview->image, level)) {
6360 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
6361
6362 if (radv_image_is_tc_compat_htile(iview->image)) {
6363 unsigned max_zplanes =
6364 radv_calc_decompress_on_z_planes(device, iview);
6365
6366 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6367
6368 if (device->physical_device->rad_info.chip_class >= GFX10) {
6369 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
6370 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
6371 } else {
6372 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
6373 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
6374 }
6375 }
6376
6377 if (!surf->has_stencil)
6378 /* Use all of the htile_buffer for depth if there's no stencil. */
6379 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
6380 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
6381 iview->image->htile_offset;
6382 ds->db_htile_data_base = va >> 8;
6383 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
6384 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
6385
6386 if (device->physical_device->rad_info.chip_class == GFX9) {
6387 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
6388 }
6389 }
6390 } else {
6391 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
6392
6393 if (stencil_only)
6394 level_info = &surf->u.legacy.stencil_level[level];
6395
6396 z_offs += surf->u.legacy.level[level].offset;
6397 s_offs += surf->u.legacy.stencil_level[level].offset;
6398
6399 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
6400 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
6401 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
6402
6403 if (iview->image->info.samples > 1)
6404 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
6405
6406 if (device->physical_device->rad_info.chip_class >= GFX7) {
6407 struct radeon_info *info = &device->physical_device->rad_info;
6408 unsigned tiling_index = surf->u.legacy.tiling_index[level];
6409 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
6410 unsigned macro_index = surf->u.legacy.macro_tile_index;
6411 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
6412 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
6413 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
6414
6415 if (stencil_only)
6416 tile_mode = stencil_tile_mode;
6417
6418 ds->db_depth_info |=
6419 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
6420 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
6421 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
6422 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
6423 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
6424 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
6425 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
6426 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
6427 } else {
6428 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
6429 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6430 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
6431 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
6432 if (stencil_only)
6433 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6434 }
6435
6436 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
6437 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
6438 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
6439
6440 if (radv_htile_enabled(iview->image, level)) {
6441 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
6442
6443 if (!surf->has_stencil &&
6444 !radv_image_is_tc_compat_htile(iview->image))
6445 /* Use all of the htile_buffer for depth if there's no stencil. */
6446 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
6447
6448 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
6449 iview->image->htile_offset;
6450 ds->db_htile_data_base = va >> 8;
6451 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
6452
6453 if (radv_image_is_tc_compat_htile(iview->image)) {
6454 unsigned max_zplanes =
6455 radv_calc_decompress_on_z_planes(device, iview);
6456
6457 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
6458 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6459 }
6460 }
6461 }
6462
6463 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
6464 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
6465 }
6466
6467 VkResult radv_CreateFramebuffer(
6468 VkDevice _device,
6469 const VkFramebufferCreateInfo* pCreateInfo,
6470 const VkAllocationCallbacks* pAllocator,
6471 VkFramebuffer* pFramebuffer)
6472 {
6473 RADV_FROM_HANDLE(radv_device, device, _device);
6474 struct radv_framebuffer *framebuffer;
6475 const VkFramebufferAttachmentsCreateInfoKHR *imageless_create_info =
6476 vk_find_struct_const(pCreateInfo->pNext,
6477 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO_KHR);
6478
6479 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
6480
6481 size_t size = sizeof(*framebuffer);
6482 if (!imageless_create_info)
6483 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
6484 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
6485 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6486 if (framebuffer == NULL)
6487 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6488
6489 framebuffer->attachment_count = pCreateInfo->attachmentCount;
6490 framebuffer->width = pCreateInfo->width;
6491 framebuffer->height = pCreateInfo->height;
6492 framebuffer->layers = pCreateInfo->layers;
6493 if (imageless_create_info) {
6494 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
6495 const VkFramebufferAttachmentImageInfoKHR *attachment =
6496 imageless_create_info->pAttachmentImageInfos + i;
6497 framebuffer->width = MIN2(framebuffer->width, attachment->width);
6498 framebuffer->height = MIN2(framebuffer->height, attachment->height);
6499 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
6500 }
6501 } else {
6502 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
6503 VkImageView _iview = pCreateInfo->pAttachments[i];
6504 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
6505 framebuffer->attachments[i] = iview;
6506 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
6507 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
6508 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
6509 }
6510 }
6511
6512 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
6513 return VK_SUCCESS;
6514 }
6515
6516 void radv_DestroyFramebuffer(
6517 VkDevice _device,
6518 VkFramebuffer _fb,
6519 const VkAllocationCallbacks* pAllocator)
6520 {
6521 RADV_FROM_HANDLE(radv_device, device, _device);
6522 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
6523
6524 if (!fb)
6525 return;
6526 vk_free2(&device->alloc, pAllocator, fb);
6527 }
6528
6529 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
6530 {
6531 switch (address_mode) {
6532 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
6533 return V_008F30_SQ_TEX_WRAP;
6534 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
6535 return V_008F30_SQ_TEX_MIRROR;
6536 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
6537 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
6538 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
6539 return V_008F30_SQ_TEX_CLAMP_BORDER;
6540 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
6541 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
6542 default:
6543 unreachable("illegal tex wrap mode");
6544 break;
6545 }
6546 }
6547
6548 static unsigned
6549 radv_tex_compare(VkCompareOp op)
6550 {
6551 switch (op) {
6552 case VK_COMPARE_OP_NEVER:
6553 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
6554 case VK_COMPARE_OP_LESS:
6555 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
6556 case VK_COMPARE_OP_EQUAL:
6557 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
6558 case VK_COMPARE_OP_LESS_OR_EQUAL:
6559 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
6560 case VK_COMPARE_OP_GREATER:
6561 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
6562 case VK_COMPARE_OP_NOT_EQUAL:
6563 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
6564 case VK_COMPARE_OP_GREATER_OR_EQUAL:
6565 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
6566 case VK_COMPARE_OP_ALWAYS:
6567 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
6568 default:
6569 unreachable("illegal compare mode");
6570 break;
6571 }
6572 }
6573
6574 static unsigned
6575 radv_tex_filter(VkFilter filter, unsigned max_ansio)
6576 {
6577 switch (filter) {
6578 case VK_FILTER_NEAREST:
6579 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
6580 V_008F38_SQ_TEX_XY_FILTER_POINT);
6581 case VK_FILTER_LINEAR:
6582 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
6583 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
6584 case VK_FILTER_CUBIC_IMG:
6585 default:
6586 fprintf(stderr, "illegal texture filter");
6587 return 0;
6588 }
6589 }
6590
6591 static unsigned
6592 radv_tex_mipfilter(VkSamplerMipmapMode mode)
6593 {
6594 switch (mode) {
6595 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
6596 return V_008F38_SQ_TEX_Z_FILTER_POINT;
6597 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
6598 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
6599 default:
6600 return V_008F38_SQ_TEX_Z_FILTER_NONE;
6601 }
6602 }
6603
6604 static unsigned
6605 radv_tex_bordercolor(VkBorderColor bcolor)
6606 {
6607 switch (bcolor) {
6608 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
6609 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
6610 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
6611 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
6612 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
6613 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
6614 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
6615 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
6616 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
6617 default:
6618 break;
6619 }
6620 return 0;
6621 }
6622
6623 static unsigned
6624 radv_tex_aniso_filter(unsigned filter)
6625 {
6626 if (filter < 2)
6627 return 0;
6628 if (filter < 4)
6629 return 1;
6630 if (filter < 8)
6631 return 2;
6632 if (filter < 16)
6633 return 3;
6634 return 4;
6635 }
6636
6637 static unsigned
6638 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
6639 {
6640 switch (mode) {
6641 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
6642 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
6643 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
6644 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
6645 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
6646 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
6647 default:
6648 break;
6649 }
6650 return 0;
6651 }
6652
6653 static uint32_t
6654 radv_get_max_anisotropy(struct radv_device *device,
6655 const VkSamplerCreateInfo *pCreateInfo)
6656 {
6657 if (device->force_aniso >= 0)
6658 return device->force_aniso;
6659
6660 if (pCreateInfo->anisotropyEnable &&
6661 pCreateInfo->maxAnisotropy > 1.0f)
6662 return (uint32_t)pCreateInfo->maxAnisotropy;
6663
6664 return 0;
6665 }
6666
6667 static void
6668 radv_init_sampler(struct radv_device *device,
6669 struct radv_sampler *sampler,
6670 const VkSamplerCreateInfo *pCreateInfo)
6671 {
6672 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
6673 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
6674 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
6675 device->physical_device->rad_info.chip_class == GFX9;
6676 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
6677
6678 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
6679 vk_find_struct_const(pCreateInfo->pNext,
6680 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
6681 if (sampler_reduction)
6682 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
6683
6684 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
6685 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
6686 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
6687 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
6688 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
6689 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
6690 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
6691 S_008F30_ANISO_BIAS(max_aniso_ratio) |
6692 S_008F30_DISABLE_CUBE_WRAP(0) |
6693 S_008F30_COMPAT_MODE(compat_mode) |
6694 S_008F30_FILTER_MODE(filter_mode));
6695 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
6696 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
6697 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
6698 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
6699 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
6700 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
6701 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
6702 S_008F38_MIP_POINT_PRECLAMP(0));
6703 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
6704 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
6705
6706 if (device->physical_device->rad_info.chip_class >= GFX10) {
6707 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
6708 } else {
6709 sampler->state[2] |=
6710 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
6711 S_008F38_FILTER_PREC_FIX(1) |
6712 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
6713 }
6714 }
6715
6716 VkResult radv_CreateSampler(
6717 VkDevice _device,
6718 const VkSamplerCreateInfo* pCreateInfo,
6719 const VkAllocationCallbacks* pAllocator,
6720 VkSampler* pSampler)
6721 {
6722 RADV_FROM_HANDLE(radv_device, device, _device);
6723 struct radv_sampler *sampler;
6724
6725 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
6726 vk_find_struct_const(pCreateInfo->pNext,
6727 SAMPLER_YCBCR_CONVERSION_INFO);
6728
6729 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
6730
6731 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
6732 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6733 if (!sampler)
6734 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6735
6736 radv_init_sampler(device, sampler, pCreateInfo);
6737
6738 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
6739 *pSampler = radv_sampler_to_handle(sampler);
6740
6741 return VK_SUCCESS;
6742 }
6743
6744 void radv_DestroySampler(
6745 VkDevice _device,
6746 VkSampler _sampler,
6747 const VkAllocationCallbacks* pAllocator)
6748 {
6749 RADV_FROM_HANDLE(radv_device, device, _device);
6750 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
6751
6752 if (!sampler)
6753 return;
6754 vk_free2(&device->alloc, pAllocator, sampler);
6755 }
6756
6757 /* vk_icd.h does not declare this function, so we declare it here to
6758 * suppress Wmissing-prototypes.
6759 */
6760 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
6761 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
6762
6763 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
6764 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
6765 {
6766 /* For the full details on loader interface versioning, see
6767 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
6768 * What follows is a condensed summary, to help you navigate the large and
6769 * confusing official doc.
6770 *
6771 * - Loader interface v0 is incompatible with later versions. We don't
6772 * support it.
6773 *
6774 * - In loader interface v1:
6775 * - The first ICD entrypoint called by the loader is
6776 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
6777 * entrypoint.
6778 * - The ICD must statically expose no other Vulkan symbol unless it is
6779 * linked with -Bsymbolic.
6780 * - Each dispatchable Vulkan handle created by the ICD must be
6781 * a pointer to a struct whose first member is VK_LOADER_DATA. The
6782 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
6783 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
6784 * vkDestroySurfaceKHR(). The ICD must be capable of working with
6785 * such loader-managed surfaces.
6786 *
6787 * - Loader interface v2 differs from v1 in:
6788 * - The first ICD entrypoint called by the loader is
6789 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
6790 * statically expose this entrypoint.
6791 *
6792 * - Loader interface v3 differs from v2 in:
6793 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
6794 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
6795 * because the loader no longer does so.
6796 */
6797 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
6798 return VK_SUCCESS;
6799 }
6800
6801 VkResult radv_GetMemoryFdKHR(VkDevice _device,
6802 const VkMemoryGetFdInfoKHR *pGetFdInfo,
6803 int *pFD)
6804 {
6805 RADV_FROM_HANDLE(radv_device, device, _device);
6806 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
6807
6808 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
6809
6810 /* At the moment, we support only the below handle types. */
6811 assert(pGetFdInfo->handleType ==
6812 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
6813 pGetFdInfo->handleType ==
6814 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
6815
6816 bool ret = radv_get_memory_fd(device, memory, pFD);
6817 if (ret == false)
6818 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6819 return VK_SUCCESS;
6820 }
6821
6822 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
6823 VkExternalMemoryHandleTypeFlagBits handleType,
6824 int fd,
6825 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
6826 {
6827 RADV_FROM_HANDLE(radv_device, device, _device);
6828
6829 switch (handleType) {
6830 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
6831 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
6832 return VK_SUCCESS;
6833
6834 default:
6835 /* The valid usage section for this function says:
6836 *
6837 * "handleType must not be one of the handle types defined as
6838 * opaque."
6839 *
6840 * So opaque handle types fall into the default "unsupported" case.
6841 */
6842 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
6843 }
6844 }
6845
6846 static VkResult radv_import_opaque_fd(struct radv_device *device,
6847 int fd,
6848 uint32_t *syncobj)
6849 {
6850 uint32_t syncobj_handle = 0;
6851 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
6852 if (ret != 0)
6853 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
6854
6855 if (*syncobj)
6856 device->ws->destroy_syncobj(device->ws, *syncobj);
6857
6858 *syncobj = syncobj_handle;
6859 close(fd);
6860
6861 return VK_SUCCESS;
6862 }
6863
6864 static VkResult radv_import_sync_fd(struct radv_device *device,
6865 int fd,
6866 uint32_t *syncobj)
6867 {
6868 /* If we create a syncobj we do it locally so that if we have an error, we don't
6869 * leave a syncobj in an undetermined state in the fence. */
6870 uint32_t syncobj_handle = *syncobj;
6871 if (!syncobj_handle) {
6872 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
6873 if (ret) {
6874 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
6875 }
6876 }
6877
6878 if (fd == -1) {
6879 device->ws->signal_syncobj(device->ws, syncobj_handle);
6880 } else {
6881 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
6882 if (ret != 0)
6883 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
6884 }
6885
6886 *syncobj = syncobj_handle;
6887 if (fd != -1)
6888 close(fd);
6889
6890 return VK_SUCCESS;
6891 }
6892
6893 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
6894 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
6895 {
6896 RADV_FROM_HANDLE(radv_device, device, _device);
6897 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
6898 VkResult result;
6899 struct radv_semaphore_part *dst = NULL;
6900
6901 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
6902 dst = &sem->temporary;
6903 } else {
6904 dst = &sem->permanent;
6905 }
6906
6907 uint32_t syncobj = dst->kind == RADV_SEMAPHORE_SYNCOBJ ? dst->syncobj : 0;
6908
6909 switch(pImportSemaphoreFdInfo->handleType) {
6910 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
6911 result = radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
6912 break;
6913 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
6914 result = radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
6915 break;
6916 default:
6917 unreachable("Unhandled semaphore handle type");
6918 }
6919
6920 if (result == VK_SUCCESS) {
6921 dst->syncobj = syncobj;
6922 dst->kind = RADV_SEMAPHORE_SYNCOBJ;
6923 }
6924
6925 return result;
6926 }
6927
6928 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
6929 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
6930 int *pFd)
6931 {
6932 RADV_FROM_HANDLE(radv_device, device, _device);
6933 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
6934 int ret;
6935 uint32_t syncobj_handle;
6936
6937 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
6938 assert(sem->temporary.kind == RADV_SEMAPHORE_SYNCOBJ);
6939 syncobj_handle = sem->temporary.syncobj;
6940 } else {
6941 assert(sem->permanent.kind == RADV_SEMAPHORE_SYNCOBJ);
6942 syncobj_handle = sem->permanent.syncobj;
6943 }
6944
6945 switch(pGetFdInfo->handleType) {
6946 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
6947 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
6948 break;
6949 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
6950 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
6951 if (!ret) {
6952 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
6953 radv_destroy_semaphore_part(device, &sem->temporary);
6954 } else {
6955 device->ws->reset_syncobj(device->ws, syncobj_handle);
6956 }
6957 }
6958 break;
6959 default:
6960 unreachable("Unhandled semaphore handle type");
6961 }
6962
6963 if (ret)
6964 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
6965 return VK_SUCCESS;
6966 }
6967
6968 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
6969 VkPhysicalDevice physicalDevice,
6970 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
6971 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
6972 {
6973 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
6974 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pExternalSemaphoreInfo->pNext, NULL);
6975
6976 if (type == VK_SEMAPHORE_TYPE_TIMELINE_KHR) {
6977 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
6978 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
6979 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
6980
6981 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
6982 } else if (pdevice->rad_info.has_syncobj_wait_for_submit &&
6983 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
6984 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
6985 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
6986 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
6987 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
6988 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
6989 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
6990 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
6991 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
6992 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
6993 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
6994 } else {
6995 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
6996 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
6997 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
6998 }
6999 }
7000
7001 VkResult radv_ImportFenceFdKHR(VkDevice _device,
7002 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
7003 {
7004 RADV_FROM_HANDLE(radv_device, device, _device);
7005 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
7006 uint32_t *syncobj_dst = NULL;
7007
7008
7009 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
7010 syncobj_dst = &fence->temp_syncobj;
7011 } else {
7012 syncobj_dst = &fence->syncobj;
7013 }
7014
7015 switch(pImportFenceFdInfo->handleType) {
7016 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7017 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
7018 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7019 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
7020 default:
7021 unreachable("Unhandled fence handle type");
7022 }
7023 }
7024
7025 VkResult radv_GetFenceFdKHR(VkDevice _device,
7026 const VkFenceGetFdInfoKHR *pGetFdInfo,
7027 int *pFd)
7028 {
7029 RADV_FROM_HANDLE(radv_device, device, _device);
7030 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
7031 int ret;
7032 uint32_t syncobj_handle;
7033
7034 if (fence->temp_syncobj)
7035 syncobj_handle = fence->temp_syncobj;
7036 else
7037 syncobj_handle = fence->syncobj;
7038
7039 switch(pGetFdInfo->handleType) {
7040 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7041 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
7042 break;
7043 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7044 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
7045 if (!ret) {
7046 if (fence->temp_syncobj) {
7047 close (fence->temp_syncobj);
7048 fence->temp_syncobj = 0;
7049 } else {
7050 device->ws->reset_syncobj(device->ws, syncobj_handle);
7051 }
7052 }
7053 break;
7054 default:
7055 unreachable("Unhandled fence handle type");
7056 }
7057
7058 if (ret)
7059 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7060 return VK_SUCCESS;
7061 }
7062
7063 void radv_GetPhysicalDeviceExternalFenceProperties(
7064 VkPhysicalDevice physicalDevice,
7065 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
7066 VkExternalFenceProperties *pExternalFenceProperties)
7067 {
7068 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7069
7070 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7071 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7072 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
7073 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7074 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7075 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
7076 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7077 } else {
7078 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
7079 pExternalFenceProperties->compatibleHandleTypes = 0;
7080 pExternalFenceProperties->externalFenceFeatures = 0;
7081 }
7082 }
7083
7084 VkResult
7085 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
7086 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
7087 const VkAllocationCallbacks* pAllocator,
7088 VkDebugReportCallbackEXT* pCallback)
7089 {
7090 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7091 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
7092 pCreateInfo, pAllocator, &instance->alloc,
7093 pCallback);
7094 }
7095
7096 void
7097 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
7098 VkDebugReportCallbackEXT _callback,
7099 const VkAllocationCallbacks* pAllocator)
7100 {
7101 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7102 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
7103 _callback, pAllocator, &instance->alloc);
7104 }
7105
7106 void
7107 radv_DebugReportMessageEXT(VkInstance _instance,
7108 VkDebugReportFlagsEXT flags,
7109 VkDebugReportObjectTypeEXT objectType,
7110 uint64_t object,
7111 size_t location,
7112 int32_t messageCode,
7113 const char* pLayerPrefix,
7114 const char* pMessage)
7115 {
7116 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7117 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
7118 object, location, messageCode, pLayerPrefix, pMessage);
7119 }
7120
7121 void
7122 radv_GetDeviceGroupPeerMemoryFeatures(
7123 VkDevice device,
7124 uint32_t heapIndex,
7125 uint32_t localDeviceIndex,
7126 uint32_t remoteDeviceIndex,
7127 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
7128 {
7129 assert(localDeviceIndex == remoteDeviceIndex);
7130
7131 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
7132 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
7133 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
7134 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
7135 }
7136
7137 static const VkTimeDomainEXT radv_time_domains[] = {
7138 VK_TIME_DOMAIN_DEVICE_EXT,
7139 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
7140 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
7141 };
7142
7143 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7144 VkPhysicalDevice physicalDevice,
7145 uint32_t *pTimeDomainCount,
7146 VkTimeDomainEXT *pTimeDomains)
7147 {
7148 int d;
7149 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
7150
7151 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
7152 vk_outarray_append(&out, i) {
7153 *i = radv_time_domains[d];
7154 }
7155 }
7156
7157 return vk_outarray_status(&out);
7158 }
7159
7160 static uint64_t
7161 radv_clock_gettime(clockid_t clock_id)
7162 {
7163 struct timespec current;
7164 int ret;
7165
7166 ret = clock_gettime(clock_id, &current);
7167 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
7168 ret = clock_gettime(CLOCK_MONOTONIC, &current);
7169 if (ret < 0)
7170 return 0;
7171
7172 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
7173 }
7174
7175 VkResult radv_GetCalibratedTimestampsEXT(
7176 VkDevice _device,
7177 uint32_t timestampCount,
7178 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
7179 uint64_t *pTimestamps,
7180 uint64_t *pMaxDeviation)
7181 {
7182 RADV_FROM_HANDLE(radv_device, device, _device);
7183 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
7184 int d;
7185 uint64_t begin, end;
7186 uint64_t max_clock_period = 0;
7187
7188 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7189
7190 for (d = 0; d < timestampCount; d++) {
7191 switch (pTimestampInfos[d].timeDomain) {
7192 case VK_TIME_DOMAIN_DEVICE_EXT:
7193 pTimestamps[d] = device->ws->query_value(device->ws,
7194 RADEON_TIMESTAMP);
7195 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
7196 max_clock_period = MAX2(max_clock_period, device_period);
7197 break;
7198 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
7199 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
7200 max_clock_period = MAX2(max_clock_period, 1);
7201 break;
7202
7203 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
7204 pTimestamps[d] = begin;
7205 break;
7206 default:
7207 pTimestamps[d] = 0;
7208 break;
7209 }
7210 }
7211
7212 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7213
7214 /*
7215 * The maximum deviation is the sum of the interval over which we
7216 * perform the sampling and the maximum period of any sampled
7217 * clock. That's because the maximum skew between any two sampled
7218 * clock edges is when the sampled clock with the largest period is
7219 * sampled at the end of that period but right at the beginning of the
7220 * sampling interval and some other clock is sampled right at the
7221 * begining of its sampling period and right at the end of the
7222 * sampling interval. Let's assume the GPU has the longest clock
7223 * period and that the application is sampling GPU and monotonic:
7224 *
7225 * s e
7226 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
7227 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7228 *
7229 * g
7230 * 0 1 2 3
7231 * GPU -----_____-----_____-----_____-----_____
7232 *
7233 * m
7234 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
7235 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7236 *
7237 * Interval <----------------->
7238 * Deviation <-------------------------->
7239 *
7240 * s = read(raw) 2
7241 * g = read(GPU) 1
7242 * m = read(monotonic) 2
7243 * e = read(raw) b
7244 *
7245 * We round the sample interval up by one tick to cover sampling error
7246 * in the interval clock
7247 */
7248
7249 uint64_t sample_interval = end - begin + 1;
7250
7251 *pMaxDeviation = sample_interval + max_clock_period;
7252
7253 return VK_SUCCESS;
7254 }
7255
7256 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
7257 VkPhysicalDevice physicalDevice,
7258 VkSampleCountFlagBits samples,
7259 VkMultisamplePropertiesEXT* pMultisampleProperties)
7260 {
7261 if (samples & (VK_SAMPLE_COUNT_2_BIT |
7262 VK_SAMPLE_COUNT_4_BIT |
7263 VK_SAMPLE_COUNT_8_BIT)) {
7264 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
7265 } else {
7266 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
7267 }
7268 }