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radv: move shaders related code to radv_shader.c
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "amdgpu_id.h"
43 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
44 #include "ac_llvm_util.h"
45 #include "vk_format.h"
46 #include "sid.h"
47 #include "gfx9d.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static const VkExtensionProperties instance_extensions[] = {
80 {
81 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
82 .specVersion = 25,
83 },
84 #ifdef VK_USE_PLATFORM_XCB_KHR
85 {
86 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
87 .specVersion = 6,
88 },
89 #endif
90 #ifdef VK_USE_PLATFORM_XLIB_KHR
91 {
92 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
93 .specVersion = 6,
94 },
95 #endif
96 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
97 {
98 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
99 .specVersion = 6,
100 },
101 #endif
102 {
103 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
104 .specVersion = 1,
105 },
106 {
107 .extensionName = VK_KHR_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME,
108 .specVersion = 1,
109 },
110 {
111 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_CAPABILITIES_EXTENSION_NAME,
112 .specVersion = 1,
113 },
114 };
115
116 static const VkExtensionProperties common_device_extensions[] = {
117 {
118 .extensionName = VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME,
119 .specVersion = 1,
120 },
121 {
122 .extensionName = VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME,
123 .specVersion = 1,
124 },
125 {
126 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
127 .specVersion = 1,
128 },
129 {
130 .extensionName = VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME,
131 .specVersion = 1,
132 },
133 {
134 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
135 .specVersion = 1,
136 },
137 {
138 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
139 .specVersion = 68,
140 },
141 {
142 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
143 .specVersion = 1,
144 },
145 {
146 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
147 .specVersion = 1,
148 },
149 {
150 .extensionName = VK_KHR_GET_MEMORY_REQUIREMENTS_2_EXTENSION_NAME,
151 .specVersion = 1,
152 },
153 {
154 .extensionName = VK_KHR_DEDICATED_ALLOCATION_EXTENSION_NAME,
155 .specVersion = 1,
156 },
157 {
158 .extensionName = VK_KHR_EXTERNAL_MEMORY_EXTENSION_NAME,
159 .specVersion = 1,
160 },
161 {
162 .extensionName = VK_KHR_EXTERNAL_MEMORY_FD_EXTENSION_NAME,
163 .specVersion = 1,
164 },
165 {
166 .extensionName = VK_KHR_STORAGE_BUFFER_STORAGE_CLASS_EXTENSION_NAME,
167 .specVersion = 1,
168 },
169 {
170 .extensionName = VK_KHR_VARIABLE_POINTERS_EXTENSION_NAME,
171 .specVersion = 1,
172 },
173 };
174 static const VkExtensionProperties ext_sema_device_extensions[] = {
175 {
176 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_EXTENSION_NAME,
177 .specVersion = 1,
178 },
179 {
180 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_FD_EXTENSION_NAME,
181 .specVersion = 1,
182 },
183 {
184 .extensionName = VK_KHX_MULTIVIEW_EXTENSION_NAME,
185 .specVersion = 1,
186 },
187 };
188
189 static VkResult
190 radv_extensions_register(struct radv_instance *instance,
191 struct radv_extensions *extensions,
192 const VkExtensionProperties *new_ext,
193 uint32_t num_ext)
194 {
195 size_t new_size;
196 VkExtensionProperties *new_ptr;
197
198 assert(new_ext && num_ext > 0);
199
200 if (!new_ext)
201 return VK_ERROR_INITIALIZATION_FAILED;
202
203 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
204 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
205 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
206
207 /* Old array continues to be valid, update nothing */
208 if (!new_ptr)
209 return VK_ERROR_OUT_OF_HOST_MEMORY;
210
211 memcpy(&new_ptr[extensions->num_ext], new_ext,
212 num_ext * sizeof(VkExtensionProperties));
213 extensions->ext_array = new_ptr;
214 extensions->num_ext += num_ext;
215
216 return VK_SUCCESS;
217 }
218
219 static void
220 radv_extensions_finish(struct radv_instance *instance,
221 struct radv_extensions *extensions)
222 {
223 assert(extensions);
224
225 if (!extensions)
226 radv_loge("Attemted to free invalid extension struct\n");
227
228 if (extensions->ext_array)
229 vk_free(&instance->alloc, extensions->ext_array);
230 }
231
232 static bool
233 is_extension_enabled(const VkExtensionProperties *extensions,
234 size_t num_ext,
235 const char *name)
236 {
237 assert(extensions && name);
238
239 for (uint32_t i = 0; i < num_ext; i++) {
240 if (strcmp(name, extensions[i].extensionName) == 0)
241 return true;
242 }
243
244 return false;
245 }
246
247 static const char *
248 get_chip_name(enum radeon_family family)
249 {
250 switch (family) {
251 case CHIP_TAHITI: return "AMD RADV TAHITI";
252 case CHIP_PITCAIRN: return "AMD RADV PITCAIRN";
253 case CHIP_VERDE: return "AMD RADV CAPE VERDE";
254 case CHIP_OLAND: return "AMD RADV OLAND";
255 case CHIP_HAINAN: return "AMD RADV HAINAN";
256 case CHIP_BONAIRE: return "AMD RADV BONAIRE";
257 case CHIP_KAVERI: return "AMD RADV KAVERI";
258 case CHIP_KABINI: return "AMD RADV KABINI";
259 case CHIP_HAWAII: return "AMD RADV HAWAII";
260 case CHIP_MULLINS: return "AMD RADV MULLINS";
261 case CHIP_TONGA: return "AMD RADV TONGA";
262 case CHIP_ICELAND: return "AMD RADV ICELAND";
263 case CHIP_CARRIZO: return "AMD RADV CARRIZO";
264 case CHIP_FIJI: return "AMD RADV FIJI";
265 case CHIP_POLARIS10: return "AMD RADV POLARIS10";
266 case CHIP_POLARIS11: return "AMD RADV POLARIS11";
267 case CHIP_POLARIS12: return "AMD RADV POLARIS12";
268 case CHIP_STONEY: return "AMD RADV STONEY";
269 case CHIP_VEGA10: return "AMD RADV VEGA";
270 case CHIP_RAVEN: return "AMD RADV RAVEN";
271 default: return "AMD RADV unknown";
272 }
273 }
274
275 static VkResult
276 radv_physical_device_init(struct radv_physical_device *device,
277 struct radv_instance *instance,
278 drmDevicePtr drm_device)
279 {
280 const char *path = drm_device->nodes[DRM_NODE_RENDER];
281 VkResult result;
282 drmVersionPtr version;
283 int fd;
284
285 fd = open(path, O_RDWR | O_CLOEXEC);
286 if (fd < 0)
287 return VK_ERROR_INCOMPATIBLE_DRIVER;
288
289 version = drmGetVersion(fd);
290 if (!version) {
291 close(fd);
292 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
293 "failed to get version %s: %m", path);
294 }
295
296 if (strcmp(version->name, "amdgpu")) {
297 drmFreeVersion(version);
298 close(fd);
299 return VK_ERROR_INCOMPATIBLE_DRIVER;
300 }
301 drmFreeVersion(version);
302
303 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
304 device->instance = instance;
305 assert(strlen(path) < ARRAY_SIZE(device->path));
306 strncpy(device->path, path, ARRAY_SIZE(device->path));
307
308 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
309 instance->perftest_flags);
310 if (!device->ws) {
311 result = VK_ERROR_INCOMPATIBLE_DRIVER;
312 goto fail;
313 }
314
315 device->local_fd = fd;
316 device->ws->query_info(device->ws, &device->rad_info);
317 result = radv_init_wsi(device);
318 if (result != VK_SUCCESS) {
319 device->ws->destroy(device->ws);
320 goto fail;
321 }
322
323 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
324 radv_finish_wsi(device);
325 device->ws->destroy(device->ws);
326 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
327 "cannot generate UUID");
328 goto fail;
329 }
330
331 result = radv_extensions_register(instance,
332 &device->extensions,
333 common_device_extensions,
334 ARRAY_SIZE(common_device_extensions));
335 if (result != VK_SUCCESS)
336 goto fail;
337
338 if (device->rad_info.has_syncobj) {
339 result = radv_extensions_register(instance,
340 &device->extensions,
341 ext_sema_device_extensions,
342 ARRAY_SIZE(ext_sema_device_extensions));
343 if (result != VK_SUCCESS)
344 goto fail;
345 }
346
347 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
348 device->name = get_chip_name(device->rad_info.family);
349
350 radv_get_driver_uuid(&device->device_uuid);
351 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
352
353 if (device->rad_info.family == CHIP_STONEY ||
354 device->rad_info.chip_class >= GFX9) {
355 device->has_rbplus = true;
356 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
357 }
358
359 return VK_SUCCESS;
360
361 fail:
362 close(fd);
363 return result;
364 }
365
366 static void
367 radv_physical_device_finish(struct radv_physical_device *device)
368 {
369 radv_extensions_finish(device->instance, &device->extensions);
370 radv_finish_wsi(device);
371 device->ws->destroy(device->ws);
372 close(device->local_fd);
373 }
374
375 static void *
376 default_alloc_func(void *pUserData, size_t size, size_t align,
377 VkSystemAllocationScope allocationScope)
378 {
379 return malloc(size);
380 }
381
382 static void *
383 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
384 size_t align, VkSystemAllocationScope allocationScope)
385 {
386 return realloc(pOriginal, size);
387 }
388
389 static void
390 default_free_func(void *pUserData, void *pMemory)
391 {
392 free(pMemory);
393 }
394
395 static const VkAllocationCallbacks default_alloc = {
396 .pUserData = NULL,
397 .pfnAllocation = default_alloc_func,
398 .pfnReallocation = default_realloc_func,
399 .pfnFree = default_free_func,
400 };
401
402 static const struct debug_control radv_debug_options[] = {
403 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
404 {"nodcc", RADV_DEBUG_NO_DCC},
405 {"shaders", RADV_DEBUG_DUMP_SHADERS},
406 {"nocache", RADV_DEBUG_NO_CACHE},
407 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
408 {"nohiz", RADV_DEBUG_NO_HIZ},
409 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
410 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
411 {"allbos", RADV_DEBUG_ALL_BOS},
412 {"noibs", RADV_DEBUG_NO_IBS},
413 {"spirv", RADV_DEBUG_DUMP_SPIRV},
414 {NULL, 0}
415 };
416
417 static const struct debug_control radv_perftest_options[] = {
418 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
419 {"sisched", RADV_PERFTEST_SISCHED},
420 {NULL, 0}
421 };
422
423 VkResult radv_CreateInstance(
424 const VkInstanceCreateInfo* pCreateInfo,
425 const VkAllocationCallbacks* pAllocator,
426 VkInstance* pInstance)
427 {
428 struct radv_instance *instance;
429
430 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
431
432 uint32_t client_version;
433 if (pCreateInfo->pApplicationInfo &&
434 pCreateInfo->pApplicationInfo->apiVersion != 0) {
435 client_version = pCreateInfo->pApplicationInfo->apiVersion;
436 } else {
437 client_version = VK_MAKE_VERSION(1, 0, 0);
438 }
439
440 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
441 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
442 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
443 "Client requested version %d.%d.%d",
444 VK_VERSION_MAJOR(client_version),
445 VK_VERSION_MINOR(client_version),
446 VK_VERSION_PATCH(client_version));
447 }
448
449 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
450 if (!is_extension_enabled(instance_extensions,
451 ARRAY_SIZE(instance_extensions),
452 pCreateInfo->ppEnabledExtensionNames[i]))
453 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
454 }
455
456 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
457 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
458 if (!instance)
459 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
460
461 memset(instance, 0, sizeof(*instance));
462
463 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
464
465 if (pAllocator)
466 instance->alloc = *pAllocator;
467 else
468 instance->alloc = default_alloc;
469
470 instance->apiVersion = client_version;
471 instance->physicalDeviceCount = -1;
472
473 _mesa_locale_init();
474
475 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
476
477 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
478 radv_debug_options);
479
480 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
481 radv_perftest_options);
482
483 *pInstance = radv_instance_to_handle(instance);
484
485 return VK_SUCCESS;
486 }
487
488 void radv_DestroyInstance(
489 VkInstance _instance,
490 const VkAllocationCallbacks* pAllocator)
491 {
492 RADV_FROM_HANDLE(radv_instance, instance, _instance);
493
494 if (!instance)
495 return;
496
497 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
498 radv_physical_device_finish(instance->physicalDevices + i);
499 }
500
501 VG(VALGRIND_DESTROY_MEMPOOL(instance));
502
503 _mesa_locale_fini();
504
505 vk_free(&instance->alloc, instance);
506 }
507
508 static VkResult
509 radv_enumerate_devices(struct radv_instance *instance)
510 {
511 /* TODO: Check for more devices ? */
512 drmDevicePtr devices[8];
513 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
514 int max_devices;
515
516 instance->physicalDeviceCount = 0;
517
518 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
519 if (max_devices < 1)
520 return VK_ERROR_INCOMPATIBLE_DRIVER;
521
522 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
523 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
524 devices[i]->bustype == DRM_BUS_PCI &&
525 devices[i]->deviceinfo.pci->vendor_id == 0x1002) {
526
527 result = radv_physical_device_init(instance->physicalDevices +
528 instance->physicalDeviceCount,
529 instance,
530 devices[i]);
531 if (result == VK_SUCCESS)
532 ++instance->physicalDeviceCount;
533 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
534 break;
535 }
536 }
537 drmFreeDevices(devices, max_devices);
538
539 return result;
540 }
541
542 VkResult radv_EnumeratePhysicalDevices(
543 VkInstance _instance,
544 uint32_t* pPhysicalDeviceCount,
545 VkPhysicalDevice* pPhysicalDevices)
546 {
547 RADV_FROM_HANDLE(radv_instance, instance, _instance);
548 VkResult result;
549
550 if (instance->physicalDeviceCount < 0) {
551 result = radv_enumerate_devices(instance);
552 if (result != VK_SUCCESS &&
553 result != VK_ERROR_INCOMPATIBLE_DRIVER)
554 return result;
555 }
556
557 if (!pPhysicalDevices) {
558 *pPhysicalDeviceCount = instance->physicalDeviceCount;
559 } else {
560 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
561 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
562 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
563 }
564
565 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
566 : VK_SUCCESS;
567 }
568
569 void radv_GetPhysicalDeviceFeatures(
570 VkPhysicalDevice physicalDevice,
571 VkPhysicalDeviceFeatures* pFeatures)
572 {
573 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
574 bool is_gfx9 = pdevice->rad_info.chip_class >= GFX9;
575 memset(pFeatures, 0, sizeof(*pFeatures));
576
577 *pFeatures = (VkPhysicalDeviceFeatures) {
578 .robustBufferAccess = true,
579 .fullDrawIndexUint32 = true,
580 .imageCubeArray = true,
581 .independentBlend = true,
582 .geometryShader = !is_gfx9,
583 .tessellationShader = !is_gfx9,
584 .sampleRateShading = true,
585 .dualSrcBlend = true,
586 .logicOp = true,
587 .multiDrawIndirect = true,
588 .drawIndirectFirstInstance = true,
589 .depthClamp = true,
590 .depthBiasClamp = true,
591 .fillModeNonSolid = true,
592 .depthBounds = true,
593 .wideLines = true,
594 .largePoints = true,
595 .alphaToOne = true,
596 .multiViewport = true,
597 .samplerAnisotropy = true,
598 .textureCompressionETC2 = false,
599 .textureCompressionASTC_LDR = false,
600 .textureCompressionBC = true,
601 .occlusionQueryPrecise = true,
602 .pipelineStatisticsQuery = true,
603 .vertexPipelineStoresAndAtomics = true,
604 .fragmentStoresAndAtomics = true,
605 .shaderTessellationAndGeometryPointSize = true,
606 .shaderImageGatherExtended = true,
607 .shaderStorageImageExtendedFormats = true,
608 .shaderStorageImageMultisample = false,
609 .shaderUniformBufferArrayDynamicIndexing = true,
610 .shaderSampledImageArrayDynamicIndexing = true,
611 .shaderStorageBufferArrayDynamicIndexing = true,
612 .shaderStorageImageArrayDynamicIndexing = true,
613 .shaderStorageImageReadWithoutFormat = true,
614 .shaderStorageImageWriteWithoutFormat = true,
615 .shaderClipDistance = true,
616 .shaderCullDistance = true,
617 .shaderFloat64 = true,
618 .shaderInt64 = true,
619 .shaderInt16 = false,
620 .sparseBinding = true,
621 .variableMultisampleRate = true,
622 .inheritedQueries = true,
623 };
624 }
625
626 void radv_GetPhysicalDeviceFeatures2KHR(
627 VkPhysicalDevice physicalDevice,
628 VkPhysicalDeviceFeatures2KHR *pFeatures)
629 {
630 vk_foreach_struct(ext, pFeatures->pNext) {
631 switch (ext->sType) {
632 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
633 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
634 features->variablePointersStorageBuffer = true;
635 features->variablePointers = false;
636 break;
637 }
638 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX: {
639 VkPhysicalDeviceMultiviewFeaturesKHX *features = (VkPhysicalDeviceMultiviewFeaturesKHX*)ext;
640 features->multiview = true;
641 features->multiviewGeometryShader = true;
642 features->multiviewTessellationShader = true;
643 break;
644 }
645 default:
646 break;
647 }
648 }
649 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
650 }
651
652 void radv_GetPhysicalDeviceProperties(
653 VkPhysicalDevice physicalDevice,
654 VkPhysicalDeviceProperties* pProperties)
655 {
656 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
657 VkSampleCountFlags sample_counts = 0xf;
658
659 /* make sure that the entire descriptor set is addressable with a signed
660 * 32-bit int. So the sum of all limits scaled by descriptor size has to
661 * be at most 2 GiB. the combined image & samples object count as one of
662 * both. This limit is for the pipeline layout, not for the set layout, but
663 * there is no set limit, so we just set a pipeline limit. I don't think
664 * any app is going to hit this soon. */
665 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
666 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
667 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
668 32 /* sampler, largest when combined with image */ +
669 64 /* sampled image */ +
670 64 /* storage image */);
671
672 VkPhysicalDeviceLimits limits = {
673 .maxImageDimension1D = (1 << 14),
674 .maxImageDimension2D = (1 << 14),
675 .maxImageDimension3D = (1 << 11),
676 .maxImageDimensionCube = (1 << 14),
677 .maxImageArrayLayers = (1 << 11),
678 .maxTexelBufferElements = 128 * 1024 * 1024,
679 .maxUniformBufferRange = UINT32_MAX,
680 .maxStorageBufferRange = UINT32_MAX,
681 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
682 .maxMemoryAllocationCount = UINT32_MAX,
683 .maxSamplerAllocationCount = 64 * 1024,
684 .bufferImageGranularity = 64, /* A cache line */
685 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
686 .maxBoundDescriptorSets = MAX_SETS,
687 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
688 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
689 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
690 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
691 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
692 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
693 .maxPerStageResources = max_descriptor_set_size,
694 .maxDescriptorSetSamplers = max_descriptor_set_size,
695 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
696 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
697 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
698 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
699 .maxDescriptorSetSampledImages = max_descriptor_set_size,
700 .maxDescriptorSetStorageImages = max_descriptor_set_size,
701 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
702 .maxVertexInputAttributes = 32,
703 .maxVertexInputBindings = 32,
704 .maxVertexInputAttributeOffset = 2047,
705 .maxVertexInputBindingStride = 2048,
706 .maxVertexOutputComponents = 128,
707 .maxTessellationGenerationLevel = 64,
708 .maxTessellationPatchSize = 32,
709 .maxTessellationControlPerVertexInputComponents = 128,
710 .maxTessellationControlPerVertexOutputComponents = 128,
711 .maxTessellationControlPerPatchOutputComponents = 120,
712 .maxTessellationControlTotalOutputComponents = 4096,
713 .maxTessellationEvaluationInputComponents = 128,
714 .maxTessellationEvaluationOutputComponents = 128,
715 .maxGeometryShaderInvocations = 127,
716 .maxGeometryInputComponents = 64,
717 .maxGeometryOutputComponents = 128,
718 .maxGeometryOutputVertices = 256,
719 .maxGeometryTotalOutputComponents = 1024,
720 .maxFragmentInputComponents = 128,
721 .maxFragmentOutputAttachments = 8,
722 .maxFragmentDualSrcAttachments = 1,
723 .maxFragmentCombinedOutputResources = 8,
724 .maxComputeSharedMemorySize = 32768,
725 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
726 .maxComputeWorkGroupInvocations = 2048,
727 .maxComputeWorkGroupSize = {
728 2048,
729 2048,
730 2048
731 },
732 .subPixelPrecisionBits = 4 /* FIXME */,
733 .subTexelPrecisionBits = 4 /* FIXME */,
734 .mipmapPrecisionBits = 4 /* FIXME */,
735 .maxDrawIndexedIndexValue = UINT32_MAX,
736 .maxDrawIndirectCount = UINT32_MAX,
737 .maxSamplerLodBias = 16,
738 .maxSamplerAnisotropy = 16,
739 .maxViewports = MAX_VIEWPORTS,
740 .maxViewportDimensions = { (1 << 14), (1 << 14) },
741 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
742 .viewportSubPixelBits = 13, /* We take a float? */
743 .minMemoryMapAlignment = 4096, /* A page */
744 .minTexelBufferOffsetAlignment = 1,
745 .minUniformBufferOffsetAlignment = 4,
746 .minStorageBufferOffsetAlignment = 4,
747 .minTexelOffset = -32,
748 .maxTexelOffset = 31,
749 .minTexelGatherOffset = -32,
750 .maxTexelGatherOffset = 31,
751 .minInterpolationOffset = -2,
752 .maxInterpolationOffset = 2,
753 .subPixelInterpolationOffsetBits = 8,
754 .maxFramebufferWidth = (1 << 14),
755 .maxFramebufferHeight = (1 << 14),
756 .maxFramebufferLayers = (1 << 10),
757 .framebufferColorSampleCounts = sample_counts,
758 .framebufferDepthSampleCounts = sample_counts,
759 .framebufferStencilSampleCounts = sample_counts,
760 .framebufferNoAttachmentsSampleCounts = sample_counts,
761 .maxColorAttachments = MAX_RTS,
762 .sampledImageColorSampleCounts = sample_counts,
763 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
764 .sampledImageDepthSampleCounts = sample_counts,
765 .sampledImageStencilSampleCounts = sample_counts,
766 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
767 .maxSampleMaskWords = 1,
768 .timestampComputeAndGraphics = true,
769 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
770 .maxClipDistances = 8,
771 .maxCullDistances = 8,
772 .maxCombinedClipAndCullDistances = 8,
773 .discreteQueuePriorities = 1,
774 .pointSizeRange = { 0.125, 255.875 },
775 .lineWidthRange = { 0.0, 7.9921875 },
776 .pointSizeGranularity = (1.0 / 8.0),
777 .lineWidthGranularity = (1.0 / 128.0),
778 .strictLines = false, /* FINISHME */
779 .standardSampleLocations = true,
780 .optimalBufferCopyOffsetAlignment = 128,
781 .optimalBufferCopyRowPitchAlignment = 128,
782 .nonCoherentAtomSize = 64,
783 };
784
785 *pProperties = (VkPhysicalDeviceProperties) {
786 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
787 .driverVersion = vk_get_driver_version(),
788 .vendorID = 0x1002,
789 .deviceID = pdevice->rad_info.pci_id,
790 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
791 .limits = limits,
792 .sparseProperties = {0},
793 };
794
795 strcpy(pProperties->deviceName, pdevice->name);
796 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
797 }
798
799 void radv_GetPhysicalDeviceProperties2KHR(
800 VkPhysicalDevice physicalDevice,
801 VkPhysicalDeviceProperties2KHR *pProperties)
802 {
803 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
804 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
805
806 vk_foreach_struct(ext, pProperties->pNext) {
807 switch (ext->sType) {
808 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
809 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
810 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
811 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
812 break;
813 }
814 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
815 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
816 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
817 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
818 properties->deviceLUIDValid = false;
819 break;
820 }
821 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX: {
822 VkPhysicalDeviceMultiviewPropertiesKHX *properties = (VkPhysicalDeviceMultiviewPropertiesKHX*)ext;
823 properties->maxMultiviewViewCount = MAX_VIEWS;
824 properties->maxMultiviewInstanceIndex = INT_MAX;
825 break;
826 }
827 default:
828 break;
829 }
830 }
831 }
832
833 static void radv_get_physical_device_queue_family_properties(
834 struct radv_physical_device* pdevice,
835 uint32_t* pCount,
836 VkQueueFamilyProperties** pQueueFamilyProperties)
837 {
838 int num_queue_families = 1;
839 int idx;
840 if (pdevice->rad_info.num_compute_rings > 0 &&
841 pdevice->rad_info.chip_class >= CIK &&
842 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
843 num_queue_families++;
844
845 if (pQueueFamilyProperties == NULL) {
846 *pCount = num_queue_families;
847 return;
848 }
849
850 if (!*pCount)
851 return;
852
853 idx = 0;
854 if (*pCount >= 1) {
855 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
856 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
857 VK_QUEUE_COMPUTE_BIT |
858 VK_QUEUE_TRANSFER_BIT |
859 VK_QUEUE_SPARSE_BINDING_BIT,
860 .queueCount = 1,
861 .timestampValidBits = 64,
862 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
863 };
864 idx++;
865 }
866
867 if (pdevice->rad_info.num_compute_rings > 0 &&
868 pdevice->rad_info.chip_class >= CIK &&
869 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
870 if (*pCount > idx) {
871 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
872 .queueFlags = VK_QUEUE_COMPUTE_BIT |
873 VK_QUEUE_TRANSFER_BIT |
874 VK_QUEUE_SPARSE_BINDING_BIT,
875 .queueCount = pdevice->rad_info.num_compute_rings,
876 .timestampValidBits = 64,
877 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
878 };
879 idx++;
880 }
881 }
882 *pCount = idx;
883 }
884
885 void radv_GetPhysicalDeviceQueueFamilyProperties(
886 VkPhysicalDevice physicalDevice,
887 uint32_t* pCount,
888 VkQueueFamilyProperties* pQueueFamilyProperties)
889 {
890 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
891 if (!pQueueFamilyProperties) {
892 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
893 return;
894 }
895 VkQueueFamilyProperties *properties[] = {
896 pQueueFamilyProperties + 0,
897 pQueueFamilyProperties + 1,
898 pQueueFamilyProperties + 2,
899 };
900 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
901 assert(*pCount <= 3);
902 }
903
904 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
905 VkPhysicalDevice physicalDevice,
906 uint32_t* pCount,
907 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
908 {
909 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
910 if (!pQueueFamilyProperties) {
911 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
912 return;
913 }
914 VkQueueFamilyProperties *properties[] = {
915 &pQueueFamilyProperties[0].queueFamilyProperties,
916 &pQueueFamilyProperties[1].queueFamilyProperties,
917 &pQueueFamilyProperties[2].queueFamilyProperties,
918 };
919 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
920 assert(*pCount <= 3);
921 }
922
923 void radv_GetPhysicalDeviceMemoryProperties(
924 VkPhysicalDevice physicalDevice,
925 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
926 {
927 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
928
929 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
930
931 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
932 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
933 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
934 .heapIndex = RADV_MEM_HEAP_VRAM,
935 };
936 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
937 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
938 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
939 .heapIndex = RADV_MEM_HEAP_GTT,
940 };
941 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
942 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
943 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
944 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
945 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
946 };
947 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
948 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
949 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
950 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
951 .heapIndex = RADV_MEM_HEAP_GTT,
952 };
953
954 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
955 uint64_t visible_vram_size = MIN2(physical_device->rad_info.vram_size,
956 physical_device->rad_info.vram_vis_size);
957
958 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
959 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
960 .size = physical_device->rad_info.vram_size -
961 visible_vram_size,
962 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
963 };
964 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
965 .size = visible_vram_size,
966 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
967 };
968 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
969 .size = physical_device->rad_info.gart_size,
970 .flags = 0,
971 };
972 }
973
974 void radv_GetPhysicalDeviceMemoryProperties2KHR(
975 VkPhysicalDevice physicalDevice,
976 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
977 {
978 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
979 &pMemoryProperties->memoryProperties);
980 }
981
982 static int
983 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
984 int queue_family_index, int idx)
985 {
986 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
987 queue->device = device;
988 queue->queue_family_index = queue_family_index;
989 queue->queue_idx = idx;
990
991 queue->hw_ctx = device->ws->ctx_create(device->ws);
992 if (!queue->hw_ctx)
993 return VK_ERROR_OUT_OF_HOST_MEMORY;
994
995 return VK_SUCCESS;
996 }
997
998 static void
999 radv_queue_finish(struct radv_queue *queue)
1000 {
1001 if (queue->hw_ctx)
1002 queue->device->ws->ctx_destroy(queue->hw_ctx);
1003
1004 if (queue->initial_full_flush_preamble_cs)
1005 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1006 if (queue->initial_preamble_cs)
1007 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1008 if (queue->continue_preamble_cs)
1009 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1010 if (queue->descriptor_bo)
1011 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1012 if (queue->scratch_bo)
1013 queue->device->ws->buffer_destroy(queue->scratch_bo);
1014 if (queue->esgs_ring_bo)
1015 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1016 if (queue->gsvs_ring_bo)
1017 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1018 if (queue->tess_factor_ring_bo)
1019 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
1020 if (queue->tess_offchip_ring_bo)
1021 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
1022 if (queue->compute_scratch_bo)
1023 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1024 }
1025
1026 static void
1027 radv_device_init_gs_info(struct radv_device *device)
1028 {
1029 switch (device->physical_device->rad_info.family) {
1030 case CHIP_OLAND:
1031 case CHIP_HAINAN:
1032 case CHIP_KAVERI:
1033 case CHIP_KABINI:
1034 case CHIP_MULLINS:
1035 case CHIP_ICELAND:
1036 case CHIP_CARRIZO:
1037 case CHIP_STONEY:
1038 device->gs_table_depth = 16;
1039 return;
1040 case CHIP_TAHITI:
1041 case CHIP_PITCAIRN:
1042 case CHIP_VERDE:
1043 case CHIP_BONAIRE:
1044 case CHIP_HAWAII:
1045 case CHIP_TONGA:
1046 case CHIP_FIJI:
1047 case CHIP_POLARIS10:
1048 case CHIP_POLARIS11:
1049 case CHIP_POLARIS12:
1050 case CHIP_VEGA10:
1051 case CHIP_RAVEN:
1052 device->gs_table_depth = 32;
1053 return;
1054 default:
1055 unreachable("unknown GPU");
1056 }
1057 }
1058
1059 VkResult radv_CreateDevice(
1060 VkPhysicalDevice physicalDevice,
1061 const VkDeviceCreateInfo* pCreateInfo,
1062 const VkAllocationCallbacks* pAllocator,
1063 VkDevice* pDevice)
1064 {
1065 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1066 VkResult result;
1067 struct radv_device *device;
1068
1069 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1070 if (!is_extension_enabled(physical_device->extensions.ext_array,
1071 physical_device->extensions.num_ext,
1072 pCreateInfo->ppEnabledExtensionNames[i]))
1073 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1074 }
1075
1076 /* Check enabled features */
1077 if (pCreateInfo->pEnabledFeatures) {
1078 VkPhysicalDeviceFeatures supported_features;
1079 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1080 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1081 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1082 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1083 for (uint32_t i = 0; i < num_features; i++) {
1084 if (enabled_feature[i] && !supported_feature[i])
1085 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1086 }
1087 }
1088
1089 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
1090 sizeof(*device), 8,
1091 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1092 if (!device)
1093 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1094
1095 memset(device, 0, sizeof(*device));
1096
1097 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1098 device->instance = physical_device->instance;
1099 device->physical_device = physical_device;
1100
1101 device->debug_flags = device->instance->debug_flags;
1102
1103 device->ws = physical_device->ws;
1104 if (pAllocator)
1105 device->alloc = *pAllocator;
1106 else
1107 device->alloc = physical_device->instance->alloc;
1108
1109 mtx_init(&device->shader_slab_mutex, mtx_plain);
1110 list_inithead(&device->shader_slabs);
1111
1112 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1113 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1114 uint32_t qfi = queue_create->queueFamilyIndex;
1115
1116 device->queues[qfi] = vk_alloc(&device->alloc,
1117 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1118 if (!device->queues[qfi]) {
1119 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1120 goto fail;
1121 }
1122
1123 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1124
1125 device->queue_count[qfi] = queue_create->queueCount;
1126
1127 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1128 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
1129 if (result != VK_SUCCESS)
1130 goto fail;
1131 }
1132 }
1133
1134 #if HAVE_LLVM < 0x0400
1135 device->llvm_supports_spill = false;
1136 #else
1137 device->llvm_supports_spill = true;
1138 #endif
1139
1140 /* The maximum number of scratch waves. Scratch space isn't divided
1141 * evenly between CUs. The number is only a function of the number of CUs.
1142 * We can decrease the constant to decrease the scratch buffer size.
1143 *
1144 * sctx->scratch_waves must be >= the maximum posible size of
1145 * 1 threadgroup, so that the hw doesn't hang from being unable
1146 * to start any.
1147 *
1148 * The recommended value is 4 per CU at most. Higher numbers don't
1149 * bring much benefit, but they still occupy chip resources (think
1150 * async compute). I've seen ~2% performance difference between 4 and 32.
1151 */
1152 uint32_t max_threads_per_block = 2048;
1153 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1154 max_threads_per_block / 64);
1155
1156 radv_device_init_gs_info(device);
1157
1158 device->tess_offchip_block_dw_size =
1159 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1160 device->has_distributed_tess =
1161 device->physical_device->rad_info.chip_class >= VI &&
1162 device->physical_device->rad_info.max_se >= 2;
1163
1164 result = radv_device_init_meta(device);
1165 if (result != VK_SUCCESS)
1166 goto fail;
1167
1168 radv_device_init_msaa(device);
1169
1170 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1171 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1172 switch (family) {
1173 case RADV_QUEUE_GENERAL:
1174 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1175 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1176 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1177 break;
1178 case RADV_QUEUE_COMPUTE:
1179 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1180 radeon_emit(device->empty_cs[family], 0);
1181 break;
1182 }
1183 device->ws->cs_finalize(device->empty_cs[family]);
1184 }
1185
1186 if (getenv("RADV_TRACE_FILE")) {
1187 if (!radv_init_trace(device))
1188 goto fail;
1189 }
1190
1191 if (device->physical_device->rad_info.chip_class >= CIK)
1192 cik_create_gfx_config(device);
1193
1194 VkPipelineCacheCreateInfo ci;
1195 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1196 ci.pNext = NULL;
1197 ci.flags = 0;
1198 ci.pInitialData = NULL;
1199 ci.initialDataSize = 0;
1200 VkPipelineCache pc;
1201 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1202 &ci, NULL, &pc);
1203 if (result != VK_SUCCESS)
1204 goto fail;
1205
1206 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1207
1208 *pDevice = radv_device_to_handle(device);
1209 return VK_SUCCESS;
1210
1211 fail:
1212 if (device->trace_bo)
1213 device->ws->buffer_destroy(device->trace_bo);
1214
1215 if (device->gfx_init)
1216 device->ws->buffer_destroy(device->gfx_init);
1217
1218 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1219 for (unsigned q = 0; q < device->queue_count[i]; q++)
1220 radv_queue_finish(&device->queues[i][q]);
1221 if (device->queue_count[i])
1222 vk_free(&device->alloc, device->queues[i]);
1223 }
1224
1225 vk_free(&device->alloc, device);
1226 return result;
1227 }
1228
1229 void radv_DestroyDevice(
1230 VkDevice _device,
1231 const VkAllocationCallbacks* pAllocator)
1232 {
1233 RADV_FROM_HANDLE(radv_device, device, _device);
1234
1235 if (!device)
1236 return;
1237
1238 if (device->trace_bo)
1239 device->ws->buffer_destroy(device->trace_bo);
1240
1241 if (device->gfx_init)
1242 device->ws->buffer_destroy(device->gfx_init);
1243
1244 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1245 for (unsigned q = 0; q < device->queue_count[i]; q++)
1246 radv_queue_finish(&device->queues[i][q]);
1247 if (device->queue_count[i])
1248 vk_free(&device->alloc, device->queues[i]);
1249 if (device->empty_cs[i])
1250 device->ws->cs_destroy(device->empty_cs[i]);
1251 }
1252 radv_device_finish_meta(device);
1253
1254 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1255 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1256
1257 radv_destroy_shader_slabs(device);
1258
1259 vk_free(&device->alloc, device);
1260 }
1261
1262 VkResult radv_EnumerateInstanceExtensionProperties(
1263 const char* pLayerName,
1264 uint32_t* pPropertyCount,
1265 VkExtensionProperties* pProperties)
1266 {
1267 if (pProperties == NULL) {
1268 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1269 return VK_SUCCESS;
1270 }
1271
1272 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1273 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1274
1275 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1276 return VK_INCOMPLETE;
1277
1278 return VK_SUCCESS;
1279 }
1280
1281 VkResult radv_EnumerateDeviceExtensionProperties(
1282 VkPhysicalDevice physicalDevice,
1283 const char* pLayerName,
1284 uint32_t* pPropertyCount,
1285 VkExtensionProperties* pProperties)
1286 {
1287 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1288
1289 if (pProperties == NULL) {
1290 *pPropertyCount = pdevice->extensions.num_ext;
1291 return VK_SUCCESS;
1292 }
1293
1294 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1295 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1296
1297 if (*pPropertyCount < pdevice->extensions.num_ext)
1298 return VK_INCOMPLETE;
1299
1300 return VK_SUCCESS;
1301 }
1302
1303 VkResult radv_EnumerateInstanceLayerProperties(
1304 uint32_t* pPropertyCount,
1305 VkLayerProperties* pProperties)
1306 {
1307 if (pProperties == NULL) {
1308 *pPropertyCount = 0;
1309 return VK_SUCCESS;
1310 }
1311
1312 /* None supported at this time */
1313 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1314 }
1315
1316 VkResult radv_EnumerateDeviceLayerProperties(
1317 VkPhysicalDevice physicalDevice,
1318 uint32_t* pPropertyCount,
1319 VkLayerProperties* pProperties)
1320 {
1321 if (pProperties == NULL) {
1322 *pPropertyCount = 0;
1323 return VK_SUCCESS;
1324 }
1325
1326 /* None supported at this time */
1327 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1328 }
1329
1330 void radv_GetDeviceQueue(
1331 VkDevice _device,
1332 uint32_t queueFamilyIndex,
1333 uint32_t queueIndex,
1334 VkQueue* pQueue)
1335 {
1336 RADV_FROM_HANDLE(radv_device, device, _device);
1337
1338 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1339 }
1340
1341 static void
1342 fill_geom_tess_rings(struct radv_queue *queue,
1343 uint32_t *map,
1344 bool add_sample_positions,
1345 uint32_t esgs_ring_size,
1346 struct radeon_winsys_bo *esgs_ring_bo,
1347 uint32_t gsvs_ring_size,
1348 struct radeon_winsys_bo *gsvs_ring_bo,
1349 uint32_t tess_factor_ring_size,
1350 struct radeon_winsys_bo *tess_factor_ring_bo,
1351 uint32_t tess_offchip_ring_size,
1352 struct radeon_winsys_bo *tess_offchip_ring_bo)
1353 {
1354 uint64_t esgs_va = 0, gsvs_va = 0;
1355 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1356 uint32_t *desc = &map[4];
1357
1358 if (esgs_ring_bo)
1359 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1360 if (gsvs_ring_bo)
1361 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1362 if (tess_factor_ring_bo)
1363 tess_factor_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1364 if (tess_offchip_ring_bo)
1365 tess_offchip_va = queue->device->ws->buffer_get_va(tess_offchip_ring_bo);
1366
1367 /* stride 0, num records - size, add tid, swizzle, elsize4,
1368 index stride 64 */
1369 desc[0] = esgs_va;
1370 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1371 S_008F04_STRIDE(0) |
1372 S_008F04_SWIZZLE_ENABLE(true);
1373 desc[2] = esgs_ring_size;
1374 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1375 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1376 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1377 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1378 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1379 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1380 S_008F0C_ELEMENT_SIZE(1) |
1381 S_008F0C_INDEX_STRIDE(3) |
1382 S_008F0C_ADD_TID_ENABLE(true);
1383
1384 desc += 4;
1385 /* GS entry for ES->GS ring */
1386 /* stride 0, num records - size, elsize0,
1387 index stride 0 */
1388 desc[0] = esgs_va;
1389 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1390 S_008F04_STRIDE(0) |
1391 S_008F04_SWIZZLE_ENABLE(false);
1392 desc[2] = esgs_ring_size;
1393 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1394 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1395 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1396 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1397 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1398 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1399 S_008F0C_ELEMENT_SIZE(0) |
1400 S_008F0C_INDEX_STRIDE(0) |
1401 S_008F0C_ADD_TID_ENABLE(false);
1402
1403 desc += 4;
1404 /* VS entry for GS->VS ring */
1405 /* stride 0, num records - size, elsize0,
1406 index stride 0 */
1407 desc[0] = gsvs_va;
1408 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1409 S_008F04_STRIDE(0) |
1410 S_008F04_SWIZZLE_ENABLE(false);
1411 desc[2] = gsvs_ring_size;
1412 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1413 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1414 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1415 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1416 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1417 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1418 S_008F0C_ELEMENT_SIZE(0) |
1419 S_008F0C_INDEX_STRIDE(0) |
1420 S_008F0C_ADD_TID_ENABLE(false);
1421 desc += 4;
1422
1423 /* stride gsvs_itemsize, num records 64
1424 elsize 4, index stride 16 */
1425 /* shader will patch stride and desc[2] */
1426 desc[0] = gsvs_va;
1427 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1428 S_008F04_STRIDE(0) |
1429 S_008F04_SWIZZLE_ENABLE(true);
1430 desc[2] = 0;
1431 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1432 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1433 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1434 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1435 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1436 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1437 S_008F0C_ELEMENT_SIZE(1) |
1438 S_008F0C_INDEX_STRIDE(1) |
1439 S_008F0C_ADD_TID_ENABLE(true);
1440 desc += 4;
1441
1442 desc[0] = tess_factor_va;
1443 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1444 S_008F04_STRIDE(0) |
1445 S_008F04_SWIZZLE_ENABLE(false);
1446 desc[2] = tess_factor_ring_size;
1447 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1448 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1449 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1450 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1451 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1452 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1453 S_008F0C_ELEMENT_SIZE(0) |
1454 S_008F0C_INDEX_STRIDE(0) |
1455 S_008F0C_ADD_TID_ENABLE(false);
1456 desc += 4;
1457
1458 desc[0] = tess_offchip_va;
1459 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1460 S_008F04_STRIDE(0) |
1461 S_008F04_SWIZZLE_ENABLE(false);
1462 desc[2] = tess_offchip_ring_size;
1463 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1464 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1465 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1466 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1467 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1468 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1469 S_008F0C_ELEMENT_SIZE(0) |
1470 S_008F0C_INDEX_STRIDE(0) |
1471 S_008F0C_ADD_TID_ENABLE(false);
1472 desc += 4;
1473
1474 /* add sample positions after all rings */
1475 memcpy(desc, queue->device->sample_locations_1x, 8);
1476 desc += 2;
1477 memcpy(desc, queue->device->sample_locations_2x, 16);
1478 desc += 4;
1479 memcpy(desc, queue->device->sample_locations_4x, 32);
1480 desc += 8;
1481 memcpy(desc, queue->device->sample_locations_8x, 64);
1482 desc += 16;
1483 memcpy(desc, queue->device->sample_locations_16x, 128);
1484 }
1485
1486 static unsigned
1487 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1488 {
1489 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1490 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1491 device->physical_device->rad_info.family != CHIP_STONEY;
1492 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1493 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1494 device->physical_device->rad_info.max_se;
1495 unsigned offchip_granularity;
1496 unsigned hs_offchip_param;
1497 switch (device->tess_offchip_block_dw_size) {
1498 default:
1499 assert(0);
1500 /* fall through */
1501 case 8192:
1502 offchip_granularity = V_03093C_X_8K_DWORDS;
1503 break;
1504 case 4096:
1505 offchip_granularity = V_03093C_X_4K_DWORDS;
1506 break;
1507 }
1508
1509 switch (device->physical_device->rad_info.chip_class) {
1510 case SI:
1511 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1512 break;
1513 case CIK:
1514 case VI:
1515 case GFX9:
1516 default:
1517 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1518 break;
1519 }
1520
1521 *max_offchip_buffers_p = max_offchip_buffers;
1522 if (device->physical_device->rad_info.chip_class >= CIK) {
1523 if (device->physical_device->rad_info.chip_class >= VI)
1524 --max_offchip_buffers;
1525 hs_offchip_param =
1526 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1527 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1528 } else {
1529 hs_offchip_param =
1530 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1531 }
1532 return hs_offchip_param;
1533 }
1534
1535 static VkResult
1536 radv_get_preamble_cs(struct radv_queue *queue,
1537 uint32_t scratch_size,
1538 uint32_t compute_scratch_size,
1539 uint32_t esgs_ring_size,
1540 uint32_t gsvs_ring_size,
1541 bool needs_tess_rings,
1542 bool needs_sample_positions,
1543 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1544 struct radeon_winsys_cs **initial_preamble_cs,
1545 struct radeon_winsys_cs **continue_preamble_cs)
1546 {
1547 struct radeon_winsys_bo *scratch_bo = NULL;
1548 struct radeon_winsys_bo *descriptor_bo = NULL;
1549 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1550 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1551 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1552 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1553 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1554 struct radeon_winsys_cs *dest_cs[3] = {0};
1555 bool add_tess_rings = false, add_sample_positions = false;
1556 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1557 unsigned max_offchip_buffers;
1558 unsigned hs_offchip_param = 0;
1559 if (!queue->has_tess_rings) {
1560 if (needs_tess_rings)
1561 add_tess_rings = true;
1562 }
1563 if (!queue->has_sample_positions) {
1564 if (needs_sample_positions)
1565 add_sample_positions = true;
1566 }
1567 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1568 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1569 &max_offchip_buffers);
1570 tess_offchip_ring_size = max_offchip_buffers *
1571 queue->device->tess_offchip_block_dw_size * 4;
1572
1573 if (scratch_size <= queue->scratch_size &&
1574 compute_scratch_size <= queue->compute_scratch_size &&
1575 esgs_ring_size <= queue->esgs_ring_size &&
1576 gsvs_ring_size <= queue->gsvs_ring_size &&
1577 !add_tess_rings && !add_sample_positions &&
1578 queue->initial_preamble_cs) {
1579 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1580 *initial_preamble_cs = queue->initial_preamble_cs;
1581 *continue_preamble_cs = queue->continue_preamble_cs;
1582 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1583 *continue_preamble_cs = NULL;
1584 return VK_SUCCESS;
1585 }
1586
1587 if (scratch_size > queue->scratch_size) {
1588 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1589 scratch_size,
1590 4096,
1591 RADEON_DOMAIN_VRAM,
1592 RADEON_FLAG_NO_CPU_ACCESS);
1593 if (!scratch_bo)
1594 goto fail;
1595 } else
1596 scratch_bo = queue->scratch_bo;
1597
1598 if (compute_scratch_size > queue->compute_scratch_size) {
1599 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1600 compute_scratch_size,
1601 4096,
1602 RADEON_DOMAIN_VRAM,
1603 RADEON_FLAG_NO_CPU_ACCESS);
1604 if (!compute_scratch_bo)
1605 goto fail;
1606
1607 } else
1608 compute_scratch_bo = queue->compute_scratch_bo;
1609
1610 if (esgs_ring_size > queue->esgs_ring_size) {
1611 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1612 esgs_ring_size,
1613 4096,
1614 RADEON_DOMAIN_VRAM,
1615 RADEON_FLAG_NO_CPU_ACCESS);
1616 if (!esgs_ring_bo)
1617 goto fail;
1618 } else {
1619 esgs_ring_bo = queue->esgs_ring_bo;
1620 esgs_ring_size = queue->esgs_ring_size;
1621 }
1622
1623 if (gsvs_ring_size > queue->gsvs_ring_size) {
1624 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1625 gsvs_ring_size,
1626 4096,
1627 RADEON_DOMAIN_VRAM,
1628 RADEON_FLAG_NO_CPU_ACCESS);
1629 if (!gsvs_ring_bo)
1630 goto fail;
1631 } else {
1632 gsvs_ring_bo = queue->gsvs_ring_bo;
1633 gsvs_ring_size = queue->gsvs_ring_size;
1634 }
1635
1636 if (add_tess_rings) {
1637 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1638 tess_factor_ring_size,
1639 256,
1640 RADEON_DOMAIN_VRAM,
1641 RADEON_FLAG_NO_CPU_ACCESS);
1642 if (!tess_factor_ring_bo)
1643 goto fail;
1644 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1645 tess_offchip_ring_size,
1646 256,
1647 RADEON_DOMAIN_VRAM,
1648 RADEON_FLAG_NO_CPU_ACCESS);
1649 if (!tess_offchip_ring_bo)
1650 goto fail;
1651 } else {
1652 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1653 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1654 }
1655
1656 if (scratch_bo != queue->scratch_bo ||
1657 esgs_ring_bo != queue->esgs_ring_bo ||
1658 gsvs_ring_bo != queue->gsvs_ring_bo ||
1659 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1660 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1661 uint32_t size = 0;
1662 if (gsvs_ring_bo || esgs_ring_bo ||
1663 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1664 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1665 if (add_sample_positions)
1666 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1667 }
1668 else if (scratch_bo)
1669 size = 8; /* 2 dword */
1670
1671 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1672 size,
1673 4096,
1674 RADEON_DOMAIN_VRAM,
1675 RADEON_FLAG_CPU_ACCESS);
1676 if (!descriptor_bo)
1677 goto fail;
1678 } else
1679 descriptor_bo = queue->descriptor_bo;
1680
1681 for(int i = 0; i < 3; ++i) {
1682 struct radeon_winsys_cs *cs = NULL;
1683 cs = queue->device->ws->cs_create(queue->device->ws,
1684 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1685 if (!cs)
1686 goto fail;
1687
1688 dest_cs[i] = cs;
1689
1690 if (scratch_bo)
1691 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1692
1693 if (esgs_ring_bo)
1694 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1695
1696 if (gsvs_ring_bo)
1697 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1698
1699 if (tess_factor_ring_bo)
1700 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1701
1702 if (tess_offchip_ring_bo)
1703 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1704
1705 if (descriptor_bo)
1706 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1707
1708 if (descriptor_bo != queue->descriptor_bo) {
1709 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1710
1711 if (scratch_bo) {
1712 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1713 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1714 S_008F04_SWIZZLE_ENABLE(1);
1715 map[0] = scratch_va;
1716 map[1] = rsrc1;
1717 }
1718
1719 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1720 add_sample_positions)
1721 fill_geom_tess_rings(queue, map, add_sample_positions,
1722 esgs_ring_size, esgs_ring_bo,
1723 gsvs_ring_size, gsvs_ring_bo,
1724 tess_factor_ring_size, tess_factor_ring_bo,
1725 tess_offchip_ring_size, tess_offchip_ring_bo);
1726
1727 queue->device->ws->buffer_unmap(descriptor_bo);
1728 }
1729
1730 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1731 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1732 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1733 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1734 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1735 }
1736
1737 if (esgs_ring_bo || gsvs_ring_bo) {
1738 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1739 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1740 radeon_emit(cs, esgs_ring_size >> 8);
1741 radeon_emit(cs, gsvs_ring_size >> 8);
1742 } else {
1743 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1744 radeon_emit(cs, esgs_ring_size >> 8);
1745 radeon_emit(cs, gsvs_ring_size >> 8);
1746 }
1747 }
1748
1749 if (tess_factor_ring_bo) {
1750 uint64_t tf_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1751 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1752 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1753 S_030938_SIZE(tess_factor_ring_size / 4));
1754 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1755 tf_va >> 8);
1756 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1757 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1758 tf_va >> 40);
1759 }
1760 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1761 } else {
1762 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1763 S_008988_SIZE(tess_factor_ring_size / 4));
1764 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1765 tf_va >> 8);
1766 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1767 hs_offchip_param);
1768 }
1769 }
1770
1771 if (descriptor_bo) {
1772 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1773 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1774 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1775 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1776 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1777 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1778
1779 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1780
1781 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1782 radeon_set_sh_reg_seq(cs, regs[i], 2);
1783 radeon_emit(cs, va);
1784 radeon_emit(cs, va >> 32);
1785 }
1786 }
1787
1788 if (compute_scratch_bo) {
1789 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1790 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1791 S_008F04_SWIZZLE_ENABLE(1);
1792
1793 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1794
1795 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1796 radeon_emit(cs, scratch_va);
1797 radeon_emit(cs, rsrc1);
1798 }
1799
1800 if (i == 0) {
1801 si_cs_emit_cache_flush(cs,
1802 false,
1803 queue->device->physical_device->rad_info.chip_class,
1804 NULL, 0,
1805 queue->queue_family_index == RING_COMPUTE &&
1806 queue->device->physical_device->rad_info.chip_class >= CIK,
1807 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1808 RADV_CMD_FLAG_INV_ICACHE |
1809 RADV_CMD_FLAG_INV_SMEM_L1 |
1810 RADV_CMD_FLAG_INV_VMEM_L1 |
1811 RADV_CMD_FLAG_INV_GLOBAL_L2);
1812 } else if (i == 1) {
1813 si_cs_emit_cache_flush(cs,
1814 false,
1815 queue->device->physical_device->rad_info.chip_class,
1816 NULL, 0,
1817 queue->queue_family_index == RING_COMPUTE &&
1818 queue->device->physical_device->rad_info.chip_class >= CIK,
1819 RADV_CMD_FLAG_INV_ICACHE |
1820 RADV_CMD_FLAG_INV_SMEM_L1 |
1821 RADV_CMD_FLAG_INV_VMEM_L1 |
1822 RADV_CMD_FLAG_INV_GLOBAL_L2);
1823 }
1824
1825 if (!queue->device->ws->cs_finalize(cs))
1826 goto fail;
1827 }
1828
1829 if (queue->initial_full_flush_preamble_cs)
1830 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1831
1832 if (queue->initial_preamble_cs)
1833 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1834
1835 if (queue->continue_preamble_cs)
1836 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1837
1838 queue->initial_full_flush_preamble_cs = dest_cs[0];
1839 queue->initial_preamble_cs = dest_cs[1];
1840 queue->continue_preamble_cs = dest_cs[2];
1841
1842 if (scratch_bo != queue->scratch_bo) {
1843 if (queue->scratch_bo)
1844 queue->device->ws->buffer_destroy(queue->scratch_bo);
1845 queue->scratch_bo = scratch_bo;
1846 queue->scratch_size = scratch_size;
1847 }
1848
1849 if (compute_scratch_bo != queue->compute_scratch_bo) {
1850 if (queue->compute_scratch_bo)
1851 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1852 queue->compute_scratch_bo = compute_scratch_bo;
1853 queue->compute_scratch_size = compute_scratch_size;
1854 }
1855
1856 if (esgs_ring_bo != queue->esgs_ring_bo) {
1857 if (queue->esgs_ring_bo)
1858 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1859 queue->esgs_ring_bo = esgs_ring_bo;
1860 queue->esgs_ring_size = esgs_ring_size;
1861 }
1862
1863 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1864 if (queue->gsvs_ring_bo)
1865 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1866 queue->gsvs_ring_bo = gsvs_ring_bo;
1867 queue->gsvs_ring_size = gsvs_ring_size;
1868 }
1869
1870 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1871 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1872 }
1873
1874 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1875 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1876 queue->has_tess_rings = true;
1877 }
1878
1879 if (descriptor_bo != queue->descriptor_bo) {
1880 if (queue->descriptor_bo)
1881 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1882
1883 queue->descriptor_bo = descriptor_bo;
1884 }
1885
1886 if (add_sample_positions)
1887 queue->has_sample_positions = true;
1888
1889 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1890 *initial_preamble_cs = queue->initial_preamble_cs;
1891 *continue_preamble_cs = queue->continue_preamble_cs;
1892 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1893 *continue_preamble_cs = NULL;
1894 return VK_SUCCESS;
1895 fail:
1896 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1897 if (dest_cs[i])
1898 queue->device->ws->cs_destroy(dest_cs[i]);
1899 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1900 queue->device->ws->buffer_destroy(descriptor_bo);
1901 if (scratch_bo && scratch_bo != queue->scratch_bo)
1902 queue->device->ws->buffer_destroy(scratch_bo);
1903 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1904 queue->device->ws->buffer_destroy(compute_scratch_bo);
1905 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1906 queue->device->ws->buffer_destroy(esgs_ring_bo);
1907 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1908 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1909 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1910 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1911 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1912 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1913 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1914 }
1915
1916 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1917 int num_sems,
1918 const VkSemaphore *sems,
1919 bool reset_temp)
1920 {
1921 int syncobj_idx = 0, sem_idx = 0;
1922
1923 if (num_sems == 0)
1924 return VK_SUCCESS;
1925 for (uint32_t i = 0; i < num_sems; i++) {
1926 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1927
1928 if (sem->temp_syncobj || sem->syncobj)
1929 counts->syncobj_count++;
1930 else
1931 counts->sem_count++;
1932 }
1933
1934 if (counts->syncobj_count) {
1935 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1936 if (!counts->syncobj)
1937 return VK_ERROR_OUT_OF_HOST_MEMORY;
1938 }
1939
1940 if (counts->sem_count) {
1941 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1942 if (!counts->sem) {
1943 free(counts->syncobj);
1944 return VK_ERROR_OUT_OF_HOST_MEMORY;
1945 }
1946 }
1947
1948 for (uint32_t i = 0; i < num_sems; i++) {
1949 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1950
1951 if (sem->temp_syncobj) {
1952 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1953 if (reset_temp) {
1954 /* after we wait on a temp import - drop it */
1955 sem->temp_syncobj = 0;
1956 }
1957 }
1958 else if (sem->syncobj)
1959 counts->syncobj[syncobj_idx++] = sem->syncobj;
1960 else {
1961 assert(sem->sem);
1962 counts->sem[sem_idx++] = sem->sem;
1963 }
1964 }
1965
1966 return VK_SUCCESS;
1967 }
1968
1969 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
1970 {
1971 free(sem_info->wait.syncobj);
1972 free(sem_info->wait.sem);
1973 free(sem_info->signal.syncobj);
1974 free(sem_info->signal.sem);
1975 }
1976
1977 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1978 int num_wait_sems,
1979 const VkSemaphore *wait_sems,
1980 int num_signal_sems,
1981 const VkSemaphore *signal_sems)
1982 {
1983 VkResult ret;
1984 memset(sem_info, 0, sizeof(*sem_info));
1985
1986 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, true);
1987 if (ret)
1988 return ret;
1989 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, false);
1990 if (ret)
1991 radv_free_sem_info(sem_info);
1992
1993 /* caller can override these */
1994 sem_info->cs_emit_wait = true;
1995 sem_info->cs_emit_signal = true;
1996 return ret;
1997 }
1998
1999 VkResult radv_QueueSubmit(
2000 VkQueue _queue,
2001 uint32_t submitCount,
2002 const VkSubmitInfo* pSubmits,
2003 VkFence _fence)
2004 {
2005 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2006 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2007 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2008 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2009 int ret;
2010 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2011 uint32_t scratch_size = 0;
2012 uint32_t compute_scratch_size = 0;
2013 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2014 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2015 VkResult result;
2016 bool fence_emitted = false;
2017 bool tess_rings_needed = false;
2018 bool sample_positions_needed = false;
2019
2020 /* Do this first so failing to allocate scratch buffers can't result in
2021 * partially executed submissions. */
2022 for (uint32_t i = 0; i < submitCount; i++) {
2023 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2024 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2025 pSubmits[i].pCommandBuffers[j]);
2026
2027 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2028 compute_scratch_size = MAX2(compute_scratch_size,
2029 cmd_buffer->compute_scratch_size_needed);
2030 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2031 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2032 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2033 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2034 }
2035 }
2036
2037 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2038 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2039 sample_positions_needed, &initial_flush_preamble_cs,
2040 &initial_preamble_cs, &continue_preamble_cs);
2041 if (result != VK_SUCCESS)
2042 return result;
2043
2044 for (uint32_t i = 0; i < submitCount; i++) {
2045 struct radeon_winsys_cs **cs_array;
2046 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2047 bool can_patch = true;
2048 uint32_t advance;
2049 struct radv_winsys_sem_info sem_info;
2050
2051 result = radv_alloc_sem_info(&sem_info,
2052 pSubmits[i].waitSemaphoreCount,
2053 pSubmits[i].pWaitSemaphores,
2054 pSubmits[i].signalSemaphoreCount,
2055 pSubmits[i].pSignalSemaphores);
2056 if (result != VK_SUCCESS)
2057 return result;
2058
2059 if (!pSubmits[i].commandBufferCount) {
2060 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2061 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2062 &queue->device->empty_cs[queue->queue_family_index],
2063 1, NULL, NULL,
2064 &sem_info,
2065 false, base_fence);
2066 if (ret) {
2067 radv_loge("failed to submit CS %d\n", i);
2068 abort();
2069 }
2070 fence_emitted = true;
2071 }
2072 radv_free_sem_info(&sem_info);
2073 continue;
2074 }
2075
2076 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2077 (pSubmits[i].commandBufferCount));
2078
2079 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2080 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2081 pSubmits[i].pCommandBuffers[j]);
2082 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2083
2084 cs_array[j] = cmd_buffer->cs;
2085 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2086 can_patch = false;
2087 }
2088
2089 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2090 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2091 advance = MIN2(max_cs_submission,
2092 pSubmits[i].commandBufferCount - j);
2093
2094 if (queue->device->trace_bo)
2095 *queue->device->trace_id_ptr = 0;
2096
2097 sem_info.cs_emit_wait = j == 0;
2098 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2099
2100 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2101 advance, initial_preamble, continue_preamble_cs,
2102 &sem_info,
2103 can_patch, base_fence);
2104
2105 if (ret) {
2106 radv_loge("failed to submit CS %d\n", i);
2107 abort();
2108 }
2109 fence_emitted = true;
2110 if (queue->device->trace_bo) {
2111 radv_check_gpu_hangs(queue, cs_array[j]);
2112 }
2113 }
2114
2115 radv_free_sem_info(&sem_info);
2116 free(cs_array);
2117 }
2118
2119 if (fence) {
2120 if (!fence_emitted) {
2121 struct radv_winsys_sem_info sem_info = {0};
2122 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2123 &queue->device->empty_cs[queue->queue_family_index],
2124 1, NULL, NULL, &sem_info,
2125 false, base_fence);
2126 }
2127 fence->submitted = true;
2128 }
2129
2130 return VK_SUCCESS;
2131 }
2132
2133 VkResult radv_QueueWaitIdle(
2134 VkQueue _queue)
2135 {
2136 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2137
2138 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2139 radv_queue_family_to_ring(queue->queue_family_index),
2140 queue->queue_idx);
2141 return VK_SUCCESS;
2142 }
2143
2144 VkResult radv_DeviceWaitIdle(
2145 VkDevice _device)
2146 {
2147 RADV_FROM_HANDLE(radv_device, device, _device);
2148
2149 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2150 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2151 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2152 }
2153 }
2154 return VK_SUCCESS;
2155 }
2156
2157 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2158 VkInstance instance,
2159 const char* pName)
2160 {
2161 return radv_lookup_entrypoint(pName);
2162 }
2163
2164 /* The loader wants us to expose a second GetInstanceProcAddr function
2165 * to work around certain LD_PRELOAD issues seen in apps.
2166 */
2167 PUBLIC
2168 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2169 VkInstance instance,
2170 const char* pName);
2171
2172 PUBLIC
2173 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2174 VkInstance instance,
2175 const char* pName)
2176 {
2177 return radv_GetInstanceProcAddr(instance, pName);
2178 }
2179
2180 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2181 VkDevice device,
2182 const char* pName)
2183 {
2184 return radv_lookup_entrypoint(pName);
2185 }
2186
2187 bool radv_get_memory_fd(struct radv_device *device,
2188 struct radv_device_memory *memory,
2189 int *pFD)
2190 {
2191 struct radeon_bo_metadata metadata;
2192
2193 if (memory->image) {
2194 radv_init_metadata(device, memory->image, &metadata);
2195 device->ws->buffer_set_metadata(memory->bo, &metadata);
2196 }
2197
2198 return device->ws->buffer_get_fd(device->ws, memory->bo,
2199 pFD);
2200 }
2201
2202 VkResult radv_AllocateMemory(
2203 VkDevice _device,
2204 const VkMemoryAllocateInfo* pAllocateInfo,
2205 const VkAllocationCallbacks* pAllocator,
2206 VkDeviceMemory* pMem)
2207 {
2208 RADV_FROM_HANDLE(radv_device, device, _device);
2209 struct radv_device_memory *mem;
2210 VkResult result;
2211 enum radeon_bo_domain domain;
2212 uint32_t flags = 0;
2213
2214 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2215
2216 if (pAllocateInfo->allocationSize == 0) {
2217 /* Apparently, this is allowed */
2218 *pMem = VK_NULL_HANDLE;
2219 return VK_SUCCESS;
2220 }
2221
2222 const VkImportMemoryFdInfoKHR *import_info =
2223 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2224 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2225 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2226
2227 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2228 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2229 if (mem == NULL)
2230 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2231
2232 if (dedicate_info) {
2233 mem->image = radv_image_from_handle(dedicate_info->image);
2234 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2235 } else {
2236 mem->image = NULL;
2237 mem->buffer = NULL;
2238 }
2239
2240 if (import_info) {
2241 assert(import_info->handleType ==
2242 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2243 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2244 NULL, NULL);
2245 if (!mem->bo) {
2246 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2247 goto fail;
2248 } else {
2249 close(import_info->fd);
2250 goto out_success;
2251 }
2252 }
2253
2254 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2255 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2256 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2257 domain = RADEON_DOMAIN_GTT;
2258 else
2259 domain = RADEON_DOMAIN_VRAM;
2260
2261 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2262 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2263 else
2264 flags |= RADEON_FLAG_CPU_ACCESS;
2265
2266 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2267 flags |= RADEON_FLAG_GTT_WC;
2268
2269 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2270 domain, flags);
2271
2272 if (!mem->bo) {
2273 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2274 goto fail;
2275 }
2276 mem->type_index = pAllocateInfo->memoryTypeIndex;
2277 out_success:
2278 *pMem = radv_device_memory_to_handle(mem);
2279
2280 return VK_SUCCESS;
2281
2282 fail:
2283 vk_free2(&device->alloc, pAllocator, mem);
2284
2285 return result;
2286 }
2287
2288 void radv_FreeMemory(
2289 VkDevice _device,
2290 VkDeviceMemory _mem,
2291 const VkAllocationCallbacks* pAllocator)
2292 {
2293 RADV_FROM_HANDLE(radv_device, device, _device);
2294 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2295
2296 if (mem == NULL)
2297 return;
2298
2299 device->ws->buffer_destroy(mem->bo);
2300 mem->bo = NULL;
2301
2302 vk_free2(&device->alloc, pAllocator, mem);
2303 }
2304
2305 VkResult radv_MapMemory(
2306 VkDevice _device,
2307 VkDeviceMemory _memory,
2308 VkDeviceSize offset,
2309 VkDeviceSize size,
2310 VkMemoryMapFlags flags,
2311 void** ppData)
2312 {
2313 RADV_FROM_HANDLE(radv_device, device, _device);
2314 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2315
2316 if (mem == NULL) {
2317 *ppData = NULL;
2318 return VK_SUCCESS;
2319 }
2320
2321 *ppData = device->ws->buffer_map(mem->bo);
2322 if (*ppData) {
2323 *ppData += offset;
2324 return VK_SUCCESS;
2325 }
2326
2327 return VK_ERROR_MEMORY_MAP_FAILED;
2328 }
2329
2330 void radv_UnmapMemory(
2331 VkDevice _device,
2332 VkDeviceMemory _memory)
2333 {
2334 RADV_FROM_HANDLE(radv_device, device, _device);
2335 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2336
2337 if (mem == NULL)
2338 return;
2339
2340 device->ws->buffer_unmap(mem->bo);
2341 }
2342
2343 VkResult radv_FlushMappedMemoryRanges(
2344 VkDevice _device,
2345 uint32_t memoryRangeCount,
2346 const VkMappedMemoryRange* pMemoryRanges)
2347 {
2348 return VK_SUCCESS;
2349 }
2350
2351 VkResult radv_InvalidateMappedMemoryRanges(
2352 VkDevice _device,
2353 uint32_t memoryRangeCount,
2354 const VkMappedMemoryRange* pMemoryRanges)
2355 {
2356 return VK_SUCCESS;
2357 }
2358
2359 void radv_GetBufferMemoryRequirements(
2360 VkDevice device,
2361 VkBuffer _buffer,
2362 VkMemoryRequirements* pMemoryRequirements)
2363 {
2364 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2365
2366 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2367
2368 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2369 pMemoryRequirements->alignment = 4096;
2370 else
2371 pMemoryRequirements->alignment = 16;
2372
2373 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2374 }
2375
2376 void radv_GetBufferMemoryRequirements2KHR(
2377 VkDevice device,
2378 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2379 VkMemoryRequirements2KHR* pMemoryRequirements)
2380 {
2381 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2382 &pMemoryRequirements->memoryRequirements);
2383
2384 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2385 switch (ext->sType) {
2386 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2387 VkMemoryDedicatedRequirementsKHR *req =
2388 (VkMemoryDedicatedRequirementsKHR *) ext;
2389 req->requiresDedicatedAllocation = false;
2390 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2391 break;
2392 }
2393 default:
2394 break;
2395 }
2396 }
2397 }
2398
2399 void radv_GetImageMemoryRequirements(
2400 VkDevice device,
2401 VkImage _image,
2402 VkMemoryRequirements* pMemoryRequirements)
2403 {
2404 RADV_FROM_HANDLE(radv_image, image, _image);
2405
2406 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2407
2408 pMemoryRequirements->size = image->size;
2409 pMemoryRequirements->alignment = image->alignment;
2410 }
2411
2412 void radv_GetImageMemoryRequirements2KHR(
2413 VkDevice device,
2414 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2415 VkMemoryRequirements2KHR* pMemoryRequirements)
2416 {
2417 radv_GetImageMemoryRequirements(device, pInfo->image,
2418 &pMemoryRequirements->memoryRequirements);
2419
2420 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2421
2422 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2423 switch (ext->sType) {
2424 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2425 VkMemoryDedicatedRequirementsKHR *req =
2426 (VkMemoryDedicatedRequirementsKHR *) ext;
2427 req->requiresDedicatedAllocation = image->shareable;
2428 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2429 break;
2430 }
2431 default:
2432 break;
2433 }
2434 }
2435 }
2436
2437 void radv_GetImageSparseMemoryRequirements(
2438 VkDevice device,
2439 VkImage image,
2440 uint32_t* pSparseMemoryRequirementCount,
2441 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2442 {
2443 stub();
2444 }
2445
2446 void radv_GetImageSparseMemoryRequirements2KHR(
2447 VkDevice device,
2448 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2449 uint32_t* pSparseMemoryRequirementCount,
2450 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2451 {
2452 stub();
2453 }
2454
2455 void radv_GetDeviceMemoryCommitment(
2456 VkDevice device,
2457 VkDeviceMemory memory,
2458 VkDeviceSize* pCommittedMemoryInBytes)
2459 {
2460 *pCommittedMemoryInBytes = 0;
2461 }
2462
2463 VkResult radv_BindBufferMemory(
2464 VkDevice device,
2465 VkBuffer _buffer,
2466 VkDeviceMemory _memory,
2467 VkDeviceSize memoryOffset)
2468 {
2469 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2470 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2471
2472 if (mem) {
2473 buffer->bo = mem->bo;
2474 buffer->offset = memoryOffset;
2475 } else {
2476 buffer->bo = NULL;
2477 buffer->offset = 0;
2478 }
2479
2480 return VK_SUCCESS;
2481 }
2482
2483 VkResult radv_BindImageMemory(
2484 VkDevice device,
2485 VkImage _image,
2486 VkDeviceMemory _memory,
2487 VkDeviceSize memoryOffset)
2488 {
2489 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2490 RADV_FROM_HANDLE(radv_image, image, _image);
2491
2492 if (mem) {
2493 image->bo = mem->bo;
2494 image->offset = memoryOffset;
2495 } else {
2496 image->bo = NULL;
2497 image->offset = 0;
2498 }
2499
2500 return VK_SUCCESS;
2501 }
2502
2503
2504 static void
2505 radv_sparse_buffer_bind_memory(struct radv_device *device,
2506 const VkSparseBufferMemoryBindInfo *bind)
2507 {
2508 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2509
2510 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2511 struct radv_device_memory *mem = NULL;
2512
2513 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2514 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2515
2516 device->ws->buffer_virtual_bind(buffer->bo,
2517 bind->pBinds[i].resourceOffset,
2518 bind->pBinds[i].size,
2519 mem ? mem->bo : NULL,
2520 bind->pBinds[i].memoryOffset);
2521 }
2522 }
2523
2524 static void
2525 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2526 const VkSparseImageOpaqueMemoryBindInfo *bind)
2527 {
2528 RADV_FROM_HANDLE(radv_image, image, bind->image);
2529
2530 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2531 struct radv_device_memory *mem = NULL;
2532
2533 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2534 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2535
2536 device->ws->buffer_virtual_bind(image->bo,
2537 bind->pBinds[i].resourceOffset,
2538 bind->pBinds[i].size,
2539 mem ? mem->bo : NULL,
2540 bind->pBinds[i].memoryOffset);
2541 }
2542 }
2543
2544 VkResult radv_QueueBindSparse(
2545 VkQueue _queue,
2546 uint32_t bindInfoCount,
2547 const VkBindSparseInfo* pBindInfo,
2548 VkFence _fence)
2549 {
2550 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2551 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2552 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2553 bool fence_emitted = false;
2554
2555 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2556 struct radv_winsys_sem_info sem_info;
2557 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2558 radv_sparse_buffer_bind_memory(queue->device,
2559 pBindInfo[i].pBufferBinds + j);
2560 }
2561
2562 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2563 radv_sparse_image_opaque_bind_memory(queue->device,
2564 pBindInfo[i].pImageOpaqueBinds + j);
2565 }
2566
2567 VkResult result;
2568 result = radv_alloc_sem_info(&sem_info,
2569 pBindInfo[i].waitSemaphoreCount,
2570 pBindInfo[i].pWaitSemaphores,
2571 pBindInfo[i].signalSemaphoreCount,
2572 pBindInfo[i].pSignalSemaphores);
2573 if (result != VK_SUCCESS)
2574 return result;
2575
2576 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2577 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2578 &queue->device->empty_cs[queue->queue_family_index],
2579 1, NULL, NULL,
2580 &sem_info,
2581 false, base_fence);
2582 fence_emitted = true;
2583 if (fence)
2584 fence->submitted = true;
2585 }
2586
2587 radv_free_sem_info(&sem_info);
2588
2589 }
2590
2591 if (fence && !fence_emitted) {
2592 fence->signalled = true;
2593 }
2594
2595 return VK_SUCCESS;
2596 }
2597
2598 VkResult radv_CreateFence(
2599 VkDevice _device,
2600 const VkFenceCreateInfo* pCreateInfo,
2601 const VkAllocationCallbacks* pAllocator,
2602 VkFence* pFence)
2603 {
2604 RADV_FROM_HANDLE(radv_device, device, _device);
2605 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2606 sizeof(*fence), 8,
2607 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2608
2609 if (!fence)
2610 return VK_ERROR_OUT_OF_HOST_MEMORY;
2611
2612 memset(fence, 0, sizeof(*fence));
2613 fence->submitted = false;
2614 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2615 fence->fence = device->ws->create_fence();
2616 if (!fence->fence) {
2617 vk_free2(&device->alloc, pAllocator, fence);
2618 return VK_ERROR_OUT_OF_HOST_MEMORY;
2619 }
2620
2621 *pFence = radv_fence_to_handle(fence);
2622
2623 return VK_SUCCESS;
2624 }
2625
2626 void radv_DestroyFence(
2627 VkDevice _device,
2628 VkFence _fence,
2629 const VkAllocationCallbacks* pAllocator)
2630 {
2631 RADV_FROM_HANDLE(radv_device, device, _device);
2632 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2633
2634 if (!fence)
2635 return;
2636 device->ws->destroy_fence(fence->fence);
2637 vk_free2(&device->alloc, pAllocator, fence);
2638 }
2639
2640 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2641 {
2642 uint64_t current_time;
2643 struct timespec tv;
2644
2645 clock_gettime(CLOCK_MONOTONIC, &tv);
2646 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2647
2648 timeout = MIN2(UINT64_MAX - current_time, timeout);
2649
2650 return current_time + timeout;
2651 }
2652
2653 VkResult radv_WaitForFences(
2654 VkDevice _device,
2655 uint32_t fenceCount,
2656 const VkFence* pFences,
2657 VkBool32 waitAll,
2658 uint64_t timeout)
2659 {
2660 RADV_FROM_HANDLE(radv_device, device, _device);
2661 timeout = radv_get_absolute_timeout(timeout);
2662
2663 if (!waitAll && fenceCount > 1) {
2664 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2665 }
2666
2667 for (uint32_t i = 0; i < fenceCount; ++i) {
2668 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2669 bool expired = false;
2670
2671 if (fence->signalled)
2672 continue;
2673
2674 if (!fence->submitted)
2675 return VK_TIMEOUT;
2676
2677 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2678 if (!expired)
2679 return VK_TIMEOUT;
2680
2681 fence->signalled = true;
2682 }
2683
2684 return VK_SUCCESS;
2685 }
2686
2687 VkResult radv_ResetFences(VkDevice device,
2688 uint32_t fenceCount,
2689 const VkFence *pFences)
2690 {
2691 for (unsigned i = 0; i < fenceCount; ++i) {
2692 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2693 fence->submitted = fence->signalled = false;
2694 }
2695
2696 return VK_SUCCESS;
2697 }
2698
2699 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2700 {
2701 RADV_FROM_HANDLE(radv_device, device, _device);
2702 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2703
2704 if (fence->signalled)
2705 return VK_SUCCESS;
2706 if (!fence->submitted)
2707 return VK_NOT_READY;
2708
2709 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2710 return VK_NOT_READY;
2711
2712 return VK_SUCCESS;
2713 }
2714
2715
2716 // Queue semaphore functions
2717
2718 VkResult radv_CreateSemaphore(
2719 VkDevice _device,
2720 const VkSemaphoreCreateInfo* pCreateInfo,
2721 const VkAllocationCallbacks* pAllocator,
2722 VkSemaphore* pSemaphore)
2723 {
2724 RADV_FROM_HANDLE(radv_device, device, _device);
2725 const VkExportSemaphoreCreateInfoKHR *export =
2726 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2727 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2728 export ? export->handleTypes : 0;
2729
2730 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2731 sizeof(*sem), 8,
2732 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2733 if (!sem)
2734 return VK_ERROR_OUT_OF_HOST_MEMORY;
2735
2736 sem->temp_syncobj = 0;
2737 /* create a syncobject if we are going to export this semaphore */
2738 if (handleTypes) {
2739 assert (device->physical_device->rad_info.has_syncobj);
2740 assert (handleTypes == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2741 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2742 if (ret) {
2743 vk_free2(&device->alloc, pAllocator, sem);
2744 return VK_ERROR_OUT_OF_HOST_MEMORY;
2745 }
2746 sem->sem = NULL;
2747 } else {
2748 sem->sem = device->ws->create_sem(device->ws);
2749 if (!sem->sem) {
2750 vk_free2(&device->alloc, pAllocator, sem);
2751 return VK_ERROR_OUT_OF_HOST_MEMORY;
2752 }
2753 sem->syncobj = 0;
2754 }
2755
2756 *pSemaphore = radv_semaphore_to_handle(sem);
2757 return VK_SUCCESS;
2758 }
2759
2760 void radv_DestroySemaphore(
2761 VkDevice _device,
2762 VkSemaphore _semaphore,
2763 const VkAllocationCallbacks* pAllocator)
2764 {
2765 RADV_FROM_HANDLE(radv_device, device, _device);
2766 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2767 if (!_semaphore)
2768 return;
2769
2770 if (sem->syncobj)
2771 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2772 else
2773 device->ws->destroy_sem(sem->sem);
2774 vk_free2(&device->alloc, pAllocator, sem);
2775 }
2776
2777 VkResult radv_CreateEvent(
2778 VkDevice _device,
2779 const VkEventCreateInfo* pCreateInfo,
2780 const VkAllocationCallbacks* pAllocator,
2781 VkEvent* pEvent)
2782 {
2783 RADV_FROM_HANDLE(radv_device, device, _device);
2784 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2785 sizeof(*event), 8,
2786 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2787
2788 if (!event)
2789 return VK_ERROR_OUT_OF_HOST_MEMORY;
2790
2791 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2792 RADEON_DOMAIN_GTT,
2793 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS);
2794 if (!event->bo) {
2795 vk_free2(&device->alloc, pAllocator, event);
2796 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2797 }
2798
2799 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2800
2801 *pEvent = radv_event_to_handle(event);
2802
2803 return VK_SUCCESS;
2804 }
2805
2806 void radv_DestroyEvent(
2807 VkDevice _device,
2808 VkEvent _event,
2809 const VkAllocationCallbacks* pAllocator)
2810 {
2811 RADV_FROM_HANDLE(radv_device, device, _device);
2812 RADV_FROM_HANDLE(radv_event, event, _event);
2813
2814 if (!event)
2815 return;
2816 device->ws->buffer_destroy(event->bo);
2817 vk_free2(&device->alloc, pAllocator, event);
2818 }
2819
2820 VkResult radv_GetEventStatus(
2821 VkDevice _device,
2822 VkEvent _event)
2823 {
2824 RADV_FROM_HANDLE(radv_event, event, _event);
2825
2826 if (*event->map == 1)
2827 return VK_EVENT_SET;
2828 return VK_EVENT_RESET;
2829 }
2830
2831 VkResult radv_SetEvent(
2832 VkDevice _device,
2833 VkEvent _event)
2834 {
2835 RADV_FROM_HANDLE(radv_event, event, _event);
2836 *event->map = 1;
2837
2838 return VK_SUCCESS;
2839 }
2840
2841 VkResult radv_ResetEvent(
2842 VkDevice _device,
2843 VkEvent _event)
2844 {
2845 RADV_FROM_HANDLE(radv_event, event, _event);
2846 *event->map = 0;
2847
2848 return VK_SUCCESS;
2849 }
2850
2851 VkResult radv_CreateBuffer(
2852 VkDevice _device,
2853 const VkBufferCreateInfo* pCreateInfo,
2854 const VkAllocationCallbacks* pAllocator,
2855 VkBuffer* pBuffer)
2856 {
2857 RADV_FROM_HANDLE(radv_device, device, _device);
2858 struct radv_buffer *buffer;
2859
2860 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2861
2862 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2863 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2864 if (buffer == NULL)
2865 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2866
2867 buffer->size = pCreateInfo->size;
2868 buffer->usage = pCreateInfo->usage;
2869 buffer->bo = NULL;
2870 buffer->offset = 0;
2871 buffer->flags = pCreateInfo->flags;
2872
2873 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2874 buffer->bo = device->ws->buffer_create(device->ws,
2875 align64(buffer->size, 4096),
2876 4096, 0, RADEON_FLAG_VIRTUAL);
2877 if (!buffer->bo) {
2878 vk_free2(&device->alloc, pAllocator, buffer);
2879 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2880 }
2881 }
2882
2883 *pBuffer = radv_buffer_to_handle(buffer);
2884
2885 return VK_SUCCESS;
2886 }
2887
2888 void radv_DestroyBuffer(
2889 VkDevice _device,
2890 VkBuffer _buffer,
2891 const VkAllocationCallbacks* pAllocator)
2892 {
2893 RADV_FROM_HANDLE(radv_device, device, _device);
2894 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2895
2896 if (!buffer)
2897 return;
2898
2899 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2900 device->ws->buffer_destroy(buffer->bo);
2901
2902 vk_free2(&device->alloc, pAllocator, buffer);
2903 }
2904
2905 static inline unsigned
2906 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2907 {
2908 if (stencil)
2909 return image->surface.u.legacy.stencil_tiling_index[level];
2910 else
2911 return image->surface.u.legacy.tiling_index[level];
2912 }
2913
2914 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2915 {
2916 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2917 }
2918
2919 static void
2920 radv_initialise_color_surface(struct radv_device *device,
2921 struct radv_color_buffer_info *cb,
2922 struct radv_image_view *iview)
2923 {
2924 const struct vk_format_description *desc;
2925 unsigned ntype, format, swap, endian;
2926 unsigned blend_clamp = 0, blend_bypass = 0;
2927 uint64_t va;
2928 const struct radeon_surf *surf = &iview->image->surface;
2929
2930 desc = vk_format_description(iview->vk_format);
2931
2932 memset(cb, 0, sizeof(*cb));
2933
2934 /* Intensity is implemented as Red, so treat it that way. */
2935 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
2936
2937 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2938
2939 cb->cb_color_base = va >> 8;
2940
2941 if (device->physical_device->rad_info.chip_class >= GFX9) {
2942 struct gfx9_surf_meta_flags meta;
2943 if (iview->image->dcc_offset)
2944 meta = iview->image->surface.u.gfx9.dcc;
2945 else
2946 meta = iview->image->surface.u.gfx9.cmask;
2947
2948 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
2949 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
2950 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2951 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2952
2953 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
2954 cb->cb_color_base |= iview->image->surface.tile_swizzle;
2955 } else {
2956 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
2957 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2958
2959 cb->cb_color_base += level_info->offset >> 8;
2960 if (level_info->mode == RADEON_SURF_MODE_2D)
2961 cb->cb_color_base |= iview->image->surface.tile_swizzle;
2962
2963 pitch_tile_max = level_info->nblk_x / 8 - 1;
2964 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2965 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2966
2967 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2968 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2969 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2970
2971 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2972 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2973
2974 if (iview->image->fmask.size) {
2975 if (device->physical_device->rad_info.chip_class >= CIK)
2976 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2977 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2978 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2979 } else {
2980 /* This must be set for fast clear to work without FMASK. */
2981 if (device->physical_device->rad_info.chip_class >= CIK)
2982 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2983 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2984 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2985 }
2986 }
2987
2988 /* CMASK variables */
2989 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2990 va += iview->image->cmask.offset;
2991 cb->cb_color_cmask = va >> 8;
2992
2993 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2994 va += iview->image->dcc_offset;
2995 cb->cb_dcc_base = va >> 8;
2996 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
2997
2998 uint32_t max_slice = radv_surface_layer_count(iview);
2999 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3000 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
3001
3002 if (iview->image->info.samples > 1) {
3003 unsigned log_samples = util_logbase2(iview->image->info.samples);
3004
3005 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3006 S_028C74_NUM_FRAGMENTS(log_samples);
3007 }
3008
3009 if (iview->image->fmask.size) {
3010 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3011 cb->cb_color_fmask = va >> 8;
3012 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3013 } else {
3014 cb->cb_color_fmask = cb->cb_color_base;
3015 }
3016
3017 ntype = radv_translate_color_numformat(iview->vk_format,
3018 desc,
3019 vk_format_get_first_non_void_channel(iview->vk_format));
3020 format = radv_translate_colorformat(iview->vk_format);
3021 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3022 radv_finishme("Illegal color\n");
3023 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3024 endian = radv_colorformat_endian_swap(format);
3025
3026 /* blend clamp should be set for all NORM/SRGB types */
3027 if (ntype == V_028C70_NUMBER_UNORM ||
3028 ntype == V_028C70_NUMBER_SNORM ||
3029 ntype == V_028C70_NUMBER_SRGB)
3030 blend_clamp = 1;
3031
3032 /* set blend bypass according to docs if SINT/UINT or
3033 8/24 COLOR variants */
3034 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3035 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3036 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3037 blend_clamp = 0;
3038 blend_bypass = 1;
3039 }
3040 #if 0
3041 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3042 (format == V_028C70_COLOR_8 ||
3043 format == V_028C70_COLOR_8_8 ||
3044 format == V_028C70_COLOR_8_8_8_8))
3045 ->color_is_int8 = true;
3046 #endif
3047 cb->cb_color_info = S_028C70_FORMAT(format) |
3048 S_028C70_COMP_SWAP(swap) |
3049 S_028C70_BLEND_CLAMP(blend_clamp) |
3050 S_028C70_BLEND_BYPASS(blend_bypass) |
3051 S_028C70_SIMPLE_FLOAT(1) |
3052 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3053 ntype != V_028C70_NUMBER_SNORM &&
3054 ntype != V_028C70_NUMBER_SRGB &&
3055 format != V_028C70_COLOR_8_24 &&
3056 format != V_028C70_COLOR_24_8) |
3057 S_028C70_NUMBER_TYPE(ntype) |
3058 S_028C70_ENDIAN(endian);
3059 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
3060 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3061 if (device->physical_device->rad_info.chip_class == SI) {
3062 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3063 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3064 }
3065 }
3066
3067 if (iview->image->cmask.size &&
3068 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3069 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3070
3071 if (iview->image->surface.dcc_size && iview->base_mip < surf->num_dcc_levels)
3072 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3073
3074 if (device->physical_device->rad_info.chip_class >= VI) {
3075 unsigned max_uncompressed_block_size = 2;
3076 if (iview->image->info.samples > 1) {
3077 if (iview->image->surface.bpe == 1)
3078 max_uncompressed_block_size = 0;
3079 else if (iview->image->surface.bpe == 2)
3080 max_uncompressed_block_size = 1;
3081 }
3082
3083 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3084 S_028C78_INDEPENDENT_64B_BLOCKS(1);
3085 }
3086
3087 /* This must be set for fast clear to work without FMASK. */
3088 if (!iview->image->fmask.size &&
3089 device->physical_device->rad_info.chip_class == SI) {
3090 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3091 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3092 }
3093
3094 if (device->physical_device->rad_info.chip_class >= GFX9) {
3095 uint32_t max_slice = radv_surface_layer_count(iview);
3096 unsigned mip0_depth = iview->base_layer + max_slice - 1;
3097
3098 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3099 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3100 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3101 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3102 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3103 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3104
3105 cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3106
3107 }
3108 }
3109
3110 static void
3111 radv_initialise_ds_surface(struct radv_device *device,
3112 struct radv_ds_buffer_info *ds,
3113 struct radv_image_view *iview)
3114 {
3115 unsigned level = iview->base_mip;
3116 unsigned format, stencil_format;
3117 uint64_t va, s_offs, z_offs;
3118 bool stencil_only = false;
3119 memset(ds, 0, sizeof(*ds));
3120 switch (iview->image->vk_format) {
3121 case VK_FORMAT_D24_UNORM_S8_UINT:
3122 case VK_FORMAT_X8_D24_UNORM_PACK32:
3123 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3124 ds->offset_scale = 2.0f;
3125 break;
3126 case VK_FORMAT_D16_UNORM:
3127 case VK_FORMAT_D16_UNORM_S8_UINT:
3128 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3129 ds->offset_scale = 4.0f;
3130 break;
3131 case VK_FORMAT_D32_SFLOAT:
3132 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3133 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3134 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3135 ds->offset_scale = 1.0f;
3136 break;
3137 case VK_FORMAT_S8_UINT:
3138 stencil_only = true;
3139 break;
3140 default:
3141 break;
3142 }
3143
3144 format = radv_translate_dbformat(iview->image->vk_format);
3145 stencil_format = iview->image->surface.has_stencil ?
3146 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3147
3148 uint32_t max_slice = radv_surface_layer_count(iview);
3149 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3150 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
3151
3152 ds->db_htile_data_base = 0;
3153 ds->db_htile_surface = 0;
3154
3155 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3156 s_offs = z_offs = va;
3157
3158 if (device->physical_device->rad_info.chip_class >= GFX9) {
3159 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3160 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3161
3162 ds->db_z_info = S_028038_FORMAT(format) |
3163 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3164 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3165 S_028038_MAXMIP(iview->image->info.levels - 1);
3166 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3167 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3168
3169 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3170 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3171 ds->db_depth_view |= S_028008_MIPID(level);
3172
3173 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3174 S_02801C_Y_MAX(iview->image->info.height - 1);
3175
3176 /* Only use HTILE for the first level. */
3177 if (iview->image->surface.htile_size && !level) {
3178 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3179
3180 if (!iview->image->surface.has_stencil)
3181 /* Use all of the htile_buffer for depth if there's no stencil. */
3182 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3183 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
3184 iview->image->htile_offset;
3185 ds->db_htile_data_base = va >> 8;
3186 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3187 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3188 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3189 }
3190 } else {
3191 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3192
3193 if (stencil_only)
3194 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3195
3196 z_offs += iview->image->surface.u.legacy.level[level].offset;
3197 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3198
3199 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
3200 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3201 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3202
3203 if (iview->image->info.samples > 1)
3204 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3205
3206 if (device->physical_device->rad_info.chip_class >= CIK) {
3207 struct radeon_info *info = &device->physical_device->rad_info;
3208 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3209 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3210 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3211 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3212 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3213 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3214
3215 if (stencil_only)
3216 tile_mode = stencil_tile_mode;
3217
3218 ds->db_depth_info |=
3219 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3220 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3221 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3222 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3223 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3224 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3225 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3226 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3227 } else {
3228 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3229 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3230 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3231 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3232 if (stencil_only)
3233 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3234 }
3235
3236 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3237 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3238 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3239
3240 if (iview->image->surface.htile_size && !level) {
3241 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3242
3243 if (!iview->image->surface.has_stencil)
3244 /* Use all of the htile_buffer for depth if there's no stencil. */
3245 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3246
3247 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
3248 iview->image->htile_offset;
3249 ds->db_htile_data_base = va >> 8;
3250 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3251 }
3252 }
3253
3254 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3255 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3256 }
3257
3258 VkResult radv_CreateFramebuffer(
3259 VkDevice _device,
3260 const VkFramebufferCreateInfo* pCreateInfo,
3261 const VkAllocationCallbacks* pAllocator,
3262 VkFramebuffer* pFramebuffer)
3263 {
3264 RADV_FROM_HANDLE(radv_device, device, _device);
3265 struct radv_framebuffer *framebuffer;
3266
3267 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3268
3269 size_t size = sizeof(*framebuffer) +
3270 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3271 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3272 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3273 if (framebuffer == NULL)
3274 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3275
3276 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3277 framebuffer->width = pCreateInfo->width;
3278 framebuffer->height = pCreateInfo->height;
3279 framebuffer->layers = pCreateInfo->layers;
3280 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3281 VkImageView _iview = pCreateInfo->pAttachments[i];
3282 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3283 framebuffer->attachments[i].attachment = iview;
3284 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3285 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3286 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3287 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3288 }
3289 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3290 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3291 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
3292 }
3293
3294 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3295 return VK_SUCCESS;
3296 }
3297
3298 void radv_DestroyFramebuffer(
3299 VkDevice _device,
3300 VkFramebuffer _fb,
3301 const VkAllocationCallbacks* pAllocator)
3302 {
3303 RADV_FROM_HANDLE(radv_device, device, _device);
3304 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3305
3306 if (!fb)
3307 return;
3308 vk_free2(&device->alloc, pAllocator, fb);
3309 }
3310
3311 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3312 {
3313 switch (address_mode) {
3314 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3315 return V_008F30_SQ_TEX_WRAP;
3316 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3317 return V_008F30_SQ_TEX_MIRROR;
3318 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3319 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3320 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3321 return V_008F30_SQ_TEX_CLAMP_BORDER;
3322 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3323 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3324 default:
3325 unreachable("illegal tex wrap mode");
3326 break;
3327 }
3328 }
3329
3330 static unsigned
3331 radv_tex_compare(VkCompareOp op)
3332 {
3333 switch (op) {
3334 case VK_COMPARE_OP_NEVER:
3335 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3336 case VK_COMPARE_OP_LESS:
3337 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3338 case VK_COMPARE_OP_EQUAL:
3339 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3340 case VK_COMPARE_OP_LESS_OR_EQUAL:
3341 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3342 case VK_COMPARE_OP_GREATER:
3343 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3344 case VK_COMPARE_OP_NOT_EQUAL:
3345 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3346 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3347 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3348 case VK_COMPARE_OP_ALWAYS:
3349 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3350 default:
3351 unreachable("illegal compare mode");
3352 break;
3353 }
3354 }
3355
3356 static unsigned
3357 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3358 {
3359 switch (filter) {
3360 case VK_FILTER_NEAREST:
3361 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3362 V_008F38_SQ_TEX_XY_FILTER_POINT);
3363 case VK_FILTER_LINEAR:
3364 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3365 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3366 case VK_FILTER_CUBIC_IMG:
3367 default:
3368 fprintf(stderr, "illegal texture filter");
3369 return 0;
3370 }
3371 }
3372
3373 static unsigned
3374 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3375 {
3376 switch (mode) {
3377 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3378 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3379 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3380 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3381 default:
3382 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3383 }
3384 }
3385
3386 static unsigned
3387 radv_tex_bordercolor(VkBorderColor bcolor)
3388 {
3389 switch (bcolor) {
3390 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3391 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3392 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3393 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3394 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3395 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3396 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3397 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3398 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3399 default:
3400 break;
3401 }
3402 return 0;
3403 }
3404
3405 static unsigned
3406 radv_tex_aniso_filter(unsigned filter)
3407 {
3408 if (filter < 2)
3409 return 0;
3410 if (filter < 4)
3411 return 1;
3412 if (filter < 8)
3413 return 2;
3414 if (filter < 16)
3415 return 3;
3416 return 4;
3417 }
3418
3419 static void
3420 radv_init_sampler(struct radv_device *device,
3421 struct radv_sampler *sampler,
3422 const VkSamplerCreateInfo *pCreateInfo)
3423 {
3424 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3425 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3426 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3427 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3428
3429 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3430 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3431 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3432 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3433 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3434 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3435 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3436 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3437 S_008F30_DISABLE_CUBE_WRAP(0) |
3438 S_008F30_COMPAT_MODE(is_vi));
3439 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3440 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3441 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3442 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3443 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3444 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3445 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3446 S_008F38_MIP_POINT_PRECLAMP(0) |
3447 S_008F38_DISABLE_LSB_CEIL(1) |
3448 S_008F38_FILTER_PREC_FIX(1) |
3449 S_008F38_ANISO_OVERRIDE(is_vi));
3450 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3451 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3452 }
3453
3454 VkResult radv_CreateSampler(
3455 VkDevice _device,
3456 const VkSamplerCreateInfo* pCreateInfo,
3457 const VkAllocationCallbacks* pAllocator,
3458 VkSampler* pSampler)
3459 {
3460 RADV_FROM_HANDLE(radv_device, device, _device);
3461 struct radv_sampler *sampler;
3462
3463 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3464
3465 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3466 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3467 if (!sampler)
3468 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3469
3470 radv_init_sampler(device, sampler, pCreateInfo);
3471 *pSampler = radv_sampler_to_handle(sampler);
3472
3473 return VK_SUCCESS;
3474 }
3475
3476 void radv_DestroySampler(
3477 VkDevice _device,
3478 VkSampler _sampler,
3479 const VkAllocationCallbacks* pAllocator)
3480 {
3481 RADV_FROM_HANDLE(radv_device, device, _device);
3482 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3483
3484 if (!sampler)
3485 return;
3486 vk_free2(&device->alloc, pAllocator, sampler);
3487 }
3488
3489 /* vk_icd.h does not declare this function, so we declare it here to
3490 * suppress Wmissing-prototypes.
3491 */
3492 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3493 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3494
3495 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3496 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3497 {
3498 /* For the full details on loader interface versioning, see
3499 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3500 * What follows is a condensed summary, to help you navigate the large and
3501 * confusing official doc.
3502 *
3503 * - Loader interface v0 is incompatible with later versions. We don't
3504 * support it.
3505 *
3506 * - In loader interface v1:
3507 * - The first ICD entrypoint called by the loader is
3508 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3509 * entrypoint.
3510 * - The ICD must statically expose no other Vulkan symbol unless it is
3511 * linked with -Bsymbolic.
3512 * - Each dispatchable Vulkan handle created by the ICD must be
3513 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3514 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3515 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3516 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3517 * such loader-managed surfaces.
3518 *
3519 * - Loader interface v2 differs from v1 in:
3520 * - The first ICD entrypoint called by the loader is
3521 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3522 * statically expose this entrypoint.
3523 *
3524 * - Loader interface v3 differs from v2 in:
3525 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3526 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3527 * because the loader no longer does so.
3528 */
3529 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3530 return VK_SUCCESS;
3531 }
3532
3533 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3534 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3535 int *pFD)
3536 {
3537 RADV_FROM_HANDLE(radv_device, device, _device);
3538 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3539
3540 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3541
3542 /* We support only one handle type. */
3543 assert(pGetFdInfo->handleType ==
3544 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3545
3546 bool ret = radv_get_memory_fd(device, memory, pFD);
3547 if (ret == false)
3548 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
3549 return VK_SUCCESS;
3550 }
3551
3552 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3553 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3554 int fd,
3555 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3556 {
3557 /* The valid usage section for this function says:
3558 *
3559 * "handleType must not be one of the handle types defined as opaque."
3560 *
3561 * Since we only handle opaque handles for now, there are no FD properties.
3562 */
3563 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3564 }
3565
3566 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3567 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3568 {
3569 RADV_FROM_HANDLE(radv_device, device, _device);
3570 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3571 uint32_t syncobj_handle = 0;
3572 assert(pImportSemaphoreFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3573
3574 int ret = device->ws->import_syncobj(device->ws, pImportSemaphoreFdInfo->fd, &syncobj_handle);
3575 if (ret != 0)
3576 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3577
3578 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3579 sem->temp_syncobj = syncobj_handle;
3580 } else {
3581 sem->syncobj = syncobj_handle;
3582 }
3583 close(pImportSemaphoreFdInfo->fd);
3584 return VK_SUCCESS;
3585 }
3586
3587 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3588 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3589 int *pFd)
3590 {
3591 RADV_FROM_HANDLE(radv_device, device, _device);
3592 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3593 int ret;
3594 uint32_t syncobj_handle;
3595
3596 assert(pGetFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3597 if (sem->temp_syncobj)
3598 syncobj_handle = sem->temp_syncobj;
3599 else
3600 syncobj_handle = sem->syncobj;
3601 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3602 if (ret)
3603 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3604 return VK_SUCCESS;
3605 }
3606
3607 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3608 VkPhysicalDevice physicalDevice,
3609 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3610 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3611 {
3612 if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3613 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3614 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3615 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3616 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3617 } else {
3618 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3619 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3620 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3621 }
3622 }