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radv: add support for VK_AMD_negative_viewport_height
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <dlfcn.h>
29 #include <stdbool.h>
30 #include <string.h>
31 #include <unistd.h>
32 #include <fcntl.h>
33 #include <sys/stat.h>
34 #include "radv_private.h"
35 #include "util/strtod.h"
36
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "util/debug.h"
46 struct radv_dispatch_table dtable;
47
48 static int
49 radv_get_function_timestamp(void *ptr, uint32_t* timestamp)
50 {
51 Dl_info info;
52 struct stat st;
53 if (!dladdr(ptr, &info) || !info.dli_fname) {
54 return -1;
55 }
56 if (stat(info.dli_fname, &st)) {
57 return -1;
58 }
59 *timestamp = st.st_mtim.tv_sec;
60 return 0;
61 }
62
63 static int
64 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
65 {
66 uint32_t mesa_timestamp, llvm_timestamp;
67 uint16_t f = family;
68 memset(uuid, 0, VK_UUID_SIZE);
69 if (radv_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
70 radv_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
71 return -1;
72
73 memcpy(uuid, &mesa_timestamp, 4);
74 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
75 memcpy((char*)uuid + 8, &f, 2);
76 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
77 return 0;
78 }
79
80 static VkResult
81 radv_physical_device_init(struct radv_physical_device *device,
82 struct radv_instance *instance,
83 const char *path)
84 {
85 VkResult result;
86 drmVersionPtr version;
87 int fd;
88
89 fd = open(path, O_RDWR | O_CLOEXEC);
90 if (fd < 0)
91 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
92 "failed to open %s: %m", path);
93
94 version = drmGetVersion(fd);
95 if (!version) {
96 close(fd);
97 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
98 "failed to get version %s: %m", path);
99 }
100
101 if (strcmp(version->name, "amdgpu")) {
102 drmFreeVersion(version);
103 close(fd);
104 return VK_ERROR_INCOMPATIBLE_DRIVER;
105 }
106 drmFreeVersion(version);
107
108 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
109 device->instance = instance;
110 assert(strlen(path) < ARRAY_SIZE(device->path));
111 strncpy(device->path, path, ARRAY_SIZE(device->path));
112
113 device->ws = radv_amdgpu_winsys_create(fd);
114 if (!device->ws) {
115 result = VK_ERROR_INCOMPATIBLE_DRIVER;
116 goto fail;
117 }
118 device->ws->query_info(device->ws, &device->rad_info);
119 result = radv_init_wsi(device);
120 if (result != VK_SUCCESS) {
121 device->ws->destroy(device->ws);
122 goto fail;
123 }
124
125 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
126 radv_finish_wsi(device);
127 device->ws->destroy(device->ws);
128 goto fail;
129 }
130
131 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
132 device->name = device->rad_info.name;
133 return VK_SUCCESS;
134
135 fail:
136 close(fd);
137 return result;
138 }
139
140 static void
141 radv_physical_device_finish(struct radv_physical_device *device)
142 {
143 radv_finish_wsi(device);
144 device->ws->destroy(device->ws);
145 }
146
147 static const VkExtensionProperties global_extensions[] = {
148 {
149 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
150 .specVersion = 25,
151 },
152 #ifdef VK_USE_PLATFORM_XCB_KHR
153 {
154 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
155 .specVersion = 6,
156 },
157 #endif
158 #ifdef VK_USE_PLATFORM_XLIB_KHR
159 {
160 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
161 .specVersion = 6,
162 },
163 #endif
164 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
165 {
166 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
167 .specVersion = 5,
168 },
169 #endif
170 };
171
172 static const VkExtensionProperties device_extensions[] = {
173 {
174 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
175 .specVersion = 1,
176 },
177 {
178 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
179 .specVersion = 68,
180 },
181 {
182 .extensionName = VK_AMD_NEGATIVE_VIEWPORT_HEIGHT_EXTENSION_NAME,
183 .specVersion = 1,
184 },
185 };
186
187 static void *
188 default_alloc_func(void *pUserData, size_t size, size_t align,
189 VkSystemAllocationScope allocationScope)
190 {
191 return malloc(size);
192 }
193
194 static void *
195 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
196 size_t align, VkSystemAllocationScope allocationScope)
197 {
198 return realloc(pOriginal, size);
199 }
200
201 static void
202 default_free_func(void *pUserData, void *pMemory)
203 {
204 free(pMemory);
205 }
206
207 static const VkAllocationCallbacks default_alloc = {
208 .pUserData = NULL,
209 .pfnAllocation = default_alloc_func,
210 .pfnReallocation = default_realloc_func,
211 .pfnFree = default_free_func,
212 };
213
214 VkResult radv_CreateInstance(
215 const VkInstanceCreateInfo* pCreateInfo,
216 const VkAllocationCallbacks* pAllocator,
217 VkInstance* pInstance)
218 {
219 struct radv_instance *instance;
220
221 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
222
223 uint32_t client_version;
224 if (pCreateInfo->pApplicationInfo &&
225 pCreateInfo->pApplicationInfo->apiVersion != 0) {
226 client_version = pCreateInfo->pApplicationInfo->apiVersion;
227 } else {
228 client_version = VK_MAKE_VERSION(1, 0, 0);
229 }
230
231 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
232 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
233 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
234 "Client requested version %d.%d.%d",
235 VK_VERSION_MAJOR(client_version),
236 VK_VERSION_MINOR(client_version),
237 VK_VERSION_PATCH(client_version));
238 }
239
240 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
241 bool found = false;
242 for (uint32_t j = 0; j < ARRAY_SIZE(global_extensions); j++) {
243 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
244 global_extensions[j].extensionName) == 0) {
245 found = true;
246 break;
247 }
248 }
249 if (!found)
250 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
251 }
252
253 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
254 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
255 if (!instance)
256 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
257
258 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
259
260 if (pAllocator)
261 instance->alloc = *pAllocator;
262 else
263 instance->alloc = default_alloc;
264
265 instance->apiVersion = client_version;
266 instance->physicalDeviceCount = -1;
267
268 _mesa_locale_init();
269
270 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
271
272 *pInstance = radv_instance_to_handle(instance);
273
274 return VK_SUCCESS;
275 }
276
277 void radv_DestroyInstance(
278 VkInstance _instance,
279 const VkAllocationCallbacks* pAllocator)
280 {
281 RADV_FROM_HANDLE(radv_instance, instance, _instance);
282
283 if (instance->physicalDeviceCount > 0) {
284 /* We support at most one physical device. */
285 assert(instance->physicalDeviceCount == 1);
286 radv_physical_device_finish(&instance->physicalDevice);
287 }
288
289 VG(VALGRIND_DESTROY_MEMPOOL(instance));
290
291 _mesa_locale_fini();
292
293 vk_free(&instance->alloc, instance);
294 }
295
296 VkResult radv_EnumeratePhysicalDevices(
297 VkInstance _instance,
298 uint32_t* pPhysicalDeviceCount,
299 VkPhysicalDevice* pPhysicalDevices)
300 {
301 RADV_FROM_HANDLE(radv_instance, instance, _instance);
302 VkResult result;
303
304 if (instance->physicalDeviceCount < 0) {
305 char path[20];
306 for (unsigned i = 0; i < 8; i++) {
307 snprintf(path, sizeof(path), "/dev/dri/renderD%d", 128 + i);
308 result = radv_physical_device_init(&instance->physicalDevice,
309 instance, path);
310 if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
311 break;
312 }
313
314 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
315 instance->physicalDeviceCount = 0;
316 } else if (result == VK_SUCCESS) {
317 instance->physicalDeviceCount = 1;
318 } else {
319 return result;
320 }
321 }
322
323 /* pPhysicalDeviceCount is an out parameter if pPhysicalDevices is NULL;
324 * otherwise it's an inout parameter.
325 *
326 * The Vulkan spec (git aaed022) says:
327 *
328 * pPhysicalDeviceCount is a pointer to an unsigned integer variable
329 * that is initialized with the number of devices the application is
330 * prepared to receive handles to. pname:pPhysicalDevices is pointer to
331 * an array of at least this many VkPhysicalDevice handles [...].
332 *
333 * Upon success, if pPhysicalDevices is NULL, vkEnumeratePhysicalDevices
334 * overwrites the contents of the variable pointed to by
335 * pPhysicalDeviceCount with the number of physical devices in in the
336 * instance; otherwise, vkEnumeratePhysicalDevices overwrites
337 * pPhysicalDeviceCount with the number of physical handles written to
338 * pPhysicalDevices.
339 */
340 if (!pPhysicalDevices) {
341 *pPhysicalDeviceCount = instance->physicalDeviceCount;
342 } else if (*pPhysicalDeviceCount >= 1) {
343 pPhysicalDevices[0] = radv_physical_device_to_handle(&instance->physicalDevice);
344 *pPhysicalDeviceCount = 1;
345 } else if (*pPhysicalDeviceCount < instance->physicalDeviceCount) {
346 return VK_INCOMPLETE;
347 } else {
348 *pPhysicalDeviceCount = 0;
349 }
350
351 return VK_SUCCESS;
352 }
353
354 void radv_GetPhysicalDeviceFeatures(
355 VkPhysicalDevice physicalDevice,
356 VkPhysicalDeviceFeatures* pFeatures)
357 {
358 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
359
360 memset(pFeatures, 0, sizeof(*pFeatures));
361
362 *pFeatures = (VkPhysicalDeviceFeatures) {
363 .robustBufferAccess = true,
364 .fullDrawIndexUint32 = true,
365 .imageCubeArray = true,
366 .independentBlend = true,
367 .geometryShader = false,
368 .tessellationShader = false,
369 .sampleRateShading = false,
370 .dualSrcBlend = true,
371 .logicOp = true,
372 .multiDrawIndirect = true,
373 .drawIndirectFirstInstance = true,
374 .depthClamp = true,
375 .depthBiasClamp = true,
376 .fillModeNonSolid = true,
377 .depthBounds = true,
378 .wideLines = true,
379 .largePoints = true,
380 .alphaToOne = true,
381 .multiViewport = false,
382 .samplerAnisotropy = true,
383 .textureCompressionETC2 = false,
384 .textureCompressionASTC_LDR = false,
385 .textureCompressionBC = true,
386 .occlusionQueryPrecise = true,
387 .pipelineStatisticsQuery = false,
388 .vertexPipelineStoresAndAtomics = true,
389 .fragmentStoresAndAtomics = true,
390 .shaderTessellationAndGeometryPointSize = true,
391 .shaderImageGatherExtended = false,
392 .shaderStorageImageExtendedFormats = false,
393 .shaderStorageImageMultisample = false,
394 .shaderUniformBufferArrayDynamicIndexing = true,
395 .shaderSampledImageArrayDynamicIndexing = true,
396 .shaderStorageBufferArrayDynamicIndexing = true,
397 .shaderStorageImageArrayDynamicIndexing = true,
398 .shaderStorageImageReadWithoutFormat = false,
399 .shaderStorageImageWriteWithoutFormat = true,
400 .shaderClipDistance = true,
401 .shaderCullDistance = true,
402 .shaderFloat64 = false,
403 .shaderInt64 = false,
404 .shaderInt16 = false,
405 .alphaToOne = true,
406 .variableMultisampleRate = false,
407 .inheritedQueries = false,
408 };
409 }
410
411 void radv_GetPhysicalDeviceProperties(
412 VkPhysicalDevice physicalDevice,
413 VkPhysicalDeviceProperties* pProperties)
414 {
415 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
416 VkSampleCountFlags sample_counts = 0xf;
417 VkPhysicalDeviceLimits limits = {
418 .maxImageDimension1D = (1 << 14),
419 .maxImageDimension2D = (1 << 14),
420 .maxImageDimension3D = (1 << 11),
421 .maxImageDimensionCube = (1 << 14),
422 .maxImageArrayLayers = (1 << 11),
423 .maxTexelBufferElements = 128 * 1024 * 1024,
424 .maxUniformBufferRange = UINT32_MAX,
425 .maxStorageBufferRange = UINT32_MAX,
426 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
427 .maxMemoryAllocationCount = UINT32_MAX,
428 .maxSamplerAllocationCount = 64 * 1024,
429 .bufferImageGranularity = 64, /* A cache line */
430 .sparseAddressSpaceSize = 0,
431 .maxBoundDescriptorSets = MAX_SETS,
432 .maxPerStageDescriptorSamplers = 64,
433 .maxPerStageDescriptorUniformBuffers = 64,
434 .maxPerStageDescriptorStorageBuffers = 64,
435 .maxPerStageDescriptorSampledImages = 64,
436 .maxPerStageDescriptorStorageImages = 64,
437 .maxPerStageDescriptorInputAttachments = 64,
438 .maxPerStageResources = 128,
439 .maxDescriptorSetSamplers = 256,
440 .maxDescriptorSetUniformBuffers = 256,
441 .maxDescriptorSetUniformBuffersDynamic = 256,
442 .maxDescriptorSetStorageBuffers = 256,
443 .maxDescriptorSetStorageBuffersDynamic = 256,
444 .maxDescriptorSetSampledImages = 256,
445 .maxDescriptorSetStorageImages = 256,
446 .maxDescriptorSetInputAttachments = 256,
447 .maxVertexInputAttributes = 32,
448 .maxVertexInputBindings = 32,
449 .maxVertexInputAttributeOffset = 2047,
450 .maxVertexInputBindingStride = 2048,
451 .maxVertexOutputComponents = 128,
452 .maxTessellationGenerationLevel = 0,
453 .maxTessellationPatchSize = 0,
454 .maxTessellationControlPerVertexInputComponents = 0,
455 .maxTessellationControlPerVertexOutputComponents = 0,
456 .maxTessellationControlPerPatchOutputComponents = 0,
457 .maxTessellationControlTotalOutputComponents = 0,
458 .maxTessellationEvaluationInputComponents = 0,
459 .maxTessellationEvaluationOutputComponents = 0,
460 .maxGeometryShaderInvocations = 32,
461 .maxGeometryInputComponents = 64,
462 .maxGeometryOutputComponents = 128,
463 .maxGeometryOutputVertices = 256,
464 .maxGeometryTotalOutputComponents = 1024,
465 .maxFragmentInputComponents = 128,
466 .maxFragmentOutputAttachments = 8,
467 .maxFragmentDualSrcAttachments = 2,
468 .maxFragmentCombinedOutputResources = 8,
469 .maxComputeSharedMemorySize = 32768,
470 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
471 .maxComputeWorkGroupInvocations = 16 * 1024,
472 .maxComputeWorkGroupSize = {
473 16 * 1024/*devinfo->max_cs_threads*/,
474 16 * 1024,
475 16 * 1024
476 },
477 .subPixelPrecisionBits = 4 /* FIXME */,
478 .subTexelPrecisionBits = 4 /* FIXME */,
479 .mipmapPrecisionBits = 4 /* FIXME */,
480 .maxDrawIndexedIndexValue = UINT32_MAX,
481 .maxDrawIndirectCount = UINT32_MAX,
482 .maxSamplerLodBias = 16,
483 .maxSamplerAnisotropy = 16,
484 .maxViewports = MAX_VIEWPORTS,
485 .maxViewportDimensions = { (1 << 14), (1 << 14) },
486 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
487 .viewportSubPixelBits = 13, /* We take a float? */
488 .minMemoryMapAlignment = 4096, /* A page */
489 .minTexelBufferOffsetAlignment = 1,
490 .minUniformBufferOffsetAlignment = 4,
491 .minStorageBufferOffsetAlignment = 4,
492 .minTexelOffset = -8,
493 .maxTexelOffset = 7,
494 .minTexelGatherOffset = -8,
495 .maxTexelGatherOffset = 7,
496 .minInterpolationOffset = 0, /* FIXME */
497 .maxInterpolationOffset = 0, /* FIXME */
498 .subPixelInterpolationOffsetBits = 0, /* FIXME */
499 .maxFramebufferWidth = (1 << 14),
500 .maxFramebufferHeight = (1 << 14),
501 .maxFramebufferLayers = (1 << 10),
502 .framebufferColorSampleCounts = sample_counts,
503 .framebufferDepthSampleCounts = sample_counts,
504 .framebufferStencilSampleCounts = sample_counts,
505 .framebufferNoAttachmentsSampleCounts = sample_counts,
506 .maxColorAttachments = MAX_RTS,
507 .sampledImageColorSampleCounts = sample_counts,
508 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
509 .sampledImageDepthSampleCounts = sample_counts,
510 .sampledImageStencilSampleCounts = sample_counts,
511 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
512 .maxSampleMaskWords = 1,
513 .timestampComputeAndGraphics = false,
514 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
515 .maxClipDistances = 8,
516 .maxCullDistances = 8,
517 .maxCombinedClipAndCullDistances = 8,
518 .discreteQueuePriorities = 1,
519 .pointSizeRange = { 0.125, 255.875 },
520 .lineWidthRange = { 0.0, 7.9921875 },
521 .pointSizeGranularity = (1.0 / 8.0),
522 .lineWidthGranularity = (1.0 / 128.0),
523 .strictLines = false, /* FINISHME */
524 .standardSampleLocations = true,
525 .optimalBufferCopyOffsetAlignment = 128,
526 .optimalBufferCopyRowPitchAlignment = 128,
527 .nonCoherentAtomSize = 64,
528 };
529
530 *pProperties = (VkPhysicalDeviceProperties) {
531 .apiVersion = VK_MAKE_VERSION(1, 0, 5),
532 .driverVersion = 1,
533 .vendorID = 0x1002,
534 .deviceID = pdevice->rad_info.pci_id,
535 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
536 .limits = limits,
537 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
538 };
539
540 strcpy(pProperties->deviceName, pdevice->name);
541 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
542 }
543
544 void radv_GetPhysicalDeviceQueueFamilyProperties(
545 VkPhysicalDevice physicalDevice,
546 uint32_t* pCount,
547 VkQueueFamilyProperties* pQueueFamilyProperties)
548 {
549 if (pQueueFamilyProperties == NULL) {
550 *pCount = 1;
551 return;
552 }
553 assert(*pCount >= 1);
554
555 *pQueueFamilyProperties = (VkQueueFamilyProperties) {
556 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
557 VK_QUEUE_COMPUTE_BIT |
558 VK_QUEUE_TRANSFER_BIT,
559 .queueCount = 1,
560 .timestampValidBits = 64,
561 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
562 };
563 }
564
565 void radv_GetPhysicalDeviceMemoryProperties(
566 VkPhysicalDevice physicalDevice,
567 VkPhysicalDeviceMemoryProperties* pMemoryProperties)
568 {
569 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
570
571 pMemoryProperties->memoryTypeCount = 4;
572 pMemoryProperties->memoryTypes[0] = (VkMemoryType) {
573 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
574 .heapIndex = 0,
575 };
576 pMemoryProperties->memoryTypes[1] = (VkMemoryType) {
577 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
578 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
579 .heapIndex = 2,
580 };
581 pMemoryProperties->memoryTypes[2] = (VkMemoryType) {
582 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
583 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
584 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
585 .heapIndex = 1,
586 };
587 pMemoryProperties->memoryTypes[3] = (VkMemoryType) {
588 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
589 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
590 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
591 .heapIndex = 2,
592 };
593
594 pMemoryProperties->memoryHeapCount = 3;
595 pMemoryProperties->memoryHeaps[0] = (VkMemoryHeap) {
596 .size = physical_device->rad_info.vram_size -
597 physical_device->rad_info.visible_vram_size,
598 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
599 };
600 pMemoryProperties->memoryHeaps[1] = (VkMemoryHeap) {
601 .size = physical_device->rad_info.visible_vram_size,
602 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
603 };
604 pMemoryProperties->memoryHeaps[2] = (VkMemoryHeap) {
605 .size = physical_device->rad_info.gart_size,
606 .flags = 0,
607 };
608 }
609
610 static VkResult
611 radv_queue_init(struct radv_device *device, struct radv_queue *queue)
612 {
613 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
614 queue->device = device;
615
616 return VK_SUCCESS;
617 }
618
619 static void
620 radv_queue_finish(struct radv_queue *queue)
621 {
622 }
623
624 VkResult radv_CreateDevice(
625 VkPhysicalDevice physicalDevice,
626 const VkDeviceCreateInfo* pCreateInfo,
627 const VkAllocationCallbacks* pAllocator,
628 VkDevice* pDevice)
629 {
630 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
631 VkResult result;
632 struct radv_device *device;
633
634 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
635 bool found = false;
636 for (uint32_t j = 0; j < ARRAY_SIZE(device_extensions); j++) {
637 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
638 device_extensions[j].extensionName) == 0) {
639 found = true;
640 break;
641 }
642 }
643 if (!found)
644 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
645 }
646
647 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
648 sizeof(*device), 8,
649 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
650 if (!device)
651 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
652
653 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
654 device->instance = physical_device->instance;
655
656 device->ws = physical_device->ws;
657 if (pAllocator)
658 device->alloc = *pAllocator;
659 else
660 device->alloc = physical_device->instance->alloc;
661
662 device->hw_ctx = device->ws->ctx_create(device->ws);
663 if (!device->hw_ctx) {
664 result = VK_ERROR_OUT_OF_HOST_MEMORY;
665 goto fail_free;
666 }
667
668 radv_queue_init(device, &device->queue);
669
670 result = radv_device_init_meta(device);
671 if (result != VK_SUCCESS) {
672 device->ws->ctx_destroy(device->hw_ctx);
673 goto fail_free;
674 }
675 device->allow_fast_clears = env_var_as_boolean("RADV_FAST_CLEARS", false);
676 device->allow_dcc = !env_var_as_boolean("RADV_DCC_DISABLE", false);
677 device->shader_stats_dump = env_var_as_boolean("RADV_SHADER_STATS", false);
678
679 if (device->allow_fast_clears && device->allow_dcc)
680 radv_finishme("DCC fast clears have not been tested\n");
681
682 radv_device_init_msaa(device);
683 device->empty_cs = device->ws->cs_create(device->ws, RING_GFX);
684 radeon_emit(device->empty_cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
685 radeon_emit(device->empty_cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
686 radeon_emit(device->empty_cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
687 device->ws->cs_finalize(device->empty_cs);
688 *pDevice = radv_device_to_handle(device);
689 return VK_SUCCESS;
690 fail_free:
691 vk_free(&device->alloc, device);
692 return result;
693 }
694
695 void radv_DestroyDevice(
696 VkDevice _device,
697 const VkAllocationCallbacks* pAllocator)
698 {
699 RADV_FROM_HANDLE(radv_device, device, _device);
700
701 device->ws->ctx_destroy(device->hw_ctx);
702 radv_queue_finish(&device->queue);
703 radv_device_finish_meta(device);
704
705 vk_free(&device->alloc, device);
706 }
707
708 VkResult radv_EnumerateInstanceExtensionProperties(
709 const char* pLayerName,
710 uint32_t* pPropertyCount,
711 VkExtensionProperties* pProperties)
712 {
713 unsigned i;
714 if (pProperties == NULL) {
715 *pPropertyCount = ARRAY_SIZE(global_extensions);
716 return VK_SUCCESS;
717 }
718
719 for (i = 0; i < *pPropertyCount; i++)
720 memcpy(&pProperties[i], &global_extensions[i], sizeof(VkExtensionProperties));
721
722 *pPropertyCount = i;
723 if (i < ARRAY_SIZE(global_extensions))
724 return VK_INCOMPLETE;
725
726 return VK_SUCCESS;
727 }
728
729 VkResult radv_EnumerateDeviceExtensionProperties(
730 VkPhysicalDevice physicalDevice,
731 const char* pLayerName,
732 uint32_t* pPropertyCount,
733 VkExtensionProperties* pProperties)
734 {
735 unsigned i;
736
737 if (pProperties == NULL) {
738 *pPropertyCount = ARRAY_SIZE(device_extensions);
739 return VK_SUCCESS;
740 }
741
742 for (i = 0; i < *pPropertyCount; i++)
743 memcpy(&pProperties[i], &device_extensions[i], sizeof(VkExtensionProperties));
744
745 *pPropertyCount = i;
746 if (i < ARRAY_SIZE(device_extensions))
747 return VK_INCOMPLETE;
748 return VK_SUCCESS;
749 }
750
751 VkResult radv_EnumerateInstanceLayerProperties(
752 uint32_t* pPropertyCount,
753 VkLayerProperties* pProperties)
754 {
755 if (pProperties == NULL) {
756 *pPropertyCount = 0;
757 return VK_SUCCESS;
758 }
759
760 /* None supported at this time */
761 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
762 }
763
764 VkResult radv_EnumerateDeviceLayerProperties(
765 VkPhysicalDevice physicalDevice,
766 uint32_t* pPropertyCount,
767 VkLayerProperties* pProperties)
768 {
769 if (pProperties == NULL) {
770 *pPropertyCount = 0;
771 return VK_SUCCESS;
772 }
773
774 /* None supported at this time */
775 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
776 }
777
778 void radv_GetDeviceQueue(
779 VkDevice _device,
780 uint32_t queueNodeIndex,
781 uint32_t queueIndex,
782 VkQueue* pQueue)
783 {
784 RADV_FROM_HANDLE(radv_device, device, _device);
785
786 assert(queueIndex == 0);
787
788 *pQueue = radv_queue_to_handle(&device->queue);
789 }
790
791 VkResult radv_QueueSubmit(
792 VkQueue _queue,
793 uint32_t submitCount,
794 const VkSubmitInfo* pSubmits,
795 VkFence _fence)
796 {
797 RADV_FROM_HANDLE(radv_queue, queue, _queue);
798 RADV_FROM_HANDLE(radv_fence, fence, _fence);
799 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
800 struct radeon_winsys_ctx *ctx = queue->device->hw_ctx;
801 int ret;
802
803 for (uint32_t i = 0; i < submitCount; i++) {
804 struct radeon_winsys_cs **cs_array;
805 bool can_patch = true;
806
807 if (!pSubmits[i].commandBufferCount)
808 continue;
809
810 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
811 pSubmits[i].commandBufferCount);
812
813 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
814 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
815 pSubmits[i].pCommandBuffers[j]);
816 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
817
818 cs_array[j] = cmd_buffer->cs;
819 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
820 can_patch = false;
821 }
822 ret = queue->device->ws->cs_submit(ctx, cs_array,
823 pSubmits[i].commandBufferCount,
824 can_patch, base_fence);
825 if (ret)
826 radv_loge("failed to submit CS %d\n", i);
827 free(cs_array);
828 }
829
830 if (fence) {
831 if (!submitCount)
832 ret = queue->device->ws->cs_submit(ctx, &queue->device->empty_cs,
833 1, false, base_fence);
834
835 fence->submitted = true;
836 }
837
838 return VK_SUCCESS;
839 }
840
841 VkResult radv_QueueWaitIdle(
842 VkQueue _queue)
843 {
844 RADV_FROM_HANDLE(radv_queue, queue, _queue);
845
846 queue->device->ws->ctx_wait_idle(queue->device->hw_ctx);
847 return VK_SUCCESS;
848 }
849
850 VkResult radv_DeviceWaitIdle(
851 VkDevice _device)
852 {
853 RADV_FROM_HANDLE(radv_device, device, _device);
854
855 device->ws->ctx_wait_idle(device->hw_ctx);
856 return VK_SUCCESS;
857 }
858
859 PFN_vkVoidFunction radv_GetInstanceProcAddr(
860 VkInstance instance,
861 const char* pName)
862 {
863 return radv_lookup_entrypoint(pName);
864 }
865
866 /* The loader wants us to expose a second GetInstanceProcAddr function
867 * to work around certain LD_PRELOAD issues seen in apps.
868 */
869 PUBLIC
870 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
871 VkInstance instance,
872 const char* pName);
873
874 PUBLIC
875 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
876 VkInstance instance,
877 const char* pName)
878 {
879 return radv_GetInstanceProcAddr(instance, pName);
880 }
881
882 PFN_vkVoidFunction radv_GetDeviceProcAddr(
883 VkDevice device,
884 const char* pName)
885 {
886 return radv_lookup_entrypoint(pName);
887 }
888
889 VkResult radv_AllocateMemory(
890 VkDevice _device,
891 const VkMemoryAllocateInfo* pAllocateInfo,
892 const VkAllocationCallbacks* pAllocator,
893 VkDeviceMemory* pMem)
894 {
895 RADV_FROM_HANDLE(radv_device, device, _device);
896 struct radv_device_memory *mem;
897 VkResult result;
898 enum radeon_bo_domain domain;
899 uint32_t flags = 0;
900 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
901
902 if (pAllocateInfo->allocationSize == 0) {
903 /* Apparently, this is allowed */
904 *pMem = VK_NULL_HANDLE;
905 return VK_SUCCESS;
906 }
907
908 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
909 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
910 if (mem == NULL)
911 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
912
913 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
914 if (pAllocateInfo->memoryTypeIndex == 1 || pAllocateInfo->memoryTypeIndex == 3)
915 domain = RADEON_DOMAIN_GTT;
916 else
917 domain = RADEON_DOMAIN_VRAM;
918
919 if (pAllocateInfo->memoryTypeIndex == 0)
920 flags |= RADEON_FLAG_NO_CPU_ACCESS;
921 else
922 flags |= RADEON_FLAG_CPU_ACCESS;
923
924 if (pAllocateInfo->memoryTypeIndex == 1)
925 flags |= RADEON_FLAG_GTT_WC;
926
927 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 32768,
928 domain, flags);
929
930 if (!mem->bo) {
931 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
932 goto fail;
933 }
934 mem->type_index = pAllocateInfo->memoryTypeIndex;
935
936 *pMem = radv_device_memory_to_handle(mem);
937
938 return VK_SUCCESS;
939
940 fail:
941 vk_free2(&device->alloc, pAllocator, mem);
942
943 return result;
944 }
945
946 void radv_FreeMemory(
947 VkDevice _device,
948 VkDeviceMemory _mem,
949 const VkAllocationCallbacks* pAllocator)
950 {
951 RADV_FROM_HANDLE(radv_device, device, _device);
952 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
953
954 if (mem == NULL)
955 return;
956
957 device->ws->buffer_destroy(mem->bo);
958 mem->bo = NULL;
959
960 vk_free2(&device->alloc, pAllocator, mem);
961 }
962
963 VkResult radv_MapMemory(
964 VkDevice _device,
965 VkDeviceMemory _memory,
966 VkDeviceSize offset,
967 VkDeviceSize size,
968 VkMemoryMapFlags flags,
969 void** ppData)
970 {
971 RADV_FROM_HANDLE(radv_device, device, _device);
972 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
973
974 if (mem == NULL) {
975 *ppData = NULL;
976 return VK_SUCCESS;
977 }
978
979 *ppData = device->ws->buffer_map(mem->bo);
980 if (*ppData) {
981 *ppData += offset;
982 return VK_SUCCESS;
983 }
984
985 return VK_ERROR_MEMORY_MAP_FAILED;
986 }
987
988 void radv_UnmapMemory(
989 VkDevice _device,
990 VkDeviceMemory _memory)
991 {
992 RADV_FROM_HANDLE(radv_device, device, _device);
993 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
994
995 if (mem == NULL)
996 return;
997
998 device->ws->buffer_unmap(mem->bo);
999 }
1000
1001 VkResult radv_FlushMappedMemoryRanges(
1002 VkDevice _device,
1003 uint32_t memoryRangeCount,
1004 const VkMappedMemoryRange* pMemoryRanges)
1005 {
1006 return VK_SUCCESS;
1007 }
1008
1009 VkResult radv_InvalidateMappedMemoryRanges(
1010 VkDevice _device,
1011 uint32_t memoryRangeCount,
1012 const VkMappedMemoryRange* pMemoryRanges)
1013 {
1014 return VK_SUCCESS;
1015 }
1016
1017 void radv_GetBufferMemoryRequirements(
1018 VkDevice device,
1019 VkBuffer _buffer,
1020 VkMemoryRequirements* pMemoryRequirements)
1021 {
1022 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1023
1024 /* The Vulkan spec (git aaed022) says:
1025 *
1026 * memoryTypeBits is a bitfield and contains one bit set for every
1027 * supported memory type for the resource. The bit `1<<i` is set if and
1028 * only if the memory type `i` in the VkPhysicalDeviceMemoryProperties
1029 * structure for the physical device is supported.
1030 *
1031 * We support exactly one memory type.
1032 */
1033 pMemoryRequirements->memoryTypeBits = 0x7;
1034
1035 pMemoryRequirements->size = buffer->size;
1036 pMemoryRequirements->alignment = 16;
1037 }
1038
1039 void radv_GetImageMemoryRequirements(
1040 VkDevice device,
1041 VkImage _image,
1042 VkMemoryRequirements* pMemoryRequirements)
1043 {
1044 RADV_FROM_HANDLE(radv_image, image, _image);
1045
1046 /* The Vulkan spec (git aaed022) says:
1047 *
1048 * memoryTypeBits is a bitfield and contains one bit set for every
1049 * supported memory type for the resource. The bit `1<<i` is set if and
1050 * only if the memory type `i` in the VkPhysicalDeviceMemoryProperties
1051 * structure for the physical device is supported.
1052 *
1053 * We support exactly one memory type.
1054 */
1055 pMemoryRequirements->memoryTypeBits = 0x7;
1056
1057 pMemoryRequirements->size = image->size;
1058 pMemoryRequirements->alignment = image->alignment;
1059 }
1060
1061 void radv_GetImageSparseMemoryRequirements(
1062 VkDevice device,
1063 VkImage image,
1064 uint32_t* pSparseMemoryRequirementCount,
1065 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
1066 {
1067 stub();
1068 }
1069
1070 void radv_GetDeviceMemoryCommitment(
1071 VkDevice device,
1072 VkDeviceMemory memory,
1073 VkDeviceSize* pCommittedMemoryInBytes)
1074 {
1075 *pCommittedMemoryInBytes = 0;
1076 }
1077
1078 VkResult radv_BindBufferMemory(
1079 VkDevice device,
1080 VkBuffer _buffer,
1081 VkDeviceMemory _memory,
1082 VkDeviceSize memoryOffset)
1083 {
1084 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1085 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1086
1087 if (mem) {
1088 buffer->bo = mem->bo;
1089 buffer->offset = memoryOffset;
1090 } else {
1091 buffer->bo = NULL;
1092 buffer->offset = 0;
1093 }
1094
1095 return VK_SUCCESS;
1096 }
1097
1098 VkResult radv_BindImageMemory(
1099 VkDevice device,
1100 VkImage _image,
1101 VkDeviceMemory _memory,
1102 VkDeviceSize memoryOffset)
1103 {
1104 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1105 RADV_FROM_HANDLE(radv_image, image, _image);
1106
1107 if (mem) {
1108 image->bo = mem->bo;
1109 image->offset = memoryOffset;
1110 } else {
1111 image->bo = NULL;
1112 image->offset = 0;
1113 }
1114
1115 return VK_SUCCESS;
1116 }
1117
1118 VkResult radv_QueueBindSparse(
1119 VkQueue queue,
1120 uint32_t bindInfoCount,
1121 const VkBindSparseInfo* pBindInfo,
1122 VkFence fence)
1123 {
1124 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER);
1125 }
1126
1127 VkResult radv_CreateFence(
1128 VkDevice _device,
1129 const VkFenceCreateInfo* pCreateInfo,
1130 const VkAllocationCallbacks* pAllocator,
1131 VkFence* pFence)
1132 {
1133 RADV_FROM_HANDLE(radv_device, device, _device);
1134 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
1135 sizeof(*fence), 8,
1136 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1137
1138 if (!fence)
1139 return VK_ERROR_OUT_OF_HOST_MEMORY;
1140
1141 memset(fence, 0, sizeof(*fence));
1142 fence->submitted = false;
1143 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
1144 fence->fence = device->ws->create_fence();
1145
1146
1147 *pFence = radv_fence_to_handle(fence);
1148
1149 return VK_SUCCESS;
1150 }
1151
1152 void radv_DestroyFence(
1153 VkDevice _device,
1154 VkFence _fence,
1155 const VkAllocationCallbacks* pAllocator)
1156 {
1157 RADV_FROM_HANDLE(radv_device, device, _device);
1158 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1159
1160 if (!fence)
1161 return;
1162 device->ws->destroy_fence(fence->fence);
1163 vk_free2(&device->alloc, pAllocator, fence);
1164 }
1165
1166 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
1167 {
1168 uint64_t current_time;
1169 struct timespec tv;
1170
1171 clock_gettime(CLOCK_MONOTONIC, &tv);
1172 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
1173
1174 timeout = MIN2(UINT64_MAX - current_time, timeout);
1175
1176 return current_time + timeout;
1177 }
1178
1179 VkResult radv_WaitForFences(
1180 VkDevice _device,
1181 uint32_t fenceCount,
1182 const VkFence* pFences,
1183 VkBool32 waitAll,
1184 uint64_t timeout)
1185 {
1186 RADV_FROM_HANDLE(radv_device, device, _device);
1187 timeout = radv_get_absolute_timeout(timeout);
1188
1189 if (!waitAll && fenceCount > 1) {
1190 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
1191 }
1192
1193 for (uint32_t i = 0; i < fenceCount; ++i) {
1194 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1195 bool expired = false;
1196
1197 if (fence->signalled)
1198 continue;
1199
1200 if (!fence->submitted)
1201 return VK_TIMEOUT;
1202
1203 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
1204 if (!expired)
1205 return VK_TIMEOUT;
1206
1207 fence->signalled = true;
1208 }
1209
1210 return VK_SUCCESS;
1211 }
1212
1213 VkResult radv_ResetFences(VkDevice device,
1214 uint32_t fenceCount,
1215 const VkFence *pFences)
1216 {
1217 for (unsigned i = 0; i < fenceCount; ++i) {
1218 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1219 fence->submitted = fence->signalled = false;
1220 }
1221
1222 return VK_SUCCESS;
1223 }
1224
1225 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
1226 {
1227 RADV_FROM_HANDLE(radv_device, device, _device);
1228 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1229
1230 if (fence->signalled)
1231 return VK_SUCCESS;
1232 if (!fence->submitted)
1233 return VK_NOT_READY;
1234
1235 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
1236 return VK_NOT_READY;
1237
1238 return VK_SUCCESS;
1239 }
1240
1241
1242 // Queue semaphore functions
1243
1244 VkResult radv_CreateSemaphore(
1245 VkDevice device,
1246 const VkSemaphoreCreateInfo* pCreateInfo,
1247 const VkAllocationCallbacks* pAllocator,
1248 VkSemaphore* pSemaphore)
1249 {
1250 /* The DRM execbuffer ioctl always execute in-oder, even between different
1251 * rings. As such, there's nothing to do for the user space semaphore.
1252 */
1253
1254 *pSemaphore = (VkSemaphore)1;
1255
1256 return VK_SUCCESS;
1257 }
1258
1259 void radv_DestroySemaphore(
1260 VkDevice device,
1261 VkSemaphore semaphore,
1262 const VkAllocationCallbacks* pAllocator)
1263 {
1264 }
1265
1266 VkResult radv_CreateEvent(
1267 VkDevice _device,
1268 const VkEventCreateInfo* pCreateInfo,
1269 const VkAllocationCallbacks* pAllocator,
1270 VkEvent* pEvent)
1271 {
1272 RADV_FROM_HANDLE(radv_device, device, _device);
1273 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
1274 sizeof(*event), 8,
1275 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1276
1277 if (!event)
1278 return VK_ERROR_OUT_OF_HOST_MEMORY;
1279
1280 event->bo = device->ws->buffer_create(device->ws, 8, 8,
1281 RADEON_DOMAIN_GTT,
1282 RADEON_FLAG_CPU_ACCESS);
1283 if (!event->bo) {
1284 vk_free2(&device->alloc, pAllocator, event);
1285 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1286 }
1287
1288 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
1289
1290 *pEvent = radv_event_to_handle(event);
1291
1292 return VK_SUCCESS;
1293 }
1294
1295 void radv_DestroyEvent(
1296 VkDevice _device,
1297 VkEvent _event,
1298 const VkAllocationCallbacks* pAllocator)
1299 {
1300 RADV_FROM_HANDLE(radv_device, device, _device);
1301 RADV_FROM_HANDLE(radv_event, event, _event);
1302
1303 if (!event)
1304 return;
1305 device->ws->buffer_destroy(event->bo);
1306 vk_free2(&device->alloc, pAllocator, event);
1307 }
1308
1309 VkResult radv_GetEventStatus(
1310 VkDevice _device,
1311 VkEvent _event)
1312 {
1313 RADV_FROM_HANDLE(radv_event, event, _event);
1314
1315 if (*event->map == 1)
1316 return VK_EVENT_SET;
1317 return VK_EVENT_RESET;
1318 }
1319
1320 VkResult radv_SetEvent(
1321 VkDevice _device,
1322 VkEvent _event)
1323 {
1324 RADV_FROM_HANDLE(radv_event, event, _event);
1325 *event->map = 1;
1326
1327 return VK_SUCCESS;
1328 }
1329
1330 VkResult radv_ResetEvent(
1331 VkDevice _device,
1332 VkEvent _event)
1333 {
1334 RADV_FROM_HANDLE(radv_event, event, _event);
1335 *event->map = 0;
1336
1337 return VK_SUCCESS;
1338 }
1339
1340 VkResult radv_CreateBuffer(
1341 VkDevice _device,
1342 const VkBufferCreateInfo* pCreateInfo,
1343 const VkAllocationCallbacks* pAllocator,
1344 VkBuffer* pBuffer)
1345 {
1346 RADV_FROM_HANDLE(radv_device, device, _device);
1347 struct radv_buffer *buffer;
1348
1349 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
1350
1351 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
1352 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1353 if (buffer == NULL)
1354 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1355
1356 buffer->size = pCreateInfo->size;
1357 buffer->usage = pCreateInfo->usage;
1358 buffer->bo = NULL;
1359 buffer->offset = 0;
1360
1361 *pBuffer = radv_buffer_to_handle(buffer);
1362
1363 return VK_SUCCESS;
1364 }
1365
1366 void radv_DestroyBuffer(
1367 VkDevice _device,
1368 VkBuffer _buffer,
1369 const VkAllocationCallbacks* pAllocator)
1370 {
1371 RADV_FROM_HANDLE(radv_device, device, _device);
1372 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1373
1374 if (!buffer)
1375 return;
1376
1377 vk_free2(&device->alloc, pAllocator, buffer);
1378 }
1379
1380 static inline unsigned
1381 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
1382 {
1383 if (stencil)
1384 return image->surface.stencil_tiling_index[level];
1385 else
1386 return image->surface.tiling_index[level];
1387 }
1388
1389 static void
1390 radv_initialise_color_surface(struct radv_device *device,
1391 struct radv_color_buffer_info *cb,
1392 struct radv_image_view *iview)
1393 {
1394 const struct vk_format_description *desc;
1395 unsigned ntype, format, swap, endian;
1396 unsigned blend_clamp = 0, blend_bypass = 0;
1397 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
1398 uint64_t va;
1399 const struct radeon_surf *surf = &iview->image->surface;
1400 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
1401
1402 desc = vk_format_description(iview->vk_format);
1403
1404 memset(cb, 0, sizeof(*cb));
1405
1406 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1407 va += level_info->offset;
1408 cb->cb_color_base = va >> 8;
1409
1410 /* CMASK variables */
1411 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1412 va += iview->image->cmask.offset;
1413 cb->cb_color_cmask = va >> 8;
1414 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
1415
1416 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1417 va += iview->image->dcc_offset;
1418 cb->cb_dcc_base = va >> 8;
1419
1420 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
1421 S_028C6C_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1422
1423 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
1424 pitch_tile_max = level_info->nblk_x / 8 - 1;
1425 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
1426 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
1427
1428 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
1429 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
1430
1431 /* Intensity is implemented as Red, so treat it that way. */
1432 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
1433 S_028C74_TILE_MODE_INDEX(tile_mode_index);
1434
1435 if (iview->image->samples > 1) {
1436 unsigned log_samples = util_logbase2(iview->image->samples);
1437
1438 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1439 S_028C74_NUM_FRAGMENTS(log_samples);
1440 }
1441
1442 if (iview->image->fmask.size) {
1443 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
1444 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1445 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
1446 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
1447 cb->cb_color_fmask = va >> 8;
1448 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
1449 } else {
1450 /* This must be set for fast clear to work without FMASK. */
1451 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1452 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
1453 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1454 cb->cb_color_fmask = cb->cb_color_base;
1455 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
1456 }
1457
1458 ntype = radv_translate_color_numformat(iview->vk_format,
1459 desc,
1460 vk_format_get_first_non_void_channel(iview->vk_format));
1461 format = radv_translate_colorformat(iview->vk_format);
1462 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
1463 radv_finishme("Illegal color\n");
1464 swap = radv_translate_colorswap(iview->vk_format, FALSE);
1465 endian = radv_colorformat_endian_swap(format);
1466
1467 /* blend clamp should be set for all NORM/SRGB types */
1468 if (ntype == V_028C70_NUMBER_UNORM ||
1469 ntype == V_028C70_NUMBER_SNORM ||
1470 ntype == V_028C70_NUMBER_SRGB)
1471 blend_clamp = 1;
1472
1473 /* set blend bypass according to docs if SINT/UINT or
1474 8/24 COLOR variants */
1475 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1476 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1477 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1478 blend_clamp = 0;
1479 blend_bypass = 1;
1480 }
1481 #if 0
1482 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
1483 (format == V_028C70_COLOR_8 ||
1484 format == V_028C70_COLOR_8_8 ||
1485 format == V_028C70_COLOR_8_8_8_8))
1486 ->color_is_int8 = true;
1487 #endif
1488 cb->cb_color_info = S_028C70_FORMAT(format) |
1489 S_028C70_COMP_SWAP(swap) |
1490 S_028C70_BLEND_CLAMP(blend_clamp) |
1491 S_028C70_BLEND_BYPASS(blend_bypass) |
1492 S_028C70_SIMPLE_FLOAT(1) |
1493 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
1494 ntype != V_028C70_NUMBER_SNORM &&
1495 ntype != V_028C70_NUMBER_SRGB &&
1496 format != V_028C70_COLOR_8_24 &&
1497 format != V_028C70_COLOR_24_8) |
1498 S_028C70_NUMBER_TYPE(ntype) |
1499 S_028C70_ENDIAN(endian);
1500 if (iview->image->samples > 1)
1501 if (iview->image->fmask.size)
1502 cb->cb_color_info |= S_028C70_COMPRESSION(1);
1503
1504 if (iview->image->cmask.size && device->allow_fast_clears)
1505 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
1506
1507 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
1508 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
1509
1510 if (device->instance->physicalDevice.rad_info.chip_class >= VI) {
1511 unsigned max_uncompressed_block_size = 2;
1512 if (iview->image->samples > 1) {
1513 if (iview->image->surface.bpe == 1)
1514 max_uncompressed_block_size = 0;
1515 else if (iview->image->surface.bpe == 2)
1516 max_uncompressed_block_size = 1;
1517 }
1518
1519 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
1520 S_028C78_INDEPENDENT_64B_BLOCKS(1);
1521 }
1522
1523 /* This must be set for fast clear to work without FMASK. */
1524 if (!iview->image->fmask.size &&
1525 device->instance->physicalDevice.rad_info.chip_class == SI) {
1526 unsigned bankh = util_logbase2(iview->image->surface.bankh);
1527 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1528 }
1529 }
1530
1531 static void
1532 radv_initialise_ds_surface(struct radv_device *device,
1533 struct radv_ds_buffer_info *ds,
1534 struct radv_image_view *iview)
1535 {
1536 unsigned level = iview->base_mip;
1537 unsigned format;
1538 uint64_t va, s_offs, z_offs;
1539 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
1540 memset(ds, 0, sizeof(*ds));
1541 switch (iview->vk_format) {
1542 case VK_FORMAT_D24_UNORM_S8_UINT:
1543 case VK_FORMAT_X8_D24_UNORM_PACK32:
1544 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1545 ds->offset_scale = 2.0f;
1546 break;
1547 case VK_FORMAT_D16_UNORM:
1548 case VK_FORMAT_D16_UNORM_S8_UINT:
1549 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1550 ds->offset_scale = 4.0f;
1551 break;
1552 case VK_FORMAT_D32_SFLOAT:
1553 case VK_FORMAT_D32_SFLOAT_S8_UINT:
1554 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1555 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1556 ds->offset_scale = 1.0f;
1557 break;
1558 default:
1559 break;
1560 }
1561
1562 format = radv_translate_dbformat(iview->vk_format);
1563 if (format == V_028040_Z_INVALID) {
1564 fprintf(stderr, "Invalid DB format: %d, disabling DB.\n", iview->vk_format);
1565 }
1566
1567 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1568 s_offs = z_offs = va;
1569 z_offs += iview->image->surface.level[level].offset;
1570 s_offs += iview->image->surface.stencil_level[level].offset;
1571
1572 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
1573 S_028008_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1574 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1575 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
1576
1577 if (iview->image->samples > 1)
1578 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
1579
1580 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
1581 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
1582 else
1583 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1584
1585 if (device->instance->physicalDevice.rad_info.chip_class >= CIK) {
1586 struct radeon_info *info = &device->instance->physicalDevice.rad_info;
1587 unsigned tiling_index = iview->image->surface.tiling_index[level];
1588 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
1589 unsigned macro_index = iview->image->surface.macro_tile_index;
1590 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
1591 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
1592 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
1593
1594 ds->db_depth_info |=
1595 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
1596 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
1597 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
1598 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
1599 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
1600 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
1601 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
1602 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
1603 } else {
1604 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
1605 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1606 tile_mode_index = si_tile_mode_index(iview->image, level, true);
1607 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1608 }
1609
1610 if (iview->image->htile.size && !level) {
1611 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1612 S_028040_ALLOW_EXPCLEAR(1);
1613
1614 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
1615 /* Workaround: For a not yet understood reason, the
1616 * combination of MSAA, fast stencil clear and stencil
1617 * decompress messes with subsequent stencil buffer
1618 * uses. Problem was reproduced on Verde, Bonaire,
1619 * Tonga, and Carrizo.
1620 *
1621 * Disabling EXPCLEAR works around the problem.
1622 *
1623 * Check piglit's arb_texture_multisample-stencil-clear
1624 * test if you want to try changing this.
1625 */
1626 if (iview->image->samples <= 1)
1627 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
1628 } else
1629 /* Use all of the htile_buffer for depth if there's no stencil. */
1630 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1631
1632 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
1633 iview->image->htile.offset;
1634 ds->db_htile_data_base = va >> 8;
1635 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
1636 } else {
1637 ds->db_htile_data_base = 0;
1638 ds->db_htile_surface = 0;
1639 }
1640
1641 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
1642 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
1643
1644 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
1645 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
1646 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
1647 }
1648
1649 VkResult radv_CreateFramebuffer(
1650 VkDevice _device,
1651 const VkFramebufferCreateInfo* pCreateInfo,
1652 const VkAllocationCallbacks* pAllocator,
1653 VkFramebuffer* pFramebuffer)
1654 {
1655 RADV_FROM_HANDLE(radv_device, device, _device);
1656 struct radv_framebuffer *framebuffer;
1657
1658 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
1659
1660 size_t size = sizeof(*framebuffer) +
1661 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
1662 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
1663 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1664 if (framebuffer == NULL)
1665 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1666
1667 framebuffer->attachment_count = pCreateInfo->attachmentCount;
1668 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
1669 VkImageView _iview = pCreateInfo->pAttachments[i];
1670 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
1671 framebuffer->attachments[i].attachment = iview;
1672 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
1673 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
1674 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
1675 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
1676 }
1677 }
1678
1679 framebuffer->width = pCreateInfo->width;
1680 framebuffer->height = pCreateInfo->height;
1681 framebuffer->layers = pCreateInfo->layers;
1682
1683 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
1684 return VK_SUCCESS;
1685 }
1686
1687 void radv_DestroyFramebuffer(
1688 VkDevice _device,
1689 VkFramebuffer _fb,
1690 const VkAllocationCallbacks* pAllocator)
1691 {
1692 RADV_FROM_HANDLE(radv_device, device, _device);
1693 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
1694
1695 if (!fb)
1696 return;
1697 vk_free2(&device->alloc, pAllocator, fb);
1698 }
1699
1700 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
1701 {
1702 switch (address_mode) {
1703 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
1704 return V_008F30_SQ_TEX_WRAP;
1705 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
1706 return V_008F30_SQ_TEX_MIRROR;
1707 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
1708 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1709 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
1710 return V_008F30_SQ_TEX_CLAMP_BORDER;
1711 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
1712 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1713 default:
1714 unreachable("illegal tex wrap mode");
1715 break;
1716 }
1717 }
1718
1719 static unsigned
1720 radv_tex_compare(VkCompareOp op)
1721 {
1722 switch (op) {
1723 case VK_COMPARE_OP_NEVER:
1724 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1725 case VK_COMPARE_OP_LESS:
1726 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1727 case VK_COMPARE_OP_EQUAL:
1728 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1729 case VK_COMPARE_OP_LESS_OR_EQUAL:
1730 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1731 case VK_COMPARE_OP_GREATER:
1732 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1733 case VK_COMPARE_OP_NOT_EQUAL:
1734 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1735 case VK_COMPARE_OP_GREATER_OR_EQUAL:
1736 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1737 case VK_COMPARE_OP_ALWAYS:
1738 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1739 default:
1740 unreachable("illegal compare mode");
1741 break;
1742 }
1743 }
1744
1745 static unsigned
1746 radv_tex_filter(VkFilter filter, unsigned max_ansio)
1747 {
1748 switch (filter) {
1749 case VK_FILTER_NEAREST:
1750 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
1751 V_008F38_SQ_TEX_XY_FILTER_POINT);
1752 case VK_FILTER_LINEAR:
1753 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
1754 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
1755 case VK_FILTER_CUBIC_IMG:
1756 default:
1757 fprintf(stderr, "illegal texture filter");
1758 return 0;
1759 }
1760 }
1761
1762 static unsigned
1763 radv_tex_mipfilter(VkSamplerMipmapMode mode)
1764 {
1765 switch (mode) {
1766 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
1767 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1768 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
1769 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1770 default:
1771 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1772 }
1773 }
1774
1775 static unsigned
1776 radv_tex_bordercolor(VkBorderColor bcolor)
1777 {
1778 switch (bcolor) {
1779 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
1780 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
1781 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
1782 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
1783 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
1784 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
1785 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
1786 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
1787 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
1788 default:
1789 break;
1790 }
1791 return 0;
1792 }
1793
1794 static unsigned
1795 radv_tex_aniso_filter(unsigned filter)
1796 {
1797 if (filter < 2)
1798 return 0;
1799 if (filter < 4)
1800 return 1;
1801 if (filter < 8)
1802 return 2;
1803 if (filter < 16)
1804 return 3;
1805 return 4;
1806 }
1807
1808 static void
1809 radv_init_sampler(struct radv_device *device,
1810 struct radv_sampler *sampler,
1811 const VkSamplerCreateInfo *pCreateInfo)
1812 {
1813 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
1814 (uint32_t) pCreateInfo->maxAnisotropy : 0;
1815 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
1816 bool is_vi = (device->instance->physicalDevice.rad_info.chip_class >= VI);
1817
1818 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
1819 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
1820 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
1821 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
1822 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
1823 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
1824 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
1825 S_008F30_ANISO_BIAS(max_aniso_ratio) |
1826 S_008F30_DISABLE_CUBE_WRAP(0) |
1827 S_008F30_COMPAT_MODE(is_vi));
1828 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
1829 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
1830 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
1831 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
1832 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
1833 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
1834 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
1835 S_008F38_MIP_POINT_PRECLAMP(1) |
1836 S_008F38_DISABLE_LSB_CEIL(1) |
1837 S_008F38_FILTER_PREC_FIX(1) |
1838 S_008F38_ANISO_OVERRIDE(is_vi));
1839 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
1840 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
1841 }
1842
1843 VkResult radv_CreateSampler(
1844 VkDevice _device,
1845 const VkSamplerCreateInfo* pCreateInfo,
1846 const VkAllocationCallbacks* pAllocator,
1847 VkSampler* pSampler)
1848 {
1849 RADV_FROM_HANDLE(radv_device, device, _device);
1850 struct radv_sampler *sampler;
1851
1852 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
1853
1854 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
1855 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1856 if (!sampler)
1857 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1858
1859 radv_init_sampler(device, sampler, pCreateInfo);
1860 *pSampler = radv_sampler_to_handle(sampler);
1861
1862 return VK_SUCCESS;
1863 }
1864
1865 void radv_DestroySampler(
1866 VkDevice _device,
1867 VkSampler _sampler,
1868 const VkAllocationCallbacks* pAllocator)
1869 {
1870 RADV_FROM_HANDLE(radv_device, device, _device);
1871 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
1872
1873 if (!sampler)
1874 return;
1875 vk_free2(&device->alloc, pAllocator, sampler);
1876 }