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radv/winsys: Add binary syncobj ABI changes for timeline semaphores.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "dirent.h"
29 #include <errno.h>
30 #include <fcntl.h>
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
36 #include <stdbool.h>
37 #include <stddef.h>
38 #include <stdio.h>
39 #include <string.h>
40 #include <sys/prctl.h>
41 #include <sys/wait.h>
42 #include <unistd.h>
43 #include <fcntl.h>
44
45 #include "radv_debug.h"
46 #include "radv_private.h"
47 #include "radv_shader.h"
48 #include "radv_cs.h"
49 #include "util/disk_cache.h"
50 #include "vk_util.h"
51 #include <xf86drm.h>
52 #include <amdgpu.h>
53 #include "drm-uapi/amdgpu_drm.h"
54 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
55 #include "winsys/null/radv_null_winsys_public.h"
56 #include "ac_llvm_util.h"
57 #include "vk_format.h"
58 #include "sid.h"
59 #include "git_sha1.h"
60 #include "util/build_id.h"
61 #include "util/debug.h"
62 #include "util/mesa-sha1.h"
63 #include "util/timespec.h"
64 #include "util/u_atomic.h"
65 #include "compiler/glsl_types.h"
66 #include "util/driconf.h"
67
68 static struct radv_timeline_point *
69 radv_timeline_find_point_at_least_locked(struct radv_device *device,
70 struct radv_timeline *timeline,
71 uint64_t p);
72
73 static struct radv_timeline_point *
74 radv_timeline_add_point_locked(struct radv_device *device,
75 struct radv_timeline *timeline,
76 uint64_t p);
77
78 static void
79 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
80 struct list_head *processing_list);
81
82 static
83 void radv_destroy_semaphore_part(struct radv_device *device,
84 struct radv_semaphore_part *part);
85
86 static int
87 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
88 {
89 struct mesa_sha1 ctx;
90 unsigned char sha1[20];
91 unsigned ptr_size = sizeof(void*);
92
93 memset(uuid, 0, VK_UUID_SIZE);
94 _mesa_sha1_init(&ctx);
95
96 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
97 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
98 return -1;
99
100 _mesa_sha1_update(&ctx, &family, sizeof(family));
101 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
102 _mesa_sha1_final(&ctx, sha1);
103
104 memcpy(uuid, sha1, VK_UUID_SIZE);
105 return 0;
106 }
107
108 static void
109 radv_get_driver_uuid(void *uuid)
110 {
111 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
112 }
113
114 static void
115 radv_get_device_uuid(struct radeon_info *info, void *uuid)
116 {
117 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
118 }
119
120 static uint64_t
121 radv_get_visible_vram_size(struct radv_physical_device *device)
122 {
123 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
124 }
125
126 static uint64_t
127 radv_get_vram_size(struct radv_physical_device *device)
128 {
129 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
130 }
131
132 static void
133 radv_physical_device_init_mem_types(struct radv_physical_device *device)
134 {
135 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
136 uint64_t vram_size = radv_get_vram_size(device);
137 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
138 device->memory_properties.memoryHeapCount = 0;
139 if (vram_size > 0) {
140 vram_index = device->memory_properties.memoryHeapCount++;
141 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
142 .size = vram_size,
143 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
144 };
145 }
146
147 if (device->rad_info.gart_size > 0) {
148 gart_index = device->memory_properties.memoryHeapCount++;
149 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
150 .size = device->rad_info.gart_size,
151 .flags = 0,
152 };
153 }
154
155 if (visible_vram_size) {
156 visible_vram_index = device->memory_properties.memoryHeapCount++;
157 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
158 .size = visible_vram_size,
159 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
160 };
161 }
162
163 unsigned type_count = 0;
164
165 if (vram_index >= 0 || visible_vram_index >= 0) {
166 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
167 device->memory_flags[type_count] = RADEON_FLAG_NO_CPU_ACCESS;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
170 .heapIndex = vram_index >= 0 ? vram_index : visible_vram_index,
171 };
172 }
173
174 if (gart_index >= 0) {
175 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
176 device->memory_flags[type_count] = RADEON_FLAG_GTT_WC | RADEON_FLAG_CPU_ACCESS;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
180 .heapIndex = gart_index,
181 };
182 }
183 if (visible_vram_index >= 0) {
184 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
185 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
186 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
187 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
188 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
189 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
190 .heapIndex = visible_vram_index,
191 };
192 }
193
194 if (gart_index >= 0) {
195 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
196 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
197 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
198 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
199 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
200 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205
206 if (device->rad_info.has_l2_uncached) {
207 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
208 VkMemoryType mem_type = device->memory_properties.memoryTypes[i];
209
210 if ((mem_type.propertyFlags & (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
211 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)) ||
212 mem_type.propertyFlags == VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) {
213
214 VkMemoryPropertyFlags property_flags = mem_type.propertyFlags |
215 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD |
216 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD;
217
218 device->memory_domains[type_count] = device->memory_domains[i];
219 device->memory_flags[type_count] = device->memory_flags[i] | RADEON_FLAG_VA_UNCACHED;
220 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
221 .propertyFlags = property_flags,
222 .heapIndex = mem_type.heapIndex,
223 };
224 }
225 }
226 device->memory_properties.memoryTypeCount = type_count;
227 }
228 }
229
230 static const char *
231 radv_get_compiler_string(struct radv_physical_device *pdevice)
232 {
233 if (!pdevice->use_llvm) {
234 /* Some games like SotTR apply shader workarounds if the LLVM
235 * version is too old or if the LLVM version string is
236 * missing. This gives 2-5% performance with SotTR and ACO.
237 */
238 if (driQueryOptionb(&pdevice->instance->dri_options,
239 "radv_report_llvm9_version_string")) {
240 return "ACO/LLVM 9.0.1";
241 }
242
243 return "ACO";
244 }
245
246 return "LLVM " MESA_LLVM_VERSION_STRING;
247 }
248
249 static VkResult
250 radv_physical_device_try_create(struct radv_instance *instance,
251 drmDevicePtr drm_device,
252 struct radv_physical_device **device_out)
253 {
254 VkResult result;
255 int fd = -1;
256 int master_fd = -1;
257
258 if (drm_device) {
259 const char *path = drm_device->nodes[DRM_NODE_RENDER];
260 drmVersionPtr version;
261
262 fd = open(path, O_RDWR | O_CLOEXEC);
263 if (fd < 0) {
264 if (instance->debug_flags & RADV_DEBUG_STARTUP)
265 radv_logi("Could not open device '%s'", path);
266
267 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
268 }
269
270 version = drmGetVersion(fd);
271 if (!version) {
272 close(fd);
273
274 if (instance->debug_flags & RADV_DEBUG_STARTUP)
275 radv_logi("Could not get the kernel driver version for device '%s'", path);
276
277 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
278 "failed to get version %s: %m", path);
279 }
280
281 if (strcmp(version->name, "amdgpu")) {
282 drmFreeVersion(version);
283 close(fd);
284
285 if (instance->debug_flags & RADV_DEBUG_STARTUP)
286 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
287
288 return VK_ERROR_INCOMPATIBLE_DRIVER;
289 }
290 drmFreeVersion(version);
291
292 if (instance->debug_flags & RADV_DEBUG_STARTUP)
293 radv_logi("Found compatible device '%s'.", path);
294 }
295
296 struct radv_physical_device *device =
297 vk_zalloc2(&instance->alloc, NULL, sizeof(*device), 8,
298 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
299 if (!device) {
300 result = vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
301 goto fail_fd;
302 }
303
304 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
305 device->instance = instance;
306
307 if (drm_device) {
308 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
309 instance->perftest_flags);
310 } else {
311 device->ws = radv_null_winsys_create();
312 }
313
314 if (!device->ws) {
315 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
316 "failed to initialize winsys");
317 goto fail_alloc;
318 }
319
320 if (drm_device && instance->enabled_extensions.KHR_display) {
321 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
322 if (master_fd >= 0) {
323 uint32_t accel_working = 0;
324 struct drm_amdgpu_info request = {
325 .return_pointer = (uintptr_t)&accel_working,
326 .return_size = sizeof(accel_working),
327 .query = AMDGPU_INFO_ACCEL_WORKING
328 };
329
330 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
331 close(master_fd);
332 master_fd = -1;
333 }
334 }
335 }
336
337 device->master_fd = master_fd;
338 device->local_fd = fd;
339 device->ws->query_info(device->ws, &device->rad_info);
340
341 device->use_llvm = instance->debug_flags & RADV_DEBUG_LLVM;
342
343 snprintf(device->name, sizeof(device->name),
344 "AMD RADV %s (%s)",
345 device->rad_info.name, radv_get_compiler_string(device));
346
347 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
348 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
349 "cannot generate UUID");
350 goto fail_wsi;
351 }
352
353 /* These flags affect shader compilation. */
354 uint64_t shader_env_flags = (device->use_llvm ? 0 : 0x2);
355
356 /* The gpu id is already embedded in the uuid so we just pass "radv"
357 * when creating the cache.
358 */
359 char buf[VK_UUID_SIZE * 2 + 1];
360 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
361 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
362
363 if (device->rad_info.chip_class < GFX8 || !device->use_llvm)
364 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
365
366 radv_get_driver_uuid(&device->driver_uuid);
367 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
368
369 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
370 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
371
372 device->dcc_msaa_allowed =
373 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
374
375 device->use_ngg = device->rad_info.chip_class >= GFX10 &&
376 device->rad_info.family != CHIP_NAVI14 &&
377 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
378
379 /* TODO: Implement NGG GS with ACO. */
380 device->use_ngg_gs = device->use_ngg && device->use_llvm;
381 device->use_ngg_streamout = false;
382
383 /* Determine the number of threads per wave for all stages. */
384 device->cs_wave_size = 64;
385 device->ps_wave_size = 64;
386 device->ge_wave_size = 64;
387
388 if (device->rad_info.chip_class >= GFX10) {
389 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
390 device->cs_wave_size = 32;
391
392 /* For pixel shaders, wave64 is recommanded. */
393 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
394 device->ps_wave_size = 32;
395
396 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
397 device->ge_wave_size = 32;
398 }
399
400 radv_physical_device_init_mem_types(device);
401
402 radv_physical_device_get_supported_extensions(device,
403 &device->supported_extensions);
404
405 if (drm_device)
406 device->bus_info = *drm_device->businfo.pci;
407
408 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
409 ac_print_gpu_info(&device->rad_info);
410
411 /* The WSI is structured as a layer on top of the driver, so this has
412 * to be the last part of initialization (at least until we get other
413 * semi-layers).
414 */
415 result = radv_init_wsi(device);
416 if (result != VK_SUCCESS) {
417 vk_error(instance, result);
418 goto fail_disk_cache;
419 }
420
421 *device_out = device;
422
423 return VK_SUCCESS;
424
425 fail_disk_cache:
426 disk_cache_destroy(device->disk_cache);
427 fail_wsi:
428 device->ws->destroy(device->ws);
429 fail_alloc:
430 vk_free(&instance->alloc, device);
431 fail_fd:
432 if (fd != -1)
433 close(fd);
434 if (master_fd != -1)
435 close(master_fd);
436 return result;
437 }
438
439 static void
440 radv_physical_device_destroy(struct radv_physical_device *device)
441 {
442 radv_finish_wsi(device);
443 device->ws->destroy(device->ws);
444 disk_cache_destroy(device->disk_cache);
445 close(device->local_fd);
446 if (device->master_fd != -1)
447 close(device->master_fd);
448 vk_free(&device->instance->alloc, device);
449 }
450
451 static void *
452 default_alloc_func(void *pUserData, size_t size, size_t align,
453 VkSystemAllocationScope allocationScope)
454 {
455 return malloc(size);
456 }
457
458 static void *
459 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
460 size_t align, VkSystemAllocationScope allocationScope)
461 {
462 return realloc(pOriginal, size);
463 }
464
465 static void
466 default_free_func(void *pUserData, void *pMemory)
467 {
468 free(pMemory);
469 }
470
471 static const VkAllocationCallbacks default_alloc = {
472 .pUserData = NULL,
473 .pfnAllocation = default_alloc_func,
474 .pfnReallocation = default_realloc_func,
475 .pfnFree = default_free_func,
476 };
477
478 static const struct debug_control radv_debug_options[] = {
479 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
480 {"nodcc", RADV_DEBUG_NO_DCC},
481 {"shaders", RADV_DEBUG_DUMP_SHADERS},
482 {"nocache", RADV_DEBUG_NO_CACHE},
483 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
484 {"nohiz", RADV_DEBUG_NO_HIZ},
485 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
486 {"allbos", RADV_DEBUG_ALL_BOS},
487 {"noibs", RADV_DEBUG_NO_IBS},
488 {"spirv", RADV_DEBUG_DUMP_SPIRV},
489 {"vmfaults", RADV_DEBUG_VM_FAULTS},
490 {"zerovram", RADV_DEBUG_ZERO_VRAM},
491 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
492 {"preoptir", RADV_DEBUG_PREOPTIR},
493 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
494 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
495 {"info", RADV_DEBUG_INFO},
496 {"errors", RADV_DEBUG_ERRORS},
497 {"startup", RADV_DEBUG_STARTUP},
498 {"checkir", RADV_DEBUG_CHECKIR},
499 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
500 {"nobinning", RADV_DEBUG_NOBINNING},
501 {"nongg", RADV_DEBUG_NO_NGG},
502 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
503 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
504 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE},
505 {"llvm", RADV_DEBUG_LLVM},
506 {NULL, 0}
507 };
508
509 const char *
510 radv_get_debug_option_name(int id)
511 {
512 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
513 return radv_debug_options[id].string;
514 }
515
516 static const struct debug_control radv_perftest_options[] = {
517 {"localbos", RADV_PERFTEST_LOCAL_BOS},
518 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
519 {"bolist", RADV_PERFTEST_BO_LIST},
520 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
521 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
522 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
523 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
524 {"dfsm", RADV_PERFTEST_DFSM},
525 {NULL, 0}
526 };
527
528 const char *
529 radv_get_perftest_option_name(int id)
530 {
531 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
532 return radv_perftest_options[id].string;
533 }
534
535 static void
536 radv_handle_per_app_options(struct radv_instance *instance,
537 const VkApplicationInfo *info)
538 {
539 const char *name = info ? info->pApplicationName : NULL;
540 const char *engine_name = info ? info->pEngineName : NULL;
541
542 if (name) {
543 if (!strcmp(name, "DOOM_VFR")) {
544 /* Work around a Doom VFR game bug */
545 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
546 } else if (!strcmp(name, "Fledge")) {
547 /*
548 * Zero VRAM for "The Surge 2"
549 *
550 * This avoid a hang when when rendering any level. Likely
551 * uninitialized data in an indirect draw.
552 */
553 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
554 } else if (!strcmp(name, "No Man's Sky")) {
555 /* Work around a NMS game bug */
556 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
557 } else if (!strcmp(name, "DOOMEternal")) {
558 /* Zero VRAM for Doom Eternal to fix rendering issues. */
559 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
560 } else if (!strcmp(name, "Red Dead Redemption 2")) {
561 /* Work around a RDR2 game bug */
562 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
563 }
564 }
565
566 if (engine_name) {
567 if (!strcmp(engine_name, "vkd3d")) {
568 /* Zero VRAM for all VKD3D (DX12->VK) games to fix
569 * rendering issues.
570 */
571 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
572 } else if (!strcmp(engine_name, "Quantic Dream Engine")) {
573 /* Fix various artifacts in Detroit: Become Human */
574 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM |
575 RADV_DEBUG_DISCARD_TO_DEMOTE;
576 }
577 }
578
579 instance->enable_mrt_output_nan_fixup =
580 driQueryOptionb(&instance->dri_options,
581 "radv_enable_mrt_output_nan_fixup");
582
583 if (driQueryOptionb(&instance->dri_options, "radv_no_dynamic_bounds"))
584 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
585 }
586
587 static const char radv_dri_options_xml[] =
588 DRI_CONF_BEGIN
589 DRI_CONF_SECTION_PERFORMANCE
590 DRI_CONF_ADAPTIVE_SYNC("true")
591 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
592 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
593 DRI_CONF_VK_X11_ENSURE_MIN_IMAGE_COUNT("false")
594 DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING("false")
595 DRI_CONF_RADV_ENABLE_MRT_OUTPUT_NAN_FIXUP("false")
596 DRI_CONF_RADV_NO_DYNAMIC_BOUNDS("false")
597 DRI_CONF_SECTION_END
598
599 DRI_CONF_SECTION_DEBUG
600 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
601 DRI_CONF_SECTION_END
602 DRI_CONF_END;
603
604 static void radv_init_dri_options(struct radv_instance *instance)
605 {
606 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
607 driParseConfigFiles(&instance->dri_options,
608 &instance->available_dri_options,
609 0, "radv", NULL,
610 instance->engineName,
611 instance->engineVersion);
612 }
613
614 VkResult radv_CreateInstance(
615 const VkInstanceCreateInfo* pCreateInfo,
616 const VkAllocationCallbacks* pAllocator,
617 VkInstance* pInstance)
618 {
619 struct radv_instance *instance;
620 VkResult result;
621
622 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
623 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
624 if (!instance)
625 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
626
627 vk_object_base_init(NULL, &instance->base, VK_OBJECT_TYPE_INSTANCE);
628
629 if (pAllocator)
630 instance->alloc = *pAllocator;
631 else
632 instance->alloc = default_alloc;
633
634 if (pCreateInfo->pApplicationInfo) {
635 const VkApplicationInfo *app = pCreateInfo->pApplicationInfo;
636
637 instance->engineName =
638 vk_strdup(&instance->alloc, app->pEngineName,
639 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
640 instance->engineVersion = app->engineVersion;
641 instance->apiVersion = app->apiVersion;
642 }
643
644 if (instance->apiVersion == 0)
645 instance->apiVersion = VK_API_VERSION_1_0;
646
647 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
648 radv_debug_options);
649
650 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
651 radv_perftest_options);
652
653 if (instance->debug_flags & RADV_DEBUG_STARTUP)
654 radv_logi("Created an instance");
655
656 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
657 int idx;
658 for (idx = 0; idx < RADV_INSTANCE_EXTENSION_COUNT; idx++) {
659 if (!strcmp(pCreateInfo->ppEnabledExtensionNames[i],
660 radv_instance_extensions[idx].extensionName))
661 break;
662 }
663
664 if (idx >= RADV_INSTANCE_EXTENSION_COUNT ||
665 !radv_instance_extensions_supported.extensions[idx]) {
666 vk_object_base_finish(&instance->base);
667 vk_free2(&default_alloc, pAllocator, instance);
668 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
669 }
670
671 instance->enabled_extensions.extensions[idx] = true;
672 }
673
674 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
675
676 for (unsigned i = 0; i < ARRAY_SIZE(instance->dispatch.entrypoints); i++) {
677 /* Vulkan requires that entrypoints for extensions which have
678 * not been enabled must not be advertised.
679 */
680 if (!unchecked &&
681 !radv_instance_entrypoint_is_enabled(i, instance->apiVersion,
682 &instance->enabled_extensions)) {
683 instance->dispatch.entrypoints[i] = NULL;
684 } else {
685 instance->dispatch.entrypoints[i] =
686 radv_instance_dispatch_table.entrypoints[i];
687 }
688 }
689
690 for (unsigned i = 0; i < ARRAY_SIZE(instance->physical_device_dispatch.entrypoints); i++) {
691 /* Vulkan requires that entrypoints for extensions which have
692 * not been enabled must not be advertised.
693 */
694 if (!unchecked &&
695 !radv_physical_device_entrypoint_is_enabled(i, instance->apiVersion,
696 &instance->enabled_extensions)) {
697 instance->physical_device_dispatch.entrypoints[i] = NULL;
698 } else {
699 instance->physical_device_dispatch.entrypoints[i] =
700 radv_physical_device_dispatch_table.entrypoints[i];
701 }
702 }
703
704 for (unsigned i = 0; i < ARRAY_SIZE(instance->device_dispatch.entrypoints); i++) {
705 /* Vulkan requires that entrypoints for extensions which have
706 * not been enabled must not be advertised.
707 */
708 if (!unchecked &&
709 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
710 &instance->enabled_extensions, NULL)) {
711 instance->device_dispatch.entrypoints[i] = NULL;
712 } else {
713 instance->device_dispatch.entrypoints[i] =
714 radv_device_dispatch_table.entrypoints[i];
715 }
716 }
717
718 instance->physical_devices_enumerated = false;
719 list_inithead(&instance->physical_devices);
720
721 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
722 if (result != VK_SUCCESS) {
723 vk_object_base_finish(&instance->base);
724 vk_free2(&default_alloc, pAllocator, instance);
725 return vk_error(instance, result);
726 }
727
728 glsl_type_singleton_init_or_ref();
729
730 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
731
732 radv_init_dri_options(instance);
733 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
734
735 *pInstance = radv_instance_to_handle(instance);
736
737 return VK_SUCCESS;
738 }
739
740 void radv_DestroyInstance(
741 VkInstance _instance,
742 const VkAllocationCallbacks* pAllocator)
743 {
744 RADV_FROM_HANDLE(radv_instance, instance, _instance);
745
746 if (!instance)
747 return;
748
749 list_for_each_entry_safe(struct radv_physical_device, pdevice,
750 &instance->physical_devices, link) {
751 radv_physical_device_destroy(pdevice);
752 }
753
754 vk_free(&instance->alloc, instance->engineName);
755
756 VG(VALGRIND_DESTROY_MEMPOOL(instance));
757
758 glsl_type_singleton_decref();
759
760 driDestroyOptionCache(&instance->dri_options);
761 driDestroyOptionInfo(&instance->available_dri_options);
762
763 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
764
765 vk_object_base_finish(&instance->base);
766 vk_free(&instance->alloc, instance);
767 }
768
769 static VkResult
770 radv_enumerate_physical_devices(struct radv_instance *instance)
771 {
772 if (instance->physical_devices_enumerated)
773 return VK_SUCCESS;
774
775 instance->physical_devices_enumerated = true;
776
777 /* TODO: Check for more devices ? */
778 drmDevicePtr devices[8];
779 VkResult result = VK_SUCCESS;
780 int max_devices;
781
782 if (getenv("RADV_FORCE_FAMILY")) {
783 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
784 * device that allows to test the compiler without having an
785 * AMDGPU instance.
786 */
787 struct radv_physical_device *pdevice;
788
789 result = radv_physical_device_try_create(instance, NULL, &pdevice);
790 if (result != VK_SUCCESS)
791 return result;
792
793 list_addtail(&pdevice->link, &instance->physical_devices);
794 return VK_SUCCESS;
795 }
796
797 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
798
799 if (instance->debug_flags & RADV_DEBUG_STARTUP)
800 radv_logi("Found %d drm nodes", max_devices);
801
802 if (max_devices < 1)
803 return vk_error(instance, VK_SUCCESS);
804
805 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
806 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
807 devices[i]->bustype == DRM_BUS_PCI &&
808 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
809
810 struct radv_physical_device *pdevice;
811 result = radv_physical_device_try_create(instance, devices[i],
812 &pdevice);
813 /* Incompatible DRM device, skip. */
814 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
815 result = VK_SUCCESS;
816 continue;
817 }
818
819 /* Error creating the physical device, report the error. */
820 if (result != VK_SUCCESS)
821 break;
822
823 list_addtail(&pdevice->link, &instance->physical_devices);
824 }
825 }
826 drmFreeDevices(devices, max_devices);
827
828 /* If we successfully enumerated any devices, call it success */
829 return result;
830 }
831
832 VkResult radv_EnumeratePhysicalDevices(
833 VkInstance _instance,
834 uint32_t* pPhysicalDeviceCount,
835 VkPhysicalDevice* pPhysicalDevices)
836 {
837 RADV_FROM_HANDLE(radv_instance, instance, _instance);
838 VK_OUTARRAY_MAKE(out, pPhysicalDevices, pPhysicalDeviceCount);
839
840 VkResult result = radv_enumerate_physical_devices(instance);
841 if (result != VK_SUCCESS)
842 return result;
843
844 list_for_each_entry(struct radv_physical_device, pdevice,
845 &instance->physical_devices, link) {
846 vk_outarray_append(&out, i) {
847 *i = radv_physical_device_to_handle(pdevice);
848 }
849 }
850
851 return vk_outarray_status(&out);
852 }
853
854 VkResult radv_EnumeratePhysicalDeviceGroups(
855 VkInstance _instance,
856 uint32_t* pPhysicalDeviceGroupCount,
857 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
858 {
859 RADV_FROM_HANDLE(radv_instance, instance, _instance);
860 VK_OUTARRAY_MAKE(out, pPhysicalDeviceGroupProperties,
861 pPhysicalDeviceGroupCount);
862
863 VkResult result = radv_enumerate_physical_devices(instance);
864 if (result != VK_SUCCESS)
865 return result;
866
867 list_for_each_entry(struct radv_physical_device, pdevice,
868 &instance->physical_devices, link) {
869 vk_outarray_append(&out, p) {
870 p->physicalDeviceCount = 1;
871 memset(p->physicalDevices, 0, sizeof(p->physicalDevices));
872 p->physicalDevices[0] = radv_physical_device_to_handle(pdevice);
873 p->subsetAllocation = false;
874 }
875 }
876
877 return vk_outarray_status(&out);
878 }
879
880 void radv_GetPhysicalDeviceFeatures(
881 VkPhysicalDevice physicalDevice,
882 VkPhysicalDeviceFeatures* pFeatures)
883 {
884 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
885 memset(pFeatures, 0, sizeof(*pFeatures));
886
887 *pFeatures = (VkPhysicalDeviceFeatures) {
888 .robustBufferAccess = true,
889 .fullDrawIndexUint32 = true,
890 .imageCubeArray = true,
891 .independentBlend = true,
892 .geometryShader = true,
893 .tessellationShader = true,
894 .sampleRateShading = true,
895 .dualSrcBlend = true,
896 .logicOp = true,
897 .multiDrawIndirect = true,
898 .drawIndirectFirstInstance = true,
899 .depthClamp = true,
900 .depthBiasClamp = true,
901 .fillModeNonSolid = true,
902 .depthBounds = true,
903 .wideLines = true,
904 .largePoints = true,
905 .alphaToOne = true,
906 .multiViewport = true,
907 .samplerAnisotropy = true,
908 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
909 .textureCompressionASTC_LDR = false,
910 .textureCompressionBC = true,
911 .occlusionQueryPrecise = true,
912 .pipelineStatisticsQuery = true,
913 .vertexPipelineStoresAndAtomics = true,
914 .fragmentStoresAndAtomics = true,
915 .shaderTessellationAndGeometryPointSize = true,
916 .shaderImageGatherExtended = true,
917 .shaderStorageImageExtendedFormats = true,
918 .shaderStorageImageMultisample = true,
919 .shaderUniformBufferArrayDynamicIndexing = true,
920 .shaderSampledImageArrayDynamicIndexing = true,
921 .shaderStorageBufferArrayDynamicIndexing = true,
922 .shaderStorageImageArrayDynamicIndexing = true,
923 .shaderStorageImageReadWithoutFormat = true,
924 .shaderStorageImageWriteWithoutFormat = true,
925 .shaderClipDistance = true,
926 .shaderCullDistance = true,
927 .shaderFloat64 = true,
928 .shaderInt64 = true,
929 .shaderInt16 = true,
930 .sparseBinding = true,
931 .variableMultisampleRate = true,
932 .shaderResourceMinLod = true,
933 .inheritedQueries = true,
934 };
935 }
936
937 static void
938 radv_get_physical_device_features_1_1(struct radv_physical_device *pdevice,
939 VkPhysicalDeviceVulkan11Features *f)
940 {
941 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES);
942
943 f->storageBuffer16BitAccess = true;
944 f->uniformAndStorageBuffer16BitAccess = true;
945 f->storagePushConstant16 = true;
946 f->storageInputOutput16 = pdevice->rad_info.has_packed_math_16bit && (LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm);
947 f->multiview = true;
948 f->multiviewGeometryShader = true;
949 f->multiviewTessellationShader = true;
950 f->variablePointersStorageBuffer = true;
951 f->variablePointers = true;
952 f->protectedMemory = false;
953 f->samplerYcbcrConversion = true;
954 f->shaderDrawParameters = true;
955 }
956
957 static void
958 radv_get_physical_device_features_1_2(struct radv_physical_device *pdevice,
959 VkPhysicalDeviceVulkan12Features *f)
960 {
961 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES);
962
963 f->samplerMirrorClampToEdge = true;
964 f->drawIndirectCount = true;
965 f->storageBuffer8BitAccess = true;
966 f->uniformAndStorageBuffer8BitAccess = true;
967 f->storagePushConstant8 = true;
968 f->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
969 f->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
970 f->shaderFloat16 = pdevice->rad_info.has_packed_math_16bit;
971 f->shaderInt8 = true;
972
973 f->descriptorIndexing = true;
974 f->shaderInputAttachmentArrayDynamicIndexing = true;
975 f->shaderUniformTexelBufferArrayDynamicIndexing = true;
976 f->shaderStorageTexelBufferArrayDynamicIndexing = true;
977 f->shaderUniformBufferArrayNonUniformIndexing = true;
978 f->shaderSampledImageArrayNonUniformIndexing = true;
979 f->shaderStorageBufferArrayNonUniformIndexing = true;
980 f->shaderStorageImageArrayNonUniformIndexing = true;
981 f->shaderInputAttachmentArrayNonUniformIndexing = true;
982 f->shaderUniformTexelBufferArrayNonUniformIndexing = true;
983 f->shaderStorageTexelBufferArrayNonUniformIndexing = true;
984 f->descriptorBindingUniformBufferUpdateAfterBind = true;
985 f->descriptorBindingSampledImageUpdateAfterBind = true;
986 f->descriptorBindingStorageImageUpdateAfterBind = true;
987 f->descriptorBindingStorageBufferUpdateAfterBind = true;
988 f->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
989 f->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
990 f->descriptorBindingUpdateUnusedWhilePending = true;
991 f->descriptorBindingPartiallyBound = true;
992 f->descriptorBindingVariableDescriptorCount = true;
993 f->runtimeDescriptorArray = true;
994
995 f->samplerFilterMinmax = true;
996 f->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
997 f->imagelessFramebuffer = true;
998 f->uniformBufferStandardLayout = true;
999 f->shaderSubgroupExtendedTypes = true;
1000 f->separateDepthStencilLayouts = true;
1001 f->hostQueryReset = true;
1002 f->timelineSemaphore = pdevice->rad_info.has_syncobj_wait_for_submit;
1003 f->bufferDeviceAddress = true;
1004 f->bufferDeviceAddressCaptureReplay = false;
1005 f->bufferDeviceAddressMultiDevice = false;
1006 f->vulkanMemoryModel = false;
1007 f->vulkanMemoryModelDeviceScope = false;
1008 f->vulkanMemoryModelAvailabilityVisibilityChains = false;
1009 f->shaderOutputViewportIndex = true;
1010 f->shaderOutputLayer = true;
1011 f->subgroupBroadcastDynamicId = true;
1012 }
1013
1014 void radv_GetPhysicalDeviceFeatures2(
1015 VkPhysicalDevice physicalDevice,
1016 VkPhysicalDeviceFeatures2 *pFeatures)
1017 {
1018 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1019 radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1020
1021 VkPhysicalDeviceVulkan11Features core_1_1 = {
1022 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES,
1023 };
1024 radv_get_physical_device_features_1_1(pdevice, &core_1_1);
1025
1026 VkPhysicalDeviceVulkan12Features core_1_2 = {
1027 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES,
1028 };
1029 radv_get_physical_device_features_1_2(pdevice, &core_1_2);
1030
1031 #define CORE_FEATURE(major, minor, feature) \
1032 features->feature = core_##major##_##minor.feature
1033
1034 vk_foreach_struct(ext, pFeatures->pNext) {
1035 switch (ext->sType) {
1036 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
1037 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
1038 CORE_FEATURE(1, 1, variablePointersStorageBuffer);
1039 CORE_FEATURE(1, 1, variablePointers);
1040 break;
1041 }
1042 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
1043 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
1044 CORE_FEATURE(1, 1, multiview);
1045 CORE_FEATURE(1, 1, multiviewGeometryShader);
1046 CORE_FEATURE(1, 1, multiviewTessellationShader);
1047 break;
1048 }
1049 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
1050 VkPhysicalDeviceShaderDrawParametersFeatures *features =
1051 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
1052 CORE_FEATURE(1, 1, shaderDrawParameters);
1053 break;
1054 }
1055 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
1056 VkPhysicalDeviceProtectedMemoryFeatures *features =
1057 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
1058 CORE_FEATURE(1, 1, protectedMemory);
1059 break;
1060 }
1061 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
1062 VkPhysicalDevice16BitStorageFeatures *features =
1063 (VkPhysicalDevice16BitStorageFeatures*)ext;
1064 CORE_FEATURE(1, 1, storageBuffer16BitAccess);
1065 CORE_FEATURE(1, 1, uniformAndStorageBuffer16BitAccess);
1066 CORE_FEATURE(1, 1, storagePushConstant16);
1067 CORE_FEATURE(1, 1, storageInputOutput16);
1068 break;
1069 }
1070 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
1071 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
1072 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
1073 CORE_FEATURE(1, 1, samplerYcbcrConversion);
1074 break;
1075 }
1076 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES: {
1077 VkPhysicalDeviceDescriptorIndexingFeatures *features =
1078 (VkPhysicalDeviceDescriptorIndexingFeatures*)ext;
1079 CORE_FEATURE(1, 2, shaderInputAttachmentArrayDynamicIndexing);
1080 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayDynamicIndexing);
1081 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayDynamicIndexing);
1082 CORE_FEATURE(1, 2, shaderUniformBufferArrayNonUniformIndexing);
1083 CORE_FEATURE(1, 2, shaderSampledImageArrayNonUniformIndexing);
1084 CORE_FEATURE(1, 2, shaderStorageBufferArrayNonUniformIndexing);
1085 CORE_FEATURE(1, 2, shaderStorageImageArrayNonUniformIndexing);
1086 CORE_FEATURE(1, 2, shaderInputAttachmentArrayNonUniformIndexing);
1087 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayNonUniformIndexing);
1088 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayNonUniformIndexing);
1089 CORE_FEATURE(1, 2, descriptorBindingUniformBufferUpdateAfterBind);
1090 CORE_FEATURE(1, 2, descriptorBindingSampledImageUpdateAfterBind);
1091 CORE_FEATURE(1, 2, descriptorBindingStorageImageUpdateAfterBind);
1092 CORE_FEATURE(1, 2, descriptorBindingStorageBufferUpdateAfterBind);
1093 CORE_FEATURE(1, 2, descriptorBindingUniformTexelBufferUpdateAfterBind);
1094 CORE_FEATURE(1, 2, descriptorBindingStorageTexelBufferUpdateAfterBind);
1095 CORE_FEATURE(1, 2, descriptorBindingUpdateUnusedWhilePending);
1096 CORE_FEATURE(1, 2, descriptorBindingPartiallyBound);
1097 CORE_FEATURE(1, 2, descriptorBindingVariableDescriptorCount);
1098 CORE_FEATURE(1, 2, runtimeDescriptorArray);
1099 break;
1100 }
1101 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
1102 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
1103 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
1104 features->conditionalRendering = true;
1105 features->inheritedConditionalRendering = false;
1106 break;
1107 }
1108 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
1109 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
1110 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
1111 features->vertexAttributeInstanceRateDivisor = true;
1112 features->vertexAttributeInstanceRateZeroDivisor = true;
1113 break;
1114 }
1115 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
1116 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
1117 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
1118 features->transformFeedback = true;
1119 features->geometryStreams = !pdevice->use_ngg_streamout;
1120 break;
1121 }
1122 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES: {
1123 VkPhysicalDeviceScalarBlockLayoutFeatures *features =
1124 (VkPhysicalDeviceScalarBlockLayoutFeatures *)ext;
1125 CORE_FEATURE(1, 2, scalarBlockLayout);
1126 break;
1127 }
1128 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
1129 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
1130 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
1131 features->memoryPriority = true;
1132 break;
1133 }
1134 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
1135 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
1136 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
1137 features->bufferDeviceAddress = true;
1138 features->bufferDeviceAddressCaptureReplay = false;
1139 features->bufferDeviceAddressMultiDevice = false;
1140 break;
1141 }
1142 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES: {
1143 VkPhysicalDeviceBufferDeviceAddressFeatures *features =
1144 (VkPhysicalDeviceBufferDeviceAddressFeatures *)ext;
1145 CORE_FEATURE(1, 2, bufferDeviceAddress);
1146 CORE_FEATURE(1, 2, bufferDeviceAddressCaptureReplay);
1147 CORE_FEATURE(1, 2, bufferDeviceAddressMultiDevice);
1148 break;
1149 }
1150 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
1151 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
1152 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
1153 features->depthClipEnable = true;
1154 break;
1155 }
1156 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES: {
1157 VkPhysicalDeviceHostQueryResetFeatures *features =
1158 (VkPhysicalDeviceHostQueryResetFeatures *)ext;
1159 CORE_FEATURE(1, 2, hostQueryReset);
1160 break;
1161 }
1162 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES: {
1163 VkPhysicalDevice8BitStorageFeatures *features =
1164 (VkPhysicalDevice8BitStorageFeatures *)ext;
1165 CORE_FEATURE(1, 2, storageBuffer8BitAccess);
1166 CORE_FEATURE(1, 2, uniformAndStorageBuffer8BitAccess);
1167 CORE_FEATURE(1, 2, storagePushConstant8);
1168 break;
1169 }
1170 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES: {
1171 VkPhysicalDeviceShaderFloat16Int8Features *features =
1172 (VkPhysicalDeviceShaderFloat16Int8Features*)ext;
1173 CORE_FEATURE(1, 2, shaderFloat16);
1174 CORE_FEATURE(1, 2, shaderInt8);
1175 break;
1176 }
1177 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES: {
1178 VkPhysicalDeviceShaderAtomicInt64Features *features =
1179 (VkPhysicalDeviceShaderAtomicInt64Features *)ext;
1180 CORE_FEATURE(1, 2, shaderBufferInt64Atomics);
1181 CORE_FEATURE(1, 2, shaderSharedInt64Atomics);
1182 break;
1183 }
1184 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
1185 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
1186 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
1187 features->shaderDemoteToHelperInvocation = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1188 break;
1189 }
1190 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
1191 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
1192 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
1193
1194 features->inlineUniformBlock = true;
1195 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1196 break;
1197 }
1198 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1199 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1200 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1201 features->computeDerivativeGroupQuads = false;
1202 features->computeDerivativeGroupLinear = true;
1203 break;
1204 }
1205 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1206 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1207 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1208 features->ycbcrImageArrays = true;
1209 break;
1210 }
1211 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES: {
1212 VkPhysicalDeviceUniformBufferStandardLayoutFeatures *features =
1213 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures *)ext;
1214 CORE_FEATURE(1, 2, uniformBufferStandardLayout);
1215 break;
1216 }
1217 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1218 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1219 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1220 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1221 break;
1222 }
1223 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES: {
1224 VkPhysicalDeviceImagelessFramebufferFeatures *features =
1225 (VkPhysicalDeviceImagelessFramebufferFeatures *)ext;
1226 CORE_FEATURE(1, 2, imagelessFramebuffer);
1227 break;
1228 }
1229 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1230 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1231 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1232 features->pipelineExecutableInfo = true;
1233 break;
1234 }
1235 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR: {
1236 VkPhysicalDeviceShaderClockFeaturesKHR *features =
1237 (VkPhysicalDeviceShaderClockFeaturesKHR *)ext;
1238 features->shaderSubgroupClock = true;
1239 features->shaderDeviceClock = pdevice->rad_info.chip_class >= GFX8;
1240 break;
1241 }
1242 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
1243 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
1244 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
1245 features->texelBufferAlignment = true;
1246 break;
1247 }
1248 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES: {
1249 VkPhysicalDeviceTimelineSemaphoreFeatures *features =
1250 (VkPhysicalDeviceTimelineSemaphoreFeatures *) ext;
1251 CORE_FEATURE(1, 2, timelineSemaphore);
1252 break;
1253 }
1254 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT: {
1255 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *features =
1256 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *)ext;
1257 features->subgroupSizeControl = true;
1258 features->computeFullSubgroups = true;
1259 break;
1260 }
1261 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD: {
1262 VkPhysicalDeviceCoherentMemoryFeaturesAMD *features =
1263 (VkPhysicalDeviceCoherentMemoryFeaturesAMD *)ext;
1264 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1265 break;
1266 }
1267 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES: {
1268 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *features =
1269 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *)ext;
1270 CORE_FEATURE(1, 2, shaderSubgroupExtendedTypes);
1271 break;
1272 }
1273 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR: {
1274 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *features =
1275 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *)ext;
1276 CORE_FEATURE(1, 2, separateDepthStencilLayouts);
1277 break;
1278 }
1279 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES: {
1280 radv_get_physical_device_features_1_1(pdevice, (void *)ext);
1281 break;
1282 }
1283 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES: {
1284 radv_get_physical_device_features_1_2(pdevice, (void *)ext);
1285 break;
1286 }
1287 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT: {
1288 VkPhysicalDeviceLineRasterizationFeaturesEXT *features =
1289 (VkPhysicalDeviceLineRasterizationFeaturesEXT *)ext;
1290 features->rectangularLines = false;
1291 features->bresenhamLines = true;
1292 features->smoothLines = false;
1293 features->stippledRectangularLines = false;
1294 features->stippledBresenhamLines = true;
1295 features->stippledSmoothLines = false;
1296 break;
1297 }
1298 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
1299 VkDeviceMemoryOverallocationCreateInfoAMD *features =
1300 (VkDeviceMemoryOverallocationCreateInfoAMD *)ext;
1301 features->overallocationBehavior = true;
1302 break;
1303 }
1304 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_FEATURES_EXT: {
1305 VkPhysicalDeviceRobustness2FeaturesEXT *features =
1306 (VkPhysicalDeviceRobustness2FeaturesEXT *)ext;
1307 features->robustBufferAccess2 = true;
1308 features->robustImageAccess2 = true;
1309 features->nullDescriptor = true;
1310 break;
1311 }
1312 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
1313 VkPhysicalDeviceCustomBorderColorFeaturesEXT *features =
1314 (VkPhysicalDeviceCustomBorderColorFeaturesEXT *)ext;
1315 features->customBorderColors = true;
1316 features->customBorderColorWithoutFormat = true;
1317 break;
1318 }
1319 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PRIVATE_DATA_FEATURES_EXT: {
1320 VkPhysicalDevicePrivateDataFeaturesEXT *features =
1321 (VkPhysicalDevicePrivateDataFeaturesEXT *)ext;
1322 features->privateData = true;
1323 break;
1324 }
1325 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_CREATION_CACHE_CONTROL_FEATURES_EXT: {
1326 VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *features =
1327 (VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *)ext;
1328 features-> pipelineCreationCacheControl = true;
1329 break;
1330 }
1331 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTENDED_DYNAMIC_STATE_FEATURES_EXT: {
1332 VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *features =
1333 (VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *) ext;
1334 features->extendedDynamicState = true;
1335 break;
1336 }
1337 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_ROBUSTNESS_FEATURES_EXT: {
1338 VkPhysicalDeviceImageRobustnessFeaturesEXT *features =
1339 (VkPhysicalDeviceImageRobustnessFeaturesEXT *)ext;
1340 features->robustImageAccess = true;
1341 break;
1342 }
1343 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_FLOAT_FEATURES_EXT: {
1344 VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *features =
1345 (VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *)ext;
1346 features->shaderBufferFloat32Atomics = true;
1347 features->shaderBufferFloat32AtomicAdd = false;
1348 features->shaderBufferFloat64Atomics = true;
1349 features->shaderBufferFloat64AtomicAdd = false;
1350 features->shaderSharedFloat32Atomics = true;
1351 features->shaderSharedFloat32AtomicAdd = pdevice->rad_info.chip_class >= GFX8 &&
1352 (!pdevice->use_llvm || LLVM_VERSION_MAJOR >= 10);
1353 features->shaderSharedFloat64Atomics = true;
1354 features->shaderSharedFloat64AtomicAdd = false;
1355 features->shaderImageFloat32Atomics = true;
1356 features->shaderImageFloat32AtomicAdd = false;
1357 features->sparseImageFloat32Atomics = false;
1358 features->sparseImageFloat32AtomicAdd = false;
1359 break;
1360 }
1361 default:
1362 break;
1363 }
1364 }
1365 #undef CORE_FEATURE
1366 }
1367
1368 static size_t
1369 radv_max_descriptor_set_size()
1370 {
1371 /* make sure that the entire descriptor set is addressable with a signed
1372 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1373 * be at most 2 GiB. the combined image & samples object count as one of
1374 * both. This limit is for the pipeline layout, not for the set layout, but
1375 * there is no set limit, so we just set a pipeline limit. I don't think
1376 * any app is going to hit this soon. */
1377 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1378 - MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1379 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1380 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1381 32 /* sampler, largest when combined with image */ +
1382 64 /* sampled image */ +
1383 64 /* storage image */);
1384 }
1385
1386 void radv_GetPhysicalDeviceProperties(
1387 VkPhysicalDevice physicalDevice,
1388 VkPhysicalDeviceProperties* pProperties)
1389 {
1390 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1391 VkSampleCountFlags sample_counts = 0xf;
1392
1393 size_t max_descriptor_set_size = radv_max_descriptor_set_size();
1394
1395 VkPhysicalDeviceLimits limits = {
1396 .maxImageDimension1D = (1 << 14),
1397 .maxImageDimension2D = (1 << 14),
1398 .maxImageDimension3D = (1 << 11),
1399 .maxImageDimensionCube = (1 << 14),
1400 .maxImageArrayLayers = (1 << 11),
1401 .maxTexelBufferElements = UINT32_MAX,
1402 .maxUniformBufferRange = UINT32_MAX,
1403 .maxStorageBufferRange = UINT32_MAX,
1404 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1405 .maxMemoryAllocationCount = UINT32_MAX,
1406 .maxSamplerAllocationCount = 64 * 1024,
1407 .bufferImageGranularity = 64, /* A cache line */
1408 .sparseAddressSpaceSize = RADV_MAX_MEMORY_ALLOCATION_SIZE, /* buffer max size */
1409 .maxBoundDescriptorSets = MAX_SETS,
1410 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1411 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1412 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1413 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1414 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1415 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1416 .maxPerStageResources = max_descriptor_set_size,
1417 .maxDescriptorSetSamplers = max_descriptor_set_size,
1418 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1419 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1420 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1421 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1422 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1423 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1424 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1425 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1426 .maxVertexInputBindings = MAX_VBS,
1427 .maxVertexInputAttributeOffset = 2047,
1428 .maxVertexInputBindingStride = 2048,
1429 .maxVertexOutputComponents = 128,
1430 .maxTessellationGenerationLevel = 64,
1431 .maxTessellationPatchSize = 32,
1432 .maxTessellationControlPerVertexInputComponents = 128,
1433 .maxTessellationControlPerVertexOutputComponents = 128,
1434 .maxTessellationControlPerPatchOutputComponents = 120,
1435 .maxTessellationControlTotalOutputComponents = 4096,
1436 .maxTessellationEvaluationInputComponents = 128,
1437 .maxTessellationEvaluationOutputComponents = 128,
1438 .maxGeometryShaderInvocations = 127,
1439 .maxGeometryInputComponents = 64,
1440 .maxGeometryOutputComponents = 128,
1441 .maxGeometryOutputVertices = 256,
1442 .maxGeometryTotalOutputComponents = 1024,
1443 .maxFragmentInputComponents = 128,
1444 .maxFragmentOutputAttachments = 8,
1445 .maxFragmentDualSrcAttachments = 1,
1446 .maxFragmentCombinedOutputResources = 8,
1447 .maxComputeSharedMemorySize = 32768,
1448 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1449 .maxComputeWorkGroupInvocations = 1024,
1450 .maxComputeWorkGroupSize = {
1451 1024,
1452 1024,
1453 1024
1454 },
1455 .subPixelPrecisionBits = 8,
1456 .subTexelPrecisionBits = 8,
1457 .mipmapPrecisionBits = 8,
1458 .maxDrawIndexedIndexValue = UINT32_MAX,
1459 .maxDrawIndirectCount = UINT32_MAX,
1460 .maxSamplerLodBias = 16,
1461 .maxSamplerAnisotropy = 16,
1462 .maxViewports = MAX_VIEWPORTS,
1463 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1464 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1465 .viewportSubPixelBits = 8,
1466 .minMemoryMapAlignment = 4096, /* A page */
1467 .minTexelBufferOffsetAlignment = 4,
1468 .minUniformBufferOffsetAlignment = 4,
1469 .minStorageBufferOffsetAlignment = 4,
1470 .minTexelOffset = -32,
1471 .maxTexelOffset = 31,
1472 .minTexelGatherOffset = -32,
1473 .maxTexelGatherOffset = 31,
1474 .minInterpolationOffset = -2,
1475 .maxInterpolationOffset = 2,
1476 .subPixelInterpolationOffsetBits = 8,
1477 .maxFramebufferWidth = (1 << 14),
1478 .maxFramebufferHeight = (1 << 14),
1479 .maxFramebufferLayers = (1 << 10),
1480 .framebufferColorSampleCounts = sample_counts,
1481 .framebufferDepthSampleCounts = sample_counts,
1482 .framebufferStencilSampleCounts = sample_counts,
1483 .framebufferNoAttachmentsSampleCounts = sample_counts,
1484 .maxColorAttachments = MAX_RTS,
1485 .sampledImageColorSampleCounts = sample_counts,
1486 .sampledImageIntegerSampleCounts = sample_counts,
1487 .sampledImageDepthSampleCounts = sample_counts,
1488 .sampledImageStencilSampleCounts = sample_counts,
1489 .storageImageSampleCounts = sample_counts,
1490 .maxSampleMaskWords = 1,
1491 .timestampComputeAndGraphics = true,
1492 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1493 .maxClipDistances = 8,
1494 .maxCullDistances = 8,
1495 .maxCombinedClipAndCullDistances = 8,
1496 .discreteQueuePriorities = 2,
1497 .pointSizeRange = { 0.0, 8191.875 },
1498 .lineWidthRange = { 0.0, 8191.875 },
1499 .pointSizeGranularity = (1.0 / 8.0),
1500 .lineWidthGranularity = (1.0 / 8.0),
1501 .strictLines = false, /* FINISHME */
1502 .standardSampleLocations = true,
1503 .optimalBufferCopyOffsetAlignment = 128,
1504 .optimalBufferCopyRowPitchAlignment = 128,
1505 .nonCoherentAtomSize = 64,
1506 };
1507
1508 *pProperties = (VkPhysicalDeviceProperties) {
1509 .apiVersion = radv_physical_device_api_version(pdevice),
1510 .driverVersion = vk_get_driver_version(),
1511 .vendorID = ATI_VENDOR_ID,
1512 .deviceID = pdevice->rad_info.pci_id,
1513 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1514 .limits = limits,
1515 .sparseProperties = {0},
1516 };
1517
1518 strcpy(pProperties->deviceName, pdevice->name);
1519 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1520 }
1521
1522 static void
1523 radv_get_physical_device_properties_1_1(struct radv_physical_device *pdevice,
1524 VkPhysicalDeviceVulkan11Properties *p)
1525 {
1526 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES);
1527
1528 memcpy(p->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1529 memcpy(p->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1530 memset(p->deviceLUID, 0, VK_LUID_SIZE);
1531 /* The LUID is for Windows. */
1532 p->deviceLUIDValid = false;
1533 p->deviceNodeMask = 0;
1534
1535 p->subgroupSize = RADV_SUBGROUP_SIZE;
1536 p->subgroupSupportedStages = VK_SHADER_STAGE_ALL_GRAPHICS |
1537 VK_SHADER_STAGE_COMPUTE_BIT;
1538 p->subgroupSupportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT |
1539 VK_SUBGROUP_FEATURE_VOTE_BIT |
1540 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1541 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1542 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1543 VK_SUBGROUP_FEATURE_QUAD_BIT |
1544 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1545 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1546 p->subgroupQuadOperationsInAllStages = true;
1547
1548 p->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1549 p->maxMultiviewViewCount = MAX_VIEWS;
1550 p->maxMultiviewInstanceIndex = INT_MAX;
1551 p->protectedNoFault = false;
1552 p->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
1553 p->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
1554 }
1555
1556 static void
1557 radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
1558 VkPhysicalDeviceVulkan12Properties *p)
1559 {
1560 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES);
1561
1562 p->driverID = VK_DRIVER_ID_MESA_RADV;
1563 snprintf(p->driverName, VK_MAX_DRIVER_NAME_SIZE, "radv");
1564 snprintf(p->driverInfo, VK_MAX_DRIVER_INFO_SIZE,
1565 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1 " (%s)",
1566 radv_get_compiler_string(pdevice));
1567 p->conformanceVersion = (VkConformanceVersion) {
1568 .major = 1,
1569 .minor = 2,
1570 .subminor = 0,
1571 .patch = 0,
1572 };
1573
1574 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1575 * controlled by the same config register.
1576 */
1577 if (pdevice->rad_info.has_packed_math_16bit) {
1578 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1579 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1580 } else {
1581 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1582 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1583 }
1584
1585 /* With LLVM, do not allow both preserving and flushing denorms because
1586 * different shaders in the same pipeline can have different settings and
1587 * this won't work for merged shaders. To make it work, this requires LLVM
1588 * support for changing the register. The same logic applies for the
1589 * rounding modes because they are configured with the same config
1590 * register.
1591 */
1592 p->shaderDenormFlushToZeroFloat32 = true;
1593 p->shaderDenormPreserveFloat32 = !pdevice->use_llvm;
1594 p->shaderRoundingModeRTEFloat32 = true;
1595 p->shaderRoundingModeRTZFloat32 = !pdevice->use_llvm;
1596 p->shaderSignedZeroInfNanPreserveFloat32 = true;
1597
1598 p->shaderDenormFlushToZeroFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1599 p->shaderDenormPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1600 p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.has_packed_math_16bit;
1601 p->shaderRoundingModeRTZFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1602 p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1603
1604 p->shaderDenormFlushToZeroFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1605 p->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1606 p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
1607 p->shaderRoundingModeRTZFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1608 p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1609
1610 p->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1611 p->shaderUniformBufferArrayNonUniformIndexingNative = false;
1612 p->shaderSampledImageArrayNonUniformIndexingNative = false;
1613 p->shaderStorageBufferArrayNonUniformIndexingNative = false;
1614 p->shaderStorageImageArrayNonUniformIndexingNative = false;
1615 p->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1616 p->robustBufferAccessUpdateAfterBind = false;
1617 p->quadDivergentImplicitLod = false;
1618
1619 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1620 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1621 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1622 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1623 32 /* sampler, largest when combined with image */ +
1624 64 /* sampled image */ +
1625 64 /* storage image */);
1626 p->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1627 p->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1628 p->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1629 p->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1630 p->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1631 p->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1632 p->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1633 p->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1634 p->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1635 p->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1636 p->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1637 p->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1638 p->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1639 p->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1640 p->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1641
1642 /* We support all of the depth resolve modes */
1643 p->supportedDepthResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1644 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1645 VK_RESOLVE_MODE_MIN_BIT_KHR |
1646 VK_RESOLVE_MODE_MAX_BIT_KHR;
1647
1648 /* Average doesn't make sense for stencil so we don't support that */
1649 p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1650 VK_RESOLVE_MODE_MIN_BIT_KHR |
1651 VK_RESOLVE_MODE_MAX_BIT_KHR;
1652
1653 p->independentResolveNone = true;
1654 p->independentResolve = true;
1655
1656 /* GFX6-8 only support single channel min/max filter. */
1657 p->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1658 p->filterMinmaxSingleComponentFormats = true;
1659
1660 p->maxTimelineSemaphoreValueDifference = UINT64_MAX;
1661
1662 p->framebufferIntegerColorSampleCounts = VK_SAMPLE_COUNT_1_BIT;
1663 }
1664
1665 void radv_GetPhysicalDeviceProperties2(
1666 VkPhysicalDevice physicalDevice,
1667 VkPhysicalDeviceProperties2 *pProperties)
1668 {
1669 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1670 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1671
1672 VkPhysicalDeviceVulkan11Properties core_1_1 = {
1673 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES,
1674 };
1675 radv_get_physical_device_properties_1_1(pdevice, &core_1_1);
1676
1677 VkPhysicalDeviceVulkan12Properties core_1_2 = {
1678 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES,
1679 };
1680 radv_get_physical_device_properties_1_2(pdevice, &core_1_2);
1681
1682 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1683 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1684 sizeof(core_##major##_##minor.core_property))
1685
1686 #define CORE_PROPERTY(major, minor, property) \
1687 CORE_RENAMED_PROPERTY(major, minor, property, property)
1688
1689 vk_foreach_struct(ext, pProperties->pNext) {
1690 switch (ext->sType) {
1691 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1692 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1693 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1694 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1695 break;
1696 }
1697 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1698 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1699 CORE_PROPERTY(1, 1, deviceUUID);
1700 CORE_PROPERTY(1, 1, driverUUID);
1701 CORE_PROPERTY(1, 1, deviceLUID);
1702 CORE_PROPERTY(1, 1, deviceLUIDValid);
1703 break;
1704 }
1705 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1706 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1707 CORE_PROPERTY(1, 1, maxMultiviewViewCount);
1708 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex);
1709 break;
1710 }
1711 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1712 VkPhysicalDevicePointClippingProperties *properties =
1713 (VkPhysicalDevicePointClippingProperties*)ext;
1714 CORE_PROPERTY(1, 1, pointClippingBehavior);
1715 break;
1716 }
1717 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1718 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1719 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1720 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1721 break;
1722 }
1723 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1724 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1725 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1726 properties->minImportedHostPointerAlignment = 4096;
1727 break;
1728 }
1729 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1730 VkPhysicalDeviceSubgroupProperties *properties =
1731 (VkPhysicalDeviceSubgroupProperties*)ext;
1732 CORE_PROPERTY(1, 1, subgroupSize);
1733 CORE_RENAMED_PROPERTY(1, 1, supportedStages,
1734 subgroupSupportedStages);
1735 CORE_RENAMED_PROPERTY(1, 1, supportedOperations,
1736 subgroupSupportedOperations);
1737 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages,
1738 subgroupQuadOperationsInAllStages);
1739 break;
1740 }
1741 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1742 VkPhysicalDeviceMaintenance3Properties *properties =
1743 (VkPhysicalDeviceMaintenance3Properties*)ext;
1744 CORE_PROPERTY(1, 1, maxPerSetDescriptors);
1745 CORE_PROPERTY(1, 1, maxMemoryAllocationSize);
1746 break;
1747 }
1748 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES: {
1749 VkPhysicalDeviceSamplerFilterMinmaxProperties *properties =
1750 (VkPhysicalDeviceSamplerFilterMinmaxProperties *)ext;
1751 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping);
1752 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats);
1753 break;
1754 }
1755 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1756 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1757 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1758
1759 /* Shader engines. */
1760 properties->shaderEngineCount =
1761 pdevice->rad_info.max_se;
1762 properties->shaderArraysPerEngineCount =
1763 pdevice->rad_info.max_sh_per_se;
1764 properties->computeUnitsPerShaderArray =
1765 pdevice->rad_info.min_good_cu_per_sa;
1766 properties->simdPerComputeUnit =
1767 pdevice->rad_info.num_simd_per_compute_unit;
1768 properties->wavefrontsPerSimd =
1769 pdevice->rad_info.max_wave64_per_simd;
1770 properties->wavefrontSize = 64;
1771
1772 /* SGPR. */
1773 properties->sgprsPerSimd =
1774 pdevice->rad_info.num_physical_sgprs_per_simd;
1775 properties->minSgprAllocation =
1776 pdevice->rad_info.min_sgpr_alloc;
1777 properties->maxSgprAllocation =
1778 pdevice->rad_info.max_sgpr_alloc;
1779 properties->sgprAllocationGranularity =
1780 pdevice->rad_info.sgpr_alloc_granularity;
1781
1782 /* VGPR. */
1783 properties->vgprsPerSimd =
1784 pdevice->rad_info.num_physical_wave64_vgprs_per_simd;
1785 properties->minVgprAllocation =
1786 pdevice->rad_info.min_wave64_vgpr_alloc;
1787 properties->maxVgprAllocation =
1788 pdevice->rad_info.max_vgpr_alloc;
1789 properties->vgprAllocationGranularity =
1790 pdevice->rad_info.wave64_vgpr_alloc_granularity;
1791 break;
1792 }
1793 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1794 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1795 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1796
1797 properties->shaderCoreFeatures = 0;
1798 properties->activeComputeUnitCount =
1799 pdevice->rad_info.num_good_compute_units;
1800 break;
1801 }
1802 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1803 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1804 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1805 properties->maxVertexAttribDivisor = UINT32_MAX;
1806 break;
1807 }
1808 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES: {
1809 VkPhysicalDeviceDescriptorIndexingProperties *properties =
1810 (VkPhysicalDeviceDescriptorIndexingProperties*)ext;
1811 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools);
1812 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative);
1813 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative);
1814 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative);
1815 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative);
1816 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative);
1817 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind);
1818 CORE_PROPERTY(1, 2, quadDivergentImplicitLod);
1819 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers);
1820 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers);
1821 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers);
1822 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages);
1823 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages);
1824 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments);
1825 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources);
1826 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers);
1827 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers);
1828 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic);
1829 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers);
1830 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic);
1831 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages);
1832 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages);
1833 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments);
1834 break;
1835 }
1836 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1837 VkPhysicalDeviceProtectedMemoryProperties *properties =
1838 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1839 CORE_PROPERTY(1, 1, protectedNoFault);
1840 break;
1841 }
1842 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1843 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1844 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1845 properties->primitiveOverestimationSize = 0;
1846 properties->maxExtraPrimitiveOverestimationSize = 0;
1847 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1848 properties->primitiveUnderestimation = false;
1849 properties->conservativePointAndLineRasterization = false;
1850 properties->degenerateTrianglesRasterized = false;
1851 properties->degenerateLinesRasterized = false;
1852 properties->fullyCoveredFragmentShaderInputVariable = false;
1853 properties->conservativeRasterizationPostDepthCoverage = false;
1854 break;
1855 }
1856 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1857 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1858 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1859 properties->pciDomain = pdevice->bus_info.domain;
1860 properties->pciBus = pdevice->bus_info.bus;
1861 properties->pciDevice = pdevice->bus_info.dev;
1862 properties->pciFunction = pdevice->bus_info.func;
1863 break;
1864 }
1865 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES: {
1866 VkPhysicalDeviceDriverProperties *properties =
1867 (VkPhysicalDeviceDriverProperties *) ext;
1868 CORE_PROPERTY(1, 2, driverID);
1869 CORE_PROPERTY(1, 2, driverName);
1870 CORE_PROPERTY(1, 2, driverInfo);
1871 CORE_PROPERTY(1, 2, conformanceVersion);
1872 break;
1873 }
1874 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1875 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1876 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1877 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1878 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1879 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1880 properties->maxTransformFeedbackStreamDataSize = 512;
1881 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1882 properties->maxTransformFeedbackBufferDataStride = 512;
1883 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1884 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1885 properties->transformFeedbackRasterizationStreamSelect = false;
1886 properties->transformFeedbackDraw = true;
1887 break;
1888 }
1889 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1890 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1891 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1892
1893 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1894 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1895 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1896 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1897 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1898 break;
1899 }
1900 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1901 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1902 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1903 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1904 VK_SAMPLE_COUNT_4_BIT |
1905 VK_SAMPLE_COUNT_8_BIT;
1906 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1907 properties->sampleLocationCoordinateRange[0] = 0.0f;
1908 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1909 properties->sampleLocationSubPixelBits = 4;
1910 properties->variableSampleLocations = false;
1911 break;
1912 }
1913 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES: {
1914 VkPhysicalDeviceDepthStencilResolveProperties *properties =
1915 (VkPhysicalDeviceDepthStencilResolveProperties *)ext;
1916 CORE_PROPERTY(1, 2, supportedDepthResolveModes);
1917 CORE_PROPERTY(1, 2, supportedStencilResolveModes);
1918 CORE_PROPERTY(1, 2, independentResolveNone);
1919 CORE_PROPERTY(1, 2, independentResolve);
1920 break;
1921 }
1922 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
1923 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *properties =
1924 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *)ext;
1925 properties->storageTexelBufferOffsetAlignmentBytes = 4;
1926 properties->storageTexelBufferOffsetSingleTexelAlignment = true;
1927 properties->uniformTexelBufferOffsetAlignmentBytes = 4;
1928 properties->uniformTexelBufferOffsetSingleTexelAlignment = true;
1929 break;
1930 }
1931 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES : {
1932 VkPhysicalDeviceFloatControlsProperties *properties =
1933 (VkPhysicalDeviceFloatControlsProperties *)ext;
1934 CORE_PROPERTY(1, 2, denormBehaviorIndependence);
1935 CORE_PROPERTY(1, 2, roundingModeIndependence);
1936 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16);
1937 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16);
1938 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16);
1939 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16);
1940 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16);
1941 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32);
1942 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32);
1943 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32);
1944 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32);
1945 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32);
1946 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64);
1947 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64);
1948 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64);
1949 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64);
1950 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64);
1951 break;
1952 }
1953 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES: {
1954 VkPhysicalDeviceTimelineSemaphoreProperties *properties =
1955 (VkPhysicalDeviceTimelineSemaphoreProperties *) ext;
1956 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference);
1957 break;
1958 }
1959 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT: {
1960 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *props =
1961 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *)ext;
1962 props->minSubgroupSize = 64;
1963 props->maxSubgroupSize = 64;
1964 props->maxComputeWorkgroupSubgroups = UINT32_MAX;
1965 props->requiredSubgroupSizeStages = 0;
1966
1967 if (pdevice->rad_info.chip_class >= GFX10) {
1968 /* Only GFX10+ supports wave32. */
1969 props->minSubgroupSize = 32;
1970 props->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT;
1971 }
1972 break;
1973 }
1974 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES:
1975 radv_get_physical_device_properties_1_1(pdevice, (void *)ext);
1976 break;
1977 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES:
1978 radv_get_physical_device_properties_1_2(pdevice, (void *)ext);
1979 break;
1980 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT: {
1981 VkPhysicalDeviceLineRasterizationPropertiesEXT *props =
1982 (VkPhysicalDeviceLineRasterizationPropertiesEXT *)ext;
1983 props->lineSubPixelPrecisionBits = 4;
1984 break;
1985 }
1986 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_PROPERTIES_EXT: {
1987 VkPhysicalDeviceRobustness2PropertiesEXT *properties =
1988 (VkPhysicalDeviceRobustness2PropertiesEXT *)ext;
1989 properties->robustStorageBufferAccessSizeAlignment = 4;
1990 properties->robustUniformBufferAccessSizeAlignment = 4;
1991 break;
1992 }
1993 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_PROPERTIES_EXT: {
1994 VkPhysicalDeviceCustomBorderColorPropertiesEXT *props =
1995 (VkPhysicalDeviceCustomBorderColorPropertiesEXT *)ext;
1996 props->maxCustomBorderColorSamplers = RADV_BORDER_COLOR_COUNT;
1997 break;
1998 }
1999 default:
2000 break;
2001 }
2002 }
2003 }
2004
2005 static void radv_get_physical_device_queue_family_properties(
2006 struct radv_physical_device* pdevice,
2007 uint32_t* pCount,
2008 VkQueueFamilyProperties** pQueueFamilyProperties)
2009 {
2010 int num_queue_families = 1;
2011 int idx;
2012 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2013 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
2014 num_queue_families++;
2015
2016 if (pQueueFamilyProperties == NULL) {
2017 *pCount = num_queue_families;
2018 return;
2019 }
2020
2021 if (!*pCount)
2022 return;
2023
2024 idx = 0;
2025 if (*pCount >= 1) {
2026 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2027 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
2028 VK_QUEUE_COMPUTE_BIT |
2029 VK_QUEUE_TRANSFER_BIT |
2030 VK_QUEUE_SPARSE_BINDING_BIT,
2031 .queueCount = 1,
2032 .timestampValidBits = 64,
2033 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2034 };
2035 idx++;
2036 }
2037
2038 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2039 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
2040 if (*pCount > idx) {
2041 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2042 .queueFlags = VK_QUEUE_COMPUTE_BIT |
2043 VK_QUEUE_TRANSFER_BIT |
2044 VK_QUEUE_SPARSE_BINDING_BIT,
2045 .queueCount = pdevice->rad_info.num_rings[RING_COMPUTE],
2046 .timestampValidBits = 64,
2047 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2048 };
2049 idx++;
2050 }
2051 }
2052 *pCount = idx;
2053 }
2054
2055 void radv_GetPhysicalDeviceQueueFamilyProperties(
2056 VkPhysicalDevice physicalDevice,
2057 uint32_t* pCount,
2058 VkQueueFamilyProperties* pQueueFamilyProperties)
2059 {
2060 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2061 if (!pQueueFamilyProperties) {
2062 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2063 return;
2064 }
2065 VkQueueFamilyProperties *properties[] = {
2066 pQueueFamilyProperties + 0,
2067 pQueueFamilyProperties + 1,
2068 pQueueFamilyProperties + 2,
2069 };
2070 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2071 assert(*pCount <= 3);
2072 }
2073
2074 void radv_GetPhysicalDeviceQueueFamilyProperties2(
2075 VkPhysicalDevice physicalDevice,
2076 uint32_t* pCount,
2077 VkQueueFamilyProperties2 *pQueueFamilyProperties)
2078 {
2079 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2080 if (!pQueueFamilyProperties) {
2081 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2082 return;
2083 }
2084 VkQueueFamilyProperties *properties[] = {
2085 &pQueueFamilyProperties[0].queueFamilyProperties,
2086 &pQueueFamilyProperties[1].queueFamilyProperties,
2087 &pQueueFamilyProperties[2].queueFamilyProperties,
2088 };
2089 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2090 assert(*pCount <= 3);
2091 }
2092
2093 void radv_GetPhysicalDeviceMemoryProperties(
2094 VkPhysicalDevice physicalDevice,
2095 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
2096 {
2097 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2098
2099 *pMemoryProperties = physical_device->memory_properties;
2100 }
2101
2102 static void
2103 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
2104 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
2105 {
2106 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2107 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
2108 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
2109 uint64_t vram_size = radv_get_vram_size(device);
2110 uint64_t gtt_size = device->rad_info.gart_size;
2111 uint64_t heap_budget, heap_usage;
2112
2113 /* For all memory heaps, the computation of budget is as follow:
2114 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2115 *
2116 * The Vulkan spec 1.1.97 says that the budget should include any
2117 * currently allocated device memory.
2118 *
2119 * Note that the application heap usages are not really accurate (eg.
2120 * in presence of shared buffers).
2121 */
2122 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
2123 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
2124
2125 if ((device->memory_domains[i] & RADEON_DOMAIN_VRAM) && (device->memory_flags[i] & RADEON_FLAG_NO_CPU_ACCESS)) {
2126 heap_usage = device->ws->query_value(device->ws,
2127 RADEON_ALLOCATED_VRAM);
2128
2129 heap_budget = vram_size -
2130 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
2131 heap_usage;
2132
2133 memoryBudget->heapBudget[heap_index] = heap_budget;
2134 memoryBudget->heapUsage[heap_index] = heap_usage;
2135 } else if (device->memory_domains[i] & RADEON_DOMAIN_VRAM) {
2136 heap_usage = device->ws->query_value(device->ws,
2137 RADEON_ALLOCATED_VRAM_VIS);
2138
2139 heap_budget = visible_vram_size -
2140 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
2141 heap_usage;
2142
2143 memoryBudget->heapBudget[heap_index] = heap_budget;
2144 memoryBudget->heapUsage[heap_index] = heap_usage;
2145 } else {
2146 assert(device->memory_domains[i] & RADEON_DOMAIN_GTT);
2147
2148 heap_usage = device->ws->query_value(device->ws,
2149 RADEON_ALLOCATED_GTT);
2150
2151 heap_budget = gtt_size -
2152 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
2153 heap_usage;
2154
2155 memoryBudget->heapBudget[heap_index] = heap_budget;
2156 memoryBudget->heapUsage[heap_index] = heap_usage;
2157 }
2158 }
2159
2160 /* The heapBudget and heapUsage values must be zero for array elements
2161 * greater than or equal to
2162 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2163 */
2164 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
2165 memoryBudget->heapBudget[i] = 0;
2166 memoryBudget->heapUsage[i] = 0;
2167 }
2168 }
2169
2170 void radv_GetPhysicalDeviceMemoryProperties2(
2171 VkPhysicalDevice physicalDevice,
2172 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
2173 {
2174 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
2175 &pMemoryProperties->memoryProperties);
2176
2177 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
2178 vk_find_struct(pMemoryProperties->pNext,
2179 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
2180 if (memory_budget)
2181 radv_get_memory_budget_properties(physicalDevice, memory_budget);
2182 }
2183
2184 VkResult radv_GetMemoryHostPointerPropertiesEXT(
2185 VkDevice _device,
2186 VkExternalMemoryHandleTypeFlagBits handleType,
2187 const void *pHostPointer,
2188 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
2189 {
2190 RADV_FROM_HANDLE(radv_device, device, _device);
2191
2192 switch (handleType)
2193 {
2194 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
2195 const struct radv_physical_device *physical_device = device->physical_device;
2196 uint32_t memoryTypeBits = 0;
2197 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
2198 if (physical_device->memory_domains[i] == RADEON_DOMAIN_GTT &&
2199 !(physical_device->memory_flags[i] & RADEON_FLAG_GTT_WC)) {
2200 memoryTypeBits = (1 << i);
2201 break;
2202 }
2203 }
2204 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
2205 return VK_SUCCESS;
2206 }
2207 default:
2208 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
2209 }
2210 }
2211
2212 static enum radeon_ctx_priority
2213 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
2214 {
2215 /* Default to MEDIUM when a specific global priority isn't requested */
2216 if (!pObj)
2217 return RADEON_CTX_PRIORITY_MEDIUM;
2218
2219 switch(pObj->globalPriority) {
2220 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
2221 return RADEON_CTX_PRIORITY_REALTIME;
2222 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
2223 return RADEON_CTX_PRIORITY_HIGH;
2224 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
2225 return RADEON_CTX_PRIORITY_MEDIUM;
2226 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
2227 return RADEON_CTX_PRIORITY_LOW;
2228 default:
2229 unreachable("Illegal global priority value");
2230 return RADEON_CTX_PRIORITY_INVALID;
2231 }
2232 }
2233
2234 static int
2235 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
2236 uint32_t queue_family_index, int idx,
2237 VkDeviceQueueCreateFlags flags,
2238 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
2239 {
2240 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2241 queue->device = device;
2242 queue->queue_family_index = queue_family_index;
2243 queue->queue_idx = idx;
2244 queue->priority = radv_get_queue_global_priority(global_priority);
2245 queue->flags = flags;
2246 queue->hw_ctx = NULL;
2247
2248 VkResult result = device->ws->ctx_create(device->ws, queue->priority, &queue->hw_ctx);
2249 if (result != VK_SUCCESS)
2250 return vk_error(device->instance, result);
2251
2252 list_inithead(&queue->pending_submissions);
2253 pthread_mutex_init(&queue->pending_mutex, NULL);
2254
2255 return VK_SUCCESS;
2256 }
2257
2258 static void
2259 radv_queue_finish(struct radv_queue *queue)
2260 {
2261 pthread_mutex_destroy(&queue->pending_mutex);
2262
2263 if (queue->hw_ctx)
2264 queue->device->ws->ctx_destroy(queue->hw_ctx);
2265
2266 if (queue->initial_full_flush_preamble_cs)
2267 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2268 if (queue->initial_preamble_cs)
2269 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2270 if (queue->continue_preamble_cs)
2271 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2272 if (queue->descriptor_bo)
2273 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2274 if (queue->scratch_bo)
2275 queue->device->ws->buffer_destroy(queue->scratch_bo);
2276 if (queue->esgs_ring_bo)
2277 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2278 if (queue->gsvs_ring_bo)
2279 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2280 if (queue->tess_rings_bo)
2281 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
2282 if (queue->gds_bo)
2283 queue->device->ws->buffer_destroy(queue->gds_bo);
2284 if (queue->gds_oa_bo)
2285 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
2286 if (queue->compute_scratch_bo)
2287 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2288 }
2289
2290 static void
2291 radv_bo_list_init(struct radv_bo_list *bo_list)
2292 {
2293 pthread_mutex_init(&bo_list->mutex, NULL);
2294 bo_list->list.count = bo_list->capacity = 0;
2295 bo_list->list.bos = NULL;
2296 }
2297
2298 static void
2299 radv_bo_list_finish(struct radv_bo_list *bo_list)
2300 {
2301 free(bo_list->list.bos);
2302 pthread_mutex_destroy(&bo_list->mutex);
2303 }
2304
2305 VkResult radv_bo_list_add(struct radv_device *device,
2306 struct radeon_winsys_bo *bo)
2307 {
2308 struct radv_bo_list *bo_list = &device->bo_list;
2309
2310 if (bo->is_local)
2311 return VK_SUCCESS;
2312
2313 if (unlikely(!device->use_global_bo_list))
2314 return VK_SUCCESS;
2315
2316 pthread_mutex_lock(&bo_list->mutex);
2317 if (bo_list->list.count == bo_list->capacity) {
2318 unsigned capacity = MAX2(4, bo_list->capacity * 2);
2319 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
2320
2321 if (!data) {
2322 pthread_mutex_unlock(&bo_list->mutex);
2323 return VK_ERROR_OUT_OF_HOST_MEMORY;
2324 }
2325
2326 bo_list->list.bos = (struct radeon_winsys_bo**)data;
2327 bo_list->capacity = capacity;
2328 }
2329
2330 bo_list->list.bos[bo_list->list.count++] = bo;
2331 pthread_mutex_unlock(&bo_list->mutex);
2332 return VK_SUCCESS;
2333 }
2334
2335 void radv_bo_list_remove(struct radv_device *device,
2336 struct radeon_winsys_bo *bo)
2337 {
2338 struct radv_bo_list *bo_list = &device->bo_list;
2339
2340 if (bo->is_local)
2341 return;
2342
2343 if (unlikely(!device->use_global_bo_list))
2344 return;
2345
2346 pthread_mutex_lock(&bo_list->mutex);
2347 /* Loop the list backwards so we find the most recently added
2348 * memory first. */
2349 for(unsigned i = bo_list->list.count; i-- > 0;) {
2350 if (bo_list->list.bos[i] == bo) {
2351 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
2352 --bo_list->list.count;
2353 break;
2354 }
2355 }
2356 pthread_mutex_unlock(&bo_list->mutex);
2357 }
2358
2359 static void
2360 radv_device_init_gs_info(struct radv_device *device)
2361 {
2362 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
2363 device->physical_device->rad_info.family);
2364 }
2365
2366 static int radv_get_device_extension_index(const char *name)
2367 {
2368 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
2369 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
2370 return i;
2371 }
2372 return -1;
2373 }
2374
2375 static int
2376 radv_get_int_debug_option(const char *name, int default_value)
2377 {
2378 const char *str;
2379 int result;
2380
2381 str = getenv(name);
2382 if (!str) {
2383 result = default_value;
2384 } else {
2385 char *endptr;
2386
2387 result = strtol(str, &endptr, 0);
2388 if (str == endptr) {
2389 /* No digits founs. */
2390 result = default_value;
2391 }
2392 }
2393
2394 return result;
2395 }
2396
2397 static void
2398 radv_device_init_dispatch(struct radv_device *device)
2399 {
2400 const struct radv_instance *instance = device->physical_device->instance;
2401 const struct radv_device_dispatch_table *dispatch_table_layer = NULL;
2402 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
2403 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2404
2405 if (radv_thread_trace >= 0) {
2406 /* Use device entrypoints from the SQTT layer if enabled. */
2407 dispatch_table_layer = &sqtt_device_dispatch_table;
2408 }
2409
2410 for (unsigned i = 0; i < ARRAY_SIZE(device->dispatch.entrypoints); i++) {
2411 /* Vulkan requires that entrypoints for extensions which have not been
2412 * enabled must not be advertised.
2413 */
2414 if (!unchecked &&
2415 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
2416 &instance->enabled_extensions,
2417 &device->enabled_extensions)) {
2418 device->dispatch.entrypoints[i] = NULL;
2419 } else if (dispatch_table_layer &&
2420 dispatch_table_layer->entrypoints[i]) {
2421 device->dispatch.entrypoints[i] =
2422 dispatch_table_layer->entrypoints[i];
2423 } else {
2424 device->dispatch.entrypoints[i] =
2425 radv_device_dispatch_table.entrypoints[i];
2426 }
2427 }
2428 }
2429
2430 static VkResult
2431 radv_create_pthread_cond(pthread_cond_t *cond)
2432 {
2433 pthread_condattr_t condattr;
2434 if (pthread_condattr_init(&condattr)) {
2435 return VK_ERROR_INITIALIZATION_FAILED;
2436 }
2437
2438 if (pthread_condattr_setclock(&condattr, CLOCK_MONOTONIC)) {
2439 pthread_condattr_destroy(&condattr);
2440 return VK_ERROR_INITIALIZATION_FAILED;
2441 }
2442 if (pthread_cond_init(cond, &condattr)) {
2443 pthread_condattr_destroy(&condattr);
2444 return VK_ERROR_INITIALIZATION_FAILED;
2445 }
2446 pthread_condattr_destroy(&condattr);
2447 return VK_SUCCESS;
2448 }
2449
2450 static VkResult
2451 check_physical_device_features(VkPhysicalDevice physicalDevice,
2452 const VkPhysicalDeviceFeatures *features)
2453 {
2454 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2455 VkPhysicalDeviceFeatures supported_features;
2456 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
2457 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
2458 VkBool32 *enabled_feature = (VkBool32 *)features;
2459 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
2460 for (uint32_t i = 0; i < num_features; i++) {
2461 if (enabled_feature[i] && !supported_feature[i])
2462 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
2463 }
2464
2465 return VK_SUCCESS;
2466 }
2467
2468 static VkResult radv_device_init_border_color(struct radv_device *device)
2469 {
2470 device->border_color_data.bo =
2471 device->ws->buffer_create(device->ws,
2472 RADV_BORDER_COLOR_BUFFER_SIZE,
2473 4096,
2474 RADEON_DOMAIN_VRAM,
2475 RADEON_FLAG_CPU_ACCESS |
2476 RADEON_FLAG_READ_ONLY |
2477 RADEON_FLAG_NO_INTERPROCESS_SHARING,
2478 RADV_BO_PRIORITY_SHADER);
2479
2480 if (device->border_color_data.bo == NULL)
2481 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2482
2483 device->border_color_data.colors_gpu_ptr =
2484 device->ws->buffer_map(device->border_color_data.bo);
2485 if (!device->border_color_data.colors_gpu_ptr)
2486 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2487 pthread_mutex_init(&device->border_color_data.mutex, NULL);
2488
2489 return VK_SUCCESS;
2490 }
2491
2492 static void radv_device_finish_border_color(struct radv_device *device)
2493 {
2494 if (device->border_color_data.bo) {
2495 device->ws->buffer_destroy(device->border_color_data.bo);
2496
2497 pthread_mutex_destroy(&device->border_color_data.mutex);
2498 }
2499 }
2500
2501 VkResult radv_CreateDevice(
2502 VkPhysicalDevice physicalDevice,
2503 const VkDeviceCreateInfo* pCreateInfo,
2504 const VkAllocationCallbacks* pAllocator,
2505 VkDevice* pDevice)
2506 {
2507 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2508 VkResult result;
2509 struct radv_device *device;
2510
2511 bool keep_shader_info = false;
2512 bool robust_buffer_access = false;
2513 bool overallocation_disallowed = false;
2514 bool custom_border_colors = false;
2515
2516 /* Check enabled features */
2517 if (pCreateInfo->pEnabledFeatures) {
2518 result = check_physical_device_features(physicalDevice,
2519 pCreateInfo->pEnabledFeatures);
2520 if (result != VK_SUCCESS)
2521 return result;
2522
2523 if (pCreateInfo->pEnabledFeatures->robustBufferAccess)
2524 robust_buffer_access = true;
2525 }
2526
2527 vk_foreach_struct_const(ext, pCreateInfo->pNext) {
2528 switch (ext->sType) {
2529 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2: {
2530 const VkPhysicalDeviceFeatures2 *features = (const void *)ext;
2531 result = check_physical_device_features(physicalDevice,
2532 &features->features);
2533 if (result != VK_SUCCESS)
2534 return result;
2535
2536 if (features->features.robustBufferAccess)
2537 robust_buffer_access = true;
2538 break;
2539 }
2540 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
2541 const VkDeviceMemoryOverallocationCreateInfoAMD *overallocation = (const void *)ext;
2542 if (overallocation->overallocationBehavior == VK_MEMORY_OVERALLOCATION_BEHAVIOR_DISALLOWED_AMD)
2543 overallocation_disallowed = true;
2544 break;
2545 }
2546 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
2547 const VkPhysicalDeviceCustomBorderColorFeaturesEXT *border_color_features = (const void *)ext;
2548 custom_border_colors = border_color_features->customBorderColors;
2549 break;
2550 }
2551 default:
2552 break;
2553 }
2554 }
2555
2556 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
2557 sizeof(*device), 8,
2558 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2559 if (!device)
2560 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2561
2562 vk_device_init(&device->vk, pCreateInfo,
2563 &physical_device->instance->alloc, pAllocator);
2564
2565 device->instance = physical_device->instance;
2566 device->physical_device = physical_device;
2567
2568 device->ws = physical_device->ws;
2569
2570 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
2571 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
2572 int index = radv_get_device_extension_index(ext_name);
2573 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
2574 vk_free(&device->vk.alloc, device);
2575 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
2576 }
2577
2578 device->enabled_extensions.extensions[index] = true;
2579 }
2580
2581 radv_device_init_dispatch(device);
2582
2583 keep_shader_info = device->enabled_extensions.AMD_shader_info;
2584
2585 /* With update after bind we can't attach bo's to the command buffer
2586 * from the descriptor set anymore, so we have to use a global BO list.
2587 */
2588 device->use_global_bo_list =
2589 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
2590 device->enabled_extensions.EXT_descriptor_indexing ||
2591 device->enabled_extensions.EXT_buffer_device_address ||
2592 device->enabled_extensions.KHR_buffer_device_address;
2593
2594 device->robust_buffer_access = robust_buffer_access;
2595
2596 mtx_init(&device->shader_slab_mutex, mtx_plain);
2597 list_inithead(&device->shader_slabs);
2598
2599 device->overallocation_disallowed = overallocation_disallowed;
2600 mtx_init(&device->overallocation_mutex, mtx_plain);
2601
2602 radv_bo_list_init(&device->bo_list);
2603
2604 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
2605 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
2606 uint32_t qfi = queue_create->queueFamilyIndex;
2607 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
2608 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
2609
2610 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
2611
2612 device->queues[qfi] = vk_alloc(&device->vk.alloc,
2613 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2614 if (!device->queues[qfi]) {
2615 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2616 goto fail;
2617 }
2618
2619 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
2620
2621 device->queue_count[qfi] = queue_create->queueCount;
2622
2623 for (unsigned q = 0; q < queue_create->queueCount; q++) {
2624 result = radv_queue_init(device, &device->queues[qfi][q],
2625 qfi, q, queue_create->flags,
2626 global_priority);
2627 if (result != VK_SUCCESS)
2628 goto fail;
2629 }
2630 }
2631
2632 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
2633 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
2634
2635 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2636 device->dfsm_allowed = device->pbb_allowed &&
2637 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
2638
2639 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
2640
2641 /* The maximum number of scratch waves. Scratch space isn't divided
2642 * evenly between CUs. The number is only a function of the number of CUs.
2643 * We can decrease the constant to decrease the scratch buffer size.
2644 *
2645 * sctx->scratch_waves must be >= the maximum possible size of
2646 * 1 threadgroup, so that the hw doesn't hang from being unable
2647 * to start any.
2648 *
2649 * The recommended value is 4 per CU at most. Higher numbers don't
2650 * bring much benefit, but they still occupy chip resources (think
2651 * async compute). I've seen ~2% performance difference between 4 and 32.
2652 */
2653 uint32_t max_threads_per_block = 2048;
2654 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
2655 max_threads_per_block / 64);
2656
2657 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
2658
2659 if (device->physical_device->rad_info.chip_class >= GFX7) {
2660 /* If the KMD allows it (there is a KMD hw register for it),
2661 * allow launching waves out-of-order.
2662 */
2663 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
2664 }
2665
2666 radv_device_init_gs_info(device);
2667
2668 device->tess_offchip_block_dw_size =
2669 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2670
2671 if (getenv("RADV_TRACE_FILE")) {
2672 const char *filename = getenv("RADV_TRACE_FILE");
2673
2674 keep_shader_info = true;
2675
2676 if (!radv_init_trace(device))
2677 goto fail;
2678
2679 fprintf(stderr, "*****************************************************************************\n");
2680 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2681 fprintf(stderr, "*****************************************************************************\n");
2682
2683 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2684 radv_dump_enabled_options(device, stderr);
2685 }
2686
2687 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2688 if (radv_thread_trace >= 0) {
2689 fprintf(stderr, "*************************************************\n");
2690 fprintf(stderr, "* WARNING: Thread trace support is experimental *\n");
2691 fprintf(stderr, "*************************************************\n");
2692
2693 if (device->physical_device->rad_info.chip_class < GFX8) {
2694 fprintf(stderr, "GPU hardware not supported: refer to "
2695 "the RGP documentation for the list of "
2696 "supported GPUs!\n");
2697 abort();
2698 }
2699
2700 /* Default buffer size set to 1MB per SE. */
2701 device->thread_trace_buffer_size =
2702 radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024);
2703 device->thread_trace_start_frame = radv_thread_trace;
2704
2705 if (!radv_thread_trace_init(device))
2706 goto fail;
2707 }
2708
2709 device->keep_shader_info = keep_shader_info;
2710 result = radv_device_init_meta(device);
2711 if (result != VK_SUCCESS)
2712 goto fail;
2713
2714 radv_device_init_msaa(device);
2715
2716 /* If the border color extension is enabled, let's create the buffer we need. */
2717 if (custom_border_colors) {
2718 result = radv_device_init_border_color(device);
2719 if (result != VK_SUCCESS)
2720 goto fail;
2721 }
2722
2723 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2724 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2725 if (!device->empty_cs[family])
2726 goto fail;
2727
2728 switch (family) {
2729 case RADV_QUEUE_GENERAL:
2730 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2731 radeon_emit(device->empty_cs[family], CC0_UPDATE_LOAD_ENABLES(1));
2732 radeon_emit(device->empty_cs[family], CC1_UPDATE_SHADOW_ENABLES(1));
2733 break;
2734 case RADV_QUEUE_COMPUTE:
2735 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2736 radeon_emit(device->empty_cs[family], 0);
2737 break;
2738 }
2739
2740 result = device->ws->cs_finalize(device->empty_cs[family]);
2741 if (result != VK_SUCCESS)
2742 goto fail;
2743 }
2744
2745 if (device->physical_device->rad_info.chip_class >= GFX7)
2746 cik_create_gfx_config(device);
2747
2748 VkPipelineCacheCreateInfo ci;
2749 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2750 ci.pNext = NULL;
2751 ci.flags = 0;
2752 ci.pInitialData = NULL;
2753 ci.initialDataSize = 0;
2754 VkPipelineCache pc;
2755 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2756 &ci, NULL, &pc);
2757 if (result != VK_SUCCESS)
2758 goto fail_meta;
2759
2760 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2761
2762 result = radv_create_pthread_cond(&device->timeline_cond);
2763 if (result != VK_SUCCESS)
2764 goto fail_mem_cache;
2765
2766 device->force_aniso =
2767 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2768 if (device->force_aniso >= 0) {
2769 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2770 1 << util_logbase2(device->force_aniso));
2771 }
2772
2773 *pDevice = radv_device_to_handle(device);
2774 return VK_SUCCESS;
2775
2776 fail_mem_cache:
2777 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2778 fail_meta:
2779 radv_device_finish_meta(device);
2780 fail:
2781 radv_bo_list_finish(&device->bo_list);
2782
2783 radv_thread_trace_finish(device);
2784
2785 if (device->trace_bo)
2786 device->ws->buffer_destroy(device->trace_bo);
2787
2788 if (device->gfx_init)
2789 device->ws->buffer_destroy(device->gfx_init);
2790
2791 radv_device_finish_border_color(device);
2792
2793 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2794 for (unsigned q = 0; q < device->queue_count[i]; q++)
2795 radv_queue_finish(&device->queues[i][q]);
2796 if (device->queue_count[i])
2797 vk_free(&device->vk.alloc, device->queues[i]);
2798 }
2799
2800 vk_free(&device->vk.alloc, device);
2801 return result;
2802 }
2803
2804 void radv_DestroyDevice(
2805 VkDevice _device,
2806 const VkAllocationCallbacks* pAllocator)
2807 {
2808 RADV_FROM_HANDLE(radv_device, device, _device);
2809
2810 if (!device)
2811 return;
2812
2813 if (device->trace_bo)
2814 device->ws->buffer_destroy(device->trace_bo);
2815
2816 if (device->gfx_init)
2817 device->ws->buffer_destroy(device->gfx_init);
2818
2819 radv_device_finish_border_color(device);
2820
2821 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2822 for (unsigned q = 0; q < device->queue_count[i]; q++)
2823 radv_queue_finish(&device->queues[i][q]);
2824 if (device->queue_count[i])
2825 vk_free(&device->vk.alloc, device->queues[i]);
2826 if (device->empty_cs[i])
2827 device->ws->cs_destroy(device->empty_cs[i]);
2828 }
2829 radv_device_finish_meta(device);
2830
2831 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2832 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2833
2834 radv_destroy_shader_slabs(device);
2835
2836 pthread_cond_destroy(&device->timeline_cond);
2837 radv_bo_list_finish(&device->bo_list);
2838
2839 radv_thread_trace_finish(device);
2840
2841 vk_free(&device->vk.alloc, device);
2842 }
2843
2844 VkResult radv_EnumerateInstanceLayerProperties(
2845 uint32_t* pPropertyCount,
2846 VkLayerProperties* pProperties)
2847 {
2848 if (pProperties == NULL) {
2849 *pPropertyCount = 0;
2850 return VK_SUCCESS;
2851 }
2852
2853 /* None supported at this time */
2854 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2855 }
2856
2857 VkResult radv_EnumerateDeviceLayerProperties(
2858 VkPhysicalDevice physicalDevice,
2859 uint32_t* pPropertyCount,
2860 VkLayerProperties* pProperties)
2861 {
2862 if (pProperties == NULL) {
2863 *pPropertyCount = 0;
2864 return VK_SUCCESS;
2865 }
2866
2867 /* None supported at this time */
2868 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2869 }
2870
2871 void radv_GetDeviceQueue2(
2872 VkDevice _device,
2873 const VkDeviceQueueInfo2* pQueueInfo,
2874 VkQueue* pQueue)
2875 {
2876 RADV_FROM_HANDLE(radv_device, device, _device);
2877 struct radv_queue *queue;
2878
2879 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2880 if (pQueueInfo->flags != queue->flags) {
2881 /* From the Vulkan 1.1.70 spec:
2882 *
2883 * "The queue returned by vkGetDeviceQueue2 must have the same
2884 * flags value from this structure as that used at device
2885 * creation time in a VkDeviceQueueCreateInfo instance. If no
2886 * matching flags were specified at device creation time then
2887 * pQueue will return VK_NULL_HANDLE."
2888 */
2889 *pQueue = VK_NULL_HANDLE;
2890 return;
2891 }
2892
2893 *pQueue = radv_queue_to_handle(queue);
2894 }
2895
2896 void radv_GetDeviceQueue(
2897 VkDevice _device,
2898 uint32_t queueFamilyIndex,
2899 uint32_t queueIndex,
2900 VkQueue* pQueue)
2901 {
2902 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2903 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2904 .queueFamilyIndex = queueFamilyIndex,
2905 .queueIndex = queueIndex
2906 };
2907
2908 radv_GetDeviceQueue2(_device, &info, pQueue);
2909 }
2910
2911 static void
2912 fill_geom_tess_rings(struct radv_queue *queue,
2913 uint32_t *map,
2914 bool add_sample_positions,
2915 uint32_t esgs_ring_size,
2916 struct radeon_winsys_bo *esgs_ring_bo,
2917 uint32_t gsvs_ring_size,
2918 struct radeon_winsys_bo *gsvs_ring_bo,
2919 uint32_t tess_factor_ring_size,
2920 uint32_t tess_offchip_ring_offset,
2921 uint32_t tess_offchip_ring_size,
2922 struct radeon_winsys_bo *tess_rings_bo)
2923 {
2924 uint32_t *desc = &map[4];
2925
2926 if (esgs_ring_bo) {
2927 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2928
2929 /* stride 0, num records - size, add tid, swizzle, elsize4,
2930 index stride 64 */
2931 desc[0] = esgs_va;
2932 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2933 S_008F04_SWIZZLE_ENABLE(true);
2934 desc[2] = esgs_ring_size;
2935 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2936 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2937 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2938 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2939 S_008F0C_INDEX_STRIDE(3) |
2940 S_008F0C_ADD_TID_ENABLE(1);
2941
2942 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2943 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2944 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
2945 S_008F0C_RESOURCE_LEVEL(1);
2946 } else {
2947 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2948 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2949 S_008F0C_ELEMENT_SIZE(1);
2950 }
2951
2952 /* GS entry for ES->GS ring */
2953 /* stride 0, num records - size, elsize0,
2954 index stride 0 */
2955 desc[4] = esgs_va;
2956 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
2957 desc[6] = esgs_ring_size;
2958 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2959 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2960 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2961 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2962
2963 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2964 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2965 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
2966 S_008F0C_RESOURCE_LEVEL(1);
2967 } else {
2968 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2969 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2970 }
2971 }
2972
2973 desc += 8;
2974
2975 if (gsvs_ring_bo) {
2976 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2977
2978 /* VS entry for GS->VS ring */
2979 /* stride 0, num records - size, elsize0,
2980 index stride 0 */
2981 desc[0] = gsvs_va;
2982 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
2983 desc[2] = gsvs_ring_size;
2984 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2985 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2986 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2987 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2988
2989 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2990 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2991 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
2992 S_008F0C_RESOURCE_LEVEL(1);
2993 } else {
2994 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2995 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2996 }
2997
2998 /* stride gsvs_itemsize, num records 64
2999 elsize 4, index stride 16 */
3000 /* shader will patch stride and desc[2] */
3001 desc[4] = gsvs_va;
3002 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
3003 S_008F04_SWIZZLE_ENABLE(1);
3004 desc[6] = 0;
3005 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3006 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3007 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3008 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3009 S_008F0C_INDEX_STRIDE(1) |
3010 S_008F0C_ADD_TID_ENABLE(true);
3011
3012 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3013 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3014 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3015 S_008F0C_RESOURCE_LEVEL(1);
3016 } else {
3017 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3018 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3019 S_008F0C_ELEMENT_SIZE(1);
3020 }
3021
3022 }
3023
3024 desc += 8;
3025
3026 if (tess_rings_bo) {
3027 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
3028 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
3029
3030 desc[0] = tess_va;
3031 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
3032 desc[2] = tess_factor_ring_size;
3033 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3034 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3035 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3036 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3037
3038 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3039 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3040 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3041 S_008F0C_RESOURCE_LEVEL(1);
3042 } else {
3043 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3044 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3045 }
3046
3047 desc[4] = tess_offchip_va;
3048 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
3049 desc[6] = tess_offchip_ring_size;
3050 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3051 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3052 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3053 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3054
3055 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3056 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3057 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3058 S_008F0C_RESOURCE_LEVEL(1);
3059 } else {
3060 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3061 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3062 }
3063 }
3064
3065 desc += 8;
3066
3067 if (add_sample_positions) {
3068 /* add sample positions after all rings */
3069 memcpy(desc, queue->device->sample_locations_1x, 8);
3070 desc += 2;
3071 memcpy(desc, queue->device->sample_locations_2x, 16);
3072 desc += 4;
3073 memcpy(desc, queue->device->sample_locations_4x, 32);
3074 desc += 8;
3075 memcpy(desc, queue->device->sample_locations_8x, 64);
3076 }
3077 }
3078
3079 static unsigned
3080 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
3081 {
3082 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
3083 device->physical_device->rad_info.family != CHIP_CARRIZO &&
3084 device->physical_device->rad_info.family != CHIP_STONEY;
3085 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
3086 unsigned max_offchip_buffers;
3087 unsigned offchip_granularity;
3088 unsigned hs_offchip_param;
3089
3090 /*
3091 * Per RadeonSI:
3092 * This must be one less than the maximum number due to a hw limitation.
3093 * Various hardware bugs need thGFX7
3094 *
3095 * Per AMDVLK:
3096 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3097 * Gfx7 should limit max_offchip_buffers to 508
3098 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3099 *
3100 * Follow AMDVLK here.
3101 */
3102 if (device->physical_device->rad_info.chip_class >= GFX10) {
3103 max_offchip_buffers_per_se = 256;
3104 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
3105 device->physical_device->rad_info.chip_class == GFX7 ||
3106 device->physical_device->rad_info.chip_class == GFX6)
3107 --max_offchip_buffers_per_se;
3108
3109 max_offchip_buffers = max_offchip_buffers_per_se *
3110 device->physical_device->rad_info.max_se;
3111
3112 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3113 * around by setting 4K granularity.
3114 */
3115 if (device->tess_offchip_block_dw_size == 4096) {
3116 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
3117 offchip_granularity = V_03093C_X_4K_DWORDS;
3118 } else {
3119 assert(device->tess_offchip_block_dw_size == 8192);
3120 offchip_granularity = V_03093C_X_8K_DWORDS;
3121 }
3122
3123 switch (device->physical_device->rad_info.chip_class) {
3124 case GFX6:
3125 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
3126 break;
3127 case GFX7:
3128 case GFX8:
3129 case GFX9:
3130 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
3131 break;
3132 case GFX10:
3133 break;
3134 default:
3135 break;
3136 }
3137
3138 *max_offchip_buffers_p = max_offchip_buffers;
3139 if (device->physical_device->rad_info.chip_class >= GFX10_3) {
3140 hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers - 1) |
3141 S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity);
3142 } else if (device->physical_device->rad_info.chip_class >= GFX7) {
3143 if (device->physical_device->rad_info.chip_class >= GFX8)
3144 --max_offchip_buffers;
3145 hs_offchip_param =
3146 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
3147 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
3148 } else {
3149 hs_offchip_param =
3150 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
3151 }
3152 return hs_offchip_param;
3153 }
3154
3155 static void
3156 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3157 struct radeon_winsys_bo *esgs_ring_bo,
3158 uint32_t esgs_ring_size,
3159 struct radeon_winsys_bo *gsvs_ring_bo,
3160 uint32_t gsvs_ring_size)
3161 {
3162 if (!esgs_ring_bo && !gsvs_ring_bo)
3163 return;
3164
3165 if (esgs_ring_bo)
3166 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
3167
3168 if (gsvs_ring_bo)
3169 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
3170
3171 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3172 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
3173 radeon_emit(cs, esgs_ring_size >> 8);
3174 radeon_emit(cs, gsvs_ring_size >> 8);
3175 } else {
3176 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
3177 radeon_emit(cs, esgs_ring_size >> 8);
3178 radeon_emit(cs, gsvs_ring_size >> 8);
3179 }
3180 }
3181
3182 static void
3183 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3184 unsigned hs_offchip_param, unsigned tf_ring_size,
3185 struct radeon_winsys_bo *tess_rings_bo)
3186 {
3187 uint64_t tf_va;
3188
3189 if (!tess_rings_bo)
3190 return;
3191
3192 tf_va = radv_buffer_get_va(tess_rings_bo);
3193
3194 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
3195
3196 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3197 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
3198 S_030938_SIZE(tf_ring_size / 4));
3199 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
3200 tf_va >> 8);
3201
3202 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3203 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3204 S_030984_BASE_HI(tf_va >> 40));
3205 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3206 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
3207 S_030944_BASE_HI(tf_va >> 40));
3208 }
3209 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
3210 hs_offchip_param);
3211 } else {
3212 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
3213 S_008988_SIZE(tf_ring_size / 4));
3214 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
3215 tf_va >> 8);
3216 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3217 hs_offchip_param);
3218 }
3219 }
3220
3221 static void
3222 radv_emit_graphics_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3223 uint32_t size_per_wave, uint32_t waves,
3224 struct radeon_winsys_bo *scratch_bo)
3225 {
3226 if (queue->queue_family_index != RADV_QUEUE_GENERAL)
3227 return;
3228
3229 if (!scratch_bo)
3230 return;
3231
3232 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3233
3234 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3235 S_0286E8_WAVES(waves) |
3236 S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3237 }
3238
3239 static void
3240 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3241 uint32_t size_per_wave, uint32_t waves,
3242 struct radeon_winsys_bo *compute_scratch_bo)
3243 {
3244 uint64_t scratch_va;
3245
3246 if (!compute_scratch_bo)
3247 return;
3248
3249 scratch_va = radv_buffer_get_va(compute_scratch_bo);
3250
3251 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
3252
3253 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
3254 radeon_emit(cs, scratch_va);
3255 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3256 S_008F04_SWIZZLE_ENABLE(1));
3257
3258 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
3259 S_00B860_WAVES(waves) |
3260 S_00B860_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3261 }
3262
3263 static void
3264 radv_emit_global_shader_pointers(struct radv_queue *queue,
3265 struct radeon_cmdbuf *cs,
3266 struct radeon_winsys_bo *descriptor_bo)
3267 {
3268 uint64_t va;
3269
3270 if (!descriptor_bo)
3271 return;
3272
3273 va = radv_buffer_get_va(descriptor_bo);
3274
3275 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
3276
3277 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3278 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3279 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3280 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3281 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3282
3283 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3284 radv_emit_shader_pointer(queue->device, cs, regs[i],
3285 va, true);
3286 }
3287 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3288 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3289 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3290 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3291 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3292
3293 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3294 radv_emit_shader_pointer(queue->device, cs, regs[i],
3295 va, true);
3296 }
3297 } else {
3298 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3299 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3300 R_00B230_SPI_SHADER_USER_DATA_GS_0,
3301 R_00B330_SPI_SHADER_USER_DATA_ES_0,
3302 R_00B430_SPI_SHADER_USER_DATA_HS_0,
3303 R_00B530_SPI_SHADER_USER_DATA_LS_0};
3304
3305 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3306 radv_emit_shader_pointer(queue->device, cs, regs[i],
3307 va, true);
3308 }
3309 }
3310 }
3311
3312 static void
3313 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3314 {
3315 struct radv_device *device = queue->device;
3316
3317 if (device->gfx_init) {
3318 uint64_t va = radv_buffer_get_va(device->gfx_init);
3319
3320 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
3321 radeon_emit(cs, va);
3322 radeon_emit(cs, va >> 32);
3323 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
3324
3325 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
3326 } else {
3327 si_emit_graphics(device, cs);
3328 }
3329 }
3330
3331 static void
3332 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3333 {
3334 struct radv_physical_device *physical_device = queue->device->physical_device;
3335 si_emit_compute(physical_device, cs);
3336 }
3337
3338 static VkResult
3339 radv_get_preamble_cs(struct radv_queue *queue,
3340 uint32_t scratch_size_per_wave,
3341 uint32_t scratch_waves,
3342 uint32_t compute_scratch_size_per_wave,
3343 uint32_t compute_scratch_waves,
3344 uint32_t esgs_ring_size,
3345 uint32_t gsvs_ring_size,
3346 bool needs_tess_rings,
3347 bool needs_gds,
3348 bool needs_gds_oa,
3349 bool needs_sample_positions,
3350 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
3351 struct radeon_cmdbuf **initial_preamble_cs,
3352 struct radeon_cmdbuf **continue_preamble_cs)
3353 {
3354 struct radeon_winsys_bo *scratch_bo = NULL;
3355 struct radeon_winsys_bo *descriptor_bo = NULL;
3356 struct radeon_winsys_bo *compute_scratch_bo = NULL;
3357 struct radeon_winsys_bo *esgs_ring_bo = NULL;
3358 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
3359 struct radeon_winsys_bo *tess_rings_bo = NULL;
3360 struct radeon_winsys_bo *gds_bo = NULL;
3361 struct radeon_winsys_bo *gds_oa_bo = NULL;
3362 struct radeon_cmdbuf *dest_cs[3] = {0};
3363 bool add_tess_rings = false, add_gds = false, add_gds_oa = false, add_sample_positions = false;
3364 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
3365 unsigned max_offchip_buffers;
3366 unsigned hs_offchip_param = 0;
3367 unsigned tess_offchip_ring_offset;
3368 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
3369 if (!queue->has_tess_rings) {
3370 if (needs_tess_rings)
3371 add_tess_rings = true;
3372 }
3373 if (!queue->has_gds) {
3374 if (needs_gds)
3375 add_gds = true;
3376 }
3377 if (!queue->has_gds_oa) {
3378 if (needs_gds_oa)
3379 add_gds_oa = true;
3380 }
3381 if (!queue->has_sample_positions) {
3382 if (needs_sample_positions)
3383 add_sample_positions = true;
3384 }
3385 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
3386 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
3387 &max_offchip_buffers);
3388 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
3389 tess_offchip_ring_size = max_offchip_buffers *
3390 queue->device->tess_offchip_block_dw_size * 4;
3391
3392 scratch_size_per_wave = MAX2(scratch_size_per_wave, queue->scratch_size_per_wave);
3393 if (scratch_size_per_wave)
3394 scratch_waves = MIN2(scratch_waves, UINT32_MAX / scratch_size_per_wave);
3395 else
3396 scratch_waves = 0;
3397
3398 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave, queue->compute_scratch_size_per_wave);
3399 if (compute_scratch_size_per_wave)
3400 compute_scratch_waves = MIN2(compute_scratch_waves, UINT32_MAX / compute_scratch_size_per_wave);
3401 else
3402 compute_scratch_waves = 0;
3403
3404 if (scratch_size_per_wave <= queue->scratch_size_per_wave &&
3405 scratch_waves <= queue->scratch_waves &&
3406 compute_scratch_size_per_wave <= queue->compute_scratch_size_per_wave &&
3407 compute_scratch_waves <= queue->compute_scratch_waves &&
3408 esgs_ring_size <= queue->esgs_ring_size &&
3409 gsvs_ring_size <= queue->gsvs_ring_size &&
3410 !add_tess_rings && !add_gds && !add_gds_oa && !add_sample_positions &&
3411 queue->initial_preamble_cs) {
3412 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3413 *initial_preamble_cs = queue->initial_preamble_cs;
3414 *continue_preamble_cs = queue->continue_preamble_cs;
3415 if (!scratch_size_per_wave && !compute_scratch_size_per_wave &&
3416 !esgs_ring_size && !gsvs_ring_size && !needs_tess_rings &&
3417 !needs_gds && !needs_gds_oa && !needs_sample_positions)
3418 *continue_preamble_cs = NULL;
3419 return VK_SUCCESS;
3420 }
3421
3422 uint32_t scratch_size = scratch_size_per_wave * scratch_waves;
3423 uint32_t queue_scratch_size = queue->scratch_size_per_wave * queue->scratch_waves;
3424 if (scratch_size > queue_scratch_size) {
3425 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3426 scratch_size,
3427 4096,
3428 RADEON_DOMAIN_VRAM,
3429 ring_bo_flags,
3430 RADV_BO_PRIORITY_SCRATCH);
3431 if (!scratch_bo)
3432 goto fail;
3433 } else
3434 scratch_bo = queue->scratch_bo;
3435
3436 uint32_t compute_scratch_size = compute_scratch_size_per_wave * compute_scratch_waves;
3437 uint32_t compute_queue_scratch_size = queue->compute_scratch_size_per_wave * queue->compute_scratch_waves;
3438 if (compute_scratch_size > compute_queue_scratch_size) {
3439 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3440 compute_scratch_size,
3441 4096,
3442 RADEON_DOMAIN_VRAM,
3443 ring_bo_flags,
3444 RADV_BO_PRIORITY_SCRATCH);
3445 if (!compute_scratch_bo)
3446 goto fail;
3447
3448 } else
3449 compute_scratch_bo = queue->compute_scratch_bo;
3450
3451 if (esgs_ring_size > queue->esgs_ring_size) {
3452 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3453 esgs_ring_size,
3454 4096,
3455 RADEON_DOMAIN_VRAM,
3456 ring_bo_flags,
3457 RADV_BO_PRIORITY_SCRATCH);
3458 if (!esgs_ring_bo)
3459 goto fail;
3460 } else {
3461 esgs_ring_bo = queue->esgs_ring_bo;
3462 esgs_ring_size = queue->esgs_ring_size;
3463 }
3464
3465 if (gsvs_ring_size > queue->gsvs_ring_size) {
3466 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3467 gsvs_ring_size,
3468 4096,
3469 RADEON_DOMAIN_VRAM,
3470 ring_bo_flags,
3471 RADV_BO_PRIORITY_SCRATCH);
3472 if (!gsvs_ring_bo)
3473 goto fail;
3474 } else {
3475 gsvs_ring_bo = queue->gsvs_ring_bo;
3476 gsvs_ring_size = queue->gsvs_ring_size;
3477 }
3478
3479 if (add_tess_rings) {
3480 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
3481 tess_offchip_ring_offset + tess_offchip_ring_size,
3482 256,
3483 RADEON_DOMAIN_VRAM,
3484 ring_bo_flags,
3485 RADV_BO_PRIORITY_SCRATCH);
3486 if (!tess_rings_bo)
3487 goto fail;
3488 } else {
3489 tess_rings_bo = queue->tess_rings_bo;
3490 }
3491
3492 if (add_gds) {
3493 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3494
3495 /* 4 streamout GDS counters.
3496 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3497 */
3498 gds_bo = queue->device->ws->buffer_create(queue->device->ws,
3499 256, 4,
3500 RADEON_DOMAIN_GDS,
3501 ring_bo_flags,
3502 RADV_BO_PRIORITY_SCRATCH);
3503 if (!gds_bo)
3504 goto fail;
3505 } else {
3506 gds_bo = queue->gds_bo;
3507 }
3508
3509 if (add_gds_oa) {
3510 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3511
3512 gds_oa_bo = queue->device->ws->buffer_create(queue->device->ws,
3513 4, 1,
3514 RADEON_DOMAIN_OA,
3515 ring_bo_flags,
3516 RADV_BO_PRIORITY_SCRATCH);
3517 if (!gds_oa_bo)
3518 goto fail;
3519 } else {
3520 gds_oa_bo = queue->gds_oa_bo;
3521 }
3522
3523 if (scratch_bo != queue->scratch_bo ||
3524 esgs_ring_bo != queue->esgs_ring_bo ||
3525 gsvs_ring_bo != queue->gsvs_ring_bo ||
3526 tess_rings_bo != queue->tess_rings_bo ||
3527 add_sample_positions) {
3528 uint32_t size = 0;
3529 if (gsvs_ring_bo || esgs_ring_bo ||
3530 tess_rings_bo || add_sample_positions) {
3531 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
3532 if (add_sample_positions)
3533 size += 128; /* 64+32+16+8 = 120 bytes */
3534 }
3535 else if (scratch_bo)
3536 size = 8; /* 2 dword */
3537
3538 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
3539 size,
3540 4096,
3541 RADEON_DOMAIN_VRAM,
3542 RADEON_FLAG_CPU_ACCESS |
3543 RADEON_FLAG_NO_INTERPROCESS_SHARING |
3544 RADEON_FLAG_READ_ONLY,
3545 RADV_BO_PRIORITY_DESCRIPTOR);
3546 if (!descriptor_bo)
3547 goto fail;
3548 } else
3549 descriptor_bo = queue->descriptor_bo;
3550
3551 if (descriptor_bo != queue->descriptor_bo) {
3552 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
3553 if (!map)
3554 goto fail;
3555
3556 if (scratch_bo) {
3557 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
3558 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3559 S_008F04_SWIZZLE_ENABLE(1);
3560 map[0] = scratch_va;
3561 map[1] = rsrc1;
3562 }
3563
3564 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
3565 fill_geom_tess_rings(queue, map, add_sample_positions,
3566 esgs_ring_size, esgs_ring_bo,
3567 gsvs_ring_size, gsvs_ring_bo,
3568 tess_factor_ring_size,
3569 tess_offchip_ring_offset,
3570 tess_offchip_ring_size,
3571 tess_rings_bo);
3572
3573 queue->device->ws->buffer_unmap(descriptor_bo);
3574 }
3575
3576 for(int i = 0; i < 3; ++i) {
3577 struct radeon_cmdbuf *cs = NULL;
3578 cs = queue->device->ws->cs_create(queue->device->ws,
3579 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
3580 if (!cs)
3581 goto fail;
3582
3583 dest_cs[i] = cs;
3584
3585 if (scratch_bo)
3586 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3587
3588 /* Emit initial configuration. */
3589 switch (queue->queue_family_index) {
3590 case RADV_QUEUE_GENERAL:
3591 radv_init_graphics_state(cs, queue);
3592 break;
3593 case RADV_QUEUE_COMPUTE:
3594 radv_init_compute_state(cs, queue);
3595 break;
3596 case RADV_QUEUE_TRANSFER:
3597 break;
3598 }
3599
3600 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
3601 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3602 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3603
3604 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3605 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3606 }
3607
3608 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
3609 gsvs_ring_bo, gsvs_ring_size);
3610 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
3611 tess_factor_ring_size, tess_rings_bo);
3612 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
3613 radv_emit_compute_scratch(queue, cs, compute_scratch_size_per_wave,
3614 compute_scratch_waves, compute_scratch_bo);
3615 radv_emit_graphics_scratch(queue, cs, scratch_size_per_wave,
3616 scratch_waves, scratch_bo);
3617
3618 if (gds_bo)
3619 radv_cs_add_buffer(queue->device->ws, cs, gds_bo);
3620 if (gds_oa_bo)
3621 radv_cs_add_buffer(queue->device->ws, cs, gds_oa_bo);
3622
3623 if (queue->device->trace_bo)
3624 radv_cs_add_buffer(queue->device->ws, cs, queue->device->trace_bo);
3625
3626 if (queue->device->border_color_data.bo)
3627 radv_cs_add_buffer(queue->device->ws, cs,
3628 queue->device->border_color_data.bo);
3629
3630 if (i == 0) {
3631 si_cs_emit_cache_flush(cs,
3632 queue->device->physical_device->rad_info.chip_class,
3633 NULL, 0,
3634 queue->queue_family_index == RING_COMPUTE &&
3635 queue->device->physical_device->rad_info.chip_class >= GFX7,
3636 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
3637 RADV_CMD_FLAG_INV_ICACHE |
3638 RADV_CMD_FLAG_INV_SCACHE |
3639 RADV_CMD_FLAG_INV_VCACHE |
3640 RADV_CMD_FLAG_INV_L2 |
3641 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3642 } else if (i == 1) {
3643 si_cs_emit_cache_flush(cs,
3644 queue->device->physical_device->rad_info.chip_class,
3645 NULL, 0,
3646 queue->queue_family_index == RING_COMPUTE &&
3647 queue->device->physical_device->rad_info.chip_class >= GFX7,
3648 RADV_CMD_FLAG_INV_ICACHE |
3649 RADV_CMD_FLAG_INV_SCACHE |
3650 RADV_CMD_FLAG_INV_VCACHE |
3651 RADV_CMD_FLAG_INV_L2 |
3652 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3653 }
3654
3655 if (queue->device->ws->cs_finalize(cs) != VK_SUCCESS)
3656 goto fail;
3657 }
3658
3659 if (queue->initial_full_flush_preamble_cs)
3660 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
3661
3662 if (queue->initial_preamble_cs)
3663 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
3664
3665 if (queue->continue_preamble_cs)
3666 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
3667
3668 queue->initial_full_flush_preamble_cs = dest_cs[0];
3669 queue->initial_preamble_cs = dest_cs[1];
3670 queue->continue_preamble_cs = dest_cs[2];
3671
3672 if (scratch_bo != queue->scratch_bo) {
3673 if (queue->scratch_bo)
3674 queue->device->ws->buffer_destroy(queue->scratch_bo);
3675 queue->scratch_bo = scratch_bo;
3676 }
3677 queue->scratch_size_per_wave = scratch_size_per_wave;
3678 queue->scratch_waves = scratch_waves;
3679
3680 if (compute_scratch_bo != queue->compute_scratch_bo) {
3681 if (queue->compute_scratch_bo)
3682 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
3683 queue->compute_scratch_bo = compute_scratch_bo;
3684 }
3685 queue->compute_scratch_size_per_wave = compute_scratch_size_per_wave;
3686 queue->compute_scratch_waves = compute_scratch_waves;
3687
3688 if (esgs_ring_bo != queue->esgs_ring_bo) {
3689 if (queue->esgs_ring_bo)
3690 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
3691 queue->esgs_ring_bo = esgs_ring_bo;
3692 queue->esgs_ring_size = esgs_ring_size;
3693 }
3694
3695 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
3696 if (queue->gsvs_ring_bo)
3697 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
3698 queue->gsvs_ring_bo = gsvs_ring_bo;
3699 queue->gsvs_ring_size = gsvs_ring_size;
3700 }
3701
3702 if (tess_rings_bo != queue->tess_rings_bo) {
3703 queue->tess_rings_bo = tess_rings_bo;
3704 queue->has_tess_rings = true;
3705 }
3706
3707 if (gds_bo != queue->gds_bo) {
3708 queue->gds_bo = gds_bo;
3709 queue->has_gds = true;
3710 }
3711
3712 if (gds_oa_bo != queue->gds_oa_bo) {
3713 queue->gds_oa_bo = gds_oa_bo;
3714 queue->has_gds_oa = true;
3715 }
3716
3717 if (descriptor_bo != queue->descriptor_bo) {
3718 if (queue->descriptor_bo)
3719 queue->device->ws->buffer_destroy(queue->descriptor_bo);
3720
3721 queue->descriptor_bo = descriptor_bo;
3722 }
3723
3724 if (add_sample_positions)
3725 queue->has_sample_positions = true;
3726
3727 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3728 *initial_preamble_cs = queue->initial_preamble_cs;
3729 *continue_preamble_cs = queue->continue_preamble_cs;
3730 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
3731 *continue_preamble_cs = NULL;
3732 return VK_SUCCESS;
3733 fail:
3734 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
3735 if (dest_cs[i])
3736 queue->device->ws->cs_destroy(dest_cs[i]);
3737 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
3738 queue->device->ws->buffer_destroy(descriptor_bo);
3739 if (scratch_bo && scratch_bo != queue->scratch_bo)
3740 queue->device->ws->buffer_destroy(scratch_bo);
3741 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
3742 queue->device->ws->buffer_destroy(compute_scratch_bo);
3743 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
3744 queue->device->ws->buffer_destroy(esgs_ring_bo);
3745 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
3746 queue->device->ws->buffer_destroy(gsvs_ring_bo);
3747 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
3748 queue->device->ws->buffer_destroy(tess_rings_bo);
3749 if (gds_bo && gds_bo != queue->gds_bo)
3750 queue->device->ws->buffer_destroy(gds_bo);
3751 if (gds_oa_bo && gds_oa_bo != queue->gds_oa_bo)
3752 queue->device->ws->buffer_destroy(gds_oa_bo);
3753
3754 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3755 }
3756
3757 static VkResult radv_alloc_sem_counts(struct radv_device *device,
3758 struct radv_winsys_sem_counts *counts,
3759 int num_sems,
3760 struct radv_semaphore_part **sems,
3761 const uint64_t *timeline_values,
3762 VkFence _fence,
3763 bool is_signal)
3764 {
3765 int syncobj_idx = 0, non_reset_idx = 0, sem_idx = 0;
3766
3767 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
3768 return VK_SUCCESS;
3769
3770 for (uint32_t i = 0; i < num_sems; i++) {
3771 switch(sems[i]->kind) {
3772 case RADV_SEMAPHORE_SYNCOBJ:
3773 counts->syncobj_count++;
3774 counts->syncobj_reset_count++;
3775 break;
3776 case RADV_SEMAPHORE_WINSYS:
3777 counts->sem_count++;
3778 break;
3779 case RADV_SEMAPHORE_NONE:
3780 break;
3781 case RADV_SEMAPHORE_TIMELINE:
3782 counts->syncobj_count++;
3783 break;
3784 }
3785 }
3786
3787 if (_fence != VK_NULL_HANDLE) {
3788 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3789
3790 struct radv_fence_part *part =
3791 fence->temporary.kind != RADV_FENCE_NONE ?
3792 &fence->temporary : &fence->permanent;
3793 if (part->kind == RADV_FENCE_SYNCOBJ)
3794 counts->syncobj_count++;
3795 }
3796
3797 if (counts->syncobj_count) {
3798 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
3799 if (!counts->syncobj)
3800 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3801 }
3802
3803 if (counts->sem_count) {
3804 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
3805 if (!counts->sem) {
3806 free(counts->syncobj);
3807 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3808 }
3809 }
3810
3811 non_reset_idx = counts->syncobj_reset_count;
3812
3813 for (uint32_t i = 0; i < num_sems; i++) {
3814 switch(sems[i]->kind) {
3815 case RADV_SEMAPHORE_NONE:
3816 unreachable("Empty semaphore");
3817 break;
3818 case RADV_SEMAPHORE_SYNCOBJ:
3819 counts->syncobj[syncobj_idx++] = sems[i]->syncobj;
3820 break;
3821 case RADV_SEMAPHORE_WINSYS:
3822 counts->sem[sem_idx++] = sems[i]->ws_sem;
3823 break;
3824 case RADV_SEMAPHORE_TIMELINE: {
3825 pthread_mutex_lock(&sems[i]->timeline.mutex);
3826 struct radv_timeline_point *point = NULL;
3827 if (is_signal) {
3828 point = radv_timeline_add_point_locked(device, &sems[i]->timeline, timeline_values[i]);
3829 } else {
3830 point = radv_timeline_find_point_at_least_locked(device, &sems[i]->timeline, timeline_values[i]);
3831 }
3832
3833 pthread_mutex_unlock(&sems[i]->timeline.mutex);
3834
3835 if (point) {
3836 counts->syncobj[non_reset_idx++] = point->syncobj;
3837 } else {
3838 /* Explicitly remove the semaphore so we might not find
3839 * a point later post-submit. */
3840 sems[i] = NULL;
3841 }
3842 break;
3843 }
3844 }
3845 }
3846
3847 if (_fence != VK_NULL_HANDLE) {
3848 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3849
3850 struct radv_fence_part *part =
3851 fence->temporary.kind != RADV_FENCE_NONE ?
3852 &fence->temporary : &fence->permanent;
3853 if (part->kind == RADV_FENCE_SYNCOBJ)
3854 counts->syncobj[non_reset_idx++] = part->syncobj;
3855 }
3856
3857 assert(MAX2(syncobj_idx, non_reset_idx) <= counts->syncobj_count);
3858 counts->syncobj_count = MAX2(syncobj_idx, non_reset_idx);
3859
3860 return VK_SUCCESS;
3861 }
3862
3863 static void
3864 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
3865 {
3866 free(sem_info->wait.syncobj);
3867 free(sem_info->wait.sem);
3868 free(sem_info->signal.syncobj);
3869 free(sem_info->signal.sem);
3870 }
3871
3872
3873 static void radv_free_temp_syncobjs(struct radv_device *device,
3874 int num_sems,
3875 struct radv_semaphore_part *sems)
3876 {
3877 for (uint32_t i = 0; i < num_sems; i++) {
3878 radv_destroy_semaphore_part(device, sems + i);
3879 }
3880 }
3881
3882 static VkResult
3883 radv_alloc_sem_info(struct radv_device *device,
3884 struct radv_winsys_sem_info *sem_info,
3885 int num_wait_sems,
3886 struct radv_semaphore_part **wait_sems,
3887 const uint64_t *wait_values,
3888 int num_signal_sems,
3889 struct radv_semaphore_part **signal_sems,
3890 const uint64_t *signal_values,
3891 VkFence fence)
3892 {
3893 VkResult ret;
3894 memset(sem_info, 0, sizeof(*sem_info));
3895
3896 ret = radv_alloc_sem_counts(device, &sem_info->wait, num_wait_sems, wait_sems, wait_values, VK_NULL_HANDLE, false);
3897 if (ret)
3898 return ret;
3899 ret = radv_alloc_sem_counts(device, &sem_info->signal, num_signal_sems, signal_sems, signal_values, fence, true);
3900 if (ret)
3901 radv_free_sem_info(sem_info);
3902
3903 /* caller can override these */
3904 sem_info->cs_emit_wait = true;
3905 sem_info->cs_emit_signal = true;
3906 return ret;
3907 }
3908
3909 static void
3910 radv_finalize_timelines(struct radv_device *device,
3911 uint32_t num_wait_sems,
3912 struct radv_semaphore_part **wait_sems,
3913 const uint64_t *wait_values,
3914 uint32_t num_signal_sems,
3915 struct radv_semaphore_part **signal_sems,
3916 const uint64_t *signal_values,
3917 struct list_head *processing_list)
3918 {
3919 for (uint32_t i = 0; i < num_wait_sems; ++i) {
3920 if (wait_sems[i] && wait_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
3921 pthread_mutex_lock(&wait_sems[i]->timeline.mutex);
3922 struct radv_timeline_point *point =
3923 radv_timeline_find_point_at_least_locked(device, &wait_sems[i]->timeline, wait_values[i]);
3924 point->wait_count -= 2;
3925 pthread_mutex_unlock(&wait_sems[i]->timeline.mutex);
3926 }
3927 }
3928 for (uint32_t i = 0; i < num_signal_sems; ++i) {
3929 if (signal_sems[i] && signal_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
3930 pthread_mutex_lock(&signal_sems[i]->timeline.mutex);
3931 struct radv_timeline_point *point =
3932 radv_timeline_find_point_at_least_locked(device, &signal_sems[i]->timeline, signal_values[i]);
3933 signal_sems[i]->timeline.highest_submitted =
3934 MAX2(signal_sems[i]->timeline.highest_submitted, point->value);
3935 point->wait_count -= 2;
3936 radv_timeline_trigger_waiters_locked(&signal_sems[i]->timeline, processing_list);
3937 pthread_mutex_unlock(&signal_sems[i]->timeline.mutex);
3938 }
3939 }
3940 }
3941
3942 static VkResult
3943 radv_sparse_buffer_bind_memory(struct radv_device *device,
3944 const VkSparseBufferMemoryBindInfo *bind)
3945 {
3946 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3947 VkResult result;
3948
3949 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3950 struct radv_device_memory *mem = NULL;
3951
3952 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3953 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3954
3955 result = device->ws->buffer_virtual_bind(buffer->bo,
3956 bind->pBinds[i].resourceOffset,
3957 bind->pBinds[i].size,
3958 mem ? mem->bo : NULL,
3959 bind->pBinds[i].memoryOffset);
3960 if (result != VK_SUCCESS)
3961 return result;
3962 }
3963
3964 return VK_SUCCESS;
3965 }
3966
3967 static VkResult
3968 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3969 const VkSparseImageOpaqueMemoryBindInfo *bind)
3970 {
3971 RADV_FROM_HANDLE(radv_image, image, bind->image);
3972 VkResult result;
3973
3974 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3975 struct radv_device_memory *mem = NULL;
3976
3977 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3978 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3979
3980 result = device->ws->buffer_virtual_bind(image->bo,
3981 bind->pBinds[i].resourceOffset,
3982 bind->pBinds[i].size,
3983 mem ? mem->bo : NULL,
3984 bind->pBinds[i].memoryOffset);
3985 if (result != VK_SUCCESS)
3986 return result;
3987 }
3988
3989 return VK_SUCCESS;
3990 }
3991
3992 static VkResult
3993 radv_get_preambles(struct radv_queue *queue,
3994 const VkCommandBuffer *cmd_buffers,
3995 uint32_t cmd_buffer_count,
3996 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
3997 struct radeon_cmdbuf **initial_preamble_cs,
3998 struct radeon_cmdbuf **continue_preamble_cs)
3999 {
4000 uint32_t scratch_size_per_wave = 0, waves_wanted = 0;
4001 uint32_t compute_scratch_size_per_wave = 0, compute_waves_wanted = 0;
4002 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
4003 bool tess_rings_needed = false;
4004 bool gds_needed = false;
4005 bool gds_oa_needed = false;
4006 bool sample_positions_needed = false;
4007
4008 for (uint32_t j = 0; j < cmd_buffer_count; j++) {
4009 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
4010 cmd_buffers[j]);
4011
4012 scratch_size_per_wave = MAX2(scratch_size_per_wave, cmd_buffer->scratch_size_per_wave_needed);
4013 waves_wanted = MAX2(waves_wanted, cmd_buffer->scratch_waves_wanted);
4014 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave,
4015 cmd_buffer->compute_scratch_size_per_wave_needed);
4016 compute_waves_wanted = MAX2(compute_waves_wanted,
4017 cmd_buffer->compute_scratch_waves_wanted);
4018 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
4019 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
4020 tess_rings_needed |= cmd_buffer->tess_rings_needed;
4021 gds_needed |= cmd_buffer->gds_needed;
4022 gds_oa_needed |= cmd_buffer->gds_oa_needed;
4023 sample_positions_needed |= cmd_buffer->sample_positions_needed;
4024 }
4025
4026 return radv_get_preamble_cs(queue, scratch_size_per_wave, waves_wanted,
4027 compute_scratch_size_per_wave, compute_waves_wanted,
4028 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
4029 gds_needed, gds_oa_needed, sample_positions_needed,
4030 initial_full_flush_preamble_cs,
4031 initial_preamble_cs, continue_preamble_cs);
4032 }
4033
4034 struct radv_deferred_queue_submission {
4035 struct radv_queue *queue;
4036 VkCommandBuffer *cmd_buffers;
4037 uint32_t cmd_buffer_count;
4038
4039 /* Sparse bindings that happen on a queue. */
4040 VkSparseBufferMemoryBindInfo *buffer_binds;
4041 uint32_t buffer_bind_count;
4042 VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4043 uint32_t image_opaque_bind_count;
4044
4045 bool flush_caches;
4046 VkShaderStageFlags wait_dst_stage_mask;
4047 struct radv_semaphore_part **wait_semaphores;
4048 uint32_t wait_semaphore_count;
4049 struct radv_semaphore_part **signal_semaphores;
4050 uint32_t signal_semaphore_count;
4051 VkFence fence;
4052
4053 uint64_t *wait_values;
4054 uint64_t *signal_values;
4055
4056 struct radv_semaphore_part *temporary_semaphore_parts;
4057 uint32_t temporary_semaphore_part_count;
4058
4059 struct list_head queue_pending_list;
4060 uint32_t submission_wait_count;
4061 struct radv_timeline_waiter *wait_nodes;
4062
4063 struct list_head processing_list;
4064 };
4065
4066 struct radv_queue_submission {
4067 const VkCommandBuffer *cmd_buffers;
4068 uint32_t cmd_buffer_count;
4069
4070 /* Sparse bindings that happen on a queue. */
4071 const VkSparseBufferMemoryBindInfo *buffer_binds;
4072 uint32_t buffer_bind_count;
4073 const VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4074 uint32_t image_opaque_bind_count;
4075
4076 bool flush_caches;
4077 VkPipelineStageFlags wait_dst_stage_mask;
4078 const VkSemaphore *wait_semaphores;
4079 uint32_t wait_semaphore_count;
4080 const VkSemaphore *signal_semaphores;
4081 uint32_t signal_semaphore_count;
4082 VkFence fence;
4083
4084 const uint64_t *wait_values;
4085 uint32_t wait_value_count;
4086 const uint64_t *signal_values;
4087 uint32_t signal_value_count;
4088 };
4089
4090 static VkResult
4091 radv_create_deferred_submission(struct radv_queue *queue,
4092 const struct radv_queue_submission *submission,
4093 struct radv_deferred_queue_submission **out)
4094 {
4095 struct radv_deferred_queue_submission *deferred = NULL;
4096 size_t size = sizeof(struct radv_deferred_queue_submission);
4097
4098 uint32_t temporary_count = 0;
4099 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4100 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4101 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE)
4102 ++temporary_count;
4103 }
4104
4105 size += submission->cmd_buffer_count * sizeof(VkCommandBuffer);
4106 size += submission->buffer_bind_count * sizeof(VkSparseBufferMemoryBindInfo);
4107 size += submission->image_opaque_bind_count * sizeof(VkSparseImageOpaqueMemoryBindInfo);
4108 size += submission->wait_semaphore_count * sizeof(struct radv_semaphore_part *);
4109 size += temporary_count * sizeof(struct radv_semaphore_part);
4110 size += submission->signal_semaphore_count * sizeof(struct radv_semaphore_part *);
4111 size += submission->wait_value_count * sizeof(uint64_t);
4112 size += submission->signal_value_count * sizeof(uint64_t);
4113 size += submission->wait_semaphore_count * sizeof(struct radv_timeline_waiter);
4114
4115 deferred = calloc(1, size);
4116 if (!deferred)
4117 return VK_ERROR_OUT_OF_HOST_MEMORY;
4118
4119 deferred->queue = queue;
4120
4121 deferred->cmd_buffers = (void*)(deferred + 1);
4122 deferred->cmd_buffer_count = submission->cmd_buffer_count;
4123 memcpy(deferred->cmd_buffers, submission->cmd_buffers,
4124 submission->cmd_buffer_count * sizeof(*deferred->cmd_buffers));
4125
4126 deferred->buffer_binds = (void*)(deferred->cmd_buffers + submission->cmd_buffer_count);
4127 deferred->buffer_bind_count = submission->buffer_bind_count;
4128 memcpy(deferred->buffer_binds, submission->buffer_binds,
4129 submission->buffer_bind_count * sizeof(*deferred->buffer_binds));
4130
4131 deferred->image_opaque_binds = (void*)(deferred->buffer_binds + submission->buffer_bind_count);
4132 deferred->image_opaque_bind_count = submission->image_opaque_bind_count;
4133 memcpy(deferred->image_opaque_binds, submission->image_opaque_binds,
4134 submission->image_opaque_bind_count * sizeof(*deferred->image_opaque_binds));
4135
4136 deferred->flush_caches = submission->flush_caches;
4137 deferred->wait_dst_stage_mask = submission->wait_dst_stage_mask;
4138
4139 deferred->wait_semaphores = (void*)(deferred->image_opaque_binds + deferred->image_opaque_bind_count);
4140 deferred->wait_semaphore_count = submission->wait_semaphore_count;
4141
4142 deferred->signal_semaphores = (void*)(deferred->wait_semaphores + deferred->wait_semaphore_count);
4143 deferred->signal_semaphore_count = submission->signal_semaphore_count;
4144
4145 deferred->fence = submission->fence;
4146
4147 deferred->temporary_semaphore_parts = (void*)(deferred->signal_semaphores + deferred->signal_semaphore_count);
4148 deferred->temporary_semaphore_part_count = temporary_count;
4149
4150 uint32_t temporary_idx = 0;
4151 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4152 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4153 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4154 deferred->wait_semaphores[i] = &deferred->temporary_semaphore_parts[temporary_idx];
4155 deferred->temporary_semaphore_parts[temporary_idx] = semaphore->temporary;
4156 semaphore->temporary.kind = RADV_SEMAPHORE_NONE;
4157 ++temporary_idx;
4158 } else
4159 deferred->wait_semaphores[i] = &semaphore->permanent;
4160 }
4161
4162 for (uint32_t i = 0; i < submission->signal_semaphore_count; ++i) {
4163 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->signal_semaphores[i]);
4164 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4165 deferred->signal_semaphores[i] = &semaphore->temporary;
4166 } else {
4167 deferred->signal_semaphores[i] = &semaphore->permanent;
4168 }
4169 }
4170
4171 deferred->wait_values = (void*)(deferred->temporary_semaphore_parts + temporary_count);
4172 memcpy(deferred->wait_values, submission->wait_values, submission->wait_value_count * sizeof(uint64_t));
4173 deferred->signal_values = deferred->wait_values + submission->wait_value_count;
4174 memcpy(deferred->signal_values, submission->signal_values, submission->signal_value_count * sizeof(uint64_t));
4175
4176 deferred->wait_nodes = (void*)(deferred->signal_values + submission->signal_value_count);
4177 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4178 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4179 deferred->submission_wait_count = 1 + submission->wait_semaphore_count;
4180
4181 *out = deferred;
4182 return VK_SUCCESS;
4183 }
4184
4185 static void
4186 radv_queue_enqueue_submission(struct radv_deferred_queue_submission *submission,
4187 struct list_head *processing_list)
4188 {
4189 uint32_t wait_cnt = 0;
4190 struct radv_timeline_waiter *waiter = submission->wait_nodes;
4191 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4192 if (submission->wait_semaphores[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4193 pthread_mutex_lock(&submission->wait_semaphores[i]->timeline.mutex);
4194 if (submission->wait_semaphores[i]->timeline.highest_submitted < submission->wait_values[i]) {
4195 ++wait_cnt;
4196 waiter->value = submission->wait_values[i];
4197 waiter->submission = submission;
4198 list_addtail(&waiter->list, &submission->wait_semaphores[i]->timeline.waiters);
4199 ++waiter;
4200 }
4201 pthread_mutex_unlock(&submission->wait_semaphores[i]->timeline.mutex);
4202 }
4203 }
4204
4205 pthread_mutex_lock(&submission->queue->pending_mutex);
4206
4207 bool is_first = list_is_empty(&submission->queue->pending_submissions);
4208 list_addtail(&submission->queue_pending_list, &submission->queue->pending_submissions);
4209
4210 pthread_mutex_unlock(&submission->queue->pending_mutex);
4211
4212 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4213 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4214 * submission. */
4215 uint32_t decrement = submission->wait_semaphore_count - wait_cnt + (is_first ? 1 : 0);
4216 if (__atomic_sub_fetch(&submission->submission_wait_count, decrement, __ATOMIC_ACQ_REL) == 0) {
4217 list_addtail(&submission->processing_list, processing_list);
4218 }
4219 }
4220
4221 static void
4222 radv_queue_submission_update_queue(struct radv_deferred_queue_submission *submission,
4223 struct list_head *processing_list)
4224 {
4225 pthread_mutex_lock(&submission->queue->pending_mutex);
4226 list_del(&submission->queue_pending_list);
4227
4228 /* trigger the next submission in the queue. */
4229 if (!list_is_empty(&submission->queue->pending_submissions)) {
4230 struct radv_deferred_queue_submission *next_submission =
4231 list_first_entry(&submission->queue->pending_submissions,
4232 struct radv_deferred_queue_submission,
4233 queue_pending_list);
4234 if (p_atomic_dec_zero(&next_submission->submission_wait_count)) {
4235 list_addtail(&next_submission->processing_list, processing_list);
4236 }
4237 }
4238 pthread_mutex_unlock(&submission->queue->pending_mutex);
4239
4240 pthread_cond_broadcast(&submission->queue->device->timeline_cond);
4241 }
4242
4243 static VkResult
4244 radv_queue_submit_deferred(struct radv_deferred_queue_submission *submission,
4245 struct list_head *processing_list)
4246 {
4247 RADV_FROM_HANDLE(radv_fence, fence, submission->fence);
4248 struct radv_queue *queue = submission->queue;
4249 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4250 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
4251 struct radeon_winsys_fence *base_fence = NULL;
4252 bool do_flush = submission->flush_caches || submission->wait_dst_stage_mask;
4253 bool can_patch = true;
4254 uint32_t advance;
4255 struct radv_winsys_sem_info sem_info;
4256 VkResult result;
4257 struct radeon_cmdbuf *initial_preamble_cs = NULL;
4258 struct radeon_cmdbuf *initial_flush_preamble_cs = NULL;
4259 struct radeon_cmdbuf *continue_preamble_cs = NULL;
4260
4261 if (fence) {
4262 /* Under most circumstances, out fences won't be temporary.
4263 * However, the spec does allow it for opaque_fd.
4264 *
4265 * From the Vulkan 1.0.53 spec:
4266 *
4267 * "If the import is temporary, the implementation must
4268 * restore the semaphore to its prior permanent state after
4269 * submitting the next semaphore wait operation."
4270 */
4271 struct radv_fence_part *part =
4272 fence->temporary.kind != RADV_FENCE_NONE ?
4273 &fence->temporary : &fence->permanent;
4274 if (part->kind == RADV_FENCE_WINSYS)
4275 base_fence = part->fence;
4276 }
4277
4278 result = radv_get_preambles(queue, submission->cmd_buffers,
4279 submission->cmd_buffer_count,
4280 &initial_preamble_cs,
4281 &initial_flush_preamble_cs,
4282 &continue_preamble_cs);
4283 if (result != VK_SUCCESS)
4284 goto fail;
4285
4286 result = radv_alloc_sem_info(queue->device,
4287 &sem_info,
4288 submission->wait_semaphore_count,
4289 submission->wait_semaphores,
4290 submission->wait_values,
4291 submission->signal_semaphore_count,
4292 submission->signal_semaphores,
4293 submission->signal_values,
4294 submission->fence);
4295 if (result != VK_SUCCESS)
4296 goto fail;
4297
4298 for (uint32_t i = 0; i < submission->buffer_bind_count; ++i) {
4299 result = radv_sparse_buffer_bind_memory(queue->device,
4300 submission->buffer_binds + i);
4301 if (result != VK_SUCCESS)
4302 goto fail;
4303 }
4304
4305 for (uint32_t i = 0; i < submission->image_opaque_bind_count; ++i) {
4306 result = radv_sparse_image_opaque_bind_memory(queue->device,
4307 submission->image_opaque_binds + i);
4308 if (result != VK_SUCCESS)
4309 goto fail;
4310 }
4311
4312 if (!submission->cmd_buffer_count) {
4313 result = queue->device->ws->cs_submit(ctx, queue->queue_idx,
4314 &queue->device->empty_cs[queue->queue_family_index],
4315 1, NULL, NULL,
4316 &sem_info, NULL,
4317 false, base_fence);
4318 if (result != VK_SUCCESS)
4319 goto fail;
4320 } else {
4321 struct radeon_cmdbuf **cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
4322 (submission->cmd_buffer_count));
4323
4324 for (uint32_t j = 0; j < submission->cmd_buffer_count; j++) {
4325 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, submission->cmd_buffers[j]);
4326 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
4327
4328 cs_array[j] = cmd_buffer->cs;
4329 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
4330 can_patch = false;
4331
4332 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
4333 }
4334
4335 for (uint32_t j = 0; j < submission->cmd_buffer_count; j += advance) {
4336 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
4337 const struct radv_winsys_bo_list *bo_list = NULL;
4338
4339 advance = MIN2(max_cs_submission,
4340 submission->cmd_buffer_count - j);
4341
4342 if (queue->device->trace_bo)
4343 *queue->device->trace_id_ptr = 0;
4344
4345 sem_info.cs_emit_wait = j == 0;
4346 sem_info.cs_emit_signal = j + advance == submission->cmd_buffer_count;
4347
4348 if (unlikely(queue->device->use_global_bo_list)) {
4349 pthread_mutex_lock(&queue->device->bo_list.mutex);
4350 bo_list = &queue->device->bo_list.list;
4351 }
4352
4353 result = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
4354 advance, initial_preamble, continue_preamble_cs,
4355 &sem_info, bo_list,
4356 can_patch, base_fence);
4357
4358 if (unlikely(queue->device->use_global_bo_list))
4359 pthread_mutex_unlock(&queue->device->bo_list.mutex);
4360
4361 if (result != VK_SUCCESS)
4362 goto fail;
4363
4364 if (queue->device->trace_bo) {
4365 radv_check_gpu_hangs(queue, cs_array[j]);
4366 }
4367 }
4368
4369 free(cs_array);
4370 }
4371
4372 radv_free_temp_syncobjs(queue->device,
4373 submission->temporary_semaphore_part_count,
4374 submission->temporary_semaphore_parts);
4375 radv_finalize_timelines(queue->device,
4376 submission->wait_semaphore_count,
4377 submission->wait_semaphores,
4378 submission->wait_values,
4379 submission->signal_semaphore_count,
4380 submission->signal_semaphores,
4381 submission->signal_values,
4382 processing_list);
4383 /* Has to happen after timeline finalization to make sure the
4384 * condition variable is only triggered when timelines and queue have
4385 * been updated. */
4386 radv_queue_submission_update_queue(submission, processing_list);
4387 radv_free_sem_info(&sem_info);
4388 free(submission);
4389 return VK_SUCCESS;
4390
4391 fail:
4392 if (result != VK_SUCCESS && result != VK_ERROR_DEVICE_LOST) {
4393 /* When something bad happened during the submission, such as
4394 * an out of memory issue, it might be hard to recover from
4395 * this inconsistent state. To avoid this sort of problem, we
4396 * assume that we are in a really bad situation and return
4397 * VK_ERROR_DEVICE_LOST to ensure the clients do not attempt
4398 * to submit the same job again to this device.
4399 */
4400 result = VK_ERROR_DEVICE_LOST;
4401 }
4402
4403 radv_free_temp_syncobjs(queue->device,
4404 submission->temporary_semaphore_part_count,
4405 submission->temporary_semaphore_parts);
4406 free(submission);
4407 return result;
4408 }
4409
4410 static VkResult
4411 radv_process_submissions(struct list_head *processing_list)
4412 {
4413 while(!list_is_empty(processing_list)) {
4414 struct radv_deferred_queue_submission *submission =
4415 list_first_entry(processing_list, struct radv_deferred_queue_submission, processing_list);
4416 list_del(&submission->processing_list);
4417
4418 VkResult result = radv_queue_submit_deferred(submission, processing_list);
4419 if (result != VK_SUCCESS)
4420 return result;
4421 }
4422 return VK_SUCCESS;
4423 }
4424
4425 static VkResult radv_queue_submit(struct radv_queue *queue,
4426 const struct radv_queue_submission *submission)
4427 {
4428 struct radv_deferred_queue_submission *deferred = NULL;
4429
4430 VkResult result = radv_create_deferred_submission(queue, submission, &deferred);
4431 if (result != VK_SUCCESS)
4432 return result;
4433
4434 struct list_head processing_list;
4435 list_inithead(&processing_list);
4436
4437 radv_queue_enqueue_submission(deferred, &processing_list);
4438 return radv_process_submissions(&processing_list);
4439 }
4440
4441 bool
4442 radv_queue_internal_submit(struct radv_queue *queue, struct radeon_cmdbuf *cs)
4443 {
4444 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4445 struct radv_winsys_sem_info sem_info;
4446 VkResult result;
4447
4448 result = radv_alloc_sem_info(queue->device, &sem_info, 0, NULL, 0, 0,
4449 0, NULL, VK_NULL_HANDLE);
4450 if (result != VK_SUCCESS)
4451 return false;
4452
4453 result = queue->device->ws->cs_submit(ctx, queue->queue_idx, &cs, 1,
4454 NULL, NULL, &sem_info, NULL,
4455 false, NULL);
4456 radv_free_sem_info(&sem_info);
4457 if (result != VK_SUCCESS)
4458 return false;
4459
4460 return true;
4461
4462 }
4463
4464 /* Signals fence as soon as all the work currently put on queue is done. */
4465 static VkResult radv_signal_fence(struct radv_queue *queue,
4466 VkFence fence)
4467 {
4468 return radv_queue_submit(queue, &(struct radv_queue_submission) {
4469 .fence = fence
4470 });
4471 }
4472
4473 static bool radv_submit_has_effects(const VkSubmitInfo *info)
4474 {
4475 return info->commandBufferCount ||
4476 info->waitSemaphoreCount ||
4477 info->signalSemaphoreCount;
4478 }
4479
4480 VkResult radv_QueueSubmit(
4481 VkQueue _queue,
4482 uint32_t submitCount,
4483 const VkSubmitInfo* pSubmits,
4484 VkFence fence)
4485 {
4486 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4487 VkResult result;
4488 uint32_t fence_idx = 0;
4489 bool flushed_caches = false;
4490
4491 if (fence != VK_NULL_HANDLE) {
4492 for (uint32_t i = 0; i < submitCount; ++i)
4493 if (radv_submit_has_effects(pSubmits + i))
4494 fence_idx = i;
4495 } else
4496 fence_idx = UINT32_MAX;
4497
4498 for (uint32_t i = 0; i < submitCount; i++) {
4499 if (!radv_submit_has_effects(pSubmits + i) && fence_idx != i)
4500 continue;
4501
4502 VkPipelineStageFlags wait_dst_stage_mask = 0;
4503 for (unsigned j = 0; j < pSubmits[i].waitSemaphoreCount; ++j) {
4504 wait_dst_stage_mask |= pSubmits[i].pWaitDstStageMask[j];
4505 }
4506
4507 const VkTimelineSemaphoreSubmitInfo *timeline_info =
4508 vk_find_struct_const(pSubmits[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
4509
4510 result = radv_queue_submit(queue, &(struct radv_queue_submission) {
4511 .cmd_buffers = pSubmits[i].pCommandBuffers,
4512 .cmd_buffer_count = pSubmits[i].commandBufferCount,
4513 .wait_dst_stage_mask = wait_dst_stage_mask,
4514 .flush_caches = !flushed_caches,
4515 .wait_semaphores = pSubmits[i].pWaitSemaphores,
4516 .wait_semaphore_count = pSubmits[i].waitSemaphoreCount,
4517 .signal_semaphores = pSubmits[i].pSignalSemaphores,
4518 .signal_semaphore_count = pSubmits[i].signalSemaphoreCount,
4519 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
4520 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
4521 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
4522 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
4523 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
4524 });
4525 if (result != VK_SUCCESS)
4526 return result;
4527
4528 flushed_caches = true;
4529 }
4530
4531 if (fence != VK_NULL_HANDLE && !submitCount) {
4532 result = radv_signal_fence(queue, fence);
4533 if (result != VK_SUCCESS)
4534 return result;
4535 }
4536
4537 return VK_SUCCESS;
4538 }
4539
4540 VkResult radv_QueueWaitIdle(
4541 VkQueue _queue)
4542 {
4543 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4544
4545 pthread_mutex_lock(&queue->pending_mutex);
4546 while (!list_is_empty(&queue->pending_submissions)) {
4547 pthread_cond_wait(&queue->device->timeline_cond, &queue->pending_mutex);
4548 }
4549 pthread_mutex_unlock(&queue->pending_mutex);
4550
4551 if (!queue->device->ws->ctx_wait_idle(queue->hw_ctx,
4552 radv_queue_family_to_ring(queue->queue_family_index),
4553 queue->queue_idx))
4554 return VK_ERROR_DEVICE_LOST;
4555
4556 return VK_SUCCESS;
4557 }
4558
4559 VkResult radv_DeviceWaitIdle(
4560 VkDevice _device)
4561 {
4562 RADV_FROM_HANDLE(radv_device, device, _device);
4563
4564 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
4565 for (unsigned q = 0; q < device->queue_count[i]; q++) {
4566 VkResult result =
4567 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
4568
4569 if (result != VK_SUCCESS)
4570 return result;
4571 }
4572 }
4573 return VK_SUCCESS;
4574 }
4575
4576 VkResult radv_EnumerateInstanceExtensionProperties(
4577 const char* pLayerName,
4578 uint32_t* pPropertyCount,
4579 VkExtensionProperties* pProperties)
4580 {
4581 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4582
4583 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
4584 if (radv_instance_extensions_supported.extensions[i]) {
4585 vk_outarray_append(&out, prop) {
4586 *prop = radv_instance_extensions[i];
4587 }
4588 }
4589 }
4590
4591 return vk_outarray_status(&out);
4592 }
4593
4594 VkResult radv_EnumerateDeviceExtensionProperties(
4595 VkPhysicalDevice physicalDevice,
4596 const char* pLayerName,
4597 uint32_t* pPropertyCount,
4598 VkExtensionProperties* pProperties)
4599 {
4600 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
4601 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4602
4603 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
4604 if (device->supported_extensions.extensions[i]) {
4605 vk_outarray_append(&out, prop) {
4606 *prop = radv_device_extensions[i];
4607 }
4608 }
4609 }
4610
4611 return vk_outarray_status(&out);
4612 }
4613
4614 PFN_vkVoidFunction radv_GetInstanceProcAddr(
4615 VkInstance _instance,
4616 const char* pName)
4617 {
4618 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4619
4620 /* The Vulkan 1.0 spec for vkGetInstanceProcAddr has a table of exactly
4621 * when we have to return valid function pointers, NULL, or it's left
4622 * undefined. See the table for exact details.
4623 */
4624 if (pName == NULL)
4625 return NULL;
4626
4627 #define LOOKUP_RADV_ENTRYPOINT(entrypoint) \
4628 if (strcmp(pName, "vk" #entrypoint) == 0) \
4629 return (PFN_vkVoidFunction)radv_##entrypoint
4630
4631 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceExtensionProperties);
4632 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceLayerProperties);
4633 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceVersion);
4634 LOOKUP_RADV_ENTRYPOINT(CreateInstance);
4635
4636 /* GetInstanceProcAddr() can also be called with a NULL instance.
4637 * See https://gitlab.khronos.org/vulkan/vulkan/issues/2057
4638 */
4639 LOOKUP_RADV_ENTRYPOINT(GetInstanceProcAddr);
4640
4641 #undef LOOKUP_RADV_ENTRYPOINT
4642
4643 if (instance == NULL)
4644 return NULL;
4645
4646 int idx = radv_get_instance_entrypoint_index(pName);
4647 if (idx >= 0)
4648 return instance->dispatch.entrypoints[idx];
4649
4650 idx = radv_get_physical_device_entrypoint_index(pName);
4651 if (idx >= 0)
4652 return instance->physical_device_dispatch.entrypoints[idx];
4653
4654 idx = radv_get_device_entrypoint_index(pName);
4655 if (idx >= 0)
4656 return instance->device_dispatch.entrypoints[idx];
4657
4658 return NULL;
4659 }
4660
4661 /* The loader wants us to expose a second GetInstanceProcAddr function
4662 * to work around certain LD_PRELOAD issues seen in apps.
4663 */
4664 PUBLIC
4665 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4666 VkInstance instance,
4667 const char* pName);
4668
4669 PUBLIC
4670 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4671 VkInstance instance,
4672 const char* pName)
4673 {
4674 return radv_GetInstanceProcAddr(instance, pName);
4675 }
4676
4677 PUBLIC
4678 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
4679 VkInstance _instance,
4680 const char* pName);
4681
4682 PUBLIC
4683 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
4684 VkInstance _instance,
4685 const char* pName)
4686 {
4687 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4688
4689 if (!pName || !instance)
4690 return NULL;
4691
4692 int idx = radv_get_physical_device_entrypoint_index(pName);
4693 if (idx < 0)
4694 return NULL;
4695
4696 return instance->physical_device_dispatch.entrypoints[idx];
4697 }
4698
4699 PFN_vkVoidFunction radv_GetDeviceProcAddr(
4700 VkDevice _device,
4701 const char* pName)
4702 {
4703 RADV_FROM_HANDLE(radv_device, device, _device);
4704
4705 if (!device || !pName)
4706 return NULL;
4707
4708 int idx = radv_get_device_entrypoint_index(pName);
4709 if (idx < 0)
4710 return NULL;
4711
4712 return device->dispatch.entrypoints[idx];
4713 }
4714
4715 bool radv_get_memory_fd(struct radv_device *device,
4716 struct radv_device_memory *memory,
4717 int *pFD)
4718 {
4719 struct radeon_bo_metadata metadata;
4720
4721 if (memory->image) {
4722 if (memory->image->tiling != VK_IMAGE_TILING_LINEAR)
4723 radv_init_metadata(device, memory->image, &metadata);
4724 device->ws->buffer_set_metadata(memory->bo, &metadata);
4725 }
4726
4727 return device->ws->buffer_get_fd(device->ws, memory->bo,
4728 pFD);
4729 }
4730
4731
4732 void
4733 radv_free_memory(struct radv_device *device,
4734 const VkAllocationCallbacks* pAllocator,
4735 struct radv_device_memory *mem)
4736 {
4737 if (mem == NULL)
4738 return;
4739
4740 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4741 if (mem->android_hardware_buffer)
4742 AHardwareBuffer_release(mem->android_hardware_buffer);
4743 #endif
4744
4745 if (mem->bo) {
4746 if (device->overallocation_disallowed) {
4747 mtx_lock(&device->overallocation_mutex);
4748 device->allocated_memory_size[mem->heap_index] -= mem->alloc_size;
4749 mtx_unlock(&device->overallocation_mutex);
4750 }
4751
4752 radv_bo_list_remove(device, mem->bo);
4753 device->ws->buffer_destroy(mem->bo);
4754 mem->bo = NULL;
4755 }
4756
4757 vk_object_base_finish(&mem->base);
4758 vk_free2(&device->vk.alloc, pAllocator, mem);
4759 }
4760
4761 static VkResult radv_alloc_memory(struct radv_device *device,
4762 const VkMemoryAllocateInfo* pAllocateInfo,
4763 const VkAllocationCallbacks* pAllocator,
4764 VkDeviceMemory* pMem)
4765 {
4766 struct radv_device_memory *mem;
4767 VkResult result;
4768 enum radeon_bo_domain domain;
4769 uint32_t flags = 0;
4770
4771 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
4772
4773 const VkImportMemoryFdInfoKHR *import_info =
4774 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
4775 const VkMemoryDedicatedAllocateInfo *dedicate_info =
4776 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
4777 const VkExportMemoryAllocateInfo *export_info =
4778 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
4779 const struct VkImportAndroidHardwareBufferInfoANDROID *ahb_import_info =
4780 vk_find_struct_const(pAllocateInfo->pNext,
4781 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID);
4782 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
4783 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
4784
4785 const struct wsi_memory_allocate_info *wsi_info =
4786 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
4787
4788 if (pAllocateInfo->allocationSize == 0 && !ahb_import_info &&
4789 !(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID))) {
4790 /* Apparently, this is allowed */
4791 *pMem = VK_NULL_HANDLE;
4792 return VK_SUCCESS;
4793 }
4794
4795 mem = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*mem), 8,
4796 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4797 if (mem == NULL)
4798 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4799
4800 vk_object_base_init(&device->vk, &mem->base,
4801 VK_OBJECT_TYPE_DEVICE_MEMORY);
4802
4803 if (wsi_info && wsi_info->implicit_sync)
4804 flags |= RADEON_FLAG_IMPLICIT_SYNC;
4805
4806 if (dedicate_info) {
4807 mem->image = radv_image_from_handle(dedicate_info->image);
4808 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
4809 } else {
4810 mem->image = NULL;
4811 mem->buffer = NULL;
4812 }
4813
4814 float priority_float = 0.5;
4815 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
4816 vk_find_struct_const(pAllocateInfo->pNext,
4817 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
4818 if (priority_ext)
4819 priority_float = priority_ext->priority;
4820
4821 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
4822 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
4823
4824 mem->user_ptr = NULL;
4825 mem->bo = NULL;
4826
4827 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4828 mem->android_hardware_buffer = NULL;
4829 #endif
4830
4831 if (ahb_import_info) {
4832 result = radv_import_ahb_memory(device, mem, priority, ahb_import_info);
4833 if (result != VK_SUCCESS)
4834 goto fail;
4835 } else if(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID)) {
4836 result = radv_create_ahb_memory(device, mem, priority, pAllocateInfo);
4837 if (result != VK_SUCCESS)
4838 goto fail;
4839 } else if (import_info) {
4840 assert(import_info->handleType ==
4841 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4842 import_info->handleType ==
4843 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4844 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
4845 priority, NULL);
4846 if (!mem->bo) {
4847 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
4848 goto fail;
4849 } else {
4850 close(import_info->fd);
4851 }
4852 } else if (host_ptr_info) {
4853 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
4854 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
4855 pAllocateInfo->allocationSize,
4856 priority);
4857 if (!mem->bo) {
4858 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
4859 goto fail;
4860 } else {
4861 mem->user_ptr = host_ptr_info->pHostPointer;
4862 }
4863 } else {
4864 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
4865 uint32_t heap_index;
4866
4867 heap_index = device->physical_device->memory_properties.memoryTypes[pAllocateInfo->memoryTypeIndex].heapIndex;
4868 domain = device->physical_device->memory_domains[pAllocateInfo->memoryTypeIndex];
4869 flags |= device->physical_device->memory_flags[pAllocateInfo->memoryTypeIndex];
4870
4871 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
4872 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
4873 if (device->use_global_bo_list) {
4874 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
4875 }
4876 }
4877
4878 if (device->overallocation_disallowed) {
4879 uint64_t total_size =
4880 device->physical_device->memory_properties.memoryHeaps[heap_index].size;
4881
4882 mtx_lock(&device->overallocation_mutex);
4883 if (device->allocated_memory_size[heap_index] + alloc_size > total_size) {
4884 mtx_unlock(&device->overallocation_mutex);
4885 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
4886 goto fail;
4887 }
4888 device->allocated_memory_size[heap_index] += alloc_size;
4889 mtx_unlock(&device->overallocation_mutex);
4890 }
4891
4892 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
4893 domain, flags, priority);
4894
4895 if (!mem->bo) {
4896 if (device->overallocation_disallowed) {
4897 mtx_lock(&device->overallocation_mutex);
4898 device->allocated_memory_size[heap_index] -= alloc_size;
4899 mtx_unlock(&device->overallocation_mutex);
4900 }
4901 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
4902 goto fail;
4903 }
4904
4905 mem->heap_index = heap_index;
4906 mem->alloc_size = alloc_size;
4907 }
4908
4909 if (!wsi_info) {
4910 result = radv_bo_list_add(device, mem->bo);
4911 if (result != VK_SUCCESS)
4912 goto fail;
4913 }
4914
4915 *pMem = radv_device_memory_to_handle(mem);
4916
4917 return VK_SUCCESS;
4918
4919 fail:
4920 radv_free_memory(device, pAllocator,mem);
4921
4922 return result;
4923 }
4924
4925 VkResult radv_AllocateMemory(
4926 VkDevice _device,
4927 const VkMemoryAllocateInfo* pAllocateInfo,
4928 const VkAllocationCallbacks* pAllocator,
4929 VkDeviceMemory* pMem)
4930 {
4931 RADV_FROM_HANDLE(radv_device, device, _device);
4932 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
4933 }
4934
4935 void radv_FreeMemory(
4936 VkDevice _device,
4937 VkDeviceMemory _mem,
4938 const VkAllocationCallbacks* pAllocator)
4939 {
4940 RADV_FROM_HANDLE(radv_device, device, _device);
4941 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
4942
4943 radv_free_memory(device, pAllocator, mem);
4944 }
4945
4946 VkResult radv_MapMemory(
4947 VkDevice _device,
4948 VkDeviceMemory _memory,
4949 VkDeviceSize offset,
4950 VkDeviceSize size,
4951 VkMemoryMapFlags flags,
4952 void** ppData)
4953 {
4954 RADV_FROM_HANDLE(radv_device, device, _device);
4955 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
4956
4957 if (mem == NULL) {
4958 *ppData = NULL;
4959 return VK_SUCCESS;
4960 }
4961
4962 if (mem->user_ptr)
4963 *ppData = mem->user_ptr;
4964 else
4965 *ppData = device->ws->buffer_map(mem->bo);
4966
4967 if (*ppData) {
4968 *ppData += offset;
4969 return VK_SUCCESS;
4970 }
4971
4972 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
4973 }
4974
4975 void radv_UnmapMemory(
4976 VkDevice _device,
4977 VkDeviceMemory _memory)
4978 {
4979 RADV_FROM_HANDLE(radv_device, device, _device);
4980 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
4981
4982 if (mem == NULL)
4983 return;
4984
4985 if (mem->user_ptr == NULL)
4986 device->ws->buffer_unmap(mem->bo);
4987 }
4988
4989 VkResult radv_FlushMappedMemoryRanges(
4990 VkDevice _device,
4991 uint32_t memoryRangeCount,
4992 const VkMappedMemoryRange* pMemoryRanges)
4993 {
4994 return VK_SUCCESS;
4995 }
4996
4997 VkResult radv_InvalidateMappedMemoryRanges(
4998 VkDevice _device,
4999 uint32_t memoryRangeCount,
5000 const VkMappedMemoryRange* pMemoryRanges)
5001 {
5002 return VK_SUCCESS;
5003 }
5004
5005 void radv_GetBufferMemoryRequirements(
5006 VkDevice _device,
5007 VkBuffer _buffer,
5008 VkMemoryRequirements* pMemoryRequirements)
5009 {
5010 RADV_FROM_HANDLE(radv_device, device, _device);
5011 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5012
5013 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
5014
5015 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
5016 pMemoryRequirements->alignment = 4096;
5017 else
5018 pMemoryRequirements->alignment = 16;
5019
5020 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
5021 }
5022
5023 void radv_GetBufferMemoryRequirements2(
5024 VkDevice device,
5025 const VkBufferMemoryRequirementsInfo2 *pInfo,
5026 VkMemoryRequirements2 *pMemoryRequirements)
5027 {
5028 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
5029 &pMemoryRequirements->memoryRequirements);
5030 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5031 switch (ext->sType) {
5032 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5033 VkMemoryDedicatedRequirements *req =
5034 (VkMemoryDedicatedRequirements *) ext;
5035 req->requiresDedicatedAllocation = false;
5036 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5037 break;
5038 }
5039 default:
5040 break;
5041 }
5042 }
5043 }
5044
5045 void radv_GetImageMemoryRequirements(
5046 VkDevice _device,
5047 VkImage _image,
5048 VkMemoryRequirements* pMemoryRequirements)
5049 {
5050 RADV_FROM_HANDLE(radv_device, device, _device);
5051 RADV_FROM_HANDLE(radv_image, image, _image);
5052
5053 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
5054
5055 pMemoryRequirements->size = image->size;
5056 pMemoryRequirements->alignment = image->alignment;
5057 }
5058
5059 void radv_GetImageMemoryRequirements2(
5060 VkDevice device,
5061 const VkImageMemoryRequirementsInfo2 *pInfo,
5062 VkMemoryRequirements2 *pMemoryRequirements)
5063 {
5064 radv_GetImageMemoryRequirements(device, pInfo->image,
5065 &pMemoryRequirements->memoryRequirements);
5066
5067 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
5068
5069 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5070 switch (ext->sType) {
5071 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5072 VkMemoryDedicatedRequirements *req =
5073 (VkMemoryDedicatedRequirements *) ext;
5074 req->requiresDedicatedAllocation = image->shareable &&
5075 image->tiling != VK_IMAGE_TILING_LINEAR;
5076 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5077 break;
5078 }
5079 default:
5080 break;
5081 }
5082 }
5083 }
5084
5085 void radv_GetImageSparseMemoryRequirements(
5086 VkDevice device,
5087 VkImage image,
5088 uint32_t* pSparseMemoryRequirementCount,
5089 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
5090 {
5091 stub();
5092 }
5093
5094 void radv_GetImageSparseMemoryRequirements2(
5095 VkDevice device,
5096 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
5097 uint32_t* pSparseMemoryRequirementCount,
5098 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
5099 {
5100 stub();
5101 }
5102
5103 void radv_GetDeviceMemoryCommitment(
5104 VkDevice device,
5105 VkDeviceMemory memory,
5106 VkDeviceSize* pCommittedMemoryInBytes)
5107 {
5108 *pCommittedMemoryInBytes = 0;
5109 }
5110
5111 VkResult radv_BindBufferMemory2(VkDevice device,
5112 uint32_t bindInfoCount,
5113 const VkBindBufferMemoryInfo *pBindInfos)
5114 {
5115 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5116 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5117 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
5118
5119 if (mem) {
5120 buffer->bo = mem->bo;
5121 buffer->offset = pBindInfos[i].memoryOffset;
5122 } else {
5123 buffer->bo = NULL;
5124 }
5125 }
5126 return VK_SUCCESS;
5127 }
5128
5129 VkResult radv_BindBufferMemory(
5130 VkDevice device,
5131 VkBuffer buffer,
5132 VkDeviceMemory memory,
5133 VkDeviceSize memoryOffset)
5134 {
5135 const VkBindBufferMemoryInfo info = {
5136 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5137 .buffer = buffer,
5138 .memory = memory,
5139 .memoryOffset = memoryOffset
5140 };
5141
5142 return radv_BindBufferMemory2(device, 1, &info);
5143 }
5144
5145 VkResult radv_BindImageMemory2(VkDevice device,
5146 uint32_t bindInfoCount,
5147 const VkBindImageMemoryInfo *pBindInfos)
5148 {
5149 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5150 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5151 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
5152
5153 if (mem) {
5154 image->bo = mem->bo;
5155 image->offset = pBindInfos[i].memoryOffset;
5156 } else {
5157 image->bo = NULL;
5158 image->offset = 0;
5159 }
5160 }
5161 return VK_SUCCESS;
5162 }
5163
5164
5165 VkResult radv_BindImageMemory(
5166 VkDevice device,
5167 VkImage image,
5168 VkDeviceMemory memory,
5169 VkDeviceSize memoryOffset)
5170 {
5171 const VkBindImageMemoryInfo info = {
5172 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5173 .image = image,
5174 .memory = memory,
5175 .memoryOffset = memoryOffset
5176 };
5177
5178 return radv_BindImageMemory2(device, 1, &info);
5179 }
5180
5181 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo *info)
5182 {
5183 return info->bufferBindCount ||
5184 info->imageOpaqueBindCount ||
5185 info->imageBindCount ||
5186 info->waitSemaphoreCount ||
5187 info->signalSemaphoreCount;
5188 }
5189
5190 VkResult radv_QueueBindSparse(
5191 VkQueue _queue,
5192 uint32_t bindInfoCount,
5193 const VkBindSparseInfo* pBindInfo,
5194 VkFence fence)
5195 {
5196 RADV_FROM_HANDLE(radv_queue, queue, _queue);
5197 VkResult result;
5198 uint32_t fence_idx = 0;
5199
5200 if (fence != VK_NULL_HANDLE) {
5201 for (uint32_t i = 0; i < bindInfoCount; ++i)
5202 if (radv_sparse_bind_has_effects(pBindInfo + i))
5203 fence_idx = i;
5204 } else
5205 fence_idx = UINT32_MAX;
5206
5207 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5208 if (i != fence_idx && !radv_sparse_bind_has_effects(pBindInfo + i))
5209 continue;
5210
5211 const VkTimelineSemaphoreSubmitInfo *timeline_info =
5212 vk_find_struct_const(pBindInfo[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
5213
5214 VkResult result = radv_queue_submit(queue, &(struct radv_queue_submission) {
5215 .buffer_binds = pBindInfo[i].pBufferBinds,
5216 .buffer_bind_count = pBindInfo[i].bufferBindCount,
5217 .image_opaque_binds = pBindInfo[i].pImageOpaqueBinds,
5218 .image_opaque_bind_count = pBindInfo[i].imageOpaqueBindCount,
5219 .wait_semaphores = pBindInfo[i].pWaitSemaphores,
5220 .wait_semaphore_count = pBindInfo[i].waitSemaphoreCount,
5221 .signal_semaphores = pBindInfo[i].pSignalSemaphores,
5222 .signal_semaphore_count = pBindInfo[i].signalSemaphoreCount,
5223 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
5224 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
5225 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
5226 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
5227 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
5228 });
5229
5230 if (result != VK_SUCCESS)
5231 return result;
5232 }
5233
5234 if (fence != VK_NULL_HANDLE && !bindInfoCount) {
5235 result = radv_signal_fence(queue, fence);
5236 if (result != VK_SUCCESS)
5237 return result;
5238 }
5239
5240 return VK_SUCCESS;
5241 }
5242
5243 static void
5244 radv_destroy_fence_part(struct radv_device *device,
5245 struct radv_fence_part *part)
5246 {
5247 switch (part->kind) {
5248 case RADV_FENCE_NONE:
5249 break;
5250 case RADV_FENCE_WINSYS:
5251 device->ws->destroy_fence(part->fence);
5252 break;
5253 case RADV_FENCE_SYNCOBJ:
5254 device->ws->destroy_syncobj(device->ws, part->syncobj);
5255 break;
5256 case RADV_FENCE_WSI:
5257 part->fence_wsi->destroy(part->fence_wsi);
5258 break;
5259 default:
5260 unreachable("Invalid fence type");
5261 }
5262
5263 part->kind = RADV_FENCE_NONE;
5264 }
5265
5266 static void
5267 radv_destroy_fence(struct radv_device *device,
5268 const VkAllocationCallbacks *pAllocator,
5269 struct radv_fence *fence)
5270 {
5271 radv_destroy_fence_part(device, &fence->temporary);
5272 radv_destroy_fence_part(device, &fence->permanent);
5273
5274 vk_object_base_finish(&fence->base);
5275 vk_free2(&device->vk.alloc, pAllocator, fence);
5276 }
5277
5278 VkResult radv_CreateFence(
5279 VkDevice _device,
5280 const VkFenceCreateInfo* pCreateInfo,
5281 const VkAllocationCallbacks* pAllocator,
5282 VkFence* pFence)
5283 {
5284 RADV_FROM_HANDLE(radv_device, device, _device);
5285 const VkExportFenceCreateInfo *export =
5286 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
5287 VkExternalFenceHandleTypeFlags handleTypes =
5288 export ? export->handleTypes : 0;
5289 struct radv_fence *fence;
5290
5291 fence = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*fence), 8,
5292 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5293 if (!fence)
5294 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5295
5296 vk_object_base_init(&device->vk, &fence->base, VK_OBJECT_TYPE_FENCE);
5297
5298 if (device->always_use_syncobj || handleTypes) {
5299 fence->permanent.kind = RADV_FENCE_SYNCOBJ;
5300
5301 bool create_signaled = false;
5302 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5303 create_signaled = true;
5304
5305 int ret = device->ws->create_syncobj(device->ws, create_signaled,
5306 &fence->permanent.syncobj);
5307 if (ret) {
5308 radv_destroy_fence(device, pAllocator, fence);
5309 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5310 }
5311 } else {
5312 fence->permanent.kind = RADV_FENCE_WINSYS;
5313
5314 fence->permanent.fence = device->ws->create_fence();
5315 if (!fence->permanent.fence) {
5316 vk_free2(&device->vk.alloc, pAllocator, fence);
5317 radv_destroy_fence(device, pAllocator, fence);
5318 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5319 }
5320 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5321 device->ws->signal_fence(fence->permanent.fence);
5322 }
5323
5324 *pFence = radv_fence_to_handle(fence);
5325
5326 return VK_SUCCESS;
5327 }
5328
5329
5330 void radv_DestroyFence(
5331 VkDevice _device,
5332 VkFence _fence,
5333 const VkAllocationCallbacks* pAllocator)
5334 {
5335 RADV_FROM_HANDLE(radv_device, device, _device);
5336 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5337
5338 if (!fence)
5339 return;
5340
5341 radv_destroy_fence(device, pAllocator, fence);
5342 }
5343
5344
5345 uint64_t radv_get_current_time(void)
5346 {
5347 struct timespec tv;
5348 clock_gettime(CLOCK_MONOTONIC, &tv);
5349 return tv.tv_nsec + tv.tv_sec*1000000000ull;
5350 }
5351
5352 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
5353 {
5354 uint64_t current_time = radv_get_current_time();
5355
5356 timeout = MIN2(UINT64_MAX - current_time, timeout);
5357
5358 return current_time + timeout;
5359 }
5360
5361
5362 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
5363 uint32_t fenceCount, const VkFence *pFences)
5364 {
5365 for (uint32_t i = 0; i < fenceCount; ++i) {
5366 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5367
5368 struct radv_fence_part *part =
5369 fence->temporary.kind != RADV_FENCE_NONE ?
5370 &fence->temporary : &fence->permanent;
5371 if (part->kind != RADV_FENCE_WINSYS ||
5372 !device->ws->is_fence_waitable(part->fence))
5373 return false;
5374 }
5375 return true;
5376 }
5377
5378 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
5379 {
5380 for (uint32_t i = 0; i < fenceCount; ++i) {
5381 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5382
5383 struct radv_fence_part *part =
5384 fence->temporary.kind != RADV_FENCE_NONE ?
5385 &fence->temporary : &fence->permanent;
5386 if (part->kind != RADV_FENCE_SYNCOBJ)
5387 return false;
5388 }
5389 return true;
5390 }
5391
5392 VkResult radv_WaitForFences(
5393 VkDevice _device,
5394 uint32_t fenceCount,
5395 const VkFence* pFences,
5396 VkBool32 waitAll,
5397 uint64_t timeout)
5398 {
5399 RADV_FROM_HANDLE(radv_device, device, _device);
5400 timeout = radv_get_absolute_timeout(timeout);
5401
5402 if (device->always_use_syncobj &&
5403 radv_all_fences_syncobj(fenceCount, pFences))
5404 {
5405 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
5406 if (!handles)
5407 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5408
5409 for (uint32_t i = 0; i < fenceCount; ++i) {
5410 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5411
5412 struct radv_fence_part *part =
5413 fence->temporary.kind != RADV_FENCE_NONE ?
5414 &fence->temporary : &fence->permanent;
5415
5416 assert(part->kind == RADV_FENCE_SYNCOBJ);
5417 handles[i] = part->syncobj;
5418 }
5419
5420 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
5421
5422 free(handles);
5423 return success ? VK_SUCCESS : VK_TIMEOUT;
5424 }
5425
5426 if (!waitAll && fenceCount > 1) {
5427 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5428 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
5429 uint32_t wait_count = 0;
5430 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
5431 if (!fences)
5432 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5433
5434 for (uint32_t i = 0; i < fenceCount; ++i) {
5435 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5436
5437 struct radv_fence_part *part =
5438 fence->temporary.kind != RADV_FENCE_NONE ?
5439 &fence->temporary : &fence->permanent;
5440 assert(part->kind == RADV_FENCE_WINSYS);
5441
5442 if (device->ws->fence_wait(device->ws, part->fence, false, 0)) {
5443 free(fences);
5444 return VK_SUCCESS;
5445 }
5446
5447 fences[wait_count++] = part->fence;
5448 }
5449
5450 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
5451 waitAll, timeout - radv_get_current_time());
5452
5453 free(fences);
5454 return success ? VK_SUCCESS : VK_TIMEOUT;
5455 }
5456
5457 while(radv_get_current_time() <= timeout) {
5458 for (uint32_t i = 0; i < fenceCount; ++i) {
5459 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
5460 return VK_SUCCESS;
5461 }
5462 }
5463 return VK_TIMEOUT;
5464 }
5465
5466 for (uint32_t i = 0; i < fenceCount; ++i) {
5467 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5468 bool expired = false;
5469
5470 struct radv_fence_part *part =
5471 fence->temporary.kind != RADV_FENCE_NONE ?
5472 &fence->temporary : &fence->permanent;
5473
5474 switch (part->kind) {
5475 case RADV_FENCE_NONE:
5476 break;
5477 case RADV_FENCE_WINSYS:
5478 if (!device->ws->is_fence_waitable(part->fence)) {
5479 while (!device->ws->is_fence_waitable(part->fence) &&
5480 radv_get_current_time() <= timeout)
5481 /* Do nothing */;
5482 }
5483
5484 expired = device->ws->fence_wait(device->ws,
5485 part->fence,
5486 true, timeout);
5487 if (!expired)
5488 return VK_TIMEOUT;
5489 break;
5490 case RADV_FENCE_SYNCOBJ:
5491 if (!device->ws->wait_syncobj(device->ws,
5492 &part->syncobj, 1, true,
5493 timeout))
5494 return VK_TIMEOUT;
5495 break;
5496 case RADV_FENCE_WSI: {
5497 VkResult result = part->fence_wsi->wait(part->fence_wsi, timeout);
5498 if (result != VK_SUCCESS)
5499 return result;
5500 break;
5501 }
5502 default:
5503 unreachable("Invalid fence type");
5504 }
5505 }
5506
5507 return VK_SUCCESS;
5508 }
5509
5510 VkResult radv_ResetFences(VkDevice _device,
5511 uint32_t fenceCount,
5512 const VkFence *pFences)
5513 {
5514 RADV_FROM_HANDLE(radv_device, device, _device);
5515
5516 for (unsigned i = 0; i < fenceCount; ++i) {
5517 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5518
5519 /* From the Vulkan 1.0.53 spec:
5520 *
5521 * "If any member of pFences currently has its payload
5522 * imported with temporary permanence, that fence’s prior
5523 * permanent payload is irst restored. The remaining
5524 * operations described therefore operate on the restored
5525 * payload."
5526 */
5527 if (fence->temporary.kind != RADV_FENCE_NONE)
5528 radv_destroy_fence_part(device, &fence->temporary);
5529
5530 struct radv_fence_part *part = &fence->permanent;
5531
5532 switch (part->kind) {
5533 case RADV_FENCE_WSI:
5534 device->ws->reset_fence(part->fence);
5535 break;
5536 case RADV_FENCE_SYNCOBJ:
5537 device->ws->reset_syncobj(device->ws, part->syncobj);
5538 break;
5539 default:
5540 unreachable("Invalid fence type");
5541 }
5542 }
5543
5544 return VK_SUCCESS;
5545 }
5546
5547 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
5548 {
5549 RADV_FROM_HANDLE(radv_device, device, _device);
5550 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5551
5552 struct radv_fence_part *part =
5553 fence->temporary.kind != RADV_FENCE_NONE ?
5554 &fence->temporary : &fence->permanent;
5555
5556 switch (part->kind) {
5557 case RADV_FENCE_NONE:
5558 break;
5559 case RADV_FENCE_WINSYS:
5560 if (!device->ws->fence_wait(device->ws, part->fence, false, 0))
5561 return VK_NOT_READY;
5562 break;
5563 case RADV_FENCE_SYNCOBJ: {
5564 bool success = device->ws->wait_syncobj(device->ws,
5565 &part->syncobj, 1, true, 0);
5566 if (!success)
5567 return VK_NOT_READY;
5568 break;
5569 }
5570 case RADV_FENCE_WSI: {
5571 VkResult result = part->fence_wsi->wait(part->fence_wsi, 0);
5572 if (result != VK_SUCCESS) {
5573 if (result == VK_TIMEOUT)
5574 return VK_NOT_READY;
5575 return result;
5576 }
5577 break;
5578 }
5579 default:
5580 unreachable("Invalid fence type");
5581 }
5582
5583 return VK_SUCCESS;
5584 }
5585
5586
5587 // Queue semaphore functions
5588
5589 static void
5590 radv_create_timeline(struct radv_timeline *timeline, uint64_t value)
5591 {
5592 timeline->highest_signaled = value;
5593 timeline->highest_submitted = value;
5594 list_inithead(&timeline->points);
5595 list_inithead(&timeline->free_points);
5596 list_inithead(&timeline->waiters);
5597 pthread_mutex_init(&timeline->mutex, NULL);
5598 }
5599
5600 static void
5601 radv_destroy_timeline(struct radv_device *device,
5602 struct radv_timeline *timeline)
5603 {
5604 list_for_each_entry_safe(struct radv_timeline_point, point,
5605 &timeline->free_points, list) {
5606 list_del(&point->list);
5607 device->ws->destroy_syncobj(device->ws, point->syncobj);
5608 free(point);
5609 }
5610 list_for_each_entry_safe(struct radv_timeline_point, point,
5611 &timeline->points, list) {
5612 list_del(&point->list);
5613 device->ws->destroy_syncobj(device->ws, point->syncobj);
5614 free(point);
5615 }
5616 pthread_mutex_destroy(&timeline->mutex);
5617 }
5618
5619 static void
5620 radv_timeline_gc_locked(struct radv_device *device,
5621 struct radv_timeline *timeline)
5622 {
5623 list_for_each_entry_safe(struct radv_timeline_point, point,
5624 &timeline->points, list) {
5625 if (point->wait_count || point->value > timeline->highest_submitted)
5626 return;
5627
5628 if (device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, 0)) {
5629 timeline->highest_signaled = point->value;
5630 list_del(&point->list);
5631 list_add(&point->list, &timeline->free_points);
5632 }
5633 }
5634 }
5635
5636 static struct radv_timeline_point *
5637 radv_timeline_find_point_at_least_locked(struct radv_device *device,
5638 struct radv_timeline *timeline,
5639 uint64_t p)
5640 {
5641 radv_timeline_gc_locked(device, timeline);
5642
5643 if (p <= timeline->highest_signaled)
5644 return NULL;
5645
5646 list_for_each_entry(struct radv_timeline_point, point,
5647 &timeline->points, list) {
5648 if (point->value >= p) {
5649 ++point->wait_count;
5650 return point;
5651 }
5652 }
5653 return NULL;
5654 }
5655
5656 static struct radv_timeline_point *
5657 radv_timeline_add_point_locked(struct radv_device *device,
5658 struct radv_timeline *timeline,
5659 uint64_t p)
5660 {
5661 radv_timeline_gc_locked(device, timeline);
5662
5663 struct radv_timeline_point *ret = NULL;
5664 struct radv_timeline_point *prev = NULL;
5665 int r;
5666
5667 if (p <= timeline->highest_signaled)
5668 return NULL;
5669
5670 list_for_each_entry(struct radv_timeline_point, point,
5671 &timeline->points, list) {
5672 if (point->value == p) {
5673 return NULL;
5674 }
5675
5676 if (point->value < p)
5677 prev = point;
5678 }
5679
5680 if (list_is_empty(&timeline->free_points)) {
5681 ret = malloc(sizeof(struct radv_timeline_point));
5682 r = device->ws->create_syncobj(device->ws, false, &ret->syncobj);
5683 if (r) {
5684 free(ret);
5685 return NULL;
5686 }
5687 } else {
5688 ret = list_first_entry(&timeline->free_points, struct radv_timeline_point, list);
5689 list_del(&ret->list);
5690
5691 device->ws->reset_syncobj(device->ws, ret->syncobj);
5692 }
5693
5694 ret->value = p;
5695 ret->wait_count = 1;
5696
5697 if (prev) {
5698 list_add(&ret->list, &prev->list);
5699 } else {
5700 list_addtail(&ret->list, &timeline->points);
5701 }
5702 return ret;
5703 }
5704
5705
5706 static VkResult
5707 radv_timeline_wait_locked(struct radv_device *device,
5708 struct radv_timeline *timeline,
5709 uint64_t value,
5710 uint64_t abs_timeout)
5711 {
5712 while(timeline->highest_submitted < value) {
5713 struct timespec abstime;
5714 timespec_from_nsec(&abstime, abs_timeout);
5715
5716 pthread_cond_timedwait(&device->timeline_cond, &timeline->mutex, &abstime);
5717
5718 if (radv_get_current_time() >= abs_timeout && timeline->highest_submitted < value)
5719 return VK_TIMEOUT;
5720 }
5721
5722 struct radv_timeline_point *point = radv_timeline_find_point_at_least_locked(device, timeline, value);
5723 if (!point)
5724 return VK_SUCCESS;
5725
5726 pthread_mutex_unlock(&timeline->mutex);
5727
5728 bool success = device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, abs_timeout);
5729
5730 pthread_mutex_lock(&timeline->mutex);
5731 point->wait_count--;
5732 return success ? VK_SUCCESS : VK_TIMEOUT;
5733 }
5734
5735 static void
5736 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
5737 struct list_head *processing_list)
5738 {
5739 list_for_each_entry_safe(struct radv_timeline_waiter, waiter,
5740 &timeline->waiters, list) {
5741 if (waiter->value > timeline->highest_submitted)
5742 continue;
5743
5744 if (p_atomic_dec_zero(&waiter->submission->submission_wait_count)) {
5745 list_addtail(&waiter->submission->processing_list, processing_list);
5746 }
5747 list_del(&waiter->list);
5748 }
5749 }
5750
5751 static
5752 void radv_destroy_semaphore_part(struct radv_device *device,
5753 struct radv_semaphore_part *part)
5754 {
5755 switch(part->kind) {
5756 case RADV_SEMAPHORE_NONE:
5757 break;
5758 case RADV_SEMAPHORE_WINSYS:
5759 device->ws->destroy_sem(part->ws_sem);
5760 break;
5761 case RADV_SEMAPHORE_TIMELINE:
5762 radv_destroy_timeline(device, &part->timeline);
5763 break;
5764 case RADV_SEMAPHORE_SYNCOBJ:
5765 device->ws->destroy_syncobj(device->ws, part->syncobj);
5766 break;
5767 }
5768 part->kind = RADV_SEMAPHORE_NONE;
5769 }
5770
5771 static VkSemaphoreTypeKHR
5772 radv_get_semaphore_type(const void *pNext, uint64_t *initial_value)
5773 {
5774 const VkSemaphoreTypeCreateInfo *type_info =
5775 vk_find_struct_const(pNext, SEMAPHORE_TYPE_CREATE_INFO);
5776
5777 if (!type_info)
5778 return VK_SEMAPHORE_TYPE_BINARY;
5779
5780 if (initial_value)
5781 *initial_value = type_info->initialValue;
5782 return type_info->semaphoreType;
5783 }
5784
5785 static void
5786 radv_destroy_semaphore(struct radv_device *device,
5787 const VkAllocationCallbacks *pAllocator,
5788 struct radv_semaphore *sem)
5789 {
5790 radv_destroy_semaphore_part(device, &sem->temporary);
5791 radv_destroy_semaphore_part(device, &sem->permanent);
5792 vk_object_base_finish(&sem->base);
5793 vk_free2(&device->vk.alloc, pAllocator, sem);
5794 }
5795
5796 VkResult radv_CreateSemaphore(
5797 VkDevice _device,
5798 const VkSemaphoreCreateInfo* pCreateInfo,
5799 const VkAllocationCallbacks* pAllocator,
5800 VkSemaphore* pSemaphore)
5801 {
5802 RADV_FROM_HANDLE(radv_device, device, _device);
5803 const VkExportSemaphoreCreateInfo *export =
5804 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
5805 VkExternalSemaphoreHandleTypeFlags handleTypes =
5806 export ? export->handleTypes : 0;
5807 uint64_t initial_value = 0;
5808 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pCreateInfo->pNext, &initial_value);
5809
5810 struct radv_semaphore *sem = vk_alloc2(&device->vk.alloc, pAllocator,
5811 sizeof(*sem), 8,
5812 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5813 if (!sem)
5814 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5815
5816 vk_object_base_init(&device->vk, &sem->base,
5817 VK_OBJECT_TYPE_SEMAPHORE);
5818
5819 sem->temporary.kind = RADV_SEMAPHORE_NONE;
5820 sem->permanent.kind = RADV_SEMAPHORE_NONE;
5821
5822 if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
5823 radv_create_timeline(&sem->permanent.timeline, initial_value);
5824 sem->permanent.kind = RADV_SEMAPHORE_TIMELINE;
5825 } else if (device->always_use_syncobj || handleTypes) {
5826 assert (device->physical_device->rad_info.has_syncobj);
5827 int ret = device->ws->create_syncobj(device->ws, false,
5828 &sem->permanent.syncobj);
5829 if (ret) {
5830 radv_destroy_semaphore(device, pAllocator, sem);
5831 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5832 }
5833 sem->permanent.kind = RADV_SEMAPHORE_SYNCOBJ;
5834 } else {
5835 sem->permanent.ws_sem = device->ws->create_sem(device->ws);
5836 if (!sem->permanent.ws_sem) {
5837 radv_destroy_semaphore(device, pAllocator, sem);
5838 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5839 }
5840 sem->permanent.kind = RADV_SEMAPHORE_WINSYS;
5841 }
5842
5843 *pSemaphore = radv_semaphore_to_handle(sem);
5844 return VK_SUCCESS;
5845 }
5846
5847 void radv_DestroySemaphore(
5848 VkDevice _device,
5849 VkSemaphore _semaphore,
5850 const VkAllocationCallbacks* pAllocator)
5851 {
5852 RADV_FROM_HANDLE(radv_device, device, _device);
5853 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
5854 if (!_semaphore)
5855 return;
5856
5857 radv_destroy_semaphore(device, pAllocator, sem);
5858 }
5859
5860 VkResult
5861 radv_GetSemaphoreCounterValue(VkDevice _device,
5862 VkSemaphore _semaphore,
5863 uint64_t* pValue)
5864 {
5865 RADV_FROM_HANDLE(radv_device, device, _device);
5866 RADV_FROM_HANDLE(radv_semaphore, semaphore, _semaphore);
5867
5868 struct radv_semaphore_part *part =
5869 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
5870
5871 switch (part->kind) {
5872 case RADV_SEMAPHORE_TIMELINE: {
5873 pthread_mutex_lock(&part->timeline.mutex);
5874 radv_timeline_gc_locked(device, &part->timeline);
5875 *pValue = part->timeline.highest_signaled;
5876 pthread_mutex_unlock(&part->timeline.mutex);
5877 return VK_SUCCESS;
5878 }
5879 case RADV_SEMAPHORE_NONE:
5880 case RADV_SEMAPHORE_SYNCOBJ:
5881 case RADV_SEMAPHORE_WINSYS:
5882 unreachable("Invalid semaphore type");
5883 }
5884 unreachable("Unhandled semaphore type");
5885 }
5886
5887
5888 static VkResult
5889 radv_wait_timelines(struct radv_device *device,
5890 const VkSemaphoreWaitInfo* pWaitInfo,
5891 uint64_t abs_timeout)
5892 {
5893 if ((pWaitInfo->flags & VK_SEMAPHORE_WAIT_ANY_BIT_KHR) && pWaitInfo->semaphoreCount > 1) {
5894 for (;;) {
5895 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
5896 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
5897 pthread_mutex_lock(&semaphore->permanent.timeline.mutex);
5898 VkResult result = radv_timeline_wait_locked(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], 0);
5899 pthread_mutex_unlock(&semaphore->permanent.timeline.mutex);
5900
5901 if (result == VK_SUCCESS)
5902 return VK_SUCCESS;
5903 }
5904 if (radv_get_current_time() > abs_timeout)
5905 return VK_TIMEOUT;
5906 }
5907 }
5908
5909 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
5910 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
5911 pthread_mutex_lock(&semaphore->permanent.timeline.mutex);
5912 VkResult result = radv_timeline_wait_locked(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], abs_timeout);
5913 pthread_mutex_unlock(&semaphore->permanent.timeline.mutex);
5914
5915 if (result != VK_SUCCESS)
5916 return result;
5917 }
5918 return VK_SUCCESS;
5919 }
5920 VkResult
5921 radv_WaitSemaphores(VkDevice _device,
5922 const VkSemaphoreWaitInfo* pWaitInfo,
5923 uint64_t timeout)
5924 {
5925 RADV_FROM_HANDLE(radv_device, device, _device);
5926 uint64_t abs_timeout = radv_get_absolute_timeout(timeout);
5927 return radv_wait_timelines(device, pWaitInfo, abs_timeout);
5928 }
5929
5930 VkResult
5931 radv_SignalSemaphore(VkDevice _device,
5932 const VkSemaphoreSignalInfo* pSignalInfo)
5933 {
5934 RADV_FROM_HANDLE(radv_device, device, _device);
5935 RADV_FROM_HANDLE(radv_semaphore, semaphore, pSignalInfo->semaphore);
5936
5937 struct radv_semaphore_part *part =
5938 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
5939
5940 switch(part->kind) {
5941 case RADV_SEMAPHORE_TIMELINE: {
5942 pthread_mutex_lock(&part->timeline.mutex);
5943 radv_timeline_gc_locked(device, &part->timeline);
5944 part->timeline.highest_submitted = MAX2(part->timeline.highest_submitted, pSignalInfo->value);
5945 part->timeline.highest_signaled = MAX2(part->timeline.highest_signaled, pSignalInfo->value);
5946
5947 struct list_head processing_list;
5948 list_inithead(&processing_list);
5949 radv_timeline_trigger_waiters_locked(&part->timeline, &processing_list);
5950 pthread_mutex_unlock(&part->timeline.mutex);
5951
5952 return radv_process_submissions(&processing_list);
5953 }
5954 case RADV_SEMAPHORE_NONE:
5955 case RADV_SEMAPHORE_SYNCOBJ:
5956 case RADV_SEMAPHORE_WINSYS:
5957 unreachable("Invalid semaphore type");
5958 }
5959 return VK_SUCCESS;
5960 }
5961
5962 static void radv_destroy_event(struct radv_device *device,
5963 const VkAllocationCallbacks* pAllocator,
5964 struct radv_event *event)
5965 {
5966 if (event->bo)
5967 device->ws->buffer_destroy(event->bo);
5968
5969 vk_object_base_finish(&event->base);
5970 vk_free2(&device->vk.alloc, pAllocator, event);
5971 }
5972
5973 VkResult radv_CreateEvent(
5974 VkDevice _device,
5975 const VkEventCreateInfo* pCreateInfo,
5976 const VkAllocationCallbacks* pAllocator,
5977 VkEvent* pEvent)
5978 {
5979 RADV_FROM_HANDLE(radv_device, device, _device);
5980 struct radv_event *event = vk_alloc2(&device->vk.alloc, pAllocator,
5981 sizeof(*event), 8,
5982 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5983
5984 if (!event)
5985 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5986
5987 vk_object_base_init(&device->vk, &event->base, VK_OBJECT_TYPE_EVENT);
5988
5989 event->bo = device->ws->buffer_create(device->ws, 8, 8,
5990 RADEON_DOMAIN_GTT,
5991 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
5992 RADV_BO_PRIORITY_FENCE);
5993 if (!event->bo) {
5994 radv_destroy_event(device, pAllocator, event);
5995 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5996 }
5997
5998 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
5999 if (!event->map) {
6000 radv_destroy_event(device, pAllocator, event);
6001 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6002 }
6003
6004 *pEvent = radv_event_to_handle(event);
6005
6006 return VK_SUCCESS;
6007 }
6008
6009 void radv_DestroyEvent(
6010 VkDevice _device,
6011 VkEvent _event,
6012 const VkAllocationCallbacks* pAllocator)
6013 {
6014 RADV_FROM_HANDLE(radv_device, device, _device);
6015 RADV_FROM_HANDLE(radv_event, event, _event);
6016
6017 if (!event)
6018 return;
6019
6020 radv_destroy_event(device, pAllocator, event);
6021 }
6022
6023 VkResult radv_GetEventStatus(
6024 VkDevice _device,
6025 VkEvent _event)
6026 {
6027 RADV_FROM_HANDLE(radv_event, event, _event);
6028
6029 if (*event->map == 1)
6030 return VK_EVENT_SET;
6031 return VK_EVENT_RESET;
6032 }
6033
6034 VkResult radv_SetEvent(
6035 VkDevice _device,
6036 VkEvent _event)
6037 {
6038 RADV_FROM_HANDLE(radv_event, event, _event);
6039 *event->map = 1;
6040
6041 return VK_SUCCESS;
6042 }
6043
6044 VkResult radv_ResetEvent(
6045 VkDevice _device,
6046 VkEvent _event)
6047 {
6048 RADV_FROM_HANDLE(radv_event, event, _event);
6049 *event->map = 0;
6050
6051 return VK_SUCCESS;
6052 }
6053
6054 static void
6055 radv_destroy_buffer(struct radv_device *device,
6056 const VkAllocationCallbacks *pAllocator,
6057 struct radv_buffer *buffer)
6058 {
6059 if ((buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) && buffer->bo)
6060 device->ws->buffer_destroy(buffer->bo);
6061
6062 vk_object_base_finish(&buffer->base);
6063 vk_free2(&device->vk.alloc, pAllocator, buffer);
6064 }
6065
6066 VkResult radv_CreateBuffer(
6067 VkDevice _device,
6068 const VkBufferCreateInfo* pCreateInfo,
6069 const VkAllocationCallbacks* pAllocator,
6070 VkBuffer* pBuffer)
6071 {
6072 RADV_FROM_HANDLE(radv_device, device, _device);
6073 struct radv_buffer *buffer;
6074
6075 if (pCreateInfo->size > RADV_MAX_MEMORY_ALLOCATION_SIZE)
6076 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
6077
6078 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
6079
6080 buffer = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*buffer), 8,
6081 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6082 if (buffer == NULL)
6083 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6084
6085 vk_object_base_init(&device->vk, &buffer->base, VK_OBJECT_TYPE_BUFFER);
6086
6087 buffer->size = pCreateInfo->size;
6088 buffer->usage = pCreateInfo->usage;
6089 buffer->bo = NULL;
6090 buffer->offset = 0;
6091 buffer->flags = pCreateInfo->flags;
6092
6093 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
6094 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
6095
6096 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
6097 buffer->bo = device->ws->buffer_create(device->ws,
6098 align64(buffer->size, 4096),
6099 4096, 0, RADEON_FLAG_VIRTUAL,
6100 RADV_BO_PRIORITY_VIRTUAL);
6101 if (!buffer->bo) {
6102 radv_destroy_buffer(device, pAllocator, buffer);
6103 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6104 }
6105 }
6106
6107 *pBuffer = radv_buffer_to_handle(buffer);
6108
6109 return VK_SUCCESS;
6110 }
6111
6112 void radv_DestroyBuffer(
6113 VkDevice _device,
6114 VkBuffer _buffer,
6115 const VkAllocationCallbacks* pAllocator)
6116 {
6117 RADV_FROM_HANDLE(radv_device, device, _device);
6118 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
6119
6120 if (!buffer)
6121 return;
6122
6123 radv_destroy_buffer(device, pAllocator, buffer);
6124 }
6125
6126 VkDeviceAddress radv_GetBufferDeviceAddress(
6127 VkDevice device,
6128 const VkBufferDeviceAddressInfo* pInfo)
6129 {
6130 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
6131 return radv_buffer_get_va(buffer->bo) + buffer->offset;
6132 }
6133
6134
6135 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device,
6136 const VkBufferDeviceAddressInfo* pInfo)
6137 {
6138 return 0;
6139 }
6140
6141 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device,
6142 const VkDeviceMemoryOpaqueCaptureAddressInfo* pInfo)
6143 {
6144 return 0;
6145 }
6146
6147 static inline unsigned
6148 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
6149 {
6150 if (stencil)
6151 return plane->surface.u.legacy.stencil_tiling_index[level];
6152 else
6153 return plane->surface.u.legacy.tiling_index[level];
6154 }
6155
6156 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
6157 {
6158 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
6159 }
6160
6161 static uint32_t
6162 radv_init_dcc_control_reg(struct radv_device *device,
6163 struct radv_image_view *iview)
6164 {
6165 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
6166 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
6167 unsigned max_compressed_block_size;
6168 unsigned independent_128b_blocks;
6169 unsigned independent_64b_blocks;
6170
6171 if (!radv_dcc_enabled(iview->image, iview->base_mip))
6172 return 0;
6173
6174 if (!device->physical_device->rad_info.has_dedicated_vram) {
6175 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6176 * dGPU and 64 for APU because all of our APUs to date use
6177 * DIMMs which have a request granularity size of 64B while all
6178 * other chips have a 32B request size.
6179 */
6180 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
6181 }
6182
6183 if (device->physical_device->rad_info.chip_class >= GFX10) {
6184 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6185 independent_64b_blocks = 0;
6186 independent_128b_blocks = 1;
6187 } else {
6188 independent_128b_blocks = 0;
6189
6190 if (iview->image->info.samples > 1) {
6191 if (iview->image->planes[0].surface.bpe == 1)
6192 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6193 else if (iview->image->planes[0].surface.bpe == 2)
6194 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6195 }
6196
6197 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
6198 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
6199 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
6200 /* If this DCC image is potentially going to be used in texture
6201 * fetches, we need some special settings.
6202 */
6203 independent_64b_blocks = 1;
6204 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6205 } else {
6206 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6207 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6208 * big as possible for better compression state.
6209 */
6210 independent_64b_blocks = 0;
6211 max_compressed_block_size = max_uncompressed_block_size;
6212 }
6213 }
6214
6215 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
6216 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
6217 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
6218 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
6219 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
6220 }
6221
6222 void
6223 radv_initialise_color_surface(struct radv_device *device,
6224 struct radv_color_buffer_info *cb,
6225 struct radv_image_view *iview)
6226 {
6227 const struct vk_format_description *desc;
6228 unsigned ntype, format, swap, endian;
6229 unsigned blend_clamp = 0, blend_bypass = 0;
6230 uint64_t va;
6231 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
6232 const struct radeon_surf *surf = &plane->surface;
6233
6234 desc = vk_format_description(iview->vk_format);
6235
6236 memset(cb, 0, sizeof(*cb));
6237
6238 /* Intensity is implemented as Red, so treat it that way. */
6239 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
6240
6241 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
6242
6243 cb->cb_color_base = va >> 8;
6244
6245 if (device->physical_device->rad_info.chip_class >= GFX9) {
6246 if (device->physical_device->rad_info.chip_class >= GFX10) {
6247 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6248 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6249 S_028EE0_CMASK_PIPE_ALIGNED(1) |
6250 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
6251 } else {
6252 struct gfx9_surf_meta_flags meta = {
6253 .rb_aligned = 1,
6254 .pipe_aligned = 1,
6255 };
6256
6257 if (surf->dcc_offset)
6258 meta = surf->u.gfx9.dcc;
6259
6260 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6261 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6262 S_028C74_RB_ALIGNED(meta.rb_aligned) |
6263 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
6264 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
6265 }
6266
6267 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
6268 cb->cb_color_base |= surf->tile_swizzle;
6269 } else {
6270 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
6271 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
6272
6273 cb->cb_color_base += level_info->offset >> 8;
6274 if (level_info->mode == RADEON_SURF_MODE_2D)
6275 cb->cb_color_base |= surf->tile_swizzle;
6276
6277 pitch_tile_max = level_info->nblk_x / 8 - 1;
6278 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
6279 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
6280
6281 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
6282 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
6283 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
6284
6285 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
6286
6287 if (radv_image_has_fmask(iview->image)) {
6288 if (device->physical_device->rad_info.chip_class >= GFX7)
6289 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
6290 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
6291 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
6292 } else {
6293 /* This must be set for fast clear to work without FMASK. */
6294 if (device->physical_device->rad_info.chip_class >= GFX7)
6295 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
6296 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
6297 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
6298 }
6299 }
6300
6301 /* CMASK variables */
6302 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6303 va += surf->cmask_offset;
6304 cb->cb_color_cmask = va >> 8;
6305
6306 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6307 va += surf->dcc_offset;
6308
6309 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
6310 device->physical_device->rad_info.chip_class <= GFX8)
6311 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
6312
6313 unsigned dcc_tile_swizzle = surf->tile_swizzle;
6314 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
6315
6316 cb->cb_dcc_base = va >> 8;
6317 cb->cb_dcc_base |= dcc_tile_swizzle;
6318
6319 /* GFX10 field has the same base shift as the GFX6 field. */
6320 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6321 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
6322 S_028C6C_SLICE_MAX_GFX10(max_slice);
6323
6324 if (iview->image->info.samples > 1) {
6325 unsigned log_samples = util_logbase2(iview->image->info.samples);
6326
6327 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
6328 S_028C74_NUM_FRAGMENTS(log_samples);
6329 }
6330
6331 if (radv_image_has_fmask(iview->image)) {
6332 va = radv_buffer_get_va(iview->bo) + iview->image->offset + surf->fmask_offset;
6333 cb->cb_color_fmask = va >> 8;
6334 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
6335 } else {
6336 cb->cb_color_fmask = cb->cb_color_base;
6337 }
6338
6339 ntype = radv_translate_color_numformat(iview->vk_format,
6340 desc,
6341 vk_format_get_first_non_void_channel(iview->vk_format));
6342 format = radv_translate_colorformat(iview->vk_format);
6343 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
6344 radv_finishme("Illegal color\n");
6345 swap = radv_translate_colorswap(iview->vk_format, false);
6346 endian = radv_colorformat_endian_swap(format);
6347
6348 /* blend clamp should be set for all NORM/SRGB types */
6349 if (ntype == V_028C70_NUMBER_UNORM ||
6350 ntype == V_028C70_NUMBER_SNORM ||
6351 ntype == V_028C70_NUMBER_SRGB)
6352 blend_clamp = 1;
6353
6354 /* set blend bypass according to docs if SINT/UINT or
6355 8/24 COLOR variants */
6356 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
6357 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
6358 format == V_028C70_COLOR_X24_8_32_FLOAT) {
6359 blend_clamp = 0;
6360 blend_bypass = 1;
6361 }
6362 #if 0
6363 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
6364 (format == V_028C70_COLOR_8 ||
6365 format == V_028C70_COLOR_8_8 ||
6366 format == V_028C70_COLOR_8_8_8_8))
6367 ->color_is_int8 = true;
6368 #endif
6369 cb->cb_color_info = S_028C70_FORMAT(format) |
6370 S_028C70_COMP_SWAP(swap) |
6371 S_028C70_BLEND_CLAMP(blend_clamp) |
6372 S_028C70_BLEND_BYPASS(blend_bypass) |
6373 S_028C70_SIMPLE_FLOAT(1) |
6374 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
6375 ntype != V_028C70_NUMBER_SNORM &&
6376 ntype != V_028C70_NUMBER_SRGB &&
6377 format != V_028C70_COLOR_8_24 &&
6378 format != V_028C70_COLOR_24_8) |
6379 S_028C70_NUMBER_TYPE(ntype) |
6380 S_028C70_ENDIAN(endian);
6381 if (radv_image_has_fmask(iview->image)) {
6382 cb->cb_color_info |= S_028C70_COMPRESSION(1);
6383 if (device->physical_device->rad_info.chip_class == GFX6) {
6384 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
6385 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
6386 }
6387
6388 if (radv_image_is_tc_compat_cmask(iview->image)) {
6389 /* Allow the texture block to read FMASK directly
6390 * without decompressing it. This bit must be cleared
6391 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6392 * otherwise the operation doesn't happen.
6393 */
6394 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6395
6396 /* Set CMASK into a tiling format that allows the
6397 * texture block to read it.
6398 */
6399 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
6400 }
6401 }
6402
6403 if (radv_image_has_cmask(iview->image) &&
6404 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
6405 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
6406
6407 if (radv_dcc_enabled(iview->image, iview->base_mip))
6408 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
6409
6410 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
6411
6412 /* This must be set for fast clear to work without FMASK. */
6413 if (!radv_image_has_fmask(iview->image) &&
6414 device->physical_device->rad_info.chip_class == GFX6) {
6415 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
6416 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
6417 }
6418
6419 if (device->physical_device->rad_info.chip_class >= GFX9) {
6420 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
6421
6422 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
6423 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
6424 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
6425 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
6426
6427 if (device->physical_device->rad_info.chip_class >= GFX10) {
6428 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
6429
6430 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
6431 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
6432 S_028EE0_RESOURCE_LEVEL(1);
6433 } else {
6434 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
6435 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
6436 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
6437 }
6438
6439 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
6440 S_028C68_MIP0_HEIGHT(height - 1) |
6441 S_028C68_MAX_MIP(iview->image->info.levels - 1);
6442 }
6443 }
6444
6445 static unsigned
6446 radv_calc_decompress_on_z_planes(struct radv_device *device,
6447 struct radv_image_view *iview)
6448 {
6449 unsigned max_zplanes = 0;
6450
6451 assert(radv_image_is_tc_compat_htile(iview->image));
6452
6453 if (device->physical_device->rad_info.chip_class >= GFX9) {
6454 /* Default value for 32-bit depth surfaces. */
6455 max_zplanes = 4;
6456
6457 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
6458 iview->image->info.samples > 1)
6459 max_zplanes = 2;
6460
6461 max_zplanes = max_zplanes + 1;
6462 } else {
6463 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
6464 /* Do not enable Z plane compression for 16-bit depth
6465 * surfaces because isn't supported on GFX8. Only
6466 * 32-bit depth surfaces are supported by the hardware.
6467 * This allows to maintain shader compatibility and to
6468 * reduce the number of depth decompressions.
6469 */
6470 max_zplanes = 1;
6471 } else {
6472 if (iview->image->info.samples <= 1)
6473 max_zplanes = 5;
6474 else if (iview->image->info.samples <= 4)
6475 max_zplanes = 3;
6476 else
6477 max_zplanes = 2;
6478 }
6479 }
6480
6481 return max_zplanes;
6482 }
6483
6484 void
6485 radv_initialise_ds_surface(struct radv_device *device,
6486 struct radv_ds_buffer_info *ds,
6487 struct radv_image_view *iview)
6488 {
6489 unsigned level = iview->base_mip;
6490 unsigned format, stencil_format;
6491 uint64_t va, s_offs, z_offs;
6492 bool stencil_only = false;
6493 const struct radv_image_plane *plane = &iview->image->planes[0];
6494 const struct radeon_surf *surf = &plane->surface;
6495
6496 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
6497
6498 memset(ds, 0, sizeof(*ds));
6499 switch (iview->image->vk_format) {
6500 case VK_FORMAT_D24_UNORM_S8_UINT:
6501 case VK_FORMAT_X8_D24_UNORM_PACK32:
6502 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6503 ds->offset_scale = 2.0f;
6504 break;
6505 case VK_FORMAT_D16_UNORM:
6506 case VK_FORMAT_D16_UNORM_S8_UINT:
6507 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6508 ds->offset_scale = 4.0f;
6509 break;
6510 case VK_FORMAT_D32_SFLOAT:
6511 case VK_FORMAT_D32_SFLOAT_S8_UINT:
6512 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6513 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6514 ds->offset_scale = 1.0f;
6515 break;
6516 case VK_FORMAT_S8_UINT:
6517 stencil_only = true;
6518 break;
6519 default:
6520 break;
6521 }
6522
6523 format = radv_translate_dbformat(iview->image->vk_format);
6524 stencil_format = surf->has_stencil ?
6525 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
6526
6527 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6528 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
6529 S_028008_SLICE_MAX(max_slice);
6530 if (device->physical_device->rad_info.chip_class >= GFX10) {
6531 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
6532 S_028008_SLICE_MAX_HI(max_slice >> 11);
6533 }
6534
6535 ds->db_htile_data_base = 0;
6536 ds->db_htile_surface = 0;
6537
6538 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6539 s_offs = z_offs = va;
6540
6541 if (device->physical_device->rad_info.chip_class >= GFX9) {
6542 assert(surf->u.gfx9.surf_offset == 0);
6543 s_offs += surf->u.gfx9.stencil_offset;
6544
6545 ds->db_z_info = S_028038_FORMAT(format) |
6546 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
6547 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6548 S_028038_MAXMIP(iview->image->info.levels - 1) |
6549 S_028038_ZRANGE_PRECISION(1);
6550 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
6551 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
6552
6553 if (device->physical_device->rad_info.chip_class == GFX9) {
6554 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
6555 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
6556 }
6557
6558 ds->db_depth_view |= S_028008_MIPID(level);
6559 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
6560 S_02801C_Y_MAX(iview->image->info.height - 1);
6561
6562 if (radv_htile_enabled(iview->image, level)) {
6563 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
6564
6565 if (radv_image_is_tc_compat_htile(iview->image)) {
6566 unsigned max_zplanes =
6567 radv_calc_decompress_on_z_planes(device, iview);
6568
6569 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6570
6571 if (device->physical_device->rad_info.chip_class >= GFX10) {
6572 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
6573 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
6574 } else {
6575 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
6576 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
6577 }
6578 }
6579
6580 if (!surf->has_stencil)
6581 /* Use all of the htile_buffer for depth if there's no stencil. */
6582 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
6583 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
6584 surf->htile_offset;
6585 ds->db_htile_data_base = va >> 8;
6586 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
6587 S_028ABC_PIPE_ALIGNED(1);
6588
6589 if (device->physical_device->rad_info.chip_class == GFX9) {
6590 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(1);
6591 }
6592 }
6593 } else {
6594 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
6595
6596 if (stencil_only)
6597 level_info = &surf->u.legacy.stencil_level[level];
6598
6599 z_offs += surf->u.legacy.level[level].offset;
6600 s_offs += surf->u.legacy.stencil_level[level].offset;
6601
6602 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
6603 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
6604 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
6605
6606 if (iview->image->info.samples > 1)
6607 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
6608
6609 if (device->physical_device->rad_info.chip_class >= GFX7) {
6610 struct radeon_info *info = &device->physical_device->rad_info;
6611 unsigned tiling_index = surf->u.legacy.tiling_index[level];
6612 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
6613 unsigned macro_index = surf->u.legacy.macro_tile_index;
6614 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
6615 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
6616 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
6617
6618 if (stencil_only)
6619 tile_mode = stencil_tile_mode;
6620
6621 ds->db_depth_info |=
6622 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
6623 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
6624 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
6625 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
6626 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
6627 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
6628 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
6629 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
6630 } else {
6631 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
6632 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6633 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
6634 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
6635 if (stencil_only)
6636 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6637 }
6638
6639 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
6640 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
6641 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
6642
6643 if (radv_htile_enabled(iview->image, level)) {
6644 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
6645
6646 if (!surf->has_stencil &&
6647 !radv_image_is_tc_compat_htile(iview->image))
6648 /* Use all of the htile_buffer for depth if there's no stencil. */
6649 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
6650
6651 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
6652 surf->htile_offset;
6653 ds->db_htile_data_base = va >> 8;
6654 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
6655
6656 if (radv_image_is_tc_compat_htile(iview->image)) {
6657 unsigned max_zplanes =
6658 radv_calc_decompress_on_z_planes(device, iview);
6659
6660 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
6661 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6662 }
6663 }
6664 }
6665
6666 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
6667 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
6668 }
6669
6670 VkResult radv_CreateFramebuffer(
6671 VkDevice _device,
6672 const VkFramebufferCreateInfo* pCreateInfo,
6673 const VkAllocationCallbacks* pAllocator,
6674 VkFramebuffer* pFramebuffer)
6675 {
6676 RADV_FROM_HANDLE(radv_device, device, _device);
6677 struct radv_framebuffer *framebuffer;
6678 const VkFramebufferAttachmentsCreateInfo *imageless_create_info =
6679 vk_find_struct_const(pCreateInfo->pNext,
6680 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO);
6681
6682 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
6683
6684 size_t size = sizeof(*framebuffer);
6685 if (!imageless_create_info)
6686 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
6687 framebuffer = vk_alloc2(&device->vk.alloc, pAllocator, size, 8,
6688 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6689 if (framebuffer == NULL)
6690 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6691
6692 vk_object_base_init(&device->vk, &framebuffer->base,
6693 VK_OBJECT_TYPE_FRAMEBUFFER);
6694
6695 framebuffer->attachment_count = pCreateInfo->attachmentCount;
6696 framebuffer->width = pCreateInfo->width;
6697 framebuffer->height = pCreateInfo->height;
6698 framebuffer->layers = pCreateInfo->layers;
6699 if (imageless_create_info) {
6700 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
6701 const VkFramebufferAttachmentImageInfo *attachment =
6702 imageless_create_info->pAttachmentImageInfos + i;
6703 framebuffer->width = MIN2(framebuffer->width, attachment->width);
6704 framebuffer->height = MIN2(framebuffer->height, attachment->height);
6705 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
6706 }
6707 } else {
6708 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
6709 VkImageView _iview = pCreateInfo->pAttachments[i];
6710 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
6711 framebuffer->attachments[i] = iview;
6712 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
6713 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
6714 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
6715 }
6716 }
6717
6718 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
6719 return VK_SUCCESS;
6720 }
6721
6722 void radv_DestroyFramebuffer(
6723 VkDevice _device,
6724 VkFramebuffer _fb,
6725 const VkAllocationCallbacks* pAllocator)
6726 {
6727 RADV_FROM_HANDLE(radv_device, device, _device);
6728 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
6729
6730 if (!fb)
6731 return;
6732 vk_object_base_finish(&fb->base);
6733 vk_free2(&device->vk.alloc, pAllocator, fb);
6734 }
6735
6736 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
6737 {
6738 switch (address_mode) {
6739 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
6740 return V_008F30_SQ_TEX_WRAP;
6741 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
6742 return V_008F30_SQ_TEX_MIRROR;
6743 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
6744 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
6745 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
6746 return V_008F30_SQ_TEX_CLAMP_BORDER;
6747 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
6748 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
6749 default:
6750 unreachable("illegal tex wrap mode");
6751 break;
6752 }
6753 }
6754
6755 static unsigned
6756 radv_tex_compare(VkCompareOp op)
6757 {
6758 switch (op) {
6759 case VK_COMPARE_OP_NEVER:
6760 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
6761 case VK_COMPARE_OP_LESS:
6762 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
6763 case VK_COMPARE_OP_EQUAL:
6764 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
6765 case VK_COMPARE_OP_LESS_OR_EQUAL:
6766 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
6767 case VK_COMPARE_OP_GREATER:
6768 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
6769 case VK_COMPARE_OP_NOT_EQUAL:
6770 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
6771 case VK_COMPARE_OP_GREATER_OR_EQUAL:
6772 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
6773 case VK_COMPARE_OP_ALWAYS:
6774 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
6775 default:
6776 unreachable("illegal compare mode");
6777 break;
6778 }
6779 }
6780
6781 static unsigned
6782 radv_tex_filter(VkFilter filter, unsigned max_ansio)
6783 {
6784 switch (filter) {
6785 case VK_FILTER_NEAREST:
6786 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
6787 V_008F38_SQ_TEX_XY_FILTER_POINT);
6788 case VK_FILTER_LINEAR:
6789 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
6790 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
6791 case VK_FILTER_CUBIC_IMG:
6792 default:
6793 fprintf(stderr, "illegal texture filter");
6794 return 0;
6795 }
6796 }
6797
6798 static unsigned
6799 radv_tex_mipfilter(VkSamplerMipmapMode mode)
6800 {
6801 switch (mode) {
6802 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
6803 return V_008F38_SQ_TEX_Z_FILTER_POINT;
6804 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
6805 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
6806 default:
6807 return V_008F38_SQ_TEX_Z_FILTER_NONE;
6808 }
6809 }
6810
6811 static unsigned
6812 radv_tex_bordercolor(VkBorderColor bcolor)
6813 {
6814 switch (bcolor) {
6815 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
6816 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
6817 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
6818 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
6819 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
6820 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
6821 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
6822 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
6823 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
6824 case VK_BORDER_COLOR_FLOAT_CUSTOM_EXT:
6825 case VK_BORDER_COLOR_INT_CUSTOM_EXT:
6826 return V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
6827 default:
6828 break;
6829 }
6830 return 0;
6831 }
6832
6833 static unsigned
6834 radv_tex_aniso_filter(unsigned filter)
6835 {
6836 if (filter < 2)
6837 return 0;
6838 if (filter < 4)
6839 return 1;
6840 if (filter < 8)
6841 return 2;
6842 if (filter < 16)
6843 return 3;
6844 return 4;
6845 }
6846
6847 static unsigned
6848 radv_tex_filter_mode(VkSamplerReductionMode mode)
6849 {
6850 switch (mode) {
6851 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
6852 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
6853 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
6854 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
6855 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
6856 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
6857 default:
6858 break;
6859 }
6860 return 0;
6861 }
6862
6863 static uint32_t
6864 radv_get_max_anisotropy(struct radv_device *device,
6865 const VkSamplerCreateInfo *pCreateInfo)
6866 {
6867 if (device->force_aniso >= 0)
6868 return device->force_aniso;
6869
6870 if (pCreateInfo->anisotropyEnable &&
6871 pCreateInfo->maxAnisotropy > 1.0f)
6872 return (uint32_t)pCreateInfo->maxAnisotropy;
6873
6874 return 0;
6875 }
6876
6877 static inline int S_FIXED(float value, unsigned frac_bits)
6878 {
6879 return value * (1 << frac_bits);
6880 }
6881
6882 static uint32_t radv_register_border_color(struct radv_device *device,
6883 VkClearColorValue value)
6884 {
6885 uint32_t slot;
6886
6887 pthread_mutex_lock(&device->border_color_data.mutex);
6888
6889 for (slot = 0; slot < RADV_BORDER_COLOR_COUNT; slot++) {
6890 if (!device->border_color_data.used[slot]) {
6891 /* Copy to the GPU wrt endian-ness. */
6892 util_memcpy_cpu_to_le32(&device->border_color_data.colors_gpu_ptr[slot],
6893 &value,
6894 sizeof(VkClearColorValue));
6895
6896 device->border_color_data.used[slot] = true;
6897 break;
6898 }
6899 }
6900
6901 pthread_mutex_unlock(&device->border_color_data.mutex);
6902
6903 return slot;
6904 }
6905
6906 static void radv_unregister_border_color(struct radv_device *device,
6907 uint32_t slot)
6908 {
6909 pthread_mutex_lock(&device->border_color_data.mutex);
6910
6911 device->border_color_data.used[slot] = false;
6912
6913 pthread_mutex_unlock(&device->border_color_data.mutex);
6914 }
6915
6916 static void
6917 radv_init_sampler(struct radv_device *device,
6918 struct radv_sampler *sampler,
6919 const VkSamplerCreateInfo *pCreateInfo)
6920 {
6921 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
6922 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
6923 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
6924 device->physical_device->rad_info.chip_class == GFX9;
6925 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
6926 unsigned depth_compare_func = V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
6927 bool trunc_coord = pCreateInfo->minFilter == VK_FILTER_NEAREST && pCreateInfo->magFilter == VK_FILTER_NEAREST;
6928 bool uses_border_color = pCreateInfo->addressModeU == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER ||
6929 pCreateInfo->addressModeV == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER ||
6930 pCreateInfo->addressModeW == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER;
6931 VkBorderColor border_color = uses_border_color ? pCreateInfo->borderColor : VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK;
6932 uint32_t border_color_ptr;
6933
6934 const struct VkSamplerReductionModeCreateInfo *sampler_reduction =
6935 vk_find_struct_const(pCreateInfo->pNext,
6936 SAMPLER_REDUCTION_MODE_CREATE_INFO);
6937 if (sampler_reduction)
6938 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
6939
6940 if (pCreateInfo->compareEnable)
6941 depth_compare_func = radv_tex_compare(pCreateInfo->compareOp);
6942
6943 sampler->border_color_slot = RADV_BORDER_COLOR_COUNT;
6944
6945 if (border_color == VK_BORDER_COLOR_FLOAT_CUSTOM_EXT || border_color == VK_BORDER_COLOR_INT_CUSTOM_EXT) {
6946 const VkSamplerCustomBorderColorCreateInfoEXT *custom_border_color =
6947 vk_find_struct_const(pCreateInfo->pNext,
6948 SAMPLER_CUSTOM_BORDER_COLOR_CREATE_INFO_EXT);
6949
6950 assert(custom_border_color);
6951
6952 sampler->border_color_slot =
6953 radv_register_border_color(device, custom_border_color->customBorderColor);
6954
6955 /* Did we fail to find a slot? */
6956 if (sampler->border_color_slot == RADV_BORDER_COLOR_COUNT) {
6957 fprintf(stderr, "WARNING: no free border color slots, defaulting to TRANS_BLACK.\n");
6958 border_color = VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK;
6959 }
6960 }
6961
6962 /* If we don't have a custom color, set the ptr to 0 */
6963 border_color_ptr = sampler->border_color_slot != RADV_BORDER_COLOR_COUNT
6964 ? sampler->border_color_slot
6965 : 0;
6966
6967 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
6968 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
6969 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
6970 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
6971 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func) |
6972 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
6973 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
6974 S_008F30_ANISO_BIAS(max_aniso_ratio) |
6975 S_008F30_DISABLE_CUBE_WRAP(0) |
6976 S_008F30_COMPAT_MODE(compat_mode) |
6977 S_008F30_FILTER_MODE(filter_mode) |
6978 S_008F30_TRUNC_COORD(trunc_coord));
6979 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
6980 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
6981 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
6982 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
6983 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
6984 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
6985 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
6986 S_008F38_MIP_POINT_PRECLAMP(0));
6987 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(border_color_ptr) |
6988 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(border_color)));
6989
6990 if (device->physical_device->rad_info.chip_class >= GFX10) {
6991 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
6992 } else {
6993 sampler->state[2] |=
6994 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
6995 S_008F38_FILTER_PREC_FIX(1) |
6996 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
6997 }
6998 }
6999
7000 VkResult radv_CreateSampler(
7001 VkDevice _device,
7002 const VkSamplerCreateInfo* pCreateInfo,
7003 const VkAllocationCallbacks* pAllocator,
7004 VkSampler* pSampler)
7005 {
7006 RADV_FROM_HANDLE(radv_device, device, _device);
7007 struct radv_sampler *sampler;
7008
7009 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
7010 vk_find_struct_const(pCreateInfo->pNext,
7011 SAMPLER_YCBCR_CONVERSION_INFO);
7012
7013 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
7014
7015 sampler = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*sampler), 8,
7016 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
7017 if (!sampler)
7018 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7019
7020 vk_object_base_init(&device->vk, &sampler->base,
7021 VK_OBJECT_TYPE_SAMPLER);
7022
7023 radv_init_sampler(device, sampler, pCreateInfo);
7024
7025 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
7026 *pSampler = radv_sampler_to_handle(sampler);
7027
7028 return VK_SUCCESS;
7029 }
7030
7031 void radv_DestroySampler(
7032 VkDevice _device,
7033 VkSampler _sampler,
7034 const VkAllocationCallbacks* pAllocator)
7035 {
7036 RADV_FROM_HANDLE(radv_device, device, _device);
7037 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
7038
7039 if (!sampler)
7040 return;
7041
7042 if (sampler->border_color_slot != RADV_BORDER_COLOR_COUNT)
7043 radv_unregister_border_color(device, sampler->border_color_slot);
7044
7045 vk_object_base_finish(&sampler->base);
7046 vk_free2(&device->vk.alloc, pAllocator, sampler);
7047 }
7048
7049 /* vk_icd.h does not declare this function, so we declare it here to
7050 * suppress Wmissing-prototypes.
7051 */
7052 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7053 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
7054
7055 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7056 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
7057 {
7058 /* For the full details on loader interface versioning, see
7059 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
7060 * What follows is a condensed summary, to help you navigate the large and
7061 * confusing official doc.
7062 *
7063 * - Loader interface v0 is incompatible with later versions. We don't
7064 * support it.
7065 *
7066 * - In loader interface v1:
7067 * - The first ICD entrypoint called by the loader is
7068 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
7069 * entrypoint.
7070 * - The ICD must statically expose no other Vulkan symbol unless it is
7071 * linked with -Bsymbolic.
7072 * - Each dispatchable Vulkan handle created by the ICD must be
7073 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7074 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7075 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7076 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7077 * such loader-managed surfaces.
7078 *
7079 * - Loader interface v2 differs from v1 in:
7080 * - The first ICD entrypoint called by the loader is
7081 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7082 * statically expose this entrypoint.
7083 *
7084 * - Loader interface v3 differs from v2 in:
7085 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7086 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7087 * because the loader no longer does so.
7088 */
7089 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
7090 return VK_SUCCESS;
7091 }
7092
7093 VkResult radv_GetMemoryFdKHR(VkDevice _device,
7094 const VkMemoryGetFdInfoKHR *pGetFdInfo,
7095 int *pFD)
7096 {
7097 RADV_FROM_HANDLE(radv_device, device, _device);
7098 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
7099
7100 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
7101
7102 /* At the moment, we support only the below handle types. */
7103 assert(pGetFdInfo->handleType ==
7104 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
7105 pGetFdInfo->handleType ==
7106 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
7107
7108 bool ret = radv_get_memory_fd(device, memory, pFD);
7109 if (ret == false)
7110 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
7111 return VK_SUCCESS;
7112 }
7113
7114 static uint32_t radv_compute_valid_memory_types_attempt(struct radv_physical_device *dev,
7115 enum radeon_bo_domain domains,
7116 enum radeon_bo_flag flags,
7117 enum radeon_bo_flag ignore_flags)
7118 {
7119 /* Don't count GTT/CPU as relevant:
7120 *
7121 * - We're not fully consistent between the two.
7122 * - Sometimes VRAM gets VRAM|GTT.
7123 */
7124 const enum radeon_bo_domain relevant_domains = RADEON_DOMAIN_VRAM |
7125 RADEON_DOMAIN_GDS |
7126 RADEON_DOMAIN_OA;
7127 uint32_t bits = 0;
7128 for (unsigned i = 0; i < dev->memory_properties.memoryTypeCount; ++i) {
7129 if ((domains & relevant_domains) != (dev->memory_domains[i] & relevant_domains))
7130 continue;
7131
7132 if ((flags & ~ignore_flags) != (dev->memory_flags[i] & ~ignore_flags))
7133 continue;
7134
7135 bits |= 1u << i;
7136 }
7137
7138 return bits;
7139 }
7140
7141 static uint32_t radv_compute_valid_memory_types(struct radv_physical_device *dev,
7142 enum radeon_bo_domain domains,
7143 enum radeon_bo_flag flags)
7144 {
7145 enum radeon_bo_flag ignore_flags = ~(RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_GTT_WC);
7146 uint32_t bits = radv_compute_valid_memory_types_attempt(dev, domains, flags, ignore_flags);
7147
7148 if (!bits) {
7149 ignore_flags |= RADEON_FLAG_NO_CPU_ACCESS;
7150 bits = radv_compute_valid_memory_types_attempt(dev, domains, flags, ignore_flags);
7151 }
7152
7153 return bits;
7154 }
7155 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
7156 VkExternalMemoryHandleTypeFlagBits handleType,
7157 int fd,
7158 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
7159 {
7160 RADV_FROM_HANDLE(radv_device, device, _device);
7161
7162 switch (handleType) {
7163 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT: {
7164 enum radeon_bo_domain domains;
7165 enum radeon_bo_flag flags;
7166 if (!device->ws->buffer_get_flags_from_fd(device->ws, fd, &domains, &flags))
7167 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7168
7169 pMemoryFdProperties->memoryTypeBits = radv_compute_valid_memory_types(device->physical_device, domains, flags);
7170 return VK_SUCCESS;
7171 }
7172 default:
7173 /* The valid usage section for this function says:
7174 *
7175 * "handleType must not be one of the handle types defined as
7176 * opaque."
7177 *
7178 * So opaque handle types fall into the default "unsupported" case.
7179 */
7180 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7181 }
7182 }
7183
7184 static VkResult radv_import_opaque_fd(struct radv_device *device,
7185 int fd,
7186 uint32_t *syncobj)
7187 {
7188 uint32_t syncobj_handle = 0;
7189 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
7190 if (ret != 0)
7191 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7192
7193 if (*syncobj)
7194 device->ws->destroy_syncobj(device->ws, *syncobj);
7195
7196 *syncobj = syncobj_handle;
7197 close(fd);
7198
7199 return VK_SUCCESS;
7200 }
7201
7202 static VkResult radv_import_sync_fd(struct radv_device *device,
7203 int fd,
7204 uint32_t *syncobj)
7205 {
7206 /* If we create a syncobj we do it locally so that if we have an error, we don't
7207 * leave a syncobj in an undetermined state in the fence. */
7208 uint32_t syncobj_handle = *syncobj;
7209 if (!syncobj_handle) {
7210 bool create_signaled = fd == -1 ? true : false;
7211
7212 int ret = device->ws->create_syncobj(device->ws, create_signaled,
7213 &syncobj_handle);
7214 if (ret) {
7215 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7216 }
7217 } else {
7218 if (fd == -1)
7219 device->ws->signal_syncobj(device->ws, syncobj_handle);
7220 }
7221
7222 if (fd != -1) {
7223 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
7224 if (ret)
7225 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7226 close(fd);
7227 }
7228
7229 *syncobj = syncobj_handle;
7230
7231 return VK_SUCCESS;
7232 }
7233
7234 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
7235 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
7236 {
7237 RADV_FROM_HANDLE(radv_device, device, _device);
7238 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
7239 VkResult result;
7240 struct radv_semaphore_part *dst = NULL;
7241
7242 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
7243 dst = &sem->temporary;
7244 } else {
7245 dst = &sem->permanent;
7246 }
7247
7248 uint32_t syncobj = dst->kind == RADV_SEMAPHORE_SYNCOBJ ? dst->syncobj : 0;
7249
7250 switch(pImportSemaphoreFdInfo->handleType) {
7251 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7252 result = radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7253 break;
7254 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7255 result = radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7256 break;
7257 default:
7258 unreachable("Unhandled semaphore handle type");
7259 }
7260
7261 if (result == VK_SUCCESS) {
7262 dst->syncobj = syncobj;
7263 dst->kind = RADV_SEMAPHORE_SYNCOBJ;
7264 }
7265
7266 return result;
7267 }
7268
7269 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
7270 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
7271 int *pFd)
7272 {
7273 RADV_FROM_HANDLE(radv_device, device, _device);
7274 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
7275 int ret;
7276 uint32_t syncobj_handle;
7277
7278 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7279 assert(sem->temporary.kind == RADV_SEMAPHORE_SYNCOBJ);
7280 syncobj_handle = sem->temporary.syncobj;
7281 } else {
7282 assert(sem->permanent.kind == RADV_SEMAPHORE_SYNCOBJ);
7283 syncobj_handle = sem->permanent.syncobj;
7284 }
7285
7286 switch(pGetFdInfo->handleType) {
7287 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7288 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
7289 if (ret)
7290 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7291 break;
7292 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7293 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
7294 if (ret)
7295 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7296
7297 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7298 radv_destroy_semaphore_part(device, &sem->temporary);
7299 } else {
7300 device->ws->reset_syncobj(device->ws, syncobj_handle);
7301 }
7302 break;
7303 default:
7304 unreachable("Unhandled semaphore handle type");
7305 }
7306
7307 return VK_SUCCESS;
7308 }
7309
7310 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7311 VkPhysicalDevice physicalDevice,
7312 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
7313 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
7314 {
7315 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7316 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pExternalSemaphoreInfo->pNext, NULL);
7317
7318 if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
7319 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7320 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7321 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7322
7323 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7324 } else if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7325 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7326 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
7327 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7328 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7329 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7330 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7331 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
7332 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7333 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7334 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7335 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7336 } else {
7337 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7338 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7339 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7340 }
7341 }
7342
7343 VkResult radv_ImportFenceFdKHR(VkDevice _device,
7344 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
7345 {
7346 RADV_FROM_HANDLE(radv_device, device, _device);
7347 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
7348 struct radv_fence_part *dst = NULL;
7349 VkResult result;
7350
7351 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
7352 dst = &fence->temporary;
7353 } else {
7354 dst = &fence->permanent;
7355 }
7356
7357 uint32_t syncobj = dst->kind == RADV_FENCE_SYNCOBJ ? dst->syncobj : 0;
7358
7359 switch(pImportFenceFdInfo->handleType) {
7360 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7361 result = radv_import_opaque_fd(device, pImportFenceFdInfo->fd, &syncobj);
7362 break;
7363 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7364 result = radv_import_sync_fd(device, pImportFenceFdInfo->fd, &syncobj);
7365 break;
7366 default:
7367 unreachable("Unhandled fence handle type");
7368 }
7369
7370 if (result == VK_SUCCESS) {
7371 dst->syncobj = syncobj;
7372 dst->kind = RADV_FENCE_SYNCOBJ;
7373 }
7374
7375 return result;
7376 }
7377
7378 VkResult radv_GetFenceFdKHR(VkDevice _device,
7379 const VkFenceGetFdInfoKHR *pGetFdInfo,
7380 int *pFd)
7381 {
7382 RADV_FROM_HANDLE(radv_device, device, _device);
7383 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
7384 int ret;
7385
7386 struct radv_fence_part *part =
7387 fence->temporary.kind != RADV_FENCE_NONE ?
7388 &fence->temporary : &fence->permanent;
7389
7390 switch(pGetFdInfo->handleType) {
7391 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7392 ret = device->ws->export_syncobj(device->ws, part->syncobj, pFd);
7393 if (ret)
7394 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7395 break;
7396 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7397 ret = device->ws->export_syncobj_to_sync_file(device->ws,
7398 part->syncobj, pFd);
7399 if (ret)
7400 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7401
7402 if (part == &fence->temporary) {
7403 radv_destroy_fence_part(device, part);
7404 } else {
7405 device->ws->reset_syncobj(device->ws, part->syncobj);
7406 }
7407 break;
7408 default:
7409 unreachable("Unhandled fence handle type");
7410 }
7411
7412 return VK_SUCCESS;
7413 }
7414
7415 void radv_GetPhysicalDeviceExternalFenceProperties(
7416 VkPhysicalDevice physicalDevice,
7417 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
7418 VkExternalFenceProperties *pExternalFenceProperties)
7419 {
7420 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7421
7422 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7423 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7424 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
7425 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7426 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7427 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
7428 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7429 } else {
7430 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
7431 pExternalFenceProperties->compatibleHandleTypes = 0;
7432 pExternalFenceProperties->externalFenceFeatures = 0;
7433 }
7434 }
7435
7436 VkResult
7437 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
7438 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
7439 const VkAllocationCallbacks* pAllocator,
7440 VkDebugReportCallbackEXT* pCallback)
7441 {
7442 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7443 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
7444 pCreateInfo, pAllocator, &instance->alloc,
7445 pCallback);
7446 }
7447
7448 void
7449 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
7450 VkDebugReportCallbackEXT _callback,
7451 const VkAllocationCallbacks* pAllocator)
7452 {
7453 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7454 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
7455 _callback, pAllocator, &instance->alloc);
7456 }
7457
7458 void
7459 radv_DebugReportMessageEXT(VkInstance _instance,
7460 VkDebugReportFlagsEXT flags,
7461 VkDebugReportObjectTypeEXT objectType,
7462 uint64_t object,
7463 size_t location,
7464 int32_t messageCode,
7465 const char* pLayerPrefix,
7466 const char* pMessage)
7467 {
7468 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7469 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
7470 object, location, messageCode, pLayerPrefix, pMessage);
7471 }
7472
7473 void
7474 radv_GetDeviceGroupPeerMemoryFeatures(
7475 VkDevice device,
7476 uint32_t heapIndex,
7477 uint32_t localDeviceIndex,
7478 uint32_t remoteDeviceIndex,
7479 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
7480 {
7481 assert(localDeviceIndex == remoteDeviceIndex);
7482
7483 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
7484 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
7485 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
7486 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
7487 }
7488
7489 static const VkTimeDomainEXT radv_time_domains[] = {
7490 VK_TIME_DOMAIN_DEVICE_EXT,
7491 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
7492 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
7493 };
7494
7495 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7496 VkPhysicalDevice physicalDevice,
7497 uint32_t *pTimeDomainCount,
7498 VkTimeDomainEXT *pTimeDomains)
7499 {
7500 int d;
7501 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
7502
7503 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
7504 vk_outarray_append(&out, i) {
7505 *i = radv_time_domains[d];
7506 }
7507 }
7508
7509 return vk_outarray_status(&out);
7510 }
7511
7512 static uint64_t
7513 radv_clock_gettime(clockid_t clock_id)
7514 {
7515 struct timespec current;
7516 int ret;
7517
7518 ret = clock_gettime(clock_id, &current);
7519 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
7520 ret = clock_gettime(CLOCK_MONOTONIC, &current);
7521 if (ret < 0)
7522 return 0;
7523
7524 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
7525 }
7526
7527 VkResult radv_GetCalibratedTimestampsEXT(
7528 VkDevice _device,
7529 uint32_t timestampCount,
7530 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
7531 uint64_t *pTimestamps,
7532 uint64_t *pMaxDeviation)
7533 {
7534 RADV_FROM_HANDLE(radv_device, device, _device);
7535 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
7536 int d;
7537 uint64_t begin, end;
7538 uint64_t max_clock_period = 0;
7539
7540 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7541
7542 for (d = 0; d < timestampCount; d++) {
7543 switch (pTimestampInfos[d].timeDomain) {
7544 case VK_TIME_DOMAIN_DEVICE_EXT:
7545 pTimestamps[d] = device->ws->query_value(device->ws,
7546 RADEON_TIMESTAMP);
7547 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
7548 max_clock_period = MAX2(max_clock_period, device_period);
7549 break;
7550 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
7551 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
7552 max_clock_period = MAX2(max_clock_period, 1);
7553 break;
7554
7555 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
7556 pTimestamps[d] = begin;
7557 break;
7558 default:
7559 pTimestamps[d] = 0;
7560 break;
7561 }
7562 }
7563
7564 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7565
7566 /*
7567 * The maximum deviation is the sum of the interval over which we
7568 * perform the sampling and the maximum period of any sampled
7569 * clock. That's because the maximum skew between any two sampled
7570 * clock edges is when the sampled clock with the largest period is
7571 * sampled at the end of that period but right at the beginning of the
7572 * sampling interval and some other clock is sampled right at the
7573 * begining of its sampling period and right at the end of the
7574 * sampling interval. Let's assume the GPU has the longest clock
7575 * period and that the application is sampling GPU and monotonic:
7576 *
7577 * s e
7578 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
7579 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7580 *
7581 * g
7582 * 0 1 2 3
7583 * GPU -----_____-----_____-----_____-----_____
7584 *
7585 * m
7586 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
7587 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7588 *
7589 * Interval <----------------->
7590 * Deviation <-------------------------->
7591 *
7592 * s = read(raw) 2
7593 * g = read(GPU) 1
7594 * m = read(monotonic) 2
7595 * e = read(raw) b
7596 *
7597 * We round the sample interval up by one tick to cover sampling error
7598 * in the interval clock
7599 */
7600
7601 uint64_t sample_interval = end - begin + 1;
7602
7603 *pMaxDeviation = sample_interval + max_clock_period;
7604
7605 return VK_SUCCESS;
7606 }
7607
7608 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
7609 VkPhysicalDevice physicalDevice,
7610 VkSampleCountFlagBits samples,
7611 VkMultisamplePropertiesEXT* pMultisampleProperties)
7612 {
7613 if (samples & (VK_SAMPLE_COUNT_2_BIT |
7614 VK_SAMPLE_COUNT_4_BIT |
7615 VK_SAMPLE_COUNT_8_BIT)) {
7616 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
7617 } else {
7618 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
7619 }
7620 }
7621
7622 VkResult radv_CreatePrivateDataSlotEXT(
7623 VkDevice _device,
7624 const VkPrivateDataSlotCreateInfoEXT* pCreateInfo,
7625 const VkAllocationCallbacks* pAllocator,
7626 VkPrivateDataSlotEXT* pPrivateDataSlot)
7627 {
7628 RADV_FROM_HANDLE(radv_device, device, _device);
7629 return vk_private_data_slot_create(&device->vk, pCreateInfo, pAllocator,
7630 pPrivateDataSlot);
7631 }
7632
7633 void radv_DestroyPrivateDataSlotEXT(
7634 VkDevice _device,
7635 VkPrivateDataSlotEXT privateDataSlot,
7636 const VkAllocationCallbacks* pAllocator)
7637 {
7638 RADV_FROM_HANDLE(radv_device, device, _device);
7639 vk_private_data_slot_destroy(&device->vk, privateDataSlot, pAllocator);
7640 }
7641
7642 VkResult radv_SetPrivateDataEXT(
7643 VkDevice _device,
7644 VkObjectType objectType,
7645 uint64_t objectHandle,
7646 VkPrivateDataSlotEXT privateDataSlot,
7647 uint64_t data)
7648 {
7649 RADV_FROM_HANDLE(radv_device, device, _device);
7650 return vk_object_base_set_private_data(&device->vk, objectType,
7651 objectHandle, privateDataSlot,
7652 data);
7653 }
7654
7655 void radv_GetPrivateDataEXT(
7656 VkDevice _device,
7657 VkObjectType objectType,
7658 uint64_t objectHandle,
7659 VkPrivateDataSlotEXT privateDataSlot,
7660 uint64_t* pData)
7661 {
7662 RADV_FROM_HANDLE(radv_device, device, _device);
7663 vk_object_base_get_private_data(&device->vk, objectType, objectHandle,
7664 privateDataSlot, pData);
7665 }