projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: fix buffer views on SI/CIK.
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "vk_format.h"
30 #include "vk_util.h"
31 #include "radv_radeon_winsys.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
36 static unsigned
37 radv_choose_tiling(struct radv_device *Device,
38 const struct radv_image_create_info *create_info)
39 {
40 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
41
42 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
43 assert(pCreateInfo->samples <= 1);
44 return RADEON_SURF_MODE_LINEAR_ALIGNED;
45 }
46
47 /* Textures with a very small height are recommended to be linear. */
48 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
49 /* Only very thin and long 2D textures should benefit from
50 * linear_aligned. */
51 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
52 return RADEON_SURF_MODE_LINEAR_ALIGNED;
53
54 /* MSAA resources must be 2D tiled. */
55 if (pCreateInfo->samples > 1)
56 return RADEON_SURF_MODE_2D;
57
58 return RADEON_SURF_MODE_2D;
59 }
60 static int
61 radv_init_surface(struct radv_device *device,
62 struct radeon_surf *surface,
63 const struct radv_image_create_info *create_info)
64 {
65 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
66 unsigned array_mode = radv_choose_tiling(device, create_info);
67 const struct vk_format_description *desc =
68 vk_format_description(pCreateInfo->format);
69 bool is_depth, is_stencil, blendable;
70
71 is_depth = vk_format_has_depth(desc);
72 is_stencil = vk_format_has_stencil(desc);
73
74 surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
75 surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
76
77 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(pCreateInfo->format));
78 /* align byte per element on dword */
79 if (surface->bpe == 3) {
80 surface->bpe = 4;
81 }
82 surface->flags = RADEON_SURF_SET(array_mode, MODE);
83
84 switch (pCreateInfo->imageType){
85 case VK_IMAGE_TYPE_1D:
86 if (pCreateInfo->arrayLayers > 1)
87 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
88 else
89 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
90 break;
91 case VK_IMAGE_TYPE_2D:
92 if (pCreateInfo->arrayLayers > 1)
93 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
94 else
95 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
96 break;
97 case VK_IMAGE_TYPE_3D:
98 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
99 break;
100 default:
101 unreachable("unhandled image type");
102 }
103
104 if (is_depth) {
105 surface->flags |= RADEON_SURF_ZBUFFER;
106 }
107
108 if (is_stencil)
109 surface->flags |= RADEON_SURF_SBUFFER;
110
111 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
112 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
113
114 if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
115 VK_IMAGE_USAGE_STORAGE_BIT)) ||
116 (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) ||
117 (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
118 device->physical_device->rad_info.chip_class < VI ||
119 create_info->scanout || (device->debug_flags & RADV_DEBUG_NO_DCC) ||
120 !radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable))
121 surface->flags |= RADEON_SURF_DISABLE_DCC;
122 if (create_info->scanout)
123 surface->flags |= RADEON_SURF_SCANOUT;
124 return 0;
125 }
126 #define ATI_VENDOR_ID 0x1002
127 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
128 {
129 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
130 }
131
132 static inline unsigned
133 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
134 {
135 if (stencil)
136 return image->surface.u.legacy.stencil_tiling_index[level];
137 else
138 return image->surface.u.legacy.tiling_index[level];
139 }
140
141 static unsigned radv_map_swizzle(unsigned swizzle)
142 {
143 switch (swizzle) {
144 case VK_SWIZZLE_Y:
145 return V_008F0C_SQ_SEL_Y;
146 case VK_SWIZZLE_Z:
147 return V_008F0C_SQ_SEL_Z;
148 case VK_SWIZZLE_W:
149 return V_008F0C_SQ_SEL_W;
150 case VK_SWIZZLE_0:
151 return V_008F0C_SQ_SEL_0;
152 case VK_SWIZZLE_1:
153 return V_008F0C_SQ_SEL_1;
154 default: /* VK_SWIZZLE_X */
155 return V_008F0C_SQ_SEL_X;
156 }
157 }
158
159 static void
160 radv_make_buffer_descriptor(struct radv_device *device,
161 struct radv_buffer *buffer,
162 VkFormat vk_format,
163 unsigned offset,
164 unsigned range,
165 uint32_t *state)
166 {
167 const struct vk_format_description *desc;
168 unsigned stride;
169 uint64_t gpu_address = device->ws->buffer_get_va(buffer->bo);
170 uint64_t va = gpu_address + buffer->offset;
171 unsigned num_format, data_format;
172 int first_non_void;
173 desc = vk_format_description(vk_format);
174 first_non_void = vk_format_get_first_non_void_channel(vk_format);
175 stride = desc->block.bits / 8;
176
177 num_format = radv_translate_buffer_numformat(desc, first_non_void);
178 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
179
180 va += offset;
181 state[0] = va;
182 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
183 S_008F04_STRIDE(stride);
184
185 if (device->physical_device->rad_info.chip_class < VI && stride) {
186 range /= stride;
187 }
188
189 state[2] = range;
190 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
191 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
192 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
193 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
194 S_008F0C_NUM_FORMAT(num_format) |
195 S_008F0C_DATA_FORMAT(data_format);
196 }
197
198 static void
199 si_set_mutable_tex_desc_fields(struct radv_device *device,
200 struct radv_image *image,
201 const struct legacy_surf_level *base_level_info,
202 unsigned base_level, unsigned first_level,
203 unsigned block_width, bool is_stencil,
204 uint32_t *state)
205 {
206 uint64_t gpu_address = image->bo ? device->ws->buffer_get_va(image->bo) + image->offset : 0;
207 uint64_t va = gpu_address;
208 unsigned pitch = base_level_info->nblk_x * block_width;
209 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
210 uint64_t meta_va = 0;
211 if (chip_class >= GFX9) {
212 if (is_stencil)
213 va += image->surface.u.gfx9.stencil_offset;
214 else
215 va += image->surface.u.gfx9.surf_offset;
216 } else
217 va += base_level_info->offset;
218
219 state[0] = va >> 8;
220 if (chip_class < GFX9)
221 state[0] |= image->surface.u.legacy.tile_swizzle;
222 state[1] &= C_008F14_BASE_ADDRESS_HI;
223 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
224 state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image, base_level,
225 is_stencil));
226 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
227
228 if (chip_class >= VI) {
229 state[6] &= C_008F28_COMPRESSION_EN;
230 state[7] = 0;
231 if (image->surface.dcc_size && first_level < image->surface.num_dcc_levels) {
232 meta_va = gpu_address + image->dcc_offset;
233 if (chip_class <= VI)
234 meta_va += base_level_info->dcc_offset;
235 state[6] |= S_008F28_COMPRESSION_EN(1);
236 state[7] = meta_va >> 8;
237 if (chip_class < GFX9)
238 state[7] |= image->surface.u.legacy.tile_swizzle;
239 }
240 }
241
242 if (chip_class >= GFX9) {
243 state[3] &= C_008F1C_SW_MODE;
244 state[4] &= C_008F20_PITCH_GFX9;
245
246 if (is_stencil) {
247 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
248 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
249 } else {
250 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode);
251 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.surf.epitch);
252 }
253
254 state[5] &= C_008F24_META_DATA_ADDRESS &
255 C_008F24_META_PIPE_ALIGNED &
256 C_008F24_META_RB_ALIGNED;
257 if (meta_va) {
258 struct gfx9_surf_meta_flags meta;
259
260 if (image->dcc_offset)
261 meta = image->surface.u.gfx9.dcc;
262 else
263 meta = image->surface.u.gfx9.htile;
264
265 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
266 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
267 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
268 }
269 } else {
270 /* SI-CI-VI */
271 unsigned pitch = base_level_info->nblk_x * block_width;
272 unsigned index = si_tile_mode_index(image, base_level, is_stencil);
273
274 state[3] &= C_008F1C_TILING_INDEX;
275 state[3] |= S_008F1C_TILING_INDEX(index);
276 state[4] &= C_008F20_PITCH_GFX6;
277 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
278 }
279 }
280
281 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
282 unsigned nr_layers, unsigned nr_samples, bool is_storage_image)
283 {
284 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
285 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
286 switch (image_type) {
287 case VK_IMAGE_TYPE_1D:
288 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
289 case VK_IMAGE_TYPE_2D:
290 if (nr_samples > 1)
291 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
292 else
293 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
294 case VK_IMAGE_TYPE_3D:
295 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
296 return V_008F1C_SQ_RSRC_IMG_3D;
297 else
298 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
299 default:
300 unreachable("illegale image type");
301 }
302 }
303
304 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
305 {
306 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
307
308 if (swizzle[3] == VK_SWIZZLE_X) {
309 /* For the pre-defined border color values (white, opaque
310 * black, transparent black), the only thing that matters is
311 * that the alpha channel winds up in the correct place
312 * (because the RGB channels are all the same) so either of
313 * these enumerations will work.
314 */
315 if (swizzle[2] == VK_SWIZZLE_Y)
316 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
317 else
318 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
319 } else if (swizzle[0] == VK_SWIZZLE_X) {
320 if (swizzle[1] == VK_SWIZZLE_Y)
321 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
322 else
323 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
324 } else if (swizzle[1] == VK_SWIZZLE_X) {
325 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
326 } else if (swizzle[2] == VK_SWIZZLE_X) {
327 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
328 }
329
330 return bc_swizzle;
331 }
332
333 /**
334 * Build the sampler view descriptor for a texture.
335 */
336 static void
337 si_make_texture_descriptor(struct radv_device *device,
338 struct radv_image *image,
339 bool is_storage_image,
340 VkImageViewType view_type,
341 VkFormat vk_format,
342 const VkComponentMapping *mapping,
343 unsigned first_level, unsigned last_level,
344 unsigned first_layer, unsigned last_layer,
345 unsigned width, unsigned height, unsigned depth,
346 uint32_t *state,
347 uint32_t *fmask_state)
348 {
349 const struct vk_format_description *desc;
350 enum vk_swizzle swizzle[4];
351 int first_non_void;
352 unsigned num_format, data_format, type;
353
354 desc = vk_format_description(vk_format);
355
356 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
357 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
358 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
359 } else {
360 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
361 }
362
363 first_non_void = vk_format_get_first_non_void_channel(vk_format);
364
365 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
366 if (num_format == ~0) {
367 num_format = 0;
368 }
369
370 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
371 if (data_format == ~0) {
372 data_format = 0;
373 }
374
375 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
376 is_storage_image);
377 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
378 height = 1;
379 depth = image->info.array_size;
380 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
381 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
382 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
383 depth = image->info.array_size;
384 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
385 depth = image->info.array_size / 6;
386
387 state[0] = 0;
388 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
389 S_008F14_NUM_FORMAT_GFX6(num_format));
390 state[2] = (S_008F18_WIDTH(width - 1) |
391 S_008F18_HEIGHT(height - 1) |
392 S_008F18_PERF_MOD(4));
393 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
394 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
395 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
396 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
397 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
398 0 : first_level) |
399 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
400 util_logbase2(image->info.samples) :
401 last_level) |
402 S_008F1C_TYPE(type));
403 state[4] = 0;
404 state[5] = S_008F24_BASE_ARRAY(first_layer);
405 state[6] = 0;
406 state[7] = 0;
407
408 if (device->physical_device->rad_info.chip_class >= GFX9) {
409 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
410
411 /* Depth is the the last accessible layer on Gfx9.
412 * The hw doesn't need to know the total number of layers.
413 */
414 if (type == V_008F1C_SQ_RSRC_IMG_3D)
415 state[4] |= S_008F20_DEPTH(depth - 1);
416 else
417 state[4] |= S_008F20_DEPTH(last_layer);
418
419 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
420 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
421 util_logbase2(image->info.samples) :
422 last_level);
423 } else {
424 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
425 state[4] |= S_008F20_DEPTH(depth - 1);
426 state[5] |= S_008F24_LAST_ARRAY(last_layer);
427 }
428 if (image->dcc_offset) {
429 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
430
431 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
432 } else {
433 /* The last dword is unused by hw. The shader uses it to clear
434 * bits in the first dword of sampler state.
435 */
436 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
437 if (first_level == last_level)
438 state[7] = C_008F30_MAX_ANISO_RATIO;
439 else
440 state[7] = 0xffffffff;
441 }
442 }
443
444 /* Initialize the sampler view for FMASK. */
445 if (image->fmask.size) {
446 uint32_t fmask_format, num_format;
447 uint64_t gpu_address = device->ws->buffer_get_va(image->bo);
448 uint64_t va;
449
450 va = gpu_address + image->offset + image->fmask.offset;
451
452 if (device->physical_device->rad_info.chip_class >= GFX9) {
453 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
454 switch (image->info.samples) {
455 case 2:
456 num_format = V_008F14_IMG_FMASK_8_2_2;
457 break;
458 case 4:
459 num_format = V_008F14_IMG_FMASK_8_4_4;
460 break;
461 case 8:
462 num_format = V_008F14_IMG_FMASK_32_8_8;
463 break;
464 default:
465 unreachable("invalid nr_samples");
466 }
467 } else {
468 switch (image->info.samples) {
469 case 2:
470 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
471 break;
472 case 4:
473 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
474 break;
475 case 8:
476 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
477 break;
478 default:
479 assert(0);
480 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
481 }
482 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
483 }
484
485 fmask_state[0] = va >> 8;
486 if (device->physical_device->rad_info.chip_class < GFX9)
487 fmask_state[0] |= image->surface.u.legacy.tile_swizzle;
488 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
489 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
490 S_008F14_NUM_FORMAT_GFX6(num_format);
491 fmask_state[2] = S_008F18_WIDTH(width - 1) |
492 S_008F18_HEIGHT(height - 1);
493 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
494 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
495 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
496 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
497 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false));
498 fmask_state[4] = 0;
499 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
500 fmask_state[6] = 0;
501 fmask_state[7] = 0;
502
503 if (device->physical_device->rad_info.chip_class >= GFX9) {
504 fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode);
505 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
506 S_008F20_PITCH_GFX9(image->surface.u.gfx9.fmask.epitch);
507 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->surface.u.gfx9.cmask.pipe_aligned) |
508 S_008F24_META_RB_ALIGNED(image->surface.u.gfx9.cmask.rb_aligned);
509 } else {
510 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
511 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
512 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
513 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
514 }
515 } else if (fmask_state)
516 memset(fmask_state, 0, 8 * 4);
517 }
518
519 static void
520 radv_query_opaque_metadata(struct radv_device *device,
521 struct radv_image *image,
522 struct radeon_bo_metadata *md)
523 {
524 static const VkComponentMapping fixedmapping;
525 uint32_t desc[8], i;
526
527 /* Metadata image format format version 1:
528 * [0] = 1 (metadata format identifier)
529 * [1] = (VENDOR_ID << 16) | PCI_ID
530 * [2:9] = image descriptor for the whole resource
531 * [2] is always 0, because the base address is cleared
532 * [9] is the DCC offset bits [39:8] from the beginning of
533 * the buffer
534 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
535 */
536 md->metadata[0] = 1; /* metadata image format version 1 */
537
538 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
539 md->metadata[1] = si_get_bo_metadata_word1(device);
540
541
542 si_make_texture_descriptor(device, image, false,
543 (VkImageViewType)image->type, image->vk_format,
544 &fixedmapping, 0, image->info.levels - 1, 0,
545 image->info.array_size,
546 image->info.width, image->info.height,
547 image->info.depth,
548 desc, NULL);
549
550 si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
551 image->surface.blk_w, false, desc);
552
553 /* Clear the base address and set the relative DCC offset. */
554 desc[0] = 0;
555 desc[1] &= C_008F14_BASE_ADDRESS_HI;
556 desc[7] = image->dcc_offset >> 8;
557
558 /* Dwords [2:9] contain the image descriptor. */
559 memcpy(&md->metadata[2], desc, sizeof(desc));
560
561 /* Dwords [10:..] contain the mipmap level offsets. */
562 for (i = 0; i <= image->info.levels - 1; i++)
563 md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
564
565 md->size_metadata = (11 + image->info.levels - 1) * 4;
566 }
567
568 void
569 radv_init_metadata(struct radv_device *device,
570 struct radv_image *image,
571 struct radeon_bo_metadata *metadata)
572 {
573 struct radeon_surf *surface = &image->surface;
574
575 memset(metadata, 0, sizeof(*metadata));
576
577 if (device->physical_device->rad_info.chip_class >= GFX9) {
578 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
579 } else {
580 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
581 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
582 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
583 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
584 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
585 metadata->u.legacy.bankw = surface->u.legacy.bankw;
586 metadata->u.legacy.bankh = surface->u.legacy.bankh;
587 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
588 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
589 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
590 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
591 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
592 }
593 radv_query_opaque_metadata(device, image, metadata);
594 }
595
596 /* The number of samples can be specified independently of the texture. */
597 static void
598 radv_image_get_fmask_info(struct radv_device *device,
599 struct radv_image *image,
600 unsigned nr_samples,
601 struct radv_fmask_info *out)
602 {
603 /* FMASK is allocated like an ordinary texture. */
604 struct radeon_surf fmask = {};
605 struct ac_surf_info info = image->info;
606 memset(out, 0, sizeof(*out));
607
608 if (device->physical_device->rad_info.chip_class >= GFX9) {
609 out->alignment = image->surface.u.gfx9.fmask_alignment;
610 out->size = image->surface.u.gfx9.fmask_size;
611 return;
612 }
613
614 fmask.blk_w = image->surface.blk_w;
615 fmask.blk_h = image->surface.blk_h;
616 info.samples = 1;
617 fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
618
619 /* Force 2D tiling if it wasn't set. This may occur when creating
620 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
621 * destination buffer must have an FMASK too. */
622 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
623 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
624
625 switch (nr_samples) {
626 case 2:
627 case 4:
628 fmask.bpe = 1;
629 break;
630 case 8:
631 fmask.bpe = 4;
632 break;
633 default:
634 return;
635 }
636
637 device->ws->surface_init(device->ws, &info, &fmask);
638 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
639
640 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
641 if (out->slice_tile_max)
642 out->slice_tile_max -= 1;
643
644 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
645 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
646 out->bank_height = fmask.u.legacy.bankh;
647 out->alignment = MAX2(256, fmask.surf_alignment);
648 out->size = fmask.surf_size;
649 }
650
651 static void
652 radv_image_alloc_fmask(struct radv_device *device,
653 struct radv_image *image)
654 {
655 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
656
657 image->fmask.offset = align64(image->size, image->fmask.alignment);
658 image->size = image->fmask.offset + image->fmask.size;
659 image->alignment = MAX2(image->alignment, image->fmask.alignment);
660 }
661
662 static void
663 radv_image_get_cmask_info(struct radv_device *device,
664 struct radv_image *image,
665 struct radv_cmask_info *out)
666 {
667 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
668 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
669 unsigned cl_width, cl_height;
670
671 if (device->physical_device->rad_info.chip_class >= GFX9) {
672 out->alignment = image->surface.u.gfx9.cmask_alignment;
673 out->size = image->surface.u.gfx9.cmask_size;
674 return;
675 }
676
677 switch (num_pipes) {
678 case 2:
679 cl_width = 32;
680 cl_height = 16;
681 break;
682 case 4:
683 cl_width = 32;
684 cl_height = 32;
685 break;
686 case 8:
687 cl_width = 64;
688 cl_height = 32;
689 break;
690 case 16: /* Hawaii */
691 cl_width = 64;
692 cl_height = 64;
693 break;
694 default:
695 assert(0);
696 return;
697 }
698
699 unsigned base_align = num_pipes * pipe_interleave_bytes;
700
701 unsigned width = align(image->info.width, cl_width*8);
702 unsigned height = align(image->info.height, cl_height*8);
703 unsigned slice_elements = (width * height) / (8*8);
704
705 /* Each element of CMASK is a nibble. */
706 unsigned slice_bytes = slice_elements / 2;
707
708 out->slice_tile_max = (width * height) / (128*128);
709 if (out->slice_tile_max)
710 out->slice_tile_max -= 1;
711
712 out->alignment = MAX2(256, base_align);
713 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
714 align(slice_bytes, base_align);
715 }
716
717 static void
718 radv_image_alloc_cmask(struct radv_device *device,
719 struct radv_image *image)
720 {
721 uint32_t clear_value_size = 0;
722 radv_image_get_cmask_info(device, image, &image->cmask);
723
724 image->cmask.offset = align64(image->size, image->cmask.alignment);
725 /* + 8 for storing the clear values */
726 if (!image->clear_value_offset) {
727 image->clear_value_offset = image->cmask.offset + image->cmask.size;
728 clear_value_size = 8;
729 }
730 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
731 image->alignment = MAX2(image->alignment, image->cmask.alignment);
732 }
733
734 static void
735 radv_image_alloc_dcc(struct radv_device *device,
736 struct radv_image *image)
737 {
738 image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
739 /* + 16 for storing the clear values + dcc pred */
740 image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
741 image->dcc_pred_offset = image->clear_value_offset + 8;
742 image->size = image->dcc_offset + image->surface.dcc_size + 16;
743 image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
744 }
745
746 static void
747 radv_image_alloc_htile(struct radv_device *device,
748 struct radv_image *image)
749 {
750 if ((device->debug_flags & RADV_DEBUG_NO_HIZ) || image->info.levels > 1) {
751 image->surface.htile_size = 0;
752 return;
753 }
754
755 image->htile_offset = align64(image->size, image->surface.htile_alignment);
756
757 /* + 8 for storing the clear values */
758 image->clear_value_offset = image->htile_offset + image->surface.htile_size;
759 image->size = image->clear_value_offset + 8;
760 image->alignment = align64(image->alignment, image->surface.htile_alignment);
761 }
762
763 VkResult
764 radv_image_create(VkDevice _device,
765 const struct radv_image_create_info *create_info,
766 const VkAllocationCallbacks* alloc,
767 VkImage *pImage)
768 {
769 RADV_FROM_HANDLE(radv_device, device, _device);
770 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
771 struct radv_image *image = NULL;
772 bool can_cmask_dcc = false;
773 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
774
775 radv_assert(pCreateInfo->mipLevels > 0);
776 radv_assert(pCreateInfo->arrayLayers > 0);
777 radv_assert(pCreateInfo->samples > 0);
778 radv_assert(pCreateInfo->extent.width > 0);
779 radv_assert(pCreateInfo->extent.height > 0);
780 radv_assert(pCreateInfo->extent.depth > 0);
781
782 image = vk_alloc2(&device->alloc, alloc, sizeof(*image), 8,
783 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
784 if (!image)
785 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
786
787 memset(image, 0, sizeof(*image));
788 image->type = pCreateInfo->imageType;
789 image->info.width = pCreateInfo->extent.width;
790 image->info.height = pCreateInfo->extent.height;
791 image->info.depth = pCreateInfo->extent.depth;
792 image->info.samples = pCreateInfo->samples;
793 image->info.array_size = pCreateInfo->arrayLayers;
794 image->info.levels = pCreateInfo->mipLevels;
795
796 image->vk_format = pCreateInfo->format;
797 image->tiling = pCreateInfo->tiling;
798 image->usage = pCreateInfo->usage;
799 image->flags = pCreateInfo->flags;
800
801 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
802 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
803 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
804 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHR)
805 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
806 else
807 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
808 }
809
810 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
811 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
812 if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
813 image->info.surf_index = p_atomic_inc_return(&device->image_mrt_offset_counter) - 1;
814 }
815
816 radv_init_surface(device, &image->surface, create_info);
817
818 device->ws->surface_init(device->ws, &image->info, &image->surface);
819
820 image->size = image->surface.surf_size;
821 image->alignment = image->surface.surf_alignment;
822
823 if (image->exclusive || image->queue_family_mask == 1)
824 can_cmask_dcc = true;
825
826 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
827 image->surface.dcc_size && can_cmask_dcc)
828 radv_image_alloc_dcc(device, image);
829 else
830 image->surface.dcc_size = 0;
831
832 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
833 pCreateInfo->mipLevels == 1 &&
834 !image->surface.dcc_size && image->info.depth == 1 && can_cmask_dcc)
835 radv_image_alloc_cmask(device, image);
836 if (image->info.samples > 1 && vk_format_is_color(pCreateInfo->format)) {
837 radv_image_alloc_fmask(device, image);
838 } else if (vk_format_is_depth(pCreateInfo->format)) {
839
840 radv_image_alloc_htile(device, image);
841 }
842
843 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
844 image->alignment = MAX2(image->alignment, 4096);
845 image->size = align64(image->size, image->alignment);
846 image->offset = 0;
847
848 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
849 0, RADEON_FLAG_VIRTUAL);
850 if (!image->bo) {
851 vk_free2(&device->alloc, alloc, image);
852 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
853 }
854 }
855
856 *pImage = radv_image_to_handle(image);
857
858 return VK_SUCCESS;
859 }
860
861 static void
862 radv_image_view_make_descriptor(struct radv_image_view *iview,
863 struct radv_device *device,
864 const VkImageViewCreateInfo* pCreateInfo,
865 bool is_storage_image)
866 {
867 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
868 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
869 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
870 uint32_t blk_w;
871 uint32_t *descriptor;
872 uint32_t *fmask_descriptor;
873
874 if (is_storage_image) {
875 descriptor = iview->storage_descriptor;
876 fmask_descriptor = iview->storage_fmask_descriptor;
877 } else {
878 descriptor = iview->descriptor;
879 fmask_descriptor = iview->fmask_descriptor;
880 }
881
882 assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
883 blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
884
885 si_make_texture_descriptor(device, image, is_storage_image,
886 iview->type,
887 iview->vk_format,
888 &pCreateInfo->components,
889 0, radv_get_levelCount(image, range) - 1,
890 range->baseArrayLayer,
891 range->baseArrayLayer + radv_get_layerCount(image, range) - 1,
892 iview->extent.width,
893 iview->extent.height,
894 iview->extent.depth,
895 descriptor,
896 fmask_descriptor);
897 si_set_mutable_tex_desc_fields(device, image,
898 is_stencil ? &image->surface.u.legacy.stencil_level[range->baseMipLevel]
899 : &image->surface.u.legacy.level[range->baseMipLevel],
900 range->baseMipLevel,
901 range->baseMipLevel,
902 blk_w, is_stencil, descriptor);
903 }
904
905 void
906 radv_image_view_init(struct radv_image_view *iview,
907 struct radv_device *device,
908 const VkImageViewCreateInfo* pCreateInfo)
909 {
910 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
911 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
912
913 switch (image->type) {
914 case VK_IMAGE_TYPE_1D:
915 case VK_IMAGE_TYPE_2D:
916 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
917 break;
918 case VK_IMAGE_TYPE_3D:
919 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
920 <= radv_minify(image->info.depth, range->baseMipLevel));
921 break;
922 default:
923 unreachable("bad VkImageType");
924 }
925 iview->image = image;
926 iview->bo = image->bo;
927 iview->type = pCreateInfo->viewType;
928 iview->vk_format = pCreateInfo->format;
929 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
930
931 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
932 iview->vk_format = vk_format_stencil_only(iview->vk_format);
933 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
934 iview->vk_format = vk_format_depth_only(iview->vk_format);
935 }
936
937 iview->extent = (VkExtent3D) {
938 .width = radv_minify(image->info.width , range->baseMipLevel),
939 .height = radv_minify(image->info.height, range->baseMipLevel),
940 .depth = radv_minify(image->info.depth , range->baseMipLevel),
941 };
942
943 iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format),
944 vk_format_get_blockwidth(image->vk_format));
945 iview->extent.height = round_up_u32(iview->extent.height * vk_format_get_blockheight(iview->vk_format),
946 vk_format_get_blockheight(image->vk_format));
947
948 iview->base_layer = range->baseArrayLayer;
949 iview->layer_count = radv_get_layerCount(image, range);
950 iview->base_mip = range->baseMipLevel;
951
952 radv_image_view_make_descriptor(iview, device, pCreateInfo, false);
953 radv_image_view_make_descriptor(iview, device, pCreateInfo, true);
954 }
955
956 bool radv_layout_has_htile(const struct radv_image *image,
957 VkImageLayout layout,
958 unsigned queue_mask)
959 {
960 return image->surface.htile_size &&
961 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
962 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
963 queue_mask == (1u << RADV_QUEUE_GENERAL);
964 }
965
966 bool radv_layout_is_htile_compressed(const struct radv_image *image,
967 VkImageLayout layout,
968 unsigned queue_mask)
969 {
970 return image->surface.htile_size &&
971 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
972 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
973 queue_mask == (1u << RADV_QUEUE_GENERAL);
974 }
975
976 bool radv_layout_can_fast_clear(const struct radv_image *image,
977 VkImageLayout layout,
978 unsigned queue_mask)
979 {
980 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
981 queue_mask == (1u << RADV_QUEUE_GENERAL);
982 }
983
984
985 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
986 {
987 if (!image->exclusive)
988 return image->queue_family_mask;
989 if (family == VK_QUEUE_FAMILY_EXTERNAL_KHR)
990 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
991 if (family == VK_QUEUE_FAMILY_IGNORED)
992 return 1u << queue_family;
993 return 1u << family;
994 }
995
996 VkResult
997 radv_CreateImage(VkDevice device,
998 const VkImageCreateInfo *pCreateInfo,
999 const VkAllocationCallbacks *pAllocator,
1000 VkImage *pImage)
1001 {
1002 return radv_image_create(device,
1003 &(struct radv_image_create_info) {
1004 .vk_info = pCreateInfo,
1005 .scanout = false,
1006 },
1007 pAllocator,
1008 pImage);
1009 }
1010
1011 void
1012 radv_DestroyImage(VkDevice _device, VkImage _image,
1013 const VkAllocationCallbacks *pAllocator)
1014 {
1015 RADV_FROM_HANDLE(radv_device, device, _device);
1016 RADV_FROM_HANDLE(radv_image, image, _image);
1017
1018 if (!image)
1019 return;
1020
1021 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1022 device->ws->buffer_destroy(image->bo);
1023
1024 vk_free2(&device->alloc, pAllocator, image);
1025 }
1026
1027 void radv_GetImageSubresourceLayout(
1028 VkDevice device,
1029 VkImage _image,
1030 const VkImageSubresource* pSubresource,
1031 VkSubresourceLayout* pLayout)
1032 {
1033 RADV_FROM_HANDLE(radv_image, image, _image);
1034 int level = pSubresource->mipLevel;
1035 int layer = pSubresource->arrayLayer;
1036 struct radeon_surf *surface = &image->surface;
1037
1038 pLayout->offset = surface->u.legacy.level[level].offset + surface->u.legacy.level[level].slice_size * layer;
1039 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1040 pLayout->arrayPitch = surface->u.legacy.level[level].slice_size;
1041 pLayout->depthPitch = surface->u.legacy.level[level].slice_size;
1042 pLayout->size = surface->u.legacy.level[level].slice_size;
1043 if (image->type == VK_IMAGE_TYPE_3D)
1044 pLayout->size *= u_minify(image->info.depth, level);
1045 }
1046
1047
1048 VkResult
1049 radv_CreateImageView(VkDevice _device,
1050 const VkImageViewCreateInfo *pCreateInfo,
1051 const VkAllocationCallbacks *pAllocator,
1052 VkImageView *pView)
1053 {
1054 RADV_FROM_HANDLE(radv_device, device, _device);
1055 struct radv_image_view *view;
1056
1057 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1058 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1059 if (view == NULL)
1060 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1061
1062 radv_image_view_init(view, device, pCreateInfo);
1063
1064 *pView = radv_image_view_to_handle(view);
1065
1066 return VK_SUCCESS;
1067 }
1068
1069 void
1070 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1071 const VkAllocationCallbacks *pAllocator)
1072 {
1073 RADV_FROM_HANDLE(radv_device, device, _device);
1074 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1075
1076 if (!iview)
1077 return;
1078 vk_free2(&device->alloc, pAllocator, iview);
1079 }
1080
1081 void radv_buffer_view_init(struct radv_buffer_view *view,
1082 struct radv_device *device,
1083 const VkBufferViewCreateInfo* pCreateInfo,
1084 struct radv_cmd_buffer *cmd_buffer)
1085 {
1086 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1087
1088 view->bo = buffer->bo;
1089 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1090 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1091 view->vk_format = pCreateInfo->format;
1092
1093 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1094 pCreateInfo->offset, view->range, view->state);
1095 }
1096
1097 VkResult
1098 radv_CreateBufferView(VkDevice _device,
1099 const VkBufferViewCreateInfo *pCreateInfo,
1100 const VkAllocationCallbacks *pAllocator,
1101 VkBufferView *pView)
1102 {
1103 RADV_FROM_HANDLE(radv_device, device, _device);
1104 struct radv_buffer_view *view;
1105
1106 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1107 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1108 if (!view)
1109 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1110
1111 radv_buffer_view_init(view, device, pCreateInfo, NULL);
1112
1113 *pView = radv_buffer_view_to_handle(view);
1114
1115 return VK_SUCCESS;
1116 }
1117
1118 void
1119 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1120 const VkAllocationCallbacks *pAllocator)
1121 {
1122 RADV_FROM_HANDLE(radv_device, device, _device);
1123 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1124
1125 if (!view)
1126 return;
1127
1128 vk_free2(&device->alloc, pAllocator, view);
1129 }