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dd2c46ae4179479497292af947c4bb74ba0c98b4
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "util/debug.h"
36 #include "util/u_atomic.h"
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= VI) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66
67 static bool
68 radv_use_tc_compat_htile_for_image(struct radv_device *device,
69 const VkImageCreateInfo *pCreateInfo)
70 {
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device->physical_device->rad_info.chip_class < VI)
73 return false;
74
75 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
76 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
77 return false;
78
79 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
80 return false;
81
82 if (pCreateInfo->mipLevels > 1)
83 return false;
84
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now */
87 if (pCreateInfo->samples >= 2 &&
88 pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
89 return false;
90
91 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
92 * supports 32-bit. Though, it's possible to enable TC-compat for
93 * 16-bit depth surfaces if no Z planes are compressed.
94 */
95 if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
96 pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
97 pCreateInfo->format != VK_FORMAT_D16_UNORM)
98 return false;
99
100 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
101 const struct VkImageFormatListCreateInfoKHR *format_list =
102 (const struct VkImageFormatListCreateInfoKHR *)
103 vk_find_struct_const(pCreateInfo->pNext,
104 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
105
106 /* We have to ignore the existence of the list if viewFormatCount = 0 */
107 if (format_list && format_list->viewFormatCount) {
108 /* compatibility is transitive, so we only need to check
109 * one format with everything else.
110 */
111 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
112 if (pCreateInfo->format != format_list->pViewFormats[i])
113 return false;
114 }
115 } else {
116 return false;
117 }
118 }
119
120 return true;
121 }
122
123 static bool
124 radv_use_dcc_for_image(struct radv_device *device,
125 const struct radv_image *image,
126 const struct radv_image_create_info *create_info,
127 const VkImageCreateInfo *pCreateInfo)
128 {
129 bool dcc_compatible_formats;
130 bool blendable;
131
132 /* DCC (Delta Color Compression) is only available for GFX8+. */
133 if (device->physical_device->rad_info.chip_class < VI)
134 return false;
135
136 if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
137 return false;
138
139 /* FIXME: DCC is broken for shareable images starting with GFX9 */
140 if (device->physical_device->rad_info.chip_class >= GFX9 &&
141 image->shareable)
142 return false;
143
144 /* TODO: Enable DCC for storage images. */
145 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
146 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
147 return false;
148
149 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
150 return false;
151
152 if (vk_format_is_subsampled(pCreateInfo->format) ||
153 vk_format_get_plane_count(pCreateInfo->format) > 1)
154 return false;
155
156 /* TODO: Enable DCC for mipmaps and array layers. */
157 if (pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1)
158 return false;
159
160 if (create_info->scanout)
161 return false;
162
163 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
164 * 2x can be enabled with an option.
165 */
166 if (pCreateInfo->samples > 2 ||
167 (pCreateInfo->samples == 2 &&
168 !device->physical_device->dcc_msaa_allowed))
169 return false;
170
171 /* Determine if the formats are DCC compatible. */
172 dcc_compatible_formats =
173 radv_is_colorbuffer_format_supported(pCreateInfo->format,
174 &blendable);
175
176 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
177 const struct VkImageFormatListCreateInfoKHR *format_list =
178 (const struct VkImageFormatListCreateInfoKHR *)
179 vk_find_struct_const(pCreateInfo->pNext,
180 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
181
182 /* We have to ignore the existence of the list if viewFormatCount = 0 */
183 if (format_list && format_list->viewFormatCount) {
184 /* compatibility is transitive, so we only need to check
185 * one format with everything else. */
186 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
187 if (!radv_dcc_formats_compatible(pCreateInfo->format,
188 format_list->pViewFormats[i]))
189 dcc_compatible_formats = false;
190 }
191 } else {
192 dcc_compatible_formats = false;
193 }
194 }
195
196 if (!dcc_compatible_formats)
197 return false;
198
199 return true;
200 }
201
202 static int
203 radv_init_surface(struct radv_device *device,
204 const struct radv_image *image,
205 struct radeon_surf *surface,
206 unsigned plane_id,
207 const struct radv_image_create_info *create_info)
208 {
209 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
210 unsigned array_mode = radv_choose_tiling(device, create_info);
211 VkFormat format = vk_format_get_plane_format(pCreateInfo->format, plane_id);
212 const struct vk_format_description *desc = vk_format_description(format);
213 bool is_depth, is_stencil;
214
215 is_depth = vk_format_has_depth(desc);
216 is_stencil = vk_format_has_stencil(desc);
217
218 surface->blk_w = vk_format_get_blockwidth(format);
219 surface->blk_h = vk_format_get_blockheight(format);
220
221 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(format));
222 /* align byte per element on dword */
223 if (surface->bpe == 3) {
224 surface->bpe = 4;
225 }
226 surface->flags = RADEON_SURF_SET(array_mode, MODE);
227
228 switch (pCreateInfo->imageType){
229 case VK_IMAGE_TYPE_1D:
230 if (pCreateInfo->arrayLayers > 1)
231 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
232 else
233 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
234 break;
235 case VK_IMAGE_TYPE_2D:
236 if (pCreateInfo->arrayLayers > 1)
237 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
238 else
239 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
240 break;
241 case VK_IMAGE_TYPE_3D:
242 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
243 break;
244 default:
245 unreachable("unhandled image type");
246 }
247
248 if (is_depth) {
249 surface->flags |= RADEON_SURF_ZBUFFER;
250 if (radv_use_tc_compat_htile_for_image(device, pCreateInfo))
251 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
252 }
253
254 if (is_stencil)
255 surface->flags |= RADEON_SURF_SBUFFER;
256
257 if (device->physical_device->rad_info.chip_class >= GFX9 &&
258 pCreateInfo->imageType == VK_IMAGE_TYPE_3D &&
259 vk_format_get_blocksizebits(pCreateInfo->format) == 128 &&
260 vk_format_is_compressed(pCreateInfo->format))
261 surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
262
263 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
264
265 if (!radv_use_dcc_for_image(device, image, create_info, pCreateInfo))
266 surface->flags |= RADEON_SURF_DISABLE_DCC;
267
268 if (create_info->scanout)
269 surface->flags |= RADEON_SURF_SCANOUT;
270 return 0;
271 }
272
273 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
274 {
275 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
276 }
277
278 static inline unsigned
279 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
280 {
281 if (stencil)
282 return plane->surface.u.legacy.stencil_tiling_index[level];
283 else
284 return plane->surface.u.legacy.tiling_index[level];
285 }
286
287 static unsigned radv_map_swizzle(unsigned swizzle)
288 {
289 switch (swizzle) {
290 case VK_SWIZZLE_Y:
291 return V_008F0C_SQ_SEL_Y;
292 case VK_SWIZZLE_Z:
293 return V_008F0C_SQ_SEL_Z;
294 case VK_SWIZZLE_W:
295 return V_008F0C_SQ_SEL_W;
296 case VK_SWIZZLE_0:
297 return V_008F0C_SQ_SEL_0;
298 case VK_SWIZZLE_1:
299 return V_008F0C_SQ_SEL_1;
300 default: /* VK_SWIZZLE_X */
301 return V_008F0C_SQ_SEL_X;
302 }
303 }
304
305 static void
306 radv_make_buffer_descriptor(struct radv_device *device,
307 struct radv_buffer *buffer,
308 VkFormat vk_format,
309 unsigned offset,
310 unsigned range,
311 uint32_t *state)
312 {
313 const struct vk_format_description *desc;
314 unsigned stride;
315 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
316 uint64_t va = gpu_address + buffer->offset;
317 unsigned num_format, data_format;
318 int first_non_void;
319 desc = vk_format_description(vk_format);
320 first_non_void = vk_format_get_first_non_void_channel(vk_format);
321 stride = desc->block.bits / 8;
322
323 num_format = radv_translate_buffer_numformat(desc, first_non_void);
324 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
325
326 va += offset;
327 state[0] = va;
328 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
329 S_008F04_STRIDE(stride);
330
331 if (device->physical_device->rad_info.chip_class != VI && stride) {
332 range /= stride;
333 }
334
335 state[2] = range;
336 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
337 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
338 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
339 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
340 S_008F0C_NUM_FORMAT(num_format) |
341 S_008F0C_DATA_FORMAT(data_format);
342 }
343
344 static void
345 si_set_mutable_tex_desc_fields(struct radv_device *device,
346 struct radv_image *image,
347 const struct legacy_surf_level *base_level_info,
348 unsigned base_level, unsigned first_level,
349 unsigned block_width, bool is_stencil,
350 bool is_storage_image, uint32_t *state)
351 {
352 struct radv_image_plane *plane = &image->planes[0];
353 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
354 uint64_t va = gpu_address + plane->offset;
355 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
356 uint64_t meta_va = 0;
357 if (chip_class >= GFX9) {
358 if (is_stencil)
359 va += plane->surface.u.gfx9.stencil_offset;
360 else
361 va += plane->surface.u.gfx9.surf_offset;
362 } else
363 va += base_level_info->offset;
364
365 state[0] = va >> 8;
366 if (chip_class >= GFX9 ||
367 base_level_info->mode == RADEON_SURF_MODE_2D)
368 state[0] |= plane->surface.tile_swizzle;
369 state[1] &= C_008F14_BASE_ADDRESS_HI;
370 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
371
372 if (chip_class >= VI) {
373 state[6] &= C_008F28_COMPRESSION_EN;
374 state[7] = 0;
375 if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
376 meta_va = gpu_address + image->dcc_offset;
377 if (chip_class <= VI)
378 meta_va += base_level_info->dcc_offset;
379 } else if (!is_storage_image &&
380 radv_image_is_tc_compat_htile(image)) {
381 meta_va = gpu_address + image->htile_offset;
382 }
383
384 if (meta_va) {
385 state[6] |= S_008F28_COMPRESSION_EN(1);
386 state[7] = meta_va >> 8;
387 state[7] |= plane->surface.tile_swizzle;
388 }
389 }
390
391 if (chip_class >= GFX9) {
392 state[3] &= C_008F1C_SW_MODE;
393 state[4] &= C_008F20_PITCH_GFX9;
394
395 if (is_stencil) {
396 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
397 state[4] |= S_008F20_PITCH_GFX9(plane->surface.u.gfx9.stencil.epitch);
398 } else {
399 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
400 state[4] |= S_008F20_PITCH_GFX9(plane->surface.u.gfx9.surf.epitch);
401 }
402
403 state[5] &= C_008F24_META_DATA_ADDRESS &
404 C_008F24_META_PIPE_ALIGNED &
405 C_008F24_META_RB_ALIGNED;
406 if (meta_va) {
407 struct gfx9_surf_meta_flags meta;
408
409 if (image->dcc_offset)
410 meta = plane->surface.u.gfx9.dcc;
411 else
412 meta = plane->surface.u.gfx9.htile;
413
414 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
415 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
416 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
417 }
418 } else {
419 /* SI-CI-VI */
420 unsigned pitch = base_level_info->nblk_x * block_width;
421 unsigned index = si_tile_mode_index(plane, base_level, is_stencil);
422
423 state[3] &= C_008F1C_TILING_INDEX;
424 state[3] |= S_008F1C_TILING_INDEX(index);
425 state[4] &= C_008F20_PITCH_GFX6;
426 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
427 }
428 }
429
430 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
431 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
432 {
433 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
434 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
435
436 /* GFX9 allocates 1D textures as 2D. */
437 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
438 image_type = VK_IMAGE_TYPE_2D;
439 switch (image_type) {
440 case VK_IMAGE_TYPE_1D:
441 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
442 case VK_IMAGE_TYPE_2D:
443 if (nr_samples > 1)
444 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
445 else
446 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
447 case VK_IMAGE_TYPE_3D:
448 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
449 return V_008F1C_SQ_RSRC_IMG_3D;
450 else
451 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
452 default:
453 unreachable("illegal image type");
454 }
455 }
456
457 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
458 {
459 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
460
461 if (swizzle[3] == VK_SWIZZLE_X) {
462 /* For the pre-defined border color values (white, opaque
463 * black, transparent black), the only thing that matters is
464 * that the alpha channel winds up in the correct place
465 * (because the RGB channels are all the same) so either of
466 * these enumerations will work.
467 */
468 if (swizzle[2] == VK_SWIZZLE_Y)
469 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
470 else
471 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
472 } else if (swizzle[0] == VK_SWIZZLE_X) {
473 if (swizzle[1] == VK_SWIZZLE_Y)
474 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
475 else
476 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
477 } else if (swizzle[1] == VK_SWIZZLE_X) {
478 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
479 } else if (swizzle[2] == VK_SWIZZLE_X) {
480 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
481 }
482
483 return bc_swizzle;
484 }
485
486 /**
487 * Build the sampler view descriptor for a texture.
488 */
489 static void
490 si_make_texture_descriptor(struct radv_device *device,
491 struct radv_image *image,
492 bool is_storage_image,
493 VkImageViewType view_type,
494 VkFormat vk_format,
495 const VkComponentMapping *mapping,
496 unsigned first_level, unsigned last_level,
497 unsigned first_layer, unsigned last_layer,
498 unsigned width, unsigned height, unsigned depth,
499 uint32_t *state,
500 uint32_t *fmask_state)
501 {
502 const struct vk_format_description *desc;
503 enum vk_swizzle swizzle[4];
504 int first_non_void;
505 unsigned num_format, data_format, type;
506
507 desc = vk_format_description(vk_format);
508
509 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
510 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
511 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
512 } else {
513 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
514 }
515
516 first_non_void = vk_format_get_first_non_void_channel(vk_format);
517
518 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
519 if (num_format == ~0) {
520 num_format = 0;
521 }
522
523 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
524 if (data_format == ~0) {
525 data_format = 0;
526 }
527
528 /* S8 with either Z16 or Z32 HTILE need a special format. */
529 if (device->physical_device->rad_info.chip_class >= GFX9 &&
530 vk_format == VK_FORMAT_S8_UINT &&
531 radv_image_is_tc_compat_htile(image)) {
532 if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
533 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
534 else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
535 data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
536 }
537 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
538 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
539 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
540 height = 1;
541 depth = image->info.array_size;
542 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
543 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
544 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
545 depth = image->info.array_size;
546 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
547 depth = image->info.array_size / 6;
548
549 state[0] = 0;
550 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
551 S_008F14_NUM_FORMAT_GFX6(num_format));
552 state[2] = (S_008F18_WIDTH(width - 1) |
553 S_008F18_HEIGHT(height - 1) |
554 S_008F18_PERF_MOD(4));
555 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
556 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
557 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
558 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
559 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
560 0 : first_level) |
561 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
562 util_logbase2(image->info.samples) :
563 last_level) |
564 S_008F1C_TYPE(type));
565 state[4] = 0;
566 state[5] = S_008F24_BASE_ARRAY(first_layer);
567 state[6] = 0;
568 state[7] = 0;
569
570 if (device->physical_device->rad_info.chip_class >= GFX9) {
571 unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
572
573 /* Depth is the last accessible layer on Gfx9.
574 * The hw doesn't need to know the total number of layers.
575 */
576 if (type == V_008F1C_SQ_RSRC_IMG_3D)
577 state[4] |= S_008F20_DEPTH(depth - 1);
578 else
579 state[4] |= S_008F20_DEPTH(last_layer);
580
581 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
582 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
583 util_logbase2(image->info.samples) :
584 image->info.levels - 1);
585 } else {
586 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
587 state[4] |= S_008F20_DEPTH(depth - 1);
588 state[5] |= S_008F24_LAST_ARRAY(last_layer);
589 }
590 if (image->dcc_offset) {
591 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
592
593 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
594 } else {
595 /* The last dword is unused by hw. The shader uses it to clear
596 * bits in the first dword of sampler state.
597 */
598 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
599 if (first_level == last_level)
600 state[7] = C_008F30_MAX_ANISO_RATIO;
601 else
602 state[7] = 0xffffffff;
603 }
604 }
605
606 /* Initialize the sampler view for FMASK. */
607 if (radv_image_has_fmask(image)) {
608 uint32_t fmask_format, num_format;
609 uint64_t gpu_address = radv_buffer_get_va(image->bo);
610 uint64_t va;
611
612 assert(image->plane_count == 1);
613
614 va = gpu_address + image->offset + image->fmask.offset;
615
616 if (device->physical_device->rad_info.chip_class >= GFX9) {
617 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
618 switch (image->info.samples) {
619 case 2:
620 num_format = V_008F14_IMG_FMASK_8_2_2;
621 break;
622 case 4:
623 num_format = V_008F14_IMG_FMASK_8_4_4;
624 break;
625 case 8:
626 num_format = V_008F14_IMG_FMASK_32_8_8;
627 break;
628 default:
629 unreachable("invalid nr_samples");
630 }
631 } else {
632 switch (image->info.samples) {
633 case 2:
634 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
635 break;
636 case 4:
637 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
638 break;
639 case 8:
640 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
641 break;
642 default:
643 assert(0);
644 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
645 }
646 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
647 }
648
649 fmask_state[0] = va >> 8;
650 fmask_state[0] |= image->fmask.tile_swizzle;
651 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
652 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
653 S_008F14_NUM_FORMAT_GFX6(num_format);
654 fmask_state[2] = S_008F18_WIDTH(width - 1) |
655 S_008F18_HEIGHT(height - 1);
656 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
657 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
658 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
659 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
660 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
661 fmask_state[4] = 0;
662 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
663 fmask_state[6] = 0;
664 fmask_state[7] = 0;
665
666 if (device->physical_device->rad_info.chip_class >= GFX9) {
667 fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
668 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
669 S_008F20_PITCH_GFX9(image->planes[0].surface.u.gfx9.fmask.epitch);
670 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
671 S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
672 } else {
673 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
674 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
675 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
676 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
677 }
678 } else if (fmask_state)
679 memset(fmask_state, 0, 8 * 4);
680 }
681
682 static void
683 radv_query_opaque_metadata(struct radv_device *device,
684 struct radv_image *image,
685 struct radeon_bo_metadata *md)
686 {
687 static const VkComponentMapping fixedmapping;
688 uint32_t desc[8], i;
689
690 assert(image->plane_count == 1);
691
692 /* Metadata image format format version 1:
693 * [0] = 1 (metadata format identifier)
694 * [1] = (VENDOR_ID << 16) | PCI_ID
695 * [2:9] = image descriptor for the whole resource
696 * [2] is always 0, because the base address is cleared
697 * [9] is the DCC offset bits [39:8] from the beginning of
698 * the buffer
699 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
700 */
701 md->metadata[0] = 1; /* metadata image format version 1 */
702
703 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
704 md->metadata[1] = si_get_bo_metadata_word1(device);
705
706
707 si_make_texture_descriptor(device, image, false,
708 (VkImageViewType)image->type, image->vk_format,
709 &fixedmapping, 0, image->info.levels - 1, 0,
710 image->info.array_size - 1,
711 image->info.width, image->info.height,
712 image->info.depth,
713 desc, NULL);
714
715 si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0,
716 image->planes[0].surface.blk_w, false, false, desc);
717
718 /* Clear the base address and set the relative DCC offset. */
719 desc[0] = 0;
720 desc[1] &= C_008F14_BASE_ADDRESS_HI;
721 desc[7] = image->dcc_offset >> 8;
722
723 /* Dwords [2:9] contain the image descriptor. */
724 memcpy(&md->metadata[2], desc, sizeof(desc));
725
726 /* Dwords [10:..] contain the mipmap level offsets. */
727 if (device->physical_device->rad_info.chip_class <= VI) {
728 for (i = 0; i <= image->info.levels - 1; i++)
729 md->metadata[10+i] = image->planes[0].surface.u.legacy.level[i].offset >> 8;
730 md->size_metadata = (11 + image->info.levels - 1) * 4;
731 }
732 }
733
734 void
735 radv_init_metadata(struct radv_device *device,
736 struct radv_image *image,
737 struct radeon_bo_metadata *metadata)
738 {
739 struct radeon_surf *surface = &image->planes[0].surface;
740
741 memset(metadata, 0, sizeof(*metadata));
742
743 if (device->physical_device->rad_info.chip_class >= GFX9) {
744 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
745 } else {
746 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
747 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
748 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
749 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
750 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
751 metadata->u.legacy.bankw = surface->u.legacy.bankw;
752 metadata->u.legacy.bankh = surface->u.legacy.bankh;
753 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
754 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
755 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
756 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
757 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
758 }
759 radv_query_opaque_metadata(device, image, metadata);
760 }
761
762 /* The number of samples can be specified independently of the texture. */
763 static void
764 radv_image_get_fmask_info(struct radv_device *device,
765 struct radv_image *image,
766 unsigned nr_samples,
767 struct radv_fmask_info *out)
768 {
769 if (device->physical_device->rad_info.chip_class >= GFX9) {
770 out->alignment = image->planes[0].surface.fmask_alignment;
771 out->size = image->planes[0].surface.fmask_size;
772 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
773 return;
774 }
775
776 out->slice_tile_max = image->planes[0].surface.u.legacy.fmask.slice_tile_max;
777 out->tile_mode_index = image->planes[0].surface.u.legacy.fmask.tiling_index;
778 out->pitch_in_pixels = image->planes[0].surface.u.legacy.fmask.pitch_in_pixels;
779 out->bank_height = image->planes[0].surface.u.legacy.fmask.bankh;
780 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
781 out->alignment = image->planes[0].surface.fmask_alignment;
782 out->size = image->planes[0].surface.fmask_size;
783
784 assert(!out->tile_swizzle || !image->shareable);
785 }
786
787 static void
788 radv_image_alloc_fmask(struct radv_device *device,
789 struct radv_image *image)
790 {
791 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
792
793 image->fmask.offset = align64(image->size, image->fmask.alignment);
794 image->size = image->fmask.offset + image->fmask.size;
795 image->alignment = MAX2(image->alignment, image->fmask.alignment);
796 }
797
798 static void
799 radv_image_get_cmask_info(struct radv_device *device,
800 struct radv_image *image,
801 struct radv_cmask_info *out)
802 {
803 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
804 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
805 unsigned cl_width, cl_height;
806
807 assert(image->plane_count == 1);
808
809 if (device->physical_device->rad_info.chip_class >= GFX9) {
810 out->alignment = image->planes[0].surface.cmask_alignment;
811 out->size = image->planes[0].surface.cmask_size;
812 return;
813 }
814
815 switch (num_pipes) {
816 case 2:
817 cl_width = 32;
818 cl_height = 16;
819 break;
820 case 4:
821 cl_width = 32;
822 cl_height = 32;
823 break;
824 case 8:
825 cl_width = 64;
826 cl_height = 32;
827 break;
828 case 16: /* Hawaii */
829 cl_width = 64;
830 cl_height = 64;
831 break;
832 default:
833 assert(0);
834 return;
835 }
836
837 unsigned base_align = num_pipes * pipe_interleave_bytes;
838
839 unsigned width = align(image->planes[0].surface.u.legacy.level[0].nblk_x, cl_width*8);
840 unsigned height = align(image->planes[0].surface.u.legacy.level[0].nblk_y, cl_height*8);
841 unsigned slice_elements = (width * height) / (8*8);
842
843 /* Each element of CMASK is a nibble. */
844 unsigned slice_bytes = slice_elements / 2;
845
846 out->slice_tile_max = (width * height) / (128*128);
847 if (out->slice_tile_max)
848 out->slice_tile_max -= 1;
849
850 out->alignment = MAX2(256, base_align);
851 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
852 align(slice_bytes, base_align);
853 }
854
855 static void
856 radv_image_alloc_cmask(struct radv_device *device,
857 struct radv_image *image)
858 {
859 uint32_t clear_value_size = 0;
860 radv_image_get_cmask_info(device, image, &image->cmask);
861
862 image->cmask.offset = align64(image->size, image->cmask.alignment);
863 /* + 8 for storing the clear values */
864 if (!image->clear_value_offset) {
865 image->clear_value_offset = image->cmask.offset + image->cmask.size;
866 clear_value_size = 8;
867 }
868 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
869 image->alignment = MAX2(image->alignment, image->cmask.alignment);
870 }
871
872 static void
873 radv_image_alloc_dcc(struct radv_image *image)
874 {
875 assert(image->plane_count == 1);
876
877 image->dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
878 /* + 16 for storing the clear values + dcc pred */
879 image->clear_value_offset = image->dcc_offset + image->planes[0].surface.dcc_size;
880 image->fce_pred_offset = image->clear_value_offset + 8;
881 image->dcc_pred_offset = image->clear_value_offset + 16;
882 image->size = image->dcc_offset + image->planes[0].surface.dcc_size + 24;
883 image->alignment = MAX2(image->alignment, image->planes[0].surface.dcc_alignment);
884 }
885
886 static void
887 radv_image_alloc_htile(struct radv_image *image)
888 {
889 image->htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
890
891 /* + 8 for storing the clear values */
892 image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
893 image->size = image->clear_value_offset + 8;
894 if (radv_image_is_tc_compat_htile(image)) {
895 /* Metadata for the TC-compatible HTILE hardware bug which
896 * have to be fixed by updating ZRANGE_PRECISION when doing
897 * fast depth clears to 0.0f.
898 */
899 image->tc_compat_zrange_offset = image->clear_value_offset + 8;
900 image->size = image->clear_value_offset + 16;
901 }
902 image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
903 }
904
905 static inline bool
906 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
907 {
908 if (image->info.samples <= 1 &&
909 image->info.width * image->info.height <= 512 * 512) {
910 /* Do not enable CMASK or DCC for small surfaces where the cost
911 * of the eliminate pass can be higher than the benefit of fast
912 * clear. RadeonSI does this, but the image threshold is
913 * different.
914 */
915 return false;
916 }
917
918 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
919 (image->exclusive || image->queue_family_mask == 1);
920 }
921
922 static inline bool
923 radv_image_can_enable_dcc(struct radv_image *image)
924 {
925 return radv_image_can_enable_dcc_or_cmask(image) &&
926 radv_image_has_dcc(image);
927 }
928
929 static inline bool
930 radv_image_can_enable_cmask(struct radv_image *image)
931 {
932 if (image->planes[0].surface.bpe > 8 && image->info.samples == 1) {
933 /* Do not enable CMASK for non-MSAA images (fast color clear)
934 * because 128 bit formats are not supported, but FMASK might
935 * still be used.
936 */
937 return false;
938 }
939
940 return radv_image_can_enable_dcc_or_cmask(image) &&
941 image->info.levels == 1 &&
942 image->info.depth == 1 &&
943 !image->planes[0].surface.is_linear;
944 }
945
946 static inline bool
947 radv_image_can_enable_fmask(struct radv_image *image)
948 {
949 return image->info.samples > 1 && vk_format_is_color(image->vk_format);
950 }
951
952 static inline bool
953 radv_image_can_enable_htile(struct radv_image *image)
954 {
955 return radv_image_has_htile(image) &&
956 image->info.levels == 1 &&
957 image->info.width * image->info.height >= 8 * 8;
958 }
959
960 static void radv_image_disable_dcc(struct radv_image *image)
961 {
962 for (unsigned i = 0; i < image->plane_count; ++i)
963 image->planes[i].surface.dcc_size = 0;
964 }
965
966 static void radv_image_disable_htile(struct radv_image *image)
967 {
968 for (unsigned i = 0; i < image->plane_count; ++i)
969 image->planes[i].surface.htile_size = 0;
970 }
971
972 VkResult
973 radv_image_create(VkDevice _device,
974 const struct radv_image_create_info *create_info,
975 const VkAllocationCallbacks* alloc,
976 VkImage *pImage)
977 {
978 RADV_FROM_HANDLE(radv_device, device, _device);
979 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
980 struct radv_image *image = NULL;
981 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
982
983 const unsigned plane_count = vk_format_get_plane_count(pCreateInfo->format);
984 const size_t image_struct_size = sizeof(*image) + sizeof(struct radv_image_plane) * plane_count;
985
986 radv_assert(pCreateInfo->mipLevels > 0);
987 radv_assert(pCreateInfo->arrayLayers > 0);
988 radv_assert(pCreateInfo->samples > 0);
989 radv_assert(pCreateInfo->extent.width > 0);
990 radv_assert(pCreateInfo->extent.height > 0);
991 radv_assert(pCreateInfo->extent.depth > 0);
992
993 image = vk_zalloc2(&device->alloc, alloc, image_struct_size, 8,
994 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
995 if (!image)
996 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
997
998 image->type = pCreateInfo->imageType;
999 image->info.width = pCreateInfo->extent.width;
1000 image->info.height = pCreateInfo->extent.height;
1001 image->info.depth = pCreateInfo->extent.depth;
1002 image->info.samples = pCreateInfo->samples;
1003 image->info.storage_samples = pCreateInfo->samples;
1004 image->info.array_size = pCreateInfo->arrayLayers;
1005 image->info.levels = pCreateInfo->mipLevels;
1006 image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
1007
1008 image->vk_format = pCreateInfo->format;
1009 image->tiling = pCreateInfo->tiling;
1010 image->usage = pCreateInfo->usage;
1011 image->flags = pCreateInfo->flags;
1012
1013 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
1014 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
1015 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
1016 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL)
1017 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1018 else
1019 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
1020 }
1021
1022 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
1023 EXTERNAL_MEMORY_IMAGE_CREATE_INFO) != NULL;
1024 if (!vk_format_is_depth_or_stencil(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
1025 image->info.surf_index = &device->image_mrt_offset_counter;
1026 }
1027
1028 image->plane_count = plane_count;
1029 image->size = 0;
1030 image->alignment = 1;
1031 for (unsigned plane = 0; plane < plane_count; ++plane) {
1032 struct ac_surf_info info = image->info;
1033 radv_init_surface(device, image, &image->planes[plane].surface, plane, create_info);
1034
1035 if (plane) {
1036 const struct vk_format_description *desc = vk_format_description(pCreateInfo->format);
1037 assert(info.width % desc->width_divisor == 0);
1038 assert(info.height % desc->height_divisor == 0);
1039
1040 info.width /= desc->width_divisor;
1041 info.height /= desc->height_divisor;
1042 }
1043
1044 device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
1045
1046 image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
1047 image->size = image->planes[plane].offset + image->planes[plane].surface.surf_size;
1048 image->alignment = image->planes[plane].surface.surf_alignment;
1049
1050 image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
1051 }
1052
1053 if (!create_info->no_metadata_planes) {
1054 /* Try to enable DCC first. */
1055 if (radv_image_can_enable_dcc(image)) {
1056 radv_image_alloc_dcc(image);
1057 if (image->info.samples > 1) {
1058 /* CMASK should be enabled because DCC fast
1059 * clear with MSAA needs it.
1060 */
1061 assert(radv_image_can_enable_cmask(image));
1062 radv_image_alloc_cmask(device, image);
1063 }
1064 } else {
1065 /* When DCC cannot be enabled, try CMASK. */
1066 radv_image_disable_dcc(image);
1067 if (radv_image_can_enable_cmask(image)) {
1068 radv_image_alloc_cmask(device, image);
1069 }
1070 }
1071
1072 /* Try to enable FMASK for multisampled images. */
1073 if (radv_image_can_enable_fmask(image)) {
1074 radv_image_alloc_fmask(device, image);
1075 } else {
1076 /* Otherwise, try to enable HTILE for depth surfaces. */
1077 if (radv_image_can_enable_htile(image) &&
1078 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
1079 image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1080 radv_image_alloc_htile(image);
1081 } else {
1082 radv_image_disable_htile(image);
1083 }
1084 }
1085 } else {
1086 radv_image_disable_dcc(image);
1087 radv_image_disable_htile(image);
1088 }
1089
1090 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
1091 image->alignment = MAX2(image->alignment, 4096);
1092 image->size = align64(image->size, image->alignment);
1093 image->offset = 0;
1094
1095 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
1096 0, RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL);
1097 if (!image->bo) {
1098 vk_free2(&device->alloc, alloc, image);
1099 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
1100 }
1101 }
1102
1103 *pImage = radv_image_to_handle(image);
1104
1105 return VK_SUCCESS;
1106 }
1107
1108 static void
1109 radv_image_view_make_descriptor(struct radv_image_view *iview,
1110 struct radv_device *device,
1111 const VkComponentMapping *components,
1112 bool is_storage_image, unsigned plane_id)
1113 {
1114 struct radv_image *image = iview->image;
1115 struct radv_image_plane *plane = &image->planes[plane_id];
1116 const struct vk_format_description *format_desc = vk_format_description(image->vk_format);
1117 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
1118 uint32_t blk_w;
1119 uint32_t *descriptor;
1120 uint32_t hw_level = 0;
1121
1122 if (is_storage_image) {
1123 descriptor = iview->storage_descriptor;
1124 } else {
1125 descriptor = iview->descriptor;
1126 }
1127
1128 assert(plane->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
1129 blk_w = plane->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
1130
1131 if (device->physical_device->rad_info.chip_class >= GFX9)
1132 hw_level = iview->base_mip;
1133 si_make_texture_descriptor(device, image, is_storage_image,
1134 iview->type,
1135 iview->vk_format,
1136 components,
1137 hw_level, hw_level + iview->level_count - 1,
1138 iview->base_layer,
1139 iview->base_layer + iview->layer_count - 1,
1140 iview->extent.width / (plane_id ? format_desc->width_divisor : 1),
1141 iview->extent.height / (plane_id ? format_desc->height_divisor : 1),
1142 iview->extent.depth,
1143 descriptor,
1144 descriptor + 8);
1145
1146 const struct legacy_surf_level *base_level_info = NULL;
1147 if (device->physical_device->rad_info.chip_class <= GFX9) {
1148 if (is_stencil)
1149 base_level_info = &plane->surface.u.legacy.stencil_level[iview->base_mip];
1150 else
1151 base_level_info = &plane->surface.u.legacy.level[iview->base_mip];
1152 }
1153 si_set_mutable_tex_desc_fields(device, image,
1154 base_level_info,
1155 iview->base_mip,
1156 iview->base_mip,
1157 blk_w, is_stencil, is_storage_image, descriptor);
1158 }
1159
1160 static unsigned
1161 radv_plane_from_aspect(VkImageAspectFlags mask)
1162 {
1163 switch(mask) {
1164 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1165 return 1;
1166 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1167 return 2;
1168 default:
1169 return 0;
1170 }
1171 }
1172
1173 VkFormat
1174 radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask)
1175 {
1176 switch(mask) {
1177 case VK_IMAGE_ASPECT_PLANE_0_BIT:
1178 return image->planes[0].format;
1179 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1180 return image->planes[1].format;
1181 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1182 return image->planes[2].format;
1183 case VK_IMAGE_ASPECT_STENCIL_BIT:
1184 return vk_format_stencil_only(image->vk_format);
1185 case VK_IMAGE_ASPECT_DEPTH_BIT:
1186 return vk_format_depth_only(image->vk_format);
1187 default:
1188 return image->vk_format;
1189 }
1190 }
1191
1192 void
1193 radv_image_view_init(struct radv_image_view *iview,
1194 struct radv_device *device,
1195 const VkImageViewCreateInfo* pCreateInfo)
1196 {
1197 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1198 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1199
1200 switch (image->type) {
1201 case VK_IMAGE_TYPE_1D:
1202 case VK_IMAGE_TYPE_2D:
1203 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1204 break;
1205 case VK_IMAGE_TYPE_3D:
1206 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1207 <= radv_minify(image->info.depth, range->baseMipLevel));
1208 break;
1209 default:
1210 unreachable("bad VkImageType");
1211 }
1212 iview->image = image;
1213 iview->bo = image->bo;
1214 iview->type = pCreateInfo->viewType;
1215 iview->vk_format = pCreateInfo->format;
1216 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1217 iview->plane_id = radv_plane_from_aspect(pCreateInfo->subresourceRange.aspectMask);
1218
1219 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1220 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1221 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1222 iview->vk_format = vk_format_depth_only(iview->vk_format);
1223 }
1224
1225 if (device->physical_device->rad_info.chip_class >= GFX9) {
1226 iview->extent = (VkExtent3D) {
1227 .width = image->info.width,
1228 .height = image->info.height,
1229 .depth = image->info.depth,
1230 };
1231 } else {
1232 iview->extent = (VkExtent3D) {
1233 .width = radv_minify(image->info.width , range->baseMipLevel),
1234 .height = radv_minify(image->info.height, range->baseMipLevel),
1235 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1236 };
1237 }
1238
1239 if (iview->vk_format != image->planes[iview->plane_id].format) {
1240 unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
1241 unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
1242 unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
1243 unsigned img_bh = vk_format_get_blockheight(image->vk_format);
1244
1245 iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
1246 iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
1247
1248 /* Comment ported from amdvlk -
1249 * If we have the following image:
1250 * Uncompressed pixels Compressed block sizes (4x4)
1251 * mip0: 22 x 22 6 x 6
1252 * mip1: 11 x 11 3 x 3
1253 * mip2: 5 x 5 2 x 2
1254 * mip3: 2 x 2 1 x 1
1255 * mip4: 1 x 1 1 x 1
1256 *
1257 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1258 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1259 * divide-by-two integer math):
1260 * mip0: 6x6
1261 * mip1: 3x3
1262 * mip2: 1x1
1263 * mip3: 1x1
1264 *
1265 * This means that mip2 will be missing texels.
1266 *
1267 * Fix this by calculating the base mip's width and height, then convert that, and round it
1268 * back up to get the level 0 size.
1269 * Clamp the converted size between the original values, and next power of two, which
1270 * means we don't oversize the image.
1271 */
1272 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1273 vk_format_is_compressed(image->vk_format) &&
1274 !vk_format_is_compressed(iview->vk_format)) {
1275 unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
1276 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
1277
1278 lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
1279 lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
1280
1281 lvl_width <<= range->baseMipLevel;
1282 lvl_height <<= range->baseMipLevel;
1283
1284 iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->planes[0].surface.u.gfx9.surf_pitch);
1285 iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->planes[0].surface.u.gfx9.surf_height);
1286 }
1287 }
1288
1289 iview->base_layer = range->baseArrayLayer;
1290 iview->layer_count = radv_get_layerCount(image, range);
1291 iview->base_mip = range->baseMipLevel;
1292 iview->level_count = radv_get_levelCount(image, range);
1293
1294 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, false, iview->plane_id);
1295 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, true, iview->plane_id);
1296 }
1297
1298 bool radv_layout_has_htile(const struct radv_image *image,
1299 VkImageLayout layout,
1300 unsigned queue_mask)
1301 {
1302 if (radv_image_is_tc_compat_htile(image))
1303 return layout != VK_IMAGE_LAYOUT_GENERAL;
1304
1305 return radv_image_has_htile(image) &&
1306 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1307 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1308 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1309 }
1310
1311 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1312 VkImageLayout layout,
1313 unsigned queue_mask)
1314 {
1315 if (radv_image_is_tc_compat_htile(image))
1316 return layout != VK_IMAGE_LAYOUT_GENERAL;
1317
1318 return radv_image_has_htile(image) &&
1319 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1320 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1321 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1322 }
1323
1324 bool radv_layout_can_fast_clear(const struct radv_image *image,
1325 VkImageLayout layout,
1326 unsigned queue_mask)
1327 {
1328 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
1329 }
1330
1331 bool radv_layout_dcc_compressed(const struct radv_image *image,
1332 VkImageLayout layout,
1333 unsigned queue_mask)
1334 {
1335 /* Don't compress compute transfer dst, as image stores are not supported. */
1336 if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1337 (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
1338 return false;
1339
1340 return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
1341 }
1342
1343
1344 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1345 {
1346 if (!image->exclusive)
1347 return image->queue_family_mask;
1348 if (family == VK_QUEUE_FAMILY_EXTERNAL)
1349 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1350 if (family == VK_QUEUE_FAMILY_IGNORED)
1351 return 1u << queue_family;
1352 return 1u << family;
1353 }
1354
1355 VkResult
1356 radv_CreateImage(VkDevice device,
1357 const VkImageCreateInfo *pCreateInfo,
1358 const VkAllocationCallbacks *pAllocator,
1359 VkImage *pImage)
1360 {
1361 #ifdef ANDROID
1362 const VkNativeBufferANDROID *gralloc_info =
1363 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
1364
1365 if (gralloc_info)
1366 return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
1367 pAllocator, pImage);
1368 #endif
1369
1370 const struct wsi_image_create_info *wsi_info =
1371 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
1372 bool scanout = wsi_info && wsi_info->scanout;
1373
1374 return radv_image_create(device,
1375 &(struct radv_image_create_info) {
1376 .vk_info = pCreateInfo,
1377 .scanout = scanout,
1378 },
1379 pAllocator,
1380 pImage);
1381 }
1382
1383 void
1384 radv_DestroyImage(VkDevice _device, VkImage _image,
1385 const VkAllocationCallbacks *pAllocator)
1386 {
1387 RADV_FROM_HANDLE(radv_device, device, _device);
1388 RADV_FROM_HANDLE(radv_image, image, _image);
1389
1390 if (!image)
1391 return;
1392
1393 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1394 device->ws->buffer_destroy(image->bo);
1395
1396 if (image->owned_memory != VK_NULL_HANDLE)
1397 radv_FreeMemory(_device, image->owned_memory, pAllocator);
1398
1399 vk_free2(&device->alloc, pAllocator, image);
1400 }
1401
1402 void radv_GetImageSubresourceLayout(
1403 VkDevice _device,
1404 VkImage _image,
1405 const VkImageSubresource* pSubresource,
1406 VkSubresourceLayout* pLayout)
1407 {
1408 RADV_FROM_HANDLE(radv_image, image, _image);
1409 RADV_FROM_HANDLE(radv_device, device, _device);
1410 int level = pSubresource->mipLevel;
1411 int layer = pSubresource->arrayLayer;
1412
1413 unsigned plane_id = radv_plane_from_aspect(pSubresource->aspectMask);
1414
1415 struct radv_image_plane *plane = &image->planes[plane_id];
1416 struct radeon_surf *surface = &plane->surface;
1417
1418 if (device->physical_device->rad_info.chip_class >= GFX9) {
1419 pLayout->offset = plane->offset + surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1420 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1421 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1422 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1423 pLayout->size = surface->u.gfx9.surf_slice_size;
1424 if (image->type == VK_IMAGE_TYPE_3D)
1425 pLayout->size *= u_minify(image->info.depth, level);
1426 } else {
1427 pLayout->offset = plane->offset + surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
1428 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1429 pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1430 pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1431 pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1432 if (image->type == VK_IMAGE_TYPE_3D)
1433 pLayout->size *= u_minify(image->info.depth, level);
1434 }
1435 }
1436
1437
1438 VkResult
1439 radv_CreateImageView(VkDevice _device,
1440 const VkImageViewCreateInfo *pCreateInfo,
1441 const VkAllocationCallbacks *pAllocator,
1442 VkImageView *pView)
1443 {
1444 RADV_FROM_HANDLE(radv_device, device, _device);
1445 struct radv_image_view *view;
1446
1447 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1448 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1449 if (view == NULL)
1450 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1451
1452 radv_image_view_init(view, device, pCreateInfo);
1453
1454 *pView = radv_image_view_to_handle(view);
1455
1456 return VK_SUCCESS;
1457 }
1458
1459 void
1460 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1461 const VkAllocationCallbacks *pAllocator)
1462 {
1463 RADV_FROM_HANDLE(radv_device, device, _device);
1464 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1465
1466 if (!iview)
1467 return;
1468 vk_free2(&device->alloc, pAllocator, iview);
1469 }
1470
1471 void radv_buffer_view_init(struct radv_buffer_view *view,
1472 struct radv_device *device,
1473 const VkBufferViewCreateInfo* pCreateInfo)
1474 {
1475 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1476
1477 view->bo = buffer->bo;
1478 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1479 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1480 view->vk_format = pCreateInfo->format;
1481
1482 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1483 pCreateInfo->offset, view->range, view->state);
1484 }
1485
1486 VkResult
1487 radv_CreateBufferView(VkDevice _device,
1488 const VkBufferViewCreateInfo *pCreateInfo,
1489 const VkAllocationCallbacks *pAllocator,
1490 VkBufferView *pView)
1491 {
1492 RADV_FROM_HANDLE(radv_device, device, _device);
1493 struct radv_buffer_view *view;
1494
1495 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1496 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1497 if (!view)
1498 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1499
1500 radv_buffer_view_init(view, device, pCreateInfo);
1501
1502 *pView = radv_buffer_view_to_handle(view);
1503
1504 return VK_SUCCESS;
1505 }
1506
1507 void
1508 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1509 const VkAllocationCallbacks *pAllocator)
1510 {
1511 RADV_FROM_HANDLE(radv_device, device, _device);
1512 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1513
1514 if (!view)
1515 return;
1516
1517 vk_free2(&device->alloc, pAllocator, view);
1518 }